From c3c6fd4176b5433ea21a1b4da45677dc71a8f7d6 Mon Sep 17 00:00:00 2001 From: Eric Lee Date: Wed, 24 Jan 2018 15:00:21 +0800 Subject: [PATCH] Initial Release of v2017.01 U-Boot for SMARC-T437X --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/am437x-smarct437x.dts | 987 +++++++++++++++++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 6 + arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 1 + arch/arm/mach-omap2/am33xx/Kconfig | 11 +- arch/arm/mach-omap2/am33xx/board.c | 2 +- arch/arm/mach-omap2/am33xx/clock_am43xx.c | 50 +- arch/arm/mach-omap2/config.mk | 1 + board/embedian/common/Kconfig | 12 +- board/embedian/smarct437x/Kconfig | 17 + board/embedian/smarct437x/MAINTAINERS | 13 + board/embedian/smarct437x/Makefile | 13 + board/embedian/smarct437x/board.c | 1157 ++++++++++++++++++++ board/embedian/smarct437x/board.h | 76 ++ board/embedian/smarct437x/mux.c | 373 +++++++ common/Kconfig | 2 +- configs/smarct437x_evm_spi_uart0_defconfig | 65 ++ configs/smarct437x_evm_spi_uart1_defconfig | 65 ++ configs/smarct437x_evm_spi_uart2_defconfig | 65 ++ configs/smarct437x_evm_spi_uart3_defconfig | 65 ++ configs/smarct437x_evm_uart0_defconfig | 65 ++ configs/smarct437x_evm_uart1_defconfig | 65 ++ configs/smarct437x_evm_uart2_defconfig | 65 ++ configs/smarct437x_evm_uart3_defconfig | 65 ++ drivers/mtd/spi/spi_flash_ids.c | 1 + drivers/power/power_i2c.c | 1 + include/configs/embedian_armv7_common.h | 30 + include/configs/embedian_armv7_omap.h | 2 +- include/configs/smarct437x_evm.h | 473 ++++++++ include/dt-bindings/pinctrl/am43xx.h | 2 + 31 files changed, 3747 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/am437x-smarct437x.dts create mode 100644 board/embedian/smarct437x/Kconfig create mode 100644 board/embedian/smarct437x/MAINTAINERS create mode 100644 board/embedian/smarct437x/Makefile create mode 100644 board/embedian/smarct437x/board.c create mode 100644 board/embedian/smarct437x/board.h create mode 100644 board/embedian/smarct437x/mux.c create mode 100644 configs/smarct437x_evm_spi_uart0_defconfig create mode 100644 configs/smarct437x_evm_spi_uart1_defconfig create mode 100644 configs/smarct437x_evm_spi_uart2_defconfig create mode 100644 configs/smarct437x_evm_spi_uart3_defconfig create mode 100644 configs/smarct437x_evm_uart0_defconfig create mode 100644 configs/smarct437x_evm_uart1_defconfig create mode 100644 configs/smarct437x_evm_uart2_defconfig create mode 100644 configs/smarct437x_evm_uart3_defconfig create mode 100644 include/configs/smarct437x_evm.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9190ad5..503dd93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1055,6 +1055,7 @@ source "board/tcl/sl50/Kconfig" source "board/ti/am335x/Kconfig" source "board/embedian/smarct335x/Kconfig" source "board/ti/am43xx/Kconfig" +source "board/embedian/smarct437x/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4cfb9a2..8b0c4f4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -117,9 +117,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ am335x-draco.dtb \ am335x-evm.dtb \ - am335x-smarct335x-uart0.dtb \ - am335x-smarct335x-uart2.dtb \ - am335x-smarct335x-uart3.dtb \ + am335x-smarct335x.dtb \ am335x-evmsk.dtb \ am335x-bonegreen.dtb \ am335x-icev2.dtb \ @@ -127,6 +125,7 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ am335x-rut.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ + am437x-smarct437x.dtb \ am437x-idk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb diff --git a/arch/arm/dts/am437x-smarct437x.dts b/arch/arm/dts/am437x-smarct437x.dts new file mode 100644 index 0000000..860abf5 --- /dev/null +++ b/arch/arm/dts/am437x-smarct437x.dts @@ -0,0 +1,987 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x SK EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include +#include +#include +#include + +/ { + model = "TI AM437x SMARCT437X"; + compatible = "ti,am437x-smarct437x","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + tick-timer = &timer2; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; /* Backlight Enable Pin*/ + pwms = <&ehrpwm0 1 250000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 128 212 255>; + default-brightness-level = <7>; /* 7 is the brightest */ + }; + + sound: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "SMARCT437X SOUND CARD"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + /* For TI TLV320AIC3106 Audio Codec */ + /*sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>;*/ + + /* For Freescale SGTL5000 Audio Codec */ + sound_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + system-clock-frequency = <24000000>; + }; + }; + + audio_mstrclk: mclk_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + lcd0: display { + compatible = "primeview,pm070wl4", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <32000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <42>; + hback-porch = <84>; + hsync-len = <128>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; +}; + +&am43xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout1_pin &clkout2_pin &gpio_pins_default &wdt_time_out_pins_default &debugss_pins>; + + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1_pins { + pinctrl-single,pins = < + 0x110 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_rxerr.i2c1_scl */ + 0x10c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* mii1_crs.i2c1_sda */ + >; + }; + + i2c2_pins: i2c2_pins { + pinctrl-single,pins = < + 0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ + 0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; + + sdmmc_pins: pinmux_sdmmc_pins { + pinctrl-single,pins = < + 0x8c (PIN_INPUT | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + 0x88 (PIN_INPUT | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + 0x30 (PIN_INPUT | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + 0x34 (PIN_INPUT | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + 0x3c (PIN_INPUT | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + 0x20 (PIN_INPUT | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ + 0x24 (PIN_INPUT | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ + 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ + 0x2c (PIN_INPUT | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ + >; + }; + + ehrpwm0b_pins: backlight_pins { + pinctrl-single,pins = < + 0x1d8 (PIN_OUTPUT | MUX_MODE6) /* cam1_vd.ehrpwm0B */ + >; + }; + + clkout1_pin: pinmux_clkout1_pin { + pinctrl-single,pins = < + 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x274 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR1/CLKOUT2 */ + >; + }; + + dcan0_default: dcan0_default_pins { + pinctrl-single,pins = < + 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.dcan0_rx */ + 0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_ctsn.dcan0_tx */ + >; + }; + + dcan1_default: dcan1_default_pins { + pinctrl-single,pins = < + 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.dcan1_rx */ + 0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart1_rxd.dcan1_tx */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x168 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ + 0x16c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ + 0x170 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart0_pins_sleep: pinmux_uart0_pins_sleep { + pinctrl-single,pins = < + 0x168 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x170 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x228 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_rxd.uart3_rxd */ + 0x22c (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart3_txd.uart3_txd */ + >; + }; + + uart3_pins_sleep: pinmux_uart3_pins_sleep { + pinctrl-single,pins = < + 0x228 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x22c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data6.uart2_ctsn */ + 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE2) /* cam1_data7_rtsn.uart2_rtsn */ + 0x1f8 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data4_uart2rxd */ + 0x1fc (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE2) /* cam1_data5.uart2_txd */ + >; + }; + + uart2_pins_sleep: pinmux_uart2_pins_sleep { + pinctrl-single,pins = < + 0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x070 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ + 0x074 (PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ + >; + }; + + uart4_pins_sleep: pinmux_uart4_pins_sleep { + pinctrl-single,pins = < + 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x174 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ + gpio_pins_default: pinmux_gpio_pin { + pinctrl-single,pins = < + 0x26c (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_cs0.gpio0_23 */ + 0x264 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d0.gpio0_20 */ + 0x268 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_d1.gpio0_21 */ + 0x260 (PIN_INPUT_PULLDOWN | MUX_MODE9) /* spi2_sclk.gpio0_22 */ + 0x21c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data5.gpio4_27 */ + 0x224 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam0_data7.gpio4_29 */ + 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ + 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_16 */ + 0x210 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data2.gpio4_24 */ + 0x214 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data3.gpio4_25 */ + 0x218 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data4.gpio4_26 */ + 0x220 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam0_data6.gpio4_28 */ + >; + }; + + wdt_time_out_pins_default: pinmux_wdt_time_out_pin { + pinctrl-single,pins = < + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* uart3_rtsn.ehrpwm5B */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + + /* Slave 2 */ + 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ + 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + 0x1b0 (PIN_OUTPUT | MUX_MODE2) /* cam0_hd.dss_data23 */ + 0x1b4 (PIN_OUTPUT | MUX_MODE2) /* cam0_vd.dss_data22 */ + 0x1b8 (PIN_OUTPUT | MUX_MODE2) /* cam0_field.dss_data21 */ + 0x1bc (PIN_OUTPUT | MUX_MODE2) /* cam0_wen.dss_data20 */ + 0x1c0 (PIN_OUTPUT | MUX_MODE2) /* cam0_pclk.dss_data19 */ + 0x1c4 (PIN_OUTPUT | MUX_MODE2) /* cam0_data8.dss_data18 */ + 0x1c8 (PIN_OUTPUT | MUX_MODE2) /* cam0_data9.dss_data17 */ + 0x1cc (PIN_OUTPUT | MUX_MODE2) /* cam1_data9.dss_data16 */ + 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ + 0x0a4 (PIN_OUTPUT | MUX_MODE0) + 0x0a8 (PIN_OUTPUT | MUX_MODE0) + 0x0ac (PIN_OUTPUT | MUX_MODE0) + 0x0b0 (PIN_OUTPUT | MUX_MODE0) + 0x0b4 (PIN_OUTPUT | MUX_MODE0) + 0x0b8 (PIN_OUTPUT | MUX_MODE0) + 0x0bc (PIN_OUTPUT | MUX_MODE0) + 0x0c0 (PIN_OUTPUT | MUX_MODE0) + 0x0c4 (PIN_OUTPUT | MUX_MODE0) + 0x0c8 (PIN_OUTPUT | MUX_MODE0) + 0x0cc (PIN_OUTPUT | MUX_MODE0) + 0x0d0 (PIN_OUTPUT | MUX_MODE0) + 0x0d4 (PIN_OUTPUT | MUX_MODE0) + 0x0d8 (PIN_OUTPUT | MUX_MODE0) + 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ + 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ + 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ + 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ + 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + /* SPI_NOR Pins */ + spi0_pins: spi0_pins { + pinctrl-single,pins = < + 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ + 0x154 (PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ + >; + }; + + /* SPI0 Pins */ + spi2_pins: spi2_pins { + pinctrl-single,pins = < + 0x1d4 (PIN_OUTPUT | MUX_MODE4) /* cam1_hd.spi2_cs0 */ + 0x1e0 (PIN_OUTPUT | MUX_MODE4) /* cam1_field.spi2_cs0 */ + 0x1dc (PIN_INPUT | MUX_MODE4) /* cam1_pclk.spi2_sclk */ + 0x1d0 (PIN_INPUT | MUX_MODE4) /* cam1_data8.spi2_d0 */ + 0x1e4 (PIN_OUTPUT | MUX_MODE4) /* cam1_wen.spi2_d1 */ + >; + }; + + /* SPI1 Pins */ + spi4_pins: spi4_pins { + pinctrl-single,pins = < + 0x25c (PIN_OUTPUT | MUX_MODE0) /* spi4_cs0.spi4_cs0 */ + 0x230 (PIN_OUTPUT | MUX_MODE2) /* uart3_cstn.spi4_cs1 */ + 0x250 (PIN_INPUT | MUX_MODE0) /* spi4_sclk.spi4_sclk */ + 0x254 (PIN_INPUT | MUX_MODE0) /* spi4_d0.spi4_d0 */ + 0x258 (PIN_OUTPUT | MUX_MODE0) /* spi4_d1.spi4_d1 */ + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ + 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ + >; + }; + + mcasp1_sleep_pins: mcasp1_sleep_pins { + pinctrl-single,pins = < + 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + lcd_pins: lcd_pins { + pinctrl-single,pins = < + 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */ + >; + }; + + debugss_pins: pinmux_debugss_pins { + pinctrl-single,pins = < + 0x290 (PIN_INPUT_PULLDOWN) + 0x294 (PIN_INPUT_PULLDOWN) + 0x298 (PIN_INPUT_PULLDOWN) + 0x29C (PIN_INPUT_PULLDOWN) + 0x2A0 (PIN_INPUT_PULLDOWN) + 0x2A4 (PIN_INPUT_PULLDOWN) + 0x2A8 (PIN_INPUT_PULLDOWN) + >; + }; + + usb1_pins: usb1_pins { + pinctrl-single,pins = < + 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + /* USB0 Over Current */ + 0x108 (PIN_INPUT | MUX_MODE9) /* mii1_col.gpio0_0 */ + >; + }; + + usb2_pins: usb2_pins { + pinctrl-single,pins = < + 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + /* USB1 Over Current */ + 0x078 (PIN_INPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + + tps@24 { + compatible = "ti,tps65218"; + reg = <0x24>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + /* VDD_CORE limits min of OPP50 and max of OPP100 */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-name = "v1_8d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + power-button { + compatible = "ti,tps65218-pwrbutton"; + status = "okay"; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + + at24@50 { + compatible = "at24,24c256"; + reg = <0x50>; + }; + + at24@57 { + compatible = "at24,24c256"; + reg = <0x57>; + }; + + /* For TI TLV320AIC3106 Audio Codec */ + /*tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + AVDD-supply = <&dcdc4>; + IOVDD-supply = <&dcdc6>; + DRVDD-supply = <&dcdc4>; + DVDD-supply = <&ldo1>; + };*/ + + /* For Freescale SGTL5000 Audio Codec */ + sgtl5000: sgtl5000@0a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&audio_mstrclk>; + VDDA-supply = <&dcdc4>; + VDDIO-supply = <&dcdc6>; + VDDD-supply = <&ldo1>; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <100000>; + + /* CH7055A Parallel LCD to VGA D-SUB 15 way */ + eeprom@76 { + compatible = "at,24c256"; + reg = <0x76>; + }; +}; + + +&epwmss0 { + status = "okay"; + + ehrpwm0: ehrpwm@48300200 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm0b_pins>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&dcdc4>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + vmmc-supply = <&vmmcwl_fixed>; + status = "okay"; + ti,non-removable; +}; + +/*If carrier board eMMC (or 2nd SD slot) is present and used, un-comment out the following nodes. SD card will be emulated /dev/mmcblk2 instead of /dev/mmcblk1*/ + +&mmc3 { + status = "okay"; + dmas = <&edma 30 + &edma 31>; + dma-names = "tx", "rx"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; + keep-power-in-suspend; + ti,non-removable; +}; + +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 30 + 2 31>; +}; + +/* Four-Wire Resistive Touch */ +&tscadc { + status = "disabled"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + ti,charge-delay = <0xB000>; + }; + + adc { + ti,adc-channels = <0 1 2 3>; + }; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&spi0 { + ti,spi-num-cs = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + dmas = <&edma 16 + &edma 17>; + dma-names = "tx0", "rx0"; + + flash: mx25u3235f@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <24000000>; + reg = <0>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "U-Boot Environment"; + reg = <0x100000 0x080000>; + }; + + partition@180000 { + label = "Flattened Device Tree"; + reg = <0x180000 0x200000>; + }; + + }; +}; + +&spi2 { + ti,spi-num-cs = <2>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + dmas = <&edma 18 + &edma 19 + &edma 20 + &edma 21>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + + spidev1: spidev@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <24000000>; + }; + + spidev2: spidev@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <24000000>; + }; + }; + +&spi4 { + ti,spi-num-cs = <2>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + dmas = <&edma 26 + &edma 27 + &edma 28 + &edma 29>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + + spidev3: spidev@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <24000000>; + }; + + spidev4: spidev@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <24000000>; + }; + }; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + pinctrl-1 = <&uart0_pins_sleep>; + + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + pinctrl-1 = <&uart3_pins_sleep>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + pinctrl-1 = <&uart2_pins_sleep>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + pinctrl-1 = <&uart4_pins_sleep>; + + status = "okay"; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_default>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_default>; + status = "okay"; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <6>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&elm { + status = "okay"; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&rtc { + status = "disabled"; /* Use Seiko S35390A on Module instead */ + ext-clk-src; +}; + +&wdt { + status = "okay"; +}; + +&cpu { + cpu0-supply = <&dcdc2>; +}; + diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index af69ac6..3cd0127 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -88,4 +88,10 @@ /* EDMA3 Base Address */ #define EDMA3_BASE 0x49000000 +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4832A000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_EHRPWM0_BASE 0x48300200 #endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 724e252..4274eba 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -23,6 +23,7 @@ */ #define OMAP_HSMMC1_BASE 0x48060100 #define OMAP_HSMMC2_BASE 0x481D8100 +#define OMAP_HSMMC3_BASE 0x47810100 #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index ea877df..70581c9 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -121,7 +121,16 @@ config TARGET_AM43XX_EVM GP EVM is a standalone test, development, and evaluation module system that enables developers to write software and develop hardware around - an AM43xx processor subsystem. + +config TARGET_SMARCT437X_EVM + bool "Support smarc-t437x" + select TI_I2C_BOARD_DETECT + help + This option specifies support for the SMARC-T437X EVM + development platforms.The SMARC-T437X EVM is a standalone + test, development, and evaluation module system that + enables developers to write software and develop + hardware around an SMARC-T437X processor subsystem. endif if AM43XX || AM33XX diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 74aafd3..d0208ad 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -120,7 +120,7 @@ int cpu_mmc_init(bd_t *bis) if (ret) return ret; - return omap_mmc_init(1, 0, 0, -1, -1); + return omap_mmc_init(2, 0, 0, -1, -1); } #endif diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c index 117a63e..41be8f2 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c @@ -60,6 +60,10 @@ void setup_clocks_for_console(void) CD_CLKCTRL_CLKTRCTRL_SW_WKUP << CD_CLKCTRL_CLKTRCTRL_SHIFT); + clrsetbits_le32(&cmper->l4lsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + /* Enable UART0 */ clrsetbits_le32(&cmwkup->wkup_uart0ctrl, MODULE_CLKCTRL_MODULEMODE_MASK, @@ -72,6 +76,45 @@ void setup_clocks_for_console(void) idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> MODULE_CLKCTRL_IDLEST_SHIFT; } + + /* Enable UART2 */ + clrsetbits_le32(&cmper->uart2clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(&cmper->uart2clkctrl); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + } + + /* Enable UART3 */ + clrsetbits_le32(&cmper->uart3clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(&cmper->uart3clkctrl); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + } + + /* Enable UART4 */ + clrsetbits_le32(&cmper->uart4clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(&cmper->uart4clkctrl); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + } } void enable_basic_clocks(void) @@ -99,6 +142,7 @@ void enable_basic_clocks(void) &cmper->elmclkctrl, &cmper->mmc0clkctrl, &cmper->mmc1clkctrl, + &cmper->mmc2clkctrl, &cmwkup->wkup_i2c0ctrl, &cmper->gpio1clkctrl, &cmper->gpio2clkctrl, @@ -106,11 +150,11 @@ void enable_basic_clocks(void) &cmper->gpio4clkctrl, &cmper->gpio5clkctrl, &cmper->i2c1clkctrl, + &cmper->i2c2clkctrl, &cmper->cpgmac0clkctrl, &cmper->emiffwclkctrl, &cmper->emifclkctrl, &cmper->otfaemifclkctrl, - &cmper->qspiclkctrl, &cmper->spi0clkctrl, 0 }; @@ -122,6 +166,10 @@ void enable_basic_clocks(void) /* For OPP100 the mac clock should be /5. */ writel(0x4, &cmdpll->clkselmacclk); + + /* enable i2c1 clock */ + writel(0x2, &cmper->i2c1clkctrl); + while (readl(&cmper->i2c1clkctrl) != 0x2) ; } void rtc_only_enable_basic_clocks(void) diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk index af45536..9449aa9 100644 --- a/arch/arm/mach-omap2/config.mk +++ b/arch/arm/mach-omap2/config.mk @@ -54,6 +54,7 @@ ALL-y += u-boot-spl_HS_2ND endif else ALL-y += MLO +ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap ifeq ($(CONFIG_AM33XX),y) ALL-y += MLO.byteswap endif diff --git a/board/embedian/common/Kconfig b/board/embedian/common/Kconfig index 6edf7cf..b311f56 100644 --- a/board/embedian/common/Kconfig +++ b/board/embedian/common/Kconfig @@ -7,7 +7,7 @@ config TI_I2C_BOARD_DETECT config EEPROM_BUS_ADDRESS int "Board EEPROM's I2C bus address" range 0 8 - default 0 + default 1 config EEPROM_CHIP_ADDRESS hex "Board EEPROM's I2C chip address" @@ -49,4 +49,14 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y +config CONFIG_SPL_SPI_BUS + int "Board NOR Flash SPI bus address" + range 0 8 + default 0 + +config CONFIG_SPL_SPI_CS + int "Board NOR Flash SPI bus chip select" + range 0 4 + default 0 + endif diff --git a/board/embedian/smarct437x/Kconfig b/board/embedian/smarct437x/Kconfig new file mode 100644 index 0000000..e63bbe7 --- /dev/null +++ b/board/embedian/smarct437x/Kconfig @@ -0,0 +1,17 @@ +if TARGET_SMARCT437X_EVM + +config SYS_BOARD + default "smarct437x" + +config SYS_VENDOR + default "embedian" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "smarct437x_evm" + +source "board/embedian/common/Kconfig" + +endif diff --git a/board/embedian/smarct437x/MAINTAINERS b/board/embedian/smarct437x/MAINTAINERS new file mode 100644 index 0000000..56f0eeb --- /dev/null +++ b/board/embedian/smarct437x/MAINTAINERS @@ -0,0 +1,13 @@ +SMARCT437X SMARC BOARD +M: Eric Lee +S: Maintained +F: board/embedian/smarct437x/ +F: include/configs/smarct437x_evm.h +F: configs/smarct437x_evm_uart0_defconfig +F: configs/smarct437x_evm_uart1_defconfig +F: configs/smarct437x_evm_uart2_defconfig +F: configs/smarct437x_evm_uart3_defconfig +F: configs/smarct437x_evm_spi_usrt0_defconfig +F: configs/smarct437x_evm_spi_uart1_defconfig +F: configs/smarct437x_evm_spi_uart2_defconfig +F: configs/smarct437x_evm_spi_uart3_defconfig diff --git a/board/embedian/smarct437x/Makefile b/board/embedian/smarct437x/Makefile new file mode 100644 index 0000000..36ecb30 --- /dev/null +++ b/board/embedian/smarct437x/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/embedian/smarct437x/board.c b/board/embedian/smarct437x/board.c new file mode 100644 index 0000000..01cfb18 --- /dev/null +++ b/board/embedian/smarct437x/board.c @@ -0,0 +1,1157 @@ +/* + * board.c + * + * Board functions for TI AM43XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/board_detect.h" +#include "board.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* + * Read header information from EEPROM into global structure. + */ +#ifdef CONFIG_TI_I2C_BOARD_DETECT +void do_board_detect(void) +{ + i2c_set_bus_num(1); + if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) + printf("ti_i2c_eeprom_init failed\n"); +} +#endif + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ + {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params gp_evm_dpll_ddr = { + 50, 2, 1, -1, 2, -1, -1}; + +static const struct dpll_params idk_dpll_ddr = { + 400, 23, 1, -1, 2, -1, -1 +}; + +static const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + +const struct ctrl_ioregs ioregs_lpddr2 = { + .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x1, +}; + +const struct emif_regs emif_regs_lpddr2 = { + .sdram_config = 0x808012BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0xEA86B411, + .sdram_tim2 = 0x103A094A, + .sdram_tim3 = 0x0F6BA37F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E284006, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_ddr_ext_phy_ctrl_1 = 0x04010040, + .emif_ddr_ext_phy_ctrl_2 = 0x00500050, + .emif_ddr_ext_phy_ctrl_3 = 0x00500050, + .emif_ddr_ext_phy_ctrl_4 = 0x00500050, + .emif_ddr_ext_phy_ctrl_5 = 0x00500050, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0xc163, +}; + +const struct emif_regs ddr3_emif_regs_400Mhz = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00400040, + .emif_ddr_ext_phy_ctrl_3 = 0x00400040, + .emif_ddr_ext_phy_ctrl_4 = 0x00400040, + .emif_ddr_ext_phy_ctrl_5 = 0x00400040, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_beta = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000065, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { + .sdram_config = 0x638413b2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x80000000, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { + .sdram_config = 0x61a11b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1 = 0x00008009, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000040, + .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, + .emif_ddr_ext_phy_ctrl_4 = 0x00000051, + .emif_ddr_ext_phy_ctrl_5 = 0x00000051, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_prio_class_serv_map = 0x00000000, + .emif_connect_id_serv_1_map = 0x00000000, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x00ffffff +}; + +static const struct emif_regs ddr3_smarc80_emif_regs_400Mhz = { + .sdram_config = 0x63841372, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x80000000, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_smarc1g_emif_regs_400Mhz = { + .sdram_config = 0x638413b2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x80000000, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } + + return; +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + int ind = get_sys_clk_index(); + + if (board_is_eposevm()) + return &epos_evm_dpll_ddr[ind]; + else if (board_is_evm() || board_is_sk() || board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) + return &gp_evm_dpll_ddr; + else if (board_is_idk()) + return &idk_dpll_ddr; + else + printf(" Board '%s' not supported\n", board_ti_get_name()); + return &gp_evm_dpll_ddr; +} + + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp, offset, i; + + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + u32 ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_per[ind]; +} + +void scale_vcores_generic(u32 m) +{ + int mpu_vdd; + + if (i2c_probe(TPS65218_CHIP_PM)) + return; + + switch (m) { + case 1000: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set DCDC1 (CORE) voltage to 1.1V */ + if (tps65218_voltage_update(TPS65218_DCDC1, + TPS65218_DCDC_VOLT_SEL_1100MV)) { + printf("%s failure\n", __func__); + return; + } + + /* Set DCDC2 (MPU) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } + + /* Set DCDC3 (DDR) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC3, + TPS65218_DCDC3_VOLT_SEL_1350MV)) { + printf("%s failure\n", __func__); + return; + } +} + +void scale_vcores_idk(u32 m) +{ + int mpu_vdd; + + if (i2c_probe(TPS62362_I2C_ADDR)) + return; + + switch (m) { + case 1000: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set VDD_MPU voltage */ + if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } +} + +void gpi2c_init(void) +{ + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (first_time) { + enable_i2c1_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + first_time = false; + } +} + +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + + /* Ensure I2C is initialized for PMIC configuration */ + gpi2c_init(); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + if (board_is_idk()) + scale_vcores_idk(mpu_params->m); + else + scale_vcores_generic(mpu_params->m); +} + +void set_uart_mux_conf(void) +{ +#if CONFIG_CONS_INDEX == 1 + enable_uart0_pin_mux(); +#elif CONFIG_CONS_INDEX == 2 + enable_uart1_pin_mux(); +#elif CONFIG_CONS_INDEX == 3 + enable_uart2_pin_mux(); +#elif CONFIG_CONS_INDEX == 4 + enable_uart3_pin_mux(); +#elif CONFIG_CONS_INDEX == 5 + enable_uart4_pin_mux(); +#elif CONFIG_CONS_INDEX == 6 + enable_uart5_pin_mux(); +#endif +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +static void enable_vtt_regulator(void) +{ + u32 temp; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO5_7 */ + writel(GPIO_SETDATAOUT(7), + AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); +} + +enum { + RTC_BOARD_EPOS = 1, + RTC_BOARD_EVM14, + RTC_BOARD_EVM12, + RTC_BOARD_GPEVM, + RTC_BOARD_SK, + RTC_BOARD_SMARC_T437X_800, + RTC_BOARD_SMARC_T437X_01G, +}; + +/* + * In the rtc_only boot path we have the board type info in the rtc scratch pad + * register hence we bypass the costly i2c reads to eeprom and directly program + * the board name string + */ +void rtc_only_update_board_type(u32 btype) +{ + const char *name = ""; + const char *rev = "1.0"; + + switch (btype) { + case RTC_BOARD_EPOS: + name = "AM43EPOS"; + break; + case RTC_BOARD_EVM14: + name = "AM43__GP"; + rev = "1.4"; + break; + case RTC_BOARD_EVM12: + name = "AM43__GP"; + rev = "1.2"; + break; + case RTC_BOARD_GPEVM: + name = "AM43__GP"; + break; + case RTC_BOARD_SK: + name = "AM43__SK"; + break; + case RTC_BOARD_SMARC_T437X_800: + name = "SMCT4X80"; + break; + case RTC_BOARD_SMARC_T437X_01G: + name = "SMCT4X1G"; + break; + } + ti_i2c_eeprom_am_set(name, rev); +} + +u32 rtc_only_get_board_type(void) +{ + if (board_is_eposevm()) + return RTC_BOARD_EPOS; + else if (board_is_evm_14_or_later()) + return RTC_BOARD_EVM14; + else if (board_is_evm_12_or_later()) + return RTC_BOARD_EVM12; + else if (board_is_gpevm()) + return RTC_BOARD_GPEVM; + else if (board_is_sk()) + return RTC_BOARD_SK; + else if (board_is_smarc_t437x_800()) + return RTC_BOARD_SMARC_T437X_800; + else if (board_is_smarc_t437x_01g()) + return RTC_BOARD_SMARC_T437X_01G; + + return 0; +} + +void sdram_init(void) +{ + /* + * EPOS EVM has 1GB LPDDR2 connected to EMIF. + * GP EMV has 1GB DDR3 connected to EMIF + * along with VTT regulator. + */ + if (board_is_eposevm()) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_evm_14_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_production, 0); + } else if (board_is_evm_12_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_beta, 0); + } else if (board_is_evm()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz, 0); + } else if (board_is_sk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_sk_emif_regs_400Mhz, 0); + } else if (board_is_idk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_idk_emif_regs_400Mhz, 0); + } else if (board_is_smarc_t437x_800()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_smarc80_emif_regs_400Mhz, 0); + } else if (board_is_smarc_t437x_01g()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_smarc1g_emif_regs_400Mhz, 0); + } else { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_smarc80_emif_regs_400Mhz, 0); + } +} +#endif + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + + if (board_is_idk()) { + power_tps62362_init(I2C_PMIC); + p = pmic_get("TPS62362"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS62362\n"); + } else { + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + } + + return 0; +} + +int board_init(void) +{ + u32 sys_reboot; + + sys_reboot = readl(PRM_RSTST); + if (sys_reboot & (1 << 9)) + puts("Reset Source: IcePick reset has occurred.\n"); + + if (sys_reboot & (1 << 5)) + puts("Reset Source: Global external warm reset has occurred.\n"); + + if (sys_reboot & (1 << 4)) + puts("Reset Source: watchdog reset has occurred.\n"); + + if (sys_reboot & (1 << 1)) + puts("Reset Source: Global warm SW reset has occurred.\n"); + + if (sys_reboot & (1 << 0)) + puts("Reset Source: Power-on reset has occurred.\n"); + + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, + modena_init0_bw_integer, modena_init0_watermark_0; + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + /* Clear all important bits for DSS errata that may need to be tweaked*/ + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & + MREQPRIO_0_SAB_INIT0_MASK; + + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; + + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & + BW_LIMITER_BW_FRAC_MASK; + + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & + BW_LIMITER_BW_INT_MASK; + + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & + BW_LIMITER_BW_WATERMARK_MASK; + + /* Setting MReq Priority of the DSS*/ + mreqprio_0 |= 0x77; + + /* + * Set L3 Fast Configuration Register + * Limiting bandwith for ARM core to 700 MBPS + */ + modena_init0_bw_fractional |= 0x10; + modena_init0_bw_integer |= 0x3; + + writel(mreqprio_0, &cdev->mreqprio_0); + writel(mreqprio_1, &cdev->mreqprio_1); + + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + struct ti_am_eeprom data; + + if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { + + /* Read Board Info from EEPROM */ + puts("-----------------------------------------\n"); + printf("Board ID: %.*s\n", + sizeof(data.name), board_ti_get_name()); + printf("Board Revision: %.*s\n", + sizeof(data.version), board_ti_get_rev()); + printf("Board Serial#: %.*s\n", + sizeof(data.serial), board_ti_get_serial()); + puts("-----------------------------------------\n"); + + } else { + puts("Bad EEPROM or unknown board!\n"); + return 0; + } + + /* LCD and Backlight Enable Pin */ +#define GPIO_LCD_BKLT_EN 68 +#define GPIO_LCD_PWM_EN 138 + /* BOOT_SEL Pin */ +#define GPIO_BOOT_SEL1 168 +#define GPIO_BOOT_SEL2 169 +#define GPIO_BOOT_SEL3 170 + gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); + gpio_direction_output(GPIO_LCD_BKLT_EN, 1); + gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); + gpio_direction_output(GPIO_LCD_PWM_EN, 1); + + gpio_request(GPIO_BOOT_SEL1, "boot_sel1"); + gpio_direction_input(GPIO_BOOT_SEL1); + gpio_request(GPIO_BOOT_SEL2, "boot_sel2"); + gpio_direction_input(GPIO_BOOT_SEL2); + gpio_request(GPIO_BOOT_SEL3, "boot_sel3"); + gpio_direction_input(GPIO_BOOT_SEL3); + + /*Read BOOT_SEL Configuration */ + if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) { + puts("BOOT_SEL Detected: OFF OFF OFF, SATA Boot Up Not Defined...\n"); + hang(); + } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) { + puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); + setenv_ulong("mmcdev", 2); + setenv("bootcmd", "run findfdt; run mmcboot;"); + } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 0)) { + puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); + setenv_ulong("mmcdev", 0); + setenv("bootcmd", "run findfdt; run mmcboot;"); + } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) { + puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); + setenv_ulong("mmcdev", 1); + setenv("bootcmd", "mmc rescan; run findfdt; run mmcboot;"); + } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) { + puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); + setenv("bootcmd", "dhcp;"); + } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 0)) { + puts("BOOT_SEL Detected: ON ON OFF, Carrier SPI Boot Not Supported...\n"); + hang(); + } else if ((gpio_get_value(168) == 0)&&(gpio_get_value(169) == 0)&&(gpio_get_value(170) == 1)) { + puts("BOOT_SEL Detected: OFF OFF ON, Load zImage from USB1...\n"); + setenv_ulong("usbdev", 0); + setenv("bootcmd", "run findfdt; run usbboot;"); + } else if ((gpio_get_value(168) == 1)&&(gpio_get_value(169) == 1)&&(gpio_get_value(170) == 1)) { + puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); + setenv_ulong("mmcdev", 1); + setenv("bootcmd", "run findfdt; run mmcboot;"); + } else { + puts("unsupported boot up devices\n"); + return 0; + } + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info_env(NULL); + + /* + * Default FIT boot on HS devices. Non FIT images are not allowed + * on HS devices. + */ + if (get_device_type() == HS_DEVICE) + setenv("boot_fit", "1"); +#endif + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device usb_otg_ss1 = { + .maximum_speed = USB_SPEED_HIGH, + .base = USB_OTG_SS1_BASE, + .tx_fifo_resize = false, + .index = 0, +}; + +static struct dwc3_omap_device usb_otg_ss1_glue = { + .base = (void *)USB_OTG_SS1_GLUE_BASE, + .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, + .index = 0, +}; + +static struct ti_usb_phy_device usb_phy1_device = { + .usb2_phy_power = (void *)USB2_PHY1_POWER, + .index = 0, +}; + +static struct dwc3_device usb_otg_ss2 = { + .maximum_speed = USB_SPEED_HIGH, + .base = USB_OTG_SS2_BASE, + .tx_fifo_resize = false, + .index = 1, +}; + +static struct dwc3_omap_device usb_otg_ss2_glue = { + .base = (void *)USB_OTG_SS2_GLUE_BASE, + .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, + .index = 1, +}; + +static struct ti_usb_phy_device usb_phy2_device = { + .usb2_phy_power = (void *)USB2_PHY2_POWER, + .index = 1, +}; + +int usb_gadget_handle_interrupts(int index) +{ + u32 status; + + status = dwc3_omap_uboot_interrupt_status(index); + if (status) + dwc3_uboot_handle_interrupt(index); + + return 0; +} +#endif /* CONFIG_USB_DWC3 */ + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) +int board_usb_init(int index, enum usb_init_type init) +{ + enable_usb_clocks(index); +#ifdef CONFIG_USB_DWC3 + switch (index) { + case 0: + if (init == USB_INIT_DEVICE) { + usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; + usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; + dwc3_omap_uboot_init(&usb_otg_ss1_glue); + ti_usb_phy_uboot_init(&usb_phy1_device); + dwc3_uboot_init(&usb_otg_ss1); + } + break; + case 1: + if (init == USB_INIT_DEVICE) { + usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; + usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; + ti_usb_phy_uboot_init(&usb_phy2_device); + dwc3_omap_uboot_init(&usb_otg_ss2_glue); + dwc3_uboot_init(&usb_otg_ss2); + } + break; + default: + printf("Invalid Controller Index\n"); + } +#endif + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ +#ifdef CONFIG_USB_DWC3 + switch (index) { + case 0: + case 1: + if (init == USB_INIT_DEVICE) { + ti_usb_phy_uboot_exit(index); + dwc3_uboot_exit(index); + dwc3_omap_uboot_exit(index); + } + break; + default: + printf("Invalid Controller Index\n"); + } +#endif + disable_usb_clocks(index); + + return 0; +} +#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ + +#ifndef CONFIG_DM_ETH +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* Additional controls can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 16, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + + +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \ + defined(CONFIG_SPL_USBETH_SUPPORT)) && \ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + puts(" not set. Validating first E-fuse MAC\n"); + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifndef CONFIG_SPL_BUILD + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } +#endif + if (board_is_eposevm()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 16; + } else if (board_is_sk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 4; + cpsw_slaves[1].phy_addr = 5; + } else if (board_is_idk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 0; + } else if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 6; + cpsw_slaves[1].phy_addr = 7; + } else { + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 6; + cpsw_slaves[1].phy_addr = 7; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) { + printf("Error %d registering CPSW switch\n", rv); + return rv; + } +#endif +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("usbnet_devaddr", mac_addr); + + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); +#endif + + return rv; +} +#endif +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) + return 0; + else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) + return 0; + else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) + return 0; + else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) + return 0; + else if (board_is_smarc_t437x_800() && !strcmp(name, "am437x-smarct437x")) + return 0; + else if (board_is_smarc_t437x_01g() && !strcmp(name, "am437x-smarct437xSMCT4X1G")) + return 0; + else + return -1; +} +#endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} + +void board_tee_image_process(ulong tee_image, size_t tee_size) +{ + secure_tee_install((u32)tee_image); +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); +#endif diff --git a/board/embedian/smarct437x/board.h b/board/embedian/smarct437x/board.h new file mode 100644 index 0000000..26a67d7 --- /dev/null +++ b/board/embedian/smarct437x/board.h @@ -0,0 +1,76 @@ +/* + * board.h + * + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include + +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + +static inline int board_is_eposevm(void) +{ + return board_ti_is("AM43EPOS"); +} + +static inline int board_is_gpevm(void) +{ + return board_ti_is("AM43__GP"); +} + +static inline int board_is_sk(void) +{ + return board_ti_is("AM43__SK"); +} + +static inline int board_is_smarc_t437x_800(void) +{ + return board_ti_is("SMCT4X80"); +} + +static inline int board_is_smarc_t437x_01g(void) +{ + return board_ti_is("SMCT4X1G"); +} + +static inline int board_is_idk(void) +{ + return board_ti_is("AM43_IDK"); +} + +static inline int board_is_hsevm(void) +{ + return board_ti_is("AM43XXHS"); +} + +static inline int board_is_evm(void) +{ + return board_is_gpevm() || board_is_hsevm(); +} + +static inline int board_is_evm_14_or_later(void) +{ + return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0; +} + +static inline int board_is_evm_12_or_later(void) +{ + return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0; +} + +void enable_uart0_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_board_pin_mux(void); +void enable_i2c1_pin_mux(void); +#endif diff --git a/board/embedian/smarct437x/mux.c b/board/embedian/smarct437x/mux.c new file mode 100644 index 0000000..95d4894 --- /dev/null +++ b/board/embedian/smarct437x/mux.c @@ -0,0 +1,373 @@ +/* + * mux.c + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "../common/board_detect.h" +#include "board.h" + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */ + {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */ + {-1}, +}; + +/* LAN1 */ +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {-1}, +}; + +/* LAN2 */ +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */ + {-1}, +}; + +static struct module_pin_mux mdio_pin_mux[] = { + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +/* SER0 */ +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {OFFSET(uart0_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +/* SER2 */ +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(cam1_data4), (MODE(2) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(cam1_data5), (MODE(2) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {OFFSET(cam1_data6), (MODE(2) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(cam1_data7), (MODE(2) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +/* SER1 */ +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(uart3_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart3_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +/* SER3 */ +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +/* SD */ +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {OFFSET(rmii1_refclk), MODE(5) | PULLUP_EN}, /* SDIO_PWREN */ + {-1}, +}; + +/* EMMC */ +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* MMC1_CMD */ + {OFFSET(gpmc_ad0), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_ad1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad2), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad4), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT4 */ + {OFFSET(gpmc_ad5), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad6), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad7), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT7 */ + {-1}, +}; + +/* SDMMC */ +static struct module_pin_mux mmc2_pin_mux[] = { + {OFFSET(gpmc_clk), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_CLK */ + {OFFSET(gpmc_csn3), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_CMD */ + {OFFSET(gpmc_ad12), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT0 */ + {OFFSET(gpmc_ad13), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT1 */ + {OFFSET(gpmc_ad14), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT2 */ + {OFFSET(gpmc_ad15), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT3 */ + {OFFSET(gpmc_ad8), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT4 */ + {OFFSET(gpmc_ad9), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT5 */ + {OFFSET(gpmc_ad10), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT6 */ + {OFFSET(gpmc_ad11), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* MMC2_DAT7 */ + {-1}, +}; + +/* I2C_GP */ +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +/* I2C_PM */ +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(mii1_crs), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(mii1_rxerr), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +/* I2C_LCD */ +static struct module_pin_mux i2c2_pin_mux[] = { + {OFFSET(cam1_data0), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(cam1_data1), (MODE(3) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +/* GPIO */ +static struct module_pin_mux smarc_gpio_pin_mux[] = { + {OFFSET(mii1_col), (MODE(9) | PULLUP_EN | RXACTIVE)}, /* USB0_OC#, mii1_col.gpio0_0*/ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* USB1_OC#, gmpc_be1n.gpio1.28 */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUP_EN)}, /* SDIO_PWREN, rmii1_refclk.gpio0.29 */ +/* By SMARC Spec. GPIO0-5 is recommended for use as outputs. */ + {OFFSET(spi2_cs0), (MODE(9) | PULLUP_EN)}, /* GPIO0, spi2_cs0.gpio0_23 */ + {OFFSET(spi2_d0), (MODE(9) | PULLUP_EN)}, /* GPIO1, spi2_d0_gpio0_20 */ + {OFFSET(spi2_d1), (MODE(9) | PULLUP_EN)}, /* GPIO2, spi2_d1.gpio0_21 */ + {OFFSET(spi2_sclk), (MODE(9) | PULLUP_EN)}, /* GPIO3, spi2_sclk.gpio0_22*/ + {OFFSET(cam0_data5), (MODE(7) | PULLUP_EN)}, /* GPIO4, cam0_data5.gpio4_7 */ + {OFFSET(cam0_data7), (MODE(7) | PULLUP_EN)}, /* GPIO5, cam0_data7.gpio4_29 */ + +/* By SMARC Spec. GPIO6-11 is recommended for use of inputs */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | RXACTIVE)}, /* GPIO6, mcasp0.ahclkr.gpio3_7 */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* GPIO7, mcasp0.axr0.gpio3_6 */ + {OFFSET(cam0_data2), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* GPIO8, cam0_data2.gpio4_24 */ + {OFFSET(cam0_data3), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* GPIO9, cam0_data3.gpio4_25 */ + {OFFSET(cam0_data4), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* GPIO10, cam0_data4_gpio4_26 */ + {OFFSET(cam0_data6), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* GPIO11, cam0_data6_gpio4_28 */ + {-1}, +}; + +/* DSS LCD */ +static struct module_pin_mux dss_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, + /* DSS DATA16~23 */ + {OFFSET(cam1_data9), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_data9), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_data8), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_pclk), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_wen), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_field), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_vd), (MODE(2) | PULLUDDIS)}, + {OFFSET(cam0_hd), (MODE(2) | PULLUDDIS)}, + {OFFSET(lcd_vsync), (MODE(0) | PULLUDEN)}, + {OFFSET(lcd_hsync), (MODE(0) | PULLUDEN)}, + {OFFSET(lcd_pclk), (MODE(0) | PULLUDEN)}, + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDEN)}, + {-1}, + }; + +static struct module_pin_mux gpio5_7_pin_mux[] = { + {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ +#endif + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */ + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */ + {-1}, +}; +#endif + +static __maybe_unused struct module_pin_mux qspi_pin_mux[] = { + {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ + {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ + {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ + {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ + {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ + {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ + {-1}, +}; + +/* SPI BOOT */ +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_d1), (MODE(0) | PULLUDEN)}, + {OFFSET(spi0_cs0), (MODE(0) | PULLUDEN)}, + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, + {-1}, +}; + +/* SPI0 */ +static struct module_pin_mux spi2_pin_mux[] = { + {OFFSET(cam1_hd), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* SPI0_CS0 */ + {OFFSET(cam1_field), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* SPI0_CS1 */ + {OFFSET(cam1_pclk), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* SPI0_CLK */ + {OFFSET(cam1_data8), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* SPI0_D0 */ + {OFFSET(cam1_wen), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* SPI0_D1 */ + {-1}, +}; + +/* SPI1 */ +static struct module_pin_mux spi4_pin_mux[] = { + {OFFSET(spi4_cs0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* SPI0_CS0 */ + {OFFSET(uart3_ctsn), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* SPI0_CS1 */ + {OFFSET(spi4_sclk), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* SPI0_CLK */ + {OFFSET(spi4_d0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* SPI0_D0 */ + {OFFSET(spi4_d1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* SPI0_D1 */ + {-1}, +}; + +/* BOOT_SEL */ +static struct module_pin_mux boot_sel_pin_mux[] = { + {OFFSET(gpio5_8), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* BOOT_SEL0, mii1_col.gpio0_0*/ + {OFFSET(gpio5_9), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* BOOT_SEL1, gmpc_be1n.gpio1.28 */ + {OFFSET(gpio5_10), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* BOOT_SEL2, spi2_cs0.gpio0_23 */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + if (board_is_gpevm()) { + configure_module_pin_mux(gpio5_7_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif + } else if (board_is_sk() || board_is_idk()) { + configure_module_pin_mux(rgmii1_pin_mux); +#if defined(CONFIG_NAND) + printf("Error: NAND flash not present on this board\n"); +#endif + configure_module_pin_mux(qspi_pin_mux); + } else if (board_is_smarc_t437x_800() || board_is_smarc_t437x_01g()) { + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mdio_pin_mux); + configure_module_pin_mux(spi2_pin_mux); + configure_module_pin_mux(spi4_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); + configure_module_pin_mux(mmc2_pin_mux); + configure_module_pin_mux(i2c2_pin_mux); + configure_module_pin_mux(smarc_gpio_pin_mux); + configure_module_pin_mux(dss_pin_mux); + configure_module_pin_mux(boot_sel_pin_mux); + } else if (board_is_eposevm()) { + configure_module_pin_mux(rmii1_pin_mux); +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#else + configure_module_pin_mux(qspi_pin_mux); +#endif + } else { + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(mdio_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(boot_sel_pin_mux); + /* Unknown board. We might still be able to boot. */ + puts("Bad EEPROM or unknown board, cannot configure pinmux."); + } +} + +void enable_i2c1_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); +} diff --git a/common/Kconfig b/common/Kconfig index a9be4d3..515cbd0 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -160,7 +160,7 @@ endmenu config BOOTDELAY int "delay in seconds before automatically booting" - default 2 + default 1 depends on AUTOBOOT help Delay before automatically running bootcmd; diff --git a/configs/smarct437x_evm_spi_uart0_defconfig b/configs/smarct437x_evm_spi_uart0_defconfig new file mode 100644 index 0000000..96772f9 --- /dev/null +++ b/configs/smarct437x_evm_spi_uart0_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,SPI_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_spi_uart1_defconfig b/configs/smarct437x_evm_spi_uart1_defconfig new file mode 100644 index 0000000..c5d87c0 --- /dev/null +++ b/configs/smarct437x_evm_spi_uart1_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=4,SPI_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_spi_uart2_defconfig b/configs/smarct437x_evm_spi_uart2_defconfig new file mode 100644 index 0000000..0502c73 --- /dev/null +++ b/configs/smarct437x_evm_spi_uart2_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPI_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_spi_uart3_defconfig b/configs/smarct437x_evm_spi_uart3_defconfig new file mode 100644 index 0000000..3006a55 --- /dev/null +++ b/configs/smarct437x_evm_spi_uart3_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5,SPI_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_uart0_defconfig b/configs/smarct437x_evm_uart0_defconfig new file mode 100644 index 0000000..8d209b1 --- /dev/null +++ b/configs/smarct437x_evm_uart0_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,EMMC_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_uart1_defconfig b/configs/smarct437x_evm_uart1_defconfig new file mode 100644 index 0000000..cb7995c --- /dev/null +++ b/configs/smarct437x_evm_uart1_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=4,EMMC_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_uart2_defconfig b/configs/smarct437x_evm_uart2_defconfig new file mode 100644 index 0000000..020e2d5 --- /dev/null +++ b/configs/smarct437x_evm_uart2_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,EMMC_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/smarct437x_evm_uart3_defconfig b/configs/smarct437x_evm_uart3_defconfig new file mode 100644 index 0000000..ff6d3c9 --- /dev/null +++ b/configs/smarct437x_evm_uart3_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_AM43XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SMARCT437X_EVM=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_RTC_ONLY_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-smarct437x" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5,EMMC_BOOT" +#CONFIG_QSPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Texas Instruments" +CONFIG_G_DNL_VENDOR_NUM=0x0403 +CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_OF_LIBFDT=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index edca94e..0427e6e 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -76,6 +76,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, + {"mx25u3235f", INFO(0xc22536, 0x0, 64 * 1024, 64, 0 | SECT_4K) }, {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index 0dcf9fe..7209d97 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -104,6 +104,7 @@ int pmic_probe(struct pmic *p) { i2c_set_bus_num(p->bus); debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name); + i2c_set_bus_num(1); if (i2c_probe(pmic_i2c_addr)) { printf("Can't find PMIC:%s\n", p->name); return -1; diff --git a/include/configs/embedian_armv7_common.h b/include/configs/embedian_armv7_common.h index 2d9790f..1eff6ab 100644 --- a/include/configs/embedian_armv7_common.h +++ b/include/configs/embedian_armv7_common.h @@ -62,6 +62,36 @@ "fit_bootfile=fitImage\0" \ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \ "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4 rootwait fixrtc\0" \ + "finduuid=part uuid mmc 0:2 uuid\0" \ + "args_mmc=run finduuid;setenv bootargs console=${console} " \ + "${optargs} " \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "bootenvfile=uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \ + "envboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootscript; then " \ + "run bootscript;" \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded env from ${bootenvfile};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "fi;\0" \ /* * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, diff --git a/include/configs/embedian_armv7_omap.h b/include/configs/embedian_armv7_omap.h index 3decf3a..6344821 100644 --- a/include/configs/embedian_armv7_omap.h +++ b/include/configs/embedian_armv7_omap.h @@ -17,7 +17,7 @@ /* I2C IP block */ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 2 #define CONFIG_SYS_I2C_OMAP24XX /* MMC/SD IP block */ diff --git a/include/configs/smarct437x_evm.h b/include/configs/smarct437x_evm.h new file mode 100644 index 0000000..e5395ef --- /dev/null +++ b/include/configs/smarct437x_evm.h @@ -0,0 +1,473 @@ +/* + * smarct437x_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SMARCT437X_EVM_H +#define __CONFIG_SMARCT437X_EVM_H + +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include +#define CONFIG_ENV_IS_NOWHERE + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_SERIAL +#endif + +/* I2C Configuration */ +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65218 +#define CONFIG_POWER_TPS62362 + +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPI_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + +/* Now bring in the rest of the common code. */ +#include + +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +#if !defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE +#endif + +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" + +/* SPL USB Support */ + +#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_AM437X_USB2PHY2_HOST +#endif + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT) +#undef CONFIG_USB_DWC3_PHY_OMAP +#undef CONFIG_USB_DWC3_OMAP +#undef CONFIG_USB_DWC3 +#undef CONFIG_USB_DWC3_GADGET + +#undef CONFIG_USB_GADGET_DOWNLOAD +#undef CONFIG_USB_GADGET_VBUS_DRAW +#undef CONFIG_G_DNL_MANUFACTURER +#undef CONFIG_G_DNL_VENDOR_NUM +#undef CONFIG_G_DNL_PRODUCT_NUM +#undef CONFIG_USB_GADGET_DUALSPEED +#endif + +#if !defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)) +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" +#endif + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80800000 + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_TIMER +#undef CONFIG_DM_NAND +#endif + +#ifndef CONFIG_SPL_BUILD +/* USB Device Firmware Update support */ +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM +#else +#define DFUARGS +#endif + +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x020000 : SPL (128KiB) + * 0x020000 - 0x0A0000 : U-Boot (512KiB) + * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) + * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) + * 0x0E0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +/*#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0*/ +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_FAT +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ +#define MTDIDS_DEFAULT "nor0=m25p80-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ + "512k(u-boot),128k(u-boot-env1)," \ + "128k(u-boot-env2),3464k(kernel)," \ + "-(rootfs)" +#endif + +#ifdef CONFIG_QSPI_BOOT +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR +#endif +#undef CONFIG_ENV_IS_IN_FAT +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ +#define CONFIG_ENV_OFFSET 0x110000 +#define CONFIG_ENV_OFFSET_REDUND 0x120000 +#ifdef MTDIDS_DEFAULT +#undef MTDIDS_DEFAULT +#endif +#ifdef MTDPARTS_DEFAULT +#undef MTDPARTS_DEFAULT +#endif +#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \ + "512k(QSPI.u-boot.backup)," \ + "512k(QSPI.u-boot-spl-os)," \ + "64k(QSPI.u-boot-env)," \ + "64k(QSPI.u-boot-env.backup)," \ + "8m(QSPI.kernel)," \ + "-(QSPI.file-system)" +#endif + +#if defined(CONFIG_EMMC_BOOT) +#undef CONFIG_SPL_OS_BOOT +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 + +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif + +/* SPI */ +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_TI_EDMA3 + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#ifndef CONFIG_SPL_BUILD +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "boot_fdt=try\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "fdtfile=am437x-smarct437x.dtb\0" \ + "bootpart=${mmcdev}:1\0" \ + "bootdir=\0" \ + "fdtdir=/dtbs\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "cmdline=\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "usbroot=/dev/sda2 rw\0" \ + "usbrootfstype=ext4 rootwait\0" \ + "usbdev=0\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "script=boot.scr\0" \ + "scriptfile=${script}\0" \ + "loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \ + "bootscript=echo Running bootscript from mmc${bootpart} ...; " \ + "source ${loadaddr}\0" \ + "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ + "loadusbbootenv=load usb ${bootpart} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t -r $loadaddr $filesize\0" \ + "importusbbootenv=echo Importing environment from usb ...; " \ + "env import -t -r $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load ${devtype} ${mmcdev}:1 ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=echo loading ${fdtdir}/${fdtfile} ...; load ${devtype} ${mmcdev}:1 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "setenv devnum ${mmcdev}; " \ + "setenv bootpart ${mmcdev}:1; "\ + "setenv devtype mmc; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${devnum};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from mmc${mmcdev} ...; " \ + "run args_mmc; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi;\0" \ + "usbboot=" \ + "setenv devnum ${usbdev}; " \ + "setenv devtype usb; " \ + "usb start ${usbdev}; " \ + "if usb dev ${usbdev}; then " \ + "if run loadusbbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importusbbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from usb ${usbdev}...; " \ + "run usbargs;" \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi\0" \ + "fi;" \ + "usb stop ${usbdev};\0" \ + "findfdt="\ + "if test $board_name = AM43EPOS; then " \ + "setenv fdtfile am43x-epos-evm.dtb; fi; " \ + "if test $board_name = AM43__GP; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $board_name = AM43XXHS; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $board_name = AM43__SK; then " \ + "setenv fdtfile am437x-sk-evm.dtb; fi; " \ + "if test $board_name = AM43_IDK; then " \ + "setenv fdtfile am437x-idk-evm.dtb; fi; " \ + "if test $board_name = SMCT4X80; then " \ + "setenv fdtfile am437x-smarct437x.dtb; fi; " \ + "if test $board_name = SMCT4X1G; then " \ + "setenv fdtfile am437x-smarct437x.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree; fi; \0" \ + NANDARGS \ + NETARGS \ + DFUARGS \ + +#define CONFIG_BOOTCOMMAND \ + "if test ${boot_fit} -eq 1; then " \ + "run update_to_fit;" \ + "fi;" \ + "run findfdt; " \ + "run envboot;" \ + "run mmcboot;" \ + "run usbboot;" \ + NANDBOOT \ + +#endif + +#ifndef CONFIG_SPL_BUILD +/* CPSW Ethernet */ +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_PHY_GIGE +#endif + +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT) +#undef CONFIG_ENV_IS_IN_FAT +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SPL_NET_SUPPORT +#endif + +#define CONFIG_SYS_RX_ETH_BUFFER 64 + +/* NAND support */ +#ifdef CONFIG_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ + } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 26 +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ + "256k(NAND.SPL)," \ + "256k(NAND.SPL.backup1)," \ + "256k(NAND.SPL.backup2)," \ + "256k(NAND.SPL.backup3)," \ + "512k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "256k(NAND.u-boot-env)," \ + "256k(NAND.u-boot-env.backup1)," \ + "7m(NAND.kernel)," \ + "-(NAND.file-system)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_AM33XX_BCH +#endif +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#endif +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#define NANDBOOT "run nandboot; " +#else /* !CONFIG_NAND */ +#define NANDARGS +#define NANDBOOT +#endif /* CONFIG_NAND */ + +#if defined(CONFIG_TI_SECURE_DEVICE) +/* Avoid relocating onto firewalled area at end of DRAM */ +#define CONFIG_PRAM (64 * 1024) +#endif /* CONFIG_TI_SECURE_DEVICE */ + +#endif /* __CONFIG_SMARCT437X_EVM_H */ diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index 292c2eb..c4a7f71 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -14,12 +14,14 @@ #define MUX_MODE6 6 #define MUX_MODE7 7 #define MUX_MODE8 8 +#define MUX_MODE9 9 #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) #define SLEWCTRL_SLOW (1 << 19) #define SLEWCTRL_FAST 0 +#define DS0_FORCE_OFF_MODE (1 << 24) #define DS0_PULL_UP_DOWN_EN (1 << 27) #define WAKEUP_ENABLE (1 << 29) -- 1.9.1