Commit c48c0a4d721107f555acd97189a5b0cbee3d9b0b
1 parent
4d0da8e30c
Exists in
smarc_8mq_lf_v2020.04
and in
4 other branches
MLK-25310 imx8m: ddr: Disable CA VREF Training for LPDDR4
Users reported LPDDR4 MR12 value is set to 0 during PHY training, not the value from FSP timing structure, which cause compliance test failed. The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing but not set in 1D. According to PHY training application node, to enable the feature both 1D and 2D need set this field to 1, otherwise the training result will be incorrect. The PHY training doc also recommends to set CATrainOpt[0] to 0 to use MR12 value from message block (FSP structure). So update the LPDDR4 scripts of all mscale to clear CATrainOpt[0]. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 2c98fb859258478e0f8bb8df980a96edff19d359)
Showing 5 changed files with 0 additions and 12 deletions Side-by-side Diff
board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c
... | ... | @@ -1060,7 +1060,6 @@ |
1060 | 1060 | { 0x54008, 0x131f }, |
1061 | 1061 | { 0x54009, 0xc8 }, |
1062 | 1062 | { 0x5400b, 0x2 }, |
1063 | - { 0x5400d, 0x100 }, | |
1064 | 1063 | { 0x54012, 0x110 }, |
1065 | 1064 | { 0x54019, 0x2dd4 }, |
1066 | 1065 | { 0x5401a, 0x31 }, |
... | ... | @@ -1101,7 +1100,6 @@ |
1101 | 1100 | { 0x54008, 0x121f }, |
1102 | 1101 | { 0x54009, 0xc8 }, |
1103 | 1102 | { 0x5400b, 0x2 }, |
1104 | - { 0x5400d, 0x100 }, | |
1105 | 1103 | { 0x54012, 0x110 }, |
1106 | 1104 | { 0x54019, 0x84 }, |
1107 | 1105 | { 0x5401a, 0x31 }, |
... | ... | @@ -1142,7 +1140,6 @@ |
1142 | 1140 | { 0x54008, 0x121f }, |
1143 | 1141 | { 0x54009, 0xc8 }, |
1144 | 1142 | { 0x5400b, 0x2 }, |
1145 | - { 0x5400d, 0x100 }, | |
1146 | 1143 | { 0x54012, 0x110 }, |
1147 | 1144 | { 0x54019, 0x84 }, |
1148 | 1145 | { 0x5401a, 0x31 }, |
board/freescale/imx8mm_evk/lpddr4_timing.c
... | ... | @@ -1060,7 +1060,6 @@ |
1060 | 1060 | { 0x54008, 0x131f }, |
1061 | 1061 | { 0x54009, 0xc8 }, |
1062 | 1062 | { 0x5400b, 0x2 }, |
1063 | - { 0x5400d, 0x100 }, | |
1064 | 1063 | { 0x54012, 0x110 }, |
1065 | 1064 | { 0x54019, 0x2dd4 }, |
1066 | 1065 | { 0x5401a, 0x31 }, |
... | ... | @@ -1101,7 +1100,6 @@ |
1101 | 1100 | { 0x54008, 0x121f }, |
1102 | 1101 | { 0x54009, 0xc8 }, |
1103 | 1102 | { 0x5400b, 0x2 }, |
1104 | - { 0x5400d, 0x100 }, | |
1105 | 1103 | { 0x54012, 0x110 }, |
1106 | 1104 | { 0x54019, 0x84 }, |
1107 | 1105 | { 0x5401a, 0x31 }, |
... | ... | @@ -1142,7 +1140,6 @@ |
1142 | 1140 | { 0x54008, 0x121f }, |
1143 | 1141 | { 0x54009, 0xc8 }, |
1144 | 1142 | { 0x5400b, 0x2 }, |
1145 | - { 0x5400d, 0x100 }, | |
1146 | 1143 | { 0x54012, 0x110 }, |
1147 | 1144 | { 0x54019, 0x84 }, |
1148 | 1145 | { 0x5401a, 0x31 }, |
board/freescale/imx8mm_evk/lpddr4_timing_4g.c
... | ... | @@ -1052,7 +1052,6 @@ |
1052 | 1052 | {0x54008,0x131f}, |
1053 | 1053 | {0x54009,0xc8}, |
1054 | 1054 | {0x5400b,0x2}, |
1055 | - {0x5400d,0x100}, | |
1056 | 1055 | {0x54012,0x310}, |
1057 | 1056 | {0x54019,0x2dd4}, |
1058 | 1057 | {0x5401a,0x31}, |
... | ... | @@ -1092,7 +1091,6 @@ |
1092 | 1091 | {0x54008,0x121f}, |
1093 | 1092 | {0x54009,0xc8}, |
1094 | 1093 | {0x5400b,0x2}, |
1095 | - {0x5400d,0x100}, | |
1096 | 1094 | {0x54012,0x310}, |
1097 | 1095 | {0x54019,0x84}, |
1098 | 1096 | {0x5401a,0x31}, |
... | ... | @@ -1132,7 +1130,6 @@ |
1132 | 1130 | {0x54008,0x121f}, |
1133 | 1131 | {0x54009,0xc8}, |
1134 | 1132 | {0x5400b,0x2}, |
1135 | - {0x5400d,0x100}, | |
1136 | 1133 | {0x54012,0x310}, |
1137 | 1134 | {0x54019,0x84}, |
1138 | 1135 | {0x5401a,0x31}, |
board/freescale/imx8mn_evk/lpddr4_timing_ld.c
board/freescale/imx8mp_evk/lpddr4_timing.c
... | ... | @@ -1298,7 +1298,6 @@ |
1298 | 1298 | { 0x54008, 0x61 }, |
1299 | 1299 | { 0x54009, 0xc8 }, |
1300 | 1300 | { 0x5400b, 0x2 }, |
1301 | - { 0x5400d, 0x100 }, | |
1302 | 1301 | { 0x5400f, 0x100 }, |
1303 | 1302 | { 0x54010, 0x1f7f }, |
1304 | 1303 | { 0x54012, 0x310 }, |
... | ... | @@ -1330,7 +1329,6 @@ |
1330 | 1329 | { 0x54008, 0x61 }, |
1331 | 1330 | { 0x54009, 0xc8 }, |
1332 | 1331 | { 0x5400b, 0x2 }, |
1333 | - { 0x5400d, 0x100 }, | |
1334 | 1332 | { 0x5400f, 0x100 }, |
1335 | 1333 | { 0x54010, 0x1f7f }, |
1336 | 1334 | { 0x54012, 0x310 }, |