From c48c0a4d721107f555acd97189a5b0cbee3d9b0b Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 20 Feb 2021 10:45:37 -0800 Subject: [PATCH] MLK-25310 imx8m: ddr: Disable CA VREF Training for LPDDR4 Users reported LPDDR4 MR12 value is set to 0 during PHY training, not the value from FSP timing structure, which cause compliance test failed. The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing but not set in 1D. According to PHY training application node, to enable the feature both 1D and 2D need set this field to 1, otherwise the training result will be incorrect. The PHY training doc also recommends to set CATrainOpt[0] to 0 to use MR12 value from message block (FSP structure). So update the LPDDR4 scripts of all mscale to clear CATrainOpt[0]. Signed-off-by: Ye Li Reviewed-by: Jacky Bai (cherry picked from commit 2c98fb859258478e0f8bb8df980a96edff19d359) --- board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c | 3 --- board/freescale/imx8mm_evk/lpddr4_timing.c | 3 --- board/freescale/imx8mm_evk/lpddr4_timing_4g.c | 3 --- board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1 - board/freescale/imx8mp_evk/lpddr4_timing.c | 2 -- 5 files changed, 12 deletions(-) diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c index 664c08e..5fe9266 100644 --- a/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c +++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c @@ -1060,7 +1060,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54008, 0x131f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, @@ -1101,7 +1100,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, @@ -1142,7 +1140,6 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c index 5068fa7..3495b9c 100644 --- a/board/freescale/imx8mm_evk/lpddr4_timing.c +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -1060,7 +1060,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54008, 0x131f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, @@ -1101,7 +1100,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, @@ -1142,7 +1140,6 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, diff --git a/board/freescale/imx8mm_evk/lpddr4_timing_4g.c b/board/freescale/imx8mm_evk/lpddr4_timing_4g.c index af64097..d32ecbf 100755 --- a/board/freescale/imx8mm_evk/lpddr4_timing_4g.c +++ b/board/freescale/imx8mm_evk/lpddr4_timing_4g.c @@ -1052,7 +1052,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { {0x54008,0x131f}, {0x54009,0xc8}, {0x5400b,0x2}, - {0x5400d,0x100}, {0x54012,0x310}, {0x54019,0x2dd4}, {0x5401a,0x31}, @@ -1092,7 +1091,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { {0x54008,0x121f}, {0x54009,0xc8}, {0x5400b,0x2}, - {0x5400d,0x100}, {0x54012,0x310}, {0x54019,0x84}, {0x5401a,0x31}, @@ -1132,7 +1130,6 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { {0x54008,0x121f}, {0x54009,0xc8}, {0x5400b,0x2}, - {0x5400d,0x100}, {0x54012,0x310}, {0x54019,0x84}, {0x5401a,0x31}, diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c index 17c0121..08f86df 100644 --- a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c +++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c @@ -803,7 +803,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c index 2a95580..d3ab61a 100755 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -1298,7 +1298,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, @@ -1330,7 +1329,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, -- 1.9.1