Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit ddcf13b15231ee2dca99285349b143c365ce5173

Authored by Otavio Salvador
Committed by Albert ARIBAUD
1 parent 3a0398d7b9
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mxs: prefix register acessor macros with 'mxs' prefix 

As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

Showing 22 changed files with 529 additions and 529 deletions Side-by-side Diff

arch/arm/cpu/arm926ejs/mxs/clock.c
Diff comments   View file @ ddcf13b
... ... @@ -207,7 +207,7 @@
207 207 return;
208 208  
209 209 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
210   - (ssp * sizeof(struct mx28_register_32));
  210 + (ssp * sizeof(struct mxs_register_32));
211 211  
212 212 clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
213 213 while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
... ... @@ -256,7 +256,7 @@
256 256 return XTAL_FREQ_KHZ;
257 257  
258 258 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
259   - (ssp * sizeof(struct mx28_register_32));
  259 + (ssp * sizeof(struct mxs_register_32));
260 260  
261 261 tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
262 262  
arch/arm/cpu/arm926ejs/mxs/iomux.c
Diff comments   View file @ ddcf13b
... ... @@ -43,7 +43,7 @@
43 43 {
44 44 u32 reg, ofs, bp, bm;
45 45 void *iomux_base = (void *)MXS_PINCTRL_BASE;
46   - struct mx28_register_32 *mxs_reg;
  46 + struct mxs_register_32 *mxs_reg;
47 47  
48 48 /* muxsel */
49 49 ofs = 0x100;
... ... @@ -70,7 +70,7 @@
70 70 /* vol */
71 71 if (PAD_VOL_VALID(pad)) {
72 72 bp = PAD_PIN(pad) % 8 * 4 + 2;
73   - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
  73 + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
74 74 if (PAD_VOL(pad))
75 75 writel(1 << bp, &mxs_reg->reg_set);
76 76 else
... ... @@ -82,7 +82,7 @@
82 82 ofs = PULL_OFFSET;
83 83 ofs += PAD_BANK(pad) * 0x10;
84 84 bp = PAD_PIN(pad);
85   - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
  85 + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
86 86 if (PAD_PULL(pad))
87 87 writel(1 << bp, &mxs_reg->reg_set);
88 88 else
arch/arm/cpu/arm926ejs/mxs/mx28.c
Diff comments   View file @ ddcf13b
... ... @@ -81,7 +81,7 @@
81 81 #endif
82 82 }
83 83  
84   -int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
  84 +int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
85 85 {
86 86 while (--timeout) {
87 87 if ((readl(&reg->reg) & mask) == mask)
... ... @@ -92,7 +92,7 @@
92 92 return !timeout;
93 93 }
94 94  
95   -int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
  95 +int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
96 96 {
97 97 while (--timeout) {
98 98 if ((readl(&reg->reg) & mask) == 0)
... ... @@ -103,7 +103,7 @@
103 103 return !timeout;
104 104 }
105 105  
106   -int mx28_reset_block(struct mx28_register_32 *reg)
  106 +int mx28_reset_block(struct mxs_register_32 *reg)
107 107 {
108 108 /* Clear SFTRST */
109 109 writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
arch/arm/include/asm/arch-mxs/regs-apbh.h
Diff comments   View file @ ddcf13b
... ... @@ -30,142 +30,142 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_apbh_regs {
33   - mx28_reg_32(hw_apbh_ctrl0)
34   - mx28_reg_32(hw_apbh_ctrl1)
35   - mx28_reg_32(hw_apbh_ctrl2)
36   - mx28_reg_32(hw_apbh_channel_ctrl)
37   - mx28_reg_32(hw_apbh_devsel)
38   - mx28_reg_32(hw_apbh_dma_burst_size)
39   - mx28_reg_32(hw_apbh_debug)
  33 + mxs_reg_32(hw_apbh_ctrl0)
  34 + mxs_reg_32(hw_apbh_ctrl1)
  35 + mxs_reg_32(hw_apbh_ctrl2)
  36 + mxs_reg_32(hw_apbh_channel_ctrl)
  37 + mxs_reg_32(hw_apbh_devsel)
  38 + mxs_reg_32(hw_apbh_dma_burst_size)
  39 + mxs_reg_32(hw_apbh_debug)
40 40  
41 41 uint32_t reserved[36];
42 42  
43 43 union {
44 44 struct {
45   - mx28_reg_32(hw_apbh_ch_curcmdar)
46   - mx28_reg_32(hw_apbh_ch_nxtcmdar)
47   - mx28_reg_32(hw_apbh_ch_cmd)
48   - mx28_reg_32(hw_apbh_ch_bar)
49   - mx28_reg_32(hw_apbh_ch_sema)
50   - mx28_reg_32(hw_apbh_ch_debug1)
51   - mx28_reg_32(hw_apbh_ch_debug2)
  45 + mxs_reg_32(hw_apbh_ch_curcmdar)
  46 + mxs_reg_32(hw_apbh_ch_nxtcmdar)
  47 + mxs_reg_32(hw_apbh_ch_cmd)
  48 + mxs_reg_32(hw_apbh_ch_bar)
  49 + mxs_reg_32(hw_apbh_ch_sema)
  50 + mxs_reg_32(hw_apbh_ch_debug1)
  51 + mxs_reg_32(hw_apbh_ch_debug2)
52 52 } ch[16];
53 53 struct {
54   - mx28_reg_32(hw_apbh_ch0_curcmdar)
55   - mx28_reg_32(hw_apbh_ch0_nxtcmdar)
56   - mx28_reg_32(hw_apbh_ch0_cmd)
57   - mx28_reg_32(hw_apbh_ch0_bar)
58   - mx28_reg_32(hw_apbh_ch0_sema)
59   - mx28_reg_32(hw_apbh_ch0_debug1)
60   - mx28_reg_32(hw_apbh_ch0_debug2)
61   - mx28_reg_32(hw_apbh_ch1_curcmdar)
62   - mx28_reg_32(hw_apbh_ch1_nxtcmdar)
63   - mx28_reg_32(hw_apbh_ch1_cmd)
64   - mx28_reg_32(hw_apbh_ch1_bar)
65   - mx28_reg_32(hw_apbh_ch1_sema)
66   - mx28_reg_32(hw_apbh_ch1_debug1)
67   - mx28_reg_32(hw_apbh_ch1_debug2)
68   - mx28_reg_32(hw_apbh_ch2_curcmdar)
69   - mx28_reg_32(hw_apbh_ch2_nxtcmdar)
70   - mx28_reg_32(hw_apbh_ch2_cmd)
71   - mx28_reg_32(hw_apbh_ch2_bar)
72   - mx28_reg_32(hw_apbh_ch2_sema)
73   - mx28_reg_32(hw_apbh_ch2_debug1)
74   - mx28_reg_32(hw_apbh_ch2_debug2)
75   - mx28_reg_32(hw_apbh_ch3_curcmdar)
76   - mx28_reg_32(hw_apbh_ch3_nxtcmdar)
77   - mx28_reg_32(hw_apbh_ch3_cmd)
78   - mx28_reg_32(hw_apbh_ch3_bar)
79   - mx28_reg_32(hw_apbh_ch3_sema)
80   - mx28_reg_32(hw_apbh_ch3_debug1)
81   - mx28_reg_32(hw_apbh_ch3_debug2)
82   - mx28_reg_32(hw_apbh_ch4_curcmdar)
83   - mx28_reg_32(hw_apbh_ch4_nxtcmdar)
84   - mx28_reg_32(hw_apbh_ch4_cmd)
85   - mx28_reg_32(hw_apbh_ch4_bar)
86   - mx28_reg_32(hw_apbh_ch4_sema)
87   - mx28_reg_32(hw_apbh_ch4_debug1)
88   - mx28_reg_32(hw_apbh_ch4_debug2)
89   - mx28_reg_32(hw_apbh_ch5_curcmdar)
90   - mx28_reg_32(hw_apbh_ch5_nxtcmdar)
91   - mx28_reg_32(hw_apbh_ch5_cmd)
92   - mx28_reg_32(hw_apbh_ch5_bar)
93   - mx28_reg_32(hw_apbh_ch5_sema)
94   - mx28_reg_32(hw_apbh_ch5_debug1)
95   - mx28_reg_32(hw_apbh_ch5_debug2)
96   - mx28_reg_32(hw_apbh_ch6_curcmdar)
97   - mx28_reg_32(hw_apbh_ch6_nxtcmdar)
98   - mx28_reg_32(hw_apbh_ch6_cmd)
99   - mx28_reg_32(hw_apbh_ch6_bar)
100   - mx28_reg_32(hw_apbh_ch6_sema)
101   - mx28_reg_32(hw_apbh_ch6_debug1)
102   - mx28_reg_32(hw_apbh_ch6_debug2)
103   - mx28_reg_32(hw_apbh_ch7_curcmdar)
104   - mx28_reg_32(hw_apbh_ch7_nxtcmdar)
105   - mx28_reg_32(hw_apbh_ch7_cmd)
106   - mx28_reg_32(hw_apbh_ch7_bar)
107   - mx28_reg_32(hw_apbh_ch7_sema)
108   - mx28_reg_32(hw_apbh_ch7_debug1)
109   - mx28_reg_32(hw_apbh_ch7_debug2)
110   - mx28_reg_32(hw_apbh_ch8_curcmdar)
111   - mx28_reg_32(hw_apbh_ch8_nxtcmdar)
112   - mx28_reg_32(hw_apbh_ch8_cmd)
113   - mx28_reg_32(hw_apbh_ch8_bar)
114   - mx28_reg_32(hw_apbh_ch8_sema)
115   - mx28_reg_32(hw_apbh_ch8_debug1)
116   - mx28_reg_32(hw_apbh_ch8_debug2)
117   - mx28_reg_32(hw_apbh_ch9_curcmdar)
118   - mx28_reg_32(hw_apbh_ch9_nxtcmdar)
119   - mx28_reg_32(hw_apbh_ch9_cmd)
120   - mx28_reg_32(hw_apbh_ch9_bar)
121   - mx28_reg_32(hw_apbh_ch9_sema)
122   - mx28_reg_32(hw_apbh_ch9_debug1)
123   - mx28_reg_32(hw_apbh_ch9_debug2)
124   - mx28_reg_32(hw_apbh_ch10_curcmdar)
125   - mx28_reg_32(hw_apbh_ch10_nxtcmdar)
126   - mx28_reg_32(hw_apbh_ch10_cmd)
127   - mx28_reg_32(hw_apbh_ch10_bar)
128   - mx28_reg_32(hw_apbh_ch10_sema)
129   - mx28_reg_32(hw_apbh_ch10_debug1)
130   - mx28_reg_32(hw_apbh_ch10_debug2)
131   - mx28_reg_32(hw_apbh_ch11_curcmdar)
132   - mx28_reg_32(hw_apbh_ch11_nxtcmdar)
133   - mx28_reg_32(hw_apbh_ch11_cmd)
134   - mx28_reg_32(hw_apbh_ch11_bar)
135   - mx28_reg_32(hw_apbh_ch11_sema)
136   - mx28_reg_32(hw_apbh_ch11_debug1)
137   - mx28_reg_32(hw_apbh_ch11_debug2)
138   - mx28_reg_32(hw_apbh_ch12_curcmdar)
139   - mx28_reg_32(hw_apbh_ch12_nxtcmdar)
140   - mx28_reg_32(hw_apbh_ch12_cmd)
141   - mx28_reg_32(hw_apbh_ch12_bar)
142   - mx28_reg_32(hw_apbh_ch12_sema)
143   - mx28_reg_32(hw_apbh_ch12_debug1)
144   - mx28_reg_32(hw_apbh_ch12_debug2)
145   - mx28_reg_32(hw_apbh_ch13_curcmdar)
146   - mx28_reg_32(hw_apbh_ch13_nxtcmdar)
147   - mx28_reg_32(hw_apbh_ch13_cmd)
148   - mx28_reg_32(hw_apbh_ch13_bar)
149   - mx28_reg_32(hw_apbh_ch13_sema)
150   - mx28_reg_32(hw_apbh_ch13_debug1)
151   - mx28_reg_32(hw_apbh_ch13_debug2)
152   - mx28_reg_32(hw_apbh_ch14_curcmdar)
153   - mx28_reg_32(hw_apbh_ch14_nxtcmdar)
154   - mx28_reg_32(hw_apbh_ch14_cmd)
155   - mx28_reg_32(hw_apbh_ch14_bar)
156   - mx28_reg_32(hw_apbh_ch14_sema)
157   - mx28_reg_32(hw_apbh_ch14_debug1)
158   - mx28_reg_32(hw_apbh_ch14_debug2)
159   - mx28_reg_32(hw_apbh_ch15_curcmdar)
160   - mx28_reg_32(hw_apbh_ch15_nxtcmdar)
161   - mx28_reg_32(hw_apbh_ch15_cmd)
162   - mx28_reg_32(hw_apbh_ch15_bar)
163   - mx28_reg_32(hw_apbh_ch15_sema)
164   - mx28_reg_32(hw_apbh_ch15_debug1)
165   - mx28_reg_32(hw_apbh_ch15_debug2)
  54 + mxs_reg_32(hw_apbh_ch0_curcmdar)
  55 + mxs_reg_32(hw_apbh_ch0_nxtcmdar)
  56 + mxs_reg_32(hw_apbh_ch0_cmd)
  57 + mxs_reg_32(hw_apbh_ch0_bar)
  58 + mxs_reg_32(hw_apbh_ch0_sema)
  59 + mxs_reg_32(hw_apbh_ch0_debug1)
  60 + mxs_reg_32(hw_apbh_ch0_debug2)
  61 + mxs_reg_32(hw_apbh_ch1_curcmdar)
  62 + mxs_reg_32(hw_apbh_ch1_nxtcmdar)
  63 + mxs_reg_32(hw_apbh_ch1_cmd)
  64 + mxs_reg_32(hw_apbh_ch1_bar)
  65 + mxs_reg_32(hw_apbh_ch1_sema)
  66 + mxs_reg_32(hw_apbh_ch1_debug1)
  67 + mxs_reg_32(hw_apbh_ch1_debug2)
  68 + mxs_reg_32(hw_apbh_ch2_curcmdar)
  69 + mxs_reg_32(hw_apbh_ch2_nxtcmdar)
  70 + mxs_reg_32(hw_apbh_ch2_cmd)
  71 + mxs_reg_32(hw_apbh_ch2_bar)
  72 + mxs_reg_32(hw_apbh_ch2_sema)
  73 + mxs_reg_32(hw_apbh_ch2_debug1)
  74 + mxs_reg_32(hw_apbh_ch2_debug2)
  75 + mxs_reg_32(hw_apbh_ch3_curcmdar)
  76 + mxs_reg_32(hw_apbh_ch3_nxtcmdar)
  77 + mxs_reg_32(hw_apbh_ch3_cmd)
  78 + mxs_reg_32(hw_apbh_ch3_bar)
  79 + mxs_reg_32(hw_apbh_ch3_sema)
  80 + mxs_reg_32(hw_apbh_ch3_debug1)
  81 + mxs_reg_32(hw_apbh_ch3_debug2)
  82 + mxs_reg_32(hw_apbh_ch4_curcmdar)
  83 + mxs_reg_32(hw_apbh_ch4_nxtcmdar)
  84 + mxs_reg_32(hw_apbh_ch4_cmd)
  85 + mxs_reg_32(hw_apbh_ch4_bar)
  86 + mxs_reg_32(hw_apbh_ch4_sema)
  87 + mxs_reg_32(hw_apbh_ch4_debug1)
  88 + mxs_reg_32(hw_apbh_ch4_debug2)
  89 + mxs_reg_32(hw_apbh_ch5_curcmdar)
  90 + mxs_reg_32(hw_apbh_ch5_nxtcmdar)
  91 + mxs_reg_32(hw_apbh_ch5_cmd)
  92 + mxs_reg_32(hw_apbh_ch5_bar)
  93 + mxs_reg_32(hw_apbh_ch5_sema)
  94 + mxs_reg_32(hw_apbh_ch5_debug1)
  95 + mxs_reg_32(hw_apbh_ch5_debug2)
  96 + mxs_reg_32(hw_apbh_ch6_curcmdar)
  97 + mxs_reg_32(hw_apbh_ch6_nxtcmdar)
  98 + mxs_reg_32(hw_apbh_ch6_cmd)
  99 + mxs_reg_32(hw_apbh_ch6_bar)
  100 + mxs_reg_32(hw_apbh_ch6_sema)
  101 + mxs_reg_32(hw_apbh_ch6_debug1)
  102 + mxs_reg_32(hw_apbh_ch6_debug2)
  103 + mxs_reg_32(hw_apbh_ch7_curcmdar)
  104 + mxs_reg_32(hw_apbh_ch7_nxtcmdar)
  105 + mxs_reg_32(hw_apbh_ch7_cmd)
  106 + mxs_reg_32(hw_apbh_ch7_bar)
  107 + mxs_reg_32(hw_apbh_ch7_sema)
  108 + mxs_reg_32(hw_apbh_ch7_debug1)
  109 + mxs_reg_32(hw_apbh_ch7_debug2)
  110 + mxs_reg_32(hw_apbh_ch8_curcmdar)
  111 + mxs_reg_32(hw_apbh_ch8_nxtcmdar)
  112 + mxs_reg_32(hw_apbh_ch8_cmd)
  113 + mxs_reg_32(hw_apbh_ch8_bar)
  114 + mxs_reg_32(hw_apbh_ch8_sema)
  115 + mxs_reg_32(hw_apbh_ch8_debug1)
  116 + mxs_reg_32(hw_apbh_ch8_debug2)
  117 + mxs_reg_32(hw_apbh_ch9_curcmdar)
  118 + mxs_reg_32(hw_apbh_ch9_nxtcmdar)
  119 + mxs_reg_32(hw_apbh_ch9_cmd)
  120 + mxs_reg_32(hw_apbh_ch9_bar)
  121 + mxs_reg_32(hw_apbh_ch9_sema)
  122 + mxs_reg_32(hw_apbh_ch9_debug1)
  123 + mxs_reg_32(hw_apbh_ch9_debug2)
  124 + mxs_reg_32(hw_apbh_ch10_curcmdar)
  125 + mxs_reg_32(hw_apbh_ch10_nxtcmdar)
  126 + mxs_reg_32(hw_apbh_ch10_cmd)
  127 + mxs_reg_32(hw_apbh_ch10_bar)
  128 + mxs_reg_32(hw_apbh_ch10_sema)
  129 + mxs_reg_32(hw_apbh_ch10_debug1)
  130 + mxs_reg_32(hw_apbh_ch10_debug2)
  131 + mxs_reg_32(hw_apbh_ch11_curcmdar)
  132 + mxs_reg_32(hw_apbh_ch11_nxtcmdar)
  133 + mxs_reg_32(hw_apbh_ch11_cmd)
  134 + mxs_reg_32(hw_apbh_ch11_bar)
  135 + mxs_reg_32(hw_apbh_ch11_sema)
  136 + mxs_reg_32(hw_apbh_ch11_debug1)
  137 + mxs_reg_32(hw_apbh_ch11_debug2)
  138 + mxs_reg_32(hw_apbh_ch12_curcmdar)
  139 + mxs_reg_32(hw_apbh_ch12_nxtcmdar)
  140 + mxs_reg_32(hw_apbh_ch12_cmd)
  141 + mxs_reg_32(hw_apbh_ch12_bar)
  142 + mxs_reg_32(hw_apbh_ch12_sema)
  143 + mxs_reg_32(hw_apbh_ch12_debug1)
  144 + mxs_reg_32(hw_apbh_ch12_debug2)
  145 + mxs_reg_32(hw_apbh_ch13_curcmdar)
  146 + mxs_reg_32(hw_apbh_ch13_nxtcmdar)
  147 + mxs_reg_32(hw_apbh_ch13_cmd)
  148 + mxs_reg_32(hw_apbh_ch13_bar)
  149 + mxs_reg_32(hw_apbh_ch13_sema)
  150 + mxs_reg_32(hw_apbh_ch13_debug1)
  151 + mxs_reg_32(hw_apbh_ch13_debug2)
  152 + mxs_reg_32(hw_apbh_ch14_curcmdar)
  153 + mxs_reg_32(hw_apbh_ch14_nxtcmdar)
  154 + mxs_reg_32(hw_apbh_ch14_cmd)
  155 + mxs_reg_32(hw_apbh_ch14_bar)
  156 + mxs_reg_32(hw_apbh_ch14_sema)
  157 + mxs_reg_32(hw_apbh_ch14_debug1)
  158 + mxs_reg_32(hw_apbh_ch14_debug2)
  159 + mxs_reg_32(hw_apbh_ch15_curcmdar)
  160 + mxs_reg_32(hw_apbh_ch15_nxtcmdar)
  161 + mxs_reg_32(hw_apbh_ch15_cmd)
  162 + mxs_reg_32(hw_apbh_ch15_bar)
  163 + mxs_reg_32(hw_apbh_ch15_sema)
  164 + mxs_reg_32(hw_apbh_ch15_debug1)
  165 + mxs_reg_32(hw_apbh_ch15_debug2)
166 166 };
167 167 };
168   - mx28_reg_32(hw_apbh_version)
  168 + mxs_reg_32(hw_apbh_version)
169 169 };
170 170 #endif
171 171  
arch/arm/include/asm/arch-mxs/regs-bch.h
Diff comments   View file @ ddcf13b
... ... @@ -30,30 +30,30 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_bch_regs {
33   - mx28_reg_32(hw_bch_ctrl)
34   - mx28_reg_32(hw_bch_status0)
35   - mx28_reg_32(hw_bch_mode)
36   - mx28_reg_32(hw_bch_encodeptr)
37   - mx28_reg_32(hw_bch_dataptr)
38   - mx28_reg_32(hw_bch_metaptr)
  33 + mxs_reg_32(hw_bch_ctrl)
  34 + mxs_reg_32(hw_bch_status0)
  35 + mxs_reg_32(hw_bch_mode)
  36 + mxs_reg_32(hw_bch_encodeptr)
  37 + mxs_reg_32(hw_bch_dataptr)
  38 + mxs_reg_32(hw_bch_metaptr)
39 39  
40 40 uint32_t reserved[4];
41 41  
42   - mx28_reg_32(hw_bch_layoutselect)
43   - mx28_reg_32(hw_bch_flash0layout0)
44   - mx28_reg_32(hw_bch_flash0layout1)
45   - mx28_reg_32(hw_bch_flash1layout0)
46   - mx28_reg_32(hw_bch_flash1layout1)
47   - mx28_reg_32(hw_bch_flash2layout0)
48   - mx28_reg_32(hw_bch_flash2layout1)
49   - mx28_reg_32(hw_bch_flash3layout0)
50   - mx28_reg_32(hw_bch_flash3layout1)
51   - mx28_reg_32(hw_bch_dbgkesread)
52   - mx28_reg_32(hw_bch_dbgcsferead)
53   - mx28_reg_32(hw_bch_dbgsyndegread)
54   - mx28_reg_32(hw_bch_dbgahbmread)
55   - mx28_reg_32(hw_bch_blockname)
56   - mx28_reg_32(hw_bch_version)
  42 + mxs_reg_32(hw_bch_layoutselect)
  43 + mxs_reg_32(hw_bch_flash0layout0)
  44 + mxs_reg_32(hw_bch_flash0layout1)
  45 + mxs_reg_32(hw_bch_flash1layout0)
  46 + mxs_reg_32(hw_bch_flash1layout1)
  47 + mxs_reg_32(hw_bch_flash2layout0)
  48 + mxs_reg_32(hw_bch_flash2layout1)
  49 + mxs_reg_32(hw_bch_flash3layout0)
  50 + mxs_reg_32(hw_bch_flash3layout1)
  51 + mxs_reg_32(hw_bch_dbgkesread)
  52 + mxs_reg_32(hw_bch_dbgcsferead)
  53 + mxs_reg_32(hw_bch_dbgsyndegread)
  54 + mxs_reg_32(hw_bch_dbgahbmread)
  55 + mxs_reg_32(hw_bch_blockname)
  56 + mxs_reg_32(hw_bch_version)
57 57 };
58 58 #endif
59 59  
arch/arm/include/asm/arch-mxs/regs-clkctrl.h
Diff comments   View file @ ddcf13b
... ... @@ -30,38 +30,38 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_clkctrl_regs {
33   - mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
34   - mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
35   - mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
36   - mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
37   - mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
38   - mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */
39   - mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */
40   - mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */
41   - mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */
42   - mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */
43   - mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
44   - mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
45   - mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
46   - mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
47   - mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */
48   - mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */
49   - mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */
50   - mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */
51   - mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */
52   - mx28_reg_32(hw_clkctrl_etm) /* 0x130 */
53   - mx28_reg_32(hw_clkctrl_enet) /* 0x140 */
54   - mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */
55   - mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */
  33 + mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
  34 + mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
  35 + mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
  36 + mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
  37 + mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
  38 + mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
  39 + mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
  40 + mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
  41 + mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
  42 + mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
  43 + mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
  44 + mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
  45 + mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
  46 + mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
  47 + mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
  48 + mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
  49 + mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
  50 + mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */
  51 + mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */
  52 + mxs_reg_32(hw_clkctrl_etm) /* 0x130 */
  53 + mxs_reg_32(hw_clkctrl_enet) /* 0x140 */
  54 + mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */
  55 + mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */
56 56  
57 57 uint32_t reserved[16];
58 58  
59   - mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
60   - mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
61   - mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
62   - mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */
63   - mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */
64   - mx28_reg_32(hw_clkctrl_version) /* 0x200 */
  59 + mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
  60 + mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
  61 + mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
  62 + mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */
  63 + mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */
  64 + mxs_reg_32(hw_clkctrl_version) /* 0x200 */
65 65 };
66 66 #endif
67 67  
arch/arm/include/asm/arch-mxs/regs-common.h
Diff comments   View file @ ddcf13b
1 1 /*
2   - * Freescale i.MX28 Register Accessors
  2 + * Freescale i.MXS Register Accessors
3 3 *
4 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 5 * on behalf of DENX Software Engineering GmbH
6 6  
... ... @@ -20,11 +20,11 @@
20 20 *
21 21 */
22 22  
23   -#ifndef __MX28_REGS_COMMON_H__
24   -#define __MX28_REGS_COMMON_H__
  23 +#ifndef __MXS_REGS_COMMON_H__
  24 +#define __MXS_REGS_COMMON_H__
25 25  
26 26 /*
27   - * The i.MX28 has interesting feature when it comes to register access. There
  27 + * The i.MXS has interesting feature when it comes to register access. There
28 28 * are four kinds of access to one particular register. Those are:
29 29 *
30 30 * 1) Common read/write access. To use this mode, just write to the address of
31 31  
32 32  
33 33  
34 34  
35 35  
36 36  
37 37  
38 38  
... ... @@ -47,37 +47,37 @@
47 47 *
48 48 */
49 49  
50   -#define __mx28_reg_8(name) \
  50 +#define __mxs_reg_8(name) \
51 51 uint8_t name[4]; \
52 52 uint8_t name##_set[4]; \
53 53 uint8_t name##_clr[4]; \
54 54 uint8_t name##_tog[4]; \
55 55  
56   -#define __mx28_reg_32(name) \
  56 +#define __mxs_reg_32(name) \
57 57 uint32_t name; \
58 58 uint32_t name##_set; \
59 59 uint32_t name##_clr; \
60 60 uint32_t name##_tog;
61 61  
62   -struct mx28_register_8 {
63   - __mx28_reg_8(reg)
  62 +struct mxs_register_8 {
  63 + __mxs_reg_8(reg)
64 64 };
65 65  
66   -struct mx28_register_32 {
67   - __mx28_reg_32(reg)
  66 +struct mxs_register_32 {
  67 + __mxs_reg_32(reg)
68 68 };
69 69  
70   -#define mx28_reg_8(name) \
  70 +#define mxs_reg_8(name) \
71 71 union { \
72   - struct { __mx28_reg_8(name) }; \
73   - struct mx28_register_8 name##_reg; \
  72 + struct { __mxs_reg_8(name) }; \
  73 + struct mxs_register_8 name##_reg; \
74 74 };
75 75  
76   -#define mx28_reg_32(name) \
  76 +#define mxs_reg_32(name) \
77 77 union { \
78   - struct { __mx28_reg_32(name) }; \
79   - struct mx28_register_32 name##_reg; \
  78 + struct { __mxs_reg_32(name) }; \
  79 + struct mxs_register_32 name##_reg; \
80 80 };
81 81  
82   -#endif /* __MX28_REGS_COMMON_H__ */
  82 +#endif /* __MXS_REGS_COMMON_H__ */
arch/arm/include/asm/arch-mxs/regs-digctl.h
Diff comments   View file @ ddcf13b
... ... @@ -26,16 +26,16 @@
26 26  
27 27 #ifndef __ASSEMBLY__
28 28 struct mx28_digctl_regs {
29   - mx28_reg_32(hw_digctl_ctrl) /* 0x000 */
30   - mx28_reg_32(hw_digctl_status) /* 0x010 */
31   - mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */
32   - mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */
33   - mx28_reg_32(hw_digctl_emi_status) /* 0x040 */
34   - mx28_reg_32(hw_digctl_read_margin) /* 0x050 */
  29 + mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
  30 + mxs_reg_32(hw_digctl_status) /* 0x010 */
  31 + mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
  32 + mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
  33 + mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
  34 + mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
35 35 uint32_t hw_digctl_writeonce; /* 0x060 */
36 36 uint32_t reserved_writeonce[3];
37   - mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */
38   - mx28_reg_32(hw_digctl_bist_status) /* 0x080 */
  37 + mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
  38 + mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
39 39 uint32_t hw_digctl_entropy; /* 0x090 */
40 40 uint32_t reserved_entropy[3];
41 41 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
... ... @@ -43,7 +43,7 @@
43 43  
44 44 uint32_t reserved1[4];
45 45  
46   - mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */
  46 + mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */
47 47 uint32_t hw_digctl_dbgrd; /* 0x0d0 */
48 48 uint32_t reserved_hw_digctl_dbgrd[3];
49 49 uint32_t hw_digctl_dbg; /* 0x0e0 */
... ... @@ -51,21 +51,21 @@
51 51  
52 52 uint32_t reserved2[4];
53 53  
54   - mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */
55   - mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */
56   - mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */
57   - mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */
58   - mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */
59   - mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */
60   - mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */
61   - mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */
62   - mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */
63   - mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */
64   - mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
65   - mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
66   - mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
67   - mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
68   - mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
  54 + mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */
  55 + mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */
  56 + mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */
  57 + mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */
  58 + mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */
  59 + mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */
  60 + mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */
  61 + mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */
  62 + mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */
  63 + mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */
  64 + mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
  65 + mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
  66 + mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
  67 + mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
  68 + mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
69 69  
70 70 uint32_t reserved3[36];
71 71  
... ... @@ -75,7 +75,7 @@
75 75 uint32_t reserved_hw_digctl_scratch1[3];
76 76 uint32_t hw_digctl_armcache; /* 0x2a0 */
77 77 uint32_t reserved_hw_digctl_armcache[3];
78   - mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
  78 + mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
79 79 uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
80 80 uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
81 81 uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
arch/arm/include/asm/arch-mxs/regs-gpmi.h
Diff comments   View file @ ddcf13b
... ... @@ -30,22 +30,22 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_gpmi_regs {
33   - mx28_reg_32(hw_gpmi_ctrl0)
34   - mx28_reg_32(hw_gpmi_compare)
35   - mx28_reg_32(hw_gpmi_eccctrl)
36   - mx28_reg_32(hw_gpmi_ecccount)
37   - mx28_reg_32(hw_gpmi_payload)
38   - mx28_reg_32(hw_gpmi_auxiliary)
39   - mx28_reg_32(hw_gpmi_ctrl1)
40   - mx28_reg_32(hw_gpmi_timing0)
41   - mx28_reg_32(hw_gpmi_timing1)
  33 + mxs_reg_32(hw_gpmi_ctrl0)
  34 + mxs_reg_32(hw_gpmi_compare)
  35 + mxs_reg_32(hw_gpmi_eccctrl)
  36 + mxs_reg_32(hw_gpmi_ecccount)
  37 + mxs_reg_32(hw_gpmi_payload)
  38 + mxs_reg_32(hw_gpmi_auxiliary)
  39 + mxs_reg_32(hw_gpmi_ctrl1)
  40 + mxs_reg_32(hw_gpmi_timing0)
  41 + mxs_reg_32(hw_gpmi_timing1)
42 42  
43 43 uint32_t reserved[4];
44 44  
45   - mx28_reg_32(hw_gpmi_data)
46   - mx28_reg_32(hw_gpmi_stat)
47   - mx28_reg_32(hw_gpmi_debug)
48   - mx28_reg_32(hw_gpmi_version)
  45 + mxs_reg_32(hw_gpmi_data)
  46 + mxs_reg_32(hw_gpmi_stat)
  47 + mxs_reg_32(hw_gpmi_debug)
  48 + mxs_reg_32(hw_gpmi_version)
49 49 };
50 50 #endif
51 51  
arch/arm/include/asm/arch-mxs/regs-i2c.h
Diff comments   View file @ ddcf13b
... ... @@ -27,20 +27,20 @@
27 27  
28 28 #ifndef __ASSEMBLY__
29 29 struct mx28_i2c_regs {
30   - mx28_reg_32(hw_i2c_ctrl0)
31   - mx28_reg_32(hw_i2c_timing0)
32   - mx28_reg_32(hw_i2c_timing1)
33   - mx28_reg_32(hw_i2c_timing2)
34   - mx28_reg_32(hw_i2c_ctrl1)
35   - mx28_reg_32(hw_i2c_stat)
36   - mx28_reg_32(hw_i2c_queuectrl)
37   - mx28_reg_32(hw_i2c_queuestat)
38   - mx28_reg_32(hw_i2c_queuecmd)
39   - mx28_reg_32(hw_i2c_queuedata)
40   - mx28_reg_32(hw_i2c_data)
41   - mx28_reg_32(hw_i2c_debug0)
42   - mx28_reg_32(hw_i2c_debug1)
43   - mx28_reg_32(hw_i2c_version)
  30 + mxs_reg_32(hw_i2c_ctrl0)
  31 + mxs_reg_32(hw_i2c_timing0)
  32 + mxs_reg_32(hw_i2c_timing1)
  33 + mxs_reg_32(hw_i2c_timing2)
  34 + mxs_reg_32(hw_i2c_ctrl1)
  35 + mxs_reg_32(hw_i2c_stat)
  36 + mxs_reg_32(hw_i2c_queuectrl)
  37 + mxs_reg_32(hw_i2c_queuestat)
  38 + mxs_reg_32(hw_i2c_queuecmd)
  39 + mxs_reg_32(hw_i2c_queuedata)
  40 + mxs_reg_32(hw_i2c_data)
  41 + mxs_reg_32(hw_i2c_debug0)
  42 + mxs_reg_32(hw_i2c_debug1)
  43 + mxs_reg_32(hw_i2c_version)
44 44 };
45 45 #endif
46 46  
arch/arm/include/asm/arch-mxs/regs-lcdif.h
Diff comments   View file @ ddcf13b
... ... @@ -30,38 +30,38 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_lcdif_regs {
33   - mx28_reg_32(hw_lcdif_ctrl) /* 0x00 */
34   - mx28_reg_32(hw_lcdif_ctrl1) /* 0x10 */
35   - mx28_reg_32(hw_lcdif_ctrl2) /* 0x20 */
36   - mx28_reg_32(hw_lcdif_transfer_count) /* 0x30 */
37   - mx28_reg_32(hw_lcdif_cur_buf) /* 0x40 */
38   - mx28_reg_32(hw_lcdif_next_buf) /* 0x50 */
39   - mx28_reg_32(hw_lcdif_timing) /* 0x60 */
40   - mx28_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
41   - mx28_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
42   - mx28_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
43   - mx28_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
44   - mx28_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
45   - mx28_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
46   - mx28_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
47   - mx28_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
48   - mx28_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
49   - mx28_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
50   - mx28_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
51   - mx28_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
52   - mx28_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
53   - mx28_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
54   - mx28_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
55   - mx28_reg_32(hw_lcdif_csc_offset) /* 0x160 */
56   - mx28_reg_32(hw_lcdif_csc_limit) /* 0x170 */
57   - mx28_reg_32(hw_lcdif_data) /* 0x180 */
58   - mx28_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
59   - mx28_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
60   - mx28_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
61   - mx28_reg_32(hw_lcdif_version) /* 0x1c0 */
62   - mx28_reg_32(hw_lcdif_debug0) /* 0x1d0 */
63   - mx28_reg_32(hw_lcdif_debug1) /* 0x1e0 */
64   - mx28_reg_32(hw_lcdif_debug2) /* 0x1f0 */
  33 + mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
  34 + mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
  35 + mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
  36 + mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */
  37 + mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */
  38 + mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */
  39 + mxs_reg_32(hw_lcdif_timing) /* 0x60 */
  40 + mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
  41 + mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
  42 + mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
  43 + mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
  44 + mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
  45 + mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
  46 + mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
  47 + mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
  48 + mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
  49 + mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
  50 + mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
  51 + mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
  52 + mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
  53 + mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
  54 + mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
  55 + mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
  56 + mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
  57 + mxs_reg_32(hw_lcdif_data) /* 0x180 */
  58 + mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
  59 + mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
  60 + mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
  61 + mxs_reg_32(hw_lcdif_version) /* 0x1c0 */
  62 + mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */
  63 + mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */
  64 + mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
65 65 };
66 66 #endif
67 67  
arch/arm/include/asm/arch-mxs/regs-lradc.h
Diff comments   View file @ ddcf13b
... ... @@ -30,30 +30,30 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_lradc_regs {
33   - mx28_reg_32(hw_lradc_ctrl0);
34   - mx28_reg_32(hw_lradc_ctrl1);
35   - mx28_reg_32(hw_lradc_ctrl2);
36   - mx28_reg_32(hw_lradc_ctrl3);
37   - mx28_reg_32(hw_lradc_status);
38   - mx28_reg_32(hw_lradc_ch0);
39   - mx28_reg_32(hw_lradc_ch1);
40   - mx28_reg_32(hw_lradc_ch2);
41   - mx28_reg_32(hw_lradc_ch3);
42   - mx28_reg_32(hw_lradc_ch4);
43   - mx28_reg_32(hw_lradc_ch5);
44   - mx28_reg_32(hw_lradc_ch6);
45   - mx28_reg_32(hw_lradc_ch7);
46   - mx28_reg_32(hw_lradc_delay0);
47   - mx28_reg_32(hw_lradc_delay1);
48   - mx28_reg_32(hw_lradc_delay2);
49   - mx28_reg_32(hw_lradc_delay3);
50   - mx28_reg_32(hw_lradc_debug0);
51   - mx28_reg_32(hw_lradc_debug1);
52   - mx28_reg_32(hw_lradc_conversion);
53   - mx28_reg_32(hw_lradc_ctrl4);
54   - mx28_reg_32(hw_lradc_treshold0);
55   - mx28_reg_32(hw_lradc_treshold1);
56   - mx28_reg_32(hw_lradc_version);
  33 + mxs_reg_32(hw_lradc_ctrl0);
  34 + mxs_reg_32(hw_lradc_ctrl1);
  35 + mxs_reg_32(hw_lradc_ctrl2);
  36 + mxs_reg_32(hw_lradc_ctrl3);
  37 + mxs_reg_32(hw_lradc_status);
  38 + mxs_reg_32(hw_lradc_ch0);
  39 + mxs_reg_32(hw_lradc_ch1);
  40 + mxs_reg_32(hw_lradc_ch2);
  41 + mxs_reg_32(hw_lradc_ch3);
  42 + mxs_reg_32(hw_lradc_ch4);
  43 + mxs_reg_32(hw_lradc_ch5);
  44 + mxs_reg_32(hw_lradc_ch6);
  45 + mxs_reg_32(hw_lradc_ch7);
  46 + mxs_reg_32(hw_lradc_delay0);
  47 + mxs_reg_32(hw_lradc_delay1);
  48 + mxs_reg_32(hw_lradc_delay2);
  49 + mxs_reg_32(hw_lradc_delay3);
  50 + mxs_reg_32(hw_lradc_debug0);
  51 + mxs_reg_32(hw_lradc_debug1);
  52 + mxs_reg_32(hw_lradc_conversion);
  53 + mxs_reg_32(hw_lradc_ctrl4);
  54 + mxs_reg_32(hw_lradc_treshold0);
  55 + mxs_reg_32(hw_lradc_treshold1);
  56 + mxs_reg_32(hw_lradc_version);
57 57 };
58 58 #endif
59 59  
arch/arm/include/asm/arch-mxs/regs-ocotp.h
Diff comments   View file @ ddcf13b
... ... @@ -30,49 +30,49 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_ocotp_regs {
33   - mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */
34   - mx28_reg_32(hw_ocotp_data) /* 0x10 */
35   - mx28_reg_32(hw_ocotp_cust0) /* 0x20 */
36   - mx28_reg_32(hw_ocotp_cust1) /* 0x30 */
37   - mx28_reg_32(hw_ocotp_cust2) /* 0x40 */
38   - mx28_reg_32(hw_ocotp_cust3) /* 0x50 */
39   - mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */
40   - mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */
41   - mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */
42   - mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */
43   - mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
44   - mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
45   - mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
46   - mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
47   - mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
48   - mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
49   - mx28_reg_32(hw_ocotp_swcap) /* 0x100 */
50   - mx28_reg_32(hw_ocotp_custcap) /* 0x110 */
51   - mx28_reg_32(hw_ocotp_lock) /* 0x120 */
52   - mx28_reg_32(hw_ocotp_ops0) /* 0x130 */
53   - mx28_reg_32(hw_ocotp_ops1) /* 0x140 */
54   - mx28_reg_32(hw_ocotp_ops2) /* 0x150 */
55   - mx28_reg_32(hw_ocotp_ops3) /* 0x160 */
56   - mx28_reg_32(hw_ocotp_un0) /* 0x170 */
57   - mx28_reg_32(hw_ocotp_un1) /* 0x180 */
58   - mx28_reg_32(hw_ocotp_un2) /* 0x190 */
59   - mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */
60   - mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */
61   - mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */
62   - mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */
63   - mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */
64   - mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */
65   - mx28_reg_32(hw_ocotp_rom6) /* 0x200 */
66   - mx28_reg_32(hw_ocotp_rom7) /* 0x210 */
67   - mx28_reg_32(hw_ocotp_srk0) /* 0x220 */
68   - mx28_reg_32(hw_ocotp_srk1) /* 0x230 */
69   - mx28_reg_32(hw_ocotp_srk2) /* 0x240 */
70   - mx28_reg_32(hw_ocotp_srk3) /* 0x250 */
71   - mx28_reg_32(hw_ocotp_srk4) /* 0x260 */
72   - mx28_reg_32(hw_ocotp_srk5) /* 0x270 */
73   - mx28_reg_32(hw_ocotp_srk6) /* 0x280 */
74   - mx28_reg_32(hw_ocotp_srk7) /* 0x290 */
75   - mx28_reg_32(hw_ocotp_version) /* 0x2a0 */
  33 + mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */
  34 + mxs_reg_32(hw_ocotp_data) /* 0x10 */
  35 + mxs_reg_32(hw_ocotp_cust0) /* 0x20 */
  36 + mxs_reg_32(hw_ocotp_cust1) /* 0x30 */
  37 + mxs_reg_32(hw_ocotp_cust2) /* 0x40 */
  38 + mxs_reg_32(hw_ocotp_cust3) /* 0x50 */
  39 + mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */
  40 + mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */
  41 + mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */
  42 + mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */
  43 + mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
  44 + mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
  45 + mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
  46 + mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
  47 + mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
  48 + mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
  49 + mxs_reg_32(hw_ocotp_swcap) /* 0x100 */
  50 + mxs_reg_32(hw_ocotp_custcap) /* 0x110 */
  51 + mxs_reg_32(hw_ocotp_lock) /* 0x120 */
  52 + mxs_reg_32(hw_ocotp_ops0) /* 0x130 */
  53 + mxs_reg_32(hw_ocotp_ops1) /* 0x140 */
  54 + mxs_reg_32(hw_ocotp_ops2) /* 0x150 */
  55 + mxs_reg_32(hw_ocotp_ops3) /* 0x160 */
  56 + mxs_reg_32(hw_ocotp_un0) /* 0x170 */
  57 + mxs_reg_32(hw_ocotp_un1) /* 0x180 */
  58 + mxs_reg_32(hw_ocotp_un2) /* 0x190 */
  59 + mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */
  60 + mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */
  61 + mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */
  62 + mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */
  63 + mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */
  64 + mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */
  65 + mxs_reg_32(hw_ocotp_rom6) /* 0x200 */
  66 + mxs_reg_32(hw_ocotp_rom7) /* 0x210 */
  67 + mxs_reg_32(hw_ocotp_srk0) /* 0x220 */
  68 + mxs_reg_32(hw_ocotp_srk1) /* 0x230 */
  69 + mxs_reg_32(hw_ocotp_srk2) /* 0x240 */
  70 + mxs_reg_32(hw_ocotp_srk3) /* 0x250 */
  71 + mxs_reg_32(hw_ocotp_srk4) /* 0x260 */
  72 + mxs_reg_32(hw_ocotp_srk5) /* 0x270 */
  73 + mxs_reg_32(hw_ocotp_srk6) /* 0x280 */
  74 + mxs_reg_32(hw_ocotp_srk7) /* 0x290 */
  75 + mxs_reg_32(hw_ocotp_version) /* 0x2a0 */
76 76 };
77 77 #endif
78 78  
arch/arm/include/asm/arch-mxs/regs-pinctrl.h
Diff comments   View file @ ddcf13b
... ... @@ -30,129 +30,129 @@
30 30  
31 31 #ifndef __ASSEMBLY__
32 32 struct mx28_pinctrl_regs {
33   - mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */
  33 + mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */
34 34  
35 35 uint32_t reserved1[60];
36 36  
37   - mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
38   - mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
39   - mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
40   - mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
41   - mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
42   - mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
43   - mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
44   - mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
45   - mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
46   - mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
47   - mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
48   - mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
49   - mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
50   - mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
  37 + mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
  38 + mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
  39 + mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
  40 + mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
  41 + mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
  42 + mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
  43 + mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
  44 + mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
  45 + mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
  46 + mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
  47 + mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
  48 + mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
  49 + mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
  50 + mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
51 51  
52 52 uint32_t reserved2[72];
53 53  
54   - mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */
55   - mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */
56   - mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */
57   - mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */
58   - mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */
59   - mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */
60   - mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */
61   - mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */
62   - mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */
63   - mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */
64   - mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
65   - mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
66   - mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
67   - mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
68   - mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
69   - mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
70   - mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */
71   - mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */
72   - mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */
73   - mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */
  54 + mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */
  55 + mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */
  56 + mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */
  57 + mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */
  58 + mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */
  59 + mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */
  60 + mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */
  61 + mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */
  62 + mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */
  63 + mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */
  64 + mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
  65 + mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
  66 + mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
  67 + mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
  68 + mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
  69 + mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
  70 + mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */
  71 + mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */
  72 + mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */
  73 + mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */
74 74  
75 75 uint32_t reserved3[112];
76 76  
77   - mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */
78   - mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */
79   - mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */
80   - mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */
81   - mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */
82   - mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */
83   - mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */
  77 + mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */
  78 + mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */
  79 + mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */
  80 + mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */
  81 + mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */
  82 + mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */
  83 + mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */
84 84  
85 85 uint32_t reserved4[36];
86 86  
87   - mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */
88   - mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */
89   - mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */
90   - mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */
91   - mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */
  87 + mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */
  88 + mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */
  89 + mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */
  90 + mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */
  91 + mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */
92 92  
93 93 uint32_t reserved5[108];
94 94  
95   - mx28_reg_32(hw_pinctrl_din0) /* 0x900 */
96   - mx28_reg_32(hw_pinctrl_din1) /* 0x910 */
97   - mx28_reg_32(hw_pinctrl_din2) /* 0x920 */
98   - mx28_reg_32(hw_pinctrl_din3) /* 0x930 */
99   - mx28_reg_32(hw_pinctrl_din4) /* 0x940 */
  95 + mxs_reg_32(hw_pinctrl_din0) /* 0x900 */
  96 + mxs_reg_32(hw_pinctrl_din1) /* 0x910 */
  97 + mxs_reg_32(hw_pinctrl_din2) /* 0x920 */
  98 + mxs_reg_32(hw_pinctrl_din3) /* 0x930 */
  99 + mxs_reg_32(hw_pinctrl_din4) /* 0x940 */
100 100  
101 101 uint32_t reserved6[108];
102 102  
103   - mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */
104   - mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */
105   - mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */
106   - mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */
107   - mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */
  103 + mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */
  104 + mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */
  105 + mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */
  106 + mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */
  107 + mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */
108 108  
109 109 uint32_t reserved7[300];
110 110  
111   - mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
112   - mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
113   - mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
114   - mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
115   - mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
  111 + mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
  112 + mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
  113 + mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
  114 + mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
  115 + mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
116 116  
117 117 uint32_t reserved8[44];
118 118  
119   - mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
120   - mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
121   - mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
122   - mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
123   - mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
  119 + mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
  120 + mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
  121 + mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
  122 + mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
  123 + mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
124 124  
125 125 uint32_t reserved9[44];
126 126  
127   - mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
128   - mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
129   - mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
130   - mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
131   - mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
  127 + mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
  128 + mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
  129 + mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
  130 + mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
  131 + mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
132 132  
133 133 uint32_t reserved10[44];
134 134  
135   - mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
136   - mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
137   - mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
138   - mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
139   - mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
  135 + mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
  136 + mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
  137 + mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
  138 + mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
  139 + mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
140 140  
141 141 uint32_t reserved11[44];
142 142  
143   - mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
144   - mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
145   - mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
146   - mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
147   - mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
  143 + mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
  144 + mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
  145 + mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
  146 + mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
  147 + mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
148 148  
149 149 uint32_t reserved12[380];
150 150  
151   - mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
  151 + mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
152 152  
153 153 uint32_t reserved13[76];
154 154  
155   - mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
  155 + mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
156 156 };
157 157 #endif
158 158  
arch/arm/include/asm/arch-mxs/regs-power.h
Diff comments   View file @ ddcf13b
... ... @@ -26,10 +26,10 @@
26 26  
27 27 #ifndef __ASSEMBLY__
28 28 struct mx28_power_regs {
29   - mx28_reg_32(hw_power_ctrl)
30   - mx28_reg_32(hw_power_5vctrl)
31   - mx28_reg_32(hw_power_minpwr)
32   - mx28_reg_32(hw_power_charge)
  29 + mxs_reg_32(hw_power_ctrl)
  30 + mxs_reg_32(hw_power_5vctrl)
  31 + mxs_reg_32(hw_power_minpwr)
  32 + mxs_reg_32(hw_power_charge)
33 33 uint32_t hw_power_vdddctrl;
34 34 uint32_t reserved_vddd[3];
35 35 uint32_t hw_power_vddactrl;
36 36  
37 37  
... ... @@ -44,23 +44,23 @@
44 44 uint32_t reserved_misc[3];
45 45 uint32_t hw_power_dclimits;
46 46 uint32_t reserved_dclimits[3];
47   - mx28_reg_32(hw_power_loopctrl)
  47 + mxs_reg_32(hw_power_loopctrl)
48 48 uint32_t hw_power_sts;
49 49 uint32_t reserved_sts[3];
50   - mx28_reg_32(hw_power_speed)
  50 + mxs_reg_32(hw_power_speed)
51 51 uint32_t hw_power_battmonitor;
52 52 uint32_t reserved_battmonitor[3];
53 53  
54 54 uint32_t reserved[4];
55 55  
56   - mx28_reg_32(hw_power_reset)
57   - mx28_reg_32(hw_power_debug)
58   - mx28_reg_32(hw_power_thermal)
59   - mx28_reg_32(hw_power_usb1ctrl)
60   - mx28_reg_32(hw_power_special)
61   - mx28_reg_32(hw_power_version)
62   - mx28_reg_32(hw_power_anaclkctrl)
63   - mx28_reg_32(hw_power_refctrl)
  56 + mxs_reg_32(hw_power_reset)
  57 + mxs_reg_32(hw_power_debug)
  58 + mxs_reg_32(hw_power_thermal)
  59 + mxs_reg_32(hw_power_usb1ctrl)
  60 + mxs_reg_32(hw_power_special)
  61 + mxs_reg_32(hw_power_version)
  62 + mxs_reg_32(hw_power_anaclkctrl)
  63 + mxs_reg_32(hw_power_refctrl)
64 64 };
65 65 #endif
66 66  
arch/arm/include/asm/arch-mxs/regs-rtc.h
Diff comments   View file @ ddcf13b
... ... @@ -27,20 +27,20 @@
27 27  
28 28 #ifndef __ASSEMBLY__
29 29 struct mx28_rtc_regs {
30   - mx28_reg_32(hw_rtc_ctrl)
31   - mx28_reg_32(hw_rtc_stat)
32   - mx28_reg_32(hw_rtc_milliseconds)
33   - mx28_reg_32(hw_rtc_seconds)
34   - mx28_reg_32(hw_rtc_rtc_alarm)
35   - mx28_reg_32(hw_rtc_watchdog)
36   - mx28_reg_32(hw_rtc_persistent0)
37   - mx28_reg_32(hw_rtc_persistent1)
38   - mx28_reg_32(hw_rtc_persistent2)
39   - mx28_reg_32(hw_rtc_persistent3)
40   - mx28_reg_32(hw_rtc_persistent4)
41   - mx28_reg_32(hw_rtc_persistent5)
42   - mx28_reg_32(hw_rtc_debug)
43   - mx28_reg_32(hw_rtc_version)
  30 + mxs_reg_32(hw_rtc_ctrl)
  31 + mxs_reg_32(hw_rtc_stat)
  32 + mxs_reg_32(hw_rtc_milliseconds)
  33 + mxs_reg_32(hw_rtc_seconds)
  34 + mxs_reg_32(hw_rtc_rtc_alarm)
  35 + mxs_reg_32(hw_rtc_watchdog)
  36 + mxs_reg_32(hw_rtc_persistent0)
  37 + mxs_reg_32(hw_rtc_persistent1)
  38 + mxs_reg_32(hw_rtc_persistent2)
  39 + mxs_reg_32(hw_rtc_persistent3)
  40 + mxs_reg_32(hw_rtc_persistent4)
  41 + mxs_reg_32(hw_rtc_persistent5)
  42 + mxs_reg_32(hw_rtc_debug)
  43 + mxs_reg_32(hw_rtc_version)
44 44 };
45 45 #endif
46 46  
arch/arm/include/asm/arch-mxs/regs-ssp.h
Diff comments   View file @ ddcf13b
... ... @@ -29,26 +29,26 @@
29 29  
30 30 #ifndef __ASSEMBLY__
31 31 struct mx28_ssp_regs {
32   - mx28_reg_32(hw_ssp_ctrl0)
33   - mx28_reg_32(hw_ssp_cmd0)
34   - mx28_reg_32(hw_ssp_cmd1)
35   - mx28_reg_32(hw_ssp_xfer_size)
36   - mx28_reg_32(hw_ssp_block_size)
37   - mx28_reg_32(hw_ssp_compref)
38   - mx28_reg_32(hw_ssp_compmask)
39   - mx28_reg_32(hw_ssp_timing)
40   - mx28_reg_32(hw_ssp_ctrl1)
41   - mx28_reg_32(hw_ssp_data)
42   - mx28_reg_32(hw_ssp_sdresp0)
43   - mx28_reg_32(hw_ssp_sdresp1)
44   - mx28_reg_32(hw_ssp_sdresp2)
45   - mx28_reg_32(hw_ssp_sdresp3)
46   - mx28_reg_32(hw_ssp_ddr_ctrl)
47   - mx28_reg_32(hw_ssp_dll_ctrl)
48   - mx28_reg_32(hw_ssp_status)
49   - mx28_reg_32(hw_ssp_dll_sts)
50   - mx28_reg_32(hw_ssp_debug)
51   - mx28_reg_32(hw_ssp_version)
  32 + mxs_reg_32(hw_ssp_ctrl0)
  33 + mxs_reg_32(hw_ssp_cmd0)
  34 + mxs_reg_32(hw_ssp_cmd1)
  35 + mxs_reg_32(hw_ssp_xfer_size)
  36 + mxs_reg_32(hw_ssp_block_size)
  37 + mxs_reg_32(hw_ssp_compref)
  38 + mxs_reg_32(hw_ssp_compmask)
  39 + mxs_reg_32(hw_ssp_timing)
  40 + mxs_reg_32(hw_ssp_ctrl1)
  41 + mxs_reg_32(hw_ssp_data)
  42 + mxs_reg_32(hw_ssp_sdresp0)
  43 + mxs_reg_32(hw_ssp_sdresp1)
  44 + mxs_reg_32(hw_ssp_sdresp2)
  45 + mxs_reg_32(hw_ssp_sdresp3)
  46 + mxs_reg_32(hw_ssp_ddr_ctrl)
  47 + mxs_reg_32(hw_ssp_dll_ctrl)
  48 + mxs_reg_32(hw_ssp_status)
  49 + mxs_reg_32(hw_ssp_dll_sts)
  50 + mxs_reg_32(hw_ssp_debug)
  51 + mxs_reg_32(hw_ssp_version)
52 52 };
53 53 #endif
54 54  
arch/arm/include/asm/arch-mxs/regs-timrot.h
Diff comments   View file @ ddcf13b
... ... @@ -29,25 +29,25 @@
29 29  
30 30 #ifndef __ASSEMBLY__
31 31 struct mx28_timrot_regs {
32   - mx28_reg_32(hw_timrot_rotctrl)
33   - mx28_reg_32(hw_timrot_rotcount)
34   - mx28_reg_32(hw_timrot_timctrl0)
35   - mx28_reg_32(hw_timrot_running_count0)
36   - mx28_reg_32(hw_timrot_fixed_count0)
37   - mx28_reg_32(hw_timrot_match_count0)
38   - mx28_reg_32(hw_timrot_timctrl1)
39   - mx28_reg_32(hw_timrot_running_count1)
40   - mx28_reg_32(hw_timrot_fixed_count1)
41   - mx28_reg_32(hw_timrot_match_count1)
42   - mx28_reg_32(hw_timrot_timctrl2)
43   - mx28_reg_32(hw_timrot_running_count2)
44   - mx28_reg_32(hw_timrot_fixed_count2)
45   - mx28_reg_32(hw_timrot_match_count2)
46   - mx28_reg_32(hw_timrot_timctrl3)
47   - mx28_reg_32(hw_timrot_running_count3)
48   - mx28_reg_32(hw_timrot_fixed_count3)
49   - mx28_reg_32(hw_timrot_match_count3)
50   - mx28_reg_32(hw_timrot_version)
  32 + mxs_reg_32(hw_timrot_rotctrl)
  33 + mxs_reg_32(hw_timrot_rotcount)
  34 + mxs_reg_32(hw_timrot_timctrl0)
  35 + mxs_reg_32(hw_timrot_running_count0)
  36 + mxs_reg_32(hw_timrot_fixed_count0)
  37 + mxs_reg_32(hw_timrot_match_count0)
  38 + mxs_reg_32(hw_timrot_timctrl1)
  39 + mxs_reg_32(hw_timrot_running_count1)
  40 + mxs_reg_32(hw_timrot_fixed_count1)
  41 + mxs_reg_32(hw_timrot_match_count1)
  42 + mxs_reg_32(hw_timrot_timctrl2)
  43 + mxs_reg_32(hw_timrot_running_count2)
  44 + mxs_reg_32(hw_timrot_fixed_count2)
  45 + mxs_reg_32(hw_timrot_match_count2)
  46 + mxs_reg_32(hw_timrot_timctrl3)
  47 + mxs_reg_32(hw_timrot_running_count3)
  48 + mxs_reg_32(hw_timrot_fixed_count3)
  49 + mxs_reg_32(hw_timrot_match_count3)
  50 + mxs_reg_32(hw_timrot_version)
51 51 };
52 52 #endif
53 53  
arch/arm/include/asm/arch-mxs/regs-usbphy.h
Diff comments   View file @ ddcf13b
... ... @@ -24,16 +24,16 @@
24 24 #define __REGS_USBPHY_H__
25 25  
26 26 struct mx28_usbphy_regs {
27   - mx28_reg_32(hw_usbphy_pwd)
28   - mx28_reg_32(hw_usbphy_tx)
29   - mx28_reg_32(hw_usbphy_rx)
30   - mx28_reg_32(hw_usbphy_ctrl)
31   - mx28_reg_32(hw_usbphy_status)
32   - mx28_reg_32(hw_usbphy_debug)
33   - mx28_reg_32(hw_usbphy_debug0_status)
34   - mx28_reg_32(hw_usbphy_debug1)
35   - mx28_reg_32(hw_usbphy_version)
36   - mx28_reg_32(hw_usbphy_ip)
  27 + mxs_reg_32(hw_usbphy_pwd)
  28 + mxs_reg_32(hw_usbphy_tx)
  29 + mxs_reg_32(hw_usbphy_rx)
  30 + mxs_reg_32(hw_usbphy_ctrl)
  31 + mxs_reg_32(hw_usbphy_status)
  32 + mxs_reg_32(hw_usbphy_debug)
  33 + mxs_reg_32(hw_usbphy_debug0_status)
  34 + mxs_reg_32(hw_usbphy_debug1)
  35 + mxs_reg_32(hw_usbphy_version)
  36 + mxs_reg_32(hw_usbphy_ip)
37 37 };
38 38  
39 39 #define USBPHY_PWD_RXPWDRX (1 << 20)
arch/arm/include/asm/arch-mxs/sys_proto.h
Diff comments   View file @ ddcf13b
... ... @@ -23,11 +23,11 @@
23 23 #ifndef __MX28_H__
24 24 #define __MX28_H__
25 25  
26   -int mx28_reset_block(struct mx28_register_32 *reg);
27   -int mx28_wait_mask_set(struct mx28_register_32 *reg,
  26 +int mx28_reset_block(struct mxs_register_32 *reg);
  27 +int mx28_wait_mask_set(struct mxs_register_32 *reg,
28 28 uint32_t mask,
29 29 int timeout);
30   -int mx28_wait_mask_clr(struct mx28_register_32 *reg,
  30 +int mx28_wait_mask_clr(struct mxs_register_32 *reg,
31 31 uint32_t mask,
32 32 int timeout);
33 33  
drivers/gpio/mxs_gpio.c
Diff comments   View file @ ddcf13b
... ... @@ -73,8 +73,8 @@
73 73 {
74 74 uint32_t bank = PAD_BANK(gpio);
75 75 uint32_t offset = PINCTRL_DIN(bank);
76   - struct mx28_register_32 *reg =
77   - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
  76 + struct mxs_register_32 *reg =
  77 + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
78 78  
79 79 return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
80 80 }
... ... @@ -83,8 +83,8 @@
83 83 {
84 84 uint32_t bank = PAD_BANK(gpio);
85 85 uint32_t offset = PINCTRL_DOUT(bank);
86   - struct mx28_register_32 *reg =
87   - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
  86 + struct mxs_register_32 *reg =
  87 + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
88 88  
89 89 if (value)
90 90 writel(1 << PAD_PIN(gpio), &reg->reg_set);
... ... @@ -96,8 +96,8 @@
96 96 {
97 97 uint32_t bank = PAD_BANK(gpio);
98 98 uint32_t offset = PINCTRL_DOE(bank);
99   - struct mx28_register_32 *reg =
100   - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
  99 + struct mxs_register_32 *reg =
  100 + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
101 101  
102 102 writel(1 << PAD_PIN(gpio), &reg->reg_clr);
103 103  
... ... @@ -108,8 +108,8 @@
108 108 {
109 109 uint32_t bank = PAD_BANK(gpio);
110 110 uint32_t offset = PINCTRL_DOE(bank);
111   - struct mx28_register_32 *reg =
112   - (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
  111 + struct mxs_register_32 *reg =
  112 + (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
113 113  
114 114 writel(1 << PAD_PIN(gpio), &reg->reg_set);
115 115  
drivers/usb/host/ehci-mxs.c
Diff comments   View file @ ddcf13b
... ... @@ -75,8 +75,8 @@
75 75  
76 76 int ret;
77 77 uint32_t usb_base, cap_base;
78   - struct mx28_register_32 *digctl_ctrl =
79   - (struct mx28_register_32 *)HW_DIGCTL_CTRL;
  78 + struct mxs_register_32 *digctl_ctrl =
  79 + (struct mxs_register_32 *)HW_DIGCTL_CTRL;
80 80 struct mx28_clkctrl_regs *clkctrl_regs =
81 81 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
82 82  
... ... @@ -119,8 +119,8 @@
119 119 {
120 120 int ret;
121 121 uint32_t tmp;
122   - struct mx28_register_32 *digctl_ctrl =
123   - (struct mx28_register_32 *)HW_DIGCTL_CTRL;
  122 + struct mxs_register_32 *digctl_ctrl =
  123 + (struct mxs_register_32 *)HW_DIGCTL_CTRL;
124 124 struct mx28_clkctrl_regs *clkctrl_regs =
125 125 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
126 126