From e29075cdf5360ea560e394c7998dfd6a599cc714 Mon Sep 17 00:00:00 2001 From: Eric Lee Date: Thu, 5 Mar 2015 17:50:54 +0800 Subject: [PATCH] Add SMARC-FiMX6 Solo/DualLite/Dual/Quad Core Initial Supports --- arch/arm/imx-common/cpu.c | 3 - arch/arm/include/asm/imx-common/video.h | 29 + arch/arm/include/asm/mach-types.h | 13 + board/embedian/smarcfimx6/Makefile | 13 + board/embedian/smarcfimx6/README | 50 + .../smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg | 195 +++ .../embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg | 206 +++ .../embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg | 204 +++ .../smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg | 195 +++ board/embedian/smarcfimx6/plugin.S | 480 +++++++ board/embedian/smarcfimx6/smarcfimx6.c | 1411 ++++++++++++++++++++ board/embedian/smarcfimx6/smarcfimx6.h | 139 ++ boards.cfg | 21 + drivers/i2c/i2c_core.c | 5 + drivers/mmc/mmc.c | 7 +- drivers/mtd/spi/sf_params.c | 1 + include/configs/smarcfimx6.h | 115 ++ include/configs/smarcfimx6_common.h | 471 +++++++ include/i2c.h | 2 + include/mmc.h | 1 + 20 files changed, 3556 insertions(+), 5 deletions(-) create mode 100644 arch/arm/include/asm/imx-common/video.h create mode 100644 board/embedian/smarcfimx6/Makefile create mode 100644 board/embedian/smarcfimx6/README create mode 100644 board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg create mode 100644 board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg create mode 100644 board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg create mode 100644 board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg create mode 100644 board/embedian/smarcfimx6/plugin.S create mode 100644 board/embedian/smarcfimx6/smarcfimx6.c create mode 100644 board/embedian/smarcfimx6/smarcfimx6.h create mode 100644 include/configs/smarcfimx6.h create mode 100644 include/configs/smarcfimx6_common.h diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 8427eb7..2b9fbbb 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -199,9 +199,6 @@ u32 get_ahb_clk(void) void arch_preboot_os(void) { -#if defined(CONFIG_LDO_BYPASS_CHECK) - ldo_mode_set(check_ldo_bypass()); -#endif #if defined(CONFIG_VIDEO_IPUV3) /* disable video before launching O/S */ ipuv3_fb_shutdown(); diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h new file mode 100644 index 0000000..1a907d4 --- /dev/null +++ b/arch/arm/include/asm/imx-common/video.h @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_VIDEO_H_ +#define __IMX_VIDEO_H_ + +#include +#include + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +#ifdef CONFIG_IMX_HDMI +extern int detect_hdmi(struct display_info_t const *dev); +#endif + +#ifdef CONFIG_IMX_VIDEO_SKIP +extern struct display_info_t const displays[]; +extern size_t display_count; +#endif + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..d870428 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 +#define MACH_TYPE_SMARCFIMX6 3990 #define MACH_TYPE_KZM9G 4140 #ifdef CONFIG_ARCH_EBSA110 @@ -3627,6 +3628,18 @@ extern unsigned int __machine_arch_type; # define machine_is_armadillo5x0() (0) #endif +#ifdef CONFIG_MACH_SMARCFIMX6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARCFIMX6 +# endif +# define machine_is_smarcfimx6() (machine_arch_type == MACH_TYPE_SMARCFIMX6) +#else +# define machine_is_smarcfimx6() (0) +#endif + #ifdef CONFIG_MACH_CC9P9360JS # ifdef machine_arch_type # undef machine_arch_type diff --git a/board/embedian/smarcfimx6/Makefile b/board/embedian/smarcfimx6/Makefile new file mode 100644 index 0000000..8ee747d --- /dev/null +++ b/board/embedian/smarcfimx6/Makefile @@ -0,0 +1,13 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := smarcfimx6.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/embedian/smarcfimx6/README b/board/embedian/smarcfimx6/README new file mode 100644 index 0000000..aa4ad34 --- /dev/null +++ b/board/embedian/smarcfimx6/README @@ -0,0 +1,50 @@ +U-Boot for SMARC-FIMX6 +-------------------- + +This file contains information for the port of U-Boot to the Embedian SMARC-FiMX6. + +SMARC-FiMX6 is a computer on module that has six variants based on the following +SoCs and memory configurations: mx6 quad 2G, mx6 quad 1G, mx6 dual 2G, mx6 dual 1G, mx6 dual lite and mx6 solo. + +For more details about SMARC-FiMX6, please refer to: +http://www.embedian.com/ + +Building U-boot for SMARC-FiMX6 +----------------------------- + +To build U-Boot for the SMARC-FiMX6 Dual Lite version: + +$ make smarcfimx6_dl_1g_ser3_config +$ make + +To build U-Boot for the SMARC-FiMX6 Solo version: + +$ make smarcfimx6_solo_ser3_config +$ make + +To build U-Boot for the SMARC-FiMX6 Quad and Dual 1G memory version: + +$ make smarcfimx6_quad_1g_ser3_config +$ make + +To build U-Boot for the SMARC-FiMX6 Quad and Dual 2G memory version: + +$ make smarcfimx6_quad_2g_ser3_config +$ make + +Flashing U-boot into the SD card +-------------------------------- + +- After the 'make' command completes, the generated 'u-boot.imx' binary must be +flashed into the SD card; + +$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync + +(Note - the SD card node may vary, so adjust this as needed). + +- Insert the SD card into the slot located in the bottom of the board (same side +as the mx6 processor) + +- Connect the serial cable to the host PC + +- Power up the board and U-boot messages will appear in the serial console. diff --git a/board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg b/board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg new file mode 100644 index 0000000..ea06311 --- /dev/null +++ b/board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + */ + +/* the same flash_offset as sd */ +BOOT_FROM spi + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +/* Enable all clocks */ +/*DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff*/ + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 + +/* CLOCK */ +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 + +/* ADDRESS */ +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 + +/* CONTROL */ +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 + +/* DATA STROBE */ +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 + +/* DATA */ +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4 0x021b0800 0xa1390003 +/* write leveling */ +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x42540258 +DATA 4 0x021b0840 0x023C023C +DATA 4 0x021b483c 0x42400244 +DATA 4 0x021b4840 0x0230023C + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x4446484A +DATA 4 0x021b4848 0x4A4E5044 + +DATA 4 0x021b0850 0x36322E34 +DATA 4 0x021b4850 0x383A3830 + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +/* MMDC init */ +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00335050 +DATA 4 0x021b000c 0x3F435333 +DATA 4 0x021b0010 0xB68E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00081740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +/* Initialize CS0: K4B2G1646Q-BCK0 */ +/* MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 +/*MDREF*/ +DATA 4 0x021b0020 0x00005800 + +/* final DDR setup, before operation start */ +DATA 4 0x021b0818 0x00011117 +/*DATA 4 0x021b4818 0x00011117*/ +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg b/board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg new file mode 100644 index 0000000..5fc217e --- /dev/null +++ b/board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + */ + +/* the same flash_offset as sd */ +BOOT_FROM spi + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +/* Enable all clocks */ +/*DATA 4, 0x020c4068, 0xffffffff +DATA 4, 0x020c406c, 0xffffffff +DATA 4, 0x020c4070, 0xffffffff +DATA 4, 0x020c4074, 0xffffffff +DATA 4, 0x020c4078, 0xffffffff +DATA 4, 0x020c407c, 0xffffffff +DATA 4, 0x020c4080, 0xffffffff +DATA 4, 0x020c4084, 0xffffffff*/ + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4, 0x020e0798, 0x000C0000 +DATA 4, 0x020e0758, 0x00000000 + +/* CLOCK */ +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 + +/* ADDRESS */ +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +/* CONTROL */ +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 + +/* DATA STROBE */ +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 +/* DATA */ +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4, 0x021b0800, 0xa1390003 +/* write leveling */ +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b480c, 0x001F001F +DATA 4, 0x021b4810, 0x001F001F + +/* DQS Read Gate */ +DATA 4, 0x021b083c, 0x4544055C +DATA 4, 0x021b0840, 0x05400540 +DATA 4, 0x021b483c, 0x4544054C +DATA 4, 0x021b4840, 0x05440510 + +/* Read/Write Delay */ +DATA 4, 0x021b0848, 0x463C3E42 +DATA 4, 0x021b4848, 0x3E3A3844 + +DATA 4, 0x021b0850, 0x38383E38 +DATA 4, 0x021b4850, 0x42344838 + +/* read data bit delay */ +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 + +/* MMDC init */ +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x09446060 +DATA 4, 0x021b000c, 0x555B79A4 +DATA 4, 0x021b0010, 0xDB538F64 +DATA 4, 0x021b0014, 0x01FF00DD +DATA 4, 0x021b0018, 0x00081740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x005B1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x11420000 +DATA 4, 0x021b4400, 0x11420000 +DATA 4, 0x021b0000, 0x831A0000 + +/* Initialize CS0: K4B2G1646Q-BCK0 */ +/* MR2 */ +DATA 4, 0x021b001c, 0x04088032 +/* MR3 */ +DATA 4, 0x021b001c, 0x00008033 +/* MR1 */ +DATA 4, 0x021b001c, 0x00048031 +/* MR0 */ +DATA 4, 0x021b001c, 0x09408030 +/* DDR device ZQ calibration */ +DATA 4, 0x021b001c, 0x04008040 +/*MDREF*/ +DATA 4, 0x021b0020, 0x00005800 + +/* final DDR setup, before operation start */ +DATA 4, 0x021b0818, 0x00011117 +/*DATA 4, 0x021b4818, 0x00011117*/ +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, 0x020c4060, 0x000000fb +#endif diff --git a/board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg b/board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg new file mode 100644 index 0000000..80beae9 --- /dev/null +++ b/board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + */ + +/* the same flash_offset as sd */ +BOOT_FROM spi + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +/* Enable all clocks */ +/*DATA 4, 0x020c4068, 0xffffffff +DATA 4, 0x020c406c, 0xffffffff +DATA 4, 0x020c4070, 0xffffffff +DATA 4, 0x020c4074, 0xffffffff +DATA 4, 0x020c4078, 0xffffffff +DATA 4, 0x020c407c, 0xffffffff +DATA 4, 0x020c4080, 0xffffffff +DATA 4, 0x020c4084, 0xffffffff*/ + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4, 0x020e0798, 0x000C0000 +DATA 4, 0x020e0758, 0x00000000 + +/* CLOCK */ +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 + +/* ADDRESS */ +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +/* CONTROL */ +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 + +/* DATA STROBE */ +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 +/* DATA */ +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4, 0x021b0800, 0xa1390003 +/* write leveling */ +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b480c, 0x001F001F +DATA 4, 0x021b4810, 0x001F001F + +/* DQS Read Gate */ +DATA 4, 0x021b083c, 0x45400554 +DATA 4, 0x021b0840, 0x0534052C +DATA 4, 0x021b483c, 0x453C0548 +DATA 4, 0x021b4840, 0x053C050C + +/* Read/Write Delay */ +DATA 4, 0x021b0848, 0x463E3E40 +DATA 4, 0x021b4848, 0x3E3C3846 + +DATA 4, 0x021b0850, 0x36383C36 +DATA 4, 0x021b4850, 0x4234443C + +/* read data bit delay */ +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 + +/* MMDC init */ +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x09446060 +DATA 4, 0x021b000c, 0x8A907BA4 +DATA 4, 0x021b0010, 0xDB538F64 +DATA 4, 0x021b0014, 0x01FF00DD +DATA 4, 0x021b0018, 0x00081740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x00901023 +DATA 4, 0x021b0040, 0x00000047 +DATA 4, 0x021b0000, 0x841A0000 + +/* Initialize CS0: K4B2G1646Q-BCK0 */ +/* MR2 */ +DATA 4, 0x021b001c, 0x04088032 +/* MR3 */ +DATA 4, 0x021b001c, 0x00008033 +/* MR1 */ +DATA 4, 0x021b001c, 0x00048031 +/* MR0 */ +DATA 4, 0x021b001c, 0x09408030 +/* DDR device ZQ calibration */ +DATA 4, 0x021b001c, 0x04008040 +/*MDREF*/ +DATA 4, 0x021b0020, 0x00005800 + +/* final DDR setup, before operation start */ +DATA 4, 0x021b0818, 0x00011117 +/*DATA 4, 0x021b4818, 0x00011117*/ +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, 0x020c4060, 0x000000fb +#endif diff --git a/board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg b/board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg new file mode 100644 index 0000000..9b45fca --- /dev/null +++ b/board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + */ + +/* the same flash_offset as sd */ +BOOT_FROM spi + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/embedian/smarcfimx6/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +/* Enable all clocks */ +/*DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff*/ + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 + +/* CLOCK */ +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 + +/* ADDRESS */ +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 + +/* CONTROL */ +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 + +/* DATA STROBE */ +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 + +/* DATA */ +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4 0x021b0800 0xa1390003 +/* write leveling */ +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x42640264 +DATA 4 0x021b0840 0x02400250 +DATA 4 0x021b483c 0x42640264 +DATA 4 0x021b4840 0x02400250 + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x44484A4C +DATA 4 0x021b4848 0x44484A4C + +DATA 4 0x021b0850 0x3C383434 +DATA 4 0x021b4850 0x3C383434 + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +/* MMDC init */ +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00335050 +DATA 4 0x021b000c 0x3F435333 +DATA 4 0x021b0010 0xB68E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00081740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000017 +DATA 4 0x021b0000 0x83190000 + +/* Initialize CS0: K4B2G1646Q-BCK0 */ +/* MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 +/*MDREF*/ +DATA 4 0x021b0020 0x00005800 + +/* final DDR setup, before operation start */ +DATA 4 0x021b0818 0x00011117 +/*DATA 4 0x021b4818 0x00011117*/ +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/embedian/smarcfimx6/plugin.S b/board/embedian/smarcfimx6/plugin.S new file mode 100644 index 0000000..26c576a --- /dev/null +++ b/board/embedian/smarcfimx6/plugin.S @@ -0,0 +1,480 @@ +/* + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro smarcfimx6_quad_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43270338 + str r2, [r0, #0x83c] + ldr r2, =0x03200314 + str r2, [r0, #0x840] + + ldr r2, =0x431A032F + str r2, [r1, #0x83c] + ldr r2, =0x03200263 + str r2, [r1, #0x840] + + ldr r2, =0x4B434748 + str r2, [r0, #0x848] + ldr r2, =0x4445404C + str r2, [r1, #0x848] + + ldr r2, =0x38444542 + str r2, [r0, #0x850] + ldr r2, =0x4935493A + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro smarcfimx6_dl__ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x4220021F + str r2, [r0, #0x83c] + ldr r2, =0x0207017E + str r2, [r0, #0x840] + + ldr r2, =0x4201020C + str r2, [r1, #0x83c] + ldr r2, =0x01660172 + str r2, [r1, #0x840] + + ldr r2, =0x4A4D4E4D + str r2, [r0, #0x848] + ldr r2, =0x4A4F5049 + str r2, [r1, #0x848] + + ldr r2, =0x3F3C3D31 + str r2, [r0, #0x850] + ldr r2, =0x3238372B + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro smarcfimx6_solo_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x42190219 + str r2, [r0, #0x83c] + ldr r2, =0x017B0177 + str r2, [r0, #0x840] + + ldr r2, =0x4B4D4E4D + str r2, [r0, #0x848] + + ldr r2, =0x3F3E2D36 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000017 + str r2, [r0, #0x040] + + ldr r2, =0x83190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFC000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0x00FFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x000003FF + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6SOLO) + smarcfimx6_solo_ddr_setting +#elif defined (CONFIG_MX6DL) + smarcfimx6_dl_ddr_setting +#elif defined (CONFIG_MX6Q) + smarcfimx6_quad_ddr_setting +#else + #error "SOC not configured" +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/board/embedian/smarcfimx6/smarcfimx6.c b/board/embedian/smarcfimx6/smarcfimx6.c new file mode 100644 index 0000000..f9de880 --- /dev/null +++ b/board/embedian/smarcfimx6/smarcfimx6.c @@ -0,0 +1,1411 @@ +/* + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include "smarcfimx6.h" +#ifdef CONFIG_CMD_SATA +#include +#endif +#ifdef CONFIG_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FASTBOOT*/ + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/*I2C1 I2C_PM*/ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2 HDMI */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3 TCA9546APWR */ +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; +#endif + +int dram_init(void) +{ + + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); + + return 0; +} + +/* SER0/UART1 */ +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* SER1/UART2 */ +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* SER2/UART4 */ +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* SER3/UART5 Debug Port */ +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const wdt_pads[] = { + MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + gpio_direction_input(IMX_GPIO_NR(4, 11)); +} + +/* SDIO */ +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */ +}; + +/* SDMMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +/* eMMC */ +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_SYS_USE_SPINOR +/* SPI0 */ +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ + MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ + MX6_PAD_EIM_D25__GPIO3_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ +}; + +static void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + gpio_direction_output(IMX_GPIO_NR(5, 29), 0); + gpio_direction_output(IMX_GPIO_NR(3, 24), 0); + gpio_direction_output(IMX_GPIO_NR(3, 25), 0); +} +#endif + +/* SPI1 */ + iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ +}; + +iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */ + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ + MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */ +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); + gpio_direction_input(IMX_GPIO_NR(1, 16)); + gpio_direction_input(IMX_GPIO_NR(1, 17)); + gpio_direction_input(IMX_GPIO_NR(1, 19)); + gpio_direction_output(IMX_GPIO_NR(1, 20), 0); +} + +/* CAN0/FLEXCAN1 */ +iomux_v3_cfg_t const flexcan1_pads[] = { + MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +/* CAN1/FLEXCAN2 */ +iomux_v3_cfg_t const flexcan2_pads[] = { + MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +/* GPIOs */ +iomux_v3_cfg_t const gpios_pads[] = { + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */ + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */ + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */ + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */ + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */ + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */ + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */ + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */ + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */ + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */ + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */ +}; + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EIM_A16__GPIO2_IO22, + MX6_PAD_EIM_DA10__GPIO3_IO10, + MX6_PAD_EIM_DA12__GPIO3_IO12, + MX6_PAD_EIM_DA11__GPIO3_IO11, + MX6_PAD_EIM_LBA__GPIO2_IO27, + MX6_PAD_EIM_EB2__GPIO2_IO30, + MX6_PAD_EIM_CS0__GPIO2_IO23, + MX6_PAD_EIM_RW__GPIO2_IO26, + MX6_PAD_EIM_A21__GPIO2_IO17, + MX6_PAD_EIM_A22__GPIO2_IO16, + MX6_PAD_EIM_A23__GPIO6_IO06, + MX6_PAD_EIM_A24__GPIO5_IO04, + MX6_PAD_EIM_D31__GPIO3_IO31, + MX6_PAD_EIM_D27__GPIO3_IO27, + MX6_PAD_EIM_DA1__GPIO3_IO01, + MX6_PAD_EIM_EB1__GPIO2_IO29, + MX6_PAD_EIM_DA2__GPIO3_IO02, + MX6_PAD_EIM_DA4__GPIO3_IO04, + MX6_PAD_EIM_DA5__GPIO3_IO05, + MX6_PAD_EIM_DA6__GPIO3_IO06, +}; +#endif + +static void setup_iomux_uart1(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static void setup_iomux_uart2(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +static void setup_iomux_uart4(void) +{ + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +static void setup_iomux_uart5(void) +{ + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +static void setup_iomux_wdt(void) +{ + imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads)); + + /* Set HW_WDT as Output High */ + gpio_direction_output(IMX_GPIO_NR(3, 16) , 1); +} + +static void setup_spi1(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_direction_output(IMX_GPIO_NR(4, 9), 0); + gpio_direction_output(IMX_GPIO_NR(4, 10), 0); +} + +static void setup_flexcan1(void) +{ + imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads)); +} + +static void setup_flexcan2(void) +{ + imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads)); +} + +static void setup_gpios(void) +{ + imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads)); + gpio_direction_output(IMX_GPIO_NR(6, 11), 0); + gpio_direction_output(IMX_GPIO_NR(2, 02), 0); + gpio_direction_output(IMX_GPIO_NR(2, 06), 0); + gpio_direction_output(IMX_GPIO_NR(2, 03), 0); + gpio_direction_output(IMX_GPIO_NR(2, 07), 0); + gpio_direction_input(IMX_GPIO_NR(6, 14)); + gpio_direction_input(IMX_GPIO_NR(6, 07)); + gpio_direction_input(IMX_GPIO_NR(2, 04)); + gpio_direction_input(IMX_GPIO_NR(2, 00)); + gpio_direction_input(IMX_GPIO_NR(2, 05)); + gpio_direction_input(IMX_GPIO_NR(6, 8)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6 ; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + /* need ubstract 1 to map to the mmc device id + * see the comments in board_mmc_init function + */ + + dev_no--; + + return dev_no; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 1; +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28) +/*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/ + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + /*ret = !gpio_get_value(USDHC3_CD_GPIO);*/ + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SDIO + * mmc1 SDMMC + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_output(IMX_GPIO_NR(1, 18), 1); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + /*gpio_direction_input(USDHC3_CD_GPIO);*/ + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + } + + return status; +} + +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#ifdef CONFIG_SPLASH_SCREEN +extern int mmc_get_env_devno(void); +int setup_splash_img(void) +{ +#ifdef CONFIG_SPLASH_IS_IN_MMC + int mmc_dev = mmc_get_env_devno(); + ulong offset = CONFIG_SPLASH_IMG_OFFSET; + ulong size = CONFIG_SPLASH_IMG_SIZE; + ulong addr = 0; + char *s = NULL; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + s = getenv("splashimage"); + + if (NULL == s) { + puts("env splashimage not found!\n"); + return -1; + } + addr = simple_strtoul(s, NULL, 16); + + if (!mmc) { + printf("MMC Device %d not found\n", mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#endif + + return 0; +} +#endif + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as input */ + gpio_direction_input(IMX_GPIO_NR(2, 21)); + + /* EIM_D17 - GPIO3[17] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(3, 17), 1); + + /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(3, 20), 1); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(2, 20), 1); +} + +int setup_waveform_file(void) +{ +#ifdef CONFIG_WAVEFORM_FILE_IN_MMC + int mmc_dev = mmc_get_env_devno(); + ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; + ulong size = CONFIG_WAVEFORM_FILE_SIZE; + ulong addr = CONFIG_WAVEFORM_BUF_ADDR; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + if (!mmc) { + printf("MMC Device %d not found\n", mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#else + return -1; +#endif +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** epdc Maxim PMIC settings ***/ + + /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC VCOM0 - GPIO3[17] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->cscdr3); + reg &= ~0x7C000; + reg |= (1 << 16) | (1 << 14); + writel(reg, &ccm_regs->cscdr3); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x00C0; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x3FE00; + reg |= (2 << 15) | (5 << 12); + writel(reg, &ccm_regs->cscdr2); + + /* PLL5 enable (defaults to 650) */ + reg = readl(&ccm_regs->analog_pll_video); + reg &= ~((1 << 16) | (1 << 12)); + reg |= (1 << 13); + writel(reg, &ccm_regs->analog_pll_video); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; + panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); + + /* Assign fb_base */ + gd->fb_base = CONFIG_FB_BASE; +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 21))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 0); +} +#endif + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight Enable for RGB: S127 */ + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define BACKLIGHT_EN IMX_GPIO_NR(1, 00) + /* PWM Backlight Control: S141 */ + MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define BACKLIGHT_PWM IMX_GPIO_NR(1, 01) + /* Backlight Enable for LVDS: S127 */ + /*MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define LVDS_BACKLIGHT_EN IMX_GPIO_NR(1, 00)*/ + /* LCD VDD Enable: S133 */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define LCD_VDD_EN IMX_GPIO_NR(1, 02) +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */ + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, +}; + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + + +static int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) + && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(BACKLIGHT_EN, 1); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(BACKLIGHT_EN, 1); + gpio_direction_output(LCD_VDD_EN, 1); + gpio_direction_output(BACKLIGHT_PWM, 1); +} + +static struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 3, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 3, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "wsvga-lvds", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 3, + .addr = 0x48, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else { + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } + } else { + printf("unsupported panel %s\n", panel); + ret = -EINVAL; + } + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlights off until needed */ + /*imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(BACKLIGHT_EN);*/ +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_MAC_ADDR_IN_EEPROM) + + uchar env_enetaddr[6]; + int enetaddr_found; + + enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); + + uint8_t enetaddr[8]; + int eeprom_mac_read; + + /* Read Ethernet MAC address from EEPROM */ + eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr); + + /* + * MAC address not present in the environment + * try and read the MAC address from EEPROM flash + * and set it. + */ + if (!enetaddr_found) { + if (eeprom_mac_read) + /* Set Ethernet MAC address from EEPROM */ + smarcfimx6_sync_env_enetaddr(enetaddr); + } else { + /* + * MAC address present in environment compare it with + * the MAC address in EEPROM and warn on mismatch + */ + if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) + printf("Warning: MAC address in EEPROM don't match " + "with the MAC address in the environment\n"); + printf("Default using MAC address from environment\n"); + } + +#endif + + setup_iomux_enet(); + setup_pcie(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_wdt(); + setup_iomux_uart1(); + setup_iomux_uart2(); + setup_iomux_uart4(); + setup_iomux_uart5(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + +#ifdef CONFIG_SYS_USE_SPINOR + setup_spinor(); +#endif + + setup_spi1(); + setup_flexcan1(); + setup_flexcan2(); + setup_gpios(); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) + setup_epdc(); +#endif + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, + 0x50, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, + 0x70, &i2c_pad_info3); + + /* Configure I2C switch (PCA9546) to enable channel 0. */ + i2c_set_bus_num(2); + uint8_t i2cbuf; + i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE; + if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0, + CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) { + printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR); + return 1; + } + +#endif + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ + // Make sure we enable ECSPI2 clock + int reg; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + reg = readl(&mxc_ccm->CCGR1); + reg |= MXC_CCM_CCGR1_ECSPI2S_MASK; + writel(reg, &mxc_ccm->CCGR1); +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: SMARC-FiMX6 Rev.00A0\n"); + return 0; +} + +#ifdef CONFIG_FASTBOOT + +void board_fastboot_setup(void) +{ + switch (get_boot_device()) { +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) + case SATA_BOOT: + if (!getenv("fastboot_dev")) + setenv("fastboot_dev", "sata"); + if (!getenv("bootcmd")) + setenv("bootcmd", "booti sata"); + break; +#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + case SD2_BOOT: + case MMC2_BOOT: + if (!getenv("fastboot_dev")) + setenv("fastboot_dev", "mmc0"); + if (!getenv("bootcmd")) + setenv("bootcmd", "booti mmc0"); + break; + case SD3_BOOT: + case MMC3_BOOT: + if (!getenv("fastboot_dev")) + setenv("fastboot_dev", "mmc1"); + if (!getenv("bootcmd")) + setenv("bootcmd", "booti mmc1"); + break; + case MMC4_BOOT: + if (!getenv("fastboot_dev")) + setenv("fastboot_dev", "mmc2"); + if (!getenv("bootcmd")) + setenv("bootcmd", "booti mmc2"); + break; +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ + default: + printf("unsupported boot devices\n"); + break; + } + +} + +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) +iomux_v3_cfg_t const recovery_key_pads[] = { + (MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int check_recovery_cmd_file(void) +{ + int button_pressed = 0; + int recovery_mode = 0; + + recovery_mode = recovery_check_and_clean_flag(); + + /* Check Recovery Combo Button press or not. */ + imx_iomux_v3_setup_multiple_pads(recovery_key_pads, + ARRAY_SIZE(recovery_key_pads)); + + gpio_direction_input(GPIO_VOL_DN_KEY); + + if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return recovery_mode || button_pressed; +} + +void board_recovery_setup(void) +{ + int bootdev = get_boot_device(); + + switch (bootdev) { +#if defined(CONFIG_FASTBOOT_STORAGE_SATA) + case SATA_BOOT: + if (!getenv("bootcmd_android_recovery")) + setenv("bootcmd_android_recovery", + "booti sata recovery"); + break; +#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ +#if defined(CONFIG_FASTBOOT_STORAGE_MMC) + case SD2_BOOT: + case MMC2_BOOT: + if (!getenv("bootcmd_android_recovery")) + setenv("bootcmd_android_recovery", + "booti mmc0 recovery"); + break; + case SD3_BOOT: + case MMC3_BOOT: + if (!getenv("bootcmd_android_recovery")) + setenv("bootcmd_android_recovery", + "booti mmc1 recovery"); + break; + case MMC4_BOOT: + if (!getenv("bootcmd_android_recovery")) + setenv("bootcmd_android_recovery", + "booti mmc2 recovery"); + break; +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ + default: + printf("Unsupported bootup device for recovery: dev: %d\n", + bootdev); + return; + } + + printf("setup env for recovery..\n"); + setenv("bootcmd", "run bootcmd_android_recovery"); +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FASTBOOT*/ + +#ifdef CONFIG_IMX_UDC +iomux_v3_cfg_t const otg_udc_pads[] = { + (MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; +void udc_pins_setting(void) +{ + imx_iomux_v3_setup_multiple_pads(otg_udc_pads, + ARRAY_SIZE(otg_udc_pads)); + + /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ + mxc_iomux_set_gpr_register(1, 13, 1, 0); +} +#endif /*CONFIG_IMX_UDC*/ + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_hc1_pads[] = { + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ + mxc_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, + ARRAY_SIZE(usb_hc1_pads)); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + if (on){ + gpio_direction_output(IMX_GPIO_NR(1, 29), 1); + gpio_direction_input(IMX_GPIO_NR(1, 30)); + } + else + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} +#endif diff --git a/board/embedian/smarcfimx6/smarcfimx6.h b/board/embedian/smarcfimx6/smarcfimx6.h new file mode 100644 index 0000000..38db0c0 --- /dev/null +++ b/board/embedian/smarcfimx6/smarcfimx6.h @@ -0,0 +1,139 @@ +/* + * smarcfimx6.h + * + * Embedian SMARC-FiMX6 boards information header + * + * Copyright (C) 2015, Embedian, Inc. - http://www.embedian.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMARCFIMX6_H_ +#define _SMARCFIMX6_H_ + +/* +* SMARC-FiMX6 Config held in module eeprom device. +* +* Header Format +* +* Name Size Contents +* (Bytes) +*------------------------------------------------------------- +* Header 4 0xAA, 0x55, 0x33, 0xEE +* +* Board Name 8 Name for board in ASCII. +* example "FIMX6Q1G" = "SMARC-FiMX6 +* Quad Core and 1GB DDR3 memory" +* +* Version 4 Hardware version code for board in +* in ASCII. "00A0" = rev.0A +* Serial Number 12 Serial number of the board. This is a 12 +* character string which is: WWYYMSkknnnn, where +* WW = 2 digit week of the year of production +* YY = 2 digit year of production +* kk = 2 digit module variants +* nnnn = incrementing board number +* Configuration Option 32 Codes to show the configuration +* setup on this board. +* MAC Address (LAN1) MAC Address for FEC controller +* MAC Address (LAN2, if any) MAC Address for 2nd LAN (if any) +* Available 32700 Available space for other non-volatile +* codes/data +*/ + +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct smarcfimx6_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +static inline int board_is_fimx6slo(struct smarcfimx6_id *header) +{ + return !strncmp(header->name, "SMCMXSLO", HDR_NAME_LEN); +} + +static inline int board_is_fimx6u1g(struct smarcfimx6_id *header) +{ + return !strncmp(header->name, "SMCMXU1G", HDR_NAME_LEN); +} + +static inline int board_is_fimx6d1g(struct smarcfimx6_id *header) +{ + return !strncmp(header->name, "SMCMXD1G", HDR_NAME_LEN); +} + +static inline int board_is_fimx6d2g(struct smarcfimx6_id *header) +{ + return !strncmp(header->name, "SMCMXD2G", HDR_NAME_LEN); +} + +static inline int board_is_fimx6q1g(struct smarcfimx6_id *header) +{ + return !strncmp(header->name, "SMCMXQ1G", HDR_NAME_LEN); +} + +static inline int board_is_fimx6q2g(struct smarcfimx6_id *header) +{ + return !strncmp(header->name, "SMCMXQ2G", HDR_NAME_LEN); +} + +/* + * Read ethernet MAC address from EEPROM for SMARC-FiMX6DVEVM compatible boards. + * Returns 1 if found, 0 otherwise. + */ +int smarcfimx6_read_mac_address(uint8_t *buf) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR + /* Read MAC address. */ + i2c_set_bus_num(0); + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x3C, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) + goto i2cerr; + + /* Check that MAC address is valid. */ + if (!is_valid_ether_addr(buf)) + goto err; + + return 1; /* Found */ + +i2cerr: + printf("Read from EEPROM @ 0x%02x failed\n", + CONFIG_SYS_I2C_EEPROM_ADDR); +err: +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ + + return 0; +} + +/* + * If there is no MAC address in the environment, then it will be initialized + * (silently) from the value in the EEPROM. + */ +void smarcfimx6_sync_env_enetaddr(uint8_t *rom_enetaddr) +{ + uint8_t env_enetaddr[6]; + int ret; + + ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + if (!ret) { + /* + * There is no MAC address in the environment, so we + * initialize it from the value in the EEPROM. + */ + debug("### Setting environment from EEPROM MAC address = " + "\"%pM\"\n", + env_enetaddr); + ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); + } + if (!ret) + printf("Failed to set mac address from EEPROM: %d\n", ret); +} + +#endif diff --git a/boards.cfg b/boards.cfg index 2383d04..f7a8277 100644 --- a/boards.cfg +++ b/boards.cfg @@ -351,6 +351,27 @@ Active arm armv7 mx6 freescale mx6slevk Active arm armv7 mx6 freescale mx6slevk mx6slevkandroid mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_USE_SPINOR,ANDROID_SUPPORT Fabio Estevam Active arm armv7 mx6 freescale mx6slevk mx6slevk_spinor mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR Fabio Estevam +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER0,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER1,DDR_MB=1024,SYS_USE_SPINORi Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER2,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_1g_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,SER3,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_dl_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6dl_4x_k4b2g1646q.cfg,MX6DL,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER0,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER1,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER2,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,SER3,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_1g_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b2g1646q.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER0,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER1,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER2,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,SER3,DDR_MB=1024,SYS_USE_SPINOR Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_quad_2g_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6q_4x_k4b4g1646q.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,ANDROID_SUPPORT Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser0 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER0,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser1 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER1,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser2 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER2,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_ser3 smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,SER3,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp" Eric Lee +Active arm armv7 mx6 embedian smarcfimx6 smarcfimx6_solo_android smarcfimx6:IMX_CONFIG=board/embedian/smarcfimx6/ddr/mx6solo_2x_k4b2g1646q.cfg,MX6SOLO,DDR_MB=512,SYS_USE_SPINOR,SYS_NOSMP="nosmp",ANDROID_SUPPORT Eric Lee Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_17x17_arm2 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" Fabio Estevam Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_14x14_lpddr2_arm2 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,MX6SX,MX6SX_14x14,LPDDR2,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb" Fabio Estevam Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_14x14_lpddr2_arm2_nand mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,MX6SX,MX6SX_14x14,LPDDR2,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb",SYS_BOOT_NAND Fabio Estevam diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 18d6736..18eff34 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -127,6 +127,11 @@ static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip, return -1; buf = (uint8_t)((channel & 0x03) | (1 << 2)); break; + case I2C_MUX_PCA9546_ID: + if (channel > 4) + return -1; + buf = (uint8_t)((channel & 0x04) | (1 << 3)); + break; case I2C_MUX_PCA9547_ID: if (channel > 7) return -1; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 16051e5..142d5ab 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -238,8 +238,8 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) if ((start + blkcnt) > mmc->block_dev.lba) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", - start + blkcnt, mmc->block_dev.lba); + /*printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, mmc->block_dev.lba);*/ #endif return 0; } @@ -963,6 +963,9 @@ static int mmc_startup(struct mmc *mmc) case 6: mmc->version = MMC_VERSION_4_5; break; + case 7: + mmc->version = MMC_VERSION_5_0; + break; } /* diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index eb372b7..14f3ec5 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -40,6 +40,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0}, {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0}, {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0}, + {"MX25U3235F", 0xc22536, 0x0, 64 * 1024, 64, 0, SECT_4K}, {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, diff --git a/include/configs/smarcfimx6.h b/include/configs/smarcfimx6.h new file mode 100644 index 0000000..4eac765 --- /dev/null +++ b/include/configs/smarcfimx6.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreSD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SMARCFIMX6_CONFIG_H +#define __SMARCFIMX6_CONFIG_H + +#include +#include + +#define CONFIG_MACH_TYPE_SMARCFIMX6 3990 /*Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_SMARCFIMX6 +#if defined(CONFIG_SER0) +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONSOLE_DEV "ttymxc0" +#endif +#if defined(CONFIG_SER1) +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" +#endif +#if defined(CONFIG_SER2) +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_CONSOLE_DEV "ttymxc3" +#endif +#if defined(CONFIG_SER3) +#define CONFIG_MXC_UART_BASE UART5_BASE +#define CONFIG_CONSOLE_DEV "ttymxc4" +#endif +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ + +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6SOLO) +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb" +#elif defined(CONFIG_MX6Q) +#define CONFIG_DEFAULT_FDT_FILE "imx6q-smarcfimx6.dtb" +#endif + +#include "smarcfimx6_common.h" + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* 0 SDHC, 1 SDMMC, 2 eMMC */ +#define CONFIG_SYS_MMC_ENV_PART 2 /* user partition */ + +#ifdef CONFIG_SYS_USE_SPINOR +#define CONFIG_SF_DEFAULT_CS (1|(IMX_GPIO_NR(5, 29)<<8)) /* Use SPI2 SS0 as chip select */ +#endif + +/* + * imx6 q/dl/solo pcie would be failed to work properly in kernel, if + * the pcie module is iniialized/enumerated both in uboot and linux + * kernel. + * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. + * it is only be RESET by the POR. So, the pcie module only be + * initialized/enumerated once in one POR. + * Set to use pcie in kernel defaultly, mask the pcie config here. + * Remove the mask freely, if the uboot pcie functions, rather than + * the kernel's, are required. + */ +/* #define CONFIG_CMD_PCI */ +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(1, 20) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 17) +#endif + +/*#define CONFIG_SPLASH_SCREEN*/ +/*#define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) + /* + * Framebuffer and LCD + */ + #define CONFIG_CMD_BMP + #define CONFIG_LCD + #define CONFIG_FB_BASE (CONFIG_SYS_TEXT_BASE + 0x300000) + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #undef LCD_TEST_PATTERN + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_WORKING_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) + #define CONFIG_WAVEFORM_BUF_ADDR (CONFIG_SYS_TEXT_BASE + 0x200000) + #define CONFIG_WAVEFORM_FILE_OFFSET 0x600000 + #define CONFIG_WAVEFORM_FILE_SIZE 0xF0A00 + #define CONFIG_WAVEFORM_FILE_IN_MMC + +#ifdef CONFIG_SPLASH_IS_IN_MMC + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 + #define CONFIG_SPLASH_IMG_SIZE 0x19000 +#endif +#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ + +#endif /* __SMARCFIMX6_CONFIG_H */ diff --git a/include/configs/smarcfimx6_common.h b/include/configs/smarcfimx6_common.h new file mode 100644 index 0000000..314eefd --- /dev/null +++ b/include/configs/smarcfimx6_common.h @@ -0,0 +1,471 @@ +/* + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreSD board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SMARCFIMX6_COMMON_CONFIG_H +#define __SMARCFIMX6_COMMON_CONFIG_H + +#define CONFIG_MX6 + +#ifdef CONFIG_MX6SOLO +#define CONFIG_MX6DL +#endif + +/* uncomment for PLUGIN mode support */ +/* #define CONFIG_USE_PLUGIN */ + +/* uncomment for SECURE mode support */ +/* #define CONFIG_SECURE_BOOT */ + +#include "mx6_common.h" +#include + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FS_FAT +#define CONFIG_FS_EXT4 +#define CONFIG_EXT4_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_PART +#define CONFIG_HOST_MAX_DEVICES 4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_SYS_BOOT_NAND +#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) " +#else +#define CONFIG_MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=" CONFIG_CONSOLE_DEV ",115200 " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "enable_wait_mode=off "\ + CONFIG_MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x12C00000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_SYS_BOOT_NAND) + /* + * The dts also enables the WEIN NOR which is mtd0. + * So the partions' layout for NAND is: + * mtd1: 16M (uboot) + * mtd2: 16M (kernel) + * mtd3: 16M (dtb) + * mtd4: left (rootfs) + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "bootargs=console=" CONFIG_CONSOLE_DEV ",115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#elif defined(CONFIG_SYS_BOOT_SATA) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "bootargs=console=" CONFIG_CONSOLE_DEV ",115200 \0"\ + "bootargs_sata=setenv bootargs ${bootargs} " \ + "root=/dev/sda1 rootwait rw \0" \ + "bootcmd_sata=run bootargs_sata; sata init; " \ + "sata read ${loadaddr} 0x800 0x4000; " \ + "sata read ${fdt_addr} 0x8000 0x800; " \ + "bootz ${loadaddr} - ${fdt_addr} \0" \ + "bootcmd=run bootcmd_sata \0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "ethprime=FEC0\0" \ + "fec.macaddr=${ethaddr}\0" \ + "ipaddr=192.168.1.60\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "optargs= fec.macaddr=${ethaddr}\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "mmcautodetect=yes\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "smp=" CONFIG_SYS_NOSMP "\0"\ + "mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \ + "${optargs} " \ + "root=${mmcroot}\0" \ + "rootfstype=${mmcrootfstype} " \ + "video=${video}\0" \ + "loadbootenv=load mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdt_addr};\0" \ + "mmcbootdefault=echo Booting from mmc ...; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz ${loadaddr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz ${loadaddr}; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} ${smp} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "run importbootenv;" \ + "fi;" \ + "echo Checking if uenvcmd is set ...;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "echo Running default loadzimage ...;" \ + "if run loadzimage; then " \ + "run loadfdt;" \ + "run mmcboot;" \ + "fi;" \ + "else run netboot; fi" +#endif + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "# " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#ifndef CONFIG_SYS_NOSMP +#define CONFIG_SYS_NOSMP +#endif + +#if defined CONFIG_SYS_BOOT_SPINOR +#define CONFIG_SYS_USE_SPINOR +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_EIMNOR +#define CONFIG_SYS_USE_EIMNOR +#define CONFIG_ENV_IS_IN_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#elif defined CONFIG_SYS_BOOT_SATA +#define CONFIG_ENV_IS_IN_SATA +#define CONFIG_CMD_SATA +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +#ifdef CONFIG_SYS_USE_SPINOR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_SPEED 12000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#ifdef CONFIG_SYS_USE_EIMNOR +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (4 * CONFIG_SYS_FLASH_SECT_SIZE) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (8 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#elif defined(CONFIG_ENV_IS_IN_SATA) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_SATA_ENV_DEV 0 +#define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */ +#endif + +#define CONFIG_OF_LIBFDT + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* + * I2C configs + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C switch definitions for PCA9546 chip */ +#define CONFIG_SYS_I2C_PCA9546_ADDR 0x70 +#define CONFIG_SYS_I2C_PCA9546_ADDR_LEN 0 /* Single register. */ +#define CONFIG_SYS_I2C_PCA9546_ENABLE 0x07 /* Enable channel 0,1,2. */ +#define CONFIG_SYS_NUM_I2C_BUSES 5 +#define CONFIG_SYS_I2C_MAX_HOPS 2 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP}}, \ + {1, {I2C_NULL_HOP}}, \ + {2, {{I2C_MUX_PCA9546, 0x70, 1}}}, \ + {2, {{I2C_MUX_PCA9546, 0x70, 2}}}, \ + {2, {{I2C_MUX_PCA9546, 0x70, 3}}}, \ + } +/* +* I2C EEPROM definitions EEPROM chip +*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_MAC_ADDR_IN_EEPROM + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#ifdef CONFIG_MX6DL +#define CONFIG_IPUV3_CLK 198000000 +#else +#define CONFIG_IPUV3_CLK 264000000 +#endif +#define CONFIG_IMX_HDMI + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6sabreandroid_common.h" +#endif + +#endif /* __SMARCFIMX6_COMMON_CONFIG_H */ diff --git a/include/i2c.h b/include/i2c.h index 1b4078e..906191a 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -134,6 +134,8 @@ extern struct i2c_bus_hose i2c_bus[]; #define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"} #define I2C_MUX_PCA9544_ID 3 #define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} +#define I2C_MUX_PCA9546_ID 6 +#define I2C_MUX_PCA9546 {I2C_MUX_PCA9546_ID, "PCA9546A"} #define I2C_MUX_PCA9547_ID 4 #define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} #define I2C_MUX_PCA9548_ID 5 diff --git a/include/mmc.h b/include/mmc.h index 42d0125..ab68cd1 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -30,6 +30,7 @@ #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) +#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500) #define MMC_MODE_HS 0x001 #define MMC_MODE_HS_52MHz 0x010 -- 1.9.1