Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04

* origin/ls_v2020.04: (8 commits) configs: ls208xa: Enable GIC_V3_ITS config configs: ls1028a: Enable GIC_V3_ITS config configs: ls1088a: Enable GIC_V3_ITS config arm64: layerscape: Move GIC RD tables initialization to CPU setup function fsl-layerscape: Kconfig: Select RESV_RAM config if GIC_V3_ITS is enabled ...

Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04
* origin/ls_v2020.04: (8 commits) configs: ls208xa: Enable GIC_V3_ITS config configs: ls1028a: Enable GIC_V3_ITS config configs: ls1088a: Enable GIC_V3_ITS config arm64: layerscape: Move GIC RD tables initialization to CPU setup function fsl-layerscape: Kconfig: Select RESV_RAM config if GIC_V3_ITS is enabled ...
BJ DevOps Team
2 parents 873587f1c0 28121af8c1
Showing 36 changed files Side-by-side Diff
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/include/asm/arch-fsl-layerscape/soc.h
board/freescale/lx2160a/lx2160a.c
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
configs/ls1028aqds_tfa_defconfig
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
configs/ls1028ardb_tfa_defconfig
configs/ls1088aqds_defconfig
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
configs/ls1088aqds_qspi_defconfig
configs/ls1088aqds_sdcard_ifc_defconfig
configs/ls1088aqds_sdcard_qspi_defconfig
configs/ls1088aqds_tfa_defconfig
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_qspi_defconfig
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_sdcard_qspi_defconfig
@@ -46,6 +46,7 @@
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A050382
+	select RESV_RAM if GIC_V3_ITS
 	imply PANIC_HANG
  
 config ARCH_LS1043A
@@ -151,6 +152,7 @@
 	select SYS_I2C_MXC_I2C2 if !TFABOOT
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
+	select RESV_RAM if GIC_V3_ITS
 	imply SCSI
 	imply PANIC_HANG
  
@@ -201,6 +203,7 @@
 	select SYS_I2C_MXC_I2C2 if !TFABOOT
 	select SYS_I2C_MXC_I2C3 if !TFABOOT
 	select SYS_I2C_MXC_I2C4 if !TFABOOT
+	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
  
@@ -227,6 +230,7 @@
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
+	select RESV_RAM if GIC_V3_ITS
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 	imply SCSI
@@ -1384,7 +1384,7 @@
 	if (i > 0)
 		ret = 0;
  
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1407,7 +1407,7 @@
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
  
 	return ret;
 }
@@ -1470,7 +1470,7 @@
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
  
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1493,7 +1493,7 @@
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
  
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
@@ -610,6 +610,10 @@
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
 			     CONFIG_SYS_CLK_FREQ, 1);
  
+#ifdef CONFIG_GIC_V3_ITS
+	ls_gic_rd_tables_init(blob);
+#endif
+
 #if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
 	ft_pci_setup(blob, bd);
 #endif
@@ -6,10 +6,12 @@
  
 #include <common.h>
 #include <clock_legacy.h>
+#include <cpu_func.h>
 #include <env.h>
 #include <fsl_immap.h>
 #include <fsl_ifc.h>
 #include <init.h>
+#include <linux/sizes.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
@@ -17,6 +19,7 @@
 #include <asm/arch-fsl-layerscape/config.h>
 #include <asm/arch-fsl-layerscape/ns_access.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 #include <fsl_csu.h>
 #endif
  
@@ -30,10 +33,51 @@
 #include <fsl_immap.h>
 #ifdef CONFIG_TFABOOT
 #include <env_internal.h>
+#endif
+#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 #include <dm.h>
 #include <linux/err.h>
+
+#ifdef CONFIG_GIC_V3_ITS
+#define PENDTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
+#define PROPTABLE_MAX_SZ	ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
+#define GIC_LPI_SIZE		ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
+				PROPTABLE_MAX_SZ, SZ_1M)
+static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
+{
+	u32 phandle;
+	int err;
+	struct fdt_memory gic_rd_tables;
+
+	gic_rd_tables.start = base;
+	gic_rd_tables.end = base + size - 1;
+	err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
+					 &phandle);
+	if (err < 0)
+		debug("%s: failed to add reserved memory: %d\n", __func__, err);
+
+	return err;
+}
+
+int ls_gic_rd_tables_init(void *blob)
+{
+	u64 gic_lpi_base;
+	int ret;
+
+	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
+	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
+	if (ret)
+		return ret;
+
+	ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+	if (ret)
+		debug("%s: failed to init gic-lpi-tables\n", __func__);
+
+	return ret;
+}
+#endif
  
 bool soc_has_dp_ddr(void)
 {
@@ -133,6 +133,10 @@
  
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
+
+#ifdef CONFIG_GIC_V3_ITS
+int ls_gic_rd_tables_init(void *blob);
+#endif
 #endif
  
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
@@ -30,14 +30,12 @@
 #include "../common/vid.h"
 #include <fsl_immap.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <asm/gic-v3.h>
 #include <cpu_func.h>
  
 #ifdef CONFIG_EMC2305
 #include "../common/emc2305.h"
 #endif
  
-#define GIC_LPI_SIZE                             0x200000
 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 #define CFG_MUX_I2C_SDHC(reg, value)		((reg & 0x3f) | value)
 #define SET_CFG_MUX1_SDHC1_SDHC(reg)		(reg & 0x3f)
@@ -699,21 +697,6 @@
 }
 #endif
  
-#ifdef CONFIG_GIC_V3_ITS
-void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
-{
-	u32 phandle;
-	int err;
-	struct fdt_memory gic_lpi;
-
-	gic_lpi.start = gic_lpi_base;
-	gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
-	err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
-	if (err < 0)
-		debug("failed to add reserved memory: %d\n", err);
-}
-#endif
-
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -725,7 +708,6 @@
 	u64 mc_memory_base = 0;
 	u64 mc_memory_size = 0;
 	u16 total_memory_banks;
-	u64 gic_lpi_base;
  
 	ft_cpu_setup(blob, bd);
  
@@ -744,12 +726,6 @@
 		base[i] = gd->bd->bi_dram[i].start;
 		size[i] = gd->bd->bi_dram[i].size;
 	}
-
-#ifdef CONFIG_GIC_V3_ITS
-	gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
-	gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
-	fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
-#endif
  
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
@@ -85,4 +85,5 @@
 CONFIG_NVME=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LS_HDP_LOAD=y
+CONFIG_GIC_V3_ITS=y
@@ -90,4 +90,5 @@
 CONFIG_NVME=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LS_HDP_LOAD=y
+CONFIG_GIC_V3_ITS=y
@@ -82,4 +82,5 @@
 CONFIG_NVME=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LS_HDP_LOAD=y
+CONFIG_GIC_V3_ITS=y
@@ -91,4 +91,5 @@
 CONFIG_NVME=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LS_HDP_LOAD=y
+CONFIG_GIC_V3_ITS=y
@@ -65,4 +65,5 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
@@ -66,4 +66,5 @@
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -67,4 +67,5 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -73,4 +73,5 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
@@ -76,4 +76,5 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
@@ -84,4 +84,5 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -67,4 +67,5 @@
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -68,4 +68,5 @@
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -75,4 +75,5 @@
 CONFIG_USB_DWC3=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
+CONFIG_GIC_V3_ITS=y
@@ -77,4 +77,5 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_GIC_V3_ITS=y
@@ -75,4 +75,5 @@
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -81,4 +81,5 @@
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
@@ -64,4 +64,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -65,4 +65,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -72,4 +72,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -64,4 +64,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -71,4 +71,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -66,4 +66,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -67,4 +67,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -72,4 +72,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -64,4 +64,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -77,4 +77,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -61,4 +61,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -66,4 +66,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -78,4 +78,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
@@ -83,4 +83,5 @@
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_CMD_NVME=y
 CONFIG_NVME=y
+CONFIG_GIC_V3_ITS=y
...	...	@@ -46,6 +46,7 @@
46	46	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47	47	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
48	48	select SYS_FSL_ERRATUM_A050382
	49	+ select RESV_RAM if GIC_V3_ITS
49	50	imply PANIC_HANG
50	51
51	52	config ARCH_LS1043A
...	...	@@ -151,6 +152,7 @@
151	152	select SYS_I2C_MXC_I2C2 if !TFABOOT
152	153	select SYS_I2C_MXC_I2C3 if !TFABOOT
153	154	select SYS_I2C_MXC_I2C4 if !TFABOOT
	155	+ select RESV_RAM if GIC_V3_ITS
154	156	imply SCSI
155	157	imply PANIC_HANG
156	158
...	...	@@ -201,6 +203,7 @@
201	203	select SYS_I2C_MXC_I2C2 if !TFABOOT
202	204	select SYS_I2C_MXC_I2C3 if !TFABOOT
203	205	select SYS_I2C_MXC_I2C4 if !TFABOOT
	206	+ select RESV_RAM if GIC_V3_ITS
204	207	imply DISTRO_DEFAULTS
205	208	imply PANIC_HANG
206	209
...	...	@@ -227,6 +230,7 @@
227	230	select ARCH_EARLY_INIT_R
228	231	select BOARD_EARLY_INIT_F
229	232	select SYS_I2C_MXC
	233	+ select RESV_RAM if GIC_V3_ITS
230	234	imply DISTRO_DEFAULTS
231	235	imply PANIC_HANG
232	236	imply SCSI
...	...	@@ -1384,7 +1384,7 @@
1384	1384	if (i > 0)
1385	1385	ret = 0;
1386	1386
1387		-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
	1387	+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1388	1388	/* Assign memory for MC */
1389	1389	#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1390	1390	if (gd->bd->bi_dram[2].size >=
...	...	@@ -1407,7 +1407,7 @@
1407	1407	board_reserve_ram_top(gd->bd->bi_dram[0].size);
1408	1408	}
1409	1409	}
1410		-#endif /* CONFIG_FSL_MC_ENET */
	1410	+#endif /* CONFIG_RESV_RAM */
1411	1411
1412	1412	return ret;
1413	1413	}
...	...	@@ -1470,7 +1470,7 @@
1470	1470	}
1471	1471	#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1472	1472
1473		-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
	1473	+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
1474	1474	/* Assign memory for MC */
1475	1475	#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1476	1476	if (gd->bd->bi_dram[2].size >=
...	...	@@ -1493,7 +1493,7 @@
1493	1493	board_reserve_ram_top(gd->bd->bi_dram[0].size);
1494	1494	}
1495	1495	}
1496		-#endif /* CONFIG_FSL_MC_ENET */
	1496	+#endif /* CONFIG_RESV_RAM */
1497	1497
1498	1498	#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1499	1499	#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
...	...	@@ -610,6 +610,10 @@
610	610	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
611	611	CONFIG_SYS_CLK_FREQ, 1);
612	612
	613	+#ifdef CONFIG_GIC_V3_ITS
	614	+ ls_gic_rd_tables_init(blob);
	615	+#endif
	616	+
613	617	#if defined(CONFIG_PCIE_LAYERSCAPE) \|\| defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
614	618	ft_pci_setup(blob, bd);
615	619	#endif
...	...	@@ -6,10 +6,12 @@
6	6
7	7	#include <common.h>
8	8	#include <clock_legacy.h>
	9	+#include <cpu_func.h>
9	10	#include <env.h>
10	11	#include <fsl_immap.h>
11	12	#include <fsl_ifc.h>
12	13	#include <init.h>
	14	+#include <linux/sizes.h>
13	15	#include <asm/arch/fsl_serdes.h>
14	16	#include <asm/arch/soc.h>
15	17	#include <asm/io.h>
...	...	@@ -17,6 +19,7 @@
17	19	#include <asm/arch-fsl-layerscape/config.h>
18	20	#include <asm/arch-fsl-layerscape/ns_access.h>
19	21	#include <asm/arch-fsl-layerscape/fsl_icid.h>
	22	+#include <asm/gic-v3.h>
20	23	#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
21	24	#include <fsl_csu.h>
22	25	#endif
23	26
...	...	@@ -30,10 +33,51 @@
30	33	#include <fsl_immap.h>
31	34	#ifdef CONFIG_TFABOOT
32	35	#include <env_internal.h>
	36	+#endif
	37	+#if defined(CONFIG_TFABOOT) \|\| defined(CONFIG_GIC_V3_ITS)
33	38	DECLARE_GLOBAL_DATA_PTR;
34	39	#endif
35	40	#include <dm.h>
36	41	#include <linux/err.h>
	42	+
	43	+#ifdef CONFIG_GIC_V3_ITS
	44	+#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
	45	+#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
	46	+#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
	47	+ PROPTABLE_MAX_SZ, SZ_1M)
	48	+static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
	49	+{
	50	+ u32 phandle;
	51	+ int err;
	52	+ struct fdt_memory gic_rd_tables;
	53	+
	54	+ gic_rd_tables.start = base;
	55	+ gic_rd_tables.end = base + size - 1;
	56	+ err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
	57	+ &phandle);
	58	+ if (err < 0)
	59	+ debug("%s: failed to add reserved memory: %d\n", __func__, err);
	60	+
	61	+ return err;
	62	+}
	63	+
	64	+int ls_gic_rd_tables_init(void *blob)
	65	+{
	66	+ u64 gic_lpi_base;
	67	+ int ret;
	68	+
	69	+ gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
	70	+ ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
	71	+ if (ret)
	72	+ return ret;
	73	+
	74	+ ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
	75	+ if (ret)
	76	+ debug("%s: failed to init gic-lpi-tables\n", __func__);
	77	+
	78	+ return ret;
	79	+}
	80	+#endif
37	81
38	82	bool soc_has_dp_ddr(void)
39	83	{
...	...	@@ -133,6 +133,10 @@
133	133
134	134	bool soc_has_dp_ddr(void);
135	135	bool soc_has_aiop(void);
	136	+
	137	+#ifdef CONFIG_GIC_V3_ITS
	138	+int ls_gic_rd_tables_init(void *blob);
	139	+#endif
136	140	#endif
137	141
138	142	#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
...	...	@@ -30,14 +30,12 @@
30	30	#include "../common/vid.h"
31	31	#include <fsl_immap.h>
32	32	#include <asm/arch-fsl-layerscape/fsl_icid.h>
33		-#include <asm/gic-v3.h>
34	33	#include <cpu_func.h>
35	34
36	35	#ifdef CONFIG_EMC2305
37	36	#include "../common/emc2305.h"
38	37	#endif
39	38
40		-#define GIC_LPI_SIZE 0x200000
41	39	#if defined(CONFIG_TARGET_LX2160AQDS) \|\| defined(CONFIG_TARGET_LX2162AQDS)
42	40	#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) \| value)
43	41	#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
...	...	@@ -699,21 +697,6 @@
699	697	}
700	698	#endif
701	699
702		-#ifdef CONFIG_GIC_V3_ITS
703		-void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
704		-{
705		- u32 phandle;
706		- int err;
707		- struct fdt_memory gic_lpi;
708		-
709		- gic_lpi.start = gic_lpi_base;
710		- gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
711		- err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
712		- if (err < 0)
713		- debug("failed to add reserved memory: %d\n", err);
714		-}
715		-#endif
716		-
717	700	#ifdef CONFIG_OF_BOARD_SETUP
718	701	int ft_board_setup(void blob, bd_t bd)
719	702	{
...	...	@@ -725,7 +708,6 @@
725	708	u64 mc_memory_base = 0;
726	709	u64 mc_memory_size = 0;
727	710	u16 total_memory_banks;
728		- u64 gic_lpi_base;
729	711
730	712	ft_cpu_setup(blob, bd);
731	713
...	...	@@ -744,12 +726,6 @@
744	726	base[i] = gd->bd->bi_dram[i].start;
745	727	size[i] = gd->bd->bi_dram[i].size;
746	728	}
747		-
748		-#ifdef CONFIG_GIC_V3_ITS
749		- gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
750		- gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
751		- fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
752		-#endif
753	729
754	730	#ifdef CONFIG_RESV_RAM
755	731	/* reduce size if reserved memory is within this bank */
...	...	@@ -85,4 +85,5 @@
85	85	CONFIG_NVME=y
86	86	CONFIG_VIDEO=y
87	87	CONFIG_VIDEO_LS_HDP_LOAD=y
	88	+CONFIG_GIC_V3_ITS=y
...	...	@@ -90,4 +90,5 @@
90	90	CONFIG_NVME=y
91	91	CONFIG_VIDEO=y
92	92	CONFIG_VIDEO_LS_HDP_LOAD=y
	93	+CONFIG_GIC_V3_ITS=y
...	...	@@ -82,4 +82,5 @@
82	82	CONFIG_NVME=y
83	83	CONFIG_VIDEO=y
84	84	CONFIG_VIDEO_LS_HDP_LOAD=y
	85	+CONFIG_GIC_V3_ITS=y
...	...	@@ -91,4 +91,5 @@
91	91	CONFIG_NVME=y
92	92	CONFIG_VIDEO=y
93	93	CONFIG_VIDEO_LS_HDP_LOAD=y
	94	+CONFIG_GIC_V3_ITS=y