Eric Lee / smarc-uboot

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Commit f1cf36095b173c6323f1e90c6ce2002cae5906e1

Authored by Ye Li
1 parent dd2cdd82b8
Exists in smarc-imx_v2018.03_4.14.78_1.0.0_ga

MLK-20528-1 imx8: Add lpcg driver for iMX8QM/QXP 

Each module may have one or more lpcg registers for SW/HW enabling its
clocks. Add lpcg register address and its driver for accessing lpcg.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 19f234266e07c18ab8364336779bf2d3d1f51c81)

Showing 4 changed files with 509 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h
Diff comments   View file @ f1cf360
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _SC_LPCG_H
  8 +#define _SC_LPCG_H
  9 +
  10 +/*LSIO SS */
  11 +#define PWM_0_LPCG 0x5D400000
  12 +#define PWM_1_LPCG 0x5D410000
  13 +#define PWM_2_LPCG 0x5D420000
  14 +#define PWM_3_LPCG 0x5D430000
  15 +#define PWM_4_LPCG 0x5D440000
  16 +#define PWM_5_LPCG 0x5D450000
  17 +#define PWM_6_LPCG 0x5D460000
  18 +#define PWM_7_LPCG 0x5D470000
  19 +#define GPIO_0_LPCG 0x5D480000
  20 +#define GPIO_1_LPCG 0x5D490000
  21 +#define GPIO_2_LPCG 0x5D4A0000
  22 +#define GPIO_3_LPCG 0x5D4B0000
  23 +#define GPIO_4_LPCG 0x5D4C0000
  24 +#define GPIO_5_LPCG 0x5D4D0000
  25 +#define GPIO_6_LPCG 0x5D4E0000
  26 +#define GPIO_7_LPCG 0x5D4F0000
  27 +#define FSPI_0_LPCG 0x5D520000
  28 +#define FSPI_1_LPCG 0x5D530000
  29 +#define GPT_0_LPCG 0x5D540000
  30 +#define GPT_1_LPCG 0x5D550000
  31 +#define GPT_2_LPCG 0x5D560000
  32 +#define GPT_3_LPCG 0x5D570000
  33 +#define GPT_4_LPCG 0x5D580000
  34 +#define OCRAM_LPCG 0x5D590000
  35 +#define KPP_LPCG 0x5D5A0000
  36 +#define MU_5A_LPCG 0x5D600000
  37 +#define MU_6A_LPCG 0x5D610000
  38 +#define MU_7A_LPCG 0x5D620000
  39 +#define MU_8A_LPCG 0x5D630000
  40 +#define MU_9A_LPCG 0x5D640000
  41 +#define MU_10A_LPCG 0x5D650000
  42 +#define MU_11A_LPCG 0x5D660000
  43 +#define MU_12A_LPCG 0x5D670000
  44 +#define MU_13A_LPCG 0x5D680000
  45 +
  46 +/* HSIO SS */
  47 +#define CRR_5_LPCG 0x5F0F0000
  48 +#define CRR_4_LPCG 0x5F0E0000
  49 +#define CRR_3_LPCG 0x5F0D0000
  50 +#define CRR_2_LPCG 0x5F0C0000
  51 +#define CRR_1_LPCG 0x5F0B0000
  52 +#define CRR_0_LPCG 0x5F0A0000
  53 +#define PHY_1_LPCG 0x5F090000
  54 +#define PHY_2_LPCG 0x5F080000
  55 +#define SATA_0_LPCG 0x5F070000
  56 +#define PCIE_B_LPCG 0x5F060000
  57 +#define PCIE_A_LPCG 0x5F050000
  58 +
  59 +/* DMA SS */
  60 +#define FLEX_CAN_2_LPCG 0x5ACF0000
  61 +#define FLEX_CAN_1_LPCG 0x5ACE0000
  62 +#define FLEX_CAN_0_LPCG 0x5ACD0000
  63 +#define FTM_1_LPCG 0x5ACB0000
  64 +#define FTM_0_LPCG 0x5ACA0000
  65 +#define ADC_1_LPCG 0x5AC90000
  66 +#define ADC_0_LPCG 0x5AC80000
  67 +#define LPI2C_4_LPCG 0x5AC40000
  68 +#define LPI2C_3_LPCG 0x5AC30000
  69 +#define LPI2C_2_LPCG 0x5AC20000
  70 +#define LPI2C_1_LPCG 0x5AC10000
  71 +#define LPI2C_0_LPCG 0x5AC00000
  72 +#define EMVSIM_1_LPCG 0x5A4E0000
  73 +#define EMVSIM_0_LPCG 0x5A4D0000
  74 +#define LPUART_4_LPCG 0x5A4A0000
  75 +#define LPUART_3_LPCG 0x5A490000
  76 +#define LPUART_2_LPCG 0x5A480000
  77 +#define LPUART_1_LPCG 0x5A470000
  78 +#define LPUART_0_LPCG 0x5A460000
  79 +#define LPSPI_3_LPCG 0x5A430000
  80 +#define LPSPI_2_LPCG 0x5A420000
  81 +#define LPSPI_1_LPCG 0x5A410000
  82 +#define LPSPI_0_LPCG 0x5A400000
  83 +
  84 +/* Display SS */
  85 +#define DC_0_LPCG 0x56010000
  86 +#define DC_1_LPCG 0x57010000
  87 +
  88 +/* LVDS */
  89 +#define DI_LVDS_0_LPCG 0x56243000
  90 +#define DI_LVDS_1_LPCG 0x57243000
  91 +
  92 +/* DI HDMI */
  93 +#define DI_HDMI_LPCG 0x56263000
  94 +
  95 +/* RX-HDMI */
  96 +#define RX_HDMI_LPCG 0x58263000
  97 +
  98 +/* MIPI CSI SS */
  99 +#define MIPI_CSI_0_LPCG 0x58223000
  100 +#define MIPI_CSI_1_LPCG 0x58243000
  101 +
  102 +/* MIPI DSI SS */
  103 +#define MIPI_DSI_0_LPCG 0x56223000
  104 +#define MIPI_DSI_1_LPCG 0x57223000
  105 +
  106 +/* Imaging SS */
  107 +#define IMG_JPEG_ENC_LPCG 0x585F0000
  108 +#define IMG_JPEG_DEC_LPCG 0x585D0000
  109 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000
  110 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000
  111 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000
  112 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000
  113 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000
  114 +#define IMG_PDMA_7_LPCG 0x58570000
  115 +#define IMG_PDMA_6_LPCG 0x58560000
  116 +#define IMG_PDMA_5_LPCG 0x58550000
  117 +#define IMG_PDMA_4_LPCG 0x58540000
  118 +#define IMG_PDMA_3_LPCG 0x58530000
  119 +#define IMG_PDMA_2_LPCG 0x58520000
  120 +#define IMG_PDMA_1_LPCG 0x58510000
  121 +#define IMG_PDMA_0_LPCG 0x58500000
  122 +
  123 +/* HSIO SS */
  124 +#define HSIO_GPIO_LPCG 0x5F100000
  125 +#define HSIO_MISC_LPCG 0x5F0F0000
  126 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000
  127 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000
  128 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000
  129 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000
  130 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000
  131 +#define HSIO_PHY_X1_LPCG 0x5F090000
  132 +#define HSIO_PHY_X2_LPCG 0x5F080000
  133 +#define HSIO_SATA_LPCG 0x5F070000
  134 +#define HSIO_PCIE_X1_LPCG 0x5F060000
  135 +#define HSIO_PCIE_X2_LPCG 0x5F050000
  136 +
  137 +/* M4 SS */
  138 +#define M4_0_I2C_LPCG 0x37630000
  139 +#define M4_0_LPUART_LPCG 0x37620000
  140 +#define M4_0_LPIT_LPCG 0x37610000
  141 +#define M4_1_I2C_LPCG 0x3B630000
  142 +#define M4_1_LPUART_LPCG 0x3B620000
  143 +#define M4_1_LPIT_LPCG 0x3B610000
  144 +
  145 +/* Audio SS */
  146 +#define AUD_ASRC_0_LPCG 0x59400000
  147 +#define AUD_ESAI_0_LPCG 0x59410000
  148 +#define AUD_SPDIF_0_LPCG 0x59420000
  149 +#define AUD_SPDIF_1_LPCG 0x59430000
  150 +#define AUD_SAI_0_LPCG 0x59440000
  151 +#define AUD_SAI_1_LPCG 0x59450000
  152 +#define AUD_SAI_2_LPCG 0x59460000
  153 +#define AUD_SAI_3_LPCG 0x59470000
  154 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000
  155 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000
  156 +#define AUD_GPT_5_LPCG 0x594B0000
  157 +#define AUD_GPT_6_LPCG 0x594C0000
  158 +#define AUD_GPT_7_LPCG 0x594D0000
  159 +#define AUD_GPT_8_LPCG 0x594E0000
  160 +#define AUD_GPT_9_LPCG 0x594F0000
  161 +#define AUD_GPT_10_LPCG 0x59500000
  162 +#define AUD_DSP_LPCG 0x59580000
  163 +#define AUD_OCRAM_LPCG 0x59590000
  164 +#define AUD_EDMA_0_LPCG 0x595f0000
  165 +#define AUD_ASRC_1_LPCG 0x59c00000
  166 +#define AUD_ESAI_1_LPCG 0x59c10000
  167 +#define AUD_SAI_6_LPCG 0x59c20000
  168 +#define AUD_SAI_7_LPCG 0x59c30000
  169 +#define AUD_AMIX_LPCG 0x59c40000
  170 +#define AUD_MQS_LPCG 0x59c50000
  171 +#define AUD_ACM_LPCG 0x59c60000
  172 +#define AUD_REC_CLK0_LPCG 0x59d00000
  173 +#define AUD_REC_CLK1_LPCG 0x59d10000
  174 +#define AUD_PLL_CLK0_LPCG 0x59d20000
  175 +#define AUD_PLL_CLK1_LPCG 0x59d30000
  176 +#define AUD_MCLKOUT0_LPCG 0x59d50000
  177 +#define AUD_MCLKOUT1_LPCG 0x59d60000
  178 +#define AUD_EDMA_1_LPCG 0x59df0000
  179 +
  180 +
  181 +/* Connectivity SS */
  182 +#define USDHC_0_LPCG 0x5B200000
  183 +#define USDHC_1_LPCG 0x5B210000
  184 +#define USDHC_2_LPCG 0x5B220000
  185 +#define ENET_0_LPCG 0x5B230000
  186 +#define ENET_1_LPCG 0x5B240000
  187 +#define DTCP_LPCG 0x5B250000
  188 +#define MLB_LPCG 0x5B260000
  189 +#define USB_2_LPCG 0x5B270000
  190 +#define USB_3_LPCG 0x5B280000
  191 +#define NAND_LPCG 0x5B290000
  192 +#define EDMA_LPCG 0x5B2A0000
  193 +
  194 +/* CM40 SS */
  195 +#define CM40_I2C_LPCG 0x37630000
  196 +
  197 +/* CM41 SS */
  198 +#define CM41_I2C_LPCG 0x3B630000
  199 +
  200 +#endif
arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h
Diff comments   View file @ f1cf360
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _SC_LPCG_H
  8 +#define _SC_LPCG_H
  9 +
  10 +/*LSIO SS */
  11 +#define PWM_0_LPCG 0x5D400000
  12 +#define PWM_1_LPCG 0x5D410000
  13 +#define PWM_2_LPCG 0x5D420000
  14 +#define PWM_3_LPCG 0x5D430000
  15 +#define PWM_4_LPCG 0x5D440000
  16 +#define PWM_5_LPCG 0x5D450000
  17 +#define PWM_6_LPCG 0x5D460000
  18 +#define PWM_7_LPCG 0x5D470000
  19 +#define GPIO_0_LPCG 0x5D480000
  20 +#define GPIO_1_LPCG 0x5D490000
  21 +#define GPIO_2_LPCG 0x5D4A0000
  22 +#define GPIO_3_LPCG 0x5D4B0000
  23 +#define GPIO_4_LPCG 0x5D4C0000
  24 +#define GPIO_5_LPCG 0x5D4D0000
  25 +#define GPIO_6_LPCG 0x5D4E0000
  26 +#define GPIO_7_LPCG 0x5D4F0000
  27 +#define FSPI_0_LPCG 0x5D520000
  28 +#define FSPI_1_LPCG 0x5D530000
  29 +#define GPT_0_LPCG 0x5D540000
  30 +#define GPT_1_LPCG 0x5D550000
  31 +#define GPT_2_LPCG 0x5D560000
  32 +#define GPT_3_LPCG 0x5D570000
  33 +#define GPT_4_LPCG 0x5D580000
  34 +#define OCRAM_LPCG 0x5D590000
  35 +#define KPP_LPCG 0x5D5A0000
  36 +#define ROMCP_LPCG 0x5D500000
  37 +#define MU_5A_LPCG 0x5D600000
  38 +#define MU_6A_LPCG 0x5D610000
  39 +#define MU_7A_LPCG 0x5D620000
  40 +#define MU_8A_LPCG 0x5D630000
  41 +#define MU_9A_LPCG 0x5D640000
  42 +#define MU_10A_LPCG 0x5D650000
  43 +#define MU_11A_LPCG 0x5D660000
  44 +#define MU_12A_LPCG 0x5D670000
  45 +#define MU_13A_LPCG 0x5D680000
  46 +
  47 +/* HSIO SS */
  48 +#define CRR_5_LPCG 0x5F0F0000
  49 +#define CRR_4_LPCG 0x5F0E0000
  50 +#define CRR_3_LPCG 0x5F0D0000
  51 +#define CRR_2_LPCG 0x5F0C0000
  52 +#define CRR_1_LPCG 0x5F0B0000
  53 +#define CRR_0_LPCG 0x5F0A0000
  54 +#define PHY_1_LPCG 0x5F090000
  55 +#define PHY_2_LPCG 0x5F080000
  56 +#define SATA_0_LPCG 0x5F070000
  57 +#define PCIE_B_LPCG 0x5F060000
  58 +#define PCIE_A_LPCG 0x5F050000
  59 +
  60 +/* DMA SS */
  61 +#define FLEX_CAN_2_LPCG 0x5ACF0000
  62 +#define FLEX_CAN_1_LPCG 0x5ACE0000
  63 +#define FLEX_CAN_0_LPCG 0x5ACD0000
  64 +#define FTM_1_LPCG 0x5ACB0000
  65 +#define FTM_0_LPCG 0x5ACA0000
  66 +#define ADC_0_LPCG 0x5AC80000
  67 +#define LPI2C_3_LPCG 0x5AC30000
  68 +#define LPI2C_2_LPCG 0x5AC20000
  69 +#define LPI2C_1_LPCG 0x5AC10000
  70 +#define LPI2C_0_LPCG 0x5AC00000
  71 +#define PWM_LPCG 0x5A590000
  72 +#define LCD_LPCG 0x5A580000
  73 +#define LPUART_3_LPCG 0x5A490000
  74 +#define LPUART_2_LPCG 0x5A480000
  75 +#define LPUART_1_LPCG 0x5A470000
  76 +#define LPUART_0_LPCG 0x5A460000
  77 +#define LPSPI_3_LPCG 0x5A430000
  78 +#define LPSPI_2_LPCG 0x5A420000
  79 +#define LPSPI_1_LPCG 0x5A410000
  80 +#define LPSPI_0_LPCG 0x5A400000
  81 +
  82 +/* Display SS */
  83 +#define DC_0_LPCG 0x56010000
  84 +#define DC_1_LPCG 0x57010000
  85 +
  86 +/* LVDS */
  87 +#define DI_LVDS_0_LPCG 0x56243000
  88 +#define DI_LVDS_1_LPCG 0x57243000
  89 +
  90 +/* DI HDMI */
  91 +#define DI_HDMI_LPCG 0x56263000
  92 +
  93 +/* RX-HDMI */
  94 +#define RX_HDMI_LPCG 0x58263000
  95 +
  96 +/* MIPI CSI SS */
  97 +#define MIPI_CSI_0_LPCG 0x58223000
  98 +#define MIPI_CSI_1_LPCG 0x58243000
  99 +
  100 +/* PARALLEL CSI SS */
  101 +#define PARALLEL_CSI_LPCG 0x58263000
  102 +
  103 +/* Display MIPI SS */
  104 +#define DI_MIPI0_LPCG 0x56223000
  105 +#define DI_MIPI1_LPCG 0x56243000
  106 +
  107 +/* Imaging SS */
  108 +#define IMG_JPEG_ENC_LPCG 0x585F0000
  109 +#define IMG_JPEG_DEC_LPCG 0x585D0000
  110 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000
  111 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000
  112 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000
  113 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000
  114 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000
  115 +#define IMG_PDMA_7_LPCG 0x58570000
  116 +#define IMG_PDMA_6_LPCG 0x58560000
  117 +#define IMG_PDMA_5_LPCG 0x58550000
  118 +#define IMG_PDMA_4_LPCG 0x58540000
  119 +#define IMG_PDMA_3_LPCG 0x58530000
  120 +#define IMG_PDMA_2_LPCG 0x58520000
  121 +#define IMG_PDMA_1_LPCG 0x58510000
  122 +#define IMG_PDMA_0_LPCG 0x58500000
  123 +
  124 +/* HSIO SS */
  125 +#define HSIO_GPIO_LPCG 0x5F100000
  126 +#define HSIO_MISC_LPCG 0x5F0F0000
  127 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000
  128 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000
  129 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000
  130 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000
  131 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000
  132 +#define HSIO_PHY_X1_LPCG 0x5F090000
  133 +#define HSIO_PHY_X2_LPCG 0x5F080000
  134 +#define HSIO_SATA_LPCG 0x5F070000
  135 +#define HSIO_PCIE_X1_LPCG 0x5F060000
  136 +#define HSIO_PCIE_X2_LPCG 0x5F050000
  137 +
  138 +/* M4 SS */
  139 +#define M4_0_I2C_LPCG 0x37630000
  140 +#define M4_0_LPUART_LPCG 0x37620000
  141 +#define M4_0_LPIT_LPCG 0x37610000
  142 +#define M4_1_I2C_LPCG 0x3B630000
  143 +#define M4_1_LPUART_LPCG 0x3B620000
  144 +#define M4_1_LPIT_LPCG 0x3B610000
  145 +
  146 +/* Audio SS */
  147 +#define AUD_ASRC_0_LPCG 0x59400000
  148 +#define AUD_ESAI_0_LPCG 0x59410000
  149 +#define AUD_SPDIF_0_LPCG 0x59420000
  150 +#define AUD_SAI_0_LPCG 0x59440000
  151 +#define AUD_SAI_1_LPCG 0x59450000
  152 +#define AUD_SAI_2_LPCG 0x59460000
  153 +#define AUD_SAI_3_LPCG 0x59470000
  154 +#define AUD_GPT_5_LPCG 0x594B0000
  155 +#define AUD_GPT_6_LPCG 0x594C0000
  156 +#define AUD_GPT_7_LPCG 0x594D0000
  157 +#define AUD_GPT_8_LPCG 0x594E0000
  158 +#define AUD_GPT_9_LPCG 0x594F0000
  159 +#define AUD_GPT_10_LPCG 0x59500000
  160 +#define AUD_DSP_LPCG 0x59580000
  161 +#define AUD_OCRAM_LPCG 0x59590000
  162 +#define AUD_EDMA_0_LPCG 0x595f0000
  163 +#define AUD_ASRC_1_LPCG 0x59c00000
  164 +#define AUD_SAI_4_LPCG 0x59c20000
  165 +#define AUD_SAI_5_LPCG 0x59c30000
  166 +#define AUD_AMIX_LPCG 0x59c40000
  167 +#define AUD_MQS_LPCG 0x59c50000
  168 +#define AUD_ACM_LPCG 0x59c60000
  169 +#define AUD_REC_CLK0_LPCG 0x59d00000
  170 +#define AUD_REC_CLK1_LPCG 0x59d10000
  171 +#define AUD_PLL_CLK0_LPCG 0x59d20000
  172 +#define AUD_PLL_CLK1_LPCG 0x59d30000
  173 +#define AUD_MCLKOUT0_LPCG 0x59d50000
  174 +#define AUD_MCLKOUT1_LPCG 0x59d60000
  175 +#define AUD_EDMA_1_LPCG 0x59df0000
  176 +
  177 +
  178 +/* Connectivity SS */
  179 +#define USDHC_0_LPCG 0x5B200000
  180 +#define USDHC_1_LPCG 0x5B210000
  181 +#define USDHC_2_LPCG 0x5B220000
  182 +#define ENET_0_LPCG 0x5B230000
  183 +#define ENET_1_LPCG 0x5B240000
  184 +#define DTCP_LPCG 0x5B250000
  185 +#define MLB_LPCG 0x5B260000
  186 +#define USB_2_LPCG 0x5B270000
  187 +#define USB_3_LPCG 0x5B280000
  188 +#define NAND_LPCG 0x5B290000
  189 +#define EDMA_LPCG 0x5B2A0000
  190 +
  191 +/* CM40 SS */
  192 +#define CM40_I2C_LPCG 0x37630000
  193 +
  194 +
  195 +#endif
arch/arm/include/asm/arch-imx8/lpcg.h
Diff comments   View file @ f1cf360
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __ASM_ARCH_IMX8_LPCG_H__
  8 +#define __ASM_ARCH_IMX8_LPCG_H__
  9 +
  10 +#if defined(CONFIG_IMX8QM)
  11 +#include "imx8qm_lpcg.h"
  12 +#elif defined(CONFIG_IMX8QXP)
  13 +#include "imx8qxp_lpcg.h"
  14 +#else
  15 +#error "No lpcg header"
  16 +#endif
  17 +
  18 +void LPCG_ClockOff(u32 lpcg_addr, u8 clk);
  19 +void LPCG_ClockOn(u32 lpcg_addr, u8 clk);
  20 +void LPCG_ClockAutoGate(u32 lpcg_addr, u8 clk);
  21 +void LPCG_AllClockOff(u32 lpcg_addr);
  22 +void LPCG_AllClockOn(u32 lpcg_addr);
  23 +void LPCG_AllClockAutoGate(u32 lpcg_addr);
  24 +
  25 +#endif /* __ASM_ARCH_IMX8_LPCG_H__ */
arch/arm/mach-imx/imx8/lpcg.c
Diff comments   View file @ f1cf360
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +#include <linux/errno.h>
  10 +#include <asm/arch/lpcg.h>
  11 +
  12 +#define LPCG_CLOCK_MASK 0x3U
  13 +#define LPCG_CLOCK_OFF 0x0U
  14 +#define LPCG_CLOCK_ON 0x2U
  15 +#define LPCG_CLOCK_AUTO 0x3U
  16 +#define LPCG_CLOCK_STOP 0x8U
  17 +
  18 +#define LPCG_ALL_CLOCK_OFF 0x00000000U
  19 +#define LPCG_ALL_CLOCK_ON 0x22222222U
  20 +#define LPCG_ALL_CLOCK_AUTO 0x33333333U
  21 +#define LPCG_ALL_CLOCK_STOP 0x88888888U
  22 +
  23 +void LPCG_ClockOff(u32 lpcg_addr, u8 clk)
  24 +{
  25 + u32 lpcgVal;
  26 +
  27 + /* Read from LPCG */
  28 + lpcgVal = readl((ulong)lpcg_addr);
  29 +
  30 + /* Modify */
  31 + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U));
  32 + lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U));
  33 +
  34 + /* Write to LPCG */
  35 + writel(lpcgVal, (ulong)lpcg_addr);
  36 +}
  37 +
  38 +void LPCG_ClockOn(u32 lpcg_addr, u8 clk)
  39 +{
  40 + u32 lpcgVal;
  41 +
  42 + /* Read from LPCG */
  43 + lpcgVal = readl((ulong)lpcg_addr);
  44 +
  45 + /* Modify */
  46 + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U));
  47 + lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U));
  48 +
  49 + /* Write to LPCG */
  50 + writel(lpcgVal, (ulong)lpcg_addr);
  51 +}
  52 +
  53 +void LPCG_ClockAutoGate(u32 lpcg_addr, u8 clk)
  54 +{
  55 + u32 lpcgVal;
  56 +
  57 + /* Read from LPCG */
  58 + lpcgVal = readl((ulong)lpcg_addr);
  59 +
  60 + /* Modify */
  61 + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U));
  62 + lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U));
  63 +
  64 + /* Write to LPCG */
  65 + writel(lpcgVal, (ulong)lpcg_addr);
  66 +}
  67 +
  68 +void LPCG_AllClockOff(u32 lpcg_addr)
  69 +{
  70 + /* Write to LPCG */
  71 + writel(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr);
  72 +}
  73 +
  74 +void LPCG_AllClockOn(u32 lpcg_addr)
  75 +{
  76 + /* Write to LPCG */
  77 + writel(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr);
  78 +
  79 + /* Wait for clocks to start */
  80 + while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U)
  81 + {
  82 + }
  83 +}
  84 +
  85 +void LPCG_AllClockAutoGate(u32 lpcg_addr)
  86 +{
  87 + /* Write to LPCG */
  88 + writel(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr);
  89 +}