Eric Lee / smarc-uboot

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Commit f229793a05f1039d9eba4286d9039403924cd1da

Authored by Ye Li
1 parent 11ea97fb3c
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-24192-3 pci: pcie_imx: Enable some LPCG clocks for iMX8 

Align the kernel's clocks enablement to enable the phy_per, misc_per
clocks for all iMX8, and enable pciex2_per and pcie_phy_pclk for
pcieb controller of iMX8QM.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 97b8d1c613f56b539328e421ba205f2221fc658e)

Showing 1 changed file with 105 additions and 39 deletions Side-by-side Diff

drivers/pci/pcie_imx.c
Diff comments   View file @ f229793
... ... @@ -252,8 +252,10 @@
252 252 #if CONFIG_IS_ENABLED(CLK)
253 253 struct clk pcie_bus;
254 254 struct clk pcie_phy;
  255 + struct clk pcie_phy_pclk;
255 256 struct clk pcie_inbound_axi;
256 257 struct clk pcie_per;
  258 + struct clk pciex2_per;
257 259 struct clk phy_per;
258 260 struct clk misc_per;
259 261 struct clk pcie;
260 262  
261 263  
262 264  
263 265  
264 266  
265 267  
266 268  
267 269  
268 270  
269 271  
270 272  
271 273  
272 274  
273 275  
274 276  
... ... @@ -962,62 +964,100 @@
962 964 printf("unable to enable pcie_phy clock\n");
963 965 goto err_pcie;
964 966 }
965   -#endif
966 967  
967   - if (priv->variant == IMX8QM
968   - || priv->variant == IMX8QXP) {
  968 + ret = clk_enable(&priv->pcie_bus);
  969 + if (ret) {
  970 + printf("unable to enable pcie_bus clock\n");
  971 + goto err_pcie_phy;
  972 + }
969 973  
970   -#if CONFIG_IS_ENABLED(CLK)
971   - ret = clk_enable(&priv->pcie_inbound_axi);
  974 + ret = clk_enable(&priv->pcie_inbound_axi);
  975 + if (ret) {
  976 + printf("unable to enable pcie_axi clock\n");
  977 + goto err_pcie_bus;
  978 + }
  979 + ret = clk_enable(&priv->pcie_per);
  980 + if (ret) {
  981 + printf("unable to enable pcie_per clock\n");
  982 + goto err_pcie_inbound_axi;
  983 + }
  984 +
  985 + ret = clk_enable(&priv->phy_per);
  986 + if (ret) {
  987 + printf("unable to enable phy_per clock\n");
  988 + goto err_pcie_per;
  989 + }
  990 +
  991 + ret = clk_enable(&priv->misc_per);
  992 + if (ret) {
  993 + printf("unable to enable misc_per clock\n");
  994 + goto err_phy_per;
  995 + }
  996 +
  997 + if (priv->variant == IMX8QM && priv->ctrl_id == 1) {
  998 + ret = clk_enable(&priv->pcie_phy_pclk);
972 999 if (ret) {
973   - printf("unable to enable pcie_axi clock\n");
974   - goto err_pcie_phy;
  1000 + printf("unable to enable pcie_phy_pclk clock\n");
  1001 + goto err_misc_per;
975 1002 }
976   - ret = clk_enable(&priv->pcie_per);
  1003 +
  1004 + ret = clk_enable(&priv->pciex2_per);
977 1005 if (ret) {
978   - printf("unable to enable pcie_per clock\n");
979   - clk_disable(&priv->pcie_inbound_axi);
980   - goto err_pcie_phy;
  1006 + printf("unable to enable pciex2_per clock\n");
  1007 + clk_disable(&priv->pcie_phy_pclk);
  1008 + goto err_misc_per;
981 1009 }
  1010 + }
982 1011 #endif
983   - /* allow the clocks to stabilize */
984   - udelay(200);
  1012 + /* allow the clocks to stabilize */
  1013 + udelay(200);
985 1014  
986   - /* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */
987   - for (i = 0; i < 100; i++) {
988   - val = IMX8QM_CSR_PCIEA_OFFSET
989   - + priv->ctrl_id * SZ_64K;
990   - imx_pcie_gpr_read(priv,
991   - val + IMX8QM_CSR_PCIE_STTS0_OFFSET,
992   - &tmp);
993   - if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0)
994   - break;
995   - udelay(10);
996   - }
  1015 + /* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */
  1016 + for (i = 0; i < 100; i++) {
  1017 + val = IMX8QM_CSR_PCIEA_OFFSET
  1018 + + priv->ctrl_id * SZ_64K;
  1019 + imx_pcie_gpr_read(priv,
  1020 + val + IMX8QM_CSR_PCIE_STTS0_OFFSET,
  1021 + &tmp);
  1022 + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0)
  1023 + break;
  1024 + udelay(10);
  1025 + }
997 1026  
998   - if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) != 0)
999   - printf("ERROR PM_REQ_CORE_RST is still set.\n");
  1027 + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) != 0)
  1028 + printf("ERROR PM_REQ_CORE_RST is still set.\n");
1000 1029  
1001   - /* wait for phy pll lock firstly. */
1002   - if (imx8_pcie_wait_for_phy_pll_lock(priv)) {
1003   - ret = -ENODEV;
1004   - goto err_ref_clk;;
1005   - }
  1030 + /* wait for phy pll lock firstly. */
  1031 + if (imx8_pcie_wait_for_phy_pll_lock(priv)) {
  1032 + ret = -ENODEV;
  1033 + goto err_ref_clk;;
  1034 + }
1006 1035  
1007   - if (dm_gpio_is_valid(&priv->reset_gpio)) {
1008   - dm_gpio_set_value(&priv->reset_gpio, 1);
1009   - mdelay(20);
1010   - dm_gpio_set_value(&priv->reset_gpio, 0);
1011   - mdelay(20);
1012   - }
1013   -
1014   - return 0;
  1036 + if (dm_gpio_is_valid(&priv->reset_gpio)) {
  1037 + dm_gpio_set_value(&priv->reset_gpio, 1);
  1038 + mdelay(20);
  1039 + dm_gpio_set_value(&priv->reset_gpio, 0);
  1040 + mdelay(20);
1015 1041 }
1016 1042  
  1043 + return 0;
  1044 +
1017 1045 err_ref_clk:
1018 1046 #if CONFIG_IS_ENABLED(CLK)
  1047 + if (priv->variant == IMX8QM && priv->ctrl_id == 1) {
  1048 + clk_disable(&priv->pciex2_per);
  1049 + clk_disable(&priv->pcie_phy_pclk);
  1050 + }
  1051 +err_misc_per:
  1052 + clk_disable(&priv->misc_per);
  1053 +err_phy_per:
  1054 + clk_disable(&priv->phy_per);
  1055 +err_pcie_per:
1019 1056 clk_disable(&priv->pcie_per);
  1057 +err_pcie_inbound_axi:
1020 1058 clk_disable(&priv->pcie_inbound_axi);
  1059 +err_pcie_bus:
  1060 + clk_disable(&priv->pcie_bus);
1021 1061 err_pcie_phy:
1022 1062 clk_disable(&priv->pcie_phy);
1023 1063 err_pcie:
... ... @@ -1620,6 +1660,32 @@
1620 1660 if (ret) {
1621 1661 printf("Failed to get pcie_inbound_axi clk\n");
1622 1662 return ret;
  1663 + }
  1664 +
  1665 + ret = clk_get_by_name(dev, "phy_per", &priv->phy_per);
  1666 + if (ret) {
  1667 + printf("Failed to get phy_per clk\n");
  1668 + return ret;
  1669 + }
  1670 +
  1671 + ret = clk_get_by_name(dev, "misc_per", &priv->misc_per);
  1672 + if (ret) {
  1673 + printf("Failed to get misc_per clk\n");
  1674 + return ret;
  1675 + }
  1676 +
  1677 + if (priv->variant == IMX8QM && priv->ctrl_id == 1) {
  1678 + ret = clk_get_by_name(dev, "pcie_phy_pclk", &priv->pcie_phy_pclk);
  1679 + if (ret) {
  1680 + printf("Failed to get pcie_phy_pclk clk\n");
  1681 + return ret;
  1682 + }
  1683 +
  1684 + ret = clk_get_by_name(dev, "pciex2_per", &priv->pciex2_per);
  1685 + if (ret) {
  1686 + printf("Failed to get pciex2_per clk\n");
  1687 + return ret;
  1688 + }
1623 1689 }
1624 1690 #endif
1625 1691 priv->iomuxc_gpr =