Eric Lee / smarc-uboot

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Commit f31be1ee0994a79dba7f8eb62ac4f08cafe687fd

Authored by BJ DevOps Team
2 parents f267d207ce ec9bce0ae4
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04 

* origin/ls_v2020.04:
  arm: dts: ls1028a: define QDS networking protocol combinations

Showing 16 changed files Side-by-side Diff

arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 1xxx
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC
  10 + * port 0 USXGMII.
  11 + */
  12 +&slot1 {
  13 + #include "fsl-sch-30842.dtsi"
  14 +};
  15 +
  16 +&enetc0 {
  17 + status = "okay";
  18 + phy-mode = "usxgmii";
  19 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
  20 +};
arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 6xxx
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using SCH-30842 cards with AQR112 PHY.
  10 + */
  11 +&slot1 {
  12 + #include "fsl-sch-30842.dtsi"
  13 +};
  14 +
  15 +&enetc0 {
  16 + status = "okay";
  17 + phy-mode = "sgmii-2500";
  18 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
  19 +};
arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 7777
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using a SCH-30841 card with AQR412 10G quad PHY.
  10 + *
  11 + * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
  12 + * Bottom port is port 0.
  13 + * Note that this is only usable for:
  14 + * - QDS boards WITHOUT lane B rework,
  15 + * - AQR412 card WITHOUT lane A -> lane C rework
  16 + *
  17 + * The following DTS assumes DIP SW5[1-3] = 000b.
  18 + */
  19 +&slot1 {
  20 +#include "fsl-sch-30841.dtsi"
  21 +};
  22 +
  23 +&ethsw_ports {
  24 + port@0 {
  25 + status = "okay";
  26 + phy-mode = "sgmii-2500";
  27 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
  28 + };
  29 + port@1 {
  30 + status = "okay";
  31 + phy-mode = "sgmii-2500";
  32 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
  33 + };
  34 + port@2 {
  35 + status = "okay";
  36 + phy-mode = "sgmii-2500";
  37 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
  38 + };
  39 + port@3 {
  40 + status = "okay";
  41 + phy-mode = "sgmii-2500";
  42 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
  43 + };
  44 +};
arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 7xx7
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +&slot1 {
  9 +#include "fsl-sch-30841.dtsi"
  10 +};
  11 +
  12 +&ethsw_ports {
  13 + port@0 {
  14 + status = "okay";
  15 + phy-mode = "sgmii-2500";
  16 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
  17 + };
  18 + port@3 {
  19 + status = "okay";
  20 + phy-mode = "sgmii-2500";
  21 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
  22 + };
  23 +};
arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 8xxx
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1.
  10 + */
  11 +&slot1 {
  12 + #include "fsl-sch-24801.dtsi"
  13 +};
  14 +
  15 +&enetc0 {
  16 + status = "okay";
  17 + phy-mode = "sgmii";
  18 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
  19 +};
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 9999
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
  10 + * LS1028A QDS boards with lane B rework require two cards for the 4 switch
  11 + * ports, QDS boards without the lane B rework only require one card.
  12 + *
  13 + * Switch ports are routed as follows:
  14 + * Port 0 goes to 1st port of VSC8234 quad card in slot 1,
  15 + * Port 1:
  16 + * - if the QDS has had lane B rework, it is 1st port in slot 2,
  17 + * - otherwise it is 2nd port in slot 1.
  18 + * Port 2:
  19 + * - if DIP SW5[1] = 0 it is 3rd port in slot 1,
  20 + * - otherwise it is 1st port in slot 3.
  21 + * Port 3:
  22 + * - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
  23 + * - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
  24 + * - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
  25 + *
  26 + * The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
  27 + * SCH-24801 cards are required in slots 1 and 2.
  28 + */
  29 +&slot1 {
  30 + #include "fsl-sch-24801.dtsi"
  31 +};
  32 +
  33 +&slot2 {
  34 + #include "fsl-sch-24801.dtsi"
  35 +};
  36 +
  37 +&ethsw_ports {
  38 + port@0 {
  39 + status = "okay";
  40 + phy-mode = "sgmii";
  41 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
  42 + };
  43 + port@1 {
  44 + status = "okay";
  45 + phy-mode = "sgmii";
  46 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
  47 + };
  48 + port@2 {
  49 + status = "okay";
  50 + phy-mode = "sgmii";
  51 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
  52 + };
  53 + port@3 {
  54 + status = "okay";
  55 + phy-mode = "sgmii";
  56 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
  57 + };
  58 +};
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 9999
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + *
  7 + */
  8 +
  9 +/*
  10 + * This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY.
  11 + *
  12 + * Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1.
  13 + * Top port is port 0.
  14 + *
  15 + * The following DTS assumes DIP SW5[1-3] = 000b.
  16 + */
  17 +
  18 +&slot1 {
  19 + #include "fsl-sch-24801.dtsi"
  20 +};
  21 +
  22 +&ethsw_ports {
  23 + port@0 {
  24 + status = "okay";
  25 + phy-mode = "sgmii";
  26 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
  27 + };
  28 + port@1 {
  29 + status = "okay";
  30 + phy-mode = "sgmii";
  31 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
  32 + };
  33 + port@2 {
  34 + status = "okay";
  35 + phy-mode = "sgmii";
  36 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
  37 + };
  38 + port@3 {
  39 + status = "okay";
  40 + phy-mode = "sgmii";
  41 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
  42 + };
  43 +};
arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW x3xx
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
  10 + * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
  11 + *
  12 + * We're including the normal .dsti file, not the reworked card .dtsi
  13 + * intentionally. We are using multiplexing of the 4 interfaces on a single
  14 + * lane and the rework doesn't actually disable any port. The rework is in fact
  15 + * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
  16 + * card.
  17 + */
  18 +&slot2 {
  19 +#include "fsl-sch-30841.dtsi"
  20 +};
  21 +
  22 +&ethsw_ports {
  23 + port@0 {
  24 + status = "okay";
  25 + phy-mode = "usxgmii";
  26 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
  27 + };
  28 + port@1 {
  29 + status = "okay";
  30 + phy-mode = "usxgmii";
  31 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
  32 + };
  33 + port@2 {
  34 + status = "okay";
  35 + phy-mode = "usxgmii";
  36 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
  37 + };
  38 + port@3 {
  39 + status = "okay";
  40 + phy-mode = "usxgmii";
  41 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
  42 + };
  43 +};
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW x5xx
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
  10 + * This is only available on LS1028A QDS boards with lane B rework.
  11 + */
  12 +&slot2 {
  13 + #include "fsl-sch-28021.dtsi"
  14 +};
  15 +
  16 +&ethsw_ports {
  17 + port@0 {
  18 + status = "okay";
  19 + phy-mode = "qsgmii";
  20 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
  21 + };
  22 + port@1 {
  23 + status = "okay";
  24 + phy-mode = "qsgmii";
  25 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
  26 + };
  27 + port@2 {
  28 + status = "okay";
  29 + phy-mode = "qsgmii";
  30 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
  31 + };
  32 + port@3 {
  33 + status = "okay";
  34 + phy-mode = "qsgmii";
  35 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
  36 + };
  37 +};
arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 7777
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +&slot2 {
  9 +#include "fsl-sch-30842.dtsi"
  10 +};
  11 +
  12 +&ethsw_ports {
  13 + port@1 {
  14 + status = "okay";
  15 + phy-mode = "sgmii-2500";
  16 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
  17 + };
  18 +};
arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * NXP LS1028A-QDS device tree fragment for RCW 7777
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +&slot3 {
  9 +#include "fsl-sch-30842.dtsi"
  10 +};
  11 +
  12 +&ethsw_ports {
  13 + port@2 {
  14 + status = "okay";
  15 + phy-mode = "sgmii-2500";
  16 + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
  17 + };
  18 +};
arch/arm/dts/fsl-ls1028a-qds.dtsi
Diff comments   View file @ f31be1e
... ... @@ -258,4 +258,7 @@
258 258 &mdio0 {
259 259 status = "okay";
260 260 };
  261 +
  262 +#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
  263 +#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"
arch/arm/dts/fsl-sch-24801.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * Device tree fragment for RCW SCH-24801 card
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards.
  10 + * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
  11 + * PHY addresses are 0x1c - 0x1f.
  12 + * On the card the first port is the top port (farthest from PEX connector).
  13 + */
  14 +phy@1c {
  15 + reg = <0x1c>;
  16 +};
  17 +
  18 +phy@1d {
  19 + reg = <0x1d>;
  20 +};
  21 +
  22 +phy@1e {
  23 + reg = <0x1e>;
  24 +};
  25 +
  26 +phy@1f {
  27 + reg = <0x1f>;
  28 +};
arch/arm/dts/fsl-sch-28021.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * Device tree fragment for RCW SCH-28021 card
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * SCH-28021 is a QSGMII add-on card used with various FSL QDS boards.
  10 + * It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
  11 + * single QSGMII lane.
  12 + * PHY addresses are 0x08 - 0x0b.
  13 + * On the card the first port is the top port (farthest from PEX connector).
  14 + */
  15 +phy@08 {
  16 + reg = <0x08>;
  17 +};
  18 +
  19 +phy@09 {
  20 + reg = <0x09>;
  21 +};
  22 +
  23 +phy@0a {
  24 + reg = <0x0a>;
  25 +};
  26 +
  27 +phy@0b {
  28 + reg = <0x0b>;
  29 +};
arch/arm/dts/fsl-sch-30841.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * Device tree fragment for RCW SCH-30841 card
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
  10 + * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
  11 + * together on a single lane or mapped 1:1 to serdes lanes.
  12 + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
  13 + * PHY addresses are 0x00 - 0x03.
  14 + * On the card the first port is the bottom port (closest to PEX connector).
  15 + */
  16 +phy@00 {
  17 + reg = <0x00>;
  18 + mdi-reversal = <1>;
  19 + smb-addr = <0x25>;
  20 +};
  21 +
  22 +phy@01 {
  23 + reg = <0x01>;
  24 + mdi-reversal = <1>;
  25 + smb-addr = <0x26>;
  26 +};
  27 +
  28 +phy@02 {
  29 + reg = <0x02>;
  30 + mdi-reversal = <1>;
  31 + smb-addr = <0x27>;
  32 +};
  33 +
  34 +phy@03 {
  35 + reg = <0x03>;
  36 + mdi-reversal = <1>;
  37 + smb-addr = <0x28>;
  38 +};
arch/arm/dts/fsl-sch-30842.dtsi
Diff comments   View file @ f31be1e
  1 +// SPDX-License-Identifier: GPL-2.0+ OR X11
  2 +/*
  3 + * Device tree fragment for RCW SCH-30842 card
  4 + *
  5 + * Copyright 2019-2021 NXP Semiconductors
  6 + */
  7 +
  8 +/*
  9 + * SCH-30842 is a single port add-on card used with various FSL QDS boards.
  10 + * It integrates a AQR112 PHY, which supports several protocols - SGMII,
  11 + * SGMII-2500, USXGMII, XFI.
  12 + * PHY address is 0x02.
  13 + */
  14 +phy@02 {
  15 + reg = <0x02>;
  16 + mdi-reversal = <1>;
  17 + smb-addr = <0x25>;
  18 +};