diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cb2c7f8..52f27ba 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -472,6 +472,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
 		fsl-imx8mq-ddr3l-arm2.dtb \
 		fsl-imx8mq-ddr4-arm2.dtb \
 		fsl-imx8mq-phanbell.dtb \
+                fsl-smarcimx8mq.dtb \
 		fsl-imx8mm-ddr3l-val.dtb \
 		fsl-imx8mm-ddr4-evk.dtb \
 		fsl-imx8mm-ddr4-val.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
index bf32df6..0aaf171 100644
--- a/arch/arm/dts/fsl-imx8mq.dtsi
+++ b/arch/arm/dts/fsl-imx8mq.dtsi
@@ -153,6 +153,17 @@
 		#power-domain-cells = <1>;
 	};
 
+        pwm1: pwm@30660000 {
+                compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+                reg = <0x0 0x30660000 0x0 0x10000>;
+                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
+                         <&clk IMX8MQ_CLK_PWM1_ROOT>;
+                clock-names = "ipg", "per";
+                #pwm-cells = <2>;
+                status = "disabled";
+        };
+
 	pwm2: pwm@30670000 {
 		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x30670000 0x0 0x10000>;
@@ -164,6 +175,28 @@
 		status = "disabled";
 	};
 
+        pwm3: pwm@30680000 {
+                compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+                reg = <0x0 0x30680000 0x0 0x10000>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
+                         <&clk IMX8MQ_CLK_PWM3_ROOT>;
+                clock-names = "ipg", "per";
+                #pwm-cells = <2>;
+                status = "disabled";
+        };
+
+        pwm4: pwm@30690000 {
+                compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+                reg = <0x0 0x30690000 0x0 0x10000>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
+                         <&clk IMX8MQ_CLK_PWM4_ROOT>;
+                clock-names = "ipg", "per";
+                #pwm-cells = <2>;
+                status = "disabled";
+        };
+
 	gpio1: gpio@30200000 {
 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 		reg = <0x0 0x30200000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-smarcimx8mq.dts b/arch/arm/dts/fsl-smarcimx8mq.dts
new file mode 100644
index 0000000..8485d5f
--- /dev/null
+++ b/arch/arm/dts/fsl-smarcimx8mq.dts
@@ -0,0 +1,672 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+	model = "Embedian SMARC-iMX8M Computer on Module";
+	compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 1000000 0>;
+                brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+                                     10 11 12 13 14 15 16 17 18 19
+                                     20 21 22 23 24 25 26 27 28 29
+                                     30 31 32 33 34 35 36 37 38 39
+                                     40 41 42 43 44 45 46 47 48 49
+                                     50 51 52 53 54 55 56 57 58 59
+                                     60 61 62 63 64 65 66 67 68 69
+                                     70 71 72 73 74 75 76 77 78 79
+                                     80 81 82 83 84 85 86 87 88 89
+                                     90 91 92 93 94 95 96 97 98 99
+                                    100>;
+                default-brightness-level = <80>;
+                status = "disabled";
+        };
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	smarc-imx8mq {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+			>;
+		};
+
+               pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x4000007f
+                                MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x4000007f
+                        >;
+                };
+
+                pinctrl_i2c4: i2c4grp {
+                        fsl,pins = <
+                                MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x4000007f
+                                MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x4000007f
+                        >;
+                };
+
+
+		pinctrl_pcie0: pcie0grp {
+			fsl,pins = <
+                                MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3       0x16
+			>;
+		};
+
+		pinctrl_pcie1: pcie1grp {
+			fsl,pins = <
+                                MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4       0x16
+			>;
+		};
+
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+                                MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT     0x16
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
+				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
+                                MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B    0x82
+				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
+				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
+				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
+				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
+
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
+				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
+			>;
+		};
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x79
+                                MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x79
+                                MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11             0x19    /* RTS */
+                                MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10             0x19    /* CTS */
+
+                        >;
+                };
+
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX             0x79
+                                MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX             0x79
+                        >;
+                };
+
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX             0x79
+                                MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX             0x79
+                        >;
+                };
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x8d
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x9f
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+                                MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20          0x41
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
+				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
+				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+        interrupt-parent = <&gpio1>;
+        interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+        s35390a: s35390a@30 {
+                compatible = "s35390a";
+                reg = <0x30>;
+        };
+
+        cape_eeprom0: cape_eeprom@57 {
+                compatible = "at,24c256";
+                reg = <0x57>;
+        };
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+        baseboard_eeprom: baseboard_eeprom@50 {
+                compatible = "at,24c256";
+                reg = <0x50>;
+        };
+
+        dsi_lvds_bridge: sn65dsi84@2c {
+                status = "disabled";
+                reg = <0x2c>;
+                compatible = "ti,sn65dsi84";
+                enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+
+                /* AUO G070VW01 7-inch 800x480 LVDS Display */
+                sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
+                                        0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
+                                        0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
+                                        0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
+                                        0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
+                                        0x3C 0x3D 0x3E 0xE0 0x0D>;
+
+                sn65dsi84,values =    < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
+                                        0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
+                                        0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
+                                        0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
+                                        0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                                        0x00 0x00 0x00 0x01 0x01>;
+
+                /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
+                /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
+                                        0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
+                                        0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
+                                        0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
+                                        0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
+                                        0x3C 0x3D 0x3E 0xE0 0x0D>;
+
+                sn65dsi84,values =    < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
+                                        0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
+                                        0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
+                                        0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
+                                        0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                                        0x00 0x00 0x00 0x01 0x01>;*/
+
+                /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
+                /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
+                                        0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
+                                        0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
+                                        0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
+                                        0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
+                                        0x3C 0x3D 0x3E 0xE0 0x0D>;
+
+                sn65dsi84,values =    < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
+                                        0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
+                                        0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
+                                        0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
+                                        0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+                                        0x00 0x00 0x00 0x01 0x01>;*/
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+};
+
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c4>;
+        status = "okay";
+};
+
+&pcie0{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie1{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie1>;
+	reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+	disp-dev = "mipi_dsi_northwest";
+	display = <&display0>;
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+        port@0 {
+                lcdif_mipi_dsi: mipi-dsi-endpoint {
+                        remote-endpoint = <&mipi_dsi_in>;
+                };
+        };
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+};
+
+&mipi_dsi {
+	reset = <&src>;
+	mux-sel = <&gpr>;	/* lcdif or dcss */
+	status = "okay";
+
+        port@1 {
+                mipi_dsi_in: endpoint {
+                        remote-endpoint = <&lcdif_mipi_dsi>;
+                };
+        };
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
+        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	status = "okay";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
+        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "disabled";
+};
+
+&usb_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
+			<&clk IMX8MQ_AUDIO_PLL1>,
+			<&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
+			<&clk IMX8MQ_CLK_SAI2_DIV>;
+	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 09779cd..0365d2e 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -38,6 +38,12 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select SUPPORT_SPL
 
+config TARGET_SMARCIMX8MQ
+        bool "smarcimx8mq"
+        select IMX8MQ
+        select SUPPORT_SPL
+        select IMX8M_LPDDR4
+
 config TARGET_IMX8MQ_AIY
 	bool "imx8mq_aiy"
 	select IMX8MQ
@@ -74,6 +80,7 @@ config SYS_SOC
 source "board/freescale/imx8mq_evk/Kconfig"
 source "board/freescale/imx8mq_arm2/Kconfig"
 source "board/freescale/imx8mq_phanbell/Kconfig"
+source "board/embedian/smarcimx8mq/Kconfig"
 source "board/freescale/imx8mq_aiy/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
 source "board/freescale/imx8mm_val/Kconfig"
diff --git a/board/embedian/embedian/smarcimx8mq/Kconfig b/board/embedian/embedian/smarcimx8mq/Kconfig
new file mode 100644
index 0000000..91b8098
--- /dev/null
+++ b/board/embedian/embedian/smarcimx8mq/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMARCIMX8MQ
+
+config SYS_BOARD
+	default "smarcimx8mq"
+
+config SYS_VENDOR
+	default "embedian"
+
+config SYS_CONFIG_NAME
+	default "smarcimx8mq"
+
+endif
diff --git a/board/embedian/embedian/smarcimx8mq/Makefile b/board/embedian/embedian/smarcimx8mq/Makefile
new file mode 100644
index 0000000..4b53f01
--- /dev/null
+++ b/board/embedian/embedian/smarcimx8mq/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += smarcimx8mq.o
+
+obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/embedian/embedian/smarcimx8mq/lpddr4_timing.c b/board/embedian/embedian/smarcimx8mq/lpddr4_timing.c
new file mode 100644
index 0000000..caea7cd
--- /dev/null
+++ b/board/embedian/embedian/smarcimx8mq/lpddr4_timing.c
@@ -0,0 +1,3459 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/imx8m_ddr.h>
+#include <common.h>
+#if defined(CONFIG_2GB_LPDDR4)
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa1080020},
+	{0x3d400028,0x0},
+	{0x3d400020,0x203},
+	{0x3d400024,0x3e800},
+	{0x3d400064,0x6100e0},
+	{0x3d4000d0,0xc003061c},
+	{0x3d4000d4,0x9e0000},
+	{0x3d4000dc,0xd4002d},
+	{0x3d4000e0,0x310008},
+	{0x3d4000e8,0x66004a},
+	{0x3d4000ec,0x16004a},
+	{0x3d400100,0x1a201b22},
+	{0x3d400104,0x60633},
+	{0x3d40010c,0xc0c000},
+	{0x3d400110,0xf04080f},
+	{0x3d400114,0x2040c0c},
+	{0x3d400118,0x1010007},
+	{0x3d40011c,0x401},
+	{0x3d400130,0x20600},
+	{0x3d400134,0xc100002},
+	{0x3d400138,0xe6},
+	{0x3d400144,0xa00050},
+	{0x3d400180,0xc3200018},
+	{0x3d400184,0x28061a8},
+	{0x3d400188,0x0},
+	{0x3d400190,0x497820a},
+	{0x3d400194,0x80303},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001b4,0x170a},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0x639},
+	{0x3d400108,0x70e1617},
+	{0x3d400200,0x1f},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0x7070707},
+	{0x3d402020,0x1},
+	{0x3d402024,0xd0c0},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0x14002f},
+	{0x3d4020dc,0x940009},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004a},
+	{0x3d4020ec,0x16004a},
+	{0x3d402100,0xb070508},
+	{0x3d402104,0x3040b},
+	{0x3d402108,0x305090c},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x4040204},
+	{0x3d402114,0x2030303},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x31},
+	{0x3d402144,0x220011},
+	{0x3d402180,0xc0a70006},
+	{0x3d402190,0x3858202},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x502},
+	{0x3d400244,0x0},
+	{0x3d400250,0x29001505},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x5900575b},
+	{0x3d400264,0x90000096},
+	{0x3d40026c,0x1000012c},
+	{0x3d400300,0x16},
+	{0x3d400304,0x0},
+	{0x3d40030c,0x0},
+	{0x3d400320,0x1},
+	{0x3d40036c,0x11},
+	{0x3d400400,0x111},
+	{0x3d400404,0x10f3},
+	{0x3d400408,0x72ff},
+	{0x3d400490,0x1},
+	{0x3d400494,0xe00},
+	{0x3d400498,0x62ffff},
+	{0x3d40049c,0xe00},
+	{0x3d4004a0,0xffff},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x2},
+	{0x110a3,0x3},
+	{0x110a4,0x4},
+	{0x110a5,0x7},
+	{0x110a6,0x6},
+	{0x110a7,0x5},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x2},
+	{0x120a3,0x3},
+	{0x120a4,0x4},
+	{0x120a5,0x5},
+	{0x120a6,0x6},
+	{0x120a7,0x7},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x20110,0x2},
+	{0x20111,0x3},
+	{0x20112,0x4},
+	{0x20113,0x5},
+	{0x20114,0x0},
+	{0x20115,0x1},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0x19},
+	{0x1200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x1},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x3},
+	{0x120056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x320},
+	{0x120008,0xa7},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x200f0,0x0},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5555},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x200c7,0x80},
+	{0x1200c7,0x80},
+	{0x200ca,0x106},
+	{0x1200ca,0x106},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },  
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },  
+	{ 0x10043, 0x0 },  
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },  
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },  
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },  
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },  
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },  
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },  
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },  
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },       
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },    
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },    
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },    
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },    
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },    
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },    
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },    
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },    
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },    
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },  
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },  
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },  
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },  
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },  
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },  
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },  
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },  
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },  
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },  
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },  
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },  
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },  
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },  
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },  
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },  
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },  
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },  
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },  
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },  
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },  
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },  
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },  
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },  
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },  
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 }, 
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 }, 
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 }, 
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 }, 
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 }, 
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 }, 
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 }, 
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 }, 
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 }, 
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 }, 
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 }, 
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 }, 
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 }, 
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 }, 
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 }, 
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 }, 
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 }, 
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 }, 
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 }, 
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 }, 
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 }, 
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 }, 
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 }, 
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 }, 
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 }, 
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 }, 
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 }, 
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 }, 
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 }, 
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 }, 
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 }, 
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 }, 
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 }, 
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 }, 
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 }, 
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 }, 
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 }, 
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 }, 
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 }, 
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 }, 
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 }, 
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 }, 
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 }, 
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 }, 
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 }, 
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 }, 
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 }, 
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 }, 
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 }, 
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 }, 
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 }, 
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 }, 
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 }, 
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 }, 
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 }, 
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 }, 
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 }, 
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 }, 
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 }, 
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 }, 
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 }, 
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 }, 
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 }, 
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 }, 
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 }, 
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 }, 
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 }, 
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 }, 
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 }, 
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 }, 
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 }, 
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 }, 
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 }, 
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 }, 
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 }, 
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 }, 
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 }, 
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 }, 
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 }, 
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 }, 
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 }, 
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 }, 
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 }, 
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 }, 
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 }, 
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 }, 
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 }, 
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 }, 
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 }, 
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 }, 
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 }, 
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 }, 
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 }, 
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 }, 
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 }, 
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 }, 
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 }, 
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 }, 
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 }, 
+	{ 0x20073, 0x0 }, 
+	{ 0x20074, 0x0 }, 
+	{ 0x100aa, 0x0 }, 
+	{ 0x110aa, 0x0 }, 
+	{ 0x120aa, 0x0 }, 
+	{ 0x130aa, 0x0 }, 
+	{ 0x20010, 0x0 }, 
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 }, 
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 }, 
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 }, 
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 }, 
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 }, 
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 }, 
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 }, 
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 }, 
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 }, 
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 }, 
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 }, 
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 }, 
+	{ 0x130a5, 0x0 }, 
+	{ 0x130a6, 0x0 }, 
+	{ 0x130a7, 0x0 }, 
+	{ 0x2007c, 0x0 }, 
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 }, 
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 }, 
+	{ 0x400c0, 0x0 }, 
+	{ 0x90201, 0x0 }, 
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 }, 
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 }, 
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 }, 
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 }, 
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 }, 
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 }, 
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 }, 
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 }, 
+	{ 0x10162, 0x0 }, 
+	{ 0x10262, 0x0 }, 
+	{ 0x10362, 0x0 }, 
+	{ 0x10462, 0x0 }, 
+	{ 0x10562, 0x0 }, 
+	{ 0x10662, 0x0 }, 
+	{ 0x10762, 0x0 }, 
+	{ 0x10862, 0x0 }, 
+	{ 0x11062, 0x0 }, 
+	{ 0x11162, 0x0 }, 
+	{ 0x11262, 0x0 }, 
+	{ 0x11362, 0x0 }, 
+	{ 0x11462, 0x0 }, 
+	{ 0x11562, 0x0 }, 
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x1},
+	{0x54003,0x29c},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x994},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x994},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x9400},
+	{0x54033,0x3109},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0x9400},
+	{0x54039,0x3109},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x110},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
+	{0x90043,0x149},
+	{0x90044,0x4f},
+	{0x90045,0x630},
+	{0x90046,0x179},
+	{0x90047,0x8},
+	{0x90048,0xe0},
+	{0x90049,0x109},
+	{0x9004a,0x0},
+	{0x9004b,0x7c8},
+	{0x9004c,0x109},
+	{0x9004d,0x0},
+	{0x9004e,0x1},
+	{0x9004f,0x8},
+	{0x90050,0x0},
+	{0x90051,0x45a},
+	{0x90052,0x9},
+	{0x90053,0x0},
+	{0x90054,0x448},
+	{0x90055,0x109},
+	{0x90056,0x40},
+	{0x90057,0x630},
+	{0x90058,0x179},
+	{0x90059,0x1},
+	{0x9005a,0x618},
+	{0x9005b,0x109},
+	{0x9005c,0x40c0},
+	{0x9005d,0x630},
+	{0x9005e,0x149},
+	{0x9005f,0x8},
+	{0x90060,0x4},
+	{0x90061,0x48},
+	{0x90062,0x4040},
+	{0x90063,0x630},
+	{0x90064,0x149},
+	{0x90065,0x0},
+	{0x90066,0x4},
+	{0x90067,0x48},
+	{0x90068,0x40},
+	{0x90069,0x630},
+	{0x9006a,0x149},
+	{0x9006b,0x10},
+	{0x9006c,0x4},
+	{0x9006d,0x18},
+	{0x9006e,0x0},
+	{0x9006f,0x4},
+	{0x90070,0x78},
+	{0x90071,0x549},
+	{0x90072,0x630},
+	{0x90073,0x159},
+	{0x90074,0xd49},
+	{0x90075,0x630},
+	{0x90076,0x159},
+	{0x90077,0x94a},
+	{0x90078,0x630},
+	{0x90079,0x159},
+	{0x9007a,0x441},
+	{0x9007b,0x630},
+	{0x9007c,0x149},
+	{0x9007d,0x42},
+	{0x9007e,0x630},
+	{0x9007f,0x149},
+	{0x90080,0x1},
+	{0x90081,0x630},
+	{0x90082,0x149},
+	{0x90083,0x0},
+	{0x90084,0xe0},
+	{0x90085,0x109},
+	{0x90086,0xa},
+	{0x90087,0x10},
+	{0x90088,0x109},
+	{0x90089,0x9},
+	{0x9008a,0x3c0},
+	{0x9008b,0x149},
+	{0x9008c,0x9},
+	{0x9008d,0x3c0},
+	{0x9008e,0x159},
+	{0x9008f,0x18},
+	{0x90090,0x10},
+	{0x90091,0x109},
+	{0x90092,0x0},
+	{0x90093,0x3c0},
+	{0x90094,0x109},
+	{0x90095,0x18},
+	{0x90096,0x4},
+	{0x90097,0x48},
+	{0x90098,0x18},
+	{0x90099,0x4},
+	{0x9009a,0x58},
+	{0x9009b,0xa},
+	{0x9009c,0x10},
+	{0x9009d,0x109},
+	{0x9009e,0x2},
+	{0x9009f,0x10},
+	{0x900a0,0x109},
+	{0x900a1,0x5},
+	{0x900a2,0x7c0},
+	{0x900a3,0x109},
+	{0x900a4,0x10},
+	{0x900a5,0x10},
+	{0x900a6,0x109},
+	{0x40000,0x811},
+	{0x40020,0x880},
+	{0x40040,0x0},
+	{0x40060,0x0},
+	{0x40001,0x4008},
+	{0x40021,0x83},
+	{0x40041,0x4f},
+	{0x40061,0x0},
+	{0x40002,0x4040},
+	{0x40022,0x83},
+	{0x40042,0x51},
+	{0x40062,0x0},
+	{0x40003,0x811},
+	{0x40023,0x880},
+	{0x40043,0x0},
+	{0x40063,0x0},
+	{0x40004,0x720},
+	{0x40024,0xf},
+	{0x40044,0x1740},
+	{0x40064,0x0},
+	{0x40005,0x16},
+	{0x40025,0x83},
+	{0x40045,0x4b},
+	{0x40065,0x0},
+	{0x40006,0x716},
+	{0x40026,0xf},
+	{0x40046,0x2001},
+	{0x40066,0x0},
+	{0x40007,0x716},
+	{0x40027,0xf},
+	{0x40047,0x2800},
+	{0x40067,0x0},
+	{0x40008,0x716},
+	{0x40028,0xf},
+	{0x40048,0xf00},
+	{0x40068,0x0},
+	{0x40009,0x720},
+	{0x40029,0xf},
+	{0x40049,0x1400},
+	{0x40069,0x0},
+	{0x4000a,0xe08},
+	{0x4002a,0xc15},
+	{0x4004a,0x0},
+	{0x4006a,0x0},
+	{0x4000b,0x623},
+	{0x4002b,0x15},
+	{0x4004b,0x0},
+	{0x4006b,0x0},
+	{0x4000c,0x4028},
+	{0x4002c,0x80},
+	{0x4004c,0x0},
+	{0x4006c,0x0},
+	{0x4000d,0xe08},
+	{0x4002d,0xc1a},
+	{0x4004d,0x0},
+	{0x4006d,0x0},
+	{0x4000e,0x623},
+	{0x4002e,0x1a},
+	{0x4004e,0x0},
+	{0x4006e,0x0},
+	{0x4000f,0x4040},
+	{0x4002f,0x80},
+	{0x4004f,0x0},
+	{0x4006f,0x0},
+	{0x40010,0x2604},
+	{0x40030,0x15},
+	{0x40050,0x0},
+	{0x40070,0x0},
+	{0x40011,0x708},
+	{0x40031,0x5},
+	{0x40051,0x0},
+	{0x40071,0x2002},
+	{0x40012,0x8},
+	{0x40032,0x80},
+	{0x40052,0x0},
+	{0x40072,0x0},
+	{0x40013,0x2604},
+	{0x40033,0x1a},
+	{0x40053,0x0},
+	{0x40073,0x0},
+	{0x40014,0x708},
+	{0x40034,0xa},
+	{0x40054,0x0},
+	{0x40074,0x2002},
+	{0x40015,0x4040},
+	{0x40035,0x80},
+	{0x40055,0x0},
+	{0x40075,0x0},
+	{0x40016,0x60a},
+	{0x40036,0x15},
+	{0x40056,0x1200},
+	{0x40076,0x0},
+	{0x40017,0x61a},
+	{0x40037,0x15},
+	{0x40057,0x1300},
+	{0x40077,0x0},
+	{0x40018,0x60a},
+	{0x40038,0x1a},
+	{0x40058,0x1200},
+	{0x40078,0x0},
+	{0x40019,0x642},
+	{0x40039,0x1a},
+	{0x40059,0x1300},
+	{0x40079,0x0},
+	{0x4001a,0x4808},
+	{0x4003a,0x880},
+	{0x4005a,0x0},
+	{0x4007a,0x0},
+	{0x900a7,0x0},
+	{0x900a8,0x790},
+	{0x900a9,0x11a},
+	{0x900aa,0x8},
+	{0x900ab,0x7aa},
+	{0x900ac,0x2a},
+	{0x900ad,0x10},
+	{0x900ae,0x7b2},
+	{0x900af,0x2a},
+	{0x900b0,0x0},
+	{0x900b1,0x7c8},
+	{0x900b2,0x109},
+	{0x900b3,0x10},
+	{0x900b4,0x2a8},
+	{0x900b5,0x129},
+	{0x900b6,0x8},
+	{0x900b7,0x370},
+	{0x900b8,0x129},
+	{0x900b9,0xa},
+	{0x900ba,0x3c8},
+	{0x900bb,0x1a9},
+	{0x900bc,0xc},
+	{0x900bd,0x408},
+	{0x900be,0x199},
+	{0x900bf,0x14},
+	{0x900c0,0x790},
+	{0x900c1,0x11a},
+	{0x900c2,0x8},
+	{0x900c3,0x4},
+	{0x900c4,0x18},
+	{0x900c5,0xe},
+	{0x900c6,0x408},
+	{0x900c7,0x199},
+	{0x900c8,0x8},
+	{0x900c9,0x8568},
+	{0x900ca,0x108},
+	{0x900cb,0x18},
+	{0x900cc,0x790},
+	{0x900cd,0x16a},
+	{0x900ce,0x8},
+	{0x900cf,0x1d8},
+	{0x900d0,0x169},
+	{0x900d1,0x10},
+	{0x900d2,0x8558},
+	{0x900d3,0x168},
+	{0x900d4,0x70},
+	{0x900d5,0x788},
+	{0x900d6,0x16a},
+	{0x900d7,0x1ff8},
+	{0x900d8,0x85a8},
+	{0x900d9,0x1e8},
+	{0x900da,0x50},
+	{0x900db,0x798},
+	{0x900dc,0x16a},
+	{0x900dd,0x60},
+	{0x900de,0x7a0},
+	{0x900df,0x16a},
+	{0x900e0,0x8},
+	{0x900e1,0x8310},
+	{0x900e2,0x168},
+	{0x900e3,0x8},
+	{0x900e4,0xa310},
+	{0x900e5,0x168},
+	{0x900e6,0xa},
+	{0x900e7,0x408},
+	{0x900e8,0x169},
+	{0x900e9,0x6e},
+	{0x900ea,0x0},
+	{0x900eb,0x68},
+	{0x900ec,0x0},
+	{0x900ed,0x408},
+	{0x900ee,0x169},
+	{0x900ef,0x0},
+	{0x900f0,0x8310},
+	{0x900f1,0x168},
+	{0x900f2,0x0},
+	{0x900f3,0xa310},
+	{0x900f4,0x168},
+	{0x900f5,0x1ff8},
+	{0x900f6,0x85a8},
+	{0x900f7,0x1e8},
+	{0x900f8,0x68},
+	{0x900f9,0x798},
+	{0x900fa,0x16a},
+	{0x900fb,0x78},
+	{0x900fc,0x7a0},
+	{0x900fd,0x16a},
+	{0x900fe,0x68},
+	{0x900ff,0x790},
+	{0x90100,0x16a},
+	{0x90101,0x8},
+	{0x90102,0x8b10},
+	{0x90103,0x168},
+	{0x90104,0x8},
+	{0x90105,0xab10},
+	{0x90106,0x168},
+	{0x90107,0xa},
+	{0x90108,0x408},
+	{0x90109,0x169},
+	{0x9010a,0x58},
+	{0x9010b,0x0},
+	{0x9010c,0x68},
+	{0x9010d,0x0},
+	{0x9010e,0x408},
+	{0x9010f,0x169},
+	{0x90110,0x0},
+	{0x90111,0x8b10},
+	{0x90112,0x168},
+	{0x90113,0x0},
+	{0x90114,0xab10},
+	{0x90115,0x168},
+	{0x90116,0x0},
+	{0x90117,0x1d8},
+	{0x90118,0x169},
+	{0x90119,0x80},
+	{0x9011a,0x790},
+	{0x9011b,0x16a},
+	{0x9011c,0x18},
+	{0x9011d,0x7aa},
+	{0x9011e,0x6a},
+	{0x9011f,0xa},
+	{0x90120,0x0},
+	{0x90121,0x1e9},
+	{0x90122,0x8},
+	{0x90123,0x8080},
+	{0x90124,0x108},
+	{0x90125,0xf},
+	{0x90126,0x408},
+	{0x90127,0x169},
+	{0x90128,0xc},
+	{0x90129,0x0},
+	{0x9012a,0x68},
+	{0x9012b,0x9},
+	{0x9012c,0x0},
+	{0x9012d,0x1a9},
+	{0x9012e,0x0},
+	{0x9012f,0x408},
+	{0x90130,0x169},
+	{0x90131,0x0},
+	{0x90132,0x8080},
+	{0x90133,0x108},
+	{0x90134,0x8},
+	{0x90135,0x7aa},
+	{0x90136,0x6a},
+	{0x90137,0x0},
+	{0x90138,0x8568},
+	{0x90139,0x108},
+	{0x9013a,0xb7},
+	{0x9013b,0x790},
+	{0x9013c,0x16a},
+	{0x9013d,0x1f},
+	{0x9013e,0x0},
+	{0x9013f,0x68},
+	{0x90140,0x8},
+	{0x90141,0x8558},
+	{0x90142,0x168},
+	{0x90143,0xf},
+	{0x90144,0x408},
+	{0x90145,0x169},
+	{0x90146,0xc},
+	{0x90147,0x0},
+	{0x90148,0x68},
+	{0x90149,0x0},
+	{0x9014a,0x408},
+	{0x9014b,0x169},
+	{0x9014c,0x0},
+	{0x9014d,0x8558},
+	{0x9014e,0x168},
+	{0x9014f,0x8},
+	{0x90150,0x3c8},
+	{0x90151,0x1a9},
+	{0x90152,0x3},
+	{0x90153,0x370},
+	{0x90154,0x129},
+	{0x90155,0x20},
+	{0x90156,0x2aa},
+	{0x90157,0x9},
+	{0x90158,0x0},
+	{0x90159,0x400},
+	{0x9015a,0x10e},
+	{0x9015b,0x8},
+	{0x9015c,0xe8},
+	{0x9015d,0x109},
+	{0x9015e,0x0},
+	{0x9015f,0x8140},
+	{0x90160,0x10c},
+	{0x90161,0x10},
+	{0x90162,0x8138},
+	{0x90163,0x10c},
+	{0x90164,0x8},
+	{0x90165,0x7c8},
+	{0x90166,0x101},
+	{0x90167,0x8},
+	{0x90168,0x0},
+	{0x90169,0x8},
+	{0x9016a,0x8},
+	{0x9016b,0x448},
+	{0x9016c,0x109},
+	{0x9016d,0xf},
+	{0x9016e,0x7c0},
+	{0x9016f,0x109},
+	{0x90170,0x0},
+	{0x90171,0xe8},
+	{0x90172,0x109},
+	{0x90173,0x47},
+	{0x90174,0x630},
+	{0x90175,0x109},
+	{0x90176,0x8},
+	{0x90177,0x618},
+	{0x90178,0x109},
+	{0x90179,0x8},
+	{0x9017a,0xe0},
+	{0x9017b,0x109},
+	{0x9017c,0x0},
+	{0x9017d,0x7c8},
+	{0x9017e,0x109},
+	{0x9017f,0x8},
+	{0x90180,0x8140},
+	{0x90181,0x10c},
+	{0x90182,0x0},
+	{0x90183,0x1},
+	{0x90184,0x8},
+	{0x90185,0x8},
+	{0x90186,0x4},
+	{0x90187,0x8},
+	{0x90188,0x8},
+	{0x90189,0x7c8},
+	{0x9018a,0x101},
+	{0x90006,0x0},
+	{0x90007,0x0},
+	{0x90008,0x8},
+	{0x90009,0x0},
+	{0x9000a,0x0},
+	{0x9000b,0x0},
+	{0xd00e7,0x400},
+	{0x90017,0x0},
+	{0x9001f,0x2a},
+	{0x90026,0x6a},
+	{0x400d0,0x0},
+	{0x400d1,0x101},
+	{0x400d2,0x105},
+	{0x400d3,0x107},
+	{0x400d4,0x10f},
+	{0x400d5,0x202},
+	{0x400d6,0x20a},
+	{0x400d7,0x20b},
+	{0x2003a,0x2},
+	{0x2000b,0x64},
+	{0x2000c,0xc8},
+	{0x2000d,0x7d0},
+	{0x2000e,0x2c},
+	{0x12000b,0x14},
+	{0x12000c,0x29},
+	{0x12000d,0x1a1},
+	{0x12000e,0x10},
+	{0x9000c,0x0},
+	{0x9000d,0x173},
+	{0x9000e,0x60},
+	{0x9000f,0x6110},
+	{0x90010,0x2152},
+	{0x90011,0xdfbd},
+	{0x90012,0x60},
+	{0x90013,0x6152},
+	{0x20010,0x5a},
+	{0x20011,0x3},
+	{0x120010,0x5a},
+	{0x120011,0x3},
+	{0x40080,0xe0},
+	{0x40081,0x12},
+	{0x40082,0xe0},
+	{0x40083,0x12},
+	{0x40084,0xe0},
+	{0x40085,0x12},
+	{0x140080,0xe0},
+	{0x140081,0x12},
+	{0x140082,0xe0},
+	{0x140083,0x12},
+	{0x140084,0xe0},
+	{0x140085,0x12},
+	{0x400fd,0xf},
+	{0x10011,0x1},
+	{0x10012,0x1},
+	{0x10013,0x180},
+	{0x10018,0x1},
+	{0x10002,0x6209},
+	{0x100b2,0x1},
+	{0x101b4,0x1},
+	{0x102b4,0x1},
+	{0x103b4,0x1},
+	{0x104b4,0x1},
+	{0x105b4,0x1},
+	{0x106b4,0x1},
+	{0x107b4,0x1},
+	{0x108b4,0x1},
+	{0x11011,0x1},
+	{0x11012,0x1},
+	{0x11013,0x180},
+	{0x11018,0x1},
+	{0x11002,0x6209},
+	{0x110b2,0x1},
+	{0x111b4,0x1},
+	{0x112b4,0x1},
+	{0x113b4,0x1},
+	{0x114b4,0x1},
+	{0x115b4,0x1},
+	{0x116b4,0x1},
+	{0x117b4,0x1},
+	{0x118b4,0x1},
+	{0x12011,0x1},
+	{0x12012,0x1},
+	{0x12013,0x180},
+	{0x12018,0x1},
+	{0x12002,0x6209},
+	{0x120b2,0x1},
+	{0x121b4,0x1},
+	{0x122b4,0x1},
+	{0x123b4,0x1},
+	{0x124b4,0x1},
+	{0x125b4,0x1},
+	{0x126b4,0x1},
+	{0x127b4,0x1},
+	{0x128b4,0x1},
+	{0x13011,0x1},
+	{0x13012,0x1},
+	{0x13013,0x180},
+	{0x13018,0x1},
+	{0x13002,0x6209},
+	{0x130b2,0x1},
+	{0x131b4,0x1},
+	{0x132b4,0x1},
+	{0x133b4,0x1},
+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+#elif defined(CONFIG_4GB_LPDDR4)
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa3080020},
+	{0x3d400028,0x0},
+	{0x3d400020,0x203},
+	{0x3d400024,0x3e800},
+	{0x3d400064,0x6100e0},
+	{0x3d4000d0,0xc003061c},
+	{0x3d4000d4,0x9e0000},
+	{0x3d4000dc,0xd4002d},
+	{0x3d4000e0,0x310008},
+	{0x3d4000e8,0x66004a},
+	{0x3d4000ec,0x16004a},
+	{0x3d400100,0x1a201b22},
+	{0x3d400104,0x60633},
+	{0x3d40010c,0xc0c000},
+	{0x3d400110,0xf04080f},
+	{0x3d400114,0x2040c0c},
+	{0x3d400118,0x1010007},
+	{0x3d40011c,0x401},
+	{0x3d400130,0x20600},
+	{0x3d400134,0xc100002},
+	{0x3d400138,0xe6},
+	{0x3d400144,0xa00050},
+	{0x3d400180,0xc3200018},
+	{0x3d400184,0x28061a8},
+	{0x3d400188,0x0},
+	{0x3d400190,0x497820a},
+	{0x3d400194,0x80303},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001b4,0x170a},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0x639},
+	{0x3d400108,0x70e1617},
+	{0x3d400200,0x17},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0x7070707},
+	{0x3d402020,0x1},
+	{0x3d402024,0xd0c0},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0x14002f},
+	{0x3d4020dc,0x940009},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004a},
+	{0x3d4020ec,0x16004a},
+	{0x3d402100,0xb070508},
+	{0x3d402104,0x3040b},
+	{0x3d402108,0x305090c},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x4040204},
+	{0x3d402114,0x2030303},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x31},
+	{0x3d402144,0x220011},
+	{0x3d402180,0xc0a70006},
+	{0x3d402190,0x3858202},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x502},
+	{0x3d400244,0x0},
+	{0x3d400250,0x29001505},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x5900575b},
+	{0x3d400264,0x90000096},
+	{0x3d40026c,0x1000012c},
+	{0x3d400300,0x16},
+	{0x3d400304,0x0},
+	{0x3d40030c,0x0},
+	{0x3d400320,0x1},
+	{0x3d40036c,0x11},
+	{0x3d400400,0x111},
+	{0x3d400404,0x10f3},
+	{0x3d400408,0x72ff},
+	{0x3d400490,0x1},
+	{0x3d400494,0xe00},
+	{0x3d400498,0x62ffff},
+	{0x3d40049c,0xe00},
+	{0x3d4004a0,0xffff},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x2},
+	{0x110a3,0x3},
+	{0x110a4,0x4},
+	{0x110a5,0x7},
+	{0x110a6,0x6},
+	{0x110a7,0x5},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x2},
+	{0x120a3,0x3},
+	{0x120a4,0x4},
+	{0x120a5,0x5},
+	{0x120a6,0x6},
+	{0x120a7,0x7},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x20110,0x2},
+	{0x20111,0x3},
+	{0x20112,0x4},
+	{0x20113,0x5},
+	{0x20114,0x0},
+	{0x20115,0x1},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0x19},
+	{0x1200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x1},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x3},
+	{0x120056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x320},
+	{0x120008,0xa7},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x200f0,0x0},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5555},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x200c7,0x80},
+	{0x1200c7,0x80},
+	{0x200ca,0x106},
+	{0x1200ca,0x106},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },  
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },  
+	{ 0x10043, 0x0 },  
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },  
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },  
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },  
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },  
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },  
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },  
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },  
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },       
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },    
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },    
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },    
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },    
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },    
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },    
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },    
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },    
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },    
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },  
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },  
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },  
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },  
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },  
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },  
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },  
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },  
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },  
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },  
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },  
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },  
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },  
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },  
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },  
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },  
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },  
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },  
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },  
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },  
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },  
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },  
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },  
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },  
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },  
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 }, 
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 }, 
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 }, 
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 }, 
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 }, 
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 }, 
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 }, 
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 }, 
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 }, 
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 }, 
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 }, 
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 }, 
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 }, 
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 }, 
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 }, 
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 }, 
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 }, 
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 }, 
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 }, 
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 }, 
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 }, 
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 }, 
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 }, 
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 }, 
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 }, 
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 }, 
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 }, 
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 }, 
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 }, 
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 }, 
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 }, 
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 }, 
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 }, 
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 }, 
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 }, 
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 }, 
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 }, 
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 }, 
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 }, 
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 }, 
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 }, 
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 }, 
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 }, 
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 }, 
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 }, 
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 }, 
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 }, 
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 }, 
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 }, 
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 }, 
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 }, 
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 }, 
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 }, 
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 }, 
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 }, 
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 }, 
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 }, 
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 }, 
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 }, 
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 }, 
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 }, 
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 }, 
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 }, 
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 }, 
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 }, 
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 }, 
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 }, 
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 }, 
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 }, 
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 }, 
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 }, 
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 }, 
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 }, 
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 }, 
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 }, 
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 }, 
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 }, 
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 }, 
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 }, 
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 }, 
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 }, 
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 }, 
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 }, 
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 }, 
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 }, 
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 }, 
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 }, 
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 }, 
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 }, 
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 }, 
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 }, 
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 }, 
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 }, 
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 }, 
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 }, 
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 }, 
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 }, 
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 }, 
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 }, 
+	{ 0x20073, 0x0 }, 
+	{ 0x20074, 0x0 }, 
+	{ 0x100aa, 0x0 }, 
+	{ 0x110aa, 0x0 }, 
+	{ 0x120aa, 0x0 }, 
+	{ 0x130aa, 0x0 }, 
+	{ 0x20010, 0x0 }, 
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 }, 
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 }, 
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 }, 
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 }, 
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 }, 
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 }, 
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 }, 
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 }, 
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 }, 
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 }, 
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 }, 
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 }, 
+	{ 0x130a5, 0x0 }, 
+	{ 0x130a6, 0x0 }, 
+	{ 0x130a7, 0x0 }, 
+	{ 0x2007c, 0x0 }, 
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 }, 
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 }, 
+	{ 0x400c0, 0x0 }, 
+	{ 0x90201, 0x0 }, 
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 }, 
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 }, 
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 }, 
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 }, 
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 }, 
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 }, 
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 }, 
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 }, 
+	{ 0x10162, 0x0 }, 
+	{ 0x10262, 0x0 }, 
+	{ 0x10362, 0x0 }, 
+	{ 0x10462, 0x0 }, 
+	{ 0x10562, 0x0 }, 
+	{ 0x10662, 0x0 }, 
+	{ 0x10762, 0x0 }, 
+	{ 0x10862, 0x0 }, 
+	{ 0x11062, 0x0 }, 
+	{ 0x11162, 0x0 }, 
+	{ 0x11262, 0x0 }, 
+	{ 0x11362, 0x0 }, 
+	{ 0x11462, 0x0 }, 
+	{ 0x11562, 0x0 }, 
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x310},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x1},
+	{0x54003,0x29c},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x310},
+	{0x54019,0x994},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x994},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0x9400},
+	{0x54033,0x3109},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0x9400},
+	{0x54039,0x3109},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x310},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
+	{0x90043,0x149},
+	{0x90044,0x4f},
+	{0x90045,0x630},
+	{0x90046,0x179},
+	{0x90047,0x8},
+	{0x90048,0xe0},
+	{0x90049,0x109},
+	{0x9004a,0x0},
+	{0x9004b,0x7c8},
+	{0x9004c,0x109},
+	{0x9004d,0x0},
+	{0x9004e,0x1},
+	{0x9004f,0x8},
+	{0x90050,0x0},
+	{0x90051,0x45a},
+	{0x90052,0x9},
+	{0x90053,0x0},
+	{0x90054,0x448},
+	{0x90055,0x109},
+	{0x90056,0x40},
+	{0x90057,0x630},
+	{0x90058,0x179},
+	{0x90059,0x1},
+	{0x9005a,0x618},
+	{0x9005b,0x109},
+	{0x9005c,0x40c0},
+	{0x9005d,0x630},
+	{0x9005e,0x149},
+	{0x9005f,0x8},
+	{0x90060,0x4},
+	{0x90061,0x48},
+	{0x90062,0x4040},
+	{0x90063,0x630},
+	{0x90064,0x149},
+	{0x90065,0x0},
+	{0x90066,0x4},
+	{0x90067,0x48},
+	{0x90068,0x40},
+	{0x90069,0x630},
+	{0x9006a,0x149},
+	{0x9006b,0x10},
+	{0x9006c,0x4},
+	{0x9006d,0x18},
+	{0x9006e,0x0},
+	{0x9006f,0x4},
+	{0x90070,0x78},
+	{0x90071,0x549},
+	{0x90072,0x630},
+	{0x90073,0x159},
+	{0x90074,0xd49},
+	{0x90075,0x630},
+	{0x90076,0x159},
+	{0x90077,0x94a},
+	{0x90078,0x630},
+	{0x90079,0x159},
+	{0x9007a,0x441},
+	{0x9007b,0x630},
+	{0x9007c,0x149},
+	{0x9007d,0x42},
+	{0x9007e,0x630},
+	{0x9007f,0x149},
+	{0x90080,0x1},
+	{0x90081,0x630},
+	{0x90082,0x149},
+	{0x90083,0x0},
+	{0x90084,0xe0},
+	{0x90085,0x109},
+	{0x90086,0xa},
+	{0x90087,0x10},
+	{0x90088,0x109},
+	{0x90089,0x9},
+	{0x9008a,0x3c0},
+	{0x9008b,0x149},
+	{0x9008c,0x9},
+	{0x9008d,0x3c0},
+	{0x9008e,0x159},
+	{0x9008f,0x18},
+	{0x90090,0x10},
+	{0x90091,0x109},
+	{0x90092,0x0},
+	{0x90093,0x3c0},
+	{0x90094,0x109},
+	{0x90095,0x18},
+	{0x90096,0x4},
+	{0x90097,0x48},
+	{0x90098,0x18},
+	{0x90099,0x4},
+	{0x9009a,0x58},
+	{0x9009b,0xa},
+	{0x9009c,0x10},
+	{0x9009d,0x109},
+	{0x9009e,0x2},
+	{0x9009f,0x10},
+	{0x900a0,0x109},
+	{0x900a1,0x5},
+	{0x900a2,0x7c0},
+	{0x900a3,0x109},
+	{0x900a4,0x10},
+	{0x900a5,0x10},
+	{0x900a6,0x109},
+	{0x40000,0x811},
+	{0x40020,0x880},
+	{0x40040,0x0},
+	{0x40060,0x0},
+	{0x40001,0x4008},
+	{0x40021,0x83},
+	{0x40041,0x4f},
+	{0x40061,0x0},
+	{0x40002,0x4040},
+	{0x40022,0x83},
+	{0x40042,0x51},
+	{0x40062,0x0},
+	{0x40003,0x811},
+	{0x40023,0x880},
+	{0x40043,0x0},
+	{0x40063,0x0},
+	{0x40004,0x720},
+	{0x40024,0xf},
+	{0x40044,0x1740},
+	{0x40064,0x0},
+	{0x40005,0x16},
+	{0x40025,0x83},
+	{0x40045,0x4b},
+	{0x40065,0x0},
+	{0x40006,0x716},
+	{0x40026,0xf},
+	{0x40046,0x2001},
+	{0x40066,0x0},
+	{0x40007,0x716},
+	{0x40027,0xf},
+	{0x40047,0x2800},
+	{0x40067,0x0},
+	{0x40008,0x716},
+	{0x40028,0xf},
+	{0x40048,0xf00},
+	{0x40068,0x0},
+	{0x40009,0x720},
+	{0x40029,0xf},
+	{0x40049,0x1400},
+	{0x40069,0x0},
+	{0x4000a,0xe08},
+	{0x4002a,0xc15},
+	{0x4004a,0x0},
+	{0x4006a,0x0},
+	{0x4000b,0x623},
+	{0x4002b,0x15},
+	{0x4004b,0x0},
+	{0x4006b,0x0},
+	{0x4000c,0x4028},
+	{0x4002c,0x80},
+	{0x4004c,0x0},
+	{0x4006c,0x0},
+	{0x4000d,0xe08},
+	{0x4002d,0xc1a},
+	{0x4004d,0x0},
+	{0x4006d,0x0},
+	{0x4000e,0x623},
+	{0x4002e,0x1a},
+	{0x4004e,0x0},
+	{0x4006e,0x0},
+	{0x4000f,0x4040},
+	{0x4002f,0x80},
+	{0x4004f,0x0},
+	{0x4006f,0x0},
+	{0x40010,0x2604},
+	{0x40030,0x15},
+	{0x40050,0x0},
+	{0x40070,0x0},
+	{0x40011,0x708},
+	{0x40031,0x5},
+	{0x40051,0x0},
+	{0x40071,0x2002},
+	{0x40012,0x8},
+	{0x40032,0x80},
+	{0x40052,0x0},
+	{0x40072,0x0},
+	{0x40013,0x2604},
+	{0x40033,0x1a},
+	{0x40053,0x0},
+	{0x40073,0x0},
+	{0x40014,0x708},
+	{0x40034,0xa},
+	{0x40054,0x0},
+	{0x40074,0x2002},
+	{0x40015,0x4040},
+	{0x40035,0x80},
+	{0x40055,0x0},
+	{0x40075,0x0},
+	{0x40016,0x60a},
+	{0x40036,0x15},
+	{0x40056,0x1200},
+	{0x40076,0x0},
+	{0x40017,0x61a},
+	{0x40037,0x15},
+	{0x40057,0x1300},
+	{0x40077,0x0},
+	{0x40018,0x60a},
+	{0x40038,0x1a},
+	{0x40058,0x1200},
+	{0x40078,0x0},
+	{0x40019,0x642},
+	{0x40039,0x1a},
+	{0x40059,0x1300},
+	{0x40079,0x0},
+	{0x4001a,0x4808},
+	{0x4003a,0x880},
+	{0x4005a,0x0},
+	{0x4007a,0x0},
+	{0x900a7,0x0},
+	{0x900a8,0x790},
+	{0x900a9,0x11a},
+	{0x900aa,0x8},
+	{0x900ab,0x7aa},
+	{0x900ac,0x2a},
+	{0x900ad,0x10},
+	{0x900ae,0x7b2},
+	{0x900af,0x2a},
+	{0x900b0,0x0},
+	{0x900b1,0x7c8},
+	{0x900b2,0x109},
+	{0x900b3,0x10},
+	{0x900b4,0x2a8},
+	{0x900b5,0x129},
+	{0x900b6,0x8},
+	{0x900b7,0x370},
+	{0x900b8,0x129},
+	{0x900b9,0xa},
+	{0x900ba,0x3c8},
+	{0x900bb,0x1a9},
+	{0x900bc,0xc},
+	{0x900bd,0x408},
+	{0x900be,0x199},
+	{0x900bf,0x14},
+	{0x900c0,0x790},
+	{0x900c1,0x11a},
+	{0x900c2,0x8},
+	{0x900c3,0x4},
+	{0x900c4,0x18},
+	{0x900c5,0xe},
+	{0x900c6,0x408},
+	{0x900c7,0x199},
+	{0x900c8,0x8},
+	{0x900c9,0x8568},
+	{0x900ca,0x108},
+	{0x900cb,0x18},
+	{0x900cc,0x790},
+	{0x900cd,0x16a},
+	{0x900ce,0x8},
+	{0x900cf,0x1d8},
+	{0x900d0,0x169},
+	{0x900d1,0x10},
+	{0x900d2,0x8558},
+	{0x900d3,0x168},
+	{0x900d4,0x70},
+	{0x900d5,0x788},
+	{0x900d6,0x16a},
+	{0x900d7,0x1ff8},
+	{0x900d8,0x85a8},
+	{0x900d9,0x1e8},
+	{0x900da,0x50},
+	{0x900db,0x798},
+	{0x900dc,0x16a},
+	{0x900dd,0x60},
+	{0x900de,0x7a0},
+	{0x900df,0x16a},
+	{0x900e0,0x8},
+	{0x900e1,0x8310},
+	{0x900e2,0x168},
+	{0x900e3,0x8},
+	{0x900e4,0xa310},
+	{0x900e5,0x168},
+	{0x900e6,0xa},
+	{0x900e7,0x408},
+	{0x900e8,0x169},
+	{0x900e9,0x6e},
+	{0x900ea,0x0},
+	{0x900eb,0x68},
+	{0x900ec,0x0},
+	{0x900ed,0x408},
+	{0x900ee,0x169},
+	{0x900ef,0x0},
+	{0x900f0,0x8310},
+	{0x900f1,0x168},
+	{0x900f2,0x0},
+	{0x900f3,0xa310},
+	{0x900f4,0x168},
+	{0x900f5,0x1ff8},
+	{0x900f6,0x85a8},
+	{0x900f7,0x1e8},
+	{0x900f8,0x68},
+	{0x900f9,0x798},
+	{0x900fa,0x16a},
+	{0x900fb,0x78},
+	{0x900fc,0x7a0},
+	{0x900fd,0x16a},
+	{0x900fe,0x68},
+	{0x900ff,0x790},
+	{0x90100,0x16a},
+	{0x90101,0x8},
+	{0x90102,0x8b10},
+	{0x90103,0x168},
+	{0x90104,0x8},
+	{0x90105,0xab10},
+	{0x90106,0x168},
+	{0x90107,0xa},
+	{0x90108,0x408},
+	{0x90109,0x169},
+	{0x9010a,0x58},
+	{0x9010b,0x0},
+	{0x9010c,0x68},
+	{0x9010d,0x0},
+	{0x9010e,0x408},
+	{0x9010f,0x169},
+	{0x90110,0x0},
+	{0x90111,0x8b10},
+	{0x90112,0x168},
+	{0x90113,0x0},
+	{0x90114,0xab10},
+	{0x90115,0x168},
+	{0x90116,0x0},
+	{0x90117,0x1d8},
+	{0x90118,0x169},
+	{0x90119,0x80},
+	{0x9011a,0x790},
+	{0x9011b,0x16a},
+	{0x9011c,0x18},
+	{0x9011d,0x7aa},
+	{0x9011e,0x6a},
+	{0x9011f,0xa},
+	{0x90120,0x0},
+	{0x90121,0x1e9},
+	{0x90122,0x8},
+	{0x90123,0x8080},
+	{0x90124,0x108},
+	{0x90125,0xf},
+	{0x90126,0x408},
+	{0x90127,0x169},
+	{0x90128,0xc},
+	{0x90129,0x0},
+	{0x9012a,0x68},
+	{0x9012b,0x9},
+	{0x9012c,0x0},
+	{0x9012d,0x1a9},
+	{0x9012e,0x0},
+	{0x9012f,0x408},
+	{0x90130,0x169},
+	{0x90131,0x0},
+	{0x90132,0x8080},
+	{0x90133,0x108},
+	{0x90134,0x8},
+	{0x90135,0x7aa},
+	{0x90136,0x6a},
+	{0x90137,0x0},
+	{0x90138,0x8568},
+	{0x90139,0x108},
+	{0x9013a,0xb7},
+	{0x9013b,0x790},
+	{0x9013c,0x16a},
+	{0x9013d,0x1f},
+	{0x9013e,0x0},
+	{0x9013f,0x68},
+	{0x90140,0x8},
+	{0x90141,0x8558},
+	{0x90142,0x168},
+	{0x90143,0xf},
+	{0x90144,0x408},
+	{0x90145,0x169},
+	{0x90146,0xc},
+	{0x90147,0x0},
+	{0x90148,0x68},
+	{0x90149,0x0},
+	{0x9014a,0x408},
+	{0x9014b,0x169},
+	{0x9014c,0x0},
+	{0x9014d,0x8558},
+	{0x9014e,0x168},
+	{0x9014f,0x8},
+	{0x90150,0x3c8},
+	{0x90151,0x1a9},
+	{0x90152,0x3},
+	{0x90153,0x370},
+	{0x90154,0x129},
+	{0x90155,0x20},
+	{0x90156,0x2aa},
+	{0x90157,0x9},
+	{0x90158,0x0},
+	{0x90159,0x400},
+	{0x9015a,0x10e},
+	{0x9015b,0x8},
+	{0x9015c,0xe8},
+	{0x9015d,0x109},
+	{0x9015e,0x0},
+	{0x9015f,0x8140},
+	{0x90160,0x10c},
+	{0x90161,0x10},
+	{0x90162,0x8138},
+	{0x90163,0x10c},
+	{0x90164,0x8},
+	{0x90165,0x7c8},
+	{0x90166,0x101},
+	{0x90167,0x8},
+	{0x90168,0x0},
+	{0x90169,0x8},
+	{0x9016a,0x8},
+	{0x9016b,0x448},
+	{0x9016c,0x109},
+	{0x9016d,0xf},
+	{0x9016e,0x7c0},
+	{0x9016f,0x109},
+	{0x90170,0x0},
+	{0x90171,0xe8},
+	{0x90172,0x109},
+	{0x90173,0x47},
+	{0x90174,0x630},
+	{0x90175,0x109},
+	{0x90176,0x8},
+	{0x90177,0x618},
+	{0x90178,0x109},
+	{0x90179,0x8},
+	{0x9017a,0xe0},
+	{0x9017b,0x109},
+	{0x9017c,0x0},
+	{0x9017d,0x7c8},
+	{0x9017e,0x109},
+	{0x9017f,0x8},
+	{0x90180,0x8140},
+	{0x90181,0x10c},
+	{0x90182,0x0},
+	{0x90183,0x1},
+	{0x90184,0x8},
+	{0x90185,0x8},
+	{0x90186,0x4},
+	{0x90187,0x8},
+	{0x90188,0x8},
+	{0x90189,0x7c8},
+	{0x9018a,0x101},
+	{0x90006,0x0},
+	{0x90007,0x0},
+	{0x90008,0x8},
+	{0x90009,0x0},
+	{0x9000a,0x0},
+	{0x9000b,0x0},
+	{0xd00e7,0x400},
+	{0x90017,0x0},
+	{0x9001f,0x2a},
+	{0x90026,0x6a},
+	{0x400d0,0x0},
+	{0x400d1,0x101},
+	{0x400d2,0x105},
+	{0x400d3,0x107},
+	{0x400d4,0x10f},
+	{0x400d5,0x202},
+	{0x400d6,0x20a},
+	{0x400d7,0x20b},
+	{0x2003a,0x2},
+	{0x2000b,0x64},
+	{0x2000c,0xc8},
+	{0x2000d,0x7d0},
+	{0x2000e,0x2c},
+	{0x12000b,0x14},
+	{0x12000c,0x29},
+	{0x12000d,0x1a1},
+	{0x12000e,0x10},
+	{0x9000c,0x0},
+	{0x9000d,0x173},
+	{0x9000e,0x60},
+	{0x9000f,0x6110},
+	{0x90010,0x2152},
+	{0x90011,0xdfbd},
+	{0x90012,0x60},
+	{0x90013,0x6152},
+	{0x20010,0x5a},
+	{0x20011,0x3},
+	{0x120010,0x5a},
+	{0x120011,0x3},
+	{0x40080,0xe0},
+	{0x40081,0x12},
+	{0x40082,0xe0},
+	{0x40083,0x12},
+	{0x40084,0xe0},
+	{0x40085,0x12},
+	{0x140080,0xe0},
+	{0x140081,0x12},
+	{0x140082,0xe0},
+	{0x140083,0x12},
+	{0x140084,0xe0},
+	{0x140085,0x12},
+	{0x400fd,0xf},
+	{0x10011,0x1},
+	{0x10012,0x1},
+	{0x10013,0x180},
+	{0x10018,0x1},
+	{0x10002,0x6209},
+	{0x100b2,0x1},
+	{0x101b4,0x1},
+	{0x102b4,0x1},
+	{0x103b4,0x1},
+	{0x104b4,0x1},
+	{0x105b4,0x1},
+	{0x106b4,0x1},
+	{0x107b4,0x1},
+	{0x108b4,0x1},
+	{0x11011,0x1},
+	{0x11012,0x1},
+	{0x11013,0x180},
+	{0x11018,0x1},
+	{0x11002,0x6209},
+	{0x110b2,0x1},
+	{0x111b4,0x1},
+	{0x112b4,0x1},
+	{0x113b4,0x1},
+	{0x114b4,0x1},
+	{0x115b4,0x1},
+	{0x116b4,0x1},
+	{0x117b4,0x1},
+	{0x118b4,0x1},
+	{0x12011,0x1},
+	{0x12012,0x1},
+	{0x12013,0x180},
+	{0x12018,0x1},
+	{0x12002,0x6209},
+	{0x120b2,0x1},
+	{0x121b4,0x1},
+	{0x122b4,0x1},
+	{0x123b4,0x1},
+	{0x124b4,0x1},
+	{0x125b4,0x1},
+	{0x126b4,0x1},
+	{0x127b4,0x1},
+	{0x128b4,0x1},
+	{0x13011,0x1},
+	{0x13012,0x1},
+	{0x13013,0x180},
+	{0x13018,0x1},
+	{0x13002,0x6209},
+	{0x130b2,0x1},
+	{0x131b4,0x1},
+	{0x132b4,0x1},
+	{0x133b4,0x1},
+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+#else
+#error "no configuration for this board"
+#endif
diff --git a/board/embedian/embedian/smarcimx8mq/smarcimx8mq.c b/board/embedian/embedian/smarcimx8mq/smarcimx8mq.c
new file mode 100644
index 0000000..9eedb2c
--- /dev/null
+++ b/board/embedian/embedian/smarcimx8mq/smarcimx8mq.c
@@ -0,0 +1,756 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/video_common.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <dm.h>
+#include "../../freescale/common/tcpc.h"
+#include "../../freescale/common/pfuze.h"
+#include "../../freescale/common/mmc.c"
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define QSPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+#define WEAK_PULLUP     (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const qspi_pads[] = {
+	IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+	IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
+
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CONSOLE_SER3
+static iomux_v3_cfg_t const uart1_pads[] = {
+        IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+static iomux_v3_cfg_t const uart2_pads[] = {
+        IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+static iomux_v3_cfg_t const uart3_pads[] = {
+        IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER0
+static iomux_v3_cfg_t const uart4_pads[] = {
+        IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+/* SPI0*/
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+        IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+        IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS0#*/
+        IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS1#*/
+        IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS2#*/
+        IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS3#*/
+};
+
+/* MISC PINs */
+static iomux_v3_cfg_t const misc_pads[] = {
+        IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP),             /*S146, PCIE_WAKE*/
+        IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP),           /*S148, LID#*/
+        IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),          /*S149, SLEEP#*/
+        IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),           /*S151, CHARGING#*/
+        IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP),          	/*S152, CHARGER_PRSNT#*/
+        IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),            /*S153, CARRIER_STBY#*/
+        IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),          	/*S156, BATLOW#*/
+        IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),           /*CAN0_INT#*/
+        IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),        /*CAN1_INT#*/
+};
+
+static void setup_iomux_misc(void)
+{
+        imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+        /* Set CARRIER_LID# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 9), "LID#");
+        gpio_direction_input(IMX_GPIO_NR(1, 9));
+        /* Set CARRIER_SLEEP# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 12), "SLEEP#");
+        gpio_direction_input(IMX_GPIO_NR(1, 12));
+        /* Set CARRIER_CHARGING# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#");
+        gpio_direction_input(IMX_GPIO_NR(1, 01));
+        /* Set CARRIER_CHARGER_PRSNT# as Input*/
+        gpio_request(IMX_GPIO_NR(4, 22), "CHARGER_PRSNT#");
+        gpio_direction_input(IMX_GPIO_NR(4, 22));
+        /* Set CARRIER_STBY# as Output High*/
+        gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#");
+        gpio_direction_output(IMX_GPIO_NR(5, 02) , 1);
+        /* Set CARRIER_BATLOW# as Input*/
+        gpio_request(IMX_GPIO_NR(4, 21), "BATLOW#");
+        gpio_direction_input(IMX_GPIO_NR(4, 21));
+        /* Set PCIE_WAKE# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#");
+        gpio_direction_input(IMX_GPIO_NR(3, 5));
+        /* Set CAN0_INT# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#");
+        gpio_direction_input(IMX_GPIO_NR(3, 18));
+        /* Set CAN1_INT# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#");
+        gpio_direction_input(IMX_GPIO_NR(3, 16));
+}
+
+/* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/
+static iomux_v3_cfg_t const gpio_pads[] = {
+        IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P108, GPIO0*/
+        IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P109, GPIO1*/
+        IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),            /*P110, GPIO2*/
+        IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P111, GPIO3*/
+        IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P112, GPIO4*/
+        IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP),             /*P113, GPIO5*/
+        IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),             /*P114, GPIO6*/
+        IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P115, GPIO7*/
+        IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P116, GPIO8*/
+        IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),            /*P114, GPIO9*/
+        IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P115, GPIO10*/
+        IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P116, GPIO11*/
+};
+
+static void setup_iomux_gpio(void)
+{
+        imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+
+        /* Set GPIO0 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 25), "GPIO0");
+        gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
+        /* Set GPIO1 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 19), "GPIO1");
+        gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+        /* Set GPIO2 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 20), "GPIO2");
+        gpio_direction_output(IMX_GPIO_NR(3, 20), 0);
+        /* Set GPIO3 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 21), "GPIO3");
+        gpio_direction_output(IMX_GPIO_NR(3, 21), 0);
+        /* Set GPIO4 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 22), "GPIO4");
+        gpio_direction_output(IMX_GPIO_NR(3, 22), 0);
+        /* Set GPIO5 as Output Low*/
+        gpio_request(IMX_GPIO_NR(5, 3), "GPIO5");
+        gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
+        /* Set GPIO6 as Input*/
+        gpio_request(IMX_GPIO_NR(5, 4), "GPIO6");
+        gpio_direction_input(IMX_GPIO_NR(5, 4));
+        /* Set GPIO7 as Input*/
+        gpio_request(IMX_GPIO_NR(3, 23), "GPIO7");
+        gpio_direction_input(IMX_GPIO_NR(3, 23));
+        /* Set GPIO8 as Input*/
+        gpio_request(IMX_GPIO_NR(3, 24), "GPIO8");
+        gpio_direction_input(IMX_GPIO_NR(3, 24));
+        /* Set GPIO9 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 11), "GPIO9");
+        gpio_direction_input(IMX_GPIO_NR(4, 11));
+        /* Set GPIO10 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 10), "GPIO10");
+        gpio_direction_input(IMX_GPIO_NR(4, 10));
+        /* Set GPIO11 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 20), "GPIO11");
+        gpio_direction_input(IMX_GPIO_NR(4, 20));
+}
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+#ifdef CONFIG_CONSOLE_SER0
+        imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+#endif
+#ifdef CONFIG_CONSOLE_SER1
+        imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+#endif
+#ifdef CONFIG_CONSOLE_SER2
+        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+#endif
+#ifdef CONFIG_CONSOLE_SER3
+        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+	/* TODO */
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C
+/*I2C2, I2C_CAM0 and I2C_LCD*/
+struct i2c_pads_info i2c_pad_info2 = {
+        .scl = {
+                .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 16),
+        },
+        .sda = {
+                .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 17),
+        },
+};
+
+/*I2C3, I2C_GP*/
+struct i2c_pads_info i2c_pad_info3 = {
+        .scl = {
+                .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 18),
+        },
+        .sda = {
+                .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 19),
+        },
+};
+
+/*I2C4, I2C_CAM1*/
+struct i2c_pads_info i2c_pad_info4 = {
+        .scl = {
+                .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 20),
+        },
+        .sda = {
+                .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 21),
+        },
+};
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+/* Get the top of usable RAM */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+
+        //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size);
+
+        if(gd->ram_top > 0x100000000)
+           gd->ram_top = 0x100000000;
+
+        return gd->ram_top;
+}
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 11)
+static iomux_v3_cfg_t const fec1_irq_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_irq_pads,
+					 ARRAY_SIZE(fec1_irq_pads));
+
+        gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq");
+        gpio_direction_input(IMX_GPIO_NR(1, 11));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+static void setup_iomux_ecspi1(void)
+{
+        imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+                                         ARRAY_SIZE(ecspi1_pads));
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+        gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0");
+        return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1;
+        gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1");
+        return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1;
+        gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2");
+        return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1;
+        gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3");
+        return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1;
+}
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+        .maximum_speed = USB_SPEED_HIGH,
+#else
+        .maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+/*USB Enable Over-Current Pin Setting*/
+static iomux_v3_cfg_t const usb_en_oc_pads[] = {
+        IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
+        IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+        IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_usb_en_oc(void)
+{
+        imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads,
+                                         ARRAY_SIZE(usb_en_oc_pads));
+
+        gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 10));
+        gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 12));
+        gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 13));
+}
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 0,
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+#define USB_TYPEC_SEL IMX_GPIO_NR(3, 15)
+
+static iomux_v3_cfg_t ss_mux_gpio[] = {
+	IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		gpio_direction_output(USB_TYPEC_SEL, 1);
+	else
+		gpio_direction_output(USB_TYPEC_SEL, 0);
+}
+
+static int setup_typec(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+	gpio_request(USB_TYPEC_SEL, "typec_sel");
+
+	ret = tcpc_init(&port, port_config, &ss_mux_select);
+	if (ret) {
+		printf("%s: tcpc init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	imx8m_usb_power(index, true);
+
+	if (index == 0 && init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_ufp_mode(&port);
+#endif
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_dfp_mode(&port);
+#endif
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_disable_src_vbus(&port);
+#endif
+	}
+
+	imx8m_usb_power(index, false);
+
+	return ret;
+}
+#endif
+
+int board_init(void)
+{
+	board_qspi_init();
+        setup_iomux_usb_en_oc();
+        setup_iomux_misc();
+        setup_iomux_gpio();
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+	init_usb_clk();
+#endif
+
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+        setup_iomux_ecspi1();
+
+        /* Read Module Information from on module EEPROM and pass
+         * mac address to kernel
+        */
+        struct udevice *dev;
+        int ret;
+        u8 name[8];
+        u8 serial[12];
+        u8 revision[4];
+        u8 mac[6];
+
+        ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev);
+        if (ret) {
+                debug("failed to get eeprom\n");
+                return 0;
+        }
+
+        /* Board ID */
+        ret = dm_i2c_read(dev, 0x4, name, 8);
+        if (ret) {
+                debug("failed to read board ID from EEPROM\n");
+                return 0;
+        }
+        puts("---------Embedian SMARC-iMX8M------------\n");
+        printf("  Board ID:             %c%c%c%c%c%c%c%c\n",
+               name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);
+
+        /* Board Hardware Revision */
+        ret = dm_i2c_read(dev, 0xc, revision, 4);
+        if (ret) {
+                debug("failed to read hardware revison from EEPROM\n");
+                return 0;
+        }
+        printf("  Hardware Revision:    %c%c%c%c\n",
+               revision[0], revision[1], revision[2], revision[3]);
+
+        /* Serial number */
+        ret = dm_i2c_read(dev, 0x10, serial, 12);
+        if (ret) {
+                debug("failed to read srial number from EEPROM\n");
+                return 0;
+        }
+        printf("  Serial Number#:       %c%c%c%c%c%c%c%c%c%c%c%c\n",
+               serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);
+
+        /*MAC address */
+        ret = dm_i2c_read(dev, 0x3c, mac, 6);
+        if (ret) {
+                debug("failed to read eth0 mac address from EEPROM\n");
+                return 0;
+        }
+
+        if (is_valid_ethaddr(mac))
+        printf("  MAC Address:          %02x:%02x:%02x:%02x:%02x:%02x\n",
+               mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+                eth_env_set_enetaddr("ethaddr", mac);
+        puts("-----------------------------------------\n");
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "SMARC-iMX8M");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+/* SMARC BOOT_SEL*/
+        gpio_request(IMX_GPIO_NR(1, 8), "BOOT_SEL_1");
+        gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2");
+        gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3");
+        if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n");
+                env_set_ulong("usb dev", 1);
+                env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n");
+                env_set_ulong("mmcdev", 1);
+                env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n");
+                env_set_ulong("mmcdev", 0);
+                env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
+                env_set("bootcmd", "run netboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("Carrier SPI Boot is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n");
+                hang();
+        } else {
+                puts("unsupported boot devices\n");
+                hang();
+        }
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+#define LID_KEY IMX_GPIO_NR(1, 9)
+#define LID_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const lid_pads[] = {
+        IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL),
+};
+
+int is_recovery_key_pressing(void)
+{
+        imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads));
+        gpio_request(LID_KEY, "LID");
+        gpio_direction_input(LID_KEY);
+        if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */
+                printf("Recovery key pressed\n");
+                return 1;
+        }
+	return 0;
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+#if defined(CONFIG_VIDEO_IMXDCSS)
+
+struct display_info_t const displays[] = {{
+	.bus	= 0, /* Unused */
+	.addr	= 0, /* Unused */
+	.pixfmt	= GDF_32BIT_X888RGB,
+	.detect	= NULL,
+	.enable	= NULL,
+#ifndef CONFIG_VIDEO_IMXDCSS_1080P
+	.mode	= {
+		.name           = "HDMI", /* 720P60 */
+		.refresh        = 60,
+		.xres           = 1280,
+		.yres           = 720,
+		.pixclock       = 13468, /* 74250  kHz */
+		.left_margin    = 110,
+		.right_margin   = 220,
+		.upper_margin   = 5,
+		.lower_margin   = 20,
+		.hsync_len      = 40,
+		.vsync_len      = 5,
+		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+#else
+	.mode	= {
+		.name           = "HDMI", /* 1080P60 */
+		.refresh        = 60,
+		.xres           = 1920,
+		.yres           = 1080,
+		.pixclock       = 6734, /* 148500 kHz */
+		.left_margin    = 148,
+		.right_margin   = 88,
+		.upper_margin   = 36,
+		.lower_margin   = 4,
+		.hsync_len      = 44,
+		.vsync_len      = 5,
+		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+#endif
+} };
+size_t display_count = ARRAY_SIZE(displays);
+
+#endif /* CONFIG_VIDEO_IMXDCSS */
+
+/* return hard code board id for imx8m_ref */
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+int get_imx8m_baseboard_id(void)
+{
+	return IMX8M_REF_3G;
+}
+#endif
diff --git a/board/embedian/embedian/smarcimx8mq/spl.c b/board/embedian/embedian/smarcimx8mq/spl.c
new file mode 100644
index 0000000..f9d0370
--- /dev/null
+++ b/board/embedian/embedian/smarcimx8mq/spl.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../../freescale/common/pfuze.h"
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8m_ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*extern struct dram_timing_info dram_timing_b0;*/
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+                ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+/* RESET_OUT */
+static iomux_v3_cfg_t const reset_out_pads[] = {
+        IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_reset_out(void)
+{
+        imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
+
+        /* Set CPU RESET_OUT as Output */
+        gpio_request(IMX_GPIO_NR(1, 03), "CPU_RESET");
+        gpio_direction_output(IMX_GPIO_NR(1, 03) , 0);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return -ENODEV;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return -ENODEV;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
+	if ((reg & 0x3f) != 0x18) {
+		reg &= ~0x3f;
+		reg |= 0x18;
+		pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+	}
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW3A standby mode to off */
+	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
+	reg &= ~0xf;
+	reg |= APS_OFF;
+	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+
+	init_usb_clk();
+
+	puts("Normal Boot\n");
+        setup_iomux_reset_out();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+#ifdef CONFIG_CONSOLE_SER3
+	init_uart_clk(0); /* Init UART0 clock */
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+        init_uart_clk(1); /* Init UART1 clock */
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+        init_uart_clk(2); /* Init UART2 clock */
+#endif
+
+#ifdef CONFIG_CONSOLE_SER0
+        init_uart_clk(3); /* Init UART3 clock */
+#endif
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x08, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/embedian/smarcimx8mq/Kconfig b/board/embedian/smarcimx8mq/Kconfig
new file mode 100644
index 0000000..91b8098
--- /dev/null
+++ b/board/embedian/smarcimx8mq/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMARCIMX8MQ
+
+config SYS_BOARD
+	default "smarcimx8mq"
+
+config SYS_VENDOR
+	default "embedian"
+
+config SYS_CONFIG_NAME
+	default "smarcimx8mq"
+
+endif
diff --git a/board/embedian/smarcimx8mq/Makefile b/board/embedian/smarcimx8mq/Makefile
new file mode 100644
index 0000000..4b53f01
--- /dev/null
+++ b/board/embedian/smarcimx8mq/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += smarcimx8mq.o
+
+obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/embedian/smarcimx8mq/lpddr4_timing.c b/board/embedian/smarcimx8mq/lpddr4_timing.c
new file mode 100644
index 0000000..caea7cd
--- /dev/null
+++ b/board/embedian/smarcimx8mq/lpddr4_timing.c
@@ -0,0 +1,3459 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/imx8m_ddr.h>
+#include <common.h>
+#if defined(CONFIG_2GB_LPDDR4)
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa1080020},
+	{0x3d400028,0x0},
+	{0x3d400020,0x203},
+	{0x3d400024,0x3e800},
+	{0x3d400064,0x6100e0},
+	{0x3d4000d0,0xc003061c},
+	{0x3d4000d4,0x9e0000},
+	{0x3d4000dc,0xd4002d},
+	{0x3d4000e0,0x310008},
+	{0x3d4000e8,0x66004a},
+	{0x3d4000ec,0x16004a},
+	{0x3d400100,0x1a201b22},
+	{0x3d400104,0x60633},
+	{0x3d40010c,0xc0c000},
+	{0x3d400110,0xf04080f},
+	{0x3d400114,0x2040c0c},
+	{0x3d400118,0x1010007},
+	{0x3d40011c,0x401},
+	{0x3d400130,0x20600},
+	{0x3d400134,0xc100002},
+	{0x3d400138,0xe6},
+	{0x3d400144,0xa00050},
+	{0x3d400180,0xc3200018},
+	{0x3d400184,0x28061a8},
+	{0x3d400188,0x0},
+	{0x3d400190,0x497820a},
+	{0x3d400194,0x80303},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001b4,0x170a},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0x639},
+	{0x3d400108,0x70e1617},
+	{0x3d400200,0x1f},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0x7070707},
+	{0x3d402020,0x1},
+	{0x3d402024,0xd0c0},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0x14002f},
+	{0x3d4020dc,0x940009},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004a},
+	{0x3d4020ec,0x16004a},
+	{0x3d402100,0xb070508},
+	{0x3d402104,0x3040b},
+	{0x3d402108,0x305090c},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x4040204},
+	{0x3d402114,0x2030303},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x31},
+	{0x3d402144,0x220011},
+	{0x3d402180,0xc0a70006},
+	{0x3d402190,0x3858202},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x502},
+	{0x3d400244,0x0},
+	{0x3d400250,0x29001505},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x5900575b},
+	{0x3d400264,0x90000096},
+	{0x3d40026c,0x1000012c},
+	{0x3d400300,0x16},
+	{0x3d400304,0x0},
+	{0x3d40030c,0x0},
+	{0x3d400320,0x1},
+	{0x3d40036c,0x11},
+	{0x3d400400,0x111},
+	{0x3d400404,0x10f3},
+	{0x3d400408,0x72ff},
+	{0x3d400490,0x1},
+	{0x3d400494,0xe00},
+	{0x3d400498,0x62ffff},
+	{0x3d40049c,0xe00},
+	{0x3d4004a0,0xffff},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x2},
+	{0x110a3,0x3},
+	{0x110a4,0x4},
+	{0x110a5,0x7},
+	{0x110a6,0x6},
+	{0x110a7,0x5},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x2},
+	{0x120a3,0x3},
+	{0x120a4,0x4},
+	{0x120a5,0x5},
+	{0x120a6,0x6},
+	{0x120a7,0x7},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x20110,0x2},
+	{0x20111,0x3},
+	{0x20112,0x4},
+	{0x20113,0x5},
+	{0x20114,0x0},
+	{0x20115,0x1},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0x19},
+	{0x1200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x1},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x3},
+	{0x120056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x320},
+	{0x120008,0xa7},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x200f0,0x0},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5555},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x200c7,0x80},
+	{0x1200c7,0x80},
+	{0x200ca,0x106},
+	{0x1200ca,0x106},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },  
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },  
+	{ 0x10043, 0x0 },  
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },  
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },  
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },  
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },  
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },  
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },  
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },  
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },       
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },    
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },    
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },    
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },    
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },    
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },    
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },    
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },    
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },    
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },  
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },  
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },  
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },  
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },  
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },  
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },  
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },  
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },  
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },  
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },  
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },  
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },  
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },  
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },  
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },  
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },  
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },  
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },  
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },  
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },  
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },  
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },  
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },  
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },  
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 }, 
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 }, 
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 }, 
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 }, 
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 }, 
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 }, 
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 }, 
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 }, 
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 }, 
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 }, 
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 }, 
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 }, 
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 }, 
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 }, 
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 }, 
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 }, 
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 }, 
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 }, 
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 }, 
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 }, 
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 }, 
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 }, 
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 }, 
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 }, 
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 }, 
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 }, 
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 }, 
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 }, 
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 }, 
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 }, 
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 }, 
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 }, 
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 }, 
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 }, 
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 }, 
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 }, 
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 }, 
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 }, 
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 }, 
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 }, 
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 }, 
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 }, 
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 }, 
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 }, 
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 }, 
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 }, 
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 }, 
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 }, 
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 }, 
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 }, 
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 }, 
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 }, 
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 }, 
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 }, 
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 }, 
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 }, 
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 }, 
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 }, 
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 }, 
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 }, 
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 }, 
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 }, 
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 }, 
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 }, 
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 }, 
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 }, 
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 }, 
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 }, 
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 }, 
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 }, 
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 }, 
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 }, 
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 }, 
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 }, 
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 }, 
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 }, 
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 }, 
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 }, 
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 }, 
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 }, 
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 }, 
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 }, 
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 }, 
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 }, 
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 }, 
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 }, 
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 }, 
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 }, 
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 }, 
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 }, 
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 }, 
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 }, 
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 }, 
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 }, 
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 }, 
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 }, 
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 }, 
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 }, 
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 }, 
+	{ 0x20073, 0x0 }, 
+	{ 0x20074, 0x0 }, 
+	{ 0x100aa, 0x0 }, 
+	{ 0x110aa, 0x0 }, 
+	{ 0x120aa, 0x0 }, 
+	{ 0x130aa, 0x0 }, 
+	{ 0x20010, 0x0 }, 
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 }, 
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 }, 
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 }, 
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 }, 
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 }, 
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 }, 
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 }, 
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 }, 
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 }, 
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 }, 
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 }, 
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 }, 
+	{ 0x130a5, 0x0 }, 
+	{ 0x130a6, 0x0 }, 
+	{ 0x130a7, 0x0 }, 
+	{ 0x2007c, 0x0 }, 
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 }, 
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 }, 
+	{ 0x400c0, 0x0 }, 
+	{ 0x90201, 0x0 }, 
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 }, 
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 }, 
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 }, 
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 }, 
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 }, 
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 }, 
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 }, 
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 }, 
+	{ 0x10162, 0x0 }, 
+	{ 0x10262, 0x0 }, 
+	{ 0x10362, 0x0 }, 
+	{ 0x10462, 0x0 }, 
+	{ 0x10562, 0x0 }, 
+	{ 0x10662, 0x0 }, 
+	{ 0x10762, 0x0 }, 
+	{ 0x10862, 0x0 }, 
+	{ 0x11062, 0x0 }, 
+	{ 0x11162, 0x0 }, 
+	{ 0x11262, 0x0 }, 
+	{ 0x11362, 0x0 }, 
+	{ 0x11462, 0x0 }, 
+	{ 0x11562, 0x0 }, 
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x1},
+	{0x54003,0x29c},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x994},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x994},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x9400},
+	{0x54033,0x3109},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0x9400},
+	{0x54039,0x3109},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x110},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
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+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+#elif defined(CONFIG_4GB_LPDDR4)
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa3080020},
+	{0x3d400028,0x0},
+	{0x3d400020,0x203},
+	{0x3d400024,0x3e800},
+	{0x3d400064,0x6100e0},
+	{0x3d4000d0,0xc003061c},
+	{0x3d4000d4,0x9e0000},
+	{0x3d4000dc,0xd4002d},
+	{0x3d4000e0,0x310008},
+	{0x3d4000e8,0x66004a},
+	{0x3d4000ec,0x16004a},
+	{0x3d400100,0x1a201b22},
+	{0x3d400104,0x60633},
+	{0x3d40010c,0xc0c000},
+	{0x3d400110,0xf04080f},
+	{0x3d400114,0x2040c0c},
+	{0x3d400118,0x1010007},
+	{0x3d40011c,0x401},
+	{0x3d400130,0x20600},
+	{0x3d400134,0xc100002},
+	{0x3d400138,0xe6},
+	{0x3d400144,0xa00050},
+	{0x3d400180,0xc3200018},
+	{0x3d400184,0x28061a8},
+	{0x3d400188,0x0},
+	{0x3d400190,0x497820a},
+	{0x3d400194,0x80303},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001b4,0x170a},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0x639},
+	{0x3d400108,0x70e1617},
+	{0x3d400200,0x17},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0x7070707},
+	{0x3d402020,0x1},
+	{0x3d402024,0xd0c0},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0x14002f},
+	{0x3d4020dc,0x940009},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004a},
+	{0x3d4020ec,0x16004a},
+	{0x3d402100,0xb070508},
+	{0x3d402104,0x3040b},
+	{0x3d402108,0x305090c},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x4040204},
+	{0x3d402114,0x2030303},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x31},
+	{0x3d402144,0x220011},
+	{0x3d402180,0xc0a70006},
+	{0x3d402190,0x3858202},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x502},
+	{0x3d400244,0x0},
+	{0x3d400250,0x29001505},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x5900575b},
+	{0x3d400264,0x90000096},
+	{0x3d40026c,0x1000012c},
+	{0x3d400300,0x16},
+	{0x3d400304,0x0},
+	{0x3d40030c,0x0},
+	{0x3d400320,0x1},
+	{0x3d40036c,0x11},
+	{0x3d400400,0x111},
+	{0x3d400404,0x10f3},
+	{0x3d400408,0x72ff},
+	{0x3d400490,0x1},
+	{0x3d400494,0xe00},
+	{0x3d400498,0x62ffff},
+	{0x3d40049c,0xe00},
+	{0x3d4004a0,0xffff},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x2},
+	{0x110a3,0x3},
+	{0x110a4,0x4},
+	{0x110a5,0x7},
+	{0x110a6,0x6},
+	{0x110a7,0x5},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x2},
+	{0x120a3,0x3},
+	{0x120a4,0x4},
+	{0x120a5,0x5},
+	{0x120a6,0x6},
+	{0x120a7,0x7},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x20110,0x2},
+	{0x20111,0x3},
+	{0x20112,0x4},
+	{0x20113,0x5},
+	{0x20114,0x0},
+	{0x20115,0x1},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0x19},
+	{0x1200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x1},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x3},
+	{0x120056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x320},
+	{0x120008,0xa7},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x200f0,0x0},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5555},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x200c7,0x80},
+	{0x1200c7,0x80},
+	{0x200ca,0x106},
+	{0x1200ca,0x106},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },  
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },  
+	{ 0x10043, 0x0 },  
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },  
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },  
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },  
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },  
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },  
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },  
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },  
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },       
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },    
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },    
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },    
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },    
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },    
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },    
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },    
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },    
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },    
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },  
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },  
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },  
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },  
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },  
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },  
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },  
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },  
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },  
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },  
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },  
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },  
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },  
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },  
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },  
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },  
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },  
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },  
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },  
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },  
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },  
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },  
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },  
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },  
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },  
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 }, 
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 }, 
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 }, 
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 }, 
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 }, 
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 }, 
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 }, 
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 }, 
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 }, 
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 }, 
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 }, 
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 }, 
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 }, 
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 }, 
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 }, 
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 }, 
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 }, 
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 }, 
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 }, 
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 }, 
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 }, 
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 }, 
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 }, 
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 }, 
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 }, 
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 }, 
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 }, 
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 }, 
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 }, 
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 }, 
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 }, 
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 }, 
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 }, 
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 }, 
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 }, 
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 }, 
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 }, 
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 }, 
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 }, 
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 }, 
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 }, 
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 }, 
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 }, 
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 }, 
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 }, 
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 }, 
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 }, 
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 }, 
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 }, 
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 }, 
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 }, 
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 }, 
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 }, 
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 }, 
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 }, 
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 }, 
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 }, 
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 }, 
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 }, 
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 }, 
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 }, 
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 }, 
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 }, 
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 }, 
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 }, 
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 }, 
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 }, 
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 }, 
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 }, 
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 }, 
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 }, 
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 }, 
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 }, 
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 }, 
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 }, 
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 }, 
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 }, 
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 }, 
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 }, 
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 }, 
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 }, 
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 }, 
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 }, 
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 }, 
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 }, 
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 }, 
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 }, 
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 }, 
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 }, 
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 }, 
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 }, 
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 }, 
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 }, 
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 }, 
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 }, 
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 }, 
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 }, 
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 }, 
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 }, 
+	{ 0x20073, 0x0 }, 
+	{ 0x20074, 0x0 }, 
+	{ 0x100aa, 0x0 }, 
+	{ 0x110aa, 0x0 }, 
+	{ 0x120aa, 0x0 }, 
+	{ 0x130aa, 0x0 }, 
+	{ 0x20010, 0x0 }, 
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 }, 
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 }, 
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 }, 
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 }, 
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 }, 
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 }, 
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 }, 
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 }, 
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 }, 
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 }, 
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 }, 
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 }, 
+	{ 0x130a5, 0x0 }, 
+	{ 0x130a6, 0x0 }, 
+	{ 0x130a7, 0x0 }, 
+	{ 0x2007c, 0x0 }, 
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 }, 
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 }, 
+	{ 0x400c0, 0x0 }, 
+	{ 0x90201, 0x0 }, 
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 }, 
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 }, 
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 }, 
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 }, 
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 }, 
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 }, 
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 }, 
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 }, 
+	{ 0x10162, 0x0 }, 
+	{ 0x10262, 0x0 }, 
+	{ 0x10362, 0x0 }, 
+	{ 0x10462, 0x0 }, 
+	{ 0x10562, 0x0 }, 
+	{ 0x10662, 0x0 }, 
+	{ 0x10762, 0x0 }, 
+	{ 0x10862, 0x0 }, 
+	{ 0x11062, 0x0 }, 
+	{ 0x11162, 0x0 }, 
+	{ 0x11262, 0x0 }, 
+	{ 0x11362, 0x0 }, 
+	{ 0x11462, 0x0 }, 
+	{ 0x11562, 0x0 }, 
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x310},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x1},
+	{0x54003,0x29c},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x310},
+	{0x54019,0x994},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x994},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0x9400},
+	{0x54033,0x3109},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0x9400},
+	{0x54039,0x3109},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xc80},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x310},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4a66},
+	{0x5401c,0x4a08},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4a66},
+	{0x54022,0x4a08},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x84a},
+	{0x54036,0x4a},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x84a},
+	{0x5403c,0x4a},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
+	{0x90043,0x149},
+	{0x90044,0x4f},
+	{0x90045,0x630},
+	{0x90046,0x179},
+	{0x90047,0x8},
+	{0x90048,0xe0},
+	{0x90049,0x109},
+	{0x9004a,0x0},
+	{0x9004b,0x7c8},
+	{0x9004c,0x109},
+	{0x9004d,0x0},
+	{0x9004e,0x1},
+	{0x9004f,0x8},
+	{0x90050,0x0},
+	{0x90051,0x45a},
+	{0x90052,0x9},
+	{0x90053,0x0},
+	{0x90054,0x448},
+	{0x90055,0x109},
+	{0x90056,0x40},
+	{0x90057,0x630},
+	{0x90058,0x179},
+	{0x90059,0x1},
+	{0x9005a,0x618},
+	{0x9005b,0x109},
+	{0x9005c,0x40c0},
+	{0x9005d,0x630},
+	{0x9005e,0x149},
+	{0x9005f,0x8},
+	{0x90060,0x4},
+	{0x90061,0x48},
+	{0x90062,0x4040},
+	{0x90063,0x630},
+	{0x90064,0x149},
+	{0x90065,0x0},
+	{0x90066,0x4},
+	{0x90067,0x48},
+	{0x90068,0x40},
+	{0x90069,0x630},
+	{0x9006a,0x149},
+	{0x9006b,0x10},
+	{0x9006c,0x4},
+	{0x9006d,0x18},
+	{0x9006e,0x0},
+	{0x9006f,0x4},
+	{0x90070,0x78},
+	{0x90071,0x549},
+	{0x90072,0x630},
+	{0x90073,0x159},
+	{0x90074,0xd49},
+	{0x90075,0x630},
+	{0x90076,0x159},
+	{0x90077,0x94a},
+	{0x90078,0x630},
+	{0x90079,0x159},
+	{0x9007a,0x441},
+	{0x9007b,0x630},
+	{0x9007c,0x149},
+	{0x9007d,0x42},
+	{0x9007e,0x630},
+	{0x9007f,0x149},
+	{0x90080,0x1},
+	{0x90081,0x630},
+	{0x90082,0x149},
+	{0x90083,0x0},
+	{0x90084,0xe0},
+	{0x90085,0x109},
+	{0x90086,0xa},
+	{0x90087,0x10},
+	{0x90088,0x109},
+	{0x90089,0x9},
+	{0x9008a,0x3c0},
+	{0x9008b,0x149},
+	{0x9008c,0x9},
+	{0x9008d,0x3c0},
+	{0x9008e,0x159},
+	{0x9008f,0x18},
+	{0x90090,0x10},
+	{0x90091,0x109},
+	{0x90092,0x0},
+	{0x90093,0x3c0},
+	{0x90094,0x109},
+	{0x90095,0x18},
+	{0x90096,0x4},
+	{0x90097,0x48},
+	{0x90098,0x18},
+	{0x90099,0x4},
+	{0x9009a,0x58},
+	{0x9009b,0xa},
+	{0x9009c,0x10},
+	{0x9009d,0x109},
+	{0x9009e,0x2},
+	{0x9009f,0x10},
+	{0x900a0,0x109},
+	{0x900a1,0x5},
+	{0x900a2,0x7c0},
+	{0x900a3,0x109},
+	{0x900a4,0x10},
+	{0x900a5,0x10},
+	{0x900a6,0x109},
+	{0x40000,0x811},
+	{0x40020,0x880},
+	{0x40040,0x0},
+	{0x40060,0x0},
+	{0x40001,0x4008},
+	{0x40021,0x83},
+	{0x40041,0x4f},
+	{0x40061,0x0},
+	{0x40002,0x4040},
+	{0x40022,0x83},
+	{0x40042,0x51},
+	{0x40062,0x0},
+	{0x40003,0x811},
+	{0x40023,0x880},
+	{0x40043,0x0},
+	{0x40063,0x0},
+	{0x40004,0x720},
+	{0x40024,0xf},
+	{0x40044,0x1740},
+	{0x40064,0x0},
+	{0x40005,0x16},
+	{0x40025,0x83},
+	{0x40045,0x4b},
+	{0x40065,0x0},
+	{0x40006,0x716},
+	{0x40026,0xf},
+	{0x40046,0x2001},
+	{0x40066,0x0},
+	{0x40007,0x716},
+	{0x40027,0xf},
+	{0x40047,0x2800},
+	{0x40067,0x0},
+	{0x40008,0x716},
+	{0x40028,0xf},
+	{0x40048,0xf00},
+	{0x40068,0x0},
+	{0x40009,0x720},
+	{0x40029,0xf},
+	{0x40049,0x1400},
+	{0x40069,0x0},
+	{0x4000a,0xe08},
+	{0x4002a,0xc15},
+	{0x4004a,0x0},
+	{0x4006a,0x0},
+	{0x4000b,0x623},
+	{0x4002b,0x15},
+	{0x4004b,0x0},
+	{0x4006b,0x0},
+	{0x4000c,0x4028},
+	{0x4002c,0x80},
+	{0x4004c,0x0},
+	{0x4006c,0x0},
+	{0x4000d,0xe08},
+	{0x4002d,0xc1a},
+	{0x4004d,0x0},
+	{0x4006d,0x0},
+	{0x4000e,0x623},
+	{0x4002e,0x1a},
+	{0x4004e,0x0},
+	{0x4006e,0x0},
+	{0x4000f,0x4040},
+	{0x4002f,0x80},
+	{0x4004f,0x0},
+	{0x4006f,0x0},
+	{0x40010,0x2604},
+	{0x40030,0x15},
+	{0x40050,0x0},
+	{0x40070,0x0},
+	{0x40011,0x708},
+	{0x40031,0x5},
+	{0x40051,0x0},
+	{0x40071,0x2002},
+	{0x40012,0x8},
+	{0x40032,0x80},
+	{0x40052,0x0},
+	{0x40072,0x0},
+	{0x40013,0x2604},
+	{0x40033,0x1a},
+	{0x40053,0x0},
+	{0x40073,0x0},
+	{0x40014,0x708},
+	{0x40034,0xa},
+	{0x40054,0x0},
+	{0x40074,0x2002},
+	{0x40015,0x4040},
+	{0x40035,0x80},
+	{0x40055,0x0},
+	{0x40075,0x0},
+	{0x40016,0x60a},
+	{0x40036,0x15},
+	{0x40056,0x1200},
+	{0x40076,0x0},
+	{0x40017,0x61a},
+	{0x40037,0x15},
+	{0x40057,0x1300},
+	{0x40077,0x0},
+	{0x40018,0x60a},
+	{0x40038,0x1a},
+	{0x40058,0x1200},
+	{0x40078,0x0},
+	{0x40019,0x642},
+	{0x40039,0x1a},
+	{0x40059,0x1300},
+	{0x40079,0x0},
+	{0x4001a,0x4808},
+	{0x4003a,0x880},
+	{0x4005a,0x0},
+	{0x4007a,0x0},
+	{0x900a7,0x0},
+	{0x900a8,0x790},
+	{0x900a9,0x11a},
+	{0x900aa,0x8},
+	{0x900ab,0x7aa},
+	{0x900ac,0x2a},
+	{0x900ad,0x10},
+	{0x900ae,0x7b2},
+	{0x900af,0x2a},
+	{0x900b0,0x0},
+	{0x900b1,0x7c8},
+	{0x900b2,0x109},
+	{0x900b3,0x10},
+	{0x900b4,0x2a8},
+	{0x900b5,0x129},
+	{0x900b6,0x8},
+	{0x900b7,0x370},
+	{0x900b8,0x129},
+	{0x900b9,0xa},
+	{0x900ba,0x3c8},
+	{0x900bb,0x1a9},
+	{0x900bc,0xc},
+	{0x900bd,0x408},
+	{0x900be,0x199},
+	{0x900bf,0x14},
+	{0x900c0,0x790},
+	{0x900c1,0x11a},
+	{0x900c2,0x8},
+	{0x900c3,0x4},
+	{0x900c4,0x18},
+	{0x900c5,0xe},
+	{0x900c6,0x408},
+	{0x900c7,0x199},
+	{0x900c8,0x8},
+	{0x900c9,0x8568},
+	{0x900ca,0x108},
+	{0x900cb,0x18},
+	{0x900cc,0x790},
+	{0x900cd,0x16a},
+	{0x900ce,0x8},
+	{0x900cf,0x1d8},
+	{0x900d0,0x169},
+	{0x900d1,0x10},
+	{0x900d2,0x8558},
+	{0x900d3,0x168},
+	{0x900d4,0x70},
+	{0x900d5,0x788},
+	{0x900d6,0x16a},
+	{0x900d7,0x1ff8},
+	{0x900d8,0x85a8},
+	{0x900d9,0x1e8},
+	{0x900da,0x50},
+	{0x900db,0x798},
+	{0x900dc,0x16a},
+	{0x900dd,0x60},
+	{0x900de,0x7a0},
+	{0x900df,0x16a},
+	{0x900e0,0x8},
+	{0x900e1,0x8310},
+	{0x900e2,0x168},
+	{0x900e3,0x8},
+	{0x900e4,0xa310},
+	{0x900e5,0x168},
+	{0x900e6,0xa},
+	{0x900e7,0x408},
+	{0x900e8,0x169},
+	{0x900e9,0x6e},
+	{0x900ea,0x0},
+	{0x900eb,0x68},
+	{0x900ec,0x0},
+	{0x900ed,0x408},
+	{0x900ee,0x169},
+	{0x900ef,0x0},
+	{0x900f0,0x8310},
+	{0x900f1,0x168},
+	{0x900f2,0x0},
+	{0x900f3,0xa310},
+	{0x900f4,0x168},
+	{0x900f5,0x1ff8},
+	{0x900f6,0x85a8},
+	{0x900f7,0x1e8},
+	{0x900f8,0x68},
+	{0x900f9,0x798},
+	{0x900fa,0x16a},
+	{0x900fb,0x78},
+	{0x900fc,0x7a0},
+	{0x900fd,0x16a},
+	{0x900fe,0x68},
+	{0x900ff,0x790},
+	{0x90100,0x16a},
+	{0x90101,0x8},
+	{0x90102,0x8b10},
+	{0x90103,0x168},
+	{0x90104,0x8},
+	{0x90105,0xab10},
+	{0x90106,0x168},
+	{0x90107,0xa},
+	{0x90108,0x408},
+	{0x90109,0x169},
+	{0x9010a,0x58},
+	{0x9010b,0x0},
+	{0x9010c,0x68},
+	{0x9010d,0x0},
+	{0x9010e,0x408},
+	{0x9010f,0x169},
+	{0x90110,0x0},
+	{0x90111,0x8b10},
+	{0x90112,0x168},
+	{0x90113,0x0},
+	{0x90114,0xab10},
+	{0x90115,0x168},
+	{0x90116,0x0},
+	{0x90117,0x1d8},
+	{0x90118,0x169},
+	{0x90119,0x80},
+	{0x9011a,0x790},
+	{0x9011b,0x16a},
+	{0x9011c,0x18},
+	{0x9011d,0x7aa},
+	{0x9011e,0x6a},
+	{0x9011f,0xa},
+	{0x90120,0x0},
+	{0x90121,0x1e9},
+	{0x90122,0x8},
+	{0x90123,0x8080},
+	{0x90124,0x108},
+	{0x90125,0xf},
+	{0x90126,0x408},
+	{0x90127,0x169},
+	{0x90128,0xc},
+	{0x90129,0x0},
+	{0x9012a,0x68},
+	{0x9012b,0x9},
+	{0x9012c,0x0},
+	{0x9012d,0x1a9},
+	{0x9012e,0x0},
+	{0x9012f,0x408},
+	{0x90130,0x169},
+	{0x90131,0x0},
+	{0x90132,0x8080},
+	{0x90133,0x108},
+	{0x90134,0x8},
+	{0x90135,0x7aa},
+	{0x90136,0x6a},
+	{0x90137,0x0},
+	{0x90138,0x8568},
+	{0x90139,0x108},
+	{0x9013a,0xb7},
+	{0x9013b,0x790},
+	{0x9013c,0x16a},
+	{0x9013d,0x1f},
+	{0x9013e,0x0},
+	{0x9013f,0x68},
+	{0x90140,0x8},
+	{0x90141,0x8558},
+	{0x90142,0x168},
+	{0x90143,0xf},
+	{0x90144,0x408},
+	{0x90145,0x169},
+	{0x90146,0xc},
+	{0x90147,0x0},
+	{0x90148,0x68},
+	{0x90149,0x0},
+	{0x9014a,0x408},
+	{0x9014b,0x169},
+	{0x9014c,0x0},
+	{0x9014d,0x8558},
+	{0x9014e,0x168},
+	{0x9014f,0x8},
+	{0x90150,0x3c8},
+	{0x90151,0x1a9},
+	{0x90152,0x3},
+	{0x90153,0x370},
+	{0x90154,0x129},
+	{0x90155,0x20},
+	{0x90156,0x2aa},
+	{0x90157,0x9},
+	{0x90158,0x0},
+	{0x90159,0x400},
+	{0x9015a,0x10e},
+	{0x9015b,0x8},
+	{0x9015c,0xe8},
+	{0x9015d,0x109},
+	{0x9015e,0x0},
+	{0x9015f,0x8140},
+	{0x90160,0x10c},
+	{0x90161,0x10},
+	{0x90162,0x8138},
+	{0x90163,0x10c},
+	{0x90164,0x8},
+	{0x90165,0x7c8},
+	{0x90166,0x101},
+	{0x90167,0x8},
+	{0x90168,0x0},
+	{0x90169,0x8},
+	{0x9016a,0x8},
+	{0x9016b,0x448},
+	{0x9016c,0x109},
+	{0x9016d,0xf},
+	{0x9016e,0x7c0},
+	{0x9016f,0x109},
+	{0x90170,0x0},
+	{0x90171,0xe8},
+	{0x90172,0x109},
+	{0x90173,0x47},
+	{0x90174,0x630},
+	{0x90175,0x109},
+	{0x90176,0x8},
+	{0x90177,0x618},
+	{0x90178,0x109},
+	{0x90179,0x8},
+	{0x9017a,0xe0},
+	{0x9017b,0x109},
+	{0x9017c,0x0},
+	{0x9017d,0x7c8},
+	{0x9017e,0x109},
+	{0x9017f,0x8},
+	{0x90180,0x8140},
+	{0x90181,0x10c},
+	{0x90182,0x0},
+	{0x90183,0x1},
+	{0x90184,0x8},
+	{0x90185,0x8},
+	{0x90186,0x4},
+	{0x90187,0x8},
+	{0x90188,0x8},
+	{0x90189,0x7c8},
+	{0x9018a,0x101},
+	{0x90006,0x0},
+	{0x90007,0x0},
+	{0x90008,0x8},
+	{0x90009,0x0},
+	{0x9000a,0x0},
+	{0x9000b,0x0},
+	{0xd00e7,0x400},
+	{0x90017,0x0},
+	{0x9001f,0x2a},
+	{0x90026,0x6a},
+	{0x400d0,0x0},
+	{0x400d1,0x101},
+	{0x400d2,0x105},
+	{0x400d3,0x107},
+	{0x400d4,0x10f},
+	{0x400d5,0x202},
+	{0x400d6,0x20a},
+	{0x400d7,0x20b},
+	{0x2003a,0x2},
+	{0x2000b,0x64},
+	{0x2000c,0xc8},
+	{0x2000d,0x7d0},
+	{0x2000e,0x2c},
+	{0x12000b,0x14},
+	{0x12000c,0x29},
+	{0x12000d,0x1a1},
+	{0x12000e,0x10},
+	{0x9000c,0x0},
+	{0x9000d,0x173},
+	{0x9000e,0x60},
+	{0x9000f,0x6110},
+	{0x90010,0x2152},
+	{0x90011,0xdfbd},
+	{0x90012,0x60},
+	{0x90013,0x6152},
+	{0x20010,0x5a},
+	{0x20011,0x3},
+	{0x120010,0x5a},
+	{0x120011,0x3},
+	{0x40080,0xe0},
+	{0x40081,0x12},
+	{0x40082,0xe0},
+	{0x40083,0x12},
+	{0x40084,0xe0},
+	{0x40085,0x12},
+	{0x140080,0xe0},
+	{0x140081,0x12},
+	{0x140082,0xe0},
+	{0x140083,0x12},
+	{0x140084,0xe0},
+	{0x140085,0x12},
+	{0x400fd,0xf},
+	{0x10011,0x1},
+	{0x10012,0x1},
+	{0x10013,0x180},
+	{0x10018,0x1},
+	{0x10002,0x6209},
+	{0x100b2,0x1},
+	{0x101b4,0x1},
+	{0x102b4,0x1},
+	{0x103b4,0x1},
+	{0x104b4,0x1},
+	{0x105b4,0x1},
+	{0x106b4,0x1},
+	{0x107b4,0x1},
+	{0x108b4,0x1},
+	{0x11011,0x1},
+	{0x11012,0x1},
+	{0x11013,0x180},
+	{0x11018,0x1},
+	{0x11002,0x6209},
+	{0x110b2,0x1},
+	{0x111b4,0x1},
+	{0x112b4,0x1},
+	{0x113b4,0x1},
+	{0x114b4,0x1},
+	{0x115b4,0x1},
+	{0x116b4,0x1},
+	{0x117b4,0x1},
+	{0x118b4,0x1},
+	{0x12011,0x1},
+	{0x12012,0x1},
+	{0x12013,0x180},
+	{0x12018,0x1},
+	{0x12002,0x6209},
+	{0x120b2,0x1},
+	{0x121b4,0x1},
+	{0x122b4,0x1},
+	{0x123b4,0x1},
+	{0x124b4,0x1},
+	{0x125b4,0x1},
+	{0x126b4,0x1},
+	{0x127b4,0x1},
+	{0x128b4,0x1},
+	{0x13011,0x1},
+	{0x13012,0x1},
+	{0x13013,0x180},
+	{0x13018,0x1},
+	{0x13002,0x6209},
+	{0x130b2,0x1},
+	{0x131b4,0x1},
+	{0x132b4,0x1},
+	{0x133b4,0x1},
+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
+#else
+#error "no configuration for this board"
+#endif
diff --git a/board/embedian/smarcimx8mq/smarcimx8mq.c b/board/embedian/smarcimx8mq/smarcimx8mq.c
new file mode 100644
index 0000000..9eedb2c
--- /dev/null
+++ b/board/embedian/smarcimx8mq/smarcimx8mq.c
@@ -0,0 +1,756 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/video_common.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <dm.h>
+#include "../../freescale/common/tcpc.h"
+#include "../../freescale/common/pfuze.h"
+#include "../../freescale/common/mmc.c"
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define QSPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+#define WEAK_PULLUP     (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const qspi_pads[] = {
+	IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+	IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
+
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CONSOLE_SER3
+static iomux_v3_cfg_t const uart1_pads[] = {
+        IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+static iomux_v3_cfg_t const uart2_pads[] = {
+        IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+static iomux_v3_cfg_t const uart3_pads[] = {
+        IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_CONSOLE_SER0
+static iomux_v3_cfg_t const uart4_pads[] = {
+        IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+        IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+/* SPI0*/
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+        IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+        IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+        IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS0#*/
+        IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS1#*/
+        IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS2#*/
+        IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),   /*SS3#*/
+};
+
+/* MISC PINs */
+static iomux_v3_cfg_t const misc_pads[] = {
+        IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP),             /*S146, PCIE_WAKE*/
+        IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP),           /*S148, LID#*/
+        IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),          /*S149, SLEEP#*/
+        IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),           /*S151, CHARGING#*/
+        IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP),          	/*S152, CHARGER_PRSNT#*/
+        IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),            /*S153, CARRIER_STBY#*/
+        IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),          	/*S156, BATLOW#*/
+        IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),           /*CAN0_INT#*/
+        IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),        /*CAN1_INT#*/
+};
+
+static void setup_iomux_misc(void)
+{
+        imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+        /* Set CARRIER_LID# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 9), "LID#");
+        gpio_direction_input(IMX_GPIO_NR(1, 9));
+        /* Set CARRIER_SLEEP# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 12), "SLEEP#");
+        gpio_direction_input(IMX_GPIO_NR(1, 12));
+        /* Set CARRIER_CHARGING# as Input*/
+        gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#");
+        gpio_direction_input(IMX_GPIO_NR(1, 01));
+        /* Set CARRIER_CHARGER_PRSNT# as Input*/
+        gpio_request(IMX_GPIO_NR(4, 22), "CHARGER_PRSNT#");
+        gpio_direction_input(IMX_GPIO_NR(4, 22));
+        /* Set CARRIER_STBY# as Output High*/
+        gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#");
+        gpio_direction_output(IMX_GPIO_NR(5, 02) , 1);
+        /* Set CARRIER_BATLOW# as Input*/
+        gpio_request(IMX_GPIO_NR(4, 21), "BATLOW#");
+        gpio_direction_input(IMX_GPIO_NR(4, 21));
+        /* Set PCIE_WAKE# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#");
+        gpio_direction_input(IMX_GPIO_NR(3, 5));
+        /* Set CAN0_INT# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#");
+        gpio_direction_input(IMX_GPIO_NR(3, 18));
+        /* Set CAN1_INT# as Input*/
+        gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#");
+        gpio_direction_input(IMX_GPIO_NR(3, 16));
+}
+
+/* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/
+static iomux_v3_cfg_t const gpio_pads[] = {
+        IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P108, GPIO0*/
+        IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P109, GPIO1*/
+        IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),            /*P110, GPIO2*/
+        IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P111, GPIO3*/
+        IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P112, GPIO4*/
+        IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP),             /*P113, GPIO5*/
+        IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),             /*P114, GPIO6*/
+        IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P115, GPIO7*/
+        IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P116, GPIO8*/
+        IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),            /*P114, GPIO9*/
+        IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P115, GPIO10*/
+        IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),           /*P116, GPIO11*/
+};
+
+static void setup_iomux_gpio(void)
+{
+        imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+
+        /* Set GPIO0 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 25), "GPIO0");
+        gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
+        /* Set GPIO1 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 19), "GPIO1");
+        gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+        /* Set GPIO2 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 20), "GPIO2");
+        gpio_direction_output(IMX_GPIO_NR(3, 20), 0);
+        /* Set GPIO3 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 21), "GPIO3");
+        gpio_direction_output(IMX_GPIO_NR(3, 21), 0);
+        /* Set GPIO4 as Output Low*/
+        gpio_request(IMX_GPIO_NR(3, 22), "GPIO4");
+        gpio_direction_output(IMX_GPIO_NR(3, 22), 0);
+        /* Set GPIO5 as Output Low*/
+        gpio_request(IMX_GPIO_NR(5, 3), "GPIO5");
+        gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
+        /* Set GPIO6 as Input*/
+        gpio_request(IMX_GPIO_NR(5, 4), "GPIO6");
+        gpio_direction_input(IMX_GPIO_NR(5, 4));
+        /* Set GPIO7 as Input*/
+        gpio_request(IMX_GPIO_NR(3, 23), "GPIO7");
+        gpio_direction_input(IMX_GPIO_NR(3, 23));
+        /* Set GPIO8 as Input*/
+        gpio_request(IMX_GPIO_NR(3, 24), "GPIO8");
+        gpio_direction_input(IMX_GPIO_NR(3, 24));
+        /* Set GPIO9 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 11), "GPIO9");
+        gpio_direction_input(IMX_GPIO_NR(4, 11));
+        /* Set GPIO10 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 10), "GPIO10");
+        gpio_direction_input(IMX_GPIO_NR(4, 10));
+        /* Set GPIO11 as Input*/
+        gpio_request(IMX_GPIO_NR(4, 20), "GPIO11");
+        gpio_direction_input(IMX_GPIO_NR(4, 20));
+}
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+#ifdef CONFIG_CONSOLE_SER0
+        imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+#endif
+#ifdef CONFIG_CONSOLE_SER1
+        imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+#endif
+#ifdef CONFIG_CONSOLE_SER2
+        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+#endif
+#ifdef CONFIG_CONSOLE_SER3
+        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+	/* TODO */
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C
+/*I2C2, I2C_CAM0 and I2C_LCD*/
+struct i2c_pads_info i2c_pad_info2 = {
+        .scl = {
+                .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 16),
+        },
+        .sda = {
+                .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 17),
+        },
+};
+
+/*I2C3, I2C_GP*/
+struct i2c_pads_info i2c_pad_info3 = {
+        .scl = {
+                .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 18),
+        },
+        .sda = {
+                .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 19),
+        },
+};
+
+/*I2C4, I2C_CAM1*/
+struct i2c_pads_info i2c_pad_info4 = {
+        .scl = {
+                .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 20),
+        },
+        .sda = {
+                .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL,
+                .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL,
+                .gp = IMX_GPIO_NR(5, 21),
+        },
+};
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+/* Get the top of usable RAM */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+
+        //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size);
+
+        if(gd->ram_top > 0x100000000)
+           gd->ram_top = 0x100000000;
+
+        return gd->ram_top;
+}
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 11)
+static iomux_v3_cfg_t const fec1_irq_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_irq_pads,
+					 ARRAY_SIZE(fec1_irq_pads));
+
+        gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq");
+        gpio_direction_input(IMX_GPIO_NR(1, 11));
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+static void setup_iomux_ecspi1(void)
+{
+        imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+                                         ARRAY_SIZE(ecspi1_pads));
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+        gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0");
+        return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1;
+        gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1");
+        return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1;
+        gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2");
+        return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1;
+        gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3");
+        return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1;
+}
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+        .maximum_speed = USB_SPEED_HIGH,
+#else
+        .maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+/*USB Enable Over-Current Pin Setting*/
+static iomux_v3_cfg_t const usb_en_oc_pads[] = {
+        IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
+        IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+        IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_usb_en_oc(void)
+{
+        imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads,
+                                         ARRAY_SIZE(usb_en_oc_pads));
+
+        gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 10));
+        gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 12));
+        gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#");
+        gpio_direction_input(IMX_GPIO_NR(3, 13));
+}
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 0,
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+#define USB_TYPEC_SEL IMX_GPIO_NR(3, 15)
+
+static iomux_v3_cfg_t ss_mux_gpio[] = {
+	IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		gpio_direction_output(USB_TYPEC_SEL, 1);
+	else
+		gpio_direction_output(USB_TYPEC_SEL, 0);
+}
+
+static int setup_typec(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+	gpio_request(USB_TYPEC_SEL, "typec_sel");
+
+	ret = tcpc_init(&port, port_config, &ss_mux_select);
+	if (ret) {
+		printf("%s: tcpc init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	imx8m_usb_power(index, true);
+
+	if (index == 0 && init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_ufp_mode(&port);
+#endif
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_dfp_mode(&port);
+#endif
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_disable_src_vbus(&port);
+#endif
+	}
+
+	imx8m_usb_power(index, false);
+
+	return ret;
+}
+#endif
+
+int board_init(void)
+{
+	board_qspi_init();
+        setup_iomux_usb_en_oc();
+        setup_iomux_misc();
+        setup_iomux_gpio();
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+	init_usb_clk();
+#endif
+
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+        setup_iomux_ecspi1();
+
+        /* Read Module Information from on module EEPROM and pass
+         * mac address to kernel
+        */
+        struct udevice *dev;
+        int ret;
+        u8 name[8];
+        u8 serial[12];
+        u8 revision[4];
+        u8 mac[6];
+
+        ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev);
+        if (ret) {
+                debug("failed to get eeprom\n");
+                return 0;
+        }
+
+        /* Board ID */
+        ret = dm_i2c_read(dev, 0x4, name, 8);
+        if (ret) {
+                debug("failed to read board ID from EEPROM\n");
+                return 0;
+        }
+        puts("---------Embedian SMARC-iMX8M------------\n");
+        printf("  Board ID:             %c%c%c%c%c%c%c%c\n",
+               name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);
+
+        /* Board Hardware Revision */
+        ret = dm_i2c_read(dev, 0xc, revision, 4);
+        if (ret) {
+                debug("failed to read hardware revison from EEPROM\n");
+                return 0;
+        }
+        printf("  Hardware Revision:    %c%c%c%c\n",
+               revision[0], revision[1], revision[2], revision[3]);
+
+        /* Serial number */
+        ret = dm_i2c_read(dev, 0x10, serial, 12);
+        if (ret) {
+                debug("failed to read srial number from EEPROM\n");
+                return 0;
+        }
+        printf("  Serial Number#:       %c%c%c%c%c%c%c%c%c%c%c%c\n",
+               serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);
+
+        /*MAC address */
+        ret = dm_i2c_read(dev, 0x3c, mac, 6);
+        if (ret) {
+                debug("failed to read eth0 mac address from EEPROM\n");
+                return 0;
+        }
+
+        if (is_valid_ethaddr(mac))
+        printf("  MAC Address:          %02x:%02x:%02x:%02x:%02x:%02x\n",
+               mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+                eth_env_set_enetaddr("ethaddr", mac);
+        puts("-----------------------------------------\n");
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "SMARC-iMX8M");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+/* SMARC BOOT_SEL*/
+        gpio_request(IMX_GPIO_NR(1, 8), "BOOT_SEL_1");
+        gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2");
+        gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3");
+        if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n");
+                env_set_ulong("usb dev", 1);
+                env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n");
+                env_set_ulong("mmcdev", 1);
+                env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n");
+                env_set_ulong("mmcdev", 0);
+                env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
+                env_set("bootcmd", "run netboot;");
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
+                puts("Carrier SPI Boot is not supported...\n");
+                hang();
+        } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
+                puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n");
+                hang();
+        } else {
+                puts("unsupported boot devices\n");
+                hang();
+        }
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+#define LID_KEY IMX_GPIO_NR(1, 9)
+#define LID_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const lid_pads[] = {
+        IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL),
+};
+
+int is_recovery_key_pressing(void)
+{
+        imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads));
+        gpio_request(LID_KEY, "LID");
+        gpio_direction_input(LID_KEY);
+        if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */
+                printf("Recovery key pressed\n");
+                return 1;
+        }
+	return 0;
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+#if defined(CONFIG_VIDEO_IMXDCSS)
+
+struct display_info_t const displays[] = {{
+	.bus	= 0, /* Unused */
+	.addr	= 0, /* Unused */
+	.pixfmt	= GDF_32BIT_X888RGB,
+	.detect	= NULL,
+	.enable	= NULL,
+#ifndef CONFIG_VIDEO_IMXDCSS_1080P
+	.mode	= {
+		.name           = "HDMI", /* 720P60 */
+		.refresh        = 60,
+		.xres           = 1280,
+		.yres           = 720,
+		.pixclock       = 13468, /* 74250  kHz */
+		.left_margin    = 110,
+		.right_margin   = 220,
+		.upper_margin   = 5,
+		.lower_margin   = 20,
+		.hsync_len      = 40,
+		.vsync_len      = 5,
+		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+#else
+	.mode	= {
+		.name           = "HDMI", /* 1080P60 */
+		.refresh        = 60,
+		.xres           = 1920,
+		.yres           = 1080,
+		.pixclock       = 6734, /* 148500 kHz */
+		.left_margin    = 148,
+		.right_margin   = 88,
+		.upper_margin   = 36,
+		.lower_margin   = 4,
+		.hsync_len      = 44,
+		.vsync_len      = 5,
+		.sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		.vmode          = FB_VMODE_NONINTERLACED
+	}
+#endif
+} };
+size_t display_count = ARRAY_SIZE(displays);
+
+#endif /* CONFIG_VIDEO_IMXDCSS */
+
+/* return hard code board id for imx8m_ref */
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+int get_imx8m_baseboard_id(void)
+{
+	return IMX8M_REF_3G;
+}
+#endif
diff --git a/board/embedian/smarcimx8mq/spl.c b/board/embedian/smarcimx8mq/spl.c
new file mode 100644
index 0000000..f9d0370
--- /dev/null
+++ b/board/embedian/smarcimx8mq/spl.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../../freescale/common/pfuze.h"
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8m_ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*extern struct dram_timing_info dram_timing_b0;*/
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+                ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+/* RESET_OUT */
+static iomux_v3_cfg_t const reset_out_pads[] = {
+        IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_reset_out(void)
+{
+        imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
+
+        /* Set CPU RESET_OUT as Output */
+        gpio_request(IMX_GPIO_NR(1, 03), "CPU_RESET");
+        gpio_direction_output(IMX_GPIO_NR(1, 03) , 0);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return -ENODEV;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return -ENODEV;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
+	if ((reg & 0x3f) != 0x18) {
+		reg &= ~0x3f;
+		reg |= 0x18;
+		pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+	}
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW3A standby mode to off */
+	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
+	reg &= ~0xf;
+	reg |= APS_OFF;
+	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+
+	init_usb_clk();
+
+	puts("Normal Boot\n");
+        setup_iomux_reset_out();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+#ifdef CONFIG_CONSOLE_SER3
+	init_uart_clk(0); /* Init UART0 clock */
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+        init_uart_clk(1); /* Init UART1 clock */
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+        init_uart_clk(2); /* Init UART2 clock */
+#endif
+
+#ifdef CONFIG_CONSOLE_SER0
+        init_uart_clk(3); /* Init UART3 clock */
+#endif
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x08, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/smarcimx8mq_2g_ser0_android_defconfig b/configs/smarcimx8mq_2g_ser0_android_defconfig
new file mode 100644
index 0000000..bf8cb8d
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser0_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER0=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_2g_ser0_androidthings_defconfig b/configs/smarcimx8mq_2g_ser0_androidthings_defconfig
new file mode 100644
index 0000000..2604ee1
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser0_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER0=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_2g_ser0_defconfig b/configs/smarcimx8mq_2g_ser0_defconfig
new file mode 100644
index 0000000..cff8ded
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser0_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER0=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_2g_ser1_android_defconfig b/configs/smarcimx8mq_2g_ser1_android_defconfig
new file mode 100644
index 0000000..9cca59b
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser1_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER1=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_2g_ser1_androidthings_defconfig b/configs/smarcimx8mq_2g_ser1_androidthings_defconfig
new file mode 100644
index 0000000..fb257fe
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser1_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER1=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_2g_ser1_defconfig b/configs/smarcimx8mq_2g_ser1_defconfig
new file mode 100644
index 0000000..5dffc58
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser1_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER1=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_2g_ser2_android_defconfig b/configs/smarcimx8mq_2g_ser2_android_defconfig
new file mode 100644
index 0000000..0cf681b
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser2_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_2g_ser2_androidthings_defconfig b/configs/smarcimx8mq_2g_ser2_androidthings_defconfig
new file mode 100644
index 0000000..86b3d72
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser2_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_2g_ser2_defconfig b/configs/smarcimx8mq_2g_ser2_defconfig
new file mode 100644
index 0000000..cb74397
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser2_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_2g_ser3_android_defconfig b/configs/smarcimx8mq_2g_ser3_android_defconfig
new file mode 100644
index 0000000..4849fe1
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser3_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER3=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_2g_ser3_androidthings_defconfig b/configs/smarcimx8mq_2g_ser3_androidthings_defconfig
new file mode 100644
index 0000000..50d70ec
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser3_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER3=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_2g_ser3_defconfig b/configs/smarcimx8mq_2g_ser3_defconfig
new file mode 100644
index 0000000..2a6be4c
--- /dev/null
+++ b/configs/smarcimx8mq_2g_ser3_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,2GB_LPDDR4"
+CONFIG_CONSOLE_SER3=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_4g_ser0_android_defconfig b/configs/smarcimx8mq_4g_ser0_android_defconfig
new file mode 100644
index 0000000..8da8054
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser0_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER0=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_4g_ser0_androidthings_defconfig b/configs/smarcimx8mq_4g_ser0_androidthings_defconfig
new file mode 100644
index 0000000..1b584ae
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser0_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER0=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_4g_ser0_defconfig b/configs/smarcimx8mq_4g_ser0_defconfig
new file mode 100644
index 0000000..bb65943
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser0_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER0=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_4g_ser1_android_defconfig b/configs/smarcimx8mq_4g_ser1_android_defconfig
new file mode 100644
index 0000000..fc64195
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser1_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER1=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_4g_ser1_androidthings_defconfig b/configs/smarcimx8mq_4g_ser1_androidthings_defconfig
new file mode 100644
index 0000000..151af0d
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser1_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER1=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_4g_ser1_defconfig b/configs/smarcimx8mq_4g_ser1_defconfig
new file mode 100644
index 0000000..f904729
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser1_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER1=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_4g_ser2_android_defconfig b/configs/smarcimx8mq_4g_ser2_android_defconfig
new file mode 100644
index 0000000..62e8c3a
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser2_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_4g_ser2_androidthings_defconfig b/configs/smarcimx8mq_4g_ser2_androidthings_defconfig
new file mode 100644
index 0000000..3f26729
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser2_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_4g_ser2_defconfig b/configs/smarcimx8mq_4g_ser2_defconfig
new file mode 100644
index 0000000..78edba4
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser2_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/smarcimx8mq_4g_ser3_android_defconfig b/configs/smarcimx8mq_4g_ser3_android_defconfig
new file mode 100644
index 0000000..e666103
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser3_android_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_SUPPORT"
+CONFIG_CONSOLE_SER3=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_NOT_UUU_BUILD=y
diff --git a/configs/smarcimx8mq_4g_ser3_androidthings_defconfig b/configs/smarcimx8mq_4g_ser3_androidthings_defconfig
new file mode 100644
index 0000000..09a4cc9
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser3_androidthings_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4,ANDROID_THINGS_SUPPORT"
+CONFIG_CONSOLE_SER3=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_BCB_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/smarcimx8mq_4g_ser3_defconfig b/configs/smarcimx8mq_4g_ser3_defconfig
new file mode 100644
index 0000000..2ae2f9c
--- /dev/null
+++ b/configs/smarcimx8mq_4g_ser3_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BOOTDELAY=1
+CONFIG_TARGET_SMARCIMX8MQ=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,4GB_LPDDR4"
+CONFIG_CONSOLE_SER3=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-smarcimx8mq"
+CONFIG_DEFAULT_FDT_FILE="fsl-smarcimx8mq.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_TIME=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 4cb234d..a1403bb 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -17,6 +17,16 @@ config SPL_RAM
 	  SPL, enable this option. It might provide a cleaner interface to
 	  setting up RAM (e.g. SDRAM / DDR) within SPL.
 
+config 2GB_LPDDR4
+        bool "SMARC-iMX8M with 16Gb LPDDR4 Memory"
+        help
+          Select this if the board is SMARC-iMX8M-D/L/Q-2G
+
+config 4GB_LPDDR4
+        bool "SMARC-iMX8M with 32Gb LPDDR4 Memory"
+        help
+          Select this if the board is SMARC-iMX8M-D/L/Q-4G
+
 config TPL_RAM
 	bool "Enable RAM support in TPL"
 	depends on RAM && TPL_DM
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c27e7f5..f56a456 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -568,22 +568,22 @@ config PXA_SERIAL
 	  can enable its onboard serial ports by enabling this option.
 
 config CONSOLE_SER0
-       	bool "SMARC-FiMX6 default console serial output port"
+       	bool "SMARC modules default console serial output port"
        	help
           Select this to enable a debug UART port from SER0 of SMARC-FiMX7.
  
 config CONSOLE_SER1
-       	bool "SMARC-FiMX6 default console serial output port"
+       	bool "SMARC modules default console serial output port"
        	help
           Select this to enable a debug UART port from SER1 of SMARC-FiMX7.
  
 config CONSOLE_SER2
-       	bool "SMARC-FiMX6 default console serial output port"
+       	bool "SMARC modules default console serial output port"
        	help
           Select this to enable a debug UART port from SER2 of SMARC-FiMX7.
  
 config CONSOLE_SER3
-       	bool "SMARC-FiMX6 default console serial output port"
+       	bool "SMARC modules default console serial output port"
        	help
           Select this to enable a debug UART port from SER3 of SMARC-FiMX7.
 
diff --git a/include/configs/smarcimx8mq.h b/include/configs/smarcimx8mq.h
new file mode 100644
index 0000000..1789cd7
--- /dev/null
+++ b/include/configs/smarcimx8mq.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SMARCIMX8MQ_H
+#define __SMARCIMX8MQ_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_TEXT_BASE		0x7E1000
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR      0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000	/* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_MALLOC_F_ADDR		0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          6
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE			0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mq.c, then clk_ingore_unused could be removed.
+ */
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_mmcboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; " \
+		"setenv jh_clk clk_ignore_unused; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=setenv fdt_file fsl-imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0"\
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	JAILHOUSE_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+        "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+        "usbroot=/dev/sda2 rootwait ro\0" \
+        "mmcrootfstype=ext4 rootwait\0" \
+        "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
+        "loadusbbootenv=fatload usb 0:1 ${loadaddr} uEnv.txt\0" \
+	"mmcautodetect=yes\0" \
+        "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
+                "env import -t $loadaddr $filesize\0" \
+        "importusbbootenv=echo Importing environment from USB (uEnv.txt)...; " \
+                "env import -t $loadaddr $filesize\0" \
+	"mmcargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
+		"rootfstype=${mmcrootfstype} root=${mmcroot}\0 " \
+        "usbargs=setenv bootargs ${jh_clk} console=${console} ${optargs} " \
+                "rootfstype=${mmcrootfstype} root=${usbroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+        "loadusbimage=fatload usb 0:1 ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
+        "loadusbfdt=fatload usb 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+        "usbboot=echo Booting from USB ...; " \
+                "run usbargs; " \
+                "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                        "if run loadusbfdt; then " \
+                                "booti ${loadaddr} - ${fdt_addr}; " \
+                        "else " \
+                                "echo WARN: Cannot load the DT; " \
+                        "fi; " \
+                "else " \
+                        "echo wait for boot; " \
+                "fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+                "echo Checking for: uEnv.txt ...; " \
+                       "if test -e mmc ${bootpart} /uEnv.txt; then " \
+                                "if run loadbootenv; then " \
+                                        "echo Loaded environment from uEnv.txt;" \
+                                        "run importbootenv;" \
+                                "fi;" \
+                                "echo Checking if uenvcmd is set ...;" \
+                                "if test -n ${uenvcmd}; then " \
+                                        "echo Running uenvcmd ...;" \
+                                        "run uenvcmd;" \
+                                "fi;" \
+                        "fi; " \
+                        "if run loadimage; then " \
+                                "run mmcboot; " \
+                        "else run netboot; " \
+                        "fi; " \
+                "booti ${loadaddr} - ${fdt_addr}; fi;"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#ifdef CONFIG_2GB_LPDDR4
+#define PHYS_SDRAM_SIZE                 0x80000000 /* 2GB DDR */
+#else
+#define PHYS_SDRAM_SIZE                 0xc0000000 /* 4GB DDR, temporary workaround */
+#endif
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_MXC_UART
+
+#ifdef CONFIG_CONSOLE_SER0
+#define CONFIG_MXC_UART_BASE            UART4_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc3"
+#endif
+
+#ifdef CONFIG_CONSOLE_SER1
+#define CONFIG_MXC_UART_BASE            UART3_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc2"
+#endif
+
+#ifdef CONFIG_CONSOLE_SER2
+#define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc1"
+#endif
+
+#ifdef CONFIG_CONSOLE_SER3
+#define CONFIG_MXC_UART_BASE            UART1_BASE_ADDR
+#define CONSOLE_DEV                     "ttymxc0"
+#endif
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"u-boot$ "
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_FS_GENERIC
+
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_FSL_QSPI    /* enable the QUADSPI driver */
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define	CONFIG_SPI_FLASH
+#define	CONFIG_SPI_FLASH_STMICRO
+#define	CONFIG_SPI_FLASH_BAR
+#define	CONFIG_SF_DEFAULT_BUS		0
+#define	CONFIG_SF_DEFAULT_CS		0
+#define	CONFIG_SF_DEFAULT_SPEED		40000000
+#define	CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+#define FSL_QSPI_FLASH_SIZE		(SZ_32M)
+#define FSL_QSPI_FLASH_NUM		1
+#endif
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+#endif
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_USBD_HS
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#define CONFIG_CMD_READ
+#endif
+
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_IMXDCSS
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+#if defined(CONFIG_ANDROID_SUPPORT)
+#include "smarcimx8mq_android.h"
+#elif defined (CONFIG_ANDROID_THINGS_SUPPORT)
+#include "smarcimx8mq_androidthings.h"
+#endif
+#endif
diff --git a/include/configs/smarcimx8mq_android.h b/include/configs/smarcimx8mq_android.h
new file mode 100644
index 0000000..f575d92
--- /dev/null
+++ b/include/configs/smarcimx8mq_android.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SMARCIMX8MQ_ANDROID_H
+#define SMARCIMX8MQ_ANDROID_H
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_ANDROID_AB_SUPPORT
+#define CONFIG_AVB_SUPPORT
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYSTEM_RAMDISK_SUPPORT
+#define CONFIG_AVB_FUSE_BANK_SIZEW 0
+#define CONFIG_AVB_FUSE_BANK_START 0
+#define CONFIG_AVB_FUSE_BANK_END 0
+#define CONFIG_FASTBOOT_LOCK
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#ifdef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN           (96 * SZ_1M)
+#endif
+
+#define CONFIG_ANDROID_RECOVERY
+
+#define CONFIG_CMD_BOOTA
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SERIAL_TAG
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x40000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#ifdef CONFIG_FSL_CAAM_KB
+#undef CONFIG_FSL_CAAM_KB
+#endif
+#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED
+
+#endif /* SMARCIMX8MQ_ANDROID_H */
diff --git a/include/configs/smarcimx8mq_androidthings.h b/include/configs/smarcimx8mq_androidthings.h
new file mode 100644
index 0000000..4fee241
--- /dev/null
+++ b/include/configs/smarcimx8mq_androidthings.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SMARCIMX8MQ_ANDROID_THINGS_H
+#define SMARCIMX8MQ_ANDROID_THINGS_H
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_ANDROID_AB_SUPPORT
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYSTEM_RAMDISK_SUPPORT
+#define CONFIG_AVB_FUSE_BANK_SIZEW 4
+#define CONFIG_AVB_FUSE_BANK_START 14
+#define CONFIG_AVB_FUSE_BANK_END 14
+#define CONFIG_FASTBOOT_LOCK
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#ifdef CONFIG_AVB_ATX
+#define UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD 0
+#define UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT 0
+#endif
+
+#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
+
+#ifdef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN           (64 * SZ_1M)
+#endif
+
+#define CONFIG_ANDROID_RECOVERY
+
+/* Use below address to store the bootloader rbindex,
+ * it's 4k offset to CONFIG_SYS_SPL_PTE_RAM_BASE
+ * */
+#if defined(CONFIG_AVB_ATX) && defined(CONFIG_DUAL_BOOTLOADER)
+#define BL_RBINDEX_LOAD_ADDR 0x4157F000
+#endif
+
+#define CONFIG_CMD_BOOTA
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SERIAL_TAG
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED
+
+#define ENTERPRISE_MICRON_1G   0x5c
+#define ENTERPRISE_HYNIX_1G    0x56
+#define ENTERPRISE_MIRCONB_3G  0x40
+#define WIBO_3G                0x00
+#define IMX8M_REF_3G           0x00
+
+#define TEE_LOAD_ADDR_1G 0x7e000000
+#define TEE_LOAD_ADDR_3G 0xfe000000
+
+
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_IMX_TRUSTY_OS)
+#define AVB_RPMB
+#endif
+
+#define KEYSLOT_HWPARTITION_ID   2
+#define KEYSLOT_BLKS             0x1FFF
+
+#ifdef CONFIG_SPL_BUILD
+
+#define CONFIG_SPL_SHA256
+#undef CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_BLK
+#define CONFIG_ENV_IS_NOWHERE
+
+#ifdef AVB_RPMB
+#define BOOTLOADER_RBIDX_OFFSET  0x1E000
+#define BOOTLOADER_RBIDX_START   0x1F000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#else
+/* imx8m won't touch CAAM in non-secure world. */
+#undef CONFIG_FSL_CAAM_KB
+#endif
+
+/* Enlarge the spl max size to 172k */
+#ifdef CONFIG_SPL_MAX_SIZE
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE 176128
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#ifdef CONFIG_DUAL_BOOTLOADER
+#define ANDROID_SPL_SIZE 0x80000
+#endif
+#endif
+
+#endif /* SMARCIMX8MQ_ANDROID_THINGS_H */