Eric Lee / smarc-uboot

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Commit f9c3571f69530ab93377010b8a6d4f137c3d1428

Authored by Ye Li
1 parent 369776edfe
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22851-4 imx8mm/imx8mn: Enable eMMC HS400ES and SD UHS mode on EVK 

Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0
So we enable the HS400ES and UHS configs to enhance eMMC/SD access.

The change also needs to set usdhc clock to 400Mhz and update compatible
string to fsl,imx8mm-usdhc

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit cf83fe7dcfcb14dd633ad43ef387793a863e111a)

Showing 9 changed files with 29 additions and 12 deletions Side-by-side Diff

arch/arm/dts/fsl-imx8mm.dtsi
Diff comments   View file @ f9c3571
... ... @@ -685,7 +685,7 @@
685 685 };
686 686  
687 687 usdhc1: mmc@30b40000 {
688   - compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
  688 + compatible = "fsl,imx8mm-usdhc", "fsl,imx8qm-usdhc";
689 689 reg = <0x0 0x30b40000 0x0 0x10000>;
690 690 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
691 691 clocks = <&clk IMX8MM_CLK_DUMMY>,
... ... @@ -701,7 +701,7 @@
701 701 };
702 702  
703 703 usdhc2: mmc@30b50000 {
704   - compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
  704 + compatible = "fsl,imx8mm-usdhc", "fsl,imx8qm-usdhc";
705 705 reg = <0x0 0x30b50000 0x0 0x10000>;
706 706 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
707 707 clocks = <&clk IMX8MM_CLK_DUMMY>,
... ... @@ -715,7 +715,7 @@
715 715 };
716 716  
717 717 usdhc3: mmc@30b60000 {
718   - compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
  718 + compatible = "fsl,imx8mm-usdhc", "fsl,imx8qm-usdhc";
719 719 reg = <0x0 0x30b60000 0x0 0x10000>;
720 720 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
721 721 clocks = <&clk IMX8MM_CLK_DUMMY>,
arch/arm/dts/fsl-imx8mn.dtsi
Diff comments   View file @ f9c3571
... ... @@ -515,7 +515,7 @@
515 515 };
516 516  
517 517 usdhc1: mmc@30b40000 {
518   - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
  518 + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
519 519 reg = <0x0 0x30b40000 0x0 0x10000>;
520 520 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
521 521 clocks = <&clk IMX8MN_CLK_DUMMY>,
... ... @@ -531,7 +531,7 @@
531 531 };
532 532  
533 533 usdhc2: mmc@30b50000 {
534   - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
  534 + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
535 535 reg = <0x0 0x30b50000 0x0 0x10000>;
536 536 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
537 537 clocks = <&clk IMX8MN_CLK_DUMMY>,
... ... @@ -545,7 +545,7 @@
545 545 };
546 546  
547 547 usdhc3: mmc@30b60000 {
548   - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
  548 + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
549 549 reg = <0x0 0x30b60000 0x0 0x10000>;
550 550 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
551 551 clocks = <&clk IMX8MN_CLK_DUMMY>,
arch/arm/mach-imx/imx8m/clock_imx8mm.c
Diff comments   View file @ f9c3571
... ... @@ -597,22 +597,19 @@
597 597 case 0:
598 598 clock_enable(CCGR_USDHC1, 0);
599 599 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
600   - CLK_ROOT_SOURCE_SEL(1) |
601   - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  600 + CLK_ROOT_SOURCE_SEL(1));
602 601 clock_enable(CCGR_USDHC1, 1);
603 602 return;
604 603 case 1:
605 604 clock_enable(CCGR_USDHC2, 0);
606 605 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
607   - CLK_ROOT_SOURCE_SEL(1) |
608   - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  606 + CLK_ROOT_SOURCE_SEL(1));
609 607 clock_enable(CCGR_USDHC2, 1);
610 608 return;
611 609 case 2:
612 610 clock_enable(CCGR_USDHC3, 0);
613 611 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
614   - CLK_ROOT_SOURCE_SEL(1) |
615   - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  612 + CLK_ROOT_SOURCE_SEL(1));
616 613 clock_enable(CCGR_USDHC3, 1);
617 614 return;
618 615 default:
configs/imx8mm_ddr4_evk_defconfig
Diff comments   View file @ f9c3571
... ... @@ -44,6 +44,8 @@
44 44 CONFIG_DM_I2C=y
45 45 CONFIG_SYS_I2C_MXC=y
46 46 CONFIG_DM_MMC=y
  47 +CONFIG_MMC_IO_VOLTAGE=y
  48 +CONFIG_MMC_UHS_SUPPORT=y
47 49 # CONFIG_DM_PMIC=y
48 50 CONFIG_EFI_PARTITION=y
49 51 CONFIG_DM_ETH=y
configs/imx8mm_ddr4_evk_nand_defconfig
Diff comments   View file @ f9c3571
... ... @@ -42,6 +42,8 @@
42 42 CONFIG_DM_I2C=y
43 43 CONFIG_SYS_I2C_MXC=y
44 44 CONFIG_DM_MMC=y
  45 +CONFIG_MMC_IO_VOLTAGE=y
  46 +CONFIG_MMC_UHS_SUPPORT=y
45 47 # CONFIG_DM_PMIC=y
46 48 CONFIG_EFI_PARTITION=y
47 49 CONFIG_DM_ETH=y
configs/imx8mm_evk_defconfig
Diff comments   View file @ f9c3571
... ... @@ -45,6 +45,10 @@
45 45 CONFIG_DM_I2C=y
46 46 CONFIG_SYS_I2C_MXC=y
47 47 CONFIG_DM_MMC=y
  48 +CONFIG_MMC_IO_VOLTAGE=y
  49 +CONFIG_MMC_UHS_SUPPORT=y
  50 +CONFIG_MMC_HS400_SUPPORT=y
  51 +CONFIG_MMC_HS400_ES_SUPPORT=y
48 52 # CONFIG_DM_PMIC=y
49 53 CONFIG_EFI_PARTITION=y
50 54 CONFIG_DM_SPI_FLASH=y
configs/imx8mm_evk_fspi_defconfig
Diff comments   View file @ f9c3571
... ... @@ -45,6 +45,10 @@
45 45 CONFIG_DM_I2C=y
46 46 CONFIG_SYS_I2C_MXC=y
47 47 CONFIG_DM_MMC=y
  48 +CONFIG_MMC_IO_VOLTAGE=y
  49 +CONFIG_MMC_UHS_SUPPORT=y
  50 +CONFIG_MMC_HS400_SUPPORT=y
  51 +CONFIG_MMC_HS400_ES_SUPPORT=y
48 52 # CONFIG_DM_PMIC=y
49 53 CONFIG_EFI_PARTITION=y
50 54 CONFIG_DM_SPI_FLASH=y
configs/imx8mn_ddr4_evk_defconfig
Diff comments   View file @ f9c3571
... ... @@ -45,6 +45,10 @@
45 45 CONFIG_DM_I2C=y
46 46 CONFIG_SYS_I2C_MXC=y
47 47 CONFIG_DM_MMC=y
  48 +CONFIG_MMC_IO_VOLTAGE=y
  49 +CONFIG_MMC_UHS_SUPPORT=y
  50 +CONFIG_MMC_HS400_SUPPORT=y
  51 +CONFIG_MMC_HS400_ES_SUPPORT=y
48 52 # CONFIG_DM_PMIC=y
49 53 CONFIG_EFI_PARTITION=y
50 54 CONFIG_DM_SPI_FLASH=y
configs/imx8mn_ddr4_evk_nom_defconfig
Diff comments   View file @ f9c3571
... ... @@ -44,6 +44,10 @@
44 44 CONFIG_DM_I2C=y
45 45 CONFIG_SYS_I2C_MXC=y
46 46 CONFIG_DM_MMC=y
  47 +CONFIG_MMC_IO_VOLTAGE=y
  48 +CONFIG_MMC_UHS_SUPPORT=y
  49 +CONFIG_MMC_HS400_SUPPORT=y
  50 +CONFIG_MMC_HS400_ES_SUPPORT=y
47 51 # CONFIG_DM_PMIC=y
48 52 CONFIG_EFI_PARTITION=y
49 53 CONFIG_DM_SPI_FLASH=y