09 Feb, 2017
2 commits
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Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
08 Feb, 2017
1 commit
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.Signed-off-by: Simon Glass
29 Jan, 2017
2 commits
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I missed to update them when DT files were resynced with Linux.
Signed-off-by: Masahiro Yamada
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Clock Driver
This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.SDRAM MC driver
The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing.
Reviewed-by: Simon Glass
10 Jan, 2017
1 commit
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Add basic clock driver support for zynqmp which
sets the required clock for GEM controllerSigned-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
Reviewed-by: Simon Glass
26 Nov, 2016
1 commit
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Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).Signed-off-by: Simon Glass
31 Oct, 2016
4 commits
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This function is called from outside the driver. It should be placed into
common SoC code. Move it.Signed-off-by: Simon Glass
Reviewed-by: Kever Yang -
This function is called from outside the driver. It should be placed into
common SoC code. Move it.Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.Signed-off-by: Simon Glass
Reviewed-by: Kever Yang -
This function is called from outside the driver. It should be placed into
common SoC code. Move it.Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.Signed-off-by: Simon Glass
Reviewed-by: Kever Yang -
clk_rk3399 is driver name, not device name
Signed-off-by: Jacob Chen
Acked-by: Simon Glass
29 Oct, 2016
3 commits
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For the peripheral clock, provide the clock ops for the clock
provider, such as spi0_clk. The .of_xlate is to get the clk->id,
the .enable is to enable the spi0 peripheral clock, the .get_rate
is to get the clock frequency.The driver for periph32ck node is responsible for recursively
binding its children as clk devices, not provide the clock ops.So do the generated clock and system clock.
Signed-off-by: Wenyou Yang
Acked-by: Stephen Warren -
In order to make clk->dev available in ops->of_xlate() to get the
clock ID from the 'reg' property of the clock node, assign the
clk->dev before calling ops->of_xlate().Signed-off-by: Wenyou Yang
Acked-by: Stephen Warren
Acked-by: Simon Glass -
The at91-pmc and at91-sckc aren't the clock providers, change their
class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't
need to bind the child nodes explicitly, the .post_bind callback
of simple_bus uclass will do it for them.Signed-off-by: Wenyou Yang
Acked-by: Stephen Warren
Reviewed-by: Simon Glass
18 Oct, 2016
1 commit
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The initial design of the UniPhier clk driver for U-Boot was not
very nice. Here is a re-work to sync it with Linux's clk and reset
drivers, maximizing the code reuse from Linux's clk data.Signed-off-by: Masahiro Yamada
14 Oct, 2016
1 commit
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These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.This applies the following upstream commits by
Thierry Reding :604e61e fdt: Add functions to retrieve strings
8702bd1 fdt: Add a function to get the index of a string
2218387 fdt: Add a function to count stringsSigned-off-by: Simon Glass
28 Sep, 2016
1 commit
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Implement a clock uclass driver for the Tegra CAR. This allows clients to
use standard clock APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses the existing custom Tegra-
specific clock APIs to avoid coupling the series with significant
refactoring of the existing Tegra clock/clock code. The driver currently
only supports peripheral clocks, and avoids support for other clocks such
as PLLs and external clocks. This should be sufficient to convert over all
Tegra peripheral drivers, and avoids a complex implementation which calls
different Tegra-specific clock APIs based on the type of clock being
manipulated.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
23 Sep, 2016
4 commits
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To sync the DT binding with Linux, the register base must be taken
from the parent syscon node.Signed-off-by: Masahiro Yamada
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Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c)
to the core support file (clk-uniphier-core.c) because I do not want
to repeat the driver boilerplate when I add more clock data.Signed-off-by: Masahiro Yamada
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Clarify these clock data are constant.
Signed-off-by: Masahiro Yamada
22 Sep, 2016
2 commits
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This patch add clk_get_rate for PWM device.
Signed-off-by: Kever Yang
Acked-by: Simon Glass -
pmucru is a module like cru which is a clock controller manage some PLL
and module clocks.Signed-off-by: Kever Yang
Acked-by: Simon Glass
21 Sep, 2016
1 commit
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Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.Signed-off-by: Paul Burton
Reviewed-by: Simon Glass
16 Aug, 2016
3 commits
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The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.Signed-off-by: Wenyou Yang
Reviewed-by: Simon Glass -
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.Signed-off-by: Stephen Warren
Reviewed-by: Simon Glass
Signed-off-by: Tom Warren
06 Aug, 2016
4 commits
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The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.Signed-off-by: Heiko Stuebner
Acked-by: Simon Glass -
MMC core will use 400KHz for card initialize first and then switch to
higher frequency like 50MHz, we need to support both 400KHz and about
50MHz for dwmmc controller.Signed-off-by: Kever Yang
Acked-by: Simon Glass -
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.Suggested-by: Simon Glass
Signed-off-by: Heiko Stuebner
Acked-by: Simon Glass
Updated for rk3399:
Signed-off-by: Simon Glass -
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driverSigned-off-by: Kever Yang
Acked-by: Simon Glass
26 Jul, 2016
3 commits
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The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.Fix this by calling rockchip_get_clk() instead.
Fixes: 135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin -
According to the TRM the minimum FREF frequency is 269kHz not MHz.
Adapt the constant accordingly.Signed-off-by: Heiko Stuebner
Acked-by: Simon Glass -
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.Signed-off-by: Heiko Stuebner
Acked-by: Simon Glass
23 Jul, 2016
1 commit
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This does not have much impact on behavior, but makes code look more
more like Linux. The use of devm_ioremap() often helps to delete
.remove callbacks entirely.Signed-off-by: Masahiro Yamada
22 Jul, 2016
1 commit
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Simple version of clk_get_by_index() added by:
"dm: clk: Add a simple version of clk_get_by_index()"
(sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44)
is only working for #clock-cells= but not for
any other values. Fixed clocks is using #clock-cells=
which requires full implementation.Remove simplified versions of clk_get_by_index() and use full version.
Also remove empty clk_get_by_name() which is failing when it is called
which is useless.Signed-off-by: Michal Simek
Acked-by: Stephen Warren
15 Jul, 2016
3 commits
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Add support for of-platdata with rk3288. This requires decoding the
of-platdata struct and setting up the devices from that. Also the driver
needs to be renamed to match the string that of-platdata will search for.Signed-off-by: Simon Glass
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It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Also add an error check on grf since if
that fails then we should not use it.Signed-off-by: Simon Glass
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Add support for this feature in the core clock code.
Signed-off-by: Simon Glass
25 Jun, 2016
1 commit
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clk->id is unsigned, so it can't be < 0. Remove the check for that.
FWIW, this issue was introduced when the clock API converted e.g.
clk_get_rate()'s clock ID parameter from an int to an unsigned long
(with a struct clk), without removing this check.Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style")
Reported-by: Coverity Scan
Signed-off-by: Stephen Warren
Acked-by: Simon Glass