05 Dec, 2019
1 commit
24 Jan, 2018
1 commit
14 Jan, 2018
1 commit
07 Sep, 2017
1 commit
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…er softare reboot the first time. 40%
RTC timer is default disabled after power off and bootup again. it will be
enabled in kernel rtc driver init. But rtc time is shorter than system clock,
so rtc time cannot update to system clock in rtc_hctosys(), and the sysfs
file /sys/class/rtc/rtc0/hctosys cat result is 0. Android AlarmManagerService
cannot work normally when hctosys is 0.
Enable RTC in u-boot so the time in RTC timer is longer than system clock.Change-Id: Ie8b1c1b36e5ab48031efe44dd06468ac35ca3d3b
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
25 Jul, 2017
1 commit
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On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing.
And due to MMDC limitation, the script we get from IC team is only doing
CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might
cause CS0 can NOT be accessed any longer.Because of this HW issue, we found the high 512MB memory needs more time to
be stable. Since the u-boot relocates itself to highest address after booting,
so this will cause issue.
To work around it, we just limit the u-boot running at low 512MB memory.Signed-off-by: Ye Li
(cherry picked from commit 5fc93379dc3576ee9dc00f108bc18d8d6059d9c3)
19 Jul, 2017
1 commit
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we set gpt image in the last lba for sd boot.
complete the gpt header, gpt entry and protective MBR according
the last lba gpt rule.Change-Id: Icc356a66f82ad359c0243245ab9fdfaea3bccd4f
Signed-off-by: zhang sanshan
12 Jul, 2017
1 commit
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Currently mx6qpsabresd board file only add PHY AR8031 gpio reset
in non-DM driver, then net DM driver PHY cannot work after stress
reboot test. So also add gpio reset for DM driver.RGMII and PHY work at VDDIO 1.8V has better timing and to align
the IO voltage with kernel, also set the IO voltage to 1.8V.Since i.MX6QP tx_clk can loop from SOC internal, no need to set
PHY output 125Mhz clock that can save power.Signed-off-by: Fugang Duan
Reviewed-by: Ye Li
11 Jul, 2017
1 commit
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…e when booting from NAND
uboot can't get the correct misc info.
nand_info[0] is the info of mtd in v2016 or more older version.
nand_info[0] hold the pointer of mtd info in v2017.Change-Id: I6b336efeafeed1e0f4e3224f738e72b83f1e09df
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
10 Jul, 2017
6 commits
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NAND macro has been changed to CONFIG_NAND_BOOT in uboot2017.
Conflicts:
include/configs/pico-imx6dl.h
include/configs/pico-imx6dl_android_things.hChange-Id: I61dd03c0eed8a65100212607447a41bde431cc04
Signed-off-by: zhang sanshan -
…s no valid gpt partition
add command "fastboot 0"
Change-Id: Ibad6dcab5213d815ac968034aeef5ff5a0be3b1b
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com> -
* add board support for android and android things.
mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
it will be included by android and android things.
defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
it's a common code.
* add invalidate_dcache_range in fixed order.
It will have salt invalid issue if we do not add it in order
* add display for pico-7d.Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: zhang sanshan -
* Add CONFIG_SYSTEM_RAMDISK_SUPPORT to support system's ramdisk
* Normal boot: cmdline to bypass ramdisk in boot.img,
but use Recovery boot: Use the ramdisk in boot.img
* commandline is larger than 512, system can't bootup sometime for commandline issue.
* support fastboot getvar.
* Support "fastboot erase" command for emmc device.
TODO: uboot community have api to operate flash, we can unify this part
* support "fastboot flash" even on damaged gptChange-Id: I080c25d6569d6cab56ff025601cd3b8df21cf3dd
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Fix issue for API changed from v2017.
porting below patch from v2016.
commit 44834fd12f60a090e3d10ab6f84a75460894d49dChange-Id: Ifaf0b86dd29648f9150646f00f54502676df9013
Signed-off-by: zhang sanshan -
boot_addr_start for booti should be the addr of Image rather than
boot.img, so need read Image into hdr->kernel_addr.
change the offset for bootloader.
booti do not call android_image_get_kernel to init android env.
booti can't load boot.img, so it can't init android env.
init android env through android_image_get_kernel.Change-Id: Ifb990ee9c5710ce7bd5fa9a0d4221dcb0e52d341
Signed-off-by: sanshan zhang
21 Jun, 2017
5 commits
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Add configure for bcb & bootctr & lock_unlock for android.
change CONFIG_SYS_BOOT_NAND to CONFIG_NAND_BOOT
correct macro ANDROID_FASTBOOT_NAND_PARTS.Change-Id: Iec2190ee940260d770de904889d8d352572a80b5
Signed-off-by: zhang sanshan -
Fix compile error when enable CONFIG_NAND_BOOT.
Fix data abort issue in uboot.Change-Id: If41a7fafa40a2c851882c723a201ac5cdf31284f
Signed-off-by: zhang sanshan -
Fix compile error for api change.
Porting below patches from v2015.o4:
MA-7875 Enable CAAM for i.MX6
MA-7875-1 Support fastboot lock&unlock in u-boot
MA-7875-2 Support fastboot lock/unlock in i.MX6 platform
MA-7875-3 Support fastboot lock/unlock in i.MX6UL
MA-8425 fastboot: return OKAY in fastboot erase
MA-8418 fix return value check for get_device_and_partition
MA-8622 - [brillo] fix uboot compile warnings and code style warningsChange-Id: I2370c3e5851cc1f92aaa93c200e6c079f7929af2
Signed-off-by: zhang sanshan -
* Add API to read\write MISC partition.
* get the boot mode from BCB command when boot up.
* get the boot up tactics from bootctrl.Change-Id: Icbba6340e10983dddc1b04804ecc012a3a3c57d0
Signed-off-by: zhang sanshan -
Request gpio before use it, otherwise it will fail to
drive the gpio when gpio_direction_output.Signed-off-by: Peng Fan
Reviewed-by: Ye Li
20 Jun, 2017
5 commits
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Fix the SW2MODE setting problem in power_init_board, which causes issue when wakeup source
is set in kernel for LPSR.Signed-off-by: Ye Li
Reviewed-by: Bai Ping
(cherry picked from commit 35e62eb779ffcc5af32a6fff615549e536bf6cf4) -
without this patch, the QoS setting will be lost after exit LPSR mode.
The patch moves the QoS setting into DDR setting group (in plugin mode), thus
when exit LPSR mode, QoS setting will be restored as well as DDR setting.Signed-off-by: Robby Cai
(cherry picked from commit 0b217456375bace3fbe9a72c7e92a46dc1907277)
(cherry picked from commit 75790929c674eea2f867b86a7734127d4cd45dfc) -
Add back the defconfig to boot M4 in single mode, because some customers
are using the defconfig during development.Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 8d4daa7703af842a56e9ea7aefe7f3d3a36580b8) -
The u-boot limits the needed sections in .bin by set -j parameter
in objcopy. Need to add the firmware_image section for M4 image.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 709839a52af39f1b4640ae3c72475fc01b1b37d5) -
The latest M4 image uses the version 0x41 not 0x40, have to update
it when checking M4 image. Otherwise M4 image won't be loaded.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 4f421455c850226b9acec9a43b3997995929872e)
12 Jun, 2017
2 commits
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To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since
the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is
201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources
from APLL PFDs are higher than this max rate.The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must
change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12),
with settings:PFD0 FRAC: 32
APLL MULT: 22
APLL NUM: 2
APLL DENOM: 5Signed-off-by: Ye Li
Tested-by: Fancy Fang
(cherry picked from commit 91be2789a93288cc087cd9e8db522c8308ef007c)
(cherry picked from commit 40fd4ea8d86142a7182d13a99db4f2b4d1b55d35) -
The OTG ID pin mux setting is missed in DTS, so the OTG can't work
as host mode.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit b23324508acf2fcda3531bce17055548758c49f8)
24 May, 2017
2 commits
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The reset_sata should reset the sata device info and free the probe_ent
memory. Otherwise, it will cause memory leak if we init the sata again.Signed-off-by: Ye Li
(cherry picked from commit 39c9261fd057b0fa98f9dfdee7d368aa029ff736) -
When sata stop is executed, the sata_curr_device is not reset to -1, so
any following sata commands will not initialize the sata again and cause
problem.Additional, in sata init implementation, the sata_curr_device should be updated,
otherwise sata will be initialized again when doing other sata commands like
read/write/info/part/device.Signed-off-by: Ye Li
(cherry picked from commit e2a66807f3573e8344dcd285dcb7d53f0e5fcf8e)
22 May, 2017
2 commits
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Current setup_spi is in board_early_init_f which is too early, so gpio_request
can't reserve the gpio successfully. Move it to board_init.Signed-off-by: Ye Li
(cherry picked from commit 7c1b220f77313d9df84dbaf0da6ac820e85cba9a) -
To avoid security leak, check the IVT DCD pointer before authenticating
the kernel image. If the pointer is not 0, set back it to 0 and give a warning
like the log below.Authenticate image from DDR location 0x80800000...
Warning, DCD pointer must be 0Signed-off-by: Ye Li
(cherry picked from commit 083daef8d9206d53fb4fa9807f37b8ff5dc319c7)
16 May, 2017
1 commit
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There are two pins used for ENET PHY reset, need to assert them before init the PHY.
Current DM driver does not have such operation, need board level codes to handle.
This patch moves the PHY reset operation into setup_fec, which is common for DM driver
and non-DM driver.Signed-off-by: Ye Li
15 May, 2017
2 commits
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This patch enables the I2C force idle bus for all i.MX6 and i.MX7 boards to avoid
i2c bus problem during reboot. To use it, we must add some i2c properties in DTB file
and the GPIO pinctrl for i2c.For mx6qsabreauto, mx6slevk, mx6sxsabresd and mx6sxscm, these boards call the
setup_i2c. To remove conflict, change to use "setup_i2c" only for non-DM i2c driver.Signed-off-by: Ye Li
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Needs to request the GPIO pin before assigning to GPIO to SPI driver
which will directly setting it to output without request it.Signed-off-by: Ye Li
12 May, 2017
2 commits
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i.MX6UL/ULL evk board net get the wrong MAC address from fuse, exp,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.Signed-off-by: Fugang Duan
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For eMMC, should using "non-removable" property, not "no-removable",
this cause USDHC driver has problem in get_cd, then switching to eMMC will
always show no card present.Signed-off-by: Ye Li
11 May, 2017
5 commits
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Using u-boot-2017.05 on i.MX6UL we ran into following problem:
Initially U-Boot could be started normally.
If we added one random command in configuration, the newly generated
image hung at startup (last output was DRAM: 256 MiB).We tracked this down to a data abort within relocation (relocated_code).
relocated_code in arch/arm/lib/relocate.S copies 8 bytes per loop
iteration until the source pointer is equal to __image_copy_end.
In a good case __image_copy_end was aligned to 8 bytes, so the loop
stopped as suggested, but in an errornous case __image_copy_end was
not aligned to 8 bytes, so the loop ran out of bounds and caused a
data abort exception.This patches solves the issue by aligning __image_copy_end to 8 byte
using the linker script related to arm.From Community: http://patchwork.ozlabs.org/patch/760592/
Signed-off-by: Peng Fan
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Fix coverity:392391 392382 392385 Unsigned compared against 0
Signed-off-by: Peng Fan
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Add return value check
Coverity 392391
Signed-off-by: Peng Fan
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The device managed API actually not free the memory, so need
to use devm_kfree to free the memory to avoid leakage.Coverity: 392384 resource leak
Signed-off-by: Peng Fan
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There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit
is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
So these operations will fail.
The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
after using DDR mode QSPI boot on 6UL/ULL EVK boards.Signed-off-by: Ye Li
