01 May, 2017
1 commit
22 Apr, 2017
1 commit
06 Mar, 2017
1 commit
16 Sep, 2016
3 commits
-
Add fastboot and recovery mode support for mx6qarm
Signed-off-by: Adrian Alonso
(Cherry picked from commit 505e899ce582118da28ca1f4487ce7f179225bd7) -
Add Android support for mx6qarm2 lpddr2 pop target
Signed-off-by: Adrian Alonso
(Cherry picked from commit 6356f2b420f3571493755f6b3a307a66a539b60c) -
Adjust ahb/axi clock root podf dividers to be divided by 1
to allow ahb/axi clock root to be 24Mhz when sourced
from osc_clk.Signed-off-by: Adrian Alonso
(Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)
30 Aug, 2016
2 commits
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VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board,
so software didn't need to change their voltage output anymore. Otherwise,
VGEN3 will be wrongly updated from 1.8v to 2.8v.Signed-off-by: Robin Gong
(cherry picked from commit 6f7f185664a401f03f6ce6c81b996c1f27fdbe73) -
On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need
to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table:'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111Signed-off-by: Bai Ping
(cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be)
25 Aug, 2016
1 commit
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Per to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:'000' - set REFTOP_VBGADJ[2:0] to 3b'110
'110' - set REFTOP_VBGADJ[2:0] to 3b'000
'001' - set REFTOP_VBGADJ[2:0] to 3b'001
'010' - set REFTOP_VBGADJ[2:0] to 3b'010
'011' - set REFTOP_VBGADJ[2:0] to 3b'011
'100' - set REFTOP_VBGADJ[2:0] to 3b'100
'101' - set REFTOP_VBGADJ[2:0] to 3b'101
'111' - set REFTOP_VBGADJ[2:0] to 3b'111Signed-off-by: Bai Ping
23 Aug, 2016
1 commit
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Update the LPDDR2 script to 1.2 rev with delay line settings changed.
File:
IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc
https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspxChanges:
Update Delay Line Settings based on the delay line calibration results of more boards.
MMDC_MPRDDLCTL = 0x40403439
MMDC_MPWRDLCTL = 0X4040342DTest:
One 9x9 EVK board pass stress memtester.Signed-off-by: Ye Li
12 Aug, 2016
1 commit
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Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script
for the board to version 1.0.DDR script:
IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.incChanges:
Initial versionTest:
Passed memtester overnight test on 1 board.Signed-off-by: Ye Li
29 Jul, 2016
2 commits
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add splash screen feature for epdc.
it's tested on imx6ull arm2 board.Signed-off-by: Robby Cai
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We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.Signed-off-by: Ye Li
26 Jul, 2016
1 commit
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Add build targets for eMMC, NAND and QSPI NOR.
Signed-off-by: Ye Li
22 Jul, 2016
1 commit
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For i.MX6, the mux width is 4, not 3. So enlarge the width.
Signed-off-by: Peng Fan
19 Jul, 2016
1 commit
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Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar
board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok
to work.The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when
it is needed.The DDR3 script is using version 1.2:
File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc
Test: 3 boards passed memtester.
Build target:
mx6ull_14x14_evk_defconfig
Signed-off-by: Ye Li
15 Jul, 2016
1 commit
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Need to gate ENET clock when switching to a new clock parent, because
the mux is not glitchless.Signed-off-by: Ye.Li
01 Jul, 2016
1 commit
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When dfu_fill_entity fail, need to free dfu to avoid memory leak.
Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"Signed-off-by: Peng Fan
Cc: "Łukasz Majewski"
Cc: Marek Vasut
(cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)
08 Jun, 2016
2 commits
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Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0
bit[6:4]) setting to 2b'110.Signed-off-by: Bai Ping
-
File:
IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.incChanges:
Change MMDC_MDMISC.WALAT to 1
setmem /32 0x021B0018 = 0x00211740Test:
Passed memtester on two mx6ull ddr3 arm2 boardsSigned-off-by: Ye Li
06 Jun, 2016
3 commits
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If the usb controller is not running, no need to shutdown it,
otherwise `usb stop` complains about:
"EHCI failed to shut down host controller".To i.MX7D SDB, there are two usb ports, one Host, one OTG.
If we only plug one udisk to the Host port and then `usb start`,
the OTG controller for OTG port does not run actually. Then,
if `usb stop`, the OTG controller for OTG port will also be
shutdown, but it is not running.This patch adds a check that only shutdown the running controller.
Signed-off-by: Peng Fan
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For Some USB mass storage devices, such as:
"
- Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x0930 Product 0x6545 Version 1.16
"
When `usb read 0x80000000 0 0x2000`, we met
"EHCI timed out on TD - token=0x80008d80".The devices does not support scsi VPD page, we are not able
to get the maximum transfer length for READ(10)/WRITE(10).So we limit this to 256 blocks as READ(6).
Signed-off-by: Peng Fan
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LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.Signed-off-by: Ye Li
(cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
03 Jun, 2016
1 commit
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Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word'
is not correct when program bank 8, since ocotp controller actully
use word index.For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67.
But actully it should be (7 << 3 | 7) ---> 63.
So fix it.Signed-off-by: Peng Fan
31 May, 2016
1 commit
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Should have "&" to access the register address, otherwise uboot will hang.
Signed-off-by: Ye Li
24 May, 2016
1 commit
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Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's
slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2
board, disable PMIC and ldo bypass check.Signed-off-by: Haibo Chen
23 May, 2016
2 commits
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A space should be added after ${smp}. If not,
bootargs is wrong, when CONFIG_SYS_NOSMP defined.Signed-off-by: Peng Fan
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add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when
NAND enabled due to pin conflict.Signed-off-by: Han Xu
(cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
16 May, 2016
3 commits
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SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
using these pins.Signed-off-by: Peng Fan
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Add revC board support.
Signed-off-by: Peng Fan
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In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
While kernel uses the clock from internal PLL by setting GPR5 bit 9.
When doing warm reset in kernel, the GPR regigster is not reset, so
the clock source still is the PLL. This causes ENET in u-boot can't work.In this patch, we change the u-boot to use internal PLL to align with
kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.Signed-off-by: Ye Li
11 May, 2016
1 commit
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To align with i.MX6UL, add the chip package size info to the i.MX6ULL ARM2 board
build target and loading dtb file name. So that mfgtool and yocto can follow i.MX6UL
naming rule to process i.MX6ULL.Signed-off-by: Ye Li
10 May, 2016
1 commit
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Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html
Signed-off-by: Peng Fan
09 May, 2016
5 commits
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Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL)
to avoid using wrong code path.Signed-off-by: Peng Fan
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The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.Reported-by: Bai Ping
Signed-off-by: Peng Fan -
On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.For LPSR mode, ddr resume flow is same as retention mode,
just adjust it accordingly.Signed-off-by: Anson Huang
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i.MX7D TO1.2 removes the DDR PADs retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.Signed-off-by: Anson Huang
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i.MX7D VDD_ARM/SOC standby voltage should be 0.95V,
adding 25mV margin, so set it to 0.975V;Signed-off-by: Anson Huang
07 May, 2016
1 commit
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This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan
06 May, 2016
1 commit
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This patch is porting from linux:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768"
We may meet the bitflips in reading an erased page(contains all 0xFF),
this may causes the UBIFS corrupt, please see the log from Elie:-----------------------------------------------------------------
[ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
...
[ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
[ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
[ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
-----------------------------------------------------------------This patch does a check for the uncorrectable failure in the following steps:
[0] set the threshold.
The threshold is set based on the truth:
"A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
do the ECC."For the sake of safe, we will set the threshold with half the gf_len, and
do not make it bigger the ECC strength.[1] count the bitflips of the current ECC chunk, assume it is N.
[2] if the (N