01 May, 2017

1 commit


22 Apr, 2017

1 commit


06 Mar, 2017

1 commit


16 Sep, 2016

3 commits


30 Aug, 2016

2 commits

  • VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board,
    so software didn't need to change their voltage output anymore. Otherwise,
    VGEN3 will be wrongly updated from 1.8v to 2.8v.

    Signed-off-by: Robin Gong
    (cherry picked from commit 6f7f185664a401f03f6ce6c81b996c1f27fdbe73)

    Robin Gong
     
  • On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need
    to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table:

    '000" - set REFTOP_VBGADJ[2:0] to 3'b000
    '001" - set REFTOP_VBGADJ[2:0] to 3'b001
    '010" - set REFTOP_VBGADJ[2:0] to 3'b010
    '011" - set REFTOP_VBGADJ[2:0] to 3'b011
    '100" - set REFTOP_VBGADJ[2:0] to 3'b100
    '101" - set REFTOP_VBGADJ[2:0] to 3'b101
    '110" - set REFTOP_VBGADJ[2:0] to 3'b110
    '111" - set REFTOP_VBGADJ[2:0] to 3'b111

    Signed-off-by: Bai Ping
    (cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be)

    Bai Ping
     

25 Aug, 2016

1 commit

  • Per to design team, we need to set REFTOP_VBGADJ
    in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
    actually table is as below:

    '000' - set REFTOP_VBGADJ[2:0] to 3b'110
    '110' - set REFTOP_VBGADJ[2:0] to 3b'000
    '001' - set REFTOP_VBGADJ[2:0] to 3b'001
    '010' - set REFTOP_VBGADJ[2:0] to 3b'010
    '011' - set REFTOP_VBGADJ[2:0] to 3b'011
    '100' - set REFTOP_VBGADJ[2:0] to 3b'100
    '101' - set REFTOP_VBGADJ[2:0] to 3b'101
    '111' - set REFTOP_VBGADJ[2:0] to 3b'111

    Signed-off-by: Bai Ping

    Bai Ping
     

23 Aug, 2016

1 commit

  • Update the LPDDR2 script to 1.2 rev with delay line settings changed.

    File:
    IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc
    https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx

    Changes:
    Update Delay Line Settings based on the delay line calibration results of more boards.
    MMDC_MPRDDLCTL = 0x40403439
    MMDC_MPWRDLCTL = 0X4040342D

    Test:
    One 9x9 EVK board pass stress memtester.

    Signed-off-by: Ye Li

    Ye Li
     

12 Aug, 2016

1 commit

  • Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script
    for the board to version 1.0.

    DDR script:
    IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.inc

    Changes:
    Initial version

    Test:
    Passed memtester overnight test on 1 board.

    Signed-off-by: Ye Li

    Ye Li
     

29 Jul, 2016

2 commits

  • add splash screen feature for epdc.
    it's tested on imx6ull arm2 board.

    Signed-off-by: Robby Cai

    Robby Cai
     
  • We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
    ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
    this changing, SATA read/write can't work after it. And we have to re-init SATA.

    The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.

    This patch is an work around that moves the ENET clock setting
    (enable_fec_anatop_clock) from ethernet init to board_init which is prior
    than SATA initialization. So there is no PLL6 change after SATA init.

    Signed-off-by: Ye Li

    Ye Li
     

26 Jul, 2016

1 commit


22 Jul, 2016

1 commit


19 Jul, 2016

1 commit

  • Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar
    board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok
    to work.

    The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when
    it is needed.

    The DDR3 script is using version 1.2:

    File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc

    Test: 3 boards passed memtester.

    Build target:

    mx6ull_14x14_evk_defconfig

    Signed-off-by: Ye Li

    Ye Li
     

15 Jul, 2016

1 commit


01 Jul, 2016

1 commit

  • When dfu_fill_entity fail, need to free dfu to avoid memory leak.

    Reported by Coverity:
    "
    Resource leak (RESOURCE_LEAK)
    leaked_storage: Variable dfu going out of scope leaks the storage
    it points to.
    "

    Signed-off-by: Peng Fan
    Cc: "Łukasz Majewski"
    Cc: Marek Vasut
    (cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)

    Peng Fan
     

08 Jun, 2016

2 commits


06 Jun, 2016

3 commits

  • If the usb controller is not running, no need to shutdown it,
    otherwise `usb stop` complains about:
    "EHCI failed to shut down host controller".

    To i.MX7D SDB, there are two usb ports, one Host, one OTG.
    If we only plug one udisk to the Host port and then `usb start`,
    the OTG controller for OTG port does not run actually. Then,
    if `usb stop`, the OTG controller for OTG port will also be
    shutdown, but it is not running.

    This patch adds a check that only shutdown the running controller.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • For Some USB mass storage devices, such as:
    "
    - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
    - Class: (from Interface) Mass Storage
    - PacketSize: 64 Configurations: 1
    - Vendor: 0x0930 Product 0x6545 Version 1.16
    "
    When `usb read 0x80000000 0 0x2000`, we met
    "EHCI timed out on TD - token=0x80008d80".

    The devices does not support scsi VPD page, we are not able
    to get the maximum transfer length for READ(10)/WRITE(10).

    So we limit this to 256 blocks as READ(6).

    Signed-off-by: Peng Fan

    Peng Fan
     
  • LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
    D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
    is actually 1.2V.

    Signed-off-by: Ye Li
    (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)

    Ye Li
     

03 Jun, 2016

1 commit

  • Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word'
    is not correct when program bank 8, since ocotp controller actully
    use word index.

    For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67.
    But actully it should be (7 << 3 | 7) ---> 63.
    So fix it.

    Signed-off-by: Peng Fan

    Peng Fan
     

31 May, 2016

1 commit


24 May, 2016

1 commit


23 May, 2016

2 commits


16 May, 2016

3 commits

  • SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
    not in IOMUXC, so correct the related registers' offset.

    Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
    them from iomuxc pins.

    Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
    using these pins.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • Add revC board support.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
    While kernel uses the clock from internal PLL by setting GPR5 bit 9.
    When doing warm reset in kernel, the GPR regigster is not reset, so
    the clock source still is the PLL. This causes ENET in u-boot can't work.

    In this patch, we change the u-boot to use internal PLL to align with
    kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.

    Signed-off-by: Ye Li

    Ye Li
     

11 May, 2016

1 commit


10 May, 2016

1 commit

  • Several UART input selects are missing. The fourth input select
    for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
    (at least in Rev. B of the i.MX 7Dual Reference Manual). However,
    when looking at the tables of other input selects, it is very natural
    that there must be an input select for the UART2_TX_DATA_ALT0 pad.
    The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
    it was required to set that particular input select register to get a
    working UART2.

    From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html

    Signed-off-by: Peng Fan

    Stefan Agner
     

09 May, 2016

5 commits


07 May, 2016

1 commit

  • This patch is a porting of
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
    "
    i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
    bitflip number for erased NAND page. So for these two platform, set the
    erase threshold to gf/2 and if bitflip detected, GPMI driver will
    correct the data to all 0xFF.

    Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
    with the one for i.MX6QP.
    "

    In this patch, i.MX6UL is added and threshold changed to use ecc_strength.

    Signed-off-by: Peng Fan

    Peng Fan
     

06 May, 2016

1 commit

  • This patch is porting from linux:
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768

    "
    We may meet the bitflips in reading an erased page(contains all 0xFF),
    this may causes the UBIFS corrupt, please see the log from Elie:

    -----------------------------------------------------------------
    [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
    ...
    [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
    [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
    [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
    -----------------------------------------------------------------

    This patch does a check for the uncorrectable failure in the following steps:

    [0] set the threshold.
    The threshold is set based on the truth:
    "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
    do the ECC."

    For the sake of safe, we will set the threshold with half the gf_len, and
    do not make it bigger the ECC strength.

    [1] count the bitflips of the current ECC chunk, assume it is N.

    [2] if the (N

    Peng Fan