01 Jul, 2022

1 commit

10 Dec, 2021

1 commit

25 Nov, 2021

1 commit

21 Jul, 2021

1 commit

19 Jul, 2021

1 commit

05 Mar, 2021

2 commits

  • * origin/ls_v2020.04:
    arm64: gic-v3-its: Clear the Pending table before enabling LPIs

    BJ DevOps Team
  • The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
    must contain only zeros on initial allocation, and this must be visible
    to the Redistributors, or else the effect is UNPREDICTABLE".

    And as the following statement, we here clear the whole Pending tables
    instead of the first 1KB.
    "An LPI Pending table that contains only zeros, including in the first 1KB,
    indicates that there are no pending LPIs.
    The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
    if the first 1KB of the LPI Pending table and the rest of the table contain
    only zeros, this must indicate that there are no pending LPIs."

    And there isn't any pending LPI under U-Boot, so it's unnecessary to
    loading the contents of the Pending table during the enablement, then set
    the GICR_PENDBASER.PTZ flag.

    Signed-off-by: Hou Zhiqiang
    Tested-by: Vladimir Oltean

    Hou Zhiqiang

01 Mar, 2021

1 commit

27 Feb, 2021

1 commit

23 Feb, 2021

1 commit

21 Feb, 2021

1 commit

  • Users reported LPDDR4 MR12 value is set to 0 during PHY training,
    not the value from FSP timing structure, which cause compliance test failed.
    The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
    but not set in 1D. According to PHY training application node,
    to enable the feature both 1D and 2D need set this field to 1,
    otherwise the training result will be incorrect.
    The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
    MR12 value from message block (FSP structure). So update the LPDDR4
    scripts of all mscale to clear CATrainOpt[0].

    Signed-off-by: Ye Li
    Reviewed-by: Jacky Bai
    (cherry picked from commit 2c98fb859258478e0f8bb8df980a96edff19d359)

    Ye Li

05 Feb, 2021

13 commits

28 Jan, 2021

3 commits

27 Jan, 2021

3 commits

  • * origin/ls_v2020.04:
    net: memac_phy: add a timeout to MDIO operations
    armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bit

    BJ DevOps Team
  • We have encountered circumstances when a board design does not include
    pull-up resistors on the external MDIO buses which are not used. This
    leads to the MDIO data line not being pulled-up, thus the MDIO controller
    will always see the line as busy.

    Without a timeout in the MDIO bus driver, the execution is stuck in an
    infinite loop when any access is initiated on that external bus.

    Add a timeout in the driver so that we are protected in this
    circumstance. This is similar to what is being done in the Linux
    xgmac_mdio driver.

    Signed-off-by: Ioana Ciornei

    Ioana Ciornei
  • Multiple LX2(LX2160A/LX2162A SoC) personality variants
    exists based on CAN-FD and security bit in SVR.

    Currenly SVR_SOC_VER mask only security bit.
    Update SVR_SOC_VER to mask CAN_FD and security bit
    for LX2 products.

    Signed-off-by: Wasim Khan

    Wasim Khan

17 Jan, 2021

3 commits

14 Jan, 2021

3 commits

  • * origin/imx_v2020.04:
    LF-3161-2 mx6ul: bee: Remove XN bit for bee enabled region
    LF-3161-1 arm: imx: Fix speculative instruction prefetch issue

    BJ DevOps Team
  • We will test a program on BEE enabled region, so remove XN bit
    to allow execution when current MMU domain is changed to client.

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan
    (cherry picked from commit e4bd1734bcba2012d4d7dea7598635256f155c96)

    Ye Li
  • Default ARM32 MMU setting in u-boot sets XN bit to entire 4GB space no
    matter which DCACHE option is used, and set domain permission to manager.
    This causes MMU ignores the access check and XN bit, so speculative
    instruction can fetch from entire space.

    This patch sets the DDR, ROM, OCRAM without XN bit, and set domain to client
    to enable the XN and access check. So speculative instruction fetch can only
    happens on these 3 regions to avoid prefetch from peripherals and invalid

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan
    (cherry picked from commit 25d70768c460bad91aa65f367203af41122399cd)

    Ye Li

13 Jan, 2021

4 commits

  • * origin/ls_v2020.04:
    armv8: ls1028a: fix stream id allocation
    configs: ls1088aqds: add COMMON_ENV to fix distroboot
    board: fsl: ls2088ardb: Program GIC LPI configuration table

    BJ DevOps Team
  • When A-050382 errata is enabled, ECAM and EDMA have
    conflicting stream id 40. This patch fixes the same.

    Signed-off-by: Nipun Gupta

    Nipun Gupta
  • Add COMMON_ENV(kernel_addr_r, fdt_addr_r and so on)
    to fix a bug that faild to boot to ubuntu, failed
    log as follows,
    ## Executing script at 80000000
    load - load binary file from a filesystemUsage:
    load [ [ [ [bytes [pos]]]]]
    - Load binary file filename from partition part on device
    type interface instance dev to address addr in memory.
    bytes gives the size to load in bytes.
    If bytes is 0 or omitted, the file is read until the end.
    pos gives the file byte position to start reading from.
    If pos is 0 or omitted, the file is read from the start.
    Bad Linux ARM64 Image magic!
    SCRIPT FAILED: continuing...

    Signed-off-by: Biwen Li

    Biwen Li
  • Program GIC LPI configuration table:

    1. Redistributor PROCBASER configuration table (which is common for all

    2. Redistributor pending table (PENDBASER), for all the available

    3.Reserve DDR memory region used for GIC LPI configuration table.

    Signed-off-by: Nikhil Gupta

    Nikhil Gupta