26 Nov, 2013

1 commit


25 Nov, 2013

25 commits


23 Nov, 2013

14 commits

  • This chip is compatible with the existing driver, except that it uses
    BAR2 instead of BAR1 for the I/O memory region. Using this patch I can
    use the PCIe ethernet interface on the CompuLab Trimslice to boot from
    the network.

    Signed-off-by: Thierry Reding
    Patch: 276477

    Thierry Reding
     
  • Instead of directly calling the low-level invalidate_dcache_range() and
    flush_cache() functions, provide thin wrappers that take into account
    alignment requirements.

    While at it, fix a case where the cache was flushed but should have been
    invalidated, two cases where the buffer data was flushed instead of the
    descriptor and a missing cache invalidation before reading the packet
    data that the NIC just wrote to memory.

    Signed-off-by: Thierry Reding
    Patch: 276474

    Thierry Reding
     
  • Added d-cache support for zynq_gem.c,
    Observed a difference of +0.8 MiB/s when downloading
    a file of size of 3007944Bytes.

    With d-cache OFF:
    ----------------
    Filename 'uImage'.
    Load address: 0x800
    Loading: #################################################################
    #################################################################
    #################################################################
    ##########
    1.3 MiB/s
    done
    Bytes transferred = 3007944 (2de5c8 hex)

    With d-cache ON:
    ---------------
    Filename 'uImage'.
    Load address: 0x800
    Loading: #################################################################
    #################################################################
    #################################################################
    ##########
    2.1 MiB/s
    done
    Bytes transferred = 3007944 (2de5c8 hex)

    Changes on zynq_gem for d-cache support:
    - Tx and Rx buffers are cache-aligned
    - Updated logic for invalidating Rx buffers and flushing Tx buffers.
    - Tx and Rx BD's are allocated from non-cacheable region.
    (When BDs are cached, we don't see a consistent link)
    - Use TX BD status intead of txsr status checks.

    Signed-off-by: Srikanth Thokala
    Signed-off-by: Jagannadha Sutradharudu Teki
    Signed-off-by: Michal Simek

    Srikanth Thokala
     
  • Signed-off-by: David Dueck

    David Dueck
     
  • The current code incorrectly detects gigabit capabilities for some
    100Mbit/s phys. (lan8720a)

    Signed-off-by: David Dueck

    David Dueck
     
  • When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will
    come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that
    gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random
    (and valid) locally administered MAC address that allows the system to
    network boot until a real MAC address can be configured.

    Signed-off-by: Andrew Ruder

    Andrew Ruder
     
  • The e1000 driver expects to always have some kind of non-volatile memory
    attached directly to the ethernet controller chip. This means that I would
    have to add an additional separate flash chip to my custom board just to
    store essentially the MAC address. Since I don't want to do that, this patch
    introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables
    all accesses to the NVM. I have tested the patch with a 82574 controller.

    Signed-off-by: Rojhalat Ibrahim

    Rojhalat Ibrahim
     
  • NetServerEther was not being cleared in the tftp server code, so the
    destination MAC address would be whatever the last destination MAC
    address was.

    Scenario:
    U-Boot:
    dhcp
    tftpsrv
    Host:
    Send device WRQ
    Device:
    Responds with ACK to dhcp server mac address with
    host ip address

    By clearing NetServerEther, we force a lookup of the host MAC address
    to go with the associated host IP.

    Signed-off-by: Andrew Ruder

    Andrew Ruder
     
  • The masks were ignoring the last 4 bits which didn't allow detection differences
    between the ar8031 and ar8035.

    Signed-off-by: Jon Nettleton
    Signed-off-by: Fabio Estevam
    Patch: 288018

    Fabio Estevam
     
  • The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
    So the phy id mask of AR8031 is the same to the phy id mask
    of AR8035. The right mask value is 0x4fffff.

    This patch has been tested on the P1010 and P1023.

    Signed-off-by: Chunhe Lan
    Cc: Joe Hershberger
    Patch: 287748

    Chunhe Lan
     
  • Fix the 32-bit memory access that is not "endianess safe",
    i.e. not giving the desired byte layout for LE cpus:
    tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'.

    Free the stack from rendundant local vars:
    tmpbuf[] and i.

    Use a portable type (u32) for the 32bit tsec register value
    holder: tempval.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • Use cross arch portable u32 instead of uint for the
    tsec registers. Remove the typedefs for the register
    struct definitions in the process. Fix long lines.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • Currently, the buffer descriptor (BD) fields cannot be
    correctly accessed by a little endian processor. This
    patch fixes the issue by making the access of BDs to be
    portable among different cpu architectures.

    Use portable data types for the Rx/Tx buffer descriptor
    fields. Use portable I/O accessors to insure that the
    big endian BDs are correctly accessed by little endian
    cpus too, and to insure proper sync with the H/W.
    Removed the redundant RTXBD "volatile" type, as proper
    synchronization around BD data accesses is provided by
    the I/O accessors now.
    The "sparse" tool was also used to verify the correctness
    of these changes.

    Cc: Scott Wood

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil
     
  • Fix bufPtr and the rxIdx/ txIdx occurrences to
    solve the related checkpatch warnings for the
    coming patches.

    Signed-off-by: Claudiu Manoil

    Claudiu Manoil