11 Mar, 2014

12 commits

  • Signed-off-by: Tom Rini

    Tom Rini
     
  • Tom Rini
     
  • Tom Rini
     
  • Many USB host controller drivers contain almost identical copies of the
    same virtual root hub descriptors. Put these into a common file to avoid
    duplication.

    Note that there were some very minor differences between the descriptors
    in the various files, such as:

    - USB 1.0 vs. USB 1.1
    - Manufacturer/Device ID
    - Max packet size
    - String content

    I assume these aren't relevant.

    Cc: Thomas Lange
    Cc: Shinya Kuribayashi
    Cc: Gary Jennejohn
    Cc: Wolfgang Denk
    Cc: Eric Millbrandt
    Cc: Pierre Aubert
    Cc: Stefan Roese
    Cc: Daniel Hellstrom
    Cc: Denis Peter
    Cc: Rodolfo Giometti
    Cc: Zhang Wei
    Cc: Mateusz Zalega
    Cc: Remy Bohmer
    Cc: Markus Klotzbuecher
    Cc: Minkyu Kang
    Cc: Gary Jennejohn
    Cc: C Nauman
    Cc: David Müller
    Cc: Yoshihiro Shimoda
    Cc: Nobuhiro Iwamatsu
    Cc: Thomas Abraham
    Cc: Tom Rini
    Cc: Andrew Murray
    Cc: Matej Frančeškin
    Cc: Cliff Cai
    Cc: Bryan Wu
    Signed-off-by: Stephen Warren

    Stephen Warren
     
  • These data structures are passed to cache-flushing routines, and hence
    must be conform to both the USB the cache-flusing alignment requirements.
    That means aligning to USB_DMA_MINALIGN. This is important on systems
    where cache lines are >32 bytes.

    Signed-off-by: Stephen Warren

    Stephen Warren
     
  • Section 4.10.2 "Advance Queue" of ehci-specification-for-usb.pdf
    specifies how an EHCI controller loads a new QTD for processing if the
    QH is not already marked as active. It states:

    =====
    If the field Bytes to Transfer is not zero and the T-bit in the Alternate
    Next qTD Pointer is set to zero, then the host controller uses the
    Alternate Next qTD Pointer. Otherwise, the host controller uses the Next
    qTD Pointer. If Next qTD Pointer’s T-bit is set to a one, then the host
    controller exits this state and uses the horizontal pointer to the next
    schedule data structure.
    =====

    Hence, we must ensure that the alternate next QTD pointer's T-bit
    (TERMINATE) is set, so the EHCI controller knows to use the next QTD
    pointer.

    Signed-off-by: Stephen Warren

    Stephen Warren
     
  • Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • include/generated/version_autogenerated.h was not correctly
    generated on the parallel build (with -j option).

    Signed-off-by: Masahiro Yamada
    Reported-by: Andreas Bießmann

    Masahiro Yamada
     
  • .bmp files contain 32-bit integers aligned at offsets of +2, +6,
    et cetera within the bmp_header structure (see include/bmp_layout.h).

    Support for gzip-compressed .bmp files is present in the cfb_console
    display subsystem by uncompressing them prior to use.

    This patch forces the in-memory header to be aligned properly
    for these compressed images by extracting them to a 2-byte
    offset in the memory returned by malloc. Since malloc will always
    return a 4-byte aligned value, this forces the .bmp header
    fields to be naturally aligned on 4-byte addresses.

    Refer to these files for more details:
    doc/README.displaying-bmps

    Signed-off-by: Eric Nelson

    Eric Nelson
     
  • I have observed timeouts on a cubietruck.

    The increase to 40ms is completely arbitrary and Works For Me(tm). I
    couldn't find a good reference for how long you are supposed to wait,
    although googling around it seems like tens of ms rather than single
    digits is more common. I don't think there is any harm in waiting a bit
    longer.

    Signed-off-by: Ian Campbell

    Ian Campbell
     
  • Signed-off-by: Ian Campbell
    Acked-by: Rob Herring

    Ian Campbell
     
  • This allow the platform to register the platform ahci device.

    Signed-off-by: Ian Campbell

    Ian Campbell
     

10 Mar, 2014

7 commits

  • CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
    as 1000000 and idmr.h defines it as (50000000 / 64).

    When compiling these two boards, a warning message is displayed:

    time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
    and should not be defined by platforms" [-Wcpp]

    There are no board maintainers for them so this commit just
    deletes them.

    Signed-off-by: Masahiro Yamada
    Cc: Jason Jin

    Masahiro Yamada
     
  • Add NAND SPL boot support with hardware PMECC.

    Signed-off-by: Bo Shen
    Signed-off-by: Andreas Bießmann

    Bo Shen
     
  • Prepare for nand spl boot support. It supports nand software ECC and
    hardware PMECC.
    This patch is take as reference.

    Signed-off-by: Bo Shen
    Signed-off-by: Andreas Bießmann

    Bo Shen
     
  • Add SPI SPL boot support for sama5d3xek board.

    Signed-off-by: Bo Shen
    Signed-off-by: Andreas Bießmann

    Bo Shen
     
  • Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC.
    Now it supports boot from NAND flash and SD/MMC card.
    Features support:
    - NAND flash
    - SD/MMC card
    - Two USB hosts
    - Ethernet (one GMAC, one EMAC)

    Signed-off-by: Bo Shen
    [reorder boards.cfg]
    Signed-off-by: Andreas Bießmann

    Bo Shen
     
  • It's called _pio_ in the version that was added to git.
    Apparently it got renamed without updating the macros before it was
    applied, c.f.
    http://u-boot.10912.n7.nabble.com/U-Boot-PATCH-3-9-V3-add-a-new-AT91-GPIO-driver-td75922.html

    Signed-off-by: Andreas Henriksson
    Signed-off-by: Andreas Bießmann

    Andreas Henriksson
     
  • Add support for using the Atmel MCI driver on at91sam9263ek.
    This change is modeled after the existing at91sam9260ek support.

    Please note that this hooks up slot1 (MCI1) for SD. Not both.

    Tested with at91bootstrap and u-boot on dataflash in slot 0
    and fat-formatted 8GB SDHC in slot 1 on first revision
    at91sam9263ek (which must use dataflash in slot0 to boot).

    CONFIG_ATMEL_MCI_PORTB not tested.

    Signed-off-by: Andreas Henriksson
    [remove empty line]
    Signed-off-by: Andreas Bießmann

    Andreas Henriksson
     

08 Mar, 2014

14 commits

  • Tom Rini
     
  • Update following DDR related settings for T1040RDB, T1042RDB_PI
    -Correct number of chip selects to two as t1040 supports
    two Chip selects.
    -Update board_specific_parameters udimm structure with settings
    derived via calibration.
    -Update ddr_raw_timing sructure corresponding to DIMM.
    -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
    but on T104xRDB, on setting this , DDR instability is observed.
    Board-level debugging is in progress.

    Verified the updated settings to be working fine with dual-ranked
    Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

    Signed-off-by: Priyanka Jain
    Signed-off-by: York Sun

    Priyanka Jain
     
  • T1040 has internal display interface unit (DIU) for driving video.
    T1040QDS supports video mode via
    -LCD using TI enconder
    -HDMI type interface via HDMI encoder

    Chrontel, CH7301C encoder which is I2C programmable is used as
    HDMI connector on T1040QDS.
    This patch add support to
    -enable Video interface for T1040QDS
    -route qixis multiplexing to enable DIU-HDMI interface on board
    -program DIU pixel clock gerenartor for T1040
    -program HDMI encoder via I2C on board

    Signed-off-by: Priyanka Jain
    Reviewed-by: York Sun

    Priyanka Jain
     
  • T1040 SoC has SCFG (Supplement Configuration) Block which provides
    chip specific configuration and status support. The base address of
    SCFG block in T1040 is 0xfc000.
    SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
    at offset 0x28.

    Add definition of
    -SCFG block
    -SCFG_PIXCLKCR register
    -Bits definition of SCFG_PIXCLK register

    Signed-off-by: Priyanka Jain
    Reviewed-by: York Sun

    Priyanka Jain
     
  • T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
    It works in two mode: standalone mode and PCIe endpoint mode.

    T2080PCIe-RDB Feature Overview
    ------------------------------
    Processor:
    - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
    DDR Memory:
    - Single memory controller capable of supporting DDR3 and DDR3-LP devices
    - 72bit 4GB DDR3-LP SODIMM in slot
    Ethernet interfaces:
    - Two 10M/100M/1G RGMII ports on-board
    - Two 10Gbps SFP+ ports on-board
    - Two 10Gbps Base-T ports on-board
    Accelerator:
    - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
    SerDes 16 lanes configuration:
    - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
    - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
    - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
    - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
    - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
    - SerDes-2 Lane G-H: to SATA1 & SATA2
    IFC/Local Bus:
    - NOR: 128MB 16-bit NOR flash
    - NAND: 512MB 8-bit NAND flash
    - CPLD: for system controlling with programable header on-board
    eSPI:
    - 64MB N25Q512 SPI flash
    USB:
    - Two USB2.0 ports with internal PHY (both Type-A)
    PCIe:
    - One PCIe x4 gold-finger
    - One PCIe x4 connector
    - One PCIe x2 end-point device (C293 Crypto co-processor)
    SATA:
    - Two SATA 2.0 ports on-board
    SDHC:
    - support a TF-card on-board
    I2C:
    - Four I2C controllers.
    UART:
    - Dual 4-pins UART serial ports

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
    Fix EMI2 for t2080qds, which was caused by adding t2081qds.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • This implements stashing of bootstage timing data to FDT and automatic
    timing reporting. To enable define CONFIG_BOOTSTAGE_FDT and
    CONFIG_BOOTSTAGE_REPORT respectively.

    Signed-off-by: Rommel G Custodio
    Reviewed-by: York Sun

    Mela Custodio
     
  • USB spec says that the minimum disconnect threshold should be
    over 525 mV. However, internal USB PHY threshold value is below
    this specified value. Due to this some devices disconnect at
    run-time. Hence, phy settings are tweaked to increased disconnect
    threshold to be above 525mV by using this workaround.

    Signed-off-by: Suresh Gupta
    Reviewed-by: York Sun

    Suresh Gupta
     
  • SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
    and at cold temperatures(A006475), workaround recalibrate the
    PLLs with some SerDes configuration

    Both these errata are only applicable for b4 rev1.
    So, make workaround for these errata conditional,
    depending upon soc version.

    Signed-off-by: Shaveta Leekha
    Reviewed-by: York Sun

    Shaveta Leekha
     
  • Change setting of SerDes2 refclk2 to have the default value as it is
    coming on board that is 156.25MHz, for XFI to work.
    Also change PLL_NUM variable to the one defined in config_mpc85xx.h
    for B4860 and B4420.

    Signed-off-by: Shaveta Leekha
    Reviewed-by: York Sun

    Shaveta Leekha
     
  • B4860 has two PLL per SerDes whereas B4420 has one PLL per SerDes,
    add their defines in arch/powerpc/include/asm/config_mpc85xx.h

    Signed-off-by: Shaveta Leekha
    Reviewed-by: York Sun

    Shaveta Leekha
     
  • On B4860 and B4420, some serdes protocols can be used with LC VCO as
    well as Ring VCO options.

    Addded Alternate options with LC VCO for such protocols.
    For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.

    The alternate option has the same functionality as the original option;
    the only difference being LC VCO rather than Ring VCO.

    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    poonam aggrwal
     
  • 1) SerDes2 Refclks have been set properly to make
    PCIe SATA to work as it work on SerDes refclk of 100MHz
    2) Mask the SerDes's device reset request before changing
    the Refclks for SerDes1 and SerDes2 for PLL locks to
    happen properly, device reset request bit unmasked
    after SerDes refclks configuration

    Signed-off-by: Shaveta Leekha
    Reviewed-by: York Sun

    Shaveta Leekha
     
  • 1) Add new SerDes1 protocols having Aurora in them
    2) Add VSC cross point connections for Aurora to work with
    CPRI and SGMIIs
    3) Configure VSC crossbar switch to connect SerDes1
    lanes to aurora on board, by checking SerDes1 protocols
    4) SerDes1 Refclks have been set properly to make
    Aurora, CPRI and SGMIIs to work together properly

    Signed-off-by: Shaveta Leekha
    Reviewed-by: York Sun

    Shaveta Leekha
     

07 Mar, 2014

7 commits

  • "checkgcc4" is used only for PowerPC.
    Move it to arch/powerpc/config.mk.

    To make sure gcc is new enough before beginning build,
    run "checkgcc4" during "archprepare".

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • "checkthumb" makes sense only for ARM architecture.
    Move it to arch/arm/config.mk.

    To make sure gcc supports THUMB mode before beginning build,
    run "checkthumb" during "archprepare".

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • Before this commit, CONFIG_MPC8260 and CONFIG_8260
    were used mixed-up.

    All boards with mpc8260 cpu defined both of them:
    - CONFIG_MPC8260 was defined in board config headers
    and include/common.h
    - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk

    We do not need to have both of them.
    This commit keeps only CONFIG_MPC8260.

    This commit does:
    - Delete CONFIG_8260 and CONFIG_MPC8260 definition
    in config headers and include/common.h
    - Rename CONFIG_8260 to CONFIG_MPC8260
    in arch/powerpc/cpu/mpc8260/config.mk.
    - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260

    Signed-off-by: Masahiro Yamada
    Cc: Wolfgang Denk

    Masahiro Yamada
     
  • All mips32 boards define CONFIG_MIPS32 in config headers
    except malta boards which define it in boards.cfg.
    We can consolidate them by defining it in
    arch/mips/cpu/mips32/config.mk.

    CONFIG_MIPS64 definition can be moved to
    arch/mips/cpu/mips64/config.mk as well.

    Signed-off-by: Masahiro Yamada
    Cc: Daniel Schwierzeck
    Acked-by: Daniel Schwierzeck

    Masahiro Yamada
     
  • Kbuild brought about many advantages for us but a significant
    performance regression was reported by Simon Glass.

    After some discussions and analysis, it turned out
    its main cause is in $(call cc-option,...).

    Historically, U-Boot parses all config.mk
    (arch/*/config.mk and board/*/config.mk)
    every time descending into subdirectories.
    That means cc-options are evaluated over and over again.

    $(call cc-option,...) is useful but costly.
    So we want to evaluate them only in ./Makefile
    and spl/Makefile and export compiler flags.

    This commit changes the build system as follows:

    - Modify scripts/Makefile.build to not include config.mk
    Instead, add $(PLATFORM_CPPFLAGS) to asflags-y, ccflags-y,
    cppflags-y.

    - Export many variables
    Going forward, Kbuild will not parse config.mk files
    when it descends into subdirectories.
    If we want to set variables in config.mk and use them
    in subdirectories, they must be exported.

    This is the list of variables to get exported:
    PLATFORM_CPPFLAGS
    CPUDIR
    BOARDDIR
    OBJCOPYFLAGS
    LDFLAGS
    LDFLAGS_FINAL
    (used in nand_spl/board/*/*/Makefile)
    CONFIG_STANDALONE_LOAD_ADDR
    (used in examples/standalone/Makefile)
    SYM_PREFIX
    (used in examples/standalone/Makefile)
    RELFLAGS
    (used in examples/standalone/Makefile)

    - Delete CPPFLAGS
    This variable has been replaced with PLATFORM_CPPFLAGS

    - Copy gcclibdir from example/standalone/Makefile
    to arch/sparc/config.mk
    The reference in CONFIG_STANDALONE_LOAD_ADDR must be
    resolved before it is exported.

    Signed-off-by: Masahiro Yamada
    Reported-by: Simon Glass
    Acked-by: Simon Glass
    Tested-by: Simon Glass [on Sandbox]
    Tested-by: Stephen Warren [on Tegra]

    Masahiro Yamada
     
  • We want to change the build system to include config.mk
    only from ./Makefile and spl/Makefile.
    We must prepare for that in this commit.

    $(src) is a moving target and not handy for our purpose.
    We must replace it with a fixed path.

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • Before this commit, USE_PRIVATE_LIBGCC was defined in
    arch-specific config.mk and referenced in
    arch/$(ARCH)/lib/Makefile.

    We are not happy about parsing config.mk again and again.
    We have to keep the same behavior with a different way.

    By adding "CONFIG_" prefix, this macro appears
    in include/autoconf.mk, include/spl-autoconf.mk.
    (And treating USE_PRIVATE_LIBGCC as CONFIG macro
    is reasonable enough.)

    Tegra SoC family defined USE_PRIVATE_LIBGCC as "yes"
    in arch/arm/cpu/arm720t/tegra*/config.mk,
    whereas did not define it in arch/arm/cpu/armv7/tegra*/config.mk.

    It means Tegra enables PRIVATE_LIBGCC only for SPL.
    We can describe the same behavior by adding

    #ifdef CONFIG_SPL_BUILD
    # define CONFIG_USE_PRIVATE_LIBGCC
    #endif

    to include/configs/tegra-common.h.

    Signed-off-by: Masahiro Yamada
    Cc: Tom Warren
    Cc: Simon Glass
    Acked-by: Stephen Warren

    Masahiro Yamada