07 Oct, 2014

5 commits


06 Oct, 2014

35 commits

  • Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
    filesystem type into the environment.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Split the SoCFPGA configuration into SoC-specific part which is
    common for all boards (socfpga_cyclone5_common.h) and a board
    specific part. There is currently only one board, which is the
    generic SoCFPGA board (socfpga_cyclone5.h), but there are more
    to come.

    This is necessary due to various features of the boards, which
    unfortunatelly cannot be autodetected.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Pavel Machek
     
  • Reorganize and cleanup the configuration file for SoCFPGA. There
    is no functional change after this cleanup. This was necessary,
    since the file was a wild mess and it was impossible to make sense
    of it's content, let alone change something without breaking some
    other thing. This patch puts the contents on par with regular U-Boot
    standards.

    Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
    and CONFIG_USE_IRQ, which is undefined by default. Finally, do
    logical reordering of the defines in the file so it's much more
    readable. The reordering was also necessary for the splitting
    as the initial one was messy.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    Marek Vasut
     
  • Add command to enable and disable the bridges between HPS and FPGA.

    This patch does have a checkpatch issue with the assembler portion,
    checkpatch correctly complains that there should be no whitespace
    before quoted newline. I do not agree that fixing this specific
    checkpatch issue will improve the readability, thus this one is not
    addressed.

    Signed-off-by: Marek Vasut
    Cc: Dinh Nguyen
    Cc: Pavel Machek
    Cc: Marek Vasut
    Cc: Tom Rini
    Cc: Albert Aribaud
    Cc: Wolfgang Denk

    Marek Vasut
     
  • Move icache_enable() and dcache_enable() function calls from
    board code into the CPU code and into the enable_caches()
    function. This is how the cache enabling code was designed
    to work.

    Signed-off-by: Marek Vasut
    Cc: Dinh Nguyen
    Cc: Pavel Machek
    Cc: Marek Vasut
    Cc: Tom Rini
    Cc: Albert Aribaud
    Cc: Wolfgang Denk
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
    Enable the bootz command as zImage is used instead uImage.

    Signed-off-by: Chin Liang See
    Signed-off-by: Marek Vasut
    Cc: Dinh Nguyen
    Cc: Pavel Machek
    Cc: Marek Vasut
    Cc: Tom Rini
    Cc: Albert Aribaud
    Cc: Wolfgang Denk
    Acked-by: Pavel Machek

    Chin Liang See
     
  • Enable the DesignWare MMC controller driver support
    for SOCFPGA Cyclone5 dev kit

    Signed-off-by: Chin Liang See
    Signed-off-by: Marek Vasut
    Cc: Dinh Nguyen
    Cc: Pavel Machek
    Cc: Marek Vasut
    Cc: Tom Rini
    Cc: Albert Aribaud
    Cc: Wolfgang Denk
    Acked-by: Pavel Machek

    Chin Liang See
     
  • Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
    The code sets the access permissions for the CPU to the AMBA slaves such
    that the CPU can access them in both secure and non-secure mode.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    Pavel Machek
     
  • Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
    This code also configures the "remap" register of NIC-301 and sets the
    required 'mpuzero' bit.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Add register definition for the NIC-301 used on SoCFPGA.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Add the Snoop Control Unit register definition file.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Enable the PL310 L2 cache controller support for the SoCFPGA.
    With the cache related issues resolved, this is safe to be done.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • The code is now fixed to the point where we can safely enable
    the L1 data cache. Enable the D-Cache and set it as write-alloc.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Add missing system manager bits from Altera U-Boot to make the code
    comparable. These are the bits which depend on the FPGA manager.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Add function to enable and disable FPGA bridges. This code is used
    by the FPGA manager to disable the bridges before programming the
    FPGA and will later be also used by the initialization code for the
    chip to put the chip into well defined state during startup.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Add code necessary to program the FPGA part of SoCFPGA from U-Boot
    with an RBF blob. This patch also integrates the code into the
    FPGA driver framework in U-Boot so it can be used via the 'fpga'
    command.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.

    Pavel Machek
     
  • Cosmetic change to the checkboard() function output. Align the
    output with the rest of initial output produced by U-Boot.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • The bi_boot_params must point to offset 0x100 in DRAM. Make it so.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    Pavel Machek
     
  • Cosmetic change to the print_cpuinfo() function output. Align the
    output with the rest of initial output produced by U-Boot.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    Pavel Machek
     
  • Add CPU function to register and initialize the dw_mmc SD controller.
    This allows us to use the HPS SDMMC block.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    Pavel Machek
     
  • Add function to initialize the EMAC blocks upon board startup.
    The preprocessor guards against building on SoCFPGA-VT and against
    SPL build are not needed as those are handled implicitly via both
    SPL framework and the socfpga_cyclone5.h config file, which will
    not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.

    We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
    Once there is hardware using both EMAC blocks, this ifdef will have
    to go.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    Pavel Machek
     
  • Add functions to reset the EMAC ethernet blocks. We cannot handle
    two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
    hardware using both EMAC blocks, this ifdef will have to go.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • The timer reload value is a property of the timer hardware and there
    is no reason for this to be configurable. Place this into the timer
    driver just like on the other hardware.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Dinh Nguyen
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Make the SoCFPGA MMC stub pick clock via the clock manager
    frequency accessors instead of hard-coding the frequency.

    Also fix calloc() misuse.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Dinh Nguyen

    Pavel Machek
     
  • Add the missing pieces from the reference clock code from Altera. This
    puts the code on par with the Altera U-Boot fork for all but the SDRAM
    self-refresh bits, which are not part of this patch.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Clean up the clock code definitions so they are aligned with mainline
    standards. There are no functional changes in this patch.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Pull out functions to read frequency of Main clock VCO and
    PLL clock VCO as the code is duplicated multiple times.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Dinh Nguyen
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Add the entire bulk of code to read out clock configuration from the SoCFPGA
    CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
    they cannot determine the frequency of their upstream clock.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    V2: Fixed the L4 MP clock divider and synced the clock code with latest
    rocketboards codebase (thanks Dinh for pointing this out)

    Pavel Machek
     
  • Add some stub defines, which are used by the clock code, but are
    missing from the auto-generated header file for the SoCFPGA family.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Dinh Nguyen
    Acked-by: Pavel Machek

    Marek Vasut
     
  • The inlining is done by GCC when needed, there is no need to do it
    explicitly. Furthermore, the inline keyword does not force-inline
    the code, but is only a hint for the compiler. Scrub this hint.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Dinh Nguyen
    Acked-by: Pavel Machek

    Marek Vasut
     
  • The bit definitions for clock manager are complete chaos. Implement
    some basic logical order into them.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • Clean up the system manager register definition and add the missing
    register definitions in place.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek

    Marek Vasut
     
  • This adds watchdog disable. It is neccessary for running Linux kernel.

    Signed-off-by: Pavel Machek
    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek

    V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
    Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)

    Pavel Machek
     
  • Sort the list of functional block addresses and fix indentation.
    No functional change.

    Signed-off-by: Marek Vasut
    Cc: Chin Liang See
    Cc: Dinh Nguyen
    Cc: Albert Aribaud
    Cc: Tom Rini
    Cc: Wolfgang Denk
    Cc: Pavel Machek
    Acked-by: Pavel Machek
    Acked-by: Chin Liang See

    Marek Vasut