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drivers/cpufreq/s3c64xx-cpufreq.c
5.38 KB
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/* |
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* Copyright 2009 Wolfson Microelectronics plc * * S3C64xx CPUfreq Support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ |
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#define pr_fmt(fmt) "cpufreq: " fmt |
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#include <linux/kernel.h> #include <linux/types.h> #include <linux/init.h> #include <linux/cpufreq.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/regulator/consumer.h> |
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#include <linux/module.h> |
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static struct regulator *vddarm; |
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static unsigned long regulator_latency; |
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#ifdef CONFIG_CPU_S3C6410 struct s3c64xx_dvfs { unsigned int vddarm_min; unsigned int vddarm_max; }; static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { |
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[0] = { 1000000, 1150000 }, [1] = { 1050000, 1150000 }, [2] = { 1100000, 1150000 }, [3] = { 1200000, 1350000 }, |
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[4] = { 1300000, 1350000 }, |
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}; static struct cpufreq_frequency_table s3c64xx_freq_table[] = { |
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{ 0, 0, 66000 }, { 0, 0, 100000 }, { 0, 0, 133000 }, { 0, 1, 200000 }, { 0, 1, 222000 }, { 0, 1, 266000 }, { 0, 2, 333000 }, { 0, 2, 400000 }, { 0, 2, 532000 }, { 0, 2, 533000 }, { 0, 3, 667000 }, { 0, 4, 800000 }, { 0, 0, CPUFREQ_TABLE_END }, |
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}; #endif |
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static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, |
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unsigned int index) |
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{ |
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struct s3c64xx_dvfs *dvfs; |
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unsigned int old_freq, new_freq; int ret; |
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old_freq = clk_get_rate(policy->clk) / 1000; |
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new_freq = s3c64xx_freq_table[index].frequency; |
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dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; |
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#ifdef CONFIG_REGULATOR |
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if (vddarm && new_freq > old_freq) { |
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ret = regulator_set_voltage(vddarm, dvfs->vddarm_min, dvfs->vddarm_max); if (ret != 0) { |
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pr_err("Failed to set VDDARM for %dkHz: %d ", |
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new_freq, ret); return ret; |
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} } #endif |
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ret = clk_set_rate(policy->clk, new_freq * 1000); |
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if (ret < 0) { |
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pr_err("Failed to set rate %dkHz: %d ", |
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new_freq, ret); return ret; |
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} #ifdef CONFIG_REGULATOR |
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if (vddarm && new_freq < old_freq) { |
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ret = regulator_set_voltage(vddarm, dvfs->vddarm_min, dvfs->vddarm_max); if (ret != 0) { |
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pr_err("Failed to set VDDARM for %dkHz: %d ", |
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new_freq, ret); |
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if (clk_set_rate(policy->clk, old_freq * 1000) < 0) |
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pr_err("Failed to restore original clock rate "); return ret; |
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} } #endif |
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pr_debug("Set actual frequency %lukHz ", |
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clk_get_rate(policy->clk) / 1000); |
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return 0; |
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} #ifdef CONFIG_REGULATOR |
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static void __init s3c64xx_cpufreq_config_regulator(void) |
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{ int count, v, i, found; struct cpufreq_frequency_table *freq; struct s3c64xx_dvfs *dvfs; count = regulator_count_voltages(vddarm); if (count < 0) { |
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pr_err("Unable to check supported voltages "); |
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} |
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if (!count) goto out; |
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cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) { |
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dvfs = &s3c64xx_dvfs_table[freq->driver_data]; |
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found = 0; for (i = 0; i < count; i++) { v = regulator_list_voltage(vddarm, i); if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) found = 1; } if (!found) { |
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pr_debug("%dkHz unsupported by regulator ", |
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freq->frequency); freq->frequency = CPUFREQ_ENTRY_INVALID; } |
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} |
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out: |
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/* Guess based on having to do an I2C/SPI write; in future we * will be able to query the regulator performance here. */ regulator_latency = 1 * 1000 * 1000; |
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} #endif |
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static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) |
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{ int ret; struct cpufreq_frequency_table *freq; if (policy->cpu != 0) return -EINVAL; if (s3c64xx_freq_table == NULL) { |
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pr_err("No frequency information for this CPU "); |
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return -ENODEV; } |
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policy->clk = clk_get(NULL, "armclk"); if (IS_ERR(policy->clk)) { |
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pr_err("Unable to obtain ARMCLK: %ld ", |
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PTR_ERR(policy->clk)); return PTR_ERR(policy->clk); |
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} #ifdef CONFIG_REGULATOR vddarm = regulator_get(NULL, "vddarm"); if (IS_ERR(vddarm)) { ret = PTR_ERR(vddarm); |
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pr_err("Failed to obtain VDDARM: %d ", ret); pr_err("Only frequency scaling available "); |
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vddarm = NULL; } else { |
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s3c64xx_cpufreq_config_regulator(); |
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} #endif |
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cpufreq_for_each_entry(freq, s3c64xx_freq_table) { |
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unsigned long r; /* Check for frequencies we can generate */ |
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r = clk_round_rate(policy->clk, freq->frequency * 1000); |
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r /= 1000; |
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if (r != freq->frequency) { |
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pr_debug("%dkHz unsupported by clock ", |
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freq->frequency); |
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freq->frequency = CPUFREQ_ENTRY_INVALID; |
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} |
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/* If we have no regulator then assume startup * frequency is the maximum we can support. */ |
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if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000) |
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freq->frequency = CPUFREQ_ENTRY_INVALID; |
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} |
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/* Datasheet says PLL stabalisation time (if we were to use * the PLLs, which we don't currently) is ~300us worst case, * but add some fudge. */ |
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ret = cpufreq_generic_init(policy, s3c64xx_freq_table, (500 * 1000) + regulator_latency); |
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if (ret != 0) { |
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pr_err("Failed to configure frequency table: %d ", |
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ret); regulator_put(vddarm); |
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clk_put(policy->clk); |
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} return ret; } static struct cpufreq_driver s3c64xx_cpufreq_driver = { |
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
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.verify = cpufreq_generic_frequency_table_verify, |
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.target_index = s3c64xx_cpufreq_set_target, |
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.get = cpufreq_generic_get, |
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.init = s3c64xx_cpufreq_driver_init, .name = "s3c", }; static int __init s3c64xx_cpufreq_init(void) { return cpufreq_register_driver(&s3c64xx_cpufreq_driver); } module_init(s3c64xx_cpufreq_init); |