/*
   * Copyright © 2012 Intel Corporation
   *
   * Permission is hereby granted, free of charge, to any person obtaining a
   * copy of this software and associated documentation files (the "Software"),
   * to deal in the Software without restriction, including without limitation
   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   * and/or sell copies of the Software, and to permit persons to whom the
   * Software is furnished to do so, subject to the following conditions:
   *
   * The above copyright notice and this permission notice (including the next
   * paragraph) shall be included in all copies or substantial portions of the
   * Software.
   *
   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
   * IN THE SOFTWARE.
   *
   * Authors:
   *    Eugeni Dodonov <eugeni.dodonov@intel.com>
   *
   */

  #include <linux/cpufreq.h>

  #include "i915_drv.h"
  #include "intel_drv.h"

  #include "../../../platform/x86/intel_ips.h"
  #include <linux/module.h>

  #include <linux/vgaarb.h>

  #include <drm/i915_powerwell.h>

  #include <linux/pm_runtime.h>

  /**
   * RC6 is a special power stage which allows the GPU to enter an very
   * low-voltage mode when idle, using down to 0V while at this stage.  This
   * stage is entered automatically when the GPU is idle when RC6 support is
   * enabled, and as soon as new workload arises GPU wakes up automatically as well.
   *
   * There are different RC6 modes available in Intel GPU, which differentiate
   * among each other with the latency required to enter and leave RC6 and
   * voltage consumed by the GPU in different states.
   *
   * The combination of the following flags define which states GPU is allowed
   * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
   * RC6pp is deepest RC6. Their support by hardware varies according to the
   * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
   * which brings the most power savings; deeper states save more power, but
   * require higher latency to switch to and wake up.
   */
  #define INTEL_RC6_ENABLE			(1<<0)
  #define INTEL_RC6p_ENABLE			(1<<1)
  #define INTEL_RC6pp_ENABLE			(1<<2)

  /* FBC, or Frame Buffer Compression, is a technique employed to compress the
   * framebuffer contents in-memory, aiming at reducing the required bandwidth
   * during in-memory transfers and, therefore, reduce the power packet.

   *

   * The benefits of FBC are mostly visible with solid backgrounds and
   * variation-less patterns.

   *

   * FBC-related functionality can be enabled by the means of the
   * i915.i915_enable_fbc parameter

   */

  static void i8xx_disable_fbc(struct drm_device *dev)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	u32 fbc_ctl;
  
  	/* Disable compression */
  	fbc_ctl = I915_READ(FBC_CONTROL);
  	if ((fbc_ctl & FBC_CTL_EN) == 0)
  		return;
  
  	fbc_ctl &= ~FBC_CTL_EN;
  	I915_WRITE(FBC_CONTROL, fbc_ctl);
  
  	/* Wait for compressing bit to clear */
  	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  		DRM_DEBUG_KMS("FBC idle timed out
  ");
  		return;
  	}
  
  	DRM_DEBUG_KMS("disabled FBC
  ");
  }

  static void i8xx_enable_fbc(struct drm_crtc *crtc)

  {
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;

  	struct drm_framebuffer *fb = crtc->primary->fb;

  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  	int cfb_pitch;

  	int i;

  	u32 fbc_ctl;

  	cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;

  	if (fb->pitches[0] < cfb_pitch)
  		cfb_pitch = fb->pitches[0];

  	/* FBC_CTL wants 32B or 64B units */
  	if (IS_GEN2(dev))
  		cfb_pitch = (cfb_pitch / 32) - 1;
  	else
  		cfb_pitch = (cfb_pitch / 64) - 1;

  
  	/* Clear old tags */
  	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  		I915_WRITE(FBC_TAG + (i * 4), 0);

  	if (IS_GEN4(dev)) {
  		u32 fbc_ctl2;
  
  		/* Set it up... */
  		fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;

  		fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);

  		I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  		I915_WRITE(FBC_FENCE_OFF, crtc->y);
  	}

  
  	/* enable it... */

  	fbc_ctl = I915_READ(FBC_CONTROL);
  	fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
  	fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;

  	if (IS_I945GM(dev))
  		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;

  	fbc_ctl |= obj->fence_reg;
  	I915_WRITE(FBC_CONTROL, fbc_ctl);

  	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c
  ",

  		      cfb_pitch, crtc->y, plane_name(intel_crtc->plane));

  }

  static bool i8xx_fbc_enabled(struct drm_device *dev)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  }

  static void g4x_enable_fbc(struct drm_crtc *crtc)

  {
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;

  	struct drm_framebuffer *fb = crtc->primary->fb;

  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

  	u32 dpfc_ctl;

  	dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
  	if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
  		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
  	else
  		dpfc_ctl |= DPFC_CTL_LIMIT_1X;

  	dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;

  	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  
  	/* enable it... */

  	I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

  	DRM_DEBUG_KMS("enabled fbc on plane %c
  ", plane_name(intel_crtc->plane));

  }

  static void g4x_disable_fbc(struct drm_device *dev)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	u32 dpfc_ctl;
  
  	/* Disable compression */
  	dpfc_ctl = I915_READ(DPFC_CONTROL);
  	if (dpfc_ctl & DPFC_CTL_EN) {
  		dpfc_ctl &= ~DPFC_CTL_EN;
  		I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  
  		DRM_DEBUG_KMS("disabled FBC
  ");
  	}
  }

  static bool g4x_fbc_enabled(struct drm_device *dev)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  }
  
  static void sandybridge_blit_fbc_update(struct drm_device *dev)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	u32 blt_ecoskpd;
  
  	/* Make sure blitter notifies FBC of writes */

  
  	/* Blitter is part of Media powerwell on VLV. No impact of
  	 * his param in other platforms for now */
  	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);

  	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  		GEN6_BLITTER_LOCK_SHIFT;
  	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  			 GEN6_BLITTER_LOCK_SHIFT);
  	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  	POSTING_READ(GEN6_BLITTER_ECOSKPD);

  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);

  }

  static void ironlake_enable_fbc(struct drm_crtc *crtc)

  {
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;

  	struct drm_framebuffer *fb = crtc->primary->fb;

  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

  	u32 dpfc_ctl;

  	dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);

  	if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)

  		dev_priv->fbc.threshold++;
  
  	switch (dev_priv->fbc.threshold) {
  	case 4:
  	case 3:
  		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
  		break;
  	case 2:

  		dpfc_ctl |= DPFC_CTL_LIMIT_2X;

  		break;
  	case 1:

  		dpfc_ctl |= DPFC_CTL_LIMIT_1X;

  		break;
  	}

  	dpfc_ctl |= DPFC_CTL_FENCE_EN;
  	if (IS_GEN5(dev))
  		dpfc_ctl |= obj->fence_reg;

  	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);

  	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);

  	/* enable it... */
  	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  
  	if (IS_GEN6(dev)) {
  		I915_WRITE(SNB_DPFC_CTL_SA,
  			   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  		sandybridge_blit_fbc_update(dev);
  	}

  	DRM_DEBUG_KMS("enabled fbc on plane %c
  ", plane_name(intel_crtc->plane));

  }

  static void ironlake_disable_fbc(struct drm_device *dev)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	u32 dpfc_ctl;
  
  	/* Disable compression */
  	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  	if (dpfc_ctl & DPFC_CTL_EN) {
  		dpfc_ctl &= ~DPFC_CTL_EN;
  		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  
  		DRM_DEBUG_KMS("disabled FBC
  ");
  	}
  }

  static bool ironlake_fbc_enabled(struct drm_device *dev)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  }

  static void gen7_enable_fbc(struct drm_crtc *crtc)

  {
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;

  	struct drm_framebuffer *fb = crtc->primary->fb;

  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

  	u32 dpfc_ctl;

  	dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
  	if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)

  		dev_priv->fbc.threshold++;
  
  	switch (dev_priv->fbc.threshold) {
  	case 4:
  	case 3:
  		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
  		break;
  	case 2:

  		dpfc_ctl |= DPFC_CTL_LIMIT_2X;

  		break;
  	case 1:

  		dpfc_ctl |= DPFC_CTL_LIMIT_1X;

  		break;
  	}

  	dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;

  	if (dev_priv->fbc.false_color)
  		dpfc_ctl |= FBC_CTL_FALSE_COLOR;

  	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

  	if (IS_IVYBRIDGE(dev)) {

  		/* WaFbcAsynchFlipDisableFbcQueue:ivb */

  		I915_WRITE(ILK_DISPLAY_CHICKEN1,
  			   I915_READ(ILK_DISPLAY_CHICKEN1) |
  			   ILK_FBCQ_DIS);

  	} else {

  		/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */

  		I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
  			   I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
  			   HSW_FBCQ_DIS);

  	}

  	I915_WRITE(SNB_DPFC_CTL_SA,
  		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  
  	sandybridge_blit_fbc_update(dev);

  	DRM_DEBUG_KMS("enabled fbc on plane %c
  ", plane_name(intel_crtc->plane));

  }

  bool intel_fbc_enabled(struct drm_device *dev)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	if (!dev_priv->display.fbc_enabled)
  		return false;
  
  	return dev_priv->display.fbc_enabled(dev);
  }

  void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	if (!IS_GEN8(dev))
  		return;
  
  	I915_WRITE(MSG_FBC_REND_STATE, value);
  }

  static void intel_fbc_work_fn(struct work_struct *__work)
  {
  	struct intel_fbc_work *work =
  		container_of(to_delayed_work(__work),
  			     struct intel_fbc_work, work);
  	struct drm_device *dev = work->crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	mutex_lock(&dev->struct_mutex);

  	if (work == dev_priv->fbc.fbc_work) {

  		/* Double check that we haven't switched fb without cancelling
  		 * the prior work.
  		 */

  		if (work->crtc->primary->fb == work->fb) {

  			dev_priv->display.enable_fbc(work->crtc);

  			dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;

  			dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;

  			dev_priv->fbc.y = work->crtc->y;

  		}

  		dev_priv->fbc.fbc_work = NULL;

  	}
  	mutex_unlock(&dev->struct_mutex);
  
  	kfree(work);
  }
  
  static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  {

  	if (dev_priv->fbc.fbc_work == NULL)

  		return;
  
  	DRM_DEBUG_KMS("cancelling pending FBC enable
  ");
  
  	/* Synchronisation is provided by struct_mutex and checking of

  	 * dev_priv->fbc.fbc_work, so we can perform the cancellation

  	 * entirely asynchronously.
  	 */

  	if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))

  		/* tasklet was killed before being run, clean up */

  		kfree(dev_priv->fbc.fbc_work);

  
  	/* Mark the work as no longer wanted so that if it does
  	 * wake-up (because the work was already running and waiting
  	 * for our mutex), it will discover that is no longer
  	 * necessary to run.
  	 */

  	dev_priv->fbc.fbc_work = NULL;

  }

  static void intel_enable_fbc(struct drm_crtc *crtc)

  {
  	struct intel_fbc_work *work;
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	if (!dev_priv->display.enable_fbc)
  		return;
  
  	intel_cancel_fbc_work(dev_priv);

  	work = kzalloc(sizeof(*work), GFP_KERNEL);

  	if (work == NULL) {

  		DRM_ERROR("Failed to allocate FBC work structure
  ");

  		dev_priv->display.enable_fbc(crtc);

  		return;
  	}
  
  	work->crtc = crtc;

  	work->fb = crtc->primary->fb;

  	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

  	dev_priv->fbc.fbc_work = work;

  	/* Delay the actual enabling to let pageflipping cease and the
  	 * display to settle before starting the compression. Note that
  	 * this delay also serves a second purpose: it allows for a
  	 * vblank to pass after disabling the FBC before we attempt
  	 * to modify the control registers.
  	 *
  	 * A more complicated solution would involve tracking vblanks
  	 * following the termination of the page-flipping sequence
  	 * and indeed performing the enable as a co-routine and not
  	 * waiting synchronously upon the vblank.

  	 *
  	 * WaFbcWaitForVBlankBeforeEnable:ilk,snb

  	 */
  	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  }
  
  void intel_disable_fbc(struct drm_device *dev)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  
  	intel_cancel_fbc_work(dev_priv);
  
  	if (!dev_priv->display.disable_fbc)
  		return;
  
  	dev_priv->display.disable_fbc(dev);

  	dev_priv->fbc.plane = -1;

  }

  static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
  			      enum no_fbc_reason reason)
  {
  	if (dev_priv->fbc.no_fbc_reason == reason)
  		return false;
  
  	dev_priv->fbc.no_fbc_reason = reason;
  	return true;
  }

  /**
   * intel_update_fbc - enable/disable FBC as needed
   * @dev: the drm_device
   *
   * Set up the framebuffer compression hardware at mode set time.  We
   * enable it if possible:
   *   - plane A only (on pre-965)
   *   - no pixel mulitply/line duplication
   *   - no alpha buffer discard
   *   - no dual wide

   *   - framebuffer <= max_hdisplay in width, max_vdisplay in height

   *
   * We can't assume that any compression will take place (worst case),
   * so the compressed buffer has to be the same size as the uncompressed
   * one.  It also must reside (along with the line length buffer) in
   * stolen memory.
   *
   * We need to enable/disable FBC on a global basis.
   */
  void intel_update_fbc(struct drm_device *dev)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct drm_crtc *crtc = NULL, *tmp_crtc;
  	struct intel_crtc *intel_crtc;
  	struct drm_framebuffer *fb;

  	struct drm_i915_gem_object *obj;

  	const struct drm_display_mode *adjusted_mode;

  	unsigned int max_width, max_height;

  	if (!HAS_FBC(dev)) {

  		set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);

  		return;

  	}

  	if (!i915.powersave) {

  		if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
  			DRM_DEBUG_KMS("fbc disabled per module param
  ");

  		return;

  	}

  
  	/*
  	 * If FBC is already on, we just have to verify that we can
  	 * keep it that way...
  	 * Need to disable if:
  	 *   - more than one pipe is active
  	 *   - changing FBC params (stride, fence, mode)
  	 *   - new fb is too large to fit in compressed buffer
  	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
  	 */

  	for_each_crtc(dev, tmp_crtc) {

  		if (intel_crtc_active(tmp_crtc) &&

  		    to_intel_crtc(tmp_crtc)->primary_enabled) {

  			if (crtc) {

  				if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
  					DRM_DEBUG_KMS("more than one pipe active, disabling compression
  ");

  				goto out_disable;
  			}
  			crtc = tmp_crtc;
  		}
  	}

  	if (!crtc || crtc->primary->fb == NULL) {

  		if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
  			DRM_DEBUG_KMS("no output, disabling
  ");

  		goto out_disable;
  	}
  
  	intel_crtc = to_intel_crtc(crtc);

  	fb = crtc->primary->fb;

  	obj = intel_fb_obj(fb);

  	adjusted_mode = &intel_crtc->config.adjusted_mode;

  	if (i915.enable_fbc < 0) {

  		if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
  			DRM_DEBUG_KMS("disabled per chip default
  ");

  		goto out_disable;

  	}

  	if (!i915.enable_fbc) {

  		if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
  			DRM_DEBUG_KMS("fbc disabled per module param
  ");

  		goto out_disable;
  	}

  	if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  	    (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {

  		if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
  			DRM_DEBUG_KMS("mode incompatible with compression, "
  				      "disabling
  ");

  		goto out_disable;
  	}

  	if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
  		max_width = 4096;
  		max_height = 4096;
  	} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {

  		max_width = 4096;
  		max_height = 2048;

  	} else {

  		max_width = 2048;
  		max_height = 1536;

  	}

  	if (intel_crtc->config.pipe_src_w > max_width ||
  	    intel_crtc->config.pipe_src_h > max_height) {

  		if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
  			DRM_DEBUG_KMS("mode too large for compression, disabling
  ");

  		goto out_disable;
  	}

  	if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&

  	    intel_crtc->plane != PLANE_A) {

  		if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))

  			DRM_DEBUG_KMS("plane not A, disabling compression
  ");

  		goto out_disable;
  	}
  
  	/* The use of a CPU fence is mandatory in order to detect writes
  	 * by the CPU to the scanout and trigger updates to the FBC.
  	 */
  	if (obj->tiling_mode != I915_TILING_X ||
  	    obj->fence_reg == I915_FENCE_REG_NONE) {

  		if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
  			DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression
  ");

  		goto out_disable;
  	}

  	if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
  	    to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
  		if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
  			DRM_DEBUG_KMS("Rotation unsupported, disabling
  ");
  		goto out_disable;
  	}

  
  	/* If the kernel debugger is active, always disable compression */
  	if (in_dbg_master())
  		goto out_disable;

  	if (i915_gem_stolen_setup_compression(dev, obj->base.size,

  					      drm_format_plane_cpp(fb->pixel_format, 0))) {

  		if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
  			DRM_DEBUG_KMS("framebuffer too large, disabling compression
  ");

  		goto out_disable;
  	}

  	/* If the scanout has not changed, don't modify the FBC settings.
  	 * Note that we make the fundamental assumption that the fb->obj
  	 * cannot be unpinned (and have its GTT offset and fence revoked)
  	 * without first being decoupled from the scanout and FBC disabled.
  	 */

  	if (dev_priv->fbc.plane == intel_crtc->plane &&
  	    dev_priv->fbc.fb_id == fb->base.id &&
  	    dev_priv->fbc.y == crtc->y)

  		return;
  
  	if (intel_fbc_enabled(dev)) {
  		/* We update FBC along two paths, after changing fb/crtc
  		 * configuration (modeswitching) and after page-flipping
  		 * finishes. For the latter, we know that not only did
  		 * we disable the FBC at the start of the page-flip
  		 * sequence, but also more than one vblank has passed.
  		 *
  		 * For the former case of modeswitching, it is possible
  		 * to switch between two FBC valid configurations
  		 * instantaneously so we do need to disable the FBC
  		 * before we can modify its control registers. We also
  		 * have to wait for the next vblank for that to take
  		 * effect. However, since we delay enabling FBC we can
  		 * assume that a vblank has passed since disabling and
  		 * that we can safely alter the registers in the deferred
  		 * callback.
  		 *
  		 * In the scenario that we go from a valid to invalid
  		 * and then back to valid FBC configuration we have
  		 * no strict enforcement that a vblank occurred since
  		 * disabling the FBC. However, along all current pipe
  		 * disabling paths we do need to wait for a vblank at
  		 * some point. And we wait before enabling FBC anyway.
  		 */
  		DRM_DEBUG_KMS("disabling active FBC for update
  ");
  		intel_disable_fbc(dev);
  	}

  	intel_enable_fbc(crtc);

  	dev_priv->fbc.no_fbc_reason = FBC_OK;

  	return;
  
  out_disable:
  	/* Multiple disables should be harmless */
  	if (intel_fbc_enabled(dev)) {
  		DRM_DEBUG_KMS("unsupported config, disabling FBC
  ");
  		intel_disable_fbc(dev);
  	}

  	i915_gem_stolen_cleanup_compression(dev);

  }

  static void i915_pineview_get_mem_freq(struct drm_device *dev)
  {

  	struct drm_i915_private *dev_priv = dev->dev_private;

  	u32 tmp;
  
  	tmp = I915_READ(CLKCFG);
  
  	switch (tmp & CLKCFG_FSB_MASK) {
  	case CLKCFG_FSB_533:
  		dev_priv->fsb_freq = 533; /* 133*4 */
  		break;
  	case CLKCFG_FSB_800:
  		dev_priv->fsb_freq = 800; /* 200*4 */
  		break;
  	case CLKCFG_FSB_667:
  		dev_priv->fsb_freq =  667; /* 167*4 */
  		break;
  	case CLKCFG_FSB_400:
  		dev_priv->fsb_freq = 400; /* 100*4 */
  		break;
  	}
  
  	switch (tmp & CLKCFG_MEM_MASK) {
  	case CLKCFG_MEM_533:
  		dev_priv->mem_freq = 533;
  		break;
  	case CLKCFG_MEM_667:
  		dev_priv->mem_freq = 667;
  		break;
  	case CLKCFG_MEM_800:
  		dev_priv->mem_freq = 800;
  		break;
  	}
  
  	/* detect pineview DDR3 setting */
  	tmp = I915_READ(CSHRDDR3CTL);
  	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  }
  
  static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  {

  	struct drm_i915_private *dev_priv = dev->dev_private;

  	u16 ddrpll, csipll;
  
  	ddrpll = I915_READ16(DDRMPLL1);
  	csipll = I915_READ16(CSIPLL0);
  
  	switch (ddrpll & 0xff) {
  	case 0xc:
  		dev_priv->mem_freq = 800;
  		break;
  	case 0x10:
  		dev_priv->mem_freq = 1066;
  		break;
  	case 0x14:
  		dev_priv->mem_freq = 1333;
  		break;
  	case 0x18:
  		dev_priv->mem_freq = 1600;
  		break;
  	default:
  		DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x
  ",
  				 ddrpll & 0xff);
  		dev_priv->mem_freq = 0;
  		break;
  	}

  	dev_priv->ips.r_t = dev_priv->mem_freq;

  
  	switch (csipll & 0x3ff) {
  	case 0x00c:
  		dev_priv->fsb_freq = 3200;
  		break;
  	case 0x00e:
  		dev_priv->fsb_freq = 3733;
  		break;
  	case 0x010:
  		dev_priv->fsb_freq = 4266;
  		break;
  	case 0x012:
  		dev_priv->fsb_freq = 4800;
  		break;
  	case 0x014:
  		dev_priv->fsb_freq = 5333;
  		break;
  	case 0x016:
  		dev_priv->fsb_freq = 5866;
  		break;
  	case 0x018:
  		dev_priv->fsb_freq = 6400;
  		break;
  	default:
  		DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x
  ",
  				 csipll & 0x3ff);
  		dev_priv->fsb_freq = 0;
  		break;
  	}
  
  	if (dev_priv->fsb_freq == 3200) {

  		dev_priv->ips.c_m = 0;

  	} else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {

  		dev_priv->ips.c_m = 1;

  	} else {

  		dev_priv->ips.c_m = 2;

  	}
  }

  static const struct cxsr_latency cxsr_latency_table[] = {
  	{1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
  	{1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
  	{1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
  	{1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
  	{1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
  
  	{1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
  	{1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
  	{1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
  	{1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
  	{1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
  
  	{1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
  	{1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
  	{1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
  	{1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
  	{1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
  
  	{0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
  	{0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
  	{0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
  	{0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
  	{0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
  
  	{0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
  	{0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
  	{0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
  	{0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
  	{0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
  
  	{0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
  	{0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
  	{0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
  	{0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
  	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
  };

  static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,

  							 int is_ddr3,
  							 int fsb,
  							 int mem)
  {
  	const struct cxsr_latency *latency;
  	int i;
  
  	if (fsb == 0 || mem == 0)
  		return NULL;
  
  	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  		latency = &cxsr_latency_table[i];
  		if (is_desktop == latency->is_desktop &&
  		    is_ddr3 == latency->is_ddr3 &&
  		    fsb == latency->fsb_freq && mem == latency->mem_freq)
  			return latency;
  	}
  
  	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR
  ");
  
  	return NULL;
  }

  void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)

  {

  	struct drm_device *dev = dev_priv->dev;
  	u32 val;

  	if (IS_VALLEYVIEW(dev)) {
  		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
  	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
  		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
  	} else if (IS_PINEVIEW(dev)) {
  		val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
  		val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
  		I915_WRITE(DSPFW3, val);
  	} else if (IS_I945G(dev) || IS_I945GM(dev)) {
  		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
  			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
  		I915_WRITE(FW_BLC_SELF, val);
  	} else if (IS_I915GM(dev)) {
  		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
  			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
  		I915_WRITE(INSTPM, val);
  	} else {
  		return;
  	}

  	DRM_DEBUG_KMS("memory self-refresh is %s
  ",
  		      enable ? "enabled" : "disabled");

  }
  
  /*
   * Latency for FIFO fetches is dependent on several factors:
   *   - memory configuration (speed, channels)
   *   - chipset
   *   - current MCH state
   * It can be fairly high in some situations, so here we assume a fairly
   * pessimal value.  It's a tradeoff between extra memory fetches (if we
   * set this value too high, the FIFO will fetch frequently to stay full)
   * and power consumption (set it too low to save power and we might see
   * FIFO underruns and display "flicker").
   *
   * A value of 5us seems to be a good balance; safe for very low end
   * platforms but not overly aggressive on lower latency configs.
   */

  static const int pessimal_latency_ns = 5000;

  static int i9xx_get_fifo_size(struct drm_device *dev, int plane)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	uint32_t dsparb = I915_READ(DSPARB);
  	int size;
  
  	size = dsparb & 0x7f;
  	if (plane)
  		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  
  	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d
  ", dsparb,
  		      plane ? "B" : "A", size);
  
  	return size;
  }

  static int i830_get_fifo_size(struct drm_device *dev, int plane)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	uint32_t dsparb = I915_READ(DSPARB);
  	int size;
  
  	size = dsparb & 0x1ff;
  	if (plane)
  		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  	size >>= 1; /* Convert to cachelines */
  
  	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d
  ", dsparb,
  		      plane ? "B" : "A", size);
  
  	return size;
  }

  static int i845_get_fifo_size(struct drm_device *dev, int plane)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	uint32_t dsparb = I915_READ(DSPARB);
  	int size;
  
  	size = dsparb & 0x7f;
  	size >>= 2; /* Convert to cachelines */
  
  	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d
  ", dsparb,
  		      plane ? "B" : "A",
  		      size);
  
  	return size;
  }

  /* Pineview has different values for various configs */
  static const struct intel_watermark_params pineview_display_wm = {

  	.fifo_size = PINEVIEW_DISPLAY_FIFO,
  	.max_wm = PINEVIEW_MAX_WM,
  	.default_wm = PINEVIEW_DFT_WM,
  	.guard_size = PINEVIEW_GUARD_WM,
  	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params pineview_display_hplloff_wm = {

  	.fifo_size = PINEVIEW_DISPLAY_FIFO,
  	.max_wm = PINEVIEW_MAX_WM,
  	.default_wm = PINEVIEW_DFT_HPLLOFF_WM,
  	.guard_size = PINEVIEW_GUARD_WM,
  	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params pineview_cursor_wm = {

  	.fifo_size = PINEVIEW_CURSOR_FIFO,
  	.max_wm = PINEVIEW_CURSOR_MAX_WM,
  	.default_wm = PINEVIEW_CURSOR_DFT_WM,
  	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
  	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params pineview_cursor_hplloff_wm = {

  	.fifo_size = PINEVIEW_CURSOR_FIFO,
  	.max_wm = PINEVIEW_CURSOR_MAX_WM,
  	.default_wm = PINEVIEW_CURSOR_DFT_WM,
  	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
  	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params g4x_wm_info = {

  	.fifo_size = G4X_FIFO_SIZE,
  	.max_wm = G4X_MAX_WM,
  	.default_wm = G4X_MAX_WM,
  	.guard_size = 2,
  	.cacheline_size = G4X_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params g4x_cursor_wm_info = {

  	.fifo_size = I965_CURSOR_FIFO,
  	.max_wm = I965_CURSOR_MAX_WM,
  	.default_wm = I965_CURSOR_DFT_WM,
  	.guard_size = 2,
  	.cacheline_size = G4X_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params valleyview_wm_info = {

  	.fifo_size = VALLEYVIEW_FIFO_SIZE,
  	.max_wm = VALLEYVIEW_MAX_WM,
  	.default_wm = VALLEYVIEW_MAX_WM,
  	.guard_size = 2,
  	.cacheline_size = G4X_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params valleyview_cursor_wm_info = {

  	.fifo_size = I965_CURSOR_FIFO,
  	.max_wm = VALLEYVIEW_CURSOR_MAX_WM,
  	.default_wm = I965_CURSOR_DFT_WM,
  	.guard_size = 2,
  	.cacheline_size = G4X_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params i965_cursor_wm_info = {

  	.fifo_size = I965_CURSOR_FIFO,
  	.max_wm = I965_CURSOR_MAX_WM,
  	.default_wm = I965_CURSOR_DFT_WM,
  	.guard_size = 2,
  	.cacheline_size = I915_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params i945_wm_info = {

  	.fifo_size = I945_FIFO_SIZE,
  	.max_wm = I915_MAX_WM,
  	.default_wm = 1,
  	.guard_size = 2,
  	.cacheline_size = I915_FIFO_LINE_SIZE,

  };
  static const struct intel_watermark_params i915_wm_info = {

  	.fifo_size = I915_FIFO_SIZE,
  	.max_wm = I915_MAX_WM,
  	.default_wm = 1,
  	.guard_size = 2,
  	.cacheline_size = I915_FIFO_LINE_SIZE,

  };

  static const struct intel_watermark_params i830_a_wm_info = {

  	.fifo_size = I855GM_FIFO_SIZE,
  	.max_wm = I915_MAX_WM,
  	.default_wm = 1,
  	.guard_size = 2,
  	.cacheline_size = I830_FIFO_LINE_SIZE,

  };

  static const struct intel_watermark_params i830_bc_wm_info = {
  	.fifo_size = I855GM_FIFO_SIZE,
  	.max_wm = I915_MAX_WM/2,
  	.default_wm = 1,
  	.guard_size = 2,
  	.cacheline_size = I830_FIFO_LINE_SIZE,
  };

  static const struct intel_watermark_params i845_wm_info = {

  	.fifo_size = I830_FIFO_SIZE,
  	.max_wm = I915_MAX_WM,
  	.default_wm = 1,
  	.guard_size = 2,
  	.cacheline_size = I830_FIFO_LINE_SIZE,

  };

  /**
   * intel_calculate_wm - calculate watermark level
   * @clock_in_khz: pixel clock
   * @wm: chip FIFO params
   * @pixel_size: display pixel size
   * @latency_ns: memory latency for the platform
   *
   * Calculate the watermark level (the level at which the display plane will
   * start fetching from memory again).  Each chip has a different display
   * FIFO size and allocation, so the caller needs to figure that out and pass
   * in the correct intel_watermark_params structure.
   *
   * As the pixel clock runs, the FIFO will be drained at a rate that depends
   * on the pixel size.  When it reaches the watermark level, it'll start
   * fetching FIFO line sized based chunks from memory until the FIFO fills
   * past the watermark point.  If the FIFO drains completely, a FIFO underrun
   * will occur, and a display engine hang could result.
   */
  static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  					const struct intel_watermark_params *wm,
  					int fifo_size,
  					int pixel_size,
  					unsigned long latency_ns)
  {
  	long entries_required, wm_size;
  
  	/*
  	 * Note: we need to make sure we don't overflow for various clock &
  	 * latency values.
  	 * clocks go from a few thousand to several hundred thousand.
  	 * latency is usually a few thousand
  	 */
  	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  		1000;
  	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  
  	DRM_DEBUG_KMS("FIFO entries required for mode: %ld
  ", entries_required);
  
  	wm_size = fifo_size - (entries_required + wm->guard_size);
  
  	DRM_DEBUG_KMS("FIFO watermark level: %ld
  ", wm_size);
  
  	/* Don't promote wm_size to unsigned... */
  	if (wm_size > (long)wm->max_wm)
  		wm_size = wm->max_wm;
  	if (wm_size <= 0)
  		wm_size = wm->default_wm;

  
  	/*
  	 * Bspec seems to indicate that the value shouldn't be lower than
  	 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
  	 * Lets go for 8 which is the burst size since certain platforms
  	 * already use a hardcoded 8 (which is what the spec says should be
  	 * done).
  	 */
  	if (wm_size <= 8)
  		wm_size = 8;

  	return wm_size;
  }
  
  static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  {
  	struct drm_crtc *crtc, *enabled = NULL;

  	for_each_crtc(dev, crtc) {

  		if (intel_crtc_active(crtc)) {

  			if (enabled)
  				return NULL;
  			enabled = crtc;
  		}
  	}
  
  	return enabled;
  }

  static void pineview_update_wm(struct drm_crtc *unused_crtc)

  {

  	struct drm_device *dev = unused_crtc->dev;

  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct drm_crtc *crtc;
  	const struct cxsr_latency *latency;
  	u32 reg;
  	unsigned long wm;
  
  	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  					 dev_priv->fsb_freq, dev_priv->mem_freq);
  	if (!latency) {
  		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR
  ");

  		intel_set_memory_cxsr(dev_priv, false);

  		return;
  	}
  
  	crtc = single_enabled_crtc(dev);
  	if (crtc) {

  		const struct drm_display_mode *adjusted_mode;

  		int pixel_size = crtc->primary->fb->bits_per_pixel / 8;

  		int clock;
  
  		adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
  		clock = adjusted_mode->crtc_clock;

  
  		/* Display SR */
  		wm = intel_calculate_wm(clock, &pineview_display_wm,
  					pineview_display_wm.fifo_size,
  					pixel_size, latency->display_sr);
  		reg = I915_READ(DSPFW1);
  		reg &= ~DSPFW_SR_MASK;
  		reg |= wm << DSPFW_SR_SHIFT;
  		I915_WRITE(DSPFW1, reg);
  		DRM_DEBUG_KMS("DSPFW1 register is %x
  ", reg);
  
  		/* cursor SR */
  		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  					pineview_display_wm.fifo_size,
  					pixel_size, latency->cursor_sr);
  		reg = I915_READ(DSPFW3);
  		reg &= ~DSPFW_CURSOR_SR_MASK;
  		reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  		I915_WRITE(DSPFW3, reg);
  
  		/* Display HPLL off SR */
  		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  					pineview_display_hplloff_wm.fifo_size,
  					pixel_size, latency->display_hpll_disable);
  		reg = I915_READ(DSPFW3);
  		reg &= ~DSPFW_HPLL_SR_MASK;
  		reg |= wm & DSPFW_HPLL_SR_MASK;
  		I915_WRITE(DSPFW3, reg);
  
  		/* cursor HPLL off SR */
  		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  					pineview_display_hplloff_wm.fifo_size,
  					pixel_size, latency->cursor_hpll_disable);
  		reg = I915_READ(DSPFW3);
  		reg &= ~DSPFW_HPLL_CURSOR_MASK;
  		reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  		I915_WRITE(DSPFW3, reg);
  		DRM_DEBUG_KMS("DSPFW3 register is %x
  ", reg);

  		intel_set_memory_cxsr(dev_priv, true);

  	} else {

  		intel_set_memory_cxsr(dev_priv, false);

  	}
  }
  
  static bool g4x_compute_wm0(struct drm_device *dev,
  			    int plane,
  			    const struct intel_watermark_params *display,
  			    int display_latency_ns,
  			    const struct intel_watermark_params *cursor,
  			    int cursor_latency_ns,
  			    int *plane_wm,
  			    int *cursor_wm)
  {
  	struct drm_crtc *crtc;

  	const struct drm_display_mode *adjusted_mode;

  	int htotal, hdisplay, clock, pixel_size;
  	int line_time_us, line_count;
  	int entries, tlb_miss;
  
  	crtc = intel_get_crtc_for_plane(dev, plane);

  	if (!intel_crtc_active(crtc)) {

  		*cursor_wm = cursor->guard_size;
  		*plane_wm = display->guard_size;
  		return false;
  	}

  	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;

  	clock = adjusted_mode->crtc_clock;

  	htotal = adjusted_mode->crtc_htotal;

  	hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;

  	pixel_size = crtc->primary->fb->bits_per_pixel / 8;

  
  	/* Use the small buffer method to calculate plane watermark */
  	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  	if (tlb_miss > 0)
  		entries += tlb_miss;
  	entries = DIV_ROUND_UP(entries, display->cacheline_size);
  	*plane_wm = entries + display->guard_size;
  	if (*plane_wm > (int)display->max_wm)
  		*plane_wm = display->max_wm;
  
  	/* Use the large buffer method to calculate cursor watermark */

  	line_time_us = max(htotal * 1000 / clock, 1);

  	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;

  	entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;

  	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  	if (tlb_miss > 0)
  		entries += tlb_miss;
  	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  	*cursor_wm = entries + cursor->guard_size;
  	if (*cursor_wm > (int)cursor->max_wm)
  		*cursor_wm = (int)cursor->max_wm;
  
  	return true;
  }
  
  /*
   * Check the wm result.
   *
   * If any calculated watermark values is larger than the maximum value that
   * can be programmed into the associated watermark register, that watermark
   * must be disabled.
   */
  static bool g4x_check_srwm(struct drm_device *dev,
  			   int display_wm, int cursor_wm,
  			   const struct intel_watermark_params *display,
  			   const struct intel_watermark_params *cursor)
  {
  	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d
  ",
  		      display_wm, cursor_wm);
  
  	if (display_wm > display->max_wm) {
  		DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling
  ",
  			      display_wm, display->max_wm);
  		return false;
  	}
  
  	if (cursor_wm > cursor->max_wm) {
  		DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling
  ",
  			      cursor_wm, cursor->max_wm);
  		return false;
  	}
  
  	if (!(display_wm || cursor_wm)) {
  		DRM_DEBUG_KMS("SR latency is 0, disabling
  ");
  		return false;
  	}
  
  	return true;
  }
  
  static bool g4x_compute_srwm(struct drm_device *dev,
  			     int plane,
  			     int latency_ns,
  			     const struct intel_watermark_params *display,
  			     const struct intel_watermark_params *cursor,
  			     int *display_wm, int *cursor_wm)
  {
  	struct drm_crtc *crtc;

  	const struct drm_display_mode *adjusted_mode;

  	int hdisplay, htotal, pixel_size, clock;
  	unsigned long line_time_us;
  	int line_count, line_size;
  	int small, large;
  	int entries;
  
  	if (!latency_ns) {
  		*display_wm = *cursor_wm = 0;
  		return false;
  	}
  
  	crtc = intel_get_crtc_for_plane(dev, plane);

  	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;

  	clock = adjusted_mode->crtc_clock;

  	htotal = adjusted_mode->crtc_htotal;

  	hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;

  	pixel_size = crtc->primary->fb->bits_per_pixel / 8;

  	line_time_us = max(htotal * 1000 / clock, 1);

  	line_count = (latency_ns / line_time_us + 1000) / 1000;
  	line_size = hdisplay * pixel_size;
  
  	/* Use the minimum of the small and large buffer method for primary */
  	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  	large = line_count * line_size;
  
  	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  	*display_wm = entries + display->guard_size;
  
  	/* calculate the self-refresh watermark for display cursor */

  	entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;

  	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  	*cursor_wm = entries + cursor->guard_size;
  
  	return g4x_check_srwm(dev,
  			      *display_wm, *cursor_wm,
  			      display, cursor);
  }

  static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
  				      int pixel_size,
  				      int *prec_mult,
  				      int *drain_latency)

  {

  	int entries;

  	int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;

  	if (WARN(clock == 0, "Pixel clock is zero!
  "))

  		return false;

  	if (WARN(pixel_size == 0, "Pixel size is zero!
  "))
  		return false;

  	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;

  	*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
  				       DRAIN_LATENCY_PRECISION_32;
  	*drain_latency = (64 * (*prec_mult) * 4) / entries;

  	if (*drain_latency > DRAIN_LATENCY_MASK)
  		*drain_latency = DRAIN_LATENCY_MASK;

  
  	return true;
  }
  
  /*
   * Update drain latency registers of memory arbiter
   *
   * Valleyview SoC has a new memory arbiter and needs drain latency registers
   * to be programmed. Each plane has a drain latency multiplier and a drain
   * latency value.
   */

  static void vlv_update_drain_latency(struct drm_crtc *crtc)

  {

  	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  	int pixel_size;
  	int drain_latency;
  	enum pipe pipe = intel_crtc->pipe;
  	int plane_prec, prec_mult, plane_dl;

  	plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
  		   DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
  		   (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
  
  	if (!intel_crtc_active(crtc)) {
  		I915_WRITE(VLV_DDL(pipe), plane_dl);
  		return;
  	}

  	/* Primary plane Drain Latency */
  	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
  	if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
  		plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
  					   DDL_PLANE_PRECISION_64 :
  					   DDL_PLANE_PRECISION_32;
  		plane_dl |= plane_prec | drain_latency;

  	}

  	/* Cursor Drain Latency
  	 * BPP is always 4 for cursor
  	 */
  	pixel_size = 4;

  	/* Program cursor DL only if it is enabled */
  	if (intel_crtc->cursor_base &&
  	    vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
  		plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
  					   DDL_CURSOR_PRECISION_64 :
  					   DDL_CURSOR_PRECISION_32;
  		plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);

  	}

  
  	I915_WRITE(VLV_DDL(pipe), plane_dl);

  }
  
  #define single_plane_enabled(mask) is_power_of_2(mask)

  static void valleyview_update_wm(struct drm_crtc *crtc)

  {

  	struct drm_device *dev = crtc->dev;

  	static const int sr_latency_ns = 12000;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  	int plane_sr, cursor_sr;

  	int ignore_plane_sr, ignore_cursor_sr;

  	unsigned int enabled = 0;

  	bool cxsr_enabled;

  	vlv_update_drain_latency(crtc);

  	if (g4x_compute_wm0(dev, PIPE_A,

  			    &valleyview_wm_info, pessimal_latency_ns,
  			    &valleyview_cursor_wm_info, pessimal_latency_ns,

  			    &planea_wm, &cursora_wm))

  		enabled |= 1 << PIPE_A;

  	if (g4x_compute_wm0(dev, PIPE_B,

  			    &valleyview_wm_info, pessimal_latency_ns,
  			    &valleyview_cursor_wm_info, pessimal_latency_ns,

  			    &planeb_wm, &cursorb_wm))

  		enabled |= 1 << PIPE_B;

  	if (single_plane_enabled(enabled) &&
  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
  			     sr_latency_ns,
  			     &valleyview_wm_info,
  			     &valleyview_cursor_wm_info,

  			     &plane_sr, &ignore_cursor_sr) &&
  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
  			     2*sr_latency_ns,
  			     &valleyview_wm_info,
  			     &valleyview_cursor_wm_info,

  			     &ignore_plane_sr, &cursor_sr)) {

  		cxsr_enabled = true;

  	} else {

  		cxsr_enabled = false;

  		intel_set_memory_cxsr(dev_priv, false);

  		plane_sr = cursor_sr = 0;
  	}

  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
  		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d
  ",

  		      planea_wm, cursora_wm,
  		      planeb_wm, cursorb_wm,
  		      plane_sr, cursor_sr);
  
  	I915_WRITE(DSPFW1,
  		   (plane_sr << DSPFW_SR_SHIFT) |
  		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  		   (planeb_wm << DSPFW_PLANEB_SHIFT) |

  		   (planea_wm << DSPFW_PLANEA_SHIFT));

  	I915_WRITE(DSPFW2,

  		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |

  		   (cursora_wm << DSPFW_CURSORA_SHIFT));
  	I915_WRITE(DSPFW3,

  		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
  		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));

  
  	if (cxsr_enabled)
  		intel_set_memory_cxsr(dev_priv, true);

  }

  static void cherryview_update_wm(struct drm_crtc *crtc)
  {
  	struct drm_device *dev = crtc->dev;
  	static const int sr_latency_ns = 12000;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	int planea_wm, planeb_wm, planec_wm;
  	int cursora_wm, cursorb_wm, cursorc_wm;
  	int plane_sr, cursor_sr;
  	int ignore_plane_sr, ignore_cursor_sr;
  	unsigned int enabled = 0;
  	bool cxsr_enabled;
  
  	vlv_update_drain_latency(crtc);
  
  	if (g4x_compute_wm0(dev, PIPE_A,

  			    &valleyview_wm_info, pessimal_latency_ns,
  			    &valleyview_cursor_wm_info, pessimal_latency_ns,

  			    &planea_wm, &cursora_wm))
  		enabled |= 1 << PIPE_A;
  
  	if (g4x_compute_wm0(dev, PIPE_B,

  			    &valleyview_wm_info, pessimal_latency_ns,
  			    &valleyview_cursor_wm_info, pessimal_latency_ns,

  			    &planeb_wm, &cursorb_wm))
  		enabled |= 1 << PIPE_B;
  
  	if (g4x_compute_wm0(dev, PIPE_C,

  			    &valleyview_wm_info, pessimal_latency_ns,
  			    &valleyview_cursor_wm_info, pessimal_latency_ns,

  			    &planec_wm, &cursorc_wm))
  		enabled |= 1 << PIPE_C;
  
  	if (single_plane_enabled(enabled) &&
  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
  			     sr_latency_ns,
  			     &valleyview_wm_info,
  			     &valleyview_cursor_wm_info,
  			     &plane_sr, &ignore_cursor_sr) &&
  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
  			     2*sr_latency_ns,
  			     &valleyview_wm_info,
  			     &valleyview_cursor_wm_info,
  			     &ignore_plane_sr, &cursor_sr)) {
  		cxsr_enabled = true;
  	} else {
  		cxsr_enabled = false;
  		intel_set_memory_cxsr(dev_priv, false);
  		plane_sr = cursor_sr = 0;
  	}
  
  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
  		      "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
  		      "SR: plane=%d, cursor=%d
  ",
  		      planea_wm, cursora_wm,
  		      planeb_wm, cursorb_wm,
  		      planec_wm, cursorc_wm,
  		      plane_sr, cursor_sr);
  
  	I915_WRITE(DSPFW1,
  		   (plane_sr << DSPFW_SR_SHIFT) |
  		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
  		   (planea_wm << DSPFW_PLANEA_SHIFT));
  	I915_WRITE(DSPFW2,
  		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
  		   (cursora_wm << DSPFW_CURSORA_SHIFT));
  	I915_WRITE(DSPFW3,
  		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
  		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  	I915_WRITE(DSPFW9_CHV,
  		   (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
  					      DSPFW_CURSORC_MASK)) |
  		   (planec_wm << DSPFW_PLANEC_SHIFT) |
  		   (cursorc_wm << DSPFW_CURSORC_SHIFT));
  
  	if (cxsr_enabled)
  		intel_set_memory_cxsr(dev_priv, true);
  }

  static void valleyview_update_sprite_wm(struct drm_plane *plane,
  					struct drm_crtc *crtc,
  					uint32_t sprite_width,
  					uint32_t sprite_height,
  					int pixel_size,
  					bool enabled, bool scaled)
  {
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	int pipe = to_intel_plane(plane)->pipe;
  	int sprite = to_intel_plane(plane)->plane;
  	int drain_latency;
  	int plane_prec;
  	int sprite_dl;
  	int prec_mult;
  
  	sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
  		    (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
  
  	if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
  						 &drain_latency)) {
  		plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
  					   DDL_SPRITE_PRECISION_64(sprite) :
  					   DDL_SPRITE_PRECISION_32(sprite);
  		sprite_dl |= plane_prec |
  			     (drain_latency << DDL_SPRITE_SHIFT(sprite));
  	}
  
  	I915_WRITE(VLV_DDL(pipe), sprite_dl);
  }

  static void g4x_update_wm(struct drm_crtc *crtc)

  {

  	struct drm_device *dev = crtc->dev;

  	static const int sr_latency_ns = 12000;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  	int plane_sr, cursor_sr;
  	unsigned int enabled = 0;

  	bool cxsr_enabled;

  	if (g4x_compute_wm0(dev, PIPE_A,

  			    &g4x_wm_info, pessimal_latency_ns,
  			    &g4x_cursor_wm_info, pessimal_latency_ns,

  			    &planea_wm, &cursora_wm))

  		enabled |= 1 << PIPE_A;

  	if (g4x_compute_wm0(dev, PIPE_B,

  			    &g4x_wm_info, pessimal_latency_ns,
  			    &g4x_cursor_wm_info, pessimal_latency_ns,

  			    &planeb_wm, &cursorb_wm))

  		enabled |= 1 << PIPE_B;

  	if (single_plane_enabled(enabled) &&
  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
  			     sr_latency_ns,
  			     &g4x_wm_info,
  			     &g4x_cursor_wm_info,

  			     &plane_sr, &cursor_sr)) {

  		cxsr_enabled = true;

  	} else {

  		cxsr_enabled = false;

  		intel_set_memory_cxsr(dev_priv, false);

  		plane_sr = cursor_sr = 0;
  	}

  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
  		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d
  ",

  		      planea_wm, cursora_wm,
  		      planeb_wm, cursorb_wm,
  		      plane_sr, cursor_sr);
  
  	I915_WRITE(DSPFW1,
  		   (plane_sr << DSPFW_SR_SHIFT) |
  		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  		   (planeb_wm << DSPFW_PLANEB_SHIFT) |

  		   (planea_wm << DSPFW_PLANEA_SHIFT));

  	I915_WRITE(DSPFW2,

  		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |

  		   (cursora_wm << DSPFW_CURSORA_SHIFT));
  	/* HPLL off in SR has some issues on G4x... disable it */
  	I915_WRITE(DSPFW3,

  		   (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |

  		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));

  
  	if (cxsr_enabled)
  		intel_set_memory_cxsr(dev_priv, true);

  }

  static void i965_update_wm(struct drm_crtc *unused_crtc)

  {

  	struct drm_device *dev = unused_crtc->dev;

  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct drm_crtc *crtc;
  	int srwm = 1;
  	int cursor_sr = 16;

  	bool cxsr_enabled;

  
  	/* Calc sr entries for one plane configs */
  	crtc = single_enabled_crtc(dev);
  	if (crtc) {
  		/* self-refresh has much higher latency */
  		static const int sr_latency_ns = 12000;

  		const struct drm_display_mode *adjusted_mode =
  			&to_intel_crtc(crtc)->config.adjusted_mode;

  		int clock = adjusted_mode->crtc_clock;

  		int htotal = adjusted_mode->crtc_htotal;

  		int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;

  		int pixel_size = crtc->primary->fb->bits_per_pixel / 8;

  		unsigned long line_time_us;
  		int entries;

  		line_time_us = max(htotal * 1000 / clock, 1);

  
  		/* Use ns/us then divide to preserve precision */
  		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  			pixel_size * hdisplay;
  		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  		srwm = I965_FIFO_SIZE - entries;
  		if (srwm < 0)
  			srwm = 1;
  		srwm &= 0x1ff;
  		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d
  ",
  			      entries, srwm);
  
  		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

  			pixel_size * to_intel_crtc(crtc)->cursor_width;

  		entries = DIV_ROUND_UP(entries,
  					  i965_cursor_wm_info.cacheline_size);
  		cursor_sr = i965_cursor_wm_info.fifo_size -
  			(entries + i965_cursor_wm_info.guard_size);
  
  		if (cursor_sr > i965_cursor_wm_info.max_wm)
  			cursor_sr = i965_cursor_wm_info.max_wm;
  
  		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  			      "cursor %d
  ", srwm, cursor_sr);

  		cxsr_enabled = true;

  	} else {

  		cxsr_enabled = false;

  		/* Turn off self refresh if both pipes are enabled */

  		intel_set_memory_cxsr(dev_priv, false);

  	}
  
  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d
  ",
  		      srwm);
  
  	/* 965 has limitations... */
  	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |

  		   (8 << DSPFW_CURSORB_SHIFT) |
  		   (8 << DSPFW_PLANEB_SHIFT) |
  		   (8 << DSPFW_PLANEA_SHIFT));
  	I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
  		   (8 << DSPFW_PLANEC_SHIFT_OLD));

  	/* update cursor SR watermark */
  	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));

  
  	if (cxsr_enabled)
  		intel_set_memory_cxsr(dev_priv, true);

  }

  static void i9xx_update_wm(struct drm_crtc *unused_crtc)

  {

  	struct drm_device *dev = unused_crtc->dev;

  	struct drm_i915_private *dev_priv = dev->dev_private;
  	const struct intel_watermark_params *wm_info;
  	uint32_t fwater_lo;
  	uint32_t fwater_hi;
  	int cwm, srwm = 1;
  	int fifo_size;
  	int planea_wm, planeb_wm;
  	struct drm_crtc *crtc, *enabled = NULL;
  
  	if (IS_I945GM(dev))
  		wm_info = &i945_wm_info;
  	else if (!IS_GEN2(dev))
  		wm_info = &i915_wm_info;
  	else

  		wm_info = &i830_a_wm_info;

  
  	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  	crtc = intel_get_crtc_for_plane(dev, 0);

  	if (intel_crtc_active(crtc)) {

  		const struct drm_display_mode *adjusted_mode;

  		int cpp = crtc->primary->fb->bits_per_pixel / 8;

  		if (IS_GEN2(dev))
  			cpp = 4;

  		adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
  		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,

  					       wm_info, fifo_size, cpp,

  					       pessimal_latency_ns);

  		enabled = crtc;

  	} else {

  		planea_wm = fifo_size - wm_info->guard_size;

  		if (planea_wm > (long)wm_info->max_wm)
  			planea_wm = wm_info->max_wm;
  	}
  
  	if (IS_GEN2(dev))
  		wm_info = &i830_bc_wm_info;

  
  	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  	crtc = intel_get_crtc_for_plane(dev, 1);

  	if (intel_crtc_active(crtc)) {

  		const struct drm_display_mode *adjusted_mode;

  		int cpp = crtc->primary->fb->bits_per_pixel / 8;

  		if (IS_GEN2(dev))
  			cpp = 4;

  		adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
  		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,

  					       wm_info, fifo_size, cpp,

  					       pessimal_latency_ns);

  		if (enabled == NULL)
  			enabled = crtc;
  		else
  			enabled = NULL;

  	} else {

  		planeb_wm = fifo_size - wm_info->guard_size;

  		if (planeb_wm > (long)wm_info->max_wm)
  			planeb_wm = wm_info->max_wm;
  	}

  
  	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d
  ", planea_wm, planeb_wm);

  	if (IS_I915GM(dev) && enabled) {

  		struct drm_i915_gem_object *obj;

  		obj = intel_fb_obj(enabled->primary->fb);

  
  		/* self-refresh seems busted with untiled */

  		if (obj->tiling_mode == I915_TILING_NONE)

  			enabled = NULL;
  	}

  	/*
  	 * Overlay gets an aggressive default since video jitter is bad.
  	 */
  	cwm = 2;
  
  	/* Play safe and disable self-refresh before adjusting watermarks. */

  	intel_set_memory_cxsr(dev_priv, false);

  
  	/* Calc sr entries for one plane configs */
  	if (HAS_FW_BLC(dev) && enabled) {
  		/* self-refresh has much higher latency */
  		static const int sr_latency_ns = 6000;

  		const struct drm_display_mode *adjusted_mode =
  			&to_intel_crtc(enabled)->config.adjusted_mode;

  		int clock = adjusted_mode->crtc_clock;

  		int htotal = adjusted_mode->crtc_htotal;

  		int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;

  		int pixel_size = enabled->primary->fb->bits_per_pixel / 8;

  		unsigned long line_time_us;
  		int entries;

  		line_time_us = max(htotal * 1000 / clock, 1);

  
  		/* Use ns/us then divide to preserve precision */
  		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  			pixel_size * hdisplay;
  		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  		DRM_DEBUG_KMS("self-refresh entries: %d
  ", entries);
  		srwm = wm_info->fifo_size - entries;
  		if (srwm < 0)
  			srwm = 1;
  
  		if (IS_I945G(dev) || IS_I945GM(dev))
  			I915_WRITE(FW_BLC_SELF,
  				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  		else if (IS_I915GM(dev))
  			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  	}
  
  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d
  ",
  		      planea_wm, planeb_wm, cwm, srwm);
  
  	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  	fwater_hi = (cwm & 0x1f);
  
  	/* Set request length to 8 cachelines per fetch */
  	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  	fwater_hi = fwater_hi | (1 << 8);
  
  	I915_WRITE(FW_BLC, fwater_lo);
  	I915_WRITE(FW_BLC2, fwater_hi);

  	if (enabled)
  		intel_set_memory_cxsr(dev_priv, true);

  }

  static void i845_update_wm(struct drm_crtc *unused_crtc)

  {

  	struct drm_device *dev = unused_crtc->dev;

  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct drm_crtc *crtc;

  	const struct drm_display_mode *adjusted_mode;

  	uint32_t fwater_lo;
  	int planea_wm;
  
  	crtc = single_enabled_crtc(dev);
  	if (crtc == NULL)
  		return;

  	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
  	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,

  				       &i845_wm_info,

  				       dev_priv->display.get_fifo_size(dev, 0),

  				       4, pessimal_latency_ns);

  	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  	fwater_lo |= (3<<8) | planea_wm;
  
  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d
  ", planea_wm);
  
  	I915_WRITE(FW_BLC, fwater_lo);
  }

  static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
  				    struct drm_crtc *crtc)

  {
  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

  	uint32_t pixel_rate;

  	pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;

  
  	/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
  	 * adjust the pixel_rate here. */

  	if (intel_crtc->config.pch_pfit.enabled) {

  		uint64_t pipe_w, pipe_h, pfit_w, pfit_h;

  		uint32_t pfit_size = intel_crtc->config.pch_pfit.size;

  		pipe_w = intel_crtc->config.pipe_src_w;
  		pipe_h = intel_crtc->config.pipe_src_h;

  		pfit_w = (pfit_size >> 16) & 0xFFFF;
  		pfit_h = pfit_size & 0xFFFF;
  		if (pipe_w < pfit_w)
  			pipe_w = pfit_w;
  		if (pipe_h < pfit_h)
  			pipe_h = pfit_h;
  
  		pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
  				     pfit_w * pfit_h);
  	}
  
  	return pixel_rate;
  }

  /* latency must be in 0.1us units. */

  static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,

  			       uint32_t latency)
  {
  	uint64_t ret;

  	if (WARN(latency == 0, "Latency value missing
  "))
  		return UINT_MAX;

  	ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
  	ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
  
  	return ret;
  }

  /* latency must be in 0.1us units. */

  static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,

  			       uint32_t horiz_pixels, uint8_t bytes_per_pixel,
  			       uint32_t latency)
  {
  	uint32_t ret;

  	if (WARN(latency == 0, "Latency value missing
  "))
  		return UINT_MAX;

  	ret = (latency * pixel_rate) / (pipe_htotal * 10000);
  	ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
  	ret = DIV_ROUND_UP(ret, 64) + 2;
  	return ret;
  }

  static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,

  			   uint8_t bytes_per_pixel)
  {
  	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
  }

  struct ilk_pipe_wm_parameters {

  	bool active;

  	uint32_t pipe_htotal;
  	uint32_t pixel_rate;

  	struct intel_plane_wm_parameters pri;
  	struct intel_plane_wm_parameters spr;
  	struct intel_plane_wm_parameters cur;

  };

  struct ilk_wm_maximums {

  	uint16_t pri;
  	uint16_t spr;
  	uint16_t cur;
  	uint16_t fbc;
  };

  /* used in computing the new watermarks state */
  struct intel_wm_config {
  	unsigned int num_pipes_active;
  	bool sprites_enabled;
  	bool sprites_scaled;

  };

  /*
   * For both WM_PIPE and WM_LP.
   * mem_value must be in 0.1us units.
   */

  static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,

  				   uint32_t mem_value,
  				   bool is_lp)

  {

  	uint32_t method1, method2;

  	if (!params->active || !params->pri.enabled)

  		return 0;

  	method1 = ilk_wm_method1(params->pixel_rate,

  				 params->pri.bytes_per_pixel,

  				 mem_value);
  
  	if (!is_lp)
  		return method1;

  	method2 = ilk_wm_method2(params->pixel_rate,

  				 params->pipe_htotal,

  				 params->pri.horiz_pixels,
  				 params->pri.bytes_per_pixel,

  				 mem_value);
  
  	return min(method1, method2);

  }

  /*
   * For both WM_PIPE and WM_LP.
   * mem_value must be in 0.1us units.
   */

  static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,

  				   uint32_t mem_value)
  {
  	uint32_t method1, method2;

  	if (!params->active || !params->spr.enabled)

  		return 0;

  	method1 = ilk_wm_method1(params->pixel_rate,

  				 params->spr.bytes_per_pixel,

  				 mem_value);

  	method2 = ilk_wm_method2(params->pixel_rate,

  				 params->pipe_htotal,

  				 params->spr.horiz_pixels,
  				 params->spr.bytes_per_pixel,

  				 mem_value);
  	return min(method1, method2);
  }

  /*
   * For both WM_PIPE and WM_LP.
   * mem_value must be in 0.1us units.
   */

  static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,

  				   uint32_t mem_value)
  {

  	if (!params->active || !params->cur.enabled)

  		return 0;

  	return ilk_wm_method2(params->pixel_rate,

  			      params->pipe_htotal,

  			      params->cur.horiz_pixels,
  			      params->cur.bytes_per_pixel,

  			      mem_value);
  }

  /* Only for WM_LP. */

  static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,

  				   uint32_t pri_val)

  {

  	if (!params->active || !params->pri.enabled)

  		return 0;

  	return ilk_wm_fbc(pri_val,

  			  params->pri.horiz_pixels,
  			  params->pri.bytes_per_pixel);

  }

  static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
  {

  	if (INTEL_INFO(dev)->gen >= 8)
  		return 3072;
  	else if (INTEL_INFO(dev)->gen >= 7)

  		return 768;
  	else
  		return 512;
  }

  static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
  					 int level, bool is_sprite)
  {
  	if (INTEL_INFO(dev)->gen >= 8)
  		/* BDW primary/sprite plane watermarks */
  		return level == 0 ? 255 : 2047;
  	else if (INTEL_INFO(dev)->gen >= 7)
  		/* IVB/HSW primary/sprite plane watermarks */
  		return level == 0 ? 127 : 1023;
  	else if (!is_sprite)
  		/* ILK/SNB primary plane watermarks */
  		return level == 0 ? 127 : 511;
  	else
  		/* ILK/SNB sprite plane watermarks */
  		return level == 0 ? 63 : 255;
  }
  
  static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
  					  int level)
  {
  	if (INTEL_INFO(dev)->gen >= 7)
  		return level == 0 ? 63 : 255;
  	else
  		return level == 0 ? 31 : 63;
  }
  
  static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
  {
  	if (INTEL_INFO(dev)->gen >= 8)
  		return 31;
  	else
  		return 15;
  }

  /* Calculate the maximum primary/sprite plane watermark */
  static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
  				     int level,

  				     const struct intel_wm_config *config,

  				     enum intel_ddb_partitioning ddb_partitioning,
  				     bool is_sprite)
  {
  	unsigned int fifo_size = ilk_display_fifo_size(dev);

  
  	/* if sprites aren't enabled, sprites get nothing */

  	if (is_sprite && !config->sprites_enabled)

  		return 0;
  
  	/* HSW allows LP1+ watermarks even with multiple pipes */

  	if (level == 0 || config->num_pipes_active > 1) {

  		fifo_size /= INTEL_INFO(dev)->num_pipes;
  
  		/*
  		 * For some reason the non self refresh
  		 * FIFO size is only half of the self
  		 * refresh FIFO size on ILK/SNB.
  		 */
  		if (INTEL_INFO(dev)->gen <= 6)
  			fifo_size /= 2;
  	}

  	if (config->sprites_enabled) {

  		/* level 0 is always calculated with 1:1 split */
  		if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
  			if (is_sprite)
  				fifo_size *= 5;
  			fifo_size /= 6;
  		} else {
  			fifo_size /= 2;
  		}
  	}
  
  	/* clamp to max that the registers can hold */

  	return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));

  }
  
  /* Calculate the maximum cursor plane watermark */
  static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,

  				      int level,
  				      const struct intel_wm_config *config)

  {
  	/* HSW LP1+ watermarks w/ multiple pipes */

  	if (level > 0 && config->num_pipes_active > 1)

  		return 64;
  
  	/* otherwise just report max that registers can hold */

  	return ilk_cursor_wm_reg_max(dev, level);

  }

  static void ilk_compute_wm_maximums(const struct drm_device *dev,

  				    int level,
  				    const struct intel_wm_config *config,
  				    enum intel_ddb_partitioning ddb_partitioning,

  				    struct ilk_wm_maximums *max)

  {

  	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
  	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
  	max->cur = ilk_cursor_wm_max(dev, level, config);

  	max->fbc = ilk_fbc_wm_reg_max(dev);

  }

  static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
  					int level,
  					struct ilk_wm_maximums *max)
  {
  	max->pri = ilk_plane_wm_reg_max(dev, level, false);
  	max->spr = ilk_plane_wm_reg_max(dev, level, true);
  	max->cur = ilk_cursor_wm_reg_max(dev, level);
  	max->fbc = ilk_fbc_wm_reg_max(dev);
  }

  static bool ilk_validate_wm_level(int level,

  				  const struct ilk_wm_maximums *max,

  				  struct intel_wm_level *result)

  {
  	bool ret;
  
  	/* already determined to be invalid? */
  	if (!result->enable)
  		return false;
  
  	result->enable = result->pri_val <= max->pri &&
  			 result->spr_val <= max->spr &&
  			 result->cur_val <= max->cur;
  
  	ret = result->enable;
  
  	/*
  	 * HACK until we can pre-compute everything,
  	 * and thus fail gracefully if LP0 watermarks
  	 * are exceeded...
  	 */
  	if (level == 0 && !result->enable) {
  		if (result->pri_val > max->pri)
  			DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)
  ",
  				      level, result->pri_val, max->pri);
  		if (result->spr_val > max->spr)
  			DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)
  ",
  				      level, result->spr_val, max->spr);
  		if (result->cur_val > max->cur)
  			DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)
  ",
  				      level, result->cur_val, max->cur);
  
  		result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
  		result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
  		result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
  		result->enable = true;
  	}

  	return ret;
  }

  static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,

  				 int level,

  				 const struct ilk_pipe_wm_parameters *p,

  				 struct intel_wm_level *result)

  {
  	uint16_t pri_latency = dev_priv->wm.pri_latency[level];
  	uint16_t spr_latency = dev_priv->wm.spr_latency[level];
  	uint16_t cur_latency = dev_priv->wm.cur_latency[level];
  
  	/* WM1+ latency values stored in 0.5us units */
  	if (level > 0) {
  		pri_latency *= 5;
  		spr_latency *= 5;
  		cur_latency *= 5;
  	}
  
  	result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
  	result->spr_val = ilk_compute_spr_wm(p, spr_latency);
  	result->cur_val = ilk_compute_cur_wm(p, cur_latency);
  	result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
  	result->enable = true;
  }

  static uint32_t
  hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)

  {
  	struct drm_i915_private *dev_priv = dev->dev_private;

  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

  	struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;

  	u32 linetime, ips_linetime;

  	if (!intel_crtc_active(crtc))
  		return 0;

  	/* The WM are computed with base on how long it takes to fill a single
  	 * row at the given clock rate, multiplied by 8.
  	 * */

  	linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
  				     mode->crtc_clock);
  	ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,

  					 intel_ddi_get_cdclk_freq(dev_priv));

  	return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
  	       PIPE_WM_LINETIME_TIME(linetime);

  }