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include/asm-arm/locks.h
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/*
* linux/include/asm-arm/locks.h
*
* Copyright (C) 2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Interrupt safe locking assembler.
*/
#ifndef __ASM_PROC_LOCKS_H
#define __ASM_PROC_LOCKS_H
#if __LINUX_ARM_ARCH__ >= 6
#define __down_op(ptr,fail) \
({ \
__asm__ __volatile__( \
"@ down_op
" \
"1: ldrex lr, [%0]
" \
" sub lr, lr, %1
" \
" strex ip, lr, [%0]
" \
" teq ip, #0
" \
" bne 1b
" \
" teq lr, #0
" \
" movmi ip, %0
" \
" blmi " #fail \
: \
: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \ smp_mb(); \ |
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})
#define __down_op_ret(ptr,fail) \
({ \
unsigned int ret; \
__asm__ __volatile__( \
"@ down_op_ret
" \
"1: ldrex lr, [%1]
" \
" sub lr, lr, %2
" \
" strex ip, lr, [%1]
" \
" teq ip, #0
" \
" bne 1b
" \
" teq lr, #0
" \
" movmi ip, %1
" \
" movpl ip, #0
" \
" blmi " #fail "
" \
" mov %0, ip" \
: "=&r" (ret) \
: "r" (ptr), "I" (1) \
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ret; \
})
#define __up_op(ptr,wake) \
({ \
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__asm__ __volatile__( \ "@ up_op " \ "1: ldrex lr, [%0] " \ " add lr, lr, %1 " \ " strex ip, lr, [%0] " \ " teq ip, #0 " \ " bne 1b " \ |
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" cmp lr, #0 " \ |
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" movle ip, %0 " \ " blle " #wake \ : \ : "r" (ptr), "I" (1) \ |
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: "ip", "lr", "cc"); \ |
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})
/*
* The value 0x01000000 supports up to 128 processors and
* lots of processes. BIAS must be chosen such that sub'ing
* BIAS once per CPU will result in the long remaining
* negative.
*/
#define RW_LOCK_BIAS 0x01000000
#define RW_LOCK_BIAS_STR "0x01000000"
#define __down_op_write(ptr,fail) \
({ \
__asm__ __volatile__( \
"@ down_op_write
" \
"1: ldrex lr, [%0]
" \
" sub lr, lr, %1
" \
" strex ip, lr, [%0]
" \
" teq ip, #0
" \
" bne 1b
" \
" teq lr, #0
" \
" movne ip, %0
" \
" blne " #fail \
: \
: "r" (ptr), "I" (RW_LOCK_BIAS) \
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})
#define __up_op_write(ptr,wake) \
({ \
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__asm__ __volatile__( \ |
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"@ up_op_write " \ |
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"1: ldrex lr, [%0] " \ |
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" adds lr, lr, %1 " \ |
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" strex ip, lr, [%0] " \ " teq ip, #0 " \ " bne 1b " \ " movcs ip, %0 " \ " blcs " #wake \ : \ : "r" (ptr), "I" (RW_LOCK_BIAS) \ |
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})
#define __down_op_read(ptr,fail) \
__down_op(ptr, fail)
#define __up_op_read(ptr,wake) \
({ \
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__asm__ __volatile__( \ "@ up_op_read " \ "1: ldrex lr, [%0] " \ " add lr, lr, %1 " \ " strex ip, lr, [%0] " \ " teq ip, #0 " \ " bne 1b " \ " teq lr, #0 " \ " moveq ip, %0 " \ " bleq " #wake \ : \ : "r" (ptr), "I" (1) \ |
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})
#else
#define __down_op(ptr,fail) \
({ \
__asm__ __volatile__( \
"@ down_op
" \
" mrs ip, cpsr
" \
" orr lr, ip, #128
" \
" msr cpsr_c, lr
" \
" ldr lr, [%0]
" \
" subs lr, lr, %1
" \
" str lr, [%0]
" \
" msr cpsr_c, ip
" \
" movmi ip, %0
" \
" blmi " #fail \
: \
: "r" (ptr), "I" (1) \
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})
#define __down_op_ret(ptr,fail) \
({ \
unsigned int ret; \
__asm__ __volatile__( \
"@ down_op_ret
" \
" mrs ip, cpsr
" \
" orr lr, ip, #128
" \
" msr cpsr_c, lr
" \
" ldr lr, [%1]
" \
" subs lr, lr, %2
" \
" str lr, [%1]
" \
" msr cpsr_c, ip
" \
" movmi ip, %1
" \
" movpl ip, #0
" \
" blmi " #fail "
" \
" mov %0, ip" \
: "=&r" (ret) \
: "r" (ptr), "I" (1) \
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ret; \
})
#define __up_op(ptr,wake) \
({ \
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__asm__ __volatile__( \ "@ up_op " \ " mrs ip, cpsr " \ " orr lr, ip, #128 " \ " msr cpsr_c, lr " \ " ldr lr, [%0] " \ " adds lr, lr, %1 " \ " str lr, [%0] " \ " msr cpsr_c, ip " \ " movle ip, %0 " \ " blle " #wake \ : \ : "r" (ptr), "I" (1) \ |
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})
/*
* The value 0x01000000 supports up to 128 processors and
* lots of processes. BIAS must be chosen such that sub'ing
* BIAS once per CPU will result in the long remaining
* negative.
*/
#define RW_LOCK_BIAS 0x01000000
#define RW_LOCK_BIAS_STR "0x01000000"
#define __down_op_write(ptr,fail) \
({ \
__asm__ __volatile__( \
"@ down_op_write
" \
" mrs ip, cpsr
" \
" orr lr, ip, #128
" \
" msr cpsr_c, lr
" \
" ldr lr, [%0]
" \
" subs lr, lr, %1
" \
" str lr, [%0]
" \
" msr cpsr_c, ip
" \
" movne ip, %0
" \
" blne " #fail \
: \
: "r" (ptr), "I" (RW_LOCK_BIAS) \
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})
#define __up_op_write(ptr,wake) \
({ \
__asm__ __volatile__( \
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" mrs ip, cpsr " \ " orr lr, ip, #128 " \ " msr cpsr_c, lr " \ " ldr lr, [%0] " \ " adds lr, lr, %1 " \ " str lr, [%0] " \ " msr cpsr_c, ip " \ " movcs ip, %0 " \ " blcs " #wake \ : \ : "r" (ptr), "I" (RW_LOCK_BIAS) \ |
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})
#define __down_op_read(ptr,fail) \
__down_op(ptr, fail)
#define __up_op_read(ptr,wake) \
({ \
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__asm__ __volatile__( \ "@ up_op_read " \ " mrs ip, cpsr " \ " orr lr, ip, #128 " \ " msr cpsr_c, lr " \ " ldr lr, [%0] " \ " adds lr, lr, %1 " \ " str lr, [%0] " \ " msr cpsr_c, ip " \ " moveq ip, %0 " \ " bleq " #wake \ : \ : "r" (ptr), "I" (1) \ |
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}) #endif #endif |