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drivers/ide/scc_pata.c
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bde18a2e1 drivers/ide: PATA... |
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/* * Support for IDE interfaces on Celleb platform * * (C) Copyright 2006 TOSHIBA CORPORATION * * This code is based on drivers/ide/pci/siimage.c: * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
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* Copyright (C) 2003 Red Hat |
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* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #include <linux/types.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/delay.h> |
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#include <linux/ide.h> #include <linux/init.h> #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 #define SCC_PATA_NAME "scc IDE" #define TDVHSEL_MASTER 0x00000001 #define TDVHSEL_SLAVE 0x00000004 #define MODE_JCUSFEN 0x00000080 #define CCKCTRL_ATARESET 0x00040000 #define CCKCTRL_BUFCNT 0x00020000 #define CCKCTRL_CRST 0x00010000 #define CCKCTRL_OCLKEN 0x00000100 #define CCKCTRL_ATACLKOEN 0x00000002 #define CCKCTRL_LCLKEN 0x00000001 #define QCHCD_IOS_SS 0x00000001 #define QCHSD_STPDIAG 0x00020000 #define INTMASK_MSK 0xD1000012 #define INTSTS_SERROR 0x80000000 #define INTSTS_PRERR 0x40000000 #define INTSTS_RERR 0x10000000 #define INTSTS_ICERR 0x01000000 #define INTSTS_BMSINT 0x00000010 #define INTSTS_BMHE 0x00000008 #define INTSTS_IOIRQS 0x00000004 #define INTSTS_INTRQ 0x00000002 #define INTSTS_ACTEINT 0x00000001 #define ECMODE_VALUE 0x01 static struct scc_ports { unsigned long ctl, dma; |
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struct ide_host *host; /* for removing port from system */ |
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} scc_ports[MAX_HWIFS]; /* PIO transfer mode table */ /* JCHST */ static unsigned long JCHSTtbl[2][7] = { {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ }; /* JCHHT */ static unsigned long JCHHTtbl[2][7] = { {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ }; /* JCHCT */ static unsigned long JCHCTtbl[2][7] = { {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ }; /* DMA transfer mode table */ /* JCHDCTM/JCHDCTS */ static unsigned long JCHDCTxtbl[2][7] = { {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ }; /* JCSTWTM/JCSTWTS */ static unsigned long JCSTWTxtbl[2][7] = { {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ }; /* JCTSS */ static unsigned long JCTSStbl[2][7] = { {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ }; /* JCENVT */ static unsigned long JCENVTtbl[2][7] = { {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ }; /* JCACTSELS/JCACTSELM */ static unsigned long JCACTSELtbl[2][7] = { {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ }; static u8 scc_ide_inb(unsigned long port) { u32 data = in_be32((void*)port); return (u8)data; } |
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static void scc_exec_command(ide_hwif_t *hwif, u8 cmd) { out_be32((void *)hwif->io_ports.command_addr, cmd); eieio(); in_be32((void *)(hwif->dma_base + 0x01c)); eieio(); } |
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static u8 scc_read_status(ide_hwif_t *hwif) { return (u8)in_be32((void *)hwif->io_ports.status_addr); } |
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static u8 scc_read_altstatus(ide_hwif_t *hwif) { return (u8)in_be32((void *)hwif->io_ports.ctl_addr); } |
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static u8 scc_dma_sff_read_status(ide_hwif_t *hwif) |
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{ |
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return (u8)in_be32((void *)(hwif->dma_base + 4)); |
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} |
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static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl) |
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{ |
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out_be32((void *)hwif->io_ports.ctl_addr, ctl); eieio(); in_be32((void *)(hwif->dma_base + 0x01c)); eieio(); } |
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static void scc_ide_insw(unsigned long port, void *addr, u32 count) { u16 *ptr = (u16 *)addr; while (count--) { *ptr++ = le16_to_cpu(in_be32((void*)port)); } } static void scc_ide_insl(unsigned long port, void *addr, u32 count) { u16 *ptr = (u16 *)addr; while (count--) { *ptr++ = le16_to_cpu(in_be32((void*)port)); *ptr++ = le16_to_cpu(in_be32((void*)port)); } } static void scc_ide_outb(u8 addr, unsigned long port) { out_be32((void*)port, addr); } |
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static void scc_ide_outsw(unsigned long port, void *addr, u32 count) { u16 *ptr = (u16 *)addr; while (count--) { out_be32((void*)port, cpu_to_le16(*ptr++)); } } static void scc_ide_outsl(unsigned long port, void *addr, u32 count) { u16 *ptr = (u16 *)addr; while (count--) { out_be32((void*)port, cpu_to_le16(*ptr++)); out_be32((void*)port, cpu_to_le16(*ptr++)); } } /** |
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* scc_set_pio_mode - set host controller for PIO mode |
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* @hwif: port |
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* @drive: drive |
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* * Load the timing settings for this device mode into the * controller. */ |
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static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct scc_ports *ports = ide_get_hwifdata(hwif); unsigned long ctl_base = ports->ctl; unsigned long cckctrl_port = ctl_base + 0xff0; unsigned long piosht_port = ctl_base + 0x000; unsigned long pioct_port = ctl_base + 0x004; unsigned long reg; |
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int offset; |
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const u8 pio = drive->pio_mode - XFER_PIO_0; |
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reg = in_be32((void __iomem *)cckctrl_port); |
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if (reg & CCKCTRL_ATACLKOEN) { offset = 1; /* 133MHz */ } else { offset = 0; /* 100MHz */ } |
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reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; |
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out_be32((void __iomem *)piosht_port, reg); |
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reg = JCHCTtbl[offset][pio]; |
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out_be32((void __iomem *)pioct_port, reg); |
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} |
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/** |
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* scc_set_dma_mode - set host controller for DMA mode |
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* @hwif: port |
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* @drive: drive |
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* * Load the timing settings for this device mode into the * controller. */ |
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static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct scc_ports *ports = ide_get_hwifdata(hwif); unsigned long ctl_base = ports->ctl; unsigned long cckctrl_port = ctl_base + 0xff0; unsigned long mdmact_port = ctl_base + 0x008; unsigned long mcrcst_port = ctl_base + 0x00c; unsigned long sdmact_port = ctl_base + 0x010; unsigned long scrcst_port = ctl_base + 0x014; unsigned long udenvt_port = ctl_base + 0x018; unsigned long tdvhsel_port = ctl_base + 0x020; |
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int is_slave = drive->dn & 1; |
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int offset, idx; unsigned long reg; unsigned long jcactsel; |
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const u8 speed = drive->dma_mode; |
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reg = in_be32((void __iomem *)cckctrl_port); |
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if (reg & CCKCTRL_ATACLKOEN) { offset = 1; /* 133MHz */ } else { offset = 0; /* 100MHz */ } |
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idx = speed - XFER_UDMA_0; |
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jcactsel = JCACTSELtbl[offset][idx]; if (is_slave) { |
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out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); jcactsel = jcactsel << 2; out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); |
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} else { |
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out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); |
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} reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; |
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out_be32((void __iomem *)udenvt_port, reg); |
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} |
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static void scc_dma_host_set(ide_drive_t *drive, int on) { ide_hwif_t *hwif = drive->hwif; |
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u8 unit = drive->dn & 1; |
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u8 dma_stat = scc_dma_sff_read_status(hwif); |
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if (on) dma_stat |= (1 << (5 + unit)); else dma_stat &= ~(1 << (5 + unit)); |
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scc_ide_outb(dma_stat, hwif->dma_base + 4); |
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} |
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/** |
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* scc_dma_setup - begin a DMA phase |
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* @drive: target device |
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* @cmd: command |
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* * Build an IDE DMA PRD (IDE speak for scatter gather table) * and then set up the DMA transfer registers. * * Returns 0 on success. If a PIO fallback is required then 1 * is returned. */ |
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static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) |
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{ ide_hwif_t *hwif = drive->hwif; |
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u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR; |
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u8 dma_stat; |
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/* fall back to pio! */ |
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if (ide_build_dmatable(drive, cmd) == 0) |
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return 1; |
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/* PRD table */ |
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out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma); |
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/* specify r/w */ |
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out_be32((void __iomem *)hwif->dma_base, rw); |
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/* read DMA status for INTR & ERROR flags */ |
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dma_stat = scc_dma_sff_read_status(hwif); |
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/* clear INTR & ERROR flags */ |
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out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6); |
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|
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return 0; } |
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static void scc_dma_start(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; |
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u8 dma_cmd = scc_ide_inb(hwif->dma_base); |
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/* start DMA */ |
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scc_ide_outb(dma_cmd | 1, hwif->dma_base); |
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} static int __scc_dma_end(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; u8 dma_stat, dma_cmd; |
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/* get DMA command mode */ |
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dma_cmd = scc_ide_inb(hwif->dma_base); |
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/* stop DMA */ |
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scc_ide_outb(dma_cmd & ~1, hwif->dma_base); |
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/* get DMA status */ |
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dma_stat = scc_dma_sff_read_status(hwif); |
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/* clear the INTR & ERROR bits */ |
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scc_ide_outb(dma_stat | 6, hwif->dma_base + 4); |
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/* verify good DMA status */ |
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return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; } |
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/** |
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* scc_dma_end - Stop DMA |
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* @drive: IDE drive * * Check and clear INT Status register. |
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* Then call __scc_dma_end(). |
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*/ |
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static int scc_dma_end(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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void __iomem *dma_base = (void __iomem *)hwif->dma_base; |
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unsigned long intsts_port = hwif->dma_base + 0x014; u32 reg; |
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int dma_stat, data_loss = 0; static int retry = 0; /* errata A308 workaround: Step5 (check data loss) */ /* We don't check non ide_disk because it is limited to UDMA4 */ |
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if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr) |
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& ATA_ERR) && |
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drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { reg = in_be32((void __iomem *)intsts_port); if (!(reg & INTSTS_ACTEINT)) { printk(KERN_WARNING "%s: operation failed (transfer data loss) ", drive->name); data_loss = 1; if (retry++) { |
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struct request *rq = hwif->rq; |
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ide_drive_t *drive; int i; |
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/* ERROR_RESET and drive->crc_count are needed * to reduce DMA transfer mode in retry process. */ if (rq) rq->errors |= ERROR_RESET; |
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ide_port_for_each_dev(i, drive, hwif) |
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drive->crc_count++; |
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} } } |
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while (1) { |
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reg = in_be32((void __iomem *)intsts_port); |
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if (reg & INTSTS_SERROR) { printk(KERN_WARNING "%s: SERROR ", SCC_PATA_NAME); |
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out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); |
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out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
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continue; } if (reg & INTSTS_PRERR) { u32 maea0, maec0; unsigned long ctl_base = hwif->config_data; |
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maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); |
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printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x] ", SCC_PATA_NAME, maea0, maec0); |
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out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); |
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out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
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continue; } if (reg & INTSTS_RERR) { printk(KERN_WARNING "%s: Response Error ", SCC_PATA_NAME); |
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out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); |
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out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
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continue; } if (reg & INTSTS_ICERR) { |
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out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
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printk(KERN_WARNING "%s: Illegal Configuration ", SCC_PATA_NAME); |
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out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); |
bde18a2e1 drivers/ide: PATA... |
426 427 428 429 430 431 |
continue; } if (reg & INTSTS_BMSINT) { printk(KERN_WARNING "%s: Internal Bus Error ", SCC_PATA_NAME); |
0ecdca26e ide: use PIO/MMIO... |
432 |
out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); |
bde18a2e1 drivers/ide: PATA... |
433 434 435 436 437 438 |
ide_do_reset(drive); continue; } if (reg & INTSTS_BMHE) { |
0ecdca26e ide: use PIO/MMIO... |
439 |
out_be32((void __iomem *)intsts_port, INTSTS_BMHE); |
bde18a2e1 drivers/ide: PATA... |
440 441 442 443 |
continue; } if (reg & INTSTS_ACTEINT) { |
0ecdca26e ide: use PIO/MMIO... |
444 |
out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); |
bde18a2e1 drivers/ide: PATA... |
445 446 447 448 |
continue; } if (reg & INTSTS_IOIRQS) { |
0ecdca26e ide: use PIO/MMIO... |
449 |
out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); |
bde18a2e1 drivers/ide: PATA... |
450 451 452 453 |
continue; } break; } |
669185e98 scc_pata: add ->d... |
454 |
dma_stat = __scc_dma_end(drive); |
4ae41ff88 scc_pata.c: Worka... |
455 456 457 |
if (data_loss) dma_stat |= 2; /* emulate DMA error (to retry command) */ return dma_stat; |
bde18a2e1 drivers/ide: PATA... |
458 |
} |
06a9952b8 scc_pata: bugfix ... |
459 460 461 |
/* returns 1 if dma irq issued, 0 otherwise */ static int scc_dma_test_irq(ide_drive_t *drive) { |
898ec223f ide: remove HWIF(... |
462 |
ide_hwif_t *hwif = drive->hwif; |
4ae41ff88 scc_pata.c: Worka... |
463 |
u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); |
06a9952b8 scc_pata: bugfix ... |
464 |
|
4ae41ff88 scc_pata.c: Worka... |
465 |
/* SCC errata A252,A308 workaround: Step4 */ |
4c3032d8a ide: add struct i... |
466 |
if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr) |
3a7d24841 ide: use ATA_* de... |
467 |
& ATA_ERR) && |
4ae41ff88 scc_pata.c: Worka... |
468 |
(int_stat & INTSTS_INTRQ)) |
06a9952b8 scc_pata: bugfix ... |
469 |
return 1; |
4ae41ff88 scc_pata.c: Worka... |
470 471 |
/* SCC errata A308 workaround: Step5 (polling IOIRQS) */ if (int_stat & INTSTS_IOIRQS) |
06a9952b8 scc_pata: bugfix ... |
472 |
return 1; |
06a9952b8 scc_pata: bugfix ... |
473 474 |
return 0; } |
4ae41ff88 scc_pata.c: Worka... |
475 476 477 478 479 480 481 482 483 484 |
static u8 scc_udma_filter(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; u8 mask = hwif->ultra_mask; /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ if ((drive->media != ide_disk) && (mask & 0xE0)) { printk(KERN_INFO "%s: limit %s to UDMA4 ", SCC_PATA_NAME, drive->name); |
5f8b6c348 ide: add ->mwdma_... |
485 |
mask = ATA_UDMA4; |
4ae41ff88 scc_pata.c: Worka... |
486 487 488 489 |
} return mask; } |
bde18a2e1 drivers/ide: PATA... |
490 491 492 493 494 495 496 497 498 |
/** * setup_mmio_scc - map CTRL/BMID region * @dev: PCI device we are configuring * @name: device name * */ static int setup_mmio_scc (struct pci_dev *dev, const char *name) { |
0bd8496b5 drivers/ misc __i... |
499 500 |
void __iomem *ctl_addr; void __iomem *dma_addr; |
0d1bad216 ide: manage resou... |
501 |
int i, ret; |
bde18a2e1 drivers/ide: PATA... |
502 503 504 505 506 507 508 |
for (i = 0; i < MAX_HWIFS; i++) { if (scc_ports[i].ctl == 0) break; } if (i >= MAX_HWIFS) return -ENOMEM; |
0d1bad216 ide: manage resou... |
509 510 511 512 513 |
ret = pci_request_selected_regions(dev, (1 << 2) - 1, name); if (ret < 0) { printk(KERN_ERR "%s: can't reserve resources ", name); return ret; |
bde18a2e1 drivers/ide: PATA... |
514 |
} |
1f1ab2745 ide: two more pci... |
515 516 |
ctl_addr = pci_ioremap_bar(dev, 0); if (!ctl_addr) |
0d1bad216 ide: manage resou... |
517 |
goto fail_0; |
bde18a2e1 drivers/ide: PATA... |
518 |
|
1f1ab2745 ide: two more pci... |
519 520 |
dma_addr = pci_ioremap_bar(dev, 1); if (!dma_addr) |
0d1bad216 ide: manage resou... |
521 |
goto fail_1; |
bde18a2e1 drivers/ide: PATA... |
522 523 524 525 526 527 528 |
pci_set_master(dev); scc_ports[i].ctl = (unsigned long)ctl_addr; scc_ports[i].dma = (unsigned long)dma_addr; pci_set_drvdata(dev, (void *) &scc_ports[i]); return 1; |
bde18a2e1 drivers/ide: PATA... |
529 |
fail_1: |
0d1bad216 ide: manage resou... |
530 |
iounmap(ctl_addr); |
bde18a2e1 drivers/ide: PATA... |
531 532 533 |
fail_0: return -ENOMEM; } |
3d53ba87f scc_pata.c: do se... |
534 535 536 537 |
static int scc_ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) { struct scc_ports *ports = pci_get_drvdata(dev); |
48c3c1072 ide: add struct i... |
538 |
struct ide_host *host; |
9f36d3143 ide: remove hw_re... |
539 |
struct ide_hw hw, *hws[] = { &hw }; |
6f904d015 ide: add ide_host... |
540 |
int i, rc; |
3d53ba87f scc_pata.c: do se... |
541 |
|
3d53ba87f scc_pata.c: do se... |
542 |
memset(&hw, 0, sizeof(hw)); |
4c3032d8a ide: add struct i... |
543 544 |
for (i = 0; i <= 8; i++) hw.io_ports_array[i] = ports->dma + 0x20 + i * 4; |
3d53ba87f scc_pata.c: do se... |
545 546 |
hw.irq = dev->irq; hw.dev = &dev->dev; |
3d53ba87f scc_pata.c: do se... |
547 |
|
dca398305 ide: pass number ... |
548 |
rc = ide_host_add(d, hws, 1, &host); |
6f904d015 ide: add ide_host... |
549 550 |
if (rc) return rc; |
48c3c1072 ide: add struct i... |
551 552 |
ports->host = host; |
3d53ba87f scc_pata.c: do se... |
553 554 555 |
return 0; } |
bde18a2e1 drivers/ide: PATA... |
556 557 558 |
/** * init_setup_scc - set up an SCC PATA Controller * @dev: PCI device |
039788e15 ide: replace ide_... |
559 |
* @d: IDE port info |
bde18a2e1 drivers/ide: PATA... |
560 561 562 |
* * Perform the initial set up for this device. */ |
fe31edc8a Drivers: ide: rem... |
563 |
static int init_setup_scc(struct pci_dev *dev, const struct ide_port_info *d) |
bde18a2e1 drivers/ide: PATA... |
564 565 566 567 568 569 570 |
{ unsigned long ctl_base; unsigned long dma_base; unsigned long cckctrl_port; unsigned long intmask_port; unsigned long mode_port; unsigned long ecmode_port; |
bde18a2e1 drivers/ide: PATA... |
571 572 573 |
u32 reg = 0; struct scc_ports *ports; int rc; |
3d53ba87f scc_pata.c: do se... |
574 575 576 |
rc = pci_enable_device(dev); if (rc) goto end; |
bde18a2e1 drivers/ide: PATA... |
577 |
rc = setup_mmio_scc(dev, d->name); |
3d53ba87f scc_pata.c: do se... |
578 579 |
if (rc < 0) goto end; |
bde18a2e1 drivers/ide: PATA... |
580 581 582 583 584 585 586 587 |
ports = pci_get_drvdata(dev); ctl_base = ports->ctl; dma_base = ports->dma; cckctrl_port = ctl_base + 0xff0; intmask_port = dma_base + 0x010; mode_port = ctl_base + 0x024; ecmode_port = ctl_base + 0xf00; |
bde18a2e1 drivers/ide: PATA... |
588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 |
/* controller initialization */ reg = 0; out_be32((void*)cckctrl_port, reg); reg |= CCKCTRL_ATACLKOEN; out_be32((void*)cckctrl_port, reg); reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; out_be32((void*)cckctrl_port, reg); reg |= CCKCTRL_CRST; out_be32((void*)cckctrl_port, reg); for (;;) { reg = in_be32((void*)cckctrl_port); if (reg & CCKCTRL_CRST) break; udelay(5000); } reg |= CCKCTRL_ATARESET; out_be32((void*)cckctrl_port, reg); out_be32((void*)ecmode_port, ECMODE_VALUE); out_be32((void*)mode_port, MODE_JCUSFEN); out_be32((void*)intmask_port, INTMASK_MSK); |
3d53ba87f scc_pata.c: do se... |
612 613 614 615 |
rc = scc_ide_setup_pci_device(dev, d); end: return rc; |
bde18a2e1 drivers/ide: PATA... |
616 |
} |
c9ff9e7b6 ide: refactor tf_... |
617 |
static void scc_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid) |
db2432c40 scc_pata: add ->t... |
618 619 |
{ struct ide_io_ports *io_ports = &drive->hwif->io_ports; |
60f85019c ide: replace IDE_... |
620 621 |
if (valid & IDE_VALID_FEATURE) |
db2432c40 scc_pata: add ->t... |
622 |
scc_ide_outb(tf->feature, io_ports->feature_addr); |
60f85019c ide: replace IDE_... |
623 |
if (valid & IDE_VALID_NSECT) |
db2432c40 scc_pata: add ->t... |
624 |
scc_ide_outb(tf->nsect, io_ports->nsect_addr); |
60f85019c ide: replace IDE_... |
625 |
if (valid & IDE_VALID_LBAL) |
db2432c40 scc_pata: add ->t... |
626 |
scc_ide_outb(tf->lbal, io_ports->lbal_addr); |
60f85019c ide: replace IDE_... |
627 |
if (valid & IDE_VALID_LBAM) |
db2432c40 scc_pata: add ->t... |
628 |
scc_ide_outb(tf->lbam, io_ports->lbam_addr); |
60f85019c ide: replace IDE_... |
629 |
if (valid & IDE_VALID_LBAH) |
db2432c40 scc_pata: add ->t... |
630 |
scc_ide_outb(tf->lbah, io_ports->lbah_addr); |
60f85019c ide: replace IDE_... |
631 |
if (valid & IDE_VALID_DEVICE) |
4109d19af ide: move common ... |
632 |
scc_ide_outb(tf->device, io_ports->device_addr); |
db2432c40 scc_pata: add ->t... |
633 |
} |
3153c26b5 ide: refactor tf_... |
634 |
static void scc_tf_read(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid) |
db2432c40 scc_pata: add ->t... |
635 636 |
{ struct ide_io_ports *io_ports = &drive->hwif->io_ports; |
db2432c40 scc_pata: add ->t... |
637 |
|
60f85019c ide: replace IDE_... |
638 |
if (valid & IDE_VALID_ERROR) |
676251193 ide: rename IDE_T... |
639 |
tf->error = scc_ide_inb(io_ports->feature_addr); |
60f85019c ide: replace IDE_... |
640 |
if (valid & IDE_VALID_NSECT) |
db2432c40 scc_pata: add ->t... |
641 |
tf->nsect = scc_ide_inb(io_ports->nsect_addr); |
60f85019c ide: replace IDE_... |
642 |
if (valid & IDE_VALID_LBAL) |
db2432c40 scc_pata: add ->t... |
643 |
tf->lbal = scc_ide_inb(io_ports->lbal_addr); |
60f85019c ide: replace IDE_... |
644 |
if (valid & IDE_VALID_LBAM) |
db2432c40 scc_pata: add ->t... |
645 |
tf->lbam = scc_ide_inb(io_ports->lbam_addr); |
60f85019c ide: replace IDE_... |
646 |
if (valid & IDE_VALID_LBAH) |
db2432c40 scc_pata: add ->t... |
647 |
tf->lbah = scc_ide_inb(io_ports->lbah_addr); |
60f85019c ide: replace IDE_... |
648 |
if (valid & IDE_VALID_DEVICE) |
db2432c40 scc_pata: add ->t... |
649 |
tf->device = scc_ide_inb(io_ports->device_addr); |
db2432c40 scc_pata: add ->t... |
650 |
} |
adb1af980 ide: pass command... |
651 |
static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd, |
efa3db1bb scc_pata: add ->{... |
652 653 654 655 656 657 658 659 660 661 662 663 664 665 |
void *buf, unsigned int len) { unsigned long data_addr = drive->hwif->io_ports.data_addr; len++; if (drive->io_32bit) { scc_ide_insl(data_addr, buf, len / 4); if ((len & 3) >= 2) scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1); } else scc_ide_insw(data_addr, buf, len / 2); } |
adb1af980 ide: pass command... |
666 |
static void scc_output_data(ide_drive_t *drive, struct ide_cmd *cmd, |
efa3db1bb scc_pata: add ->{... |
667 668 669 670 671 672 673 674 675 676 677 678 679 680 |
void *buf, unsigned int len) { unsigned long data_addr = drive->hwif->io_ports.data_addr; len++; if (drive->io_32bit) { scc_ide_outsl(data_addr, buf, len / 4); if ((len & 3) >= 2) scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1); } else scc_ide_outsw(data_addr, buf, len / 2); } |
bde18a2e1 drivers/ide: PATA... |
681 682 683 684 685 |
/** * init_mmio_iops_scc - set up the iops for MMIO * @hwif: interface to set up * */ |
fe31edc8a Drivers: ide: rem... |
686 |
static void init_mmio_iops_scc(ide_hwif_t *hwif) |
bde18a2e1 drivers/ide: PATA... |
687 |
{ |
36501650e ide: keep pointer... |
688 |
struct pci_dev *dev = to_pci_dev(hwif->dev); |
bde18a2e1 drivers/ide: PATA... |
689 690 691 692 |
struct scc_ports *ports = pci_get_drvdata(dev); unsigned long dma_base = ports->dma; ide_set_hwifdata(hwif, ports); |
bde18a2e1 drivers/ide: PATA... |
693 694 |
hwif->dma_base = dma_base; hwif->config_data = ports->ctl; |
bde18a2e1 drivers/ide: PATA... |
695 696 697 698 699 700 701 702 703 |
} /** * init_iops_scc - set up iops * @hwif: interface to set up * * Do the basic setup for the SCC hardware interface * and then do the MMIO setup. */ |
fe31edc8a Drivers: ide: rem... |
704 |
static void init_iops_scc(ide_hwif_t *hwif) |
bde18a2e1 drivers/ide: PATA... |
705 |
{ |
36501650e ide: keep pointer... |
706 |
struct pci_dev *dev = to_pci_dev(hwif->dev); |
bde18a2e1 drivers/ide: PATA... |
707 708 709 710 711 |
hwif->hwif_data = NULL; if (pci_get_drvdata(dev) == NULL) return; init_mmio_iops_scc(hwif); } |
fe31edc8a Drivers: ide: rem... |
712 |
static int scc_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
2bbd57cad ide: switch to DM... |
713 714 715 |
{ return ide_allocate_dma_engine(hwif); } |
f454cbe8c ide: ->cable_dete... |
716 |
static u8 scc_cable_detect(ide_hwif_t *hwif) |
b4d1c73dc atiixp/cs5535/scc... |
717 718 719 |
{ return ATA_CBL_PATA80; } |
bde18a2e1 drivers/ide: PATA... |
720 721 722 723 724 725 726 727 |
/** * init_hwif_scc - set up hwif * @hwif: interface to set up * * We do the basic set up of the interface structure. The SCC * requires several custom handlers so we override the default * ide DMA handlers appropriately. */ |
fe31edc8a Drivers: ide: rem... |
728 |
static void init_hwif_scc(ide_hwif_t *hwif) |
bde18a2e1 drivers/ide: PATA... |
729 |
{ |
0ecdca26e ide: use PIO/MMIO... |
730 731 |
/* PTERADD */ out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); |
bde18a2e1 drivers/ide: PATA... |
732 |
|
5f8b6c348 ide: add ->mwdma_... |
733 734 735 736 |
if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) hwif->ultra_mask = ATA_UDMA6; /* 133MHz */ else hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ |
bde18a2e1 drivers/ide: PATA... |
737 |
} |
374e042c3 ide: add struct i... |
738 739 740 741 |
static const struct ide_tp_ops scc_tp_ops = { .exec_command = scc_exec_command, .read_status = scc_read_status, .read_altstatus = scc_read_altstatus, |
ecf3a31d2 ide: turn set_irq... |
742 |
.write_devctl = scc_write_devctl, |
374e042c3 ide: add struct i... |
743 |
|
abb596b25 ide: turn selectp... |
744 |
.dev_select = ide_dev_select, |
374e042c3 ide: add struct i... |
745 746 747 748 749 750 |
.tf_load = scc_tf_load, .tf_read = scc_tf_read, .input_data = scc_input_data, .output_data = scc_output_data, }; |
ac95beedf ide: add struct i... |
751 752 753 754 755 756 |
static const struct ide_port_ops scc_port_ops = { .set_pio_mode = scc_set_pio_mode, .set_dma_mode = scc_set_dma_mode, .udma_filter = scc_udma_filter, .cable_detect = scc_cable_detect, }; |
f37afdaca ide: constify str... |
757 |
static const struct ide_dma_ops scc_dma_ops = { |
669185e98 scc_pata: add ->d... |
758 |
.dma_host_set = scc_dma_host_set, |
5e37bdc08 ide: add struct i... |
759 |
.dma_setup = scc_dma_setup, |
669185e98 scc_pata: add ->d... |
760 |
.dma_start = scc_dma_start, |
5e37bdc08 ide: add struct i... |
761 762 |
.dma_end = scc_dma_end, .dma_test_irq = scc_dma_test_irq, |
f37afdaca ide: constify str... |
763 |
.dma_lost_irq = ide_dma_lost_irq, |
22117d6ea ide: add ->dma_ti... |
764 |
.dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b53152 ide: move read_sf... |
765 |
.dma_sff_read_status = scc_dma_sff_read_status, |
5e37bdc08 ide: add struct i... |
766 |
}; |
fe31edc8a Drivers: ide: rem... |
767 |
static const struct ide_port_info scc_chipset = { |
304ffd6d3 scc_pata: remove ... |
768 769 770 771 772 773 774 775 |
.name = "sccIDE", .init_iops = init_iops_scc, .init_dma = scc_init_dma, .init_hwif = init_hwif_scc, .tp_ops = &scc_tp_ops, .port_ops = &scc_port_ops, .dma_ops = &scc_dma_ops, .host_flags = IDE_HFLAG_SINGLE, |
255115fb3 ide: allow host d... |
776 |
.irq_flags = IRQF_SHARED, |
304ffd6d3 scc_pata: remove ... |
777 |
.pio_mask = ATA_PIO4, |
29e52cf79 ide: remove chips... |
778 |
.chipset = ide_pci, |
bde18a2e1 drivers/ide: PATA... |
779 780 781 782 783 784 785 786 787 788 |
}; /** * scc_init_one - pci layer discovery entry * @dev: PCI device * @id: ident table entry * * Called by the PCI code when it finds an SCC PATA controller. * We then use the IDE PCI generic helper to do most of the work. */ |
fe31edc8a Drivers: ide: rem... |
789 |
static int scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
bde18a2e1 drivers/ide: PATA... |
790 |
{ |
304ffd6d3 scc_pata: remove ... |
791 |
return init_setup_scc(dev, &scc_chipset); |
bde18a2e1 drivers/ide: PATA... |
792 793 794 795 796 797 798 799 |
} /** * scc_remove - pci layer remove entry * @dev: PCI device * * Called by the PCI code when it removes an SCC PATA controller. */ |
fe31edc8a Drivers: ide: rem... |
800 |
static void scc_remove(struct pci_dev *dev) |
bde18a2e1 drivers/ide: PATA... |
801 802 |
{ struct scc_ports *ports = pci_get_drvdata(dev); |
48c3c1072 ide: add struct i... |
803 |
struct ide_host *host = ports->host; |
bde18a2e1 drivers/ide: PATA... |
804 |
|
48c3c1072 ide: add struct i... |
805 |
ide_host_remove(host); |
bde18a2e1 drivers/ide: PATA... |
806 |
|
bde18a2e1 drivers/ide: PATA... |
807 808 |
iounmap((void*)ports->dma); iounmap((void*)ports->ctl); |
0d1bad216 ide: manage resou... |
809 |
pci_release_selected_regions(dev, (1 << 2) - 1); |
bde18a2e1 drivers/ide: PATA... |
810 811 |
memset(ports, 0, sizeof(*ports)); } |
9cbcc5e3c ide: use PCI_VDEV... |
812 813 |
static const struct pci_device_id scc_pci_tbl[] = { { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 }, |
bde18a2e1 drivers/ide: PATA... |
814 815 816 |
{ 0, }, }; MODULE_DEVICE_TABLE(pci, scc_pci_tbl); |
a9ab09e26 ide: use unique n... |
817 |
static struct pci_driver scc_pci_driver = { |
bde18a2e1 drivers/ide: PATA... |
818 819 820 |
.name = "SCC IDE", .id_table = scc_pci_tbl, .probe = scc_init_one, |
fe31edc8a Drivers: ide: rem... |
821 |
.remove = scc_remove, |
bde18a2e1 drivers/ide: PATA... |
822 |
}; |
4cd7d9247 scc_pata: fix mod... |
823 |
static int __init scc_ide_init(void) |
bde18a2e1 drivers/ide: PATA... |
824 |
{ |
a9ab09e26 ide: use unique n... |
825 |
return ide_pci_register_driver(&scc_pci_driver); |
bde18a2e1 drivers/ide: PATA... |
826 |
} |
4cd7d9247 scc_pata: fix mod... |
827 |
static void __exit scc_ide_exit(void) |
bde18a2e1 drivers/ide: PATA... |
828 |
{ |
4cd7d9247 scc_pata: fix mod... |
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pci_unregister_driver(&scc_pci_driver); |
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} |
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|
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module_init(scc_ide_init); module_exit(scc_ide_exit); |
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MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); MODULE_LICENSE("GPL"); |