Blame view
include/linux/clk-private.h
6.08 KB
b2476490e
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
/* * linux/include/linux/clk-private.h * * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __LINUX_CLK_PRIVATE_H #define __LINUX_CLK_PRIVATE_H #include <linux/clk-provider.h> |
fcb0ee6a3
|
15 |
#include <linux/kref.h> |
b2476490e
|
16 17 18 19 20 21 22 23 24 25 26 27 |
#include <linux/list.h> /* * WARNING: Do not include clk-private.h from any file that implements struct * clk_ops. Doing so is a layering violation! * * This header exists only to allow for statically initialized clock data. Any * static clock data must be defined in a separate file from the logic that * implements the clock operations for that same data. */ #ifdef CONFIG_COMMON_CLK |
ac2df527f
|
28 |
struct module; |
b2476490e
|
29 30 31 32 |
struct clk { const char *name; const struct clk_ops *ops; struct clk_hw *hw; |
ac2df527f
|
33 |
struct module *owner; |
b2476490e
|
34 |
struct clk *parent; |
d305fb78f
|
35 |
const char **parent_names; |
b2476490e
|
36 37 |
struct clk **parents; u8 num_parents; |
71472c0c0
|
38 |
u8 new_parent_index; |
b2476490e
|
39 40 |
unsigned long rate; unsigned long new_rate; |
71472c0c0
|
41 42 |
struct clk *new_parent; struct clk *new_child; |
b2476490e
|
43 44 45 |
unsigned long flags; unsigned int enable_count; unsigned int prepare_count; |
5279fc402
|
46 |
unsigned long accuracy; |
b2476490e
|
47 48 49 |
struct hlist_head children; struct hlist_node child_node; unsigned int notifier_count; |
ea72dc2cf
|
50 |
#ifdef CONFIG_DEBUG_FS |
b2476490e
|
51 52 |
struct dentry *dentry; #endif |
fcb0ee6a3
|
53 |
struct kref ref; |
b2476490e
|
54 |
}; |
9d9f78ed9
|
55 56 57 58 59 60 61 62 |
/* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ |
182f9e8cd
|
63 64 65 66 67 68 69 70 71 |
#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \ _parents) \ static struct clk _name = { \ .name = #_name, \ .ops = &_ops, \ .hw = &_name##_hw.hw, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ .parents = _parents, \ |
f7d8caadf
|
72 |
.flags = _flags | CLK_IS_BASIC, \ |
182f9e8cd
|
73 |
} |
9d9f78ed9
|
74 75 76 |
#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ _fixed_rate_flags) \ static struct clk _name; \ |
e447c50e3
|
77 |
static const char *_name##_parent_names[] = {}; \ |
9d9f78ed9
|
78 79 80 81 82 83 84 |
static struct clk_fixed_rate _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .fixed_rate = _rate, \ .flags = _fixed_rate_flags, \ }; \ |
182f9e8cd
|
85 86 |
DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \ _name##_parent_names, NULL); |
9d9f78ed9
|
87 |
|
9d9f78ed9
|
88 89 90 91 |
#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ _flags, _reg, _bit_idx, \ _gate_flags, _lock) \ static struct clk _name; \ |
e447c50e3
|
92 |
static const char *_name##_parent_names[] = { \ |
9d9f78ed9
|
93 94 95 96 97 98 99 100 101 102 103 104 105 106 |
_parent_name, \ }; \ static struct clk *_name##_parents[] = { \ _parent_ptr, \ }; \ static struct clk_gate _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .reg = _reg, \ .bit_idx = _bit_idx, \ .flags = _gate_flags, \ .lock = _lock, \ }; \ |
182f9e8cd
|
107 108 |
DEFINE_CLK(_name, clk_gate_ops, _flags, \ _name##_parent_names, _name##_parents); |
9d9f78ed9
|
109 |
|
357c3f0a6
|
110 |
#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ |
9d9f78ed9
|
111 |
_flags, _reg, _shift, _width, \ |
357c3f0a6
|
112 |
_divider_flags, _table, _lock) \ |
9d9f78ed9
|
113 |
static struct clk _name; \ |
e447c50e3
|
114 |
static const char *_name##_parent_names[] = { \ |
9d9f78ed9
|
115 116 117 118 119 120 121 122 123 124 125 126 127 |
_parent_name, \ }; \ static struct clk *_name##_parents[] = { \ _parent_ptr, \ }; \ static struct clk_divider _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .reg = _reg, \ .shift = _shift, \ .width = _width, \ .flags = _divider_flags, \ |
357c3f0a6
|
128 |
.table = _table, \ |
9d9f78ed9
|
129 130 |
.lock = _lock, \ }; \ |
182f9e8cd
|
131 132 |
DEFINE_CLK(_name, clk_divider_ops, _flags, \ _name##_parent_names, _name##_parents); |
9d9f78ed9
|
133 |
|
357c3f0a6
|
134 135 136 137 138 139 140 141 142 143 144 145 146 147 |
#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ _flags, _reg, _shift, _width, \ _divider_flags, _lock) \ _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ _flags, _reg, _shift, _width, \ _divider_flags, NULL, _lock) #define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \ _parent_ptr, _flags, _reg, \ _shift, _width, _divider_flags, \ _table, _lock) \ _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ _flags, _reg, _shift, _width, \ _divider_flags, _table, _lock) \ |
9d9f78ed9
|
148 149 150 151 152 153 154 155 156 157 |
#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ _reg, _shift, _width, \ _mux_flags, _lock) \ static struct clk _name; \ static struct clk_mux _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .reg = _reg, \ .shift = _shift, \ |
ce4f3313b
|
158 |
.mask = BIT(_width) - 1, \ |
9d9f78ed9
|
159 160 161 |
.flags = _mux_flags, \ .lock = _lock, \ }; \ |
182f9e8cd
|
162 163 |
DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \ _parents); |
9d9f78ed9
|
164 |
|
f0948f59d
|
165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 |
#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \ _parent_ptr, _flags, \ _mult, _div) \ static struct clk _name; \ static const char *_name##_parent_names[] = { \ _parent_name, \ }; \ static struct clk *_name##_parents[] = { \ _parent_ptr, \ }; \ static struct clk_fixed_factor _name##_hw = { \ .hw = { \ .clk = &_name, \ }, \ .mult = _mult, \ .div = _div, \ }; \ DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \ _name##_parent_names, _name##_parents); |
b2476490e
|
184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 |
/** * __clk_init - initialize the data structures in a struct clk * @dev: device initializing this clk, placeholder for now * @clk: clk being initialized * * Initializes the lists in struct clk, queries the hardware for the * parent and rate and sets them both. * * Any struct clk passed into __clk_init must have the following members * populated: * .name * .ops * .hw * .parent_names * .num_parents * .flags * * It is not necessary to call clk_register if __clk_init is used directly with * statically initialized clock data. |
d1302a36a
|
203 204 |
* * Returns 0 on success, otherwise an error code. |
b2476490e
|
205 |
*/ |
d1302a36a
|
206 |
int __clk_init(struct device *dev, struct clk *clk); |
b2476490e
|
207 |
|
0197b3ea0
|
208 |
struct clk *__clk_register(struct device *dev, struct clk_hw *hw); |
b2476490e
|
209 210 |
#endif /* CONFIG_COMMON_CLK */ #endif /* CLK_PRIVATE_H */ |