Eric Lee / smarc-ti-linux-kernel

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Commit 0bde8afc3a76100eb9c72ab6059f00362278e407

Authored by Kishon Vijay Abraham I
1 parent 4b4f155d66
Exists in ti-linux-3.12.y and in 3 other branches newt-ti-linux-3.12.y, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y

Revert "arm: dts: am335x-evm: add sleep states for i2c-1" 

This reverts commit 60a0cf7f99e85884a05bf2a661cea0f52a12dafe.

Fixes omap_i2c 4802a000.i2c: controller timed out on on
am335x-evm during suspend.

Reported-by: Russ Dill <russ.dill@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

Showing 1 changed file with 3 additions and 11 deletions Inline Diff

arch/arm/boot/dts/am335x-evm.dts
Diff comments   View file @ 0bde8af
1 /* 1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "am33xx.dtsi" 10 #include "am33xx.dtsi"
11 11
12 / { 12 / {
13 model = "TI AM335x EVM"; 13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx"; 14 compatible = "ti,am335x-evm", "ti,am33xx";
15 15
16 cpus { 16 cpus {
17 cpu@0 { 17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>; 18 cpu0-supply = <&vdd1_reg>;
19 }; 19 };
20 }; 20 };
21 21
22 memory { 22 memory {
23 device_type = "memory"; 23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 }; 25 };
26 26
27 am33xx_pinmux: pinmux@44e10800 { 27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&volume_keys_s0 &clkout2_pin &mmc2_pins &wlan_pins>; 29 pinctrl-0 = <&volume_keys_s0 &clkout2_pin &mmc2_pins &wlan_pins>;
30 30
31 matrix_keypad_default: matrix_keypad_default { 31 matrix_keypad_default: matrix_keypad_default {
32 pinctrl-single,pins = < 32 pinctrl-single,pins = <
33 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 33 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
34 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ 34 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
35 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ 35 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
36 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ 36 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
37 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ 37 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
38 >; 38 >;
39 }; 39 };
40 40
41 matrix_keypad_sleep: matrix_keypad_sleep { 41 matrix_keypad_sleep: matrix_keypad_sleep {
42 pinctrl-single,pins = < 42 pinctrl-single,pins = <
43 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 43 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
44 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ 44 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
45 >; 45 >;
46 }; 46 };
47 47
48 volume_keys_s0: volume_keys_s0 { 48 volume_keys_s0: volume_keys_s0 {
49 pinctrl-single,pins = < 49 pinctrl-single,pins = <
50 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ 50 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
51 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ 51 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
52 >; 52 >;
53 }; 53 };
54 54
55 i2c0_pins: pinmux_i2c0_pins { 55 i2c0_pins: pinmux_i2c0_pins {
56 pinctrl-single,pins = < 56 pinctrl-single,pins = <
57 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 57 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
58 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 58 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
59 >; 59 >;
60 }; 60 };
61 61
62 i2c1_pins_default: pinmux_i2c1_pins { 62 i2c1_pins: pinmux_i2c1_pins {
63 pinctrl-single,pins = < 63 pinctrl-single,pins = <
64 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ 64 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
65 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 65 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
66 >; 66 >;
67 }; 67 };
68 68
69 i2c1_pins_sleep: i2c1_pins_sleep {
70 pinctrl-single,pins = <
71 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
72 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
73 >;
74 };
75
76 uart0_pins: pinmux_uart0_pins { 69 uart0_pins: pinmux_uart0_pins {
77 pinctrl-single,pins = < 70 pinctrl-single,pins = <
78 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 71 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
79 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 72 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
80 >; 73 >;
81 }; 74 };
82 75
83 uart1_pins_default: pinmux_uart1_pins_default { 76 uart1_pins_default: pinmux_uart1_pins_default {
84 pinctrl-single,pins = < 77 pinctrl-single,pins = <
85 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ 78 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
86 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ 79 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
87 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ 80 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
88 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ 81 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
89 >; 82 >;
90 }; 83 };
91 84
92 uart1_pins_sleep: pinmux_uart1_pins_sleep { 85 uart1_pins_sleep: pinmux_uart1_pins_sleep {
93 pinctrl-single,pins = < 86 pinctrl-single,pins = <
94 0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7) 87 0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7)
95 0x17C (PIN_INPUT_PULLDOWN | MUX_MODE7) 88 0x17C (PIN_INPUT_PULLDOWN | MUX_MODE7)
96 0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7) 89 0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7)
97 0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7) 90 0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7)
98 >; 91 >;
99 }; 92 };
100 93
101 clkout2_pin: pinmux_clkout2_pin { 94 clkout2_pin: pinmux_clkout2_pin {
102 pinctrl-single,pins = < 95 pinctrl-single,pins = <
103 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 96 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
104 >; 97 >;
105 }; 98 };
106 99
107 nandflash_pins_default: nandflash_pins_default { 100 nandflash_pins_default: nandflash_pins_default {
108 pinctrl-single,pins = < 101 pinctrl-single,pins = <
109 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 102 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
110 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 103 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
111 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 104 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
112 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 105 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
113 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 106 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
114 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 107 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
115 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 108 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
116 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 109 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
117 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 110 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
118 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 111 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
119 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 112 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
120 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 113 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
121 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 114 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
122 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 115 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
123 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 116 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
124 >; 117 >;
125 }; 118 };
126 119
127 nandflash_pins_sleep: nandflash_pins_sleep { 120 nandflash_pins_sleep: nandflash_pins_sleep {
128 pinctrl-single,pins = < 121 pinctrl-single,pins = <
129 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7) 122 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7) 123 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7) 124 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0xc (PIN_INPUT_PULLDOWN | MUX_MODE7) 125 0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) 126 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) 127 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) 128 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
136 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) 129 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
137 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) 130 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
138 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) 131 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
139 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7) 132 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
140 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) 133 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
141 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) 134 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
142 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7) 135 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
143 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) 136 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
144 >; 137 >;
145 }; 138 };
146 139
147 ecap0_pins_default: backlight_pins { 140 ecap0_pins_default: backlight_pins {
148 pinctrl-single,pins = < 141 pinctrl-single,pins = <
149 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 142 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
150 >; 143 >;
151 }; 144 };
152 145
153 ecap0_pins_sleep: ecap0_pins_sleep { 146 ecap0_pins_sleep: ecap0_pins_sleep {
154 pinctrl-single,pins = < 147 pinctrl-single,pins = <
155 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ 148 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
156 >; 149 >;
157 }; 150 };
158 151
159 cpsw_default: cpsw_default { 152 cpsw_default: cpsw_default {
160 pinctrl-single,pins = < 153 pinctrl-single,pins = <
161 /* Slave 1 */ 154 /* Slave 1 */
162 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 155 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
163 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 156 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
164 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 157 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
165 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 158 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
166 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 159 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
167 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 160 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
168 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 161 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
169 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 162 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
170 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 163 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
171 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 164 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
172 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 165 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
173 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 166 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
174 >; 167 >;
175 }; 168 };
176 169
177 cpsw_sleep: cpsw_sleep { 170 cpsw_sleep: cpsw_sleep {
178 pinctrl-single,pins = < 171 pinctrl-single,pins = <
179 /* Slave 1 reset value */ 172 /* Slave 1 reset value */
180 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 173 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
181 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 174 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
182 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 175 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
183 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 176 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
184 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 177 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
185 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 178 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
186 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 179 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
187 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 180 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
188 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 181 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
189 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 182 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
190 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 183 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
191 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 184 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 >; 185 >;
193 }; 186 };
194 187
195 davinci_mdio_default: davinci_mdio_default { 188 davinci_mdio_default: davinci_mdio_default {
196 pinctrl-single,pins = < 189 pinctrl-single,pins = <
197 /* MDIO */ 190 /* MDIO */
198 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 191 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
199 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 192 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
200 >; 193 >;
201 }; 194 };
202 195
203 davinci_mdio_sleep: davinci_mdio_sleep { 196 davinci_mdio_sleep: davinci_mdio_sleep {
204 pinctrl-single,pins = < 197 pinctrl-single,pins = <
205 /* MDIO reset value */ 198 /* MDIO reset value */
206 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 199 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 200 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 >; 201 >;
209 }; 202 };
210 203
211 mmc1_pins_default: pinmux_mmc1_pins { 204 mmc1_pins_default: pinmux_mmc1_pins {
212 pinctrl-single,pins = < 205 pinctrl-single,pins = <
213 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ 206 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
214 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ 207 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
215 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ 208 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
216 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ 209 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
217 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ 210 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
218 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ 211 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
219 0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 */ 212 0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 */
220 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 213 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
221 >; 214 >;
222 }; 215 };
223 216
224 mmc1_pins_sleep: pinmux_mmc1_pins_sleep { 217 mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
225 pinctrl-single,pins = < 218 pinctrl-single,pins = <
226 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7) 219 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7) 220 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7) 221 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7) 222 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
230 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7) 223 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
231 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7) 224 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
232 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) 225 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7) 226 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234 >; 227 >;
235 }; 228 };
236 229
237 lcd_pins_s0: lcd_pins_s0 { 230 lcd_pins_s0: lcd_pins_s0 {
238 pinctrl-single,pins = < 231 pinctrl-single,pins = <
239 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ 232 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
240 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ 233 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
241 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ 234 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
242 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ 235 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
243 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ 236 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
244 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ 237 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
245 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ 238 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
246 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ 239 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
247 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ 240 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
248 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ 241 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
249 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ 242 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
250 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ 243 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
251 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ 244 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
252 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ 245 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
253 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ 246 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
254 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ 247 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
255 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ 248 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
256 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ 249 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
257 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ 250 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
258 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ 251 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
259 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ 252 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
260 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ 253 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
261 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ 254 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
262 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ 255 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
263 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ 256 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
264 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ 257 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
265 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ 258 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
266 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ 259 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
267 >; 260 >;
268 }; 261 };
269 262
270 am335x_evm_audio_pins: am335x_evm_audio_pins { 263 am335x_evm_audio_pins: am335x_evm_audio_pins {
271 pinctrl-single,pins = < 264 pinctrl-single,pins = <
272 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */ 265 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
273 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */ 266 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
274 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 267 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
275 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 268 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
276 >; 269 >;
277 }; 270 };
278 271
279 /* wl12xx/wl18xx card on mmc2 */ 272 /* wl12xx/wl18xx card on mmc2 */
280 mmc2_pins: pinmux_mmc2_pins { 273 mmc2_pins: pinmux_mmc2_pins {
281 pinctrl-single,pins = < 274 pinctrl-single,pins = <
282 0x44 0x33 /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ 275 0x44 0x33 /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
283 0x48 0x33 /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ 276 0x48 0x33 /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
284 0x4C 0x33 /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ 277 0x4C 0x33 /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
285 0x78 0x33 /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ 278 0x78 0x33 /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
286 0x88 0x33 /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ 279 0x88 0x33 /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
287 0x8C 0x33 /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ 280 0x8C 0x33 /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
288 >; 281 >;
289 }; 282 };
290 283
291 /* wl12xx/wl18xx card enable/irq GPIOs. */ 284 /* wl12xx/wl18xx card enable/irq GPIOs. */
292 wlan_pins: pinmux_wlan_pins { 285 wlan_pins: pinmux_wlan_pins {
293 pinctrl-single,pins = < 286 pinctrl-single,pins = <
294 0x40 0x07 /* gpmc_a0.gpio1_16, OUTPUT | MODE7 */ 287 0x40 0x07 /* gpmc_a0.gpio1_16, OUTPUT | MODE7 */
295 0x19C 0x27 /* mcasp0_ahclkr.gpio3_17, INPUT | MODE7 */ 288 0x19C 0x27 /* mcasp0_ahclkr.gpio3_17, INPUT | MODE7 */
296 0x1AC 0x17 /* mcasp0_ahclkx.gpio3_21, OUTPUT_PULLUP | MODE7 */ 289 0x1AC 0x17 /* mcasp0_ahclkx.gpio3_21, OUTPUT_PULLUP | MODE7 */
297 >; 290 >;
298 }; 291 };
299 }; 292 };
300 293
301 ocp { 294 ocp {
302 uart0: serial@44e09000 { 295 uart0: serial@44e09000 {
303 pinctrl-names = "default"; 296 pinctrl-names = "default";
304 pinctrl-0 = <&uart0_pins>; 297 pinctrl-0 = <&uart0_pins>;
305 298
306 status = "okay"; 299 status = "okay";
307 }; 300 };
308 301
309 uart1: serial@48022000 { 302 uart1: serial@48022000 {
310 pinctrl-names = "default", "sleep"; 303 pinctrl-names = "default", "sleep";
311 pinctrl-0 = <&uart1_pins_default>; 304 pinctrl-0 = <&uart1_pins_default>;
312 pinctrl-1 = <&uart1_pins_sleep>; 305 pinctrl-1 = <&uart1_pins_sleep>;
313 306
314 status = "okay"; 307 status = "okay";
315 }; 308 };
316 309
317 i2c0: i2c@44e0b000 { 310 i2c0: i2c@44e0b000 {
318 pinctrl-names = "default"; 311 pinctrl-names = "default";
319 pinctrl-0 = <&i2c0_pins>; 312 pinctrl-0 = <&i2c0_pins>;
320 313
321 status = "okay"; 314 status = "okay";
322 clock-frequency = <400000>; 315 clock-frequency = <400000>;
323 /* Set OPP50 (0.95V) for VDD core */ 316 /* Set OPP50 (0.95V) for VDD core */
324 sleep-sequence = /bits/ 8 < 317 sleep-sequence = /bits/ 8 <
325 0x02 0x2d 0x25 0x1f /* Set VDD2 to 0.95V */ 318 0x02 0x2d 0x25 0x1f /* Set VDD2 to 0.95V */
326 >; 319 >;
327 320
328 /* Set OPP100 (1.10V) for VDD core */ 321 /* Set OPP100 (1.10V) for VDD core */
329 wake-sequence = /bits/ 8 < 322 wake-sequence = /bits/ 8 <
330 0x02 0x2d 0x25 0x2b /* Set VDD2 to 1.1V */ 323 0x02 0x2d 0x25 0x2b /* Set VDD2 to 1.1V */
331 >; 324 >;
332 325
333 tps: tps@2d { 326 tps: tps@2d {
334 reg = <0x2d>; 327 reg = <0x2d>;
335 }; 328 };
336 }; 329 };
337 330
338 musb: usb@47400000 { 331 musb: usb@47400000 {
339 status = "okay"; 332 status = "okay";
340 333
341 control@44e10000 { 334 control@44e10000 {
342 status = "okay"; 335 status = "okay";
343 }; 336 };
344 337
345 usb-phy@47401300 { 338 usb-phy@47401300 {
346 status = "okay"; 339 status = "okay";
347 }; 340 };
348 341
349 usb-phy@47401b00 { 342 usb-phy@47401b00 {
350 status = "okay"; 343 status = "okay";
351 }; 344 };
352 345
353 usb@47401000 { 346 usb@47401000 {
354 status = "okay"; 347 status = "okay";
355 }; 348 };
356 349
357 usb@47401800 { 350 usb@47401800 {
358 status = "okay"; 351 status = "okay";
359 dr_mode = "host"; 352 dr_mode = "host";
360 }; 353 };
361 354
362 dma-controller@07402000 { 355 dma-controller@07402000 {
363 status = "okay"; 356 status = "okay";
364 }; 357 };
365 }; 358 };
366 359
367 i2c1: i2c@4802a000 { 360 i2c1: i2c@4802a000 {
368 pinctrl-names = "default", "sleep"; 361 pinctrl-names = "default";
369 pinctrl-0 = <&i2c1_pins_default>; 362 pinctrl-0 = <&i2c1_pins>;
370 pinctrl-1 = <&i2c1_pins_sleep>;
371 363
372 status = "okay"; 364 status = "okay";
373 clock-frequency = <100000>; 365 clock-frequency = <100000>;
374 366
375 lis331dlh: lis331dlh@18 { 367 lis331dlh: lis331dlh@18 {
376 compatible = "st,lis331dlh", "st,lis3lv02d"; 368 compatible = "st,lis331dlh", "st,lis3lv02d";
377 reg = <0x18>; 369 reg = <0x18>;
378 Vdd-supply = <&lis3_reg>; 370 Vdd-supply = <&lis3_reg>;
379 Vdd_IO-supply = <&lis3_reg>; 371 Vdd_IO-supply = <&lis3_reg>;
380 372
381 st,click-single-x; 373 st,click-single-x;
382 st,click-single-y; 374 st,click-single-y;
383 st,click-single-z; 375 st,click-single-z;
384 st,click-thresh-x = <10>; 376 st,click-thresh-x = <10>;
385 st,click-thresh-y = <10>; 377 st,click-thresh-y = <10>;
386 st,click-thresh-z = <10>; 378 st,click-thresh-z = <10>;
387 st,irq1-click; 379 st,irq1-click;
388 st,irq2-click; 380 st,irq2-click;
389 st,wakeup-x-lo; 381 st,wakeup-x-lo;
390 st,wakeup-x-hi; 382 st,wakeup-x-hi;
391 st,wakeup-y-lo; 383 st,wakeup-y-lo;
392 st,wakeup-y-hi; 384 st,wakeup-y-hi;
393 st,wakeup-z-lo; 385 st,wakeup-z-lo;
394 st,wakeup-z-hi; 386 st,wakeup-z-hi;
395 st,min-limit-x = <120>; 387 st,min-limit-x = <120>;
396 st,min-limit-y = <120>; 388 st,min-limit-y = <120>;
397 st,min-limit-z = <140>; 389 st,min-limit-z = <140>;
398 st,max-limit-x = <550>; 390 st,max-limit-x = <550>;
399 st,max-limit-y = <550>; 391 st,max-limit-y = <550>;
400 st,max-limit-z = <750>; 392 st,max-limit-z = <750>;
401 }; 393 };
402 394
403 tsl2550: tsl2550@39 { 395 tsl2550: tsl2550@39 {
404 compatible = "taos,tsl2550"; 396 compatible = "taos,tsl2550";
405 reg = <0x39>; 397 reg = <0x39>;
406 }; 398 };
407 399
408 tmp275: tmp275@48 { 400 tmp275: tmp275@48 {
409 compatible = "ti,tmp275"; 401 compatible = "ti,tmp275";
410 reg = <0x48>; 402 reg = <0x48>;
411 }; 403 };
412 404
413 tlv320aic3106: tlv320aic3106@1b { 405 tlv320aic3106: tlv320aic3106@1b {
414 compatible = "ti,tlv320aic3106"; 406 compatible = "ti,tlv320aic3106";
415 reg = <0x1b>; 407 reg = <0x1b>;
416 status = "okay"; 408 status = "okay";
417 409
418 /* Regulators */ 410 /* Regulators */
419 AVDD-supply = <&vaux2_reg>; 411 AVDD-supply = <&vaux2_reg>;
420 IOVDD-supply = <&vaux2_reg>; 412 IOVDD-supply = <&vaux2_reg>;
421 DRVDD-supply = <&vaux2_reg>; 413 DRVDD-supply = <&vaux2_reg>;
422 DVDD-supply = <&vbat>; 414 DVDD-supply = <&vbat>;
423 }; 415 };
424 }; 416 };
425 417
426 elm: elm@48080000 { 418 elm: elm@48080000 {
427 status = "okay"; 419 status = "okay";
428 }; 420 };
429 421
430 epwmss0: epwmss@48300000 { 422 epwmss0: epwmss@48300000 {
431 status = "okay"; 423 status = "okay";
432 424
433 ecap0: ecap@48300100 { 425 ecap0: ecap@48300100 {
434 status = "okay"; 426 status = "okay";
435 pinctrl-names = "default", "sleep"; 427 pinctrl-names = "default", "sleep";
436 pinctrl-0 = <&ecap0_pins_default>; 428 pinctrl-0 = <&ecap0_pins_default>;
437 pinctrl-1 = <&ecap0_pins_sleep>; 429 pinctrl-1 = <&ecap0_pins_sleep>;
438 }; 430 };
439 }; 431 };
440 432
441 gpmc: gpmc@50000000 { 433 gpmc: gpmc@50000000 {
442 status = "okay"; 434 status = "okay";
443 pinctrl-names = "default", "sleep"; 435 pinctrl-names = "default", "sleep";
444 pinctrl-0 = <&nandflash_pins_default>; 436 pinctrl-0 = <&nandflash_pins_default>;
445 pinctrl-1 = <&nandflash_pins_sleep>; 437 pinctrl-1 = <&nandflash_pins_sleep>;
446 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 438 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
447 nand@0,0 { 439 nand@0,0 {
448 reg = <0 0 0>; /* CS0, offset 0 */ 440 reg = <0 0 0>; /* CS0, offset 0 */
449 nand-bus-width = <8>; 441 nand-bus-width = <8>;
450 gpmc,device-width = <1>; 442 gpmc,device-width = <1>;
451 gpmc,sync-clk-ps = <0>; 443 gpmc,sync-clk-ps = <0>;
452 gpmc,cs-on-ns = <0>; 444 gpmc,cs-on-ns = <0>;
453 gpmc,cs-rd-off-ns = <44>; 445 gpmc,cs-rd-off-ns = <44>;
454 gpmc,cs-wr-off-ns = <44>; 446 gpmc,cs-wr-off-ns = <44>;
455 gpmc,adv-on-ns = <6>; 447 gpmc,adv-on-ns = <6>;
456 gpmc,adv-rd-off-ns = <34>; 448 gpmc,adv-rd-off-ns = <34>;
457 gpmc,adv-wr-off-ns = <44>; 449 gpmc,adv-wr-off-ns = <44>;
458 gpmc,we-on-ns = <0>; 450 gpmc,we-on-ns = <0>;
459 gpmc,we-off-ns = <40>; 451 gpmc,we-off-ns = <40>;
460 gpmc,oe-on-ns = <0>; 452 gpmc,oe-on-ns = <0>;
461 gpmc,oe-off-ns = <54>; 453 gpmc,oe-off-ns = <54>;
462 gpmc,access-ns = <64>; 454 gpmc,access-ns = <64>;
463 gpmc,rd-cycle-ns = <82>; 455 gpmc,rd-cycle-ns = <82>;
464 gpmc,wr-cycle-ns = <82>; 456 gpmc,wr-cycle-ns = <82>;
465 gpmc,wait-on-read = "true"; 457 gpmc,wait-on-read = "true";
466 gpmc,wait-on-write = "true"; 458 gpmc,wait-on-write = "true";
467 gpmc,bus-turnaround-ns = <0>; 459 gpmc,bus-turnaround-ns = <0>;
468 gpmc,cycle2cycle-delay-ns = <0>; 460 gpmc,cycle2cycle-delay-ns = <0>;
469 gpmc,clk-activation-ns = <0>; 461 gpmc,clk-activation-ns = <0>;
470 gpmc,wait-monitoring-ns = <0>; 462 gpmc,wait-monitoring-ns = <0>;
471 gpmc,wr-access-ns = <40>; 463 gpmc,wr-access-ns = <40>;
472 gpmc,wr-data-mux-bus-ns = <0>; 464 gpmc,wr-data-mux-bus-ns = <0>;
473 ti,nand-ecc-opt= "bch8"; 465 ti,nand-ecc-opt= "bch8";
474 ti,elm-id = <&elm>; 466 ti,elm-id = <&elm>;
475 /* MTD partition table */ 467 /* MTD partition table */
476 /* All SPL-* partitions are sized to minimal length 468 /* All SPL-* partitions are sized to minimal length
477 * which can be independently programmable. For 469 * which can be independently programmable. For
478 * NAND flash this is equal to size of erase-block */ 470 * NAND flash this is equal to size of erase-block */
479 #address-cells = <1>; 471 #address-cells = <1>;
480 #size-cells = <1>; 472 #size-cells = <1>;
481 partition@0 { 473 partition@0 {
482 label = "NAND.SPL"; 474 label = "NAND.SPL";
483 reg = <0x00000000 0x000020000>; 475 reg = <0x00000000 0x000020000>;
484 }; 476 };
485 partition@1 { 477 partition@1 {
486 label = "NAND.SPL.backup1"; 478 label = "NAND.SPL.backup1";
487 reg = <0x00020000 0x00020000>; 479 reg = <0x00020000 0x00020000>;
488 }; 480 };
489 partition@2 { 481 partition@2 {
490 label = "NAND.SPL.backup2"; 482 label = "NAND.SPL.backup2";
491 reg = <0x00040000 0x00020000>; 483 reg = <0x00040000 0x00020000>;
492 }; 484 };
493 partition@3 { 485 partition@3 {
494 label = "NAND.SPL.backup3"; 486 label = "NAND.SPL.backup3";
495 reg = <0x00060000 0x00020000>; 487 reg = <0x00060000 0x00020000>;
496 }; 488 };
497 partition@4 { 489 partition@4 {
498 label = "NAND.u-boot-spl-os"; 490 label = "NAND.u-boot-spl-os";
499 reg = <0x00080000 0x00040000>; 491 reg = <0x00080000 0x00040000>;
500 }; 492 };
501 partition@5 { 493 partition@5 {
502 label = "NAND.u-boot"; 494 label = "NAND.u-boot";
503 reg = <0x000C0000 0x00100000>; 495 reg = <0x000C0000 0x00100000>;
504 }; 496 };
505 partition@6 { 497 partition@6 {
506 label = "NAND.u-boot-env"; 498 label = "NAND.u-boot-env";
507 reg = <0x001C0000 0x00020000>; 499 reg = <0x001C0000 0x00020000>;
508 }; 500 };
509 partition@7 { 501 partition@7 {
510 label = "NAND.u-boot-env.backup1"; 502 label = "NAND.u-boot-env.backup1";
511 reg = <0x001E0000 0x00020000>; 503 reg = <0x001E0000 0x00020000>;
512 }; 504 };
513 partition@8 { 505 partition@8 {
514 label = "NAND.kernel"; 506 label = "NAND.kernel";
515 reg = <0x00200000 0x00800000>; 507 reg = <0x00200000 0x00800000>;
516 }; 508 };
517 partition@9 { 509 partition@9 {
518 label = "NAND.file-system"; 510 label = "NAND.file-system";
519 reg = <0x00A00000 0x0F600000>; 511 reg = <0x00A00000 0x0F600000>;
520 }; 512 };
521 }; 513 };
522 }; 514 };
523 515
524 lcdc: lcdc@0x4830e000 { 516 lcdc: lcdc@0x4830e000 {
525 pinctrl-names = "default"; 517 pinctrl-names = "default";
526 pinctrl-0 = <&lcd_pins_s0>; 518 pinctrl-0 = <&lcd_pins_s0>;
527 status = "okay"; 519 status = "okay";
528 display-timings { 520 display-timings {
529 800x480p62 { 521 800x480p62 {
530 clock-frequency = <30000000>; 522 clock-frequency = <30000000>;
531 hactive = <800>; 523 hactive = <800>;
532 vactive = <480>; 524 vactive = <480>;
533 hfront-porch = <39>; 525 hfront-porch = <39>;
534 hback-porch = <39>; 526 hback-porch = <39>;
535 hsync-len = <47>; 527 hsync-len = <47>;
536 vback-porch = <29>; 528 vback-porch = <29>;
537 vfront-porch = <13>; 529 vfront-porch = <13>;
538 vsync-len = <2>; 530 vsync-len = <2>;
539 hsync-active = <1>; 531 hsync-active = <1>;
540 vsync-active = <1>; 532 vsync-active = <1>;
541 }; 533 };
542 }; 534 };
543 }; 535 };
544 536
545 sound { 537 sound {
546 compatible = "ti,da830-evm-audio"; 538 compatible = "ti,da830-evm-audio";
547 ti,model = "AM335x-EVM"; 539 ti,model = "AM335x-EVM";
548 ti,audio-codec = <&tlv320aic3106>; 540 ti,audio-codec = <&tlv320aic3106>;
549 ti,mcasp-controller = <&mcasp1>; 541 ti,mcasp-controller = <&mcasp1>;
550 ti,codec-clock-rate = <12000000>; 542 ti,codec-clock-rate = <12000000>;
551 ti,audio-routing = 543 ti,audio-routing =
552 "Headphone Jack", "HPLOUT", 544 "Headphone Jack", "HPLOUT",
553 "Headphone Jack", "HPROUT", 545 "Headphone Jack", "HPROUT",
554 "LINE1L", "Line In", 546 "LINE1L", "Line In",
555 "LINE1R", "Line In"; 547 "LINE1R", "Line In";
556 }; 548 };
557 }; 549 };
558 550
559 vbat: fixedregulator@0 { 551 vbat: fixedregulator@0 {
560 compatible = "regulator-fixed"; 552 compatible = "regulator-fixed";
561 regulator-name = "vbat"; 553 regulator-name = "vbat";
562 regulator-min-microvolt = <5000000>; 554 regulator-min-microvolt = <5000000>;
563 regulator-max-microvolt = <5000000>; 555 regulator-max-microvolt = <5000000>;
564 regulator-boot-on; 556 regulator-boot-on;
565 }; 557 };
566 558
567 lis3_reg: fixedregulator@1 { 559 lis3_reg: fixedregulator@1 {
568 compatible = "regulator-fixed"; 560 compatible = "regulator-fixed";
569 regulator-name = "lis3_reg"; 561 regulator-name = "lis3_reg";
570 regulator-boot-on; 562 regulator-boot-on;
571 }; 563 };
572 564
573 wlan_en_reg: fixedregulator@2 { 565 wlan_en_reg: fixedregulator@2 {
574 compatible = "regulator-fixed"; 566 compatible = "regulator-fixed";
575 regulator-name = "wlan-en-regulator"; 567 regulator-name = "wlan-en-regulator";
576 regulator-min-microvolt = <1800000>; 568 regulator-min-microvolt = <1800000>;
577 regulator-max-microvolt = <1800000>; 569 regulator-max-microvolt = <1800000>;
578 570
579 /* WLAN_EN GPIO for this board - Bank1, pin16 */ 571 /* WLAN_EN GPIO for this board - Bank1, pin16 */
580 gpio = <&gpio1 16 0>; 572 gpio = <&gpio1 16 0>;
581 573
582 /* WLAN card specific delay */ 574 /* WLAN card specific delay */
583 startup-delay-us = <70000>; 575 startup-delay-us = <70000>;
584 enable-active-high; 576 enable-active-high;
585 }; 577 };
586 578
587 matrix_keypad: matrix_keypad@0 { 579 matrix_keypad: matrix_keypad@0 {
588 compatible = "gpio-matrix-keypad"; 580 compatible = "gpio-matrix-keypad";
589 debounce-delay-ms = <5>; 581 debounce-delay-ms = <5>;
590 col-scan-delay-us = <2>; 582 col-scan-delay-us = <2>;
591 583
592 pinctrl-names = "default", "sleep"; 584 pinctrl-names = "default", "sleep";
593 pinctrl-0 = <&matrix_keypad_default>; 585 pinctrl-0 = <&matrix_keypad_default>;
594 pinctrl-1 = <&matrix_keypad_sleep>; 586 pinctrl-1 = <&matrix_keypad_sleep>;
595 587
596 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ 588 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
597 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ 589 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
598 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ 590 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
599 591
600 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ 592 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
601 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ 593 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
602 594
603 linux,keymap = <0x0000008b /* MENU */ 595 linux,keymap = <0x0000008b /* MENU */
604 0x0100009e /* BACK */ 596 0x0100009e /* BACK */
605 0x02000069 /* LEFT */ 597 0x02000069 /* LEFT */
606 0x0001006a /* RIGHT */ 598 0x0001006a /* RIGHT */
607 0x0101001c /* ENTER */ 599 0x0101001c /* ENTER */
608 0x0201006c>; /* DOWN */ 600 0x0201006c>; /* DOWN */
609 }; 601 };
610 602
611 gpio_keys: volume_keys@0 { 603 gpio_keys: volume_keys@0 {
612 compatible = "gpio-keys"; 604 compatible = "gpio-keys";
613 #address-cells = <1>; 605 #address-cells = <1>;
614 #size-cells = <0>; 606 #size-cells = <0>;
615 autorepeat; 607 autorepeat;
616 608
617 switch@9 { 609 switch@9 {
618 label = "volume-up"; 610 label = "volume-up";
619 linux,code = <115>; 611 linux,code = <115>;
620 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 612 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
621 gpio-key,wakeup; 613 gpio-key,wakeup;
622 }; 614 };
623 615
624 switch@10 { 616 switch@10 {
625 label = "volume-down"; 617 label = "volume-down";
626 linux,code = <114>; 618 linux,code = <114>;
627 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 619 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
628 gpio-key,wakeup; 620 gpio-key,wakeup;
629 }; 621 };
630 }; 622 };
631 623
632 backlight { 624 backlight {
633 compatible = "pwm-backlight"; 625 compatible = "pwm-backlight";
634 pwms = <&ecap0 0 50000 0>; 626 pwms = <&ecap0 0 50000 0>;
635 brightness-levels = <0 51 53 56 62 75 101 152 255>; 627 brightness-levels = <0 51 53 56 62 75 101 152 255>;
636 default-brightness-level = <8>; 628 default-brightness-level = <8>;
637 }; 629 };
638 630
639 panel { 631 panel {
640 compatible = "ti,tilcdc,panel"; 632 compatible = "ti,tilcdc,panel";
641 status = "okay"; 633 status = "okay";
642 pinctrl-names = "default"; 634 pinctrl-names = "default";
643 pinctrl-0 = <&lcd_pins_s0>; 635 pinctrl-0 = <&lcd_pins_s0>;
644 panel-info { 636 panel-info {
645 ac-bias = <255>; 637 ac-bias = <255>;
646 ac-bias-intrpt = <0>; 638 ac-bias-intrpt = <0>;
647 dma-burst-sz = <16>; 639 dma-burst-sz = <16>;
648 bpp = <32>; 640 bpp = <32>;
649 fdd = <0x80>; 641 fdd = <0x80>;
650 sync-edge = <0>; 642 sync-edge = <0>;
651 sync-ctrl = <1>; 643 sync-ctrl = <1>;
652 raster-order = <0>; 644 raster-order = <0>;
653 fifo-th = <0>; 645 fifo-th = <0>;
654 }; 646 };
655 647
656 display-timings { 648 display-timings {
657 800x480p62 { 649 800x480p62 {
658 clock-frequency = <30000000>; 650 clock-frequency = <30000000>;
659 hactive = <800>; 651 hactive = <800>;
660 vactive = <480>; 652 vactive = <480>;
661 hfront-porch = <39>; 653 hfront-porch = <39>;
662 hback-porch = <39>; 654 hback-porch = <39>;
663 hsync-len = <47>; 655 hsync-len = <47>;
664 vback-porch = <29>; 656 vback-porch = <29>;
665 vfront-porch = <13>; 657 vfront-porch = <13>;
666 vsync-len = <2>; 658 vsync-len = <2>;
667 hsync-active = <1>; 659 hsync-active = <1>;
668 vsync-active = <1>; 660 vsync-active = <1>;
669 }; 661 };
670 }; 662 };
671 }; 663 };
672 664
673 wlcore { 665 wlcore {
674 compatible = "wlcore"; 666 compatible = "wlcore";
675 gpio = <113>; /* Bank3, pin17 */ 667 gpio = <113>; /* Bank3, pin17 */
676 668
677 /* 669 /*
678 * TODO: use edge irqs for suspend/resume. 670 * TODO: use edge irqs for suspend/resume.
679 * in newer kerenls, we seem to miss interrupts when 671 * in newer kerenls, we seem to miss interrupts when
680 * working with edge irqs, so revert back to level irqs. 672 * working with edge irqs, so revert back to level irqs.
681 */ 673 */
682 /* platform-quirks = <1>; */ 674 /* platform-quirks = <1>; */
683 675
684 /* if a 12xx card is there, configure the clock to 676 /* if a 12xx card is there, configure the clock to
685 WL12XX_REFCLOCK_38_XTAL */ 677 WL12XX_REFCLOCK_38_XTAL */
686 board-ref-clock = <4>; 678 board-ref-clock = <4>;
687 }; 679 };
688 680
689 kim { 681 kim {
690 compatible = "kim"; 682 compatible = "kim";
691 nshutdown_gpio = <117>; /* Bank3, pin21 */ 683 nshutdown_gpio = <117>; /* Bank3, pin21 */
692 dev_name = "/dev/ttyO1"; 684 dev_name = "/dev/ttyO1";
693 flow_cntrl = <1>; 685 flow_cntrl = <1>;
694 baud_rate = <3000000>; 686 baud_rate = <3000000>;
695 }; 687 };
696 688
697 btwilink { 689 btwilink {
698 compatible = "btwilink"; 690 compatible = "btwilink";
699 }; 691 };
700 692
701 }; 693 };
702 694
703 #include "tps65910.dtsi" 695 #include "tps65910.dtsi"
704 696
705 &mcasp1 { 697 &mcasp1 {
706 pinctrl-names = "default"; 698 pinctrl-names = "default";
707 pinctrl-0 = <&am335x_evm_audio_pins>; 699 pinctrl-0 = <&am335x_evm_audio_pins>;
708 700
709 status = "okay"; 701 status = "okay";
710 702
711 op-mode = <0>; /* MCASP_IIS_MODE */ 703 op-mode = <0>; /* MCASP_IIS_MODE */
712 tdm-slots = <2>; 704 tdm-slots = <2>;
713 /* 16 serializer */ 705 /* 16 serializer */
714 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 706 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
715 0 0 1 2 707 0 0 1 2
716 >; 708 >;
717 tx-num-evt = <1>; 709 tx-num-evt = <1>;
718 rx-num-evt = <1>; 710 rx-num-evt = <1>;
719 }; 711 };
720 712
721 &tps { 713 &tps {
722 vcc1-supply = <&vbat>; 714 vcc1-supply = <&vbat>;
723 vcc2-supply = <&vbat>; 715 vcc2-supply = <&vbat>;
724 vcc3-supply = <&vbat>; 716 vcc3-supply = <&vbat>;
725 vcc4-supply = <&vbat>; 717 vcc4-supply = <&vbat>;
726 vcc5-supply = <&vbat>; 718 vcc5-supply = <&vbat>;
727 vcc6-supply = <&vbat>; 719 vcc6-supply = <&vbat>;
728 vcc7-supply = <&vbat>; 720 vcc7-supply = <&vbat>;
729 vccio-supply = <&vbat>; 721 vccio-supply = <&vbat>;
730 722
731 regulators { 723 regulators {
732 vrtc_reg: regulator@0 { 724 vrtc_reg: regulator@0 {
733 regulator-always-on; 725 regulator-always-on;
734 }; 726 };
735 727
736 vio_reg: regulator@1 { 728 vio_reg: regulator@1 {
737 regulator-always-on; 729 regulator-always-on;
738 }; 730 };
739 731
740 vdd1_reg: regulator@2 { 732 vdd1_reg: regulator@2 {
741 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ 733 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
742 regulator-name = "vdd_mpu"; 734 regulator-name = "vdd_mpu";
743 regulator-min-microvolt = <912500>; 735 regulator-min-microvolt = <912500>;
744 regulator-max-microvolt = <1378000>; 736 regulator-max-microvolt = <1378000>;
745 regulator-boot-on; 737 regulator-boot-on;
746 regulator-always-on; 738 regulator-always-on;
747 }; 739 };
748 740
749 vdd2_reg: regulator@3 { 741 vdd2_reg: regulator@3 {
750 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 742 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
751 regulator-name = "vdd_core"; 743 regulator-name = "vdd_core";
752 regulator-min-microvolt = <912500>; 744 regulator-min-microvolt = <912500>;
753 regulator-max-microvolt = <1150000>; 745 regulator-max-microvolt = <1150000>;
754 regulator-boot-on; 746 regulator-boot-on;
755 regulator-always-on; 747 regulator-always-on;
756 }; 748 };
757 749
758 vdd3_reg: regulator@4 { 750 vdd3_reg: regulator@4 {
759 regulator-always-on; 751 regulator-always-on;
760 }; 752 };
761 753
762 vdig1_reg: regulator@5 { 754 vdig1_reg: regulator@5 {
763 regulator-always-on; 755 regulator-always-on;
764 }; 756 };
765 757
766 vdig2_reg: regulator@6 { 758 vdig2_reg: regulator@6 {
767 regulator-always-on; 759 regulator-always-on;
768 }; 760 };
769 761
770 vpll_reg: regulator@7 { 762 vpll_reg: regulator@7 {
771 regulator-always-on; 763 regulator-always-on;
772 }; 764 };
773 765
774 vdac_reg: regulator@8 { 766 vdac_reg: regulator@8 {
775 regulator-always-on; 767 regulator-always-on;
776 }; 768 };
777 769
778 vaux1_reg: regulator@9 { 770 vaux1_reg: regulator@9 {
779 regulator-always-on; 771 regulator-always-on;
780 }; 772 };
781 773
782 vaux2_reg: regulator@10 { 774 vaux2_reg: regulator@10 {
783 regulator-always-on; 775 regulator-always-on;
784 }; 776 };
785 777
786 vaux33_reg: regulator@11 { 778 vaux33_reg: regulator@11 {
787 regulator-always-on; 779 regulator-always-on;
788 }; 780 };
789 781
790 vmmc_reg: regulator@12 { 782 vmmc_reg: regulator@12 {
791 regulator-min-microvolt = <1800000>; 783 regulator-min-microvolt = <1800000>;
792 regulator-max-microvolt = <3300000>; 784 regulator-max-microvolt = <3300000>;
793 regulator-always-on; 785 regulator-always-on;
794 }; 786 };
795 }; 787 };
796 }; 788 };
797 789
798 &mac { 790 &mac {
799 slaves = <1>; 791 slaves = <1>;
800 pinctrl-names = "default", "sleep"; 792 pinctrl-names = "default", "sleep";
801 pinctrl-0 = <&cpsw_default>; 793 pinctrl-0 = <&cpsw_default>;
802 pinctrl-1 = <&cpsw_sleep>; 794 pinctrl-1 = <&cpsw_sleep>;
803 }; 795 };
804 796
805 &davinci_mdio { 797 &davinci_mdio {
806 pinctrl-names = "default", "sleep"; 798 pinctrl-names = "default", "sleep";
807 pinctrl-0 = <&davinci_mdio_default>; 799 pinctrl-0 = <&davinci_mdio_default>;
808 pinctrl-1 = <&davinci_mdio_sleep>; 800 pinctrl-1 = <&davinci_mdio_sleep>;
809 }; 801 };
810 802
811 &cpsw_emac0 { 803 &cpsw_emac0 {
812 phy_id = <&davinci_mdio>, <0>; 804 phy_id = <&davinci_mdio>, <0>;
813 phy-mode = "rgmii-txid"; 805 phy-mode = "rgmii-txid";
814 }; 806 };
815 807
816 &tscadc { 808 &tscadc {
817 status = "okay"; 809 status = "okay";
818 tsc { 810 tsc {
819 ti,wires = <4>; 811 ti,wires = <4>;
820 ti,x-plate-resistance = <200>; 812 ti,x-plate-resistance = <200>;
821 ti,coordinate-readouts = <5>; 813 ti,coordinate-readouts = <5>;
822 ti,wire-config = <0x00 0x11 0x22 0x33>; 814 ti,wire-config = <0x00 0x11 0x22 0x33>;
823 }; 815 };
824 816
825 adc { 817 adc {
826 ti,adc-channels = <4 5 6 7>; 818 ti,adc-channels = <4 5 6 7>;
827 }; 819 };
828 }; 820 };
829 821
830 &mmc1 { 822 &mmc1 {
831 status = "okay"; 823 status = "okay";
832 vmmc-supply = <&vmmc_reg>; 824 vmmc-supply = <&vmmc_reg>;
833 bus-width = <4>; 825 bus-width = <4>;
834 pinctrl-names = "default", "sleep"; 826 pinctrl-names = "default", "sleep";
835 pinctrl-0 = <&mmc1_pins_default>; 827 pinctrl-0 = <&mmc1_pins_default>;
836 pinctrl-1 = <&mmc1_pins_sleep>; 828 pinctrl-1 = <&mmc1_pins_sleep>;
837 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 829 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
838 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; 830 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
839 }; 831 };
840 832
841 &mmc3 { 833 &mmc3 {
842 /* these are on the crossbar and are outlined in the 834 /* these are on the crossbar and are outlined in the
843 xbar-event-map element */ 835 xbar-event-map element */
844 dmas = <&edma 12 836 dmas = <&edma 12
845 &edma 13>; 837 &edma 13>;
846 dma-names = "tx", "rx"; 838 dma-names = "tx", "rx";
847 839
848 status = "okay"; 840 status = "okay";
849 vmmc-supply = <&wlan_en_reg>; 841 vmmc-supply = <&wlan_en_reg>;
850 bus-width = <4>; 842 bus-width = <4>;
851 ti,non-removable; 843 ti,non-removable;
852 ti,needs-special-hs-handling; 844 ti,needs-special-hs-handling;
853 cap-power-off-card; 845 cap-power-off-card;
854 keep-power-in-suspend; 846 keep-power-in-suspend;
855 }; 847 };
856 848
857 &edma { 849 &edma {
858 ti,edma-xbar-event-map = <1 12 850 ti,edma-xbar-event-map = <1 12
859 2 13>; 851 2 13>;
860 }; 852 };
861 853