Commit 1401ebda89ebf3156984c175209f630e0844f6ce
Committed by
Greg Kroah-Hartman
1 parent
71378785b6
Exists in
smarct4x-processor-sdk-linux-03.00.00.04
and in
2 other branches
serial: 8250_pci: fix divide error bug if baud rate is 0
commit 6f210c18c1c0f016772c8cd51ae12a02bfb9e7ef upstream. Since commit 21947ba654a6 ("serial: 8250_pci: replace switch-case by formula"), the 8250 driver crashes in the byt_set_termios() function with a divide error. This is caused by the fact that a baud rate of 0 (B0) is not handled properly. Fix it by falling back to B9600 in this case. Signed-off-by: David Müller <d.mueller@elsoft.ch> Fixes: 21947ba654a6 ("serial: 8250_pci: replace switch-case by formula") Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Showing 1 changed file with 3 additions and 0 deletions Inline Diff
drivers/tty/serial/8250/8250_pci.c
1 | /* | 1 | /* |
2 | * Probe module for 8250/16550-type PCI serial ports. | 2 | * Probe module for 8250/16550-type PCI serial ports. |
3 | * | 3 | * |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | 4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
5 | * | 5 | * |
6 | * Copyright (C) 2001 Russell King, All Rights Reserved. | 6 | * Copyright (C) 2001 Russell King, All Rights Reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | 9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License. | 10 | * the Free Software Foundation; either version 2 of the License. |
11 | */ | 11 | */ |
12 | #undef DEBUG | 12 | #undef DEBUG |
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/pci.h> | 14 | #include <linux/pci.h> |
15 | #include <linux/string.h> | 15 | #include <linux/string.h> |
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/slab.h> | 17 | #include <linux/slab.h> |
18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
19 | #include <linux/tty.h> | 19 | #include <linux/tty.h> |
20 | #include <linux/serial_reg.h> | 20 | #include <linux/serial_reg.h> |
21 | #include <linux/serial_core.h> | 21 | #include <linux/serial_core.h> |
22 | #include <linux/8250_pci.h> | 22 | #include <linux/8250_pci.h> |
23 | #include <linux/bitops.h> | 23 | #include <linux/bitops.h> |
24 | #include <linux/rational.h> | 24 | #include <linux/rational.h> |
25 | 25 | ||
26 | #include <asm/byteorder.h> | 26 | #include <asm/byteorder.h> |
27 | #include <asm/io.h> | 27 | #include <asm/io.h> |
28 | 28 | ||
29 | #include <linux/dmaengine.h> | 29 | #include <linux/dmaengine.h> |
30 | #include <linux/platform_data/dma-dw.h> | 30 | #include <linux/platform_data/dma-dw.h> |
31 | 31 | ||
32 | #include "8250.h" | 32 | #include "8250.h" |
33 | 33 | ||
34 | /* | 34 | /* |
35 | * init function returns: | 35 | * init function returns: |
36 | * > 0 - number of ports | 36 | * > 0 - number of ports |
37 | * = 0 - use board->num_ports | 37 | * = 0 - use board->num_ports |
38 | * < 0 - error | 38 | * < 0 - error |
39 | */ | 39 | */ |
40 | struct pci_serial_quirk { | 40 | struct pci_serial_quirk { |
41 | u32 vendor; | 41 | u32 vendor; |
42 | u32 device; | 42 | u32 device; |
43 | u32 subvendor; | 43 | u32 subvendor; |
44 | u32 subdevice; | 44 | u32 subdevice; |
45 | int (*probe)(struct pci_dev *dev); | 45 | int (*probe)(struct pci_dev *dev); |
46 | int (*init)(struct pci_dev *dev); | 46 | int (*init)(struct pci_dev *dev); |
47 | int (*setup)(struct serial_private *, | 47 | int (*setup)(struct serial_private *, |
48 | const struct pciserial_board *, | 48 | const struct pciserial_board *, |
49 | struct uart_8250_port *, int); | 49 | struct uart_8250_port *, int); |
50 | void (*exit)(struct pci_dev *dev); | 50 | void (*exit)(struct pci_dev *dev); |
51 | }; | 51 | }; |
52 | 52 | ||
53 | #define PCI_NUM_BAR_RESOURCES 6 | 53 | #define PCI_NUM_BAR_RESOURCES 6 |
54 | 54 | ||
55 | struct serial_private { | 55 | struct serial_private { |
56 | struct pci_dev *dev; | 56 | struct pci_dev *dev; |
57 | unsigned int nr; | 57 | unsigned int nr; |
58 | void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; | 58 | void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; |
59 | struct pci_serial_quirk *quirk; | 59 | struct pci_serial_quirk *quirk; |
60 | int line[0]; | 60 | int line[0]; |
61 | }; | 61 | }; |
62 | 62 | ||
63 | static int pci_default_setup(struct serial_private*, | 63 | static int pci_default_setup(struct serial_private*, |
64 | const struct pciserial_board*, struct uart_8250_port *, int); | 64 | const struct pciserial_board*, struct uart_8250_port *, int); |
65 | 65 | ||
66 | static void moan_device(const char *str, struct pci_dev *dev) | 66 | static void moan_device(const char *str, struct pci_dev *dev) |
67 | { | 67 | { |
68 | dev_err(&dev->dev, | 68 | dev_err(&dev->dev, |
69 | "%s: %s\n" | 69 | "%s: %s\n" |
70 | "Please send the output of lspci -vv, this\n" | 70 | "Please send the output of lspci -vv, this\n" |
71 | "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" | 71 | "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" |
72 | "manufacturer and name of serial board or\n" | 72 | "manufacturer and name of serial board or\n" |
73 | "modem board to <linux-serial@vger.kernel.org>.\n", | 73 | "modem board to <linux-serial@vger.kernel.org>.\n", |
74 | pci_name(dev), str, dev->vendor, dev->device, | 74 | pci_name(dev), str, dev->vendor, dev->device, |
75 | dev->subsystem_vendor, dev->subsystem_device); | 75 | dev->subsystem_vendor, dev->subsystem_device); |
76 | } | 76 | } |
77 | 77 | ||
78 | static int | 78 | static int |
79 | setup_port(struct serial_private *priv, struct uart_8250_port *port, | 79 | setup_port(struct serial_private *priv, struct uart_8250_port *port, |
80 | int bar, int offset, int regshift) | 80 | int bar, int offset, int regshift) |
81 | { | 81 | { |
82 | struct pci_dev *dev = priv->dev; | 82 | struct pci_dev *dev = priv->dev; |
83 | 83 | ||
84 | if (bar >= PCI_NUM_BAR_RESOURCES) | 84 | if (bar >= PCI_NUM_BAR_RESOURCES) |
85 | return -EINVAL; | 85 | return -EINVAL; |
86 | 86 | ||
87 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { | 87 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { |
88 | if (!priv->remapped_bar[bar]) | 88 | if (!priv->remapped_bar[bar]) |
89 | priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar); | 89 | priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar); |
90 | if (!priv->remapped_bar[bar]) | 90 | if (!priv->remapped_bar[bar]) |
91 | return -ENOMEM; | 91 | return -ENOMEM; |
92 | 92 | ||
93 | port->port.iotype = UPIO_MEM; | 93 | port->port.iotype = UPIO_MEM; |
94 | port->port.iobase = 0; | 94 | port->port.iobase = 0; |
95 | port->port.mapbase = pci_resource_start(dev, bar) + offset; | 95 | port->port.mapbase = pci_resource_start(dev, bar) + offset; |
96 | port->port.membase = priv->remapped_bar[bar] + offset; | 96 | port->port.membase = priv->remapped_bar[bar] + offset; |
97 | port->port.regshift = regshift; | 97 | port->port.regshift = regshift; |
98 | } else { | 98 | } else { |
99 | port->port.iotype = UPIO_PORT; | 99 | port->port.iotype = UPIO_PORT; |
100 | port->port.iobase = pci_resource_start(dev, bar) + offset; | 100 | port->port.iobase = pci_resource_start(dev, bar) + offset; |
101 | port->port.mapbase = 0; | 101 | port->port.mapbase = 0; |
102 | port->port.membase = NULL; | 102 | port->port.membase = NULL; |
103 | port->port.regshift = 0; | 103 | port->port.regshift = 0; |
104 | } | 104 | } |
105 | return 0; | 105 | return 0; |
106 | } | 106 | } |
107 | 107 | ||
108 | /* | 108 | /* |
109 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | 109 | * ADDI-DATA GmbH communication cards <info@addi-data.com> |
110 | */ | 110 | */ |
111 | static int addidata_apci7800_setup(struct serial_private *priv, | 111 | static int addidata_apci7800_setup(struct serial_private *priv, |
112 | const struct pciserial_board *board, | 112 | const struct pciserial_board *board, |
113 | struct uart_8250_port *port, int idx) | 113 | struct uart_8250_port *port, int idx) |
114 | { | 114 | { |
115 | unsigned int bar = 0, offset = board->first_offset; | 115 | unsigned int bar = 0, offset = board->first_offset; |
116 | bar = FL_GET_BASE(board->flags); | 116 | bar = FL_GET_BASE(board->flags); |
117 | 117 | ||
118 | if (idx < 2) { | 118 | if (idx < 2) { |
119 | offset += idx * board->uart_offset; | 119 | offset += idx * board->uart_offset; |
120 | } else if ((idx >= 2) && (idx < 4)) { | 120 | } else if ((idx >= 2) && (idx < 4)) { |
121 | bar += 1; | 121 | bar += 1; |
122 | offset += ((idx - 2) * board->uart_offset); | 122 | offset += ((idx - 2) * board->uart_offset); |
123 | } else if ((idx >= 4) && (idx < 6)) { | 123 | } else if ((idx >= 4) && (idx < 6)) { |
124 | bar += 2; | 124 | bar += 2; |
125 | offset += ((idx - 4) * board->uart_offset); | 125 | offset += ((idx - 4) * board->uart_offset); |
126 | } else if (idx >= 6) { | 126 | } else if (idx >= 6) { |
127 | bar += 3; | 127 | bar += 3; |
128 | offset += ((idx - 6) * board->uart_offset); | 128 | offset += ((idx - 6) * board->uart_offset); |
129 | } | 129 | } |
130 | 130 | ||
131 | return setup_port(priv, port, bar, offset, board->reg_shift); | 131 | return setup_port(priv, port, bar, offset, board->reg_shift); |
132 | } | 132 | } |
133 | 133 | ||
134 | /* | 134 | /* |
135 | * AFAVLAB uses a different mixture of BARs and offsets | 135 | * AFAVLAB uses a different mixture of BARs and offsets |
136 | * Not that ugly ;) -- HW | 136 | * Not that ugly ;) -- HW |
137 | */ | 137 | */ |
138 | static int | 138 | static int |
139 | afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, | 139 | afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, |
140 | struct uart_8250_port *port, int idx) | 140 | struct uart_8250_port *port, int idx) |
141 | { | 141 | { |
142 | unsigned int bar, offset = board->first_offset; | 142 | unsigned int bar, offset = board->first_offset; |
143 | 143 | ||
144 | bar = FL_GET_BASE(board->flags); | 144 | bar = FL_GET_BASE(board->flags); |
145 | if (idx < 4) | 145 | if (idx < 4) |
146 | bar += idx; | 146 | bar += idx; |
147 | else { | 147 | else { |
148 | bar = 4; | 148 | bar = 4; |
149 | offset += (idx - 4) * board->uart_offset; | 149 | offset += (idx - 4) * board->uart_offset; |
150 | } | 150 | } |
151 | 151 | ||
152 | return setup_port(priv, port, bar, offset, board->reg_shift); | 152 | return setup_port(priv, port, bar, offset, board->reg_shift); |
153 | } | 153 | } |
154 | 154 | ||
155 | /* | 155 | /* |
156 | * HP's Remote Management Console. The Diva chip came in several | 156 | * HP's Remote Management Console. The Diva chip came in several |
157 | * different versions. N-class, L2000 and A500 have two Diva chips, each | 157 | * different versions. N-class, L2000 and A500 have two Diva chips, each |
158 | * with 3 UARTs (the third UART on the second chip is unused). Superdome | 158 | * with 3 UARTs (the third UART on the second chip is unused). Superdome |
159 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have | 159 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have |
160 | * one Diva chip, but it has been expanded to 5 UARTs. | 160 | * one Diva chip, but it has been expanded to 5 UARTs. |
161 | */ | 161 | */ |
162 | static int pci_hp_diva_init(struct pci_dev *dev) | 162 | static int pci_hp_diva_init(struct pci_dev *dev) |
163 | { | 163 | { |
164 | int rc = 0; | 164 | int rc = 0; |
165 | 165 | ||
166 | switch (dev->subsystem_device) { | 166 | switch (dev->subsystem_device) { |
167 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: | 167 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: |
168 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: | 168 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: |
169 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: | 169 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: |
170 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | 170 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: |
171 | rc = 3; | 171 | rc = 3; |
172 | break; | 172 | break; |
173 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: | 173 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: |
174 | rc = 2; | 174 | rc = 2; |
175 | break; | 175 | break; |
176 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | 176 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: |
177 | rc = 4; | 177 | rc = 4; |
178 | break; | 178 | break; |
179 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: | 179 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: |
180 | case PCI_DEVICE_ID_HP_DIVA_HURRICANE: | 180 | case PCI_DEVICE_ID_HP_DIVA_HURRICANE: |
181 | rc = 1; | 181 | rc = 1; |
182 | break; | 182 | break; |
183 | } | 183 | } |
184 | 184 | ||
185 | return rc; | 185 | return rc; |
186 | } | 186 | } |
187 | 187 | ||
188 | /* | 188 | /* |
189 | * HP's Diva chip puts the 4th/5th serial port further out, and | 189 | * HP's Diva chip puts the 4th/5th serial port further out, and |
190 | * some serial ports are supposed to be hidden on certain models. | 190 | * some serial ports are supposed to be hidden on certain models. |
191 | */ | 191 | */ |
192 | static int | 192 | static int |
193 | pci_hp_diva_setup(struct serial_private *priv, | 193 | pci_hp_diva_setup(struct serial_private *priv, |
194 | const struct pciserial_board *board, | 194 | const struct pciserial_board *board, |
195 | struct uart_8250_port *port, int idx) | 195 | struct uart_8250_port *port, int idx) |
196 | { | 196 | { |
197 | unsigned int offset = board->first_offset; | 197 | unsigned int offset = board->first_offset; |
198 | unsigned int bar = FL_GET_BASE(board->flags); | 198 | unsigned int bar = FL_GET_BASE(board->flags); |
199 | 199 | ||
200 | switch (priv->dev->subsystem_device) { | 200 | switch (priv->dev->subsystem_device) { |
201 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | 201 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: |
202 | if (idx == 3) | 202 | if (idx == 3) |
203 | idx++; | 203 | idx++; |
204 | break; | 204 | break; |
205 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | 205 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: |
206 | if (idx > 0) | 206 | if (idx > 0) |
207 | idx++; | 207 | idx++; |
208 | if (idx > 2) | 208 | if (idx > 2) |
209 | idx++; | 209 | idx++; |
210 | break; | 210 | break; |
211 | } | 211 | } |
212 | if (idx > 2) | 212 | if (idx > 2) |
213 | offset = 0x18; | 213 | offset = 0x18; |
214 | 214 | ||
215 | offset += idx * board->uart_offset; | 215 | offset += idx * board->uart_offset; |
216 | 216 | ||
217 | return setup_port(priv, port, bar, offset, board->reg_shift); | 217 | return setup_port(priv, port, bar, offset, board->reg_shift); |
218 | } | 218 | } |
219 | 219 | ||
220 | /* | 220 | /* |
221 | * Added for EKF Intel i960 serial boards | 221 | * Added for EKF Intel i960 serial boards |
222 | */ | 222 | */ |
223 | static int pci_inteli960ni_init(struct pci_dev *dev) | 223 | static int pci_inteli960ni_init(struct pci_dev *dev) |
224 | { | 224 | { |
225 | u32 oldval; | 225 | u32 oldval; |
226 | 226 | ||
227 | if (!(dev->subsystem_device & 0x1000)) | 227 | if (!(dev->subsystem_device & 0x1000)) |
228 | return -ENODEV; | 228 | return -ENODEV; |
229 | 229 | ||
230 | /* is firmware started? */ | 230 | /* is firmware started? */ |
231 | pci_read_config_dword(dev, 0x44, &oldval); | 231 | pci_read_config_dword(dev, 0x44, &oldval); |
232 | if (oldval == 0x00001000L) { /* RESET value */ | 232 | if (oldval == 0x00001000L) { /* RESET value */ |
233 | dev_dbg(&dev->dev, "Local i960 firmware missing\n"); | 233 | dev_dbg(&dev->dev, "Local i960 firmware missing\n"); |
234 | return -ENODEV; | 234 | return -ENODEV; |
235 | } | 235 | } |
236 | return 0; | 236 | return 0; |
237 | } | 237 | } |
238 | 238 | ||
239 | /* | 239 | /* |
240 | * Some PCI serial cards using the PLX 9050 PCI interface chip require | 240 | * Some PCI serial cards using the PLX 9050 PCI interface chip require |
241 | * that the card interrupt be explicitly enabled or disabled. This | 241 | * that the card interrupt be explicitly enabled or disabled. This |
242 | * seems to be mainly needed on card using the PLX which also use I/O | 242 | * seems to be mainly needed on card using the PLX which also use I/O |
243 | * mapped memory. | 243 | * mapped memory. |
244 | */ | 244 | */ |
245 | static int pci_plx9050_init(struct pci_dev *dev) | 245 | static int pci_plx9050_init(struct pci_dev *dev) |
246 | { | 246 | { |
247 | u8 irq_config; | 247 | u8 irq_config; |
248 | void __iomem *p; | 248 | void __iomem *p; |
249 | 249 | ||
250 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { | 250 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { |
251 | moan_device("no memory in bar 0", dev); | 251 | moan_device("no memory in bar 0", dev); |
252 | return 0; | 252 | return 0; |
253 | } | 253 | } |
254 | 254 | ||
255 | irq_config = 0x41; | 255 | irq_config = 0x41; |
256 | if (dev->vendor == PCI_VENDOR_ID_PANACOM || | 256 | if (dev->vendor == PCI_VENDOR_ID_PANACOM || |
257 | dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) | 257 | dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) |
258 | irq_config = 0x43; | 258 | irq_config = 0x43; |
259 | 259 | ||
260 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && | 260 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && |
261 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) | 261 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) |
262 | /* | 262 | /* |
263 | * As the megawolf cards have the int pins active | 263 | * As the megawolf cards have the int pins active |
264 | * high, and have 2 UART chips, both ints must be | 264 | * high, and have 2 UART chips, both ints must be |
265 | * enabled on the 9050. Also, the UARTS are set in | 265 | * enabled on the 9050. Also, the UARTS are set in |
266 | * 16450 mode by default, so we have to enable the | 266 | * 16450 mode by default, so we have to enable the |
267 | * 16C950 'enhanced' mode so that we can use the | 267 | * 16C950 'enhanced' mode so that we can use the |
268 | * deep FIFOs | 268 | * deep FIFOs |
269 | */ | 269 | */ |
270 | irq_config = 0x5b; | 270 | irq_config = 0x5b; |
271 | /* | 271 | /* |
272 | * enable/disable interrupts | 272 | * enable/disable interrupts |
273 | */ | 273 | */ |
274 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); | 274 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
275 | if (p == NULL) | 275 | if (p == NULL) |
276 | return -ENOMEM; | 276 | return -ENOMEM; |
277 | writel(irq_config, p + 0x4c); | 277 | writel(irq_config, p + 0x4c); |
278 | 278 | ||
279 | /* | 279 | /* |
280 | * Read the register back to ensure that it took effect. | 280 | * Read the register back to ensure that it took effect. |
281 | */ | 281 | */ |
282 | readl(p + 0x4c); | 282 | readl(p + 0x4c); |
283 | iounmap(p); | 283 | iounmap(p); |
284 | 284 | ||
285 | return 0; | 285 | return 0; |
286 | } | 286 | } |
287 | 287 | ||
288 | static void pci_plx9050_exit(struct pci_dev *dev) | 288 | static void pci_plx9050_exit(struct pci_dev *dev) |
289 | { | 289 | { |
290 | u8 __iomem *p; | 290 | u8 __iomem *p; |
291 | 291 | ||
292 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) | 292 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) |
293 | return; | 293 | return; |
294 | 294 | ||
295 | /* | 295 | /* |
296 | * disable interrupts | 296 | * disable interrupts |
297 | */ | 297 | */ |
298 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); | 298 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
299 | if (p != NULL) { | 299 | if (p != NULL) { |
300 | writel(0, p + 0x4c); | 300 | writel(0, p + 0x4c); |
301 | 301 | ||
302 | /* | 302 | /* |
303 | * Read the register back to ensure that it took effect. | 303 | * Read the register back to ensure that it took effect. |
304 | */ | 304 | */ |
305 | readl(p + 0x4c); | 305 | readl(p + 0x4c); |
306 | iounmap(p); | 306 | iounmap(p); |
307 | } | 307 | } |
308 | } | 308 | } |
309 | 309 | ||
310 | #define NI8420_INT_ENABLE_REG 0x38 | 310 | #define NI8420_INT_ENABLE_REG 0x38 |
311 | #define NI8420_INT_ENABLE_BIT 0x2000 | 311 | #define NI8420_INT_ENABLE_BIT 0x2000 |
312 | 312 | ||
313 | static void pci_ni8420_exit(struct pci_dev *dev) | 313 | static void pci_ni8420_exit(struct pci_dev *dev) |
314 | { | 314 | { |
315 | void __iomem *p; | 315 | void __iomem *p; |
316 | unsigned int bar = 0; | 316 | unsigned int bar = 0; |
317 | 317 | ||
318 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | 318 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { |
319 | moan_device("no memory in bar", dev); | 319 | moan_device("no memory in bar", dev); |
320 | return; | 320 | return; |
321 | } | 321 | } |
322 | 322 | ||
323 | p = pci_ioremap_bar(dev, bar); | 323 | p = pci_ioremap_bar(dev, bar); |
324 | if (p == NULL) | 324 | if (p == NULL) |
325 | return; | 325 | return; |
326 | 326 | ||
327 | /* Disable the CPU Interrupt */ | 327 | /* Disable the CPU Interrupt */ |
328 | writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), | 328 | writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), |
329 | p + NI8420_INT_ENABLE_REG); | 329 | p + NI8420_INT_ENABLE_REG); |
330 | iounmap(p); | 330 | iounmap(p); |
331 | } | 331 | } |
332 | 332 | ||
333 | 333 | ||
334 | /* MITE registers */ | 334 | /* MITE registers */ |
335 | #define MITE_IOWBSR1 0xc4 | 335 | #define MITE_IOWBSR1 0xc4 |
336 | #define MITE_IOWCR1 0xf4 | 336 | #define MITE_IOWCR1 0xf4 |
337 | #define MITE_LCIMR1 0x08 | 337 | #define MITE_LCIMR1 0x08 |
338 | #define MITE_LCIMR2 0x10 | 338 | #define MITE_LCIMR2 0x10 |
339 | 339 | ||
340 | #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) | 340 | #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) |
341 | 341 | ||
342 | static void pci_ni8430_exit(struct pci_dev *dev) | 342 | static void pci_ni8430_exit(struct pci_dev *dev) |
343 | { | 343 | { |
344 | void __iomem *p; | 344 | void __iomem *p; |
345 | unsigned int bar = 0; | 345 | unsigned int bar = 0; |
346 | 346 | ||
347 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | 347 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { |
348 | moan_device("no memory in bar", dev); | 348 | moan_device("no memory in bar", dev); |
349 | return; | 349 | return; |
350 | } | 350 | } |
351 | 351 | ||
352 | p = pci_ioremap_bar(dev, bar); | 352 | p = pci_ioremap_bar(dev, bar); |
353 | if (p == NULL) | 353 | if (p == NULL) |
354 | return; | 354 | return; |
355 | 355 | ||
356 | /* Disable the CPU Interrupt */ | 356 | /* Disable the CPU Interrupt */ |
357 | writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); | 357 | writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); |
358 | iounmap(p); | 358 | iounmap(p); |
359 | } | 359 | } |
360 | 360 | ||
361 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ | 361 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ |
362 | static int | 362 | static int |
363 | sbs_setup(struct serial_private *priv, const struct pciserial_board *board, | 363 | sbs_setup(struct serial_private *priv, const struct pciserial_board *board, |
364 | struct uart_8250_port *port, int idx) | 364 | struct uart_8250_port *port, int idx) |
365 | { | 365 | { |
366 | unsigned int bar, offset = board->first_offset; | 366 | unsigned int bar, offset = board->first_offset; |
367 | 367 | ||
368 | bar = 0; | 368 | bar = 0; |
369 | 369 | ||
370 | if (idx < 4) { | 370 | if (idx < 4) { |
371 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ | 371 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ |
372 | offset += idx * board->uart_offset; | 372 | offset += idx * board->uart_offset; |
373 | } else if (idx < 8) { | 373 | } else if (idx < 8) { |
374 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ | 374 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ |
375 | offset += idx * board->uart_offset + 0xC00; | 375 | offset += idx * board->uart_offset + 0xC00; |
376 | } else /* we have only 8 ports on PMC-OCTALPRO */ | 376 | } else /* we have only 8 ports on PMC-OCTALPRO */ |
377 | return 1; | 377 | return 1; |
378 | 378 | ||
379 | return setup_port(priv, port, bar, offset, board->reg_shift); | 379 | return setup_port(priv, port, bar, offset, board->reg_shift); |
380 | } | 380 | } |
381 | 381 | ||
382 | /* | 382 | /* |
383 | * This does initialization for PMC OCTALPRO cards: | 383 | * This does initialization for PMC OCTALPRO cards: |
384 | * maps the device memory, resets the UARTs (needed, bc | 384 | * maps the device memory, resets the UARTs (needed, bc |
385 | * if the module is removed and inserted again, the card | 385 | * if the module is removed and inserted again, the card |
386 | * is in the sleep mode) and enables global interrupt. | 386 | * is in the sleep mode) and enables global interrupt. |
387 | */ | 387 | */ |
388 | 388 | ||
389 | /* global control register offset for SBS PMC-OctalPro */ | 389 | /* global control register offset for SBS PMC-OctalPro */ |
390 | #define OCT_REG_CR_OFF 0x500 | 390 | #define OCT_REG_CR_OFF 0x500 |
391 | 391 | ||
392 | static int sbs_init(struct pci_dev *dev) | 392 | static int sbs_init(struct pci_dev *dev) |
393 | { | 393 | { |
394 | u8 __iomem *p; | 394 | u8 __iomem *p; |
395 | 395 | ||
396 | p = pci_ioremap_bar(dev, 0); | 396 | p = pci_ioremap_bar(dev, 0); |
397 | 397 | ||
398 | if (p == NULL) | 398 | if (p == NULL) |
399 | return -ENOMEM; | 399 | return -ENOMEM; |
400 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ | 400 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ |
401 | writeb(0x10, p + OCT_REG_CR_OFF); | 401 | writeb(0x10, p + OCT_REG_CR_OFF); |
402 | udelay(50); | 402 | udelay(50); |
403 | writeb(0x0, p + OCT_REG_CR_OFF); | 403 | writeb(0x0, p + OCT_REG_CR_OFF); |
404 | 404 | ||
405 | /* Set bit-2 (INTENABLE) of Control Register */ | 405 | /* Set bit-2 (INTENABLE) of Control Register */ |
406 | writeb(0x4, p + OCT_REG_CR_OFF); | 406 | writeb(0x4, p + OCT_REG_CR_OFF); |
407 | iounmap(p); | 407 | iounmap(p); |
408 | 408 | ||
409 | return 0; | 409 | return 0; |
410 | } | 410 | } |
411 | 411 | ||
412 | /* | 412 | /* |
413 | * Disables the global interrupt of PMC-OctalPro | 413 | * Disables the global interrupt of PMC-OctalPro |
414 | */ | 414 | */ |
415 | 415 | ||
416 | static void sbs_exit(struct pci_dev *dev) | 416 | static void sbs_exit(struct pci_dev *dev) |
417 | { | 417 | { |
418 | u8 __iomem *p; | 418 | u8 __iomem *p; |
419 | 419 | ||
420 | p = pci_ioremap_bar(dev, 0); | 420 | p = pci_ioremap_bar(dev, 0); |
421 | /* FIXME: What if resource_len < OCT_REG_CR_OFF */ | 421 | /* FIXME: What if resource_len < OCT_REG_CR_OFF */ |
422 | if (p != NULL) | 422 | if (p != NULL) |
423 | writeb(0, p + OCT_REG_CR_OFF); | 423 | writeb(0, p + OCT_REG_CR_OFF); |
424 | iounmap(p); | 424 | iounmap(p); |
425 | } | 425 | } |
426 | 426 | ||
427 | /* | 427 | /* |
428 | * SIIG serial cards have an PCI interface chip which also controls | 428 | * SIIG serial cards have an PCI interface chip which also controls |
429 | * the UART clocking frequency. Each UART can be clocked independently | 429 | * the UART clocking frequency. Each UART can be clocked independently |
430 | * (except cards equipped with 4 UARTs) and initial clocking settings | 430 | * (except cards equipped with 4 UARTs) and initial clocking settings |
431 | * are stored in the EEPROM chip. It can cause problems because this | 431 | * are stored in the EEPROM chip. It can cause problems because this |
432 | * version of serial driver doesn't support differently clocked UART's | 432 | * version of serial driver doesn't support differently clocked UART's |
433 | * on single PCI card. To prevent this, initialization functions set | 433 | * on single PCI card. To prevent this, initialization functions set |
434 | * high frequency clocking for all UART's on given card. It is safe (I | 434 | * high frequency clocking for all UART's on given card. It is safe (I |
435 | * hope) because it doesn't touch EEPROM settings to prevent conflicts | 435 | * hope) because it doesn't touch EEPROM settings to prevent conflicts |
436 | * with other OSes (like M$ DOS). | 436 | * with other OSes (like M$ DOS). |
437 | * | 437 | * |
438 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 | 438 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 |
439 | * | 439 | * |
440 | * There is two family of SIIG serial cards with different PCI | 440 | * There is two family of SIIG serial cards with different PCI |
441 | * interface chip and different configuration methods: | 441 | * interface chip and different configuration methods: |
442 | * - 10x cards have control registers in IO and/or memory space; | 442 | * - 10x cards have control registers in IO and/or memory space; |
443 | * - 20x cards have control registers in standard PCI configuration space. | 443 | * - 20x cards have control registers in standard PCI configuration space. |
444 | * | 444 | * |
445 | * Note: all 10x cards have PCI device ids 0x10.. | 445 | * Note: all 10x cards have PCI device ids 0x10.. |
446 | * all 20x cards have PCI device ids 0x20.. | 446 | * all 20x cards have PCI device ids 0x20.. |
447 | * | 447 | * |
448 | * There are also Quartet Serial cards which use Oxford Semiconductor | 448 | * There are also Quartet Serial cards which use Oxford Semiconductor |
449 | * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. | 449 | * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. |
450 | * | 450 | * |
451 | * Note: some SIIG cards are probed by the parport_serial object. | 451 | * Note: some SIIG cards are probed by the parport_serial object. |
452 | */ | 452 | */ |
453 | 453 | ||
454 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) | 454 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) |
455 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) | 455 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) |
456 | 456 | ||
457 | static int pci_siig10x_init(struct pci_dev *dev) | 457 | static int pci_siig10x_init(struct pci_dev *dev) |
458 | { | 458 | { |
459 | u16 data; | 459 | u16 data; |
460 | void __iomem *p; | 460 | void __iomem *p; |
461 | 461 | ||
462 | switch (dev->device & 0xfff8) { | 462 | switch (dev->device & 0xfff8) { |
463 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ | 463 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ |
464 | data = 0xffdf; | 464 | data = 0xffdf; |
465 | break; | 465 | break; |
466 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ | 466 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ |
467 | data = 0xf7ff; | 467 | data = 0xf7ff; |
468 | break; | 468 | break; |
469 | default: /* 1S1P, 4S */ | 469 | default: /* 1S1P, 4S */ |
470 | data = 0xfffb; | 470 | data = 0xfffb; |
471 | break; | 471 | break; |
472 | } | 472 | } |
473 | 473 | ||
474 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); | 474 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
475 | if (p == NULL) | 475 | if (p == NULL) |
476 | return -ENOMEM; | 476 | return -ENOMEM; |
477 | 477 | ||
478 | writew(readw(p + 0x28) & data, p + 0x28); | 478 | writew(readw(p + 0x28) & data, p + 0x28); |
479 | readw(p + 0x28); | 479 | readw(p + 0x28); |
480 | iounmap(p); | 480 | iounmap(p); |
481 | return 0; | 481 | return 0; |
482 | } | 482 | } |
483 | 483 | ||
484 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) | 484 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) |
485 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) | 485 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) |
486 | 486 | ||
487 | static int pci_siig20x_init(struct pci_dev *dev) | 487 | static int pci_siig20x_init(struct pci_dev *dev) |
488 | { | 488 | { |
489 | u8 data; | 489 | u8 data; |
490 | 490 | ||
491 | /* Change clock frequency for the first UART. */ | 491 | /* Change clock frequency for the first UART. */ |
492 | pci_read_config_byte(dev, 0x6f, &data); | 492 | pci_read_config_byte(dev, 0x6f, &data); |
493 | pci_write_config_byte(dev, 0x6f, data & 0xef); | 493 | pci_write_config_byte(dev, 0x6f, data & 0xef); |
494 | 494 | ||
495 | /* If this card has 2 UART, we have to do the same with second UART. */ | 495 | /* If this card has 2 UART, we have to do the same with second UART. */ |
496 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || | 496 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || |
497 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { | 497 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { |
498 | pci_read_config_byte(dev, 0x73, &data); | 498 | pci_read_config_byte(dev, 0x73, &data); |
499 | pci_write_config_byte(dev, 0x73, data & 0xef); | 499 | pci_write_config_byte(dev, 0x73, data & 0xef); |
500 | } | 500 | } |
501 | return 0; | 501 | return 0; |
502 | } | 502 | } |
503 | 503 | ||
504 | static int pci_siig_init(struct pci_dev *dev) | 504 | static int pci_siig_init(struct pci_dev *dev) |
505 | { | 505 | { |
506 | unsigned int type = dev->device & 0xff00; | 506 | unsigned int type = dev->device & 0xff00; |
507 | 507 | ||
508 | if (type == 0x1000) | 508 | if (type == 0x1000) |
509 | return pci_siig10x_init(dev); | 509 | return pci_siig10x_init(dev); |
510 | else if (type == 0x2000) | 510 | else if (type == 0x2000) |
511 | return pci_siig20x_init(dev); | 511 | return pci_siig20x_init(dev); |
512 | 512 | ||
513 | moan_device("Unknown SIIG card", dev); | 513 | moan_device("Unknown SIIG card", dev); |
514 | return -ENODEV; | 514 | return -ENODEV; |
515 | } | 515 | } |
516 | 516 | ||
517 | static int pci_siig_setup(struct serial_private *priv, | 517 | static int pci_siig_setup(struct serial_private *priv, |
518 | const struct pciserial_board *board, | 518 | const struct pciserial_board *board, |
519 | struct uart_8250_port *port, int idx) | 519 | struct uart_8250_port *port, int idx) |
520 | { | 520 | { |
521 | unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; | 521 | unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; |
522 | 522 | ||
523 | if (idx > 3) { | 523 | if (idx > 3) { |
524 | bar = 4; | 524 | bar = 4; |
525 | offset = (idx - 4) * 8; | 525 | offset = (idx - 4) * 8; |
526 | } | 526 | } |
527 | 527 | ||
528 | return setup_port(priv, port, bar, offset, 0); | 528 | return setup_port(priv, port, bar, offset, 0); |
529 | } | 529 | } |
530 | 530 | ||
531 | /* | 531 | /* |
532 | * Timedia has an explosion of boards, and to avoid the PCI table from | 532 | * Timedia has an explosion of boards, and to avoid the PCI table from |
533 | * growing *huge*, we use this function to collapse some 70 entries | 533 | * growing *huge*, we use this function to collapse some 70 entries |
534 | * in the PCI table into one, for sanity's and compactness's sake. | 534 | * in the PCI table into one, for sanity's and compactness's sake. |
535 | */ | 535 | */ |
536 | static const unsigned short timedia_single_port[] = { | 536 | static const unsigned short timedia_single_port[] = { |
537 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 | 537 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 |
538 | }; | 538 | }; |
539 | 539 | ||
540 | static const unsigned short timedia_dual_port[] = { | 540 | static const unsigned short timedia_dual_port[] = { |
541 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, | 541 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, |
542 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, | 542 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, |
543 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, | 543 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, |
544 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, | 544 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, |
545 | 0xD079, 0 | 545 | 0xD079, 0 |
546 | }; | 546 | }; |
547 | 547 | ||
548 | static const unsigned short timedia_quad_port[] = { | 548 | static const unsigned short timedia_quad_port[] = { |
549 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, | 549 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, |
550 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, | 550 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, |
551 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, | 551 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, |
552 | 0xB157, 0 | 552 | 0xB157, 0 |
553 | }; | 553 | }; |
554 | 554 | ||
555 | static const unsigned short timedia_eight_port[] = { | 555 | static const unsigned short timedia_eight_port[] = { |
556 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, | 556 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, |
557 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 | 557 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 |
558 | }; | 558 | }; |
559 | 559 | ||
560 | static const struct timedia_struct { | 560 | static const struct timedia_struct { |
561 | int num; | 561 | int num; |
562 | const unsigned short *ids; | 562 | const unsigned short *ids; |
563 | } timedia_data[] = { | 563 | } timedia_data[] = { |
564 | { 1, timedia_single_port }, | 564 | { 1, timedia_single_port }, |
565 | { 2, timedia_dual_port }, | 565 | { 2, timedia_dual_port }, |
566 | { 4, timedia_quad_port }, | 566 | { 4, timedia_quad_port }, |
567 | { 8, timedia_eight_port } | 567 | { 8, timedia_eight_port } |
568 | }; | 568 | }; |
569 | 569 | ||
570 | /* | 570 | /* |
571 | * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of | 571 | * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of |
572 | * listing them individually, this driver merely grabs them all with | 572 | * listing them individually, this driver merely grabs them all with |
573 | * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, | 573 | * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, |
574 | * and should be left free to be claimed by parport_serial instead. | 574 | * and should be left free to be claimed by parport_serial instead. |
575 | */ | 575 | */ |
576 | static int pci_timedia_probe(struct pci_dev *dev) | 576 | static int pci_timedia_probe(struct pci_dev *dev) |
577 | { | 577 | { |
578 | /* | 578 | /* |
579 | * Check the third digit of the subdevice ID | 579 | * Check the third digit of the subdevice ID |
580 | * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) | 580 | * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) |
581 | */ | 581 | */ |
582 | if ((dev->subsystem_device & 0x00f0) >= 0x70) { | 582 | if ((dev->subsystem_device & 0x00f0) >= 0x70) { |
583 | dev_info(&dev->dev, | 583 | dev_info(&dev->dev, |
584 | "ignoring Timedia subdevice %04x for parport_serial\n", | 584 | "ignoring Timedia subdevice %04x for parport_serial\n", |
585 | dev->subsystem_device); | 585 | dev->subsystem_device); |
586 | return -ENODEV; | 586 | return -ENODEV; |
587 | } | 587 | } |
588 | 588 | ||
589 | return 0; | 589 | return 0; |
590 | } | 590 | } |
591 | 591 | ||
592 | static int pci_timedia_init(struct pci_dev *dev) | 592 | static int pci_timedia_init(struct pci_dev *dev) |
593 | { | 593 | { |
594 | const unsigned short *ids; | 594 | const unsigned short *ids; |
595 | int i, j; | 595 | int i, j; |
596 | 596 | ||
597 | for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { | 597 | for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { |
598 | ids = timedia_data[i].ids; | 598 | ids = timedia_data[i].ids; |
599 | for (j = 0; ids[j]; j++) | 599 | for (j = 0; ids[j]; j++) |
600 | if (dev->subsystem_device == ids[j]) | 600 | if (dev->subsystem_device == ids[j]) |
601 | return timedia_data[i].num; | 601 | return timedia_data[i].num; |
602 | } | 602 | } |
603 | return 0; | 603 | return 0; |
604 | } | 604 | } |
605 | 605 | ||
606 | /* | 606 | /* |
607 | * Timedia/SUNIX uses a mixture of BARs and offsets | 607 | * Timedia/SUNIX uses a mixture of BARs and offsets |
608 | * Ugh, this is ugly as all hell --- TYT | 608 | * Ugh, this is ugly as all hell --- TYT |
609 | */ | 609 | */ |
610 | static int | 610 | static int |
611 | pci_timedia_setup(struct serial_private *priv, | 611 | pci_timedia_setup(struct serial_private *priv, |
612 | const struct pciserial_board *board, | 612 | const struct pciserial_board *board, |
613 | struct uart_8250_port *port, int idx) | 613 | struct uart_8250_port *port, int idx) |
614 | { | 614 | { |
615 | unsigned int bar = 0, offset = board->first_offset; | 615 | unsigned int bar = 0, offset = board->first_offset; |
616 | 616 | ||
617 | switch (idx) { | 617 | switch (idx) { |
618 | case 0: | 618 | case 0: |
619 | bar = 0; | 619 | bar = 0; |
620 | break; | 620 | break; |
621 | case 1: | 621 | case 1: |
622 | offset = board->uart_offset; | 622 | offset = board->uart_offset; |
623 | bar = 0; | 623 | bar = 0; |
624 | break; | 624 | break; |
625 | case 2: | 625 | case 2: |
626 | bar = 1; | 626 | bar = 1; |
627 | break; | 627 | break; |
628 | case 3: | 628 | case 3: |
629 | offset = board->uart_offset; | 629 | offset = board->uart_offset; |
630 | /* FALLTHROUGH */ | 630 | /* FALLTHROUGH */ |
631 | case 4: /* BAR 2 */ | 631 | case 4: /* BAR 2 */ |
632 | case 5: /* BAR 3 */ | 632 | case 5: /* BAR 3 */ |
633 | case 6: /* BAR 4 */ | 633 | case 6: /* BAR 4 */ |
634 | case 7: /* BAR 5 */ | 634 | case 7: /* BAR 5 */ |
635 | bar = idx - 2; | 635 | bar = idx - 2; |
636 | } | 636 | } |
637 | 637 | ||
638 | return setup_port(priv, port, bar, offset, board->reg_shift); | 638 | return setup_port(priv, port, bar, offset, board->reg_shift); |
639 | } | 639 | } |
640 | 640 | ||
641 | /* | 641 | /* |
642 | * Some Titan cards are also a little weird | 642 | * Some Titan cards are also a little weird |
643 | */ | 643 | */ |
644 | static int | 644 | static int |
645 | titan_400l_800l_setup(struct serial_private *priv, | 645 | titan_400l_800l_setup(struct serial_private *priv, |
646 | const struct pciserial_board *board, | 646 | const struct pciserial_board *board, |
647 | struct uart_8250_port *port, int idx) | 647 | struct uart_8250_port *port, int idx) |
648 | { | 648 | { |
649 | unsigned int bar, offset = board->first_offset; | 649 | unsigned int bar, offset = board->first_offset; |
650 | 650 | ||
651 | switch (idx) { | 651 | switch (idx) { |
652 | case 0: | 652 | case 0: |
653 | bar = 1; | 653 | bar = 1; |
654 | break; | 654 | break; |
655 | case 1: | 655 | case 1: |
656 | bar = 2; | 656 | bar = 2; |
657 | break; | 657 | break; |
658 | default: | 658 | default: |
659 | bar = 4; | 659 | bar = 4; |
660 | offset = (idx - 2) * board->uart_offset; | 660 | offset = (idx - 2) * board->uart_offset; |
661 | } | 661 | } |
662 | 662 | ||
663 | return setup_port(priv, port, bar, offset, board->reg_shift); | 663 | return setup_port(priv, port, bar, offset, board->reg_shift); |
664 | } | 664 | } |
665 | 665 | ||
666 | static int pci_xircom_init(struct pci_dev *dev) | 666 | static int pci_xircom_init(struct pci_dev *dev) |
667 | { | 667 | { |
668 | msleep(100); | 668 | msleep(100); |
669 | return 0; | 669 | return 0; |
670 | } | 670 | } |
671 | 671 | ||
672 | static int pci_ni8420_init(struct pci_dev *dev) | 672 | static int pci_ni8420_init(struct pci_dev *dev) |
673 | { | 673 | { |
674 | void __iomem *p; | 674 | void __iomem *p; |
675 | unsigned int bar = 0; | 675 | unsigned int bar = 0; |
676 | 676 | ||
677 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | 677 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { |
678 | moan_device("no memory in bar", dev); | 678 | moan_device("no memory in bar", dev); |
679 | return 0; | 679 | return 0; |
680 | } | 680 | } |
681 | 681 | ||
682 | p = pci_ioremap_bar(dev, bar); | 682 | p = pci_ioremap_bar(dev, bar); |
683 | if (p == NULL) | 683 | if (p == NULL) |
684 | return -ENOMEM; | 684 | return -ENOMEM; |
685 | 685 | ||
686 | /* Enable CPU Interrupt */ | 686 | /* Enable CPU Interrupt */ |
687 | writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, | 687 | writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, |
688 | p + NI8420_INT_ENABLE_REG); | 688 | p + NI8420_INT_ENABLE_REG); |
689 | 689 | ||
690 | iounmap(p); | 690 | iounmap(p); |
691 | return 0; | 691 | return 0; |
692 | } | 692 | } |
693 | 693 | ||
694 | #define MITE_IOWBSR1_WSIZE 0xa | 694 | #define MITE_IOWBSR1_WSIZE 0xa |
695 | #define MITE_IOWBSR1_WIN_OFFSET 0x800 | 695 | #define MITE_IOWBSR1_WIN_OFFSET 0x800 |
696 | #define MITE_IOWBSR1_WENAB (1 << 7) | 696 | #define MITE_IOWBSR1_WENAB (1 << 7) |
697 | #define MITE_LCIMR1_IO_IE_0 (1 << 24) | 697 | #define MITE_LCIMR1_IO_IE_0 (1 << 24) |
698 | #define MITE_LCIMR2_SET_CPU_IE (1 << 31) | 698 | #define MITE_LCIMR2_SET_CPU_IE (1 << 31) |
699 | #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe | 699 | #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe |
700 | 700 | ||
701 | static int pci_ni8430_init(struct pci_dev *dev) | 701 | static int pci_ni8430_init(struct pci_dev *dev) |
702 | { | 702 | { |
703 | void __iomem *p; | 703 | void __iomem *p; |
704 | struct pci_bus_region region; | 704 | struct pci_bus_region region; |
705 | u32 device_window; | 705 | u32 device_window; |
706 | unsigned int bar = 0; | 706 | unsigned int bar = 0; |
707 | 707 | ||
708 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | 708 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { |
709 | moan_device("no memory in bar", dev); | 709 | moan_device("no memory in bar", dev); |
710 | return 0; | 710 | return 0; |
711 | } | 711 | } |
712 | 712 | ||
713 | p = pci_ioremap_bar(dev, bar); | 713 | p = pci_ioremap_bar(dev, bar); |
714 | if (p == NULL) | 714 | if (p == NULL) |
715 | return -ENOMEM; | 715 | return -ENOMEM; |
716 | 716 | ||
717 | /* | 717 | /* |
718 | * Set device window address and size in BAR0, while acknowledging that | 718 | * Set device window address and size in BAR0, while acknowledging that |
719 | * the resource structure may contain a translated address that differs | 719 | * the resource structure may contain a translated address that differs |
720 | * from the address the device responds to. | 720 | * from the address the device responds to. |
721 | */ | 721 | */ |
722 | pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); | 722 | pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); |
723 | device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) | 723 | device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) |
724 | | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; | 724 | | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; |
725 | writel(device_window, p + MITE_IOWBSR1); | 725 | writel(device_window, p + MITE_IOWBSR1); |
726 | 726 | ||
727 | /* Set window access to go to RAMSEL IO address space */ | 727 | /* Set window access to go to RAMSEL IO address space */ |
728 | writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), | 728 | writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), |
729 | p + MITE_IOWCR1); | 729 | p + MITE_IOWCR1); |
730 | 730 | ||
731 | /* Enable IO Bus Interrupt 0 */ | 731 | /* Enable IO Bus Interrupt 0 */ |
732 | writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); | 732 | writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); |
733 | 733 | ||
734 | /* Enable CPU Interrupt */ | 734 | /* Enable CPU Interrupt */ |
735 | writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); | 735 | writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); |
736 | 736 | ||
737 | iounmap(p); | 737 | iounmap(p); |
738 | return 0; | 738 | return 0; |
739 | } | 739 | } |
740 | 740 | ||
741 | /* UART Port Control Register */ | 741 | /* UART Port Control Register */ |
742 | #define NI8430_PORTCON 0x0f | 742 | #define NI8430_PORTCON 0x0f |
743 | #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) | 743 | #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) |
744 | 744 | ||
745 | static int | 745 | static int |
746 | pci_ni8430_setup(struct serial_private *priv, | 746 | pci_ni8430_setup(struct serial_private *priv, |
747 | const struct pciserial_board *board, | 747 | const struct pciserial_board *board, |
748 | struct uart_8250_port *port, int idx) | 748 | struct uart_8250_port *port, int idx) |
749 | { | 749 | { |
750 | struct pci_dev *dev = priv->dev; | 750 | struct pci_dev *dev = priv->dev; |
751 | void __iomem *p; | 751 | void __iomem *p; |
752 | unsigned int bar, offset = board->first_offset; | 752 | unsigned int bar, offset = board->first_offset; |
753 | 753 | ||
754 | if (idx >= board->num_ports) | 754 | if (idx >= board->num_ports) |
755 | return 1; | 755 | return 1; |
756 | 756 | ||
757 | bar = FL_GET_BASE(board->flags); | 757 | bar = FL_GET_BASE(board->flags); |
758 | offset += idx * board->uart_offset; | 758 | offset += idx * board->uart_offset; |
759 | 759 | ||
760 | p = pci_ioremap_bar(dev, bar); | 760 | p = pci_ioremap_bar(dev, bar); |
761 | if (!p) | 761 | if (!p) |
762 | return -ENOMEM; | 762 | return -ENOMEM; |
763 | 763 | ||
764 | /* enable the transceiver */ | 764 | /* enable the transceiver */ |
765 | writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, | 765 | writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, |
766 | p + offset + NI8430_PORTCON); | 766 | p + offset + NI8430_PORTCON); |
767 | 767 | ||
768 | iounmap(p); | 768 | iounmap(p); |
769 | 769 | ||
770 | return setup_port(priv, port, bar, offset, board->reg_shift); | 770 | return setup_port(priv, port, bar, offset, board->reg_shift); |
771 | } | 771 | } |
772 | 772 | ||
773 | static int pci_netmos_9900_setup(struct serial_private *priv, | 773 | static int pci_netmos_9900_setup(struct serial_private *priv, |
774 | const struct pciserial_board *board, | 774 | const struct pciserial_board *board, |
775 | struct uart_8250_port *port, int idx) | 775 | struct uart_8250_port *port, int idx) |
776 | { | 776 | { |
777 | unsigned int bar; | 777 | unsigned int bar; |
778 | 778 | ||
779 | if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && | 779 | if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && |
780 | (priv->dev->subsystem_device & 0xff00) == 0x3000) { | 780 | (priv->dev->subsystem_device & 0xff00) == 0x3000) { |
781 | /* netmos apparently orders BARs by datasheet layout, so serial | 781 | /* netmos apparently orders BARs by datasheet layout, so serial |
782 | * ports get BARs 0 and 3 (or 1 and 4 for memmapped) | 782 | * ports get BARs 0 and 3 (or 1 and 4 for memmapped) |
783 | */ | 783 | */ |
784 | bar = 3 * idx; | 784 | bar = 3 * idx; |
785 | 785 | ||
786 | return setup_port(priv, port, bar, 0, board->reg_shift); | 786 | return setup_port(priv, port, bar, 0, board->reg_shift); |
787 | } else { | 787 | } else { |
788 | return pci_default_setup(priv, board, port, idx); | 788 | return pci_default_setup(priv, board, port, idx); |
789 | } | 789 | } |
790 | } | 790 | } |
791 | 791 | ||
792 | /* the 99xx series comes with a range of device IDs and a variety | 792 | /* the 99xx series comes with a range of device IDs and a variety |
793 | * of capabilities: | 793 | * of capabilities: |
794 | * | 794 | * |
795 | * 9900 has varying capabilities and can cascade to sub-controllers | 795 | * 9900 has varying capabilities and can cascade to sub-controllers |
796 | * (cascading should be purely internal) | 796 | * (cascading should be purely internal) |
797 | * 9904 is hardwired with 4 serial ports | 797 | * 9904 is hardwired with 4 serial ports |
798 | * 9912 and 9922 are hardwired with 2 serial ports | 798 | * 9912 and 9922 are hardwired with 2 serial ports |
799 | */ | 799 | */ |
800 | static int pci_netmos_9900_numports(struct pci_dev *dev) | 800 | static int pci_netmos_9900_numports(struct pci_dev *dev) |
801 | { | 801 | { |
802 | unsigned int c = dev->class; | 802 | unsigned int c = dev->class; |
803 | unsigned int pi; | 803 | unsigned int pi; |
804 | unsigned short sub_serports; | 804 | unsigned short sub_serports; |
805 | 805 | ||
806 | pi = (c & 0xff); | 806 | pi = (c & 0xff); |
807 | 807 | ||
808 | if (pi == 2) { | 808 | if (pi == 2) { |
809 | return 1; | 809 | return 1; |
810 | } else if ((pi == 0) && | 810 | } else if ((pi == 0) && |
811 | (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { | 811 | (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { |
812 | /* two possibilities: 0x30ps encodes number of parallel and | 812 | /* two possibilities: 0x30ps encodes number of parallel and |
813 | * serial ports, or 0x1000 indicates *something*. This is not | 813 | * serial ports, or 0x1000 indicates *something*. This is not |
814 | * immediately obvious, since the 2s1p+4s configuration seems | 814 | * immediately obvious, since the 2s1p+4s configuration seems |
815 | * to offer all functionality on functions 0..2, while still | 815 | * to offer all functionality on functions 0..2, while still |
816 | * advertising the same function 3 as the 4s+2s1p config. | 816 | * advertising the same function 3 as the 4s+2s1p config. |
817 | */ | 817 | */ |
818 | sub_serports = dev->subsystem_device & 0xf; | 818 | sub_serports = dev->subsystem_device & 0xf; |
819 | if (sub_serports > 0) { | 819 | if (sub_serports > 0) { |
820 | return sub_serports; | 820 | return sub_serports; |
821 | } else { | 821 | } else { |
822 | dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); | 822 | dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); |
823 | return 0; | 823 | return 0; |
824 | } | 824 | } |
825 | } | 825 | } |
826 | 826 | ||
827 | moan_device("unknown NetMos/Mostech program interface", dev); | 827 | moan_device("unknown NetMos/Mostech program interface", dev); |
828 | return 0; | 828 | return 0; |
829 | } | 829 | } |
830 | 830 | ||
831 | static int pci_netmos_init(struct pci_dev *dev) | 831 | static int pci_netmos_init(struct pci_dev *dev) |
832 | { | 832 | { |
833 | /* subdevice 0x00PS means <P> parallel, <S> serial */ | 833 | /* subdevice 0x00PS means <P> parallel, <S> serial */ |
834 | unsigned int num_serial = dev->subsystem_device & 0xf; | 834 | unsigned int num_serial = dev->subsystem_device & 0xf; |
835 | 835 | ||
836 | if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || | 836 | if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || |
837 | (dev->device == PCI_DEVICE_ID_NETMOS_9865)) | 837 | (dev->device == PCI_DEVICE_ID_NETMOS_9865)) |
838 | return 0; | 838 | return 0; |
839 | 839 | ||
840 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | 840 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && |
841 | dev->subsystem_device == 0x0299) | 841 | dev->subsystem_device == 0x0299) |
842 | return 0; | 842 | return 0; |
843 | 843 | ||
844 | switch (dev->device) { /* FALLTHROUGH on all */ | 844 | switch (dev->device) { /* FALLTHROUGH on all */ |
845 | case PCI_DEVICE_ID_NETMOS_9904: | 845 | case PCI_DEVICE_ID_NETMOS_9904: |
846 | case PCI_DEVICE_ID_NETMOS_9912: | 846 | case PCI_DEVICE_ID_NETMOS_9912: |
847 | case PCI_DEVICE_ID_NETMOS_9922: | 847 | case PCI_DEVICE_ID_NETMOS_9922: |
848 | case PCI_DEVICE_ID_NETMOS_9900: | 848 | case PCI_DEVICE_ID_NETMOS_9900: |
849 | num_serial = pci_netmos_9900_numports(dev); | 849 | num_serial = pci_netmos_9900_numports(dev); |
850 | break; | 850 | break; |
851 | 851 | ||
852 | default: | 852 | default: |
853 | if (num_serial == 0 ) { | 853 | if (num_serial == 0 ) { |
854 | moan_device("unknown NetMos/Mostech device", dev); | 854 | moan_device("unknown NetMos/Mostech device", dev); |
855 | } | 855 | } |
856 | } | 856 | } |
857 | 857 | ||
858 | if (num_serial == 0) | 858 | if (num_serial == 0) |
859 | return -ENODEV; | 859 | return -ENODEV; |
860 | 860 | ||
861 | return num_serial; | 861 | return num_serial; |
862 | } | 862 | } |
863 | 863 | ||
864 | /* | 864 | /* |
865 | * These chips are available with optionally one parallel port and up to | 865 | * These chips are available with optionally one parallel port and up to |
866 | * two serial ports. Unfortunately they all have the same product id. | 866 | * two serial ports. Unfortunately they all have the same product id. |
867 | * | 867 | * |
868 | * Basic configuration is done over a region of 32 I/O ports. The base | 868 | * Basic configuration is done over a region of 32 I/O ports. The base |
869 | * ioport is called INTA or INTC, depending on docs/other drivers. | 869 | * ioport is called INTA or INTC, depending on docs/other drivers. |
870 | * | 870 | * |
871 | * The region of the 32 I/O ports is configured in POSIO0R... | 871 | * The region of the 32 I/O ports is configured in POSIO0R... |
872 | */ | 872 | */ |
873 | 873 | ||
874 | /* registers */ | 874 | /* registers */ |
875 | #define ITE_887x_MISCR 0x9c | 875 | #define ITE_887x_MISCR 0x9c |
876 | #define ITE_887x_INTCBAR 0x78 | 876 | #define ITE_887x_INTCBAR 0x78 |
877 | #define ITE_887x_UARTBAR 0x7c | 877 | #define ITE_887x_UARTBAR 0x7c |
878 | #define ITE_887x_PS0BAR 0x10 | 878 | #define ITE_887x_PS0BAR 0x10 |
879 | #define ITE_887x_POSIO0 0x60 | 879 | #define ITE_887x_POSIO0 0x60 |
880 | 880 | ||
881 | /* I/O space size */ | 881 | /* I/O space size */ |
882 | #define ITE_887x_IOSIZE 32 | 882 | #define ITE_887x_IOSIZE 32 |
883 | /* I/O space size (bits 26-24; 8 bytes = 011b) */ | 883 | /* I/O space size (bits 26-24; 8 bytes = 011b) */ |
884 | #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) | 884 | #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) |
885 | /* I/O space size (bits 26-24; 32 bytes = 101b) */ | 885 | /* I/O space size (bits 26-24; 32 bytes = 101b) */ |
886 | #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) | 886 | #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) |
887 | /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ | 887 | /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ |
888 | #define ITE_887x_POSIO_SPEED (3 << 29) | 888 | #define ITE_887x_POSIO_SPEED (3 << 29) |
889 | /* enable IO_Space bit */ | 889 | /* enable IO_Space bit */ |
890 | #define ITE_887x_POSIO_ENABLE (1 << 31) | 890 | #define ITE_887x_POSIO_ENABLE (1 << 31) |
891 | 891 | ||
892 | static int pci_ite887x_init(struct pci_dev *dev) | 892 | static int pci_ite887x_init(struct pci_dev *dev) |
893 | { | 893 | { |
894 | /* inta_addr are the configuration addresses of the ITE */ | 894 | /* inta_addr are the configuration addresses of the ITE */ |
895 | static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, | 895 | static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, |
896 | 0x200, 0x280, 0 }; | 896 | 0x200, 0x280, 0 }; |
897 | int ret, i, type; | 897 | int ret, i, type; |
898 | struct resource *iobase = NULL; | 898 | struct resource *iobase = NULL; |
899 | u32 miscr, uartbar, ioport; | 899 | u32 miscr, uartbar, ioport; |
900 | 900 | ||
901 | /* search for the base-ioport */ | 901 | /* search for the base-ioport */ |
902 | i = 0; | 902 | i = 0; |
903 | while (inta_addr[i] && iobase == NULL) { | 903 | while (inta_addr[i] && iobase == NULL) { |
904 | iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, | 904 | iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, |
905 | "ite887x"); | 905 | "ite887x"); |
906 | if (iobase != NULL) { | 906 | if (iobase != NULL) { |
907 | /* write POSIO0R - speed | size | ioport */ | 907 | /* write POSIO0R - speed | size | ioport */ |
908 | pci_write_config_dword(dev, ITE_887x_POSIO0, | 908 | pci_write_config_dword(dev, ITE_887x_POSIO0, |
909 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | | 909 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | |
910 | ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); | 910 | ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); |
911 | /* write INTCBAR - ioport */ | 911 | /* write INTCBAR - ioport */ |
912 | pci_write_config_dword(dev, ITE_887x_INTCBAR, | 912 | pci_write_config_dword(dev, ITE_887x_INTCBAR, |
913 | inta_addr[i]); | 913 | inta_addr[i]); |
914 | ret = inb(inta_addr[i]); | 914 | ret = inb(inta_addr[i]); |
915 | if (ret != 0xff) { | 915 | if (ret != 0xff) { |
916 | /* ioport connected */ | 916 | /* ioport connected */ |
917 | break; | 917 | break; |
918 | } | 918 | } |
919 | release_region(iobase->start, ITE_887x_IOSIZE); | 919 | release_region(iobase->start, ITE_887x_IOSIZE); |
920 | iobase = NULL; | 920 | iobase = NULL; |
921 | } | 921 | } |
922 | i++; | 922 | i++; |
923 | } | 923 | } |
924 | 924 | ||
925 | if (!inta_addr[i]) { | 925 | if (!inta_addr[i]) { |
926 | dev_err(&dev->dev, "ite887x: could not find iobase\n"); | 926 | dev_err(&dev->dev, "ite887x: could not find iobase\n"); |
927 | return -ENODEV; | 927 | return -ENODEV; |
928 | } | 928 | } |
929 | 929 | ||
930 | /* start of undocumented type checking (see parport_pc.c) */ | 930 | /* start of undocumented type checking (see parport_pc.c) */ |
931 | type = inb(iobase->start + 0x18) & 0x0f; | 931 | type = inb(iobase->start + 0x18) & 0x0f; |
932 | 932 | ||
933 | switch (type) { | 933 | switch (type) { |
934 | case 0x2: /* ITE8871 (1P) */ | 934 | case 0x2: /* ITE8871 (1P) */ |
935 | case 0xa: /* ITE8875 (1P) */ | 935 | case 0xa: /* ITE8875 (1P) */ |
936 | ret = 0; | 936 | ret = 0; |
937 | break; | 937 | break; |
938 | case 0xe: /* ITE8872 (2S1P) */ | 938 | case 0xe: /* ITE8872 (2S1P) */ |
939 | ret = 2; | 939 | ret = 2; |
940 | break; | 940 | break; |
941 | case 0x6: /* ITE8873 (1S) */ | 941 | case 0x6: /* ITE8873 (1S) */ |
942 | ret = 1; | 942 | ret = 1; |
943 | break; | 943 | break; |
944 | case 0x8: /* ITE8874 (2S) */ | 944 | case 0x8: /* ITE8874 (2S) */ |
945 | ret = 2; | 945 | ret = 2; |
946 | break; | 946 | break; |
947 | default: | 947 | default: |
948 | moan_device("Unknown ITE887x", dev); | 948 | moan_device("Unknown ITE887x", dev); |
949 | ret = -ENODEV; | 949 | ret = -ENODEV; |
950 | } | 950 | } |
951 | 951 | ||
952 | /* configure all serial ports */ | 952 | /* configure all serial ports */ |
953 | for (i = 0; i < ret; i++) { | 953 | for (i = 0; i < ret; i++) { |
954 | /* read the I/O port from the device */ | 954 | /* read the I/O port from the device */ |
955 | pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), | 955 | pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), |
956 | &ioport); | 956 | &ioport); |
957 | ioport &= 0x0000FF00; /* the actual base address */ | 957 | ioport &= 0x0000FF00; /* the actual base address */ |
958 | pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), | 958 | pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), |
959 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | | 959 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | |
960 | ITE_887x_POSIO_IOSIZE_8 | ioport); | 960 | ITE_887x_POSIO_IOSIZE_8 | ioport); |
961 | 961 | ||
962 | /* write the ioport to the UARTBAR */ | 962 | /* write the ioport to the UARTBAR */ |
963 | pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); | 963 | pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); |
964 | uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ | 964 | uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ |
965 | uartbar |= (ioport << (16 * i)); /* set the ioport */ | 965 | uartbar |= (ioport << (16 * i)); /* set the ioport */ |
966 | pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); | 966 | pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); |
967 | 967 | ||
968 | /* get current config */ | 968 | /* get current config */ |
969 | pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); | 969 | pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); |
970 | /* disable interrupts (UARTx_Routing[3:0]) */ | 970 | /* disable interrupts (UARTx_Routing[3:0]) */ |
971 | miscr &= ~(0xf << (12 - 4 * i)); | 971 | miscr &= ~(0xf << (12 - 4 * i)); |
972 | /* activate the UART (UARTx_En) */ | 972 | /* activate the UART (UARTx_En) */ |
973 | miscr |= 1 << (23 - i); | 973 | miscr |= 1 << (23 - i); |
974 | /* write new config with activated UART */ | 974 | /* write new config with activated UART */ |
975 | pci_write_config_dword(dev, ITE_887x_MISCR, miscr); | 975 | pci_write_config_dword(dev, ITE_887x_MISCR, miscr); |
976 | } | 976 | } |
977 | 977 | ||
978 | if (ret <= 0) { | 978 | if (ret <= 0) { |
979 | /* the device has no UARTs if we get here */ | 979 | /* the device has no UARTs if we get here */ |
980 | release_region(iobase->start, ITE_887x_IOSIZE); | 980 | release_region(iobase->start, ITE_887x_IOSIZE); |
981 | } | 981 | } |
982 | 982 | ||
983 | return ret; | 983 | return ret; |
984 | } | 984 | } |
985 | 985 | ||
986 | static void pci_ite887x_exit(struct pci_dev *dev) | 986 | static void pci_ite887x_exit(struct pci_dev *dev) |
987 | { | 987 | { |
988 | u32 ioport; | 988 | u32 ioport; |
989 | /* the ioport is bit 0-15 in POSIO0R */ | 989 | /* the ioport is bit 0-15 in POSIO0R */ |
990 | pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); | 990 | pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); |
991 | ioport &= 0xffff; | 991 | ioport &= 0xffff; |
992 | release_region(ioport, ITE_887x_IOSIZE); | 992 | release_region(ioport, ITE_887x_IOSIZE); |
993 | } | 993 | } |
994 | 994 | ||
995 | /* | 995 | /* |
996 | * EndRun Technologies. | 996 | * EndRun Technologies. |
997 | * Determine the number of ports available on the device. | 997 | * Determine the number of ports available on the device. |
998 | */ | 998 | */ |
999 | #define PCI_VENDOR_ID_ENDRUN 0x7401 | 999 | #define PCI_VENDOR_ID_ENDRUN 0x7401 |
1000 | #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 | 1000 | #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 |
1001 | 1001 | ||
1002 | static int pci_endrun_init(struct pci_dev *dev) | 1002 | static int pci_endrun_init(struct pci_dev *dev) |
1003 | { | 1003 | { |
1004 | u8 __iomem *p; | 1004 | u8 __iomem *p; |
1005 | unsigned long deviceID; | 1005 | unsigned long deviceID; |
1006 | unsigned int number_uarts = 0; | 1006 | unsigned int number_uarts = 0; |
1007 | 1007 | ||
1008 | /* EndRun device is all 0xexxx */ | 1008 | /* EndRun device is all 0xexxx */ |
1009 | if (dev->vendor == PCI_VENDOR_ID_ENDRUN && | 1009 | if (dev->vendor == PCI_VENDOR_ID_ENDRUN && |
1010 | (dev->device & 0xf000) != 0xe000) | 1010 | (dev->device & 0xf000) != 0xe000) |
1011 | return 0; | 1011 | return 0; |
1012 | 1012 | ||
1013 | p = pci_iomap(dev, 0, 5); | 1013 | p = pci_iomap(dev, 0, 5); |
1014 | if (p == NULL) | 1014 | if (p == NULL) |
1015 | return -ENOMEM; | 1015 | return -ENOMEM; |
1016 | 1016 | ||
1017 | deviceID = ioread32(p); | 1017 | deviceID = ioread32(p); |
1018 | /* EndRun device */ | 1018 | /* EndRun device */ |
1019 | if (deviceID == 0x07000200) { | 1019 | if (deviceID == 0x07000200) { |
1020 | number_uarts = ioread8(p + 4); | 1020 | number_uarts = ioread8(p + 4); |
1021 | dev_dbg(&dev->dev, | 1021 | dev_dbg(&dev->dev, |
1022 | "%d ports detected on EndRun PCI Express device\n", | 1022 | "%d ports detected on EndRun PCI Express device\n", |
1023 | number_uarts); | 1023 | number_uarts); |
1024 | } | 1024 | } |
1025 | pci_iounmap(dev, p); | 1025 | pci_iounmap(dev, p); |
1026 | return number_uarts; | 1026 | return number_uarts; |
1027 | } | 1027 | } |
1028 | 1028 | ||
1029 | /* | 1029 | /* |
1030 | * Oxford Semiconductor Inc. | 1030 | * Oxford Semiconductor Inc. |
1031 | * Check that device is part of the Tornado range of devices, then determine | 1031 | * Check that device is part of the Tornado range of devices, then determine |
1032 | * the number of ports available on the device. | 1032 | * the number of ports available on the device. |
1033 | */ | 1033 | */ |
1034 | static int pci_oxsemi_tornado_init(struct pci_dev *dev) | 1034 | static int pci_oxsemi_tornado_init(struct pci_dev *dev) |
1035 | { | 1035 | { |
1036 | u8 __iomem *p; | 1036 | u8 __iomem *p; |
1037 | unsigned long deviceID; | 1037 | unsigned long deviceID; |
1038 | unsigned int number_uarts = 0; | 1038 | unsigned int number_uarts = 0; |
1039 | 1039 | ||
1040 | /* OxSemi Tornado devices are all 0xCxxx */ | 1040 | /* OxSemi Tornado devices are all 0xCxxx */ |
1041 | if (dev->vendor == PCI_VENDOR_ID_OXSEMI && | 1041 | if (dev->vendor == PCI_VENDOR_ID_OXSEMI && |
1042 | (dev->device & 0xF000) != 0xC000) | 1042 | (dev->device & 0xF000) != 0xC000) |
1043 | return 0; | 1043 | return 0; |
1044 | 1044 | ||
1045 | p = pci_iomap(dev, 0, 5); | 1045 | p = pci_iomap(dev, 0, 5); |
1046 | if (p == NULL) | 1046 | if (p == NULL) |
1047 | return -ENOMEM; | 1047 | return -ENOMEM; |
1048 | 1048 | ||
1049 | deviceID = ioread32(p); | 1049 | deviceID = ioread32(p); |
1050 | /* Tornado device */ | 1050 | /* Tornado device */ |
1051 | if (deviceID == 0x07000200) { | 1051 | if (deviceID == 0x07000200) { |
1052 | number_uarts = ioread8(p + 4); | 1052 | number_uarts = ioread8(p + 4); |
1053 | dev_dbg(&dev->dev, | 1053 | dev_dbg(&dev->dev, |
1054 | "%d ports detected on Oxford PCI Express device\n", | 1054 | "%d ports detected on Oxford PCI Express device\n", |
1055 | number_uarts); | 1055 | number_uarts); |
1056 | } | 1056 | } |
1057 | pci_iounmap(dev, p); | 1057 | pci_iounmap(dev, p); |
1058 | return number_uarts; | 1058 | return number_uarts; |
1059 | } | 1059 | } |
1060 | 1060 | ||
1061 | static int pci_asix_setup(struct serial_private *priv, | 1061 | static int pci_asix_setup(struct serial_private *priv, |
1062 | const struct pciserial_board *board, | 1062 | const struct pciserial_board *board, |
1063 | struct uart_8250_port *port, int idx) | 1063 | struct uart_8250_port *port, int idx) |
1064 | { | 1064 | { |
1065 | port->bugs |= UART_BUG_PARITY; | 1065 | port->bugs |= UART_BUG_PARITY; |
1066 | return pci_default_setup(priv, board, port, idx); | 1066 | return pci_default_setup(priv, board, port, idx); |
1067 | } | 1067 | } |
1068 | 1068 | ||
1069 | /* Quatech devices have their own extra interface features */ | 1069 | /* Quatech devices have their own extra interface features */ |
1070 | 1070 | ||
1071 | struct quatech_feature { | 1071 | struct quatech_feature { |
1072 | u16 devid; | 1072 | u16 devid; |
1073 | bool amcc; | 1073 | bool amcc; |
1074 | }; | 1074 | }; |
1075 | 1075 | ||
1076 | #define QPCR_TEST_FOR1 0x3F | 1076 | #define QPCR_TEST_FOR1 0x3F |
1077 | #define QPCR_TEST_GET1 0x00 | 1077 | #define QPCR_TEST_GET1 0x00 |
1078 | #define QPCR_TEST_FOR2 0x40 | 1078 | #define QPCR_TEST_FOR2 0x40 |
1079 | #define QPCR_TEST_GET2 0x40 | 1079 | #define QPCR_TEST_GET2 0x40 |
1080 | #define QPCR_TEST_FOR3 0x80 | 1080 | #define QPCR_TEST_FOR3 0x80 |
1081 | #define QPCR_TEST_GET3 0x40 | 1081 | #define QPCR_TEST_GET3 0x40 |
1082 | #define QPCR_TEST_FOR4 0xC0 | 1082 | #define QPCR_TEST_FOR4 0xC0 |
1083 | #define QPCR_TEST_GET4 0x80 | 1083 | #define QPCR_TEST_GET4 0x80 |
1084 | 1084 | ||
1085 | #define QOPR_CLOCK_X1 0x0000 | 1085 | #define QOPR_CLOCK_X1 0x0000 |
1086 | #define QOPR_CLOCK_X2 0x0001 | 1086 | #define QOPR_CLOCK_X2 0x0001 |
1087 | #define QOPR_CLOCK_X4 0x0002 | 1087 | #define QOPR_CLOCK_X4 0x0002 |
1088 | #define QOPR_CLOCK_X8 0x0003 | 1088 | #define QOPR_CLOCK_X8 0x0003 |
1089 | #define QOPR_CLOCK_RATE_MASK 0x0003 | 1089 | #define QOPR_CLOCK_RATE_MASK 0x0003 |
1090 | 1090 | ||
1091 | 1091 | ||
1092 | static struct quatech_feature quatech_cards[] = { | 1092 | static struct quatech_feature quatech_cards[] = { |
1093 | { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, | 1093 | { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, |
1094 | { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, | 1094 | { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, |
1095 | { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, | 1095 | { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, |
1096 | { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, | 1096 | { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, |
1097 | { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, | 1097 | { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, |
1098 | { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, | 1098 | { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, |
1099 | { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, | 1099 | { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, |
1100 | { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, | 1100 | { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, |
1101 | { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, | 1101 | { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, |
1102 | { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, | 1102 | { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, |
1103 | { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, | 1103 | { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, |
1104 | { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, | 1104 | { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, |
1105 | { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, | 1105 | { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, |
1106 | { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, | 1106 | { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, |
1107 | { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, | 1107 | { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, |
1108 | { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, | 1108 | { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, |
1109 | { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, | 1109 | { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, |
1110 | { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, | 1110 | { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, |
1111 | { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, | 1111 | { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, |
1112 | { 0, } | 1112 | { 0, } |
1113 | }; | 1113 | }; |
1114 | 1114 | ||
1115 | static int pci_quatech_amcc(u16 devid) | 1115 | static int pci_quatech_amcc(u16 devid) |
1116 | { | 1116 | { |
1117 | struct quatech_feature *qf = &quatech_cards[0]; | 1117 | struct quatech_feature *qf = &quatech_cards[0]; |
1118 | while (qf->devid) { | 1118 | while (qf->devid) { |
1119 | if (qf->devid == devid) | 1119 | if (qf->devid == devid) |
1120 | return qf->amcc; | 1120 | return qf->amcc; |
1121 | qf++; | 1121 | qf++; |
1122 | } | 1122 | } |
1123 | pr_err("quatech: unknown port type '0x%04X'.\n", devid); | 1123 | pr_err("quatech: unknown port type '0x%04X'.\n", devid); |
1124 | return 0; | 1124 | return 0; |
1125 | }; | 1125 | }; |
1126 | 1126 | ||
1127 | static int pci_quatech_rqopr(struct uart_8250_port *port) | 1127 | static int pci_quatech_rqopr(struct uart_8250_port *port) |
1128 | { | 1128 | { |
1129 | unsigned long base = port->port.iobase; | 1129 | unsigned long base = port->port.iobase; |
1130 | u8 LCR, val; | 1130 | u8 LCR, val; |
1131 | 1131 | ||
1132 | LCR = inb(base + UART_LCR); | 1132 | LCR = inb(base + UART_LCR); |
1133 | outb(0xBF, base + UART_LCR); | 1133 | outb(0xBF, base + UART_LCR); |
1134 | val = inb(base + UART_SCR); | 1134 | val = inb(base + UART_SCR); |
1135 | outb(LCR, base + UART_LCR); | 1135 | outb(LCR, base + UART_LCR); |
1136 | return val; | 1136 | return val; |
1137 | } | 1137 | } |
1138 | 1138 | ||
1139 | static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) | 1139 | static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) |
1140 | { | 1140 | { |
1141 | unsigned long base = port->port.iobase; | 1141 | unsigned long base = port->port.iobase; |
1142 | u8 LCR, val; | 1142 | u8 LCR, val; |
1143 | 1143 | ||
1144 | LCR = inb(base + UART_LCR); | 1144 | LCR = inb(base + UART_LCR); |
1145 | outb(0xBF, base + UART_LCR); | 1145 | outb(0xBF, base + UART_LCR); |
1146 | val = inb(base + UART_SCR); | 1146 | val = inb(base + UART_SCR); |
1147 | outb(qopr, base + UART_SCR); | 1147 | outb(qopr, base + UART_SCR); |
1148 | outb(LCR, base + UART_LCR); | 1148 | outb(LCR, base + UART_LCR); |
1149 | } | 1149 | } |
1150 | 1150 | ||
1151 | static int pci_quatech_rqmcr(struct uart_8250_port *port) | 1151 | static int pci_quatech_rqmcr(struct uart_8250_port *port) |
1152 | { | 1152 | { |
1153 | unsigned long base = port->port.iobase; | 1153 | unsigned long base = port->port.iobase; |
1154 | u8 LCR, val, qmcr; | 1154 | u8 LCR, val, qmcr; |
1155 | 1155 | ||
1156 | LCR = inb(base + UART_LCR); | 1156 | LCR = inb(base + UART_LCR); |
1157 | outb(0xBF, base + UART_LCR); | 1157 | outb(0xBF, base + UART_LCR); |
1158 | val = inb(base + UART_SCR); | 1158 | val = inb(base + UART_SCR); |
1159 | outb(val | 0x10, base + UART_SCR); | 1159 | outb(val | 0x10, base + UART_SCR); |
1160 | qmcr = inb(base + UART_MCR); | 1160 | qmcr = inb(base + UART_MCR); |
1161 | outb(val, base + UART_SCR); | 1161 | outb(val, base + UART_SCR); |
1162 | outb(LCR, base + UART_LCR); | 1162 | outb(LCR, base + UART_LCR); |
1163 | 1163 | ||
1164 | return qmcr; | 1164 | return qmcr; |
1165 | } | 1165 | } |
1166 | 1166 | ||
1167 | static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) | 1167 | static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) |
1168 | { | 1168 | { |
1169 | unsigned long base = port->port.iobase; | 1169 | unsigned long base = port->port.iobase; |
1170 | u8 LCR, val; | 1170 | u8 LCR, val; |
1171 | 1171 | ||
1172 | LCR = inb(base + UART_LCR); | 1172 | LCR = inb(base + UART_LCR); |
1173 | outb(0xBF, base + UART_LCR); | 1173 | outb(0xBF, base + UART_LCR); |
1174 | val = inb(base + UART_SCR); | 1174 | val = inb(base + UART_SCR); |
1175 | outb(val | 0x10, base + UART_SCR); | 1175 | outb(val | 0x10, base + UART_SCR); |
1176 | outb(qmcr, base + UART_MCR); | 1176 | outb(qmcr, base + UART_MCR); |
1177 | outb(val, base + UART_SCR); | 1177 | outb(val, base + UART_SCR); |
1178 | outb(LCR, base + UART_LCR); | 1178 | outb(LCR, base + UART_LCR); |
1179 | } | 1179 | } |
1180 | 1180 | ||
1181 | static int pci_quatech_has_qmcr(struct uart_8250_port *port) | 1181 | static int pci_quatech_has_qmcr(struct uart_8250_port *port) |
1182 | { | 1182 | { |
1183 | unsigned long base = port->port.iobase; | 1183 | unsigned long base = port->port.iobase; |
1184 | u8 LCR, val; | 1184 | u8 LCR, val; |
1185 | 1185 | ||
1186 | LCR = inb(base + UART_LCR); | 1186 | LCR = inb(base + UART_LCR); |
1187 | outb(0xBF, base + UART_LCR); | 1187 | outb(0xBF, base + UART_LCR); |
1188 | val = inb(base + UART_SCR); | 1188 | val = inb(base + UART_SCR); |
1189 | if (val & 0x20) { | 1189 | if (val & 0x20) { |
1190 | outb(0x80, UART_LCR); | 1190 | outb(0x80, UART_LCR); |
1191 | if (!(inb(UART_SCR) & 0x20)) { | 1191 | if (!(inb(UART_SCR) & 0x20)) { |
1192 | outb(LCR, base + UART_LCR); | 1192 | outb(LCR, base + UART_LCR); |
1193 | return 1; | 1193 | return 1; |
1194 | } | 1194 | } |
1195 | } | 1195 | } |
1196 | return 0; | 1196 | return 0; |
1197 | } | 1197 | } |
1198 | 1198 | ||
1199 | static int pci_quatech_test(struct uart_8250_port *port) | 1199 | static int pci_quatech_test(struct uart_8250_port *port) |
1200 | { | 1200 | { |
1201 | u8 reg; | 1201 | u8 reg; |
1202 | u8 qopr = pci_quatech_rqopr(port); | 1202 | u8 qopr = pci_quatech_rqopr(port); |
1203 | pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); | 1203 | pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); |
1204 | reg = pci_quatech_rqopr(port) & 0xC0; | 1204 | reg = pci_quatech_rqopr(port) & 0xC0; |
1205 | if (reg != QPCR_TEST_GET1) | 1205 | if (reg != QPCR_TEST_GET1) |
1206 | return -EINVAL; | 1206 | return -EINVAL; |
1207 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); | 1207 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); |
1208 | reg = pci_quatech_rqopr(port) & 0xC0; | 1208 | reg = pci_quatech_rqopr(port) & 0xC0; |
1209 | if (reg != QPCR_TEST_GET2) | 1209 | if (reg != QPCR_TEST_GET2) |
1210 | return -EINVAL; | 1210 | return -EINVAL; |
1211 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); | 1211 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); |
1212 | reg = pci_quatech_rqopr(port) & 0xC0; | 1212 | reg = pci_quatech_rqopr(port) & 0xC0; |
1213 | if (reg != QPCR_TEST_GET3) | 1213 | if (reg != QPCR_TEST_GET3) |
1214 | return -EINVAL; | 1214 | return -EINVAL; |
1215 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); | 1215 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); |
1216 | reg = pci_quatech_rqopr(port) & 0xC0; | 1216 | reg = pci_quatech_rqopr(port) & 0xC0; |
1217 | if (reg != QPCR_TEST_GET4) | 1217 | if (reg != QPCR_TEST_GET4) |
1218 | return -EINVAL; | 1218 | return -EINVAL; |
1219 | 1219 | ||
1220 | pci_quatech_wqopr(port, qopr); | 1220 | pci_quatech_wqopr(port, qopr); |
1221 | return 0; | 1221 | return 0; |
1222 | } | 1222 | } |
1223 | 1223 | ||
1224 | static int pci_quatech_clock(struct uart_8250_port *port) | 1224 | static int pci_quatech_clock(struct uart_8250_port *port) |
1225 | { | 1225 | { |
1226 | u8 qopr, reg, set; | 1226 | u8 qopr, reg, set; |
1227 | unsigned long clock; | 1227 | unsigned long clock; |
1228 | 1228 | ||
1229 | if (pci_quatech_test(port) < 0) | 1229 | if (pci_quatech_test(port) < 0) |
1230 | return 1843200; | 1230 | return 1843200; |
1231 | 1231 | ||
1232 | qopr = pci_quatech_rqopr(port); | 1232 | qopr = pci_quatech_rqopr(port); |
1233 | 1233 | ||
1234 | pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); | 1234 | pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); |
1235 | reg = pci_quatech_rqopr(port); | 1235 | reg = pci_quatech_rqopr(port); |
1236 | if (reg & QOPR_CLOCK_X8) { | 1236 | if (reg & QOPR_CLOCK_X8) { |
1237 | clock = 1843200; | 1237 | clock = 1843200; |
1238 | goto out; | 1238 | goto out; |
1239 | } | 1239 | } |
1240 | pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); | 1240 | pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); |
1241 | reg = pci_quatech_rqopr(port); | 1241 | reg = pci_quatech_rqopr(port); |
1242 | if (!(reg & QOPR_CLOCK_X8)) { | 1242 | if (!(reg & QOPR_CLOCK_X8)) { |
1243 | clock = 1843200; | 1243 | clock = 1843200; |
1244 | goto out; | 1244 | goto out; |
1245 | } | 1245 | } |
1246 | reg &= QOPR_CLOCK_X8; | 1246 | reg &= QOPR_CLOCK_X8; |
1247 | if (reg == QOPR_CLOCK_X2) { | 1247 | if (reg == QOPR_CLOCK_X2) { |
1248 | clock = 3685400; | 1248 | clock = 3685400; |
1249 | set = QOPR_CLOCK_X2; | 1249 | set = QOPR_CLOCK_X2; |
1250 | } else if (reg == QOPR_CLOCK_X4) { | 1250 | } else if (reg == QOPR_CLOCK_X4) { |
1251 | clock = 7372800; | 1251 | clock = 7372800; |
1252 | set = QOPR_CLOCK_X4; | 1252 | set = QOPR_CLOCK_X4; |
1253 | } else if (reg == QOPR_CLOCK_X8) { | 1253 | } else if (reg == QOPR_CLOCK_X8) { |
1254 | clock = 14745600; | 1254 | clock = 14745600; |
1255 | set = QOPR_CLOCK_X8; | 1255 | set = QOPR_CLOCK_X8; |
1256 | } else { | 1256 | } else { |
1257 | clock = 1843200; | 1257 | clock = 1843200; |
1258 | set = QOPR_CLOCK_X1; | 1258 | set = QOPR_CLOCK_X1; |
1259 | } | 1259 | } |
1260 | qopr &= ~QOPR_CLOCK_RATE_MASK; | 1260 | qopr &= ~QOPR_CLOCK_RATE_MASK; |
1261 | qopr |= set; | 1261 | qopr |= set; |
1262 | 1262 | ||
1263 | out: | 1263 | out: |
1264 | pci_quatech_wqopr(port, qopr); | 1264 | pci_quatech_wqopr(port, qopr); |
1265 | return clock; | 1265 | return clock; |
1266 | } | 1266 | } |
1267 | 1267 | ||
1268 | static int pci_quatech_rs422(struct uart_8250_port *port) | 1268 | static int pci_quatech_rs422(struct uart_8250_port *port) |
1269 | { | 1269 | { |
1270 | u8 qmcr; | 1270 | u8 qmcr; |
1271 | int rs422 = 0; | 1271 | int rs422 = 0; |
1272 | 1272 | ||
1273 | if (!pci_quatech_has_qmcr(port)) | 1273 | if (!pci_quatech_has_qmcr(port)) |
1274 | return 0; | 1274 | return 0; |
1275 | qmcr = pci_quatech_rqmcr(port); | 1275 | qmcr = pci_quatech_rqmcr(port); |
1276 | pci_quatech_wqmcr(port, 0xFF); | 1276 | pci_quatech_wqmcr(port, 0xFF); |
1277 | if (pci_quatech_rqmcr(port)) | 1277 | if (pci_quatech_rqmcr(port)) |
1278 | rs422 = 1; | 1278 | rs422 = 1; |
1279 | pci_quatech_wqmcr(port, qmcr); | 1279 | pci_quatech_wqmcr(port, qmcr); |
1280 | return rs422; | 1280 | return rs422; |
1281 | } | 1281 | } |
1282 | 1282 | ||
1283 | static int pci_quatech_init(struct pci_dev *dev) | 1283 | static int pci_quatech_init(struct pci_dev *dev) |
1284 | { | 1284 | { |
1285 | if (pci_quatech_amcc(dev->device)) { | 1285 | if (pci_quatech_amcc(dev->device)) { |
1286 | unsigned long base = pci_resource_start(dev, 0); | 1286 | unsigned long base = pci_resource_start(dev, 0); |
1287 | if (base) { | 1287 | if (base) { |
1288 | u32 tmp; | 1288 | u32 tmp; |
1289 | outl(inl(base + 0x38) | 0x00002000, base + 0x38); | 1289 | outl(inl(base + 0x38) | 0x00002000, base + 0x38); |
1290 | tmp = inl(base + 0x3c); | 1290 | tmp = inl(base + 0x3c); |
1291 | outl(tmp | 0x01000000, base + 0x3c); | 1291 | outl(tmp | 0x01000000, base + 0x3c); |
1292 | outl(tmp &= ~0x01000000, base + 0x3c); | 1292 | outl(tmp &= ~0x01000000, base + 0x3c); |
1293 | } | 1293 | } |
1294 | } | 1294 | } |
1295 | return 0; | 1295 | return 0; |
1296 | } | 1296 | } |
1297 | 1297 | ||
1298 | static int pci_quatech_setup(struct serial_private *priv, | 1298 | static int pci_quatech_setup(struct serial_private *priv, |
1299 | const struct pciserial_board *board, | 1299 | const struct pciserial_board *board, |
1300 | struct uart_8250_port *port, int idx) | 1300 | struct uart_8250_port *port, int idx) |
1301 | { | 1301 | { |
1302 | /* Needed by pci_quatech calls below */ | 1302 | /* Needed by pci_quatech calls below */ |
1303 | port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); | 1303 | port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); |
1304 | /* Set up the clocking */ | 1304 | /* Set up the clocking */ |
1305 | port->port.uartclk = pci_quatech_clock(port); | 1305 | port->port.uartclk = pci_quatech_clock(port); |
1306 | /* For now just warn about RS422 */ | 1306 | /* For now just warn about RS422 */ |
1307 | if (pci_quatech_rs422(port)) | 1307 | if (pci_quatech_rs422(port)) |
1308 | pr_warn("quatech: software control of RS422 features not currently supported.\n"); | 1308 | pr_warn("quatech: software control of RS422 features not currently supported.\n"); |
1309 | return pci_default_setup(priv, board, port, idx); | 1309 | return pci_default_setup(priv, board, port, idx); |
1310 | } | 1310 | } |
1311 | 1311 | ||
1312 | static void pci_quatech_exit(struct pci_dev *dev) | 1312 | static void pci_quatech_exit(struct pci_dev *dev) |
1313 | { | 1313 | { |
1314 | } | 1314 | } |
1315 | 1315 | ||
1316 | static int pci_default_setup(struct serial_private *priv, | 1316 | static int pci_default_setup(struct serial_private *priv, |
1317 | const struct pciserial_board *board, | 1317 | const struct pciserial_board *board, |
1318 | struct uart_8250_port *port, int idx) | 1318 | struct uart_8250_port *port, int idx) |
1319 | { | 1319 | { |
1320 | unsigned int bar, offset = board->first_offset, maxnr; | 1320 | unsigned int bar, offset = board->first_offset, maxnr; |
1321 | 1321 | ||
1322 | bar = FL_GET_BASE(board->flags); | 1322 | bar = FL_GET_BASE(board->flags); |
1323 | if (board->flags & FL_BASE_BARS) | 1323 | if (board->flags & FL_BASE_BARS) |
1324 | bar += idx; | 1324 | bar += idx; |
1325 | else | 1325 | else |
1326 | offset += idx * board->uart_offset; | 1326 | offset += idx * board->uart_offset; |
1327 | 1327 | ||
1328 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> | 1328 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> |
1329 | (board->reg_shift + 3); | 1329 | (board->reg_shift + 3); |
1330 | 1330 | ||
1331 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | 1331 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) |
1332 | return 1; | 1332 | return 1; |
1333 | 1333 | ||
1334 | return setup_port(priv, port, bar, offset, board->reg_shift); | 1334 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1335 | } | 1335 | } |
1336 | 1336 | ||
1337 | static int pci_pericom_setup(struct serial_private *priv, | 1337 | static int pci_pericom_setup(struct serial_private *priv, |
1338 | const struct pciserial_board *board, | 1338 | const struct pciserial_board *board, |
1339 | struct uart_8250_port *port, int idx) | 1339 | struct uart_8250_port *port, int idx) |
1340 | { | 1340 | { |
1341 | unsigned int bar, offset = board->first_offset, maxnr; | 1341 | unsigned int bar, offset = board->first_offset, maxnr; |
1342 | 1342 | ||
1343 | bar = FL_GET_BASE(board->flags); | 1343 | bar = FL_GET_BASE(board->flags); |
1344 | if (board->flags & FL_BASE_BARS) | 1344 | if (board->flags & FL_BASE_BARS) |
1345 | bar += idx; | 1345 | bar += idx; |
1346 | else | 1346 | else |
1347 | offset += idx * board->uart_offset; | 1347 | offset += idx * board->uart_offset; |
1348 | 1348 | ||
1349 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> | 1349 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> |
1350 | (board->reg_shift + 3); | 1350 | (board->reg_shift + 3); |
1351 | 1351 | ||
1352 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | 1352 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) |
1353 | return 1; | 1353 | return 1; |
1354 | 1354 | ||
1355 | port->port.uartclk = 14745600; | 1355 | port->port.uartclk = 14745600; |
1356 | 1356 | ||
1357 | return setup_port(priv, port, bar, offset, board->reg_shift); | 1357 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1358 | } | 1358 | } |
1359 | 1359 | ||
1360 | static int | 1360 | static int |
1361 | ce4100_serial_setup(struct serial_private *priv, | 1361 | ce4100_serial_setup(struct serial_private *priv, |
1362 | const struct pciserial_board *board, | 1362 | const struct pciserial_board *board, |
1363 | struct uart_8250_port *port, int idx) | 1363 | struct uart_8250_port *port, int idx) |
1364 | { | 1364 | { |
1365 | int ret; | 1365 | int ret; |
1366 | 1366 | ||
1367 | ret = setup_port(priv, port, idx, 0, board->reg_shift); | 1367 | ret = setup_port(priv, port, idx, 0, board->reg_shift); |
1368 | port->port.iotype = UPIO_MEM32; | 1368 | port->port.iotype = UPIO_MEM32; |
1369 | port->port.type = PORT_XSCALE; | 1369 | port->port.type = PORT_XSCALE; |
1370 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); | 1370 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); |
1371 | port->port.regshift = 2; | 1371 | port->port.regshift = 2; |
1372 | 1372 | ||
1373 | return ret; | 1373 | return ret; |
1374 | } | 1374 | } |
1375 | 1375 | ||
1376 | #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a | 1376 | #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a |
1377 | #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c | 1377 | #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c |
1378 | 1378 | ||
1379 | #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a | 1379 | #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a |
1380 | #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c | 1380 | #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c |
1381 | 1381 | ||
1382 | #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3 | 1382 | #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3 |
1383 | #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4 | 1383 | #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4 |
1384 | 1384 | ||
1385 | #define BYT_PRV_CLK 0x800 | 1385 | #define BYT_PRV_CLK 0x800 |
1386 | #define BYT_PRV_CLK_EN (1 << 0) | 1386 | #define BYT_PRV_CLK_EN (1 << 0) |
1387 | #define BYT_PRV_CLK_M_VAL_SHIFT 1 | 1387 | #define BYT_PRV_CLK_M_VAL_SHIFT 1 |
1388 | #define BYT_PRV_CLK_N_VAL_SHIFT 16 | 1388 | #define BYT_PRV_CLK_N_VAL_SHIFT 16 |
1389 | #define BYT_PRV_CLK_UPDATE (1 << 31) | 1389 | #define BYT_PRV_CLK_UPDATE (1 << 31) |
1390 | 1390 | ||
1391 | #define BYT_TX_OVF_INT 0x820 | 1391 | #define BYT_TX_OVF_INT 0x820 |
1392 | #define BYT_TX_OVF_INT_MASK (1 << 1) | 1392 | #define BYT_TX_OVF_INT_MASK (1 << 1) |
1393 | 1393 | ||
1394 | static void | 1394 | static void |
1395 | byt_set_termios(struct uart_port *p, struct ktermios *termios, | 1395 | byt_set_termios(struct uart_port *p, struct ktermios *termios, |
1396 | struct ktermios *old) | 1396 | struct ktermios *old) |
1397 | { | 1397 | { |
1398 | unsigned int baud = tty_termios_baud_rate(termios); | 1398 | unsigned int baud = tty_termios_baud_rate(termios); |
1399 | unsigned long fref = 100000000, fuart = baud * 16; | 1399 | unsigned long fref = 100000000, fuart = baud * 16; |
1400 | unsigned long w = BIT(15) - 1; | 1400 | unsigned long w = BIT(15) - 1; |
1401 | unsigned long m, n; | 1401 | unsigned long m, n; |
1402 | u32 reg; | 1402 | u32 reg; |
1403 | 1403 | ||
1404 | /* Gracefully handle the B0 case: fall back to B9600 */ | ||
1405 | fuart = fuart ? fuart : 9600 * 16; | ||
1406 | |||
1404 | /* Get Fuart closer to Fref */ | 1407 | /* Get Fuart closer to Fref */ |
1405 | fuart *= rounddown_pow_of_two(fref / fuart); | 1408 | fuart *= rounddown_pow_of_two(fref / fuart); |
1406 | 1409 | ||
1407 | /* | 1410 | /* |
1408 | * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the | 1411 | * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the |
1409 | * dividers must be adjusted. | 1412 | * dividers must be adjusted. |
1410 | * | 1413 | * |
1411 | * uartclk = (m / n) * 100 MHz, where m <= n | 1414 | * uartclk = (m / n) * 100 MHz, where m <= n |
1412 | */ | 1415 | */ |
1413 | rational_best_approximation(fuart, fref, w, w, &m, &n); | 1416 | rational_best_approximation(fuart, fref, w, w, &m, &n); |
1414 | p->uartclk = fuart; | 1417 | p->uartclk = fuart; |
1415 | 1418 | ||
1416 | /* Reset the clock */ | 1419 | /* Reset the clock */ |
1417 | reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); | 1420 | reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); |
1418 | writel(reg, p->membase + BYT_PRV_CLK); | 1421 | writel(reg, p->membase + BYT_PRV_CLK); |
1419 | reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; | 1422 | reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; |
1420 | writel(reg, p->membase + BYT_PRV_CLK); | 1423 | writel(reg, p->membase + BYT_PRV_CLK); |
1421 | 1424 | ||
1422 | p->status &= ~UPSTAT_AUTOCTS; | 1425 | p->status &= ~UPSTAT_AUTOCTS; |
1423 | if (termios->c_cflag & CRTSCTS) | 1426 | if (termios->c_cflag & CRTSCTS) |
1424 | p->status |= UPSTAT_AUTOCTS; | 1427 | p->status |= UPSTAT_AUTOCTS; |
1425 | 1428 | ||
1426 | serial8250_do_set_termios(p, termios, old); | 1429 | serial8250_do_set_termios(p, termios, old); |
1427 | } | 1430 | } |
1428 | 1431 | ||
1429 | static bool byt_dma_filter(struct dma_chan *chan, void *param) | 1432 | static bool byt_dma_filter(struct dma_chan *chan, void *param) |
1430 | { | 1433 | { |
1431 | struct dw_dma_slave *dws = param; | 1434 | struct dw_dma_slave *dws = param; |
1432 | 1435 | ||
1433 | if (dws->dma_dev != chan->device->dev) | 1436 | if (dws->dma_dev != chan->device->dev) |
1434 | return false; | 1437 | return false; |
1435 | 1438 | ||
1436 | chan->private = dws; | 1439 | chan->private = dws; |
1437 | return true; | 1440 | return true; |
1438 | } | 1441 | } |
1439 | 1442 | ||
1440 | static int | 1443 | static int |
1441 | byt_serial_setup(struct serial_private *priv, | 1444 | byt_serial_setup(struct serial_private *priv, |
1442 | const struct pciserial_board *board, | 1445 | const struct pciserial_board *board, |
1443 | struct uart_8250_port *port, int idx) | 1446 | struct uart_8250_port *port, int idx) |
1444 | { | 1447 | { |
1445 | struct pci_dev *pdev = priv->dev; | 1448 | struct pci_dev *pdev = priv->dev; |
1446 | struct device *dev = port->port.dev; | 1449 | struct device *dev = port->port.dev; |
1447 | struct uart_8250_dma *dma; | 1450 | struct uart_8250_dma *dma; |
1448 | struct dw_dma_slave *tx_param, *rx_param; | 1451 | struct dw_dma_slave *tx_param, *rx_param; |
1449 | struct pci_dev *dma_dev; | 1452 | struct pci_dev *dma_dev; |
1450 | int ret; | 1453 | int ret; |
1451 | 1454 | ||
1452 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); | 1455 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); |
1453 | if (!dma) | 1456 | if (!dma) |
1454 | return -ENOMEM; | 1457 | return -ENOMEM; |
1455 | 1458 | ||
1456 | tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); | 1459 | tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); |
1457 | if (!tx_param) | 1460 | if (!tx_param) |
1458 | return -ENOMEM; | 1461 | return -ENOMEM; |
1459 | 1462 | ||
1460 | rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); | 1463 | rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); |
1461 | if (!rx_param) | 1464 | if (!rx_param) |
1462 | return -ENOMEM; | 1465 | return -ENOMEM; |
1463 | 1466 | ||
1464 | switch (pdev->device) { | 1467 | switch (pdev->device) { |
1465 | case PCI_DEVICE_ID_INTEL_BYT_UART1: | 1468 | case PCI_DEVICE_ID_INTEL_BYT_UART1: |
1466 | case PCI_DEVICE_ID_INTEL_BSW_UART1: | 1469 | case PCI_DEVICE_ID_INTEL_BSW_UART1: |
1467 | case PCI_DEVICE_ID_INTEL_BDW_UART1: | 1470 | case PCI_DEVICE_ID_INTEL_BDW_UART1: |
1468 | rx_param->src_id = 3; | 1471 | rx_param->src_id = 3; |
1469 | tx_param->dst_id = 2; | 1472 | tx_param->dst_id = 2; |
1470 | break; | 1473 | break; |
1471 | case PCI_DEVICE_ID_INTEL_BYT_UART2: | 1474 | case PCI_DEVICE_ID_INTEL_BYT_UART2: |
1472 | case PCI_DEVICE_ID_INTEL_BSW_UART2: | 1475 | case PCI_DEVICE_ID_INTEL_BSW_UART2: |
1473 | case PCI_DEVICE_ID_INTEL_BDW_UART2: | 1476 | case PCI_DEVICE_ID_INTEL_BDW_UART2: |
1474 | rx_param->src_id = 5; | 1477 | rx_param->src_id = 5; |
1475 | tx_param->dst_id = 4; | 1478 | tx_param->dst_id = 4; |
1476 | break; | 1479 | break; |
1477 | default: | 1480 | default: |
1478 | return -EINVAL; | 1481 | return -EINVAL; |
1479 | } | 1482 | } |
1480 | 1483 | ||
1481 | rx_param->src_master = 1; | 1484 | rx_param->src_master = 1; |
1482 | rx_param->dst_master = 0; | 1485 | rx_param->dst_master = 0; |
1483 | 1486 | ||
1484 | dma->rxconf.src_maxburst = 16; | 1487 | dma->rxconf.src_maxburst = 16; |
1485 | 1488 | ||
1486 | tx_param->src_master = 1; | 1489 | tx_param->src_master = 1; |
1487 | tx_param->dst_master = 0; | 1490 | tx_param->dst_master = 0; |
1488 | 1491 | ||
1489 | dma->txconf.dst_maxburst = 16; | 1492 | dma->txconf.dst_maxburst = 16; |
1490 | 1493 | ||
1491 | dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); | 1494 | dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); |
1492 | rx_param->dma_dev = &dma_dev->dev; | 1495 | rx_param->dma_dev = &dma_dev->dev; |
1493 | tx_param->dma_dev = &dma_dev->dev; | 1496 | tx_param->dma_dev = &dma_dev->dev; |
1494 | 1497 | ||
1495 | dma->fn = byt_dma_filter; | 1498 | dma->fn = byt_dma_filter; |
1496 | dma->rx_param = rx_param; | 1499 | dma->rx_param = rx_param; |
1497 | dma->tx_param = tx_param; | 1500 | dma->tx_param = tx_param; |
1498 | 1501 | ||
1499 | ret = pci_default_setup(priv, board, port, idx); | 1502 | ret = pci_default_setup(priv, board, port, idx); |
1500 | port->port.iotype = UPIO_MEM; | 1503 | port->port.iotype = UPIO_MEM; |
1501 | port->port.type = PORT_16550A; | 1504 | port->port.type = PORT_16550A; |
1502 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); | 1505 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); |
1503 | port->port.set_termios = byt_set_termios; | 1506 | port->port.set_termios = byt_set_termios; |
1504 | port->port.fifosize = 64; | 1507 | port->port.fifosize = 64; |
1505 | port->tx_loadsz = 64; | 1508 | port->tx_loadsz = 64; |
1506 | port->dma = dma; | 1509 | port->dma = dma; |
1507 | port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; | 1510 | port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; |
1508 | 1511 | ||
1509 | /* Disable Tx counter interrupts */ | 1512 | /* Disable Tx counter interrupts */ |
1510 | writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); | 1513 | writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); |
1511 | 1514 | ||
1512 | return ret; | 1515 | return ret; |
1513 | } | 1516 | } |
1514 | 1517 | ||
1515 | static int | 1518 | static int |
1516 | pci_omegapci_setup(struct serial_private *priv, | 1519 | pci_omegapci_setup(struct serial_private *priv, |
1517 | const struct pciserial_board *board, | 1520 | const struct pciserial_board *board, |
1518 | struct uart_8250_port *port, int idx) | 1521 | struct uart_8250_port *port, int idx) |
1519 | { | 1522 | { |
1520 | return setup_port(priv, port, 2, idx * 8, 0); | 1523 | return setup_port(priv, port, 2, idx * 8, 0); |
1521 | } | 1524 | } |
1522 | 1525 | ||
1523 | static int | 1526 | static int |
1524 | pci_brcm_trumanage_setup(struct serial_private *priv, | 1527 | pci_brcm_trumanage_setup(struct serial_private *priv, |
1525 | const struct pciserial_board *board, | 1528 | const struct pciserial_board *board, |
1526 | struct uart_8250_port *port, int idx) | 1529 | struct uart_8250_port *port, int idx) |
1527 | { | 1530 | { |
1528 | int ret = pci_default_setup(priv, board, port, idx); | 1531 | int ret = pci_default_setup(priv, board, port, idx); |
1529 | 1532 | ||
1530 | port->port.type = PORT_BRCM_TRUMANAGE; | 1533 | port->port.type = PORT_BRCM_TRUMANAGE; |
1531 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); | 1534 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); |
1532 | return ret; | 1535 | return ret; |
1533 | } | 1536 | } |
1534 | 1537 | ||
1535 | /* RTS will control by MCR if this bit is 0 */ | 1538 | /* RTS will control by MCR if this bit is 0 */ |
1536 | #define FINTEK_RTS_CONTROL_BY_HW BIT(4) | 1539 | #define FINTEK_RTS_CONTROL_BY_HW BIT(4) |
1537 | /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ | 1540 | /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ |
1538 | #define FINTEK_RTS_INVERT BIT(5) | 1541 | #define FINTEK_RTS_INVERT BIT(5) |
1539 | 1542 | ||
1540 | /* We should do proper H/W transceiver setting before change to RS485 mode */ | 1543 | /* We should do proper H/W transceiver setting before change to RS485 mode */ |
1541 | static int pci_fintek_rs485_config(struct uart_port *port, | 1544 | static int pci_fintek_rs485_config(struct uart_port *port, |
1542 | struct serial_rs485 *rs485) | 1545 | struct serial_rs485 *rs485) |
1543 | { | 1546 | { |
1544 | u8 setting; | 1547 | u8 setting; |
1545 | u8 *index = (u8 *) port->private_data; | 1548 | u8 *index = (u8 *) port->private_data; |
1546 | struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev, | 1549 | struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev, |
1547 | dev); | 1550 | dev); |
1548 | 1551 | ||
1549 | pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); | 1552 | pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); |
1550 | 1553 | ||
1551 | if (!rs485) | 1554 | if (!rs485) |
1552 | rs485 = &port->rs485; | 1555 | rs485 = &port->rs485; |
1553 | else if (rs485->flags & SER_RS485_ENABLED) | 1556 | else if (rs485->flags & SER_RS485_ENABLED) |
1554 | memset(rs485->padding, 0, sizeof(rs485->padding)); | 1557 | memset(rs485->padding, 0, sizeof(rs485->padding)); |
1555 | else | 1558 | else |
1556 | memset(rs485, 0, sizeof(*rs485)); | 1559 | memset(rs485, 0, sizeof(*rs485)); |
1557 | 1560 | ||
1558 | /* F81504/508/512 not support RTS delay before or after send */ | 1561 | /* F81504/508/512 not support RTS delay before or after send */ |
1559 | rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; | 1562 | rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; |
1560 | 1563 | ||
1561 | if (rs485->flags & SER_RS485_ENABLED) { | 1564 | if (rs485->flags & SER_RS485_ENABLED) { |
1562 | /* Enable RTS H/W control mode */ | 1565 | /* Enable RTS H/W control mode */ |
1563 | setting |= FINTEK_RTS_CONTROL_BY_HW; | 1566 | setting |= FINTEK_RTS_CONTROL_BY_HW; |
1564 | 1567 | ||
1565 | if (rs485->flags & SER_RS485_RTS_ON_SEND) { | 1568 | if (rs485->flags & SER_RS485_RTS_ON_SEND) { |
1566 | /* RTS driving high on TX */ | 1569 | /* RTS driving high on TX */ |
1567 | setting &= ~FINTEK_RTS_INVERT; | 1570 | setting &= ~FINTEK_RTS_INVERT; |
1568 | } else { | 1571 | } else { |
1569 | /* RTS driving low on TX */ | 1572 | /* RTS driving low on TX */ |
1570 | setting |= FINTEK_RTS_INVERT; | 1573 | setting |= FINTEK_RTS_INVERT; |
1571 | } | 1574 | } |
1572 | 1575 | ||
1573 | rs485->delay_rts_after_send = 0; | 1576 | rs485->delay_rts_after_send = 0; |
1574 | rs485->delay_rts_before_send = 0; | 1577 | rs485->delay_rts_before_send = 0; |
1575 | } else { | 1578 | } else { |
1576 | /* Disable RTS H/W control mode */ | 1579 | /* Disable RTS H/W control mode */ |
1577 | setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); | 1580 | setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); |
1578 | } | 1581 | } |
1579 | 1582 | ||
1580 | pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); | 1583 | pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); |
1581 | 1584 | ||
1582 | if (rs485 != &port->rs485) | 1585 | if (rs485 != &port->rs485) |
1583 | port->rs485 = *rs485; | 1586 | port->rs485 = *rs485; |
1584 | 1587 | ||
1585 | return 0; | 1588 | return 0; |
1586 | } | 1589 | } |
1587 | 1590 | ||
1588 | static int pci_fintek_setup(struct serial_private *priv, | 1591 | static int pci_fintek_setup(struct serial_private *priv, |
1589 | const struct pciserial_board *board, | 1592 | const struct pciserial_board *board, |
1590 | struct uart_8250_port *port, int idx) | 1593 | struct uart_8250_port *port, int idx) |
1591 | { | 1594 | { |
1592 | struct pci_dev *pdev = priv->dev; | 1595 | struct pci_dev *pdev = priv->dev; |
1593 | u8 *data; | 1596 | u8 *data; |
1594 | u8 config_base; | 1597 | u8 config_base; |
1595 | u16 iobase; | 1598 | u16 iobase; |
1596 | 1599 | ||
1597 | config_base = 0x40 + 0x08 * idx; | 1600 | config_base = 0x40 + 0x08 * idx; |
1598 | 1601 | ||
1599 | /* Get the io address from configuration space */ | 1602 | /* Get the io address from configuration space */ |
1600 | pci_read_config_word(pdev, config_base + 4, &iobase); | 1603 | pci_read_config_word(pdev, config_base + 4, &iobase); |
1601 | 1604 | ||
1602 | dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); | 1605 | dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); |
1603 | 1606 | ||
1604 | port->port.iotype = UPIO_PORT; | 1607 | port->port.iotype = UPIO_PORT; |
1605 | port->port.iobase = iobase; | 1608 | port->port.iobase = iobase; |
1606 | port->port.rs485_config = pci_fintek_rs485_config; | 1609 | port->port.rs485_config = pci_fintek_rs485_config; |
1607 | 1610 | ||
1608 | data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); | 1611 | data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); |
1609 | if (!data) | 1612 | if (!data) |
1610 | return -ENOMEM; | 1613 | return -ENOMEM; |
1611 | 1614 | ||
1612 | /* preserve index in PCI configuration space */ | 1615 | /* preserve index in PCI configuration space */ |
1613 | *data = idx; | 1616 | *data = idx; |
1614 | port->port.private_data = data; | 1617 | port->port.private_data = data; |
1615 | 1618 | ||
1616 | return 0; | 1619 | return 0; |
1617 | } | 1620 | } |
1618 | 1621 | ||
1619 | static int pci_fintek_init(struct pci_dev *dev) | 1622 | static int pci_fintek_init(struct pci_dev *dev) |
1620 | { | 1623 | { |
1621 | unsigned long iobase; | 1624 | unsigned long iobase; |
1622 | u32 max_port, i; | 1625 | u32 max_port, i; |
1623 | u32 bar_data[3]; | 1626 | u32 bar_data[3]; |
1624 | u8 config_base; | 1627 | u8 config_base; |
1625 | struct serial_private *priv = pci_get_drvdata(dev); | 1628 | struct serial_private *priv = pci_get_drvdata(dev); |
1626 | struct uart_8250_port *port; | 1629 | struct uart_8250_port *port; |
1627 | 1630 | ||
1628 | switch (dev->device) { | 1631 | switch (dev->device) { |
1629 | case 0x1104: /* 4 ports */ | 1632 | case 0x1104: /* 4 ports */ |
1630 | case 0x1108: /* 8 ports */ | 1633 | case 0x1108: /* 8 ports */ |
1631 | max_port = dev->device & 0xff; | 1634 | max_port = dev->device & 0xff; |
1632 | break; | 1635 | break; |
1633 | case 0x1112: /* 12 ports */ | 1636 | case 0x1112: /* 12 ports */ |
1634 | max_port = 12; | 1637 | max_port = 12; |
1635 | break; | 1638 | break; |
1636 | default: | 1639 | default: |
1637 | return -EINVAL; | 1640 | return -EINVAL; |
1638 | } | 1641 | } |
1639 | 1642 | ||
1640 | /* Get the io address dispatch from the BIOS */ | 1643 | /* Get the io address dispatch from the BIOS */ |
1641 | pci_read_config_dword(dev, 0x24, &bar_data[0]); | 1644 | pci_read_config_dword(dev, 0x24, &bar_data[0]); |
1642 | pci_read_config_dword(dev, 0x20, &bar_data[1]); | 1645 | pci_read_config_dword(dev, 0x20, &bar_data[1]); |
1643 | pci_read_config_dword(dev, 0x1c, &bar_data[2]); | 1646 | pci_read_config_dword(dev, 0x1c, &bar_data[2]); |
1644 | 1647 | ||
1645 | for (i = 0; i < max_port; ++i) { | 1648 | for (i = 0; i < max_port; ++i) { |
1646 | /* UART0 configuration offset start from 0x40 */ | 1649 | /* UART0 configuration offset start from 0x40 */ |
1647 | config_base = 0x40 + 0x08 * i; | 1650 | config_base = 0x40 + 0x08 * i; |
1648 | 1651 | ||
1649 | /* Calculate Real IO Port */ | 1652 | /* Calculate Real IO Port */ |
1650 | iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; | 1653 | iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; |
1651 | 1654 | ||
1652 | /* Enable UART I/O port */ | 1655 | /* Enable UART I/O port */ |
1653 | pci_write_config_byte(dev, config_base + 0x00, 0x01); | 1656 | pci_write_config_byte(dev, config_base + 0x00, 0x01); |
1654 | 1657 | ||
1655 | /* Select 128-byte FIFO and 8x FIFO threshold */ | 1658 | /* Select 128-byte FIFO and 8x FIFO threshold */ |
1656 | pci_write_config_byte(dev, config_base + 0x01, 0x33); | 1659 | pci_write_config_byte(dev, config_base + 0x01, 0x33); |
1657 | 1660 | ||
1658 | /* LSB UART */ | 1661 | /* LSB UART */ |
1659 | pci_write_config_byte(dev, config_base + 0x04, | 1662 | pci_write_config_byte(dev, config_base + 0x04, |
1660 | (u8)(iobase & 0xff)); | 1663 | (u8)(iobase & 0xff)); |
1661 | 1664 | ||
1662 | /* MSB UART */ | 1665 | /* MSB UART */ |
1663 | pci_write_config_byte(dev, config_base + 0x05, | 1666 | pci_write_config_byte(dev, config_base + 0x05, |
1664 | (u8)((iobase & 0xff00) >> 8)); | 1667 | (u8)((iobase & 0xff00) >> 8)); |
1665 | 1668 | ||
1666 | pci_write_config_byte(dev, config_base + 0x06, dev->irq); | 1669 | pci_write_config_byte(dev, config_base + 0x06, dev->irq); |
1667 | 1670 | ||
1668 | if (priv) { | 1671 | if (priv) { |
1669 | /* re-apply RS232/485 mode when | 1672 | /* re-apply RS232/485 mode when |
1670 | * pciserial_resume_ports() | 1673 | * pciserial_resume_ports() |
1671 | */ | 1674 | */ |
1672 | port = serial8250_get_port(priv->line[i]); | 1675 | port = serial8250_get_port(priv->line[i]); |
1673 | pci_fintek_rs485_config(&port->port, NULL); | 1676 | pci_fintek_rs485_config(&port->port, NULL); |
1674 | } else { | 1677 | } else { |
1675 | /* First init without port data | 1678 | /* First init without port data |
1676 | * force init to RS232 Mode | 1679 | * force init to RS232 Mode |
1677 | */ | 1680 | */ |
1678 | pci_write_config_byte(dev, config_base + 0x07, 0x01); | 1681 | pci_write_config_byte(dev, config_base + 0x07, 0x01); |
1679 | } | 1682 | } |
1680 | } | 1683 | } |
1681 | 1684 | ||
1682 | return max_port; | 1685 | return max_port; |
1683 | } | 1686 | } |
1684 | 1687 | ||
1685 | static int skip_tx_en_setup(struct serial_private *priv, | 1688 | static int skip_tx_en_setup(struct serial_private *priv, |
1686 | const struct pciserial_board *board, | 1689 | const struct pciserial_board *board, |
1687 | struct uart_8250_port *port, int idx) | 1690 | struct uart_8250_port *port, int idx) |
1688 | { | 1691 | { |
1689 | port->port.flags |= UPF_NO_TXEN_TEST; | 1692 | port->port.flags |= UPF_NO_TXEN_TEST; |
1690 | dev_dbg(&priv->dev->dev, | 1693 | dev_dbg(&priv->dev->dev, |
1691 | "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", | 1694 | "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", |
1692 | priv->dev->vendor, priv->dev->device, | 1695 | priv->dev->vendor, priv->dev->device, |
1693 | priv->dev->subsystem_vendor, priv->dev->subsystem_device); | 1696 | priv->dev->subsystem_vendor, priv->dev->subsystem_device); |
1694 | 1697 | ||
1695 | return pci_default_setup(priv, board, port, idx); | 1698 | return pci_default_setup(priv, board, port, idx); |
1696 | } | 1699 | } |
1697 | 1700 | ||
1698 | static void kt_handle_break(struct uart_port *p) | 1701 | static void kt_handle_break(struct uart_port *p) |
1699 | { | 1702 | { |
1700 | struct uart_8250_port *up = up_to_u8250p(p); | 1703 | struct uart_8250_port *up = up_to_u8250p(p); |
1701 | /* | 1704 | /* |
1702 | * On receipt of a BI, serial device in Intel ME (Intel | 1705 | * On receipt of a BI, serial device in Intel ME (Intel |
1703 | * management engine) needs to have its fifos cleared for sane | 1706 | * management engine) needs to have its fifos cleared for sane |
1704 | * SOL (Serial Over Lan) output. | 1707 | * SOL (Serial Over Lan) output. |
1705 | */ | 1708 | */ |
1706 | serial8250_clear_and_reinit_fifos(up); | 1709 | serial8250_clear_and_reinit_fifos(up); |
1707 | } | 1710 | } |
1708 | 1711 | ||
1709 | static unsigned int kt_serial_in(struct uart_port *p, int offset) | 1712 | static unsigned int kt_serial_in(struct uart_port *p, int offset) |
1710 | { | 1713 | { |
1711 | struct uart_8250_port *up = up_to_u8250p(p); | 1714 | struct uart_8250_port *up = up_to_u8250p(p); |
1712 | unsigned int val; | 1715 | unsigned int val; |
1713 | 1716 | ||
1714 | /* | 1717 | /* |
1715 | * When the Intel ME (management engine) gets reset its serial | 1718 | * When the Intel ME (management engine) gets reset its serial |
1716 | * port registers could return 0 momentarily. Functions like | 1719 | * port registers could return 0 momentarily. Functions like |
1717 | * serial8250_console_write, read and save the IER, perform | 1720 | * serial8250_console_write, read and save the IER, perform |
1718 | * some operation and then restore it. In order to avoid | 1721 | * some operation and then restore it. In order to avoid |
1719 | * setting IER register inadvertently to 0, if the value read | 1722 | * setting IER register inadvertently to 0, if the value read |
1720 | * is 0, double check with ier value in uart_8250_port and use | 1723 | * is 0, double check with ier value in uart_8250_port and use |
1721 | * that instead. up->ier should be the same value as what is | 1724 | * that instead. up->ier should be the same value as what is |
1722 | * currently configured. | 1725 | * currently configured. |
1723 | */ | 1726 | */ |
1724 | val = inb(p->iobase + offset); | 1727 | val = inb(p->iobase + offset); |
1725 | if (offset == UART_IER) { | 1728 | if (offset == UART_IER) { |
1726 | if (val == 0) | 1729 | if (val == 0) |
1727 | val = up->ier; | 1730 | val = up->ier; |
1728 | } | 1731 | } |
1729 | return val; | 1732 | return val; |
1730 | } | 1733 | } |
1731 | 1734 | ||
1732 | static int kt_serial_setup(struct serial_private *priv, | 1735 | static int kt_serial_setup(struct serial_private *priv, |
1733 | const struct pciserial_board *board, | 1736 | const struct pciserial_board *board, |
1734 | struct uart_8250_port *port, int idx) | 1737 | struct uart_8250_port *port, int idx) |
1735 | { | 1738 | { |
1736 | port->port.flags |= UPF_BUG_THRE; | 1739 | port->port.flags |= UPF_BUG_THRE; |
1737 | port->port.serial_in = kt_serial_in; | 1740 | port->port.serial_in = kt_serial_in; |
1738 | port->port.handle_break = kt_handle_break; | 1741 | port->port.handle_break = kt_handle_break; |
1739 | return skip_tx_en_setup(priv, board, port, idx); | 1742 | return skip_tx_en_setup(priv, board, port, idx); |
1740 | } | 1743 | } |
1741 | 1744 | ||
1742 | static int pci_eg20t_init(struct pci_dev *dev) | 1745 | static int pci_eg20t_init(struct pci_dev *dev) |
1743 | { | 1746 | { |
1744 | #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) | 1747 | #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) |
1745 | return -ENODEV; | 1748 | return -ENODEV; |
1746 | #else | 1749 | #else |
1747 | return 0; | 1750 | return 0; |
1748 | #endif | 1751 | #endif |
1749 | } | 1752 | } |
1750 | 1753 | ||
1751 | #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 | 1754 | #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 |
1752 | #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 | 1755 | #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 |
1753 | 1756 | ||
1754 | static int | 1757 | static int |
1755 | pci_xr17c154_setup(struct serial_private *priv, | 1758 | pci_xr17c154_setup(struct serial_private *priv, |
1756 | const struct pciserial_board *board, | 1759 | const struct pciserial_board *board, |
1757 | struct uart_8250_port *port, int idx) | 1760 | struct uart_8250_port *port, int idx) |
1758 | { | 1761 | { |
1759 | port->port.flags |= UPF_EXAR_EFR; | 1762 | port->port.flags |= UPF_EXAR_EFR; |
1760 | return pci_default_setup(priv, board, port, idx); | 1763 | return pci_default_setup(priv, board, port, idx); |
1761 | } | 1764 | } |
1762 | 1765 | ||
1763 | static inline int | 1766 | static inline int |
1764 | xr17v35x_has_slave(struct serial_private *priv) | 1767 | xr17v35x_has_slave(struct serial_private *priv) |
1765 | { | 1768 | { |
1766 | const int dev_id = priv->dev->device; | 1769 | const int dev_id = priv->dev->device; |
1767 | 1770 | ||
1768 | return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) || | 1771 | return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) || |
1769 | (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358)); | 1772 | (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358)); |
1770 | } | 1773 | } |
1771 | 1774 | ||
1772 | static int | 1775 | static int |
1773 | pci_xr17v35x_setup(struct serial_private *priv, | 1776 | pci_xr17v35x_setup(struct serial_private *priv, |
1774 | const struct pciserial_board *board, | 1777 | const struct pciserial_board *board, |
1775 | struct uart_8250_port *port, int idx) | 1778 | struct uart_8250_port *port, int idx) |
1776 | { | 1779 | { |
1777 | u8 __iomem *p; | 1780 | u8 __iomem *p; |
1778 | 1781 | ||
1779 | p = pci_ioremap_bar(priv->dev, 0); | 1782 | p = pci_ioremap_bar(priv->dev, 0); |
1780 | if (p == NULL) | 1783 | if (p == NULL) |
1781 | return -ENOMEM; | 1784 | return -ENOMEM; |
1782 | 1785 | ||
1783 | port->port.flags |= UPF_EXAR_EFR; | 1786 | port->port.flags |= UPF_EXAR_EFR; |
1784 | 1787 | ||
1785 | /* | 1788 | /* |
1786 | * Setup the uart clock for the devices on expansion slot to | 1789 | * Setup the uart clock for the devices on expansion slot to |
1787 | * half the clock speed of the main chip (which is 125MHz) | 1790 | * half the clock speed of the main chip (which is 125MHz) |
1788 | */ | 1791 | */ |
1789 | if (xr17v35x_has_slave(priv) && idx >= 8) | 1792 | if (xr17v35x_has_slave(priv) && idx >= 8) |
1790 | port->port.uartclk = (7812500 * 16 / 2); | 1793 | port->port.uartclk = (7812500 * 16 / 2); |
1791 | 1794 | ||
1792 | /* | 1795 | /* |
1793 | * Setup Multipurpose Input/Output pins. | 1796 | * Setup Multipurpose Input/Output pins. |
1794 | */ | 1797 | */ |
1795 | if (idx == 0) { | 1798 | if (idx == 0) { |
1796 | writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ | 1799 | writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ |
1797 | writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ | 1800 | writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ |
1798 | writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ | 1801 | writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ |
1799 | writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ | 1802 | writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ |
1800 | writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ | 1803 | writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ |
1801 | writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ | 1804 | writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ |
1802 | writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ | 1805 | writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ |
1803 | writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ | 1806 | writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ |
1804 | writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ | 1807 | writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ |
1805 | writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ | 1808 | writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ |
1806 | writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ | 1809 | writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ |
1807 | writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ | 1810 | writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ |
1808 | } | 1811 | } |
1809 | writeb(0x00, p + UART_EXAR_8XMODE); | 1812 | writeb(0x00, p + UART_EXAR_8XMODE); |
1810 | writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); | 1813 | writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); |
1811 | writeb(128, p + UART_EXAR_TXTRG); | 1814 | writeb(128, p + UART_EXAR_TXTRG); |
1812 | writeb(128, p + UART_EXAR_RXTRG); | 1815 | writeb(128, p + UART_EXAR_RXTRG); |
1813 | iounmap(p); | 1816 | iounmap(p); |
1814 | 1817 | ||
1815 | return pci_default_setup(priv, board, port, idx); | 1818 | return pci_default_setup(priv, board, port, idx); |
1816 | } | 1819 | } |
1817 | 1820 | ||
1818 | #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 | 1821 | #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 |
1819 | #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 | 1822 | #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 |
1820 | #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a | 1823 | #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a |
1821 | #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b | 1824 | #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b |
1822 | 1825 | ||
1823 | static int | 1826 | static int |
1824 | pci_fastcom335_setup(struct serial_private *priv, | 1827 | pci_fastcom335_setup(struct serial_private *priv, |
1825 | const struct pciserial_board *board, | 1828 | const struct pciserial_board *board, |
1826 | struct uart_8250_port *port, int idx) | 1829 | struct uart_8250_port *port, int idx) |
1827 | { | 1830 | { |
1828 | u8 __iomem *p; | 1831 | u8 __iomem *p; |
1829 | 1832 | ||
1830 | p = pci_ioremap_bar(priv->dev, 0); | 1833 | p = pci_ioremap_bar(priv->dev, 0); |
1831 | if (p == NULL) | 1834 | if (p == NULL) |
1832 | return -ENOMEM; | 1835 | return -ENOMEM; |
1833 | 1836 | ||
1834 | port->port.flags |= UPF_EXAR_EFR; | 1837 | port->port.flags |= UPF_EXAR_EFR; |
1835 | 1838 | ||
1836 | /* | 1839 | /* |
1837 | * Setup Multipurpose Input/Output pins. | 1840 | * Setup Multipurpose Input/Output pins. |
1838 | */ | 1841 | */ |
1839 | if (idx == 0) { | 1842 | if (idx == 0) { |
1840 | switch (priv->dev->device) { | 1843 | switch (priv->dev->device) { |
1841 | case PCI_DEVICE_ID_COMMTECH_4222PCI335: | 1844 | case PCI_DEVICE_ID_COMMTECH_4222PCI335: |
1842 | case PCI_DEVICE_ID_COMMTECH_4224PCI335: | 1845 | case PCI_DEVICE_ID_COMMTECH_4224PCI335: |
1843 | writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ | 1846 | writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ |
1844 | writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ | 1847 | writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ |
1845 | writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ | 1848 | writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ |
1846 | break; | 1849 | break; |
1847 | case PCI_DEVICE_ID_COMMTECH_2324PCI335: | 1850 | case PCI_DEVICE_ID_COMMTECH_2324PCI335: |
1848 | case PCI_DEVICE_ID_COMMTECH_2328PCI335: | 1851 | case PCI_DEVICE_ID_COMMTECH_2328PCI335: |
1849 | writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ | 1852 | writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ |
1850 | writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ | 1853 | writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ |
1851 | writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ | 1854 | writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ |
1852 | break; | 1855 | break; |
1853 | } | 1856 | } |
1854 | writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ | 1857 | writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ |
1855 | writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ | 1858 | writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ |
1856 | writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ | 1859 | writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ |
1857 | } | 1860 | } |
1858 | writeb(0x00, p + UART_EXAR_8XMODE); | 1861 | writeb(0x00, p + UART_EXAR_8XMODE); |
1859 | writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); | 1862 | writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); |
1860 | writeb(32, p + UART_EXAR_TXTRG); | 1863 | writeb(32, p + UART_EXAR_TXTRG); |
1861 | writeb(32, p + UART_EXAR_RXTRG); | 1864 | writeb(32, p + UART_EXAR_RXTRG); |
1862 | iounmap(p); | 1865 | iounmap(p); |
1863 | 1866 | ||
1864 | return pci_default_setup(priv, board, port, idx); | 1867 | return pci_default_setup(priv, board, port, idx); |
1865 | } | 1868 | } |
1866 | 1869 | ||
1867 | static int | 1870 | static int |
1868 | pci_wch_ch353_setup(struct serial_private *priv, | 1871 | pci_wch_ch353_setup(struct serial_private *priv, |
1869 | const struct pciserial_board *board, | 1872 | const struct pciserial_board *board, |
1870 | struct uart_8250_port *port, int idx) | 1873 | struct uart_8250_port *port, int idx) |
1871 | { | 1874 | { |
1872 | port->port.flags |= UPF_FIXED_TYPE; | 1875 | port->port.flags |= UPF_FIXED_TYPE; |
1873 | port->port.type = PORT_16550A; | 1876 | port->port.type = PORT_16550A; |
1874 | return pci_default_setup(priv, board, port, idx); | 1877 | return pci_default_setup(priv, board, port, idx); |
1875 | } | 1878 | } |
1876 | 1879 | ||
1877 | static int | 1880 | static int |
1878 | pci_wch_ch38x_setup(struct serial_private *priv, | 1881 | pci_wch_ch38x_setup(struct serial_private *priv, |
1879 | const struct pciserial_board *board, | 1882 | const struct pciserial_board *board, |
1880 | struct uart_8250_port *port, int idx) | 1883 | struct uart_8250_port *port, int idx) |
1881 | { | 1884 | { |
1882 | port->port.flags |= UPF_FIXED_TYPE; | 1885 | port->port.flags |= UPF_FIXED_TYPE; |
1883 | port->port.type = PORT_16850; | 1886 | port->port.type = PORT_16850; |
1884 | return pci_default_setup(priv, board, port, idx); | 1887 | return pci_default_setup(priv, board, port, idx); |
1885 | } | 1888 | } |
1886 | 1889 | ||
1887 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B | 1890 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B |
1888 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B | 1891 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B |
1889 | #define PCI_DEVICE_ID_OCTPRO 0x0001 | 1892 | #define PCI_DEVICE_ID_OCTPRO 0x0001 |
1890 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 | 1893 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 |
1891 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 | 1894 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 |
1892 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 | 1895 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 |
1893 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 | 1896 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 |
1894 | #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 | 1897 | #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 |
1895 | #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 | 1898 | #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 |
1896 | #define PCI_VENDOR_ID_ADVANTECH 0x13fe | 1899 | #define PCI_VENDOR_ID_ADVANTECH 0x13fe |
1897 | #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 | 1900 | #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 |
1898 | #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 | 1901 | #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 |
1899 | #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 | 1902 | #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 |
1900 | #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 | 1903 | #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 |
1901 | #define PCI_DEVICE_ID_TITAN_200I 0x8028 | 1904 | #define PCI_DEVICE_ID_TITAN_200I 0x8028 |
1902 | #define PCI_DEVICE_ID_TITAN_400I 0x8048 | 1905 | #define PCI_DEVICE_ID_TITAN_400I 0x8048 |
1903 | #define PCI_DEVICE_ID_TITAN_800I 0x8088 | 1906 | #define PCI_DEVICE_ID_TITAN_800I 0x8088 |
1904 | #define PCI_DEVICE_ID_TITAN_800EH 0xA007 | 1907 | #define PCI_DEVICE_ID_TITAN_800EH 0xA007 |
1905 | #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 | 1908 | #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 |
1906 | #define PCI_DEVICE_ID_TITAN_400EH 0xA009 | 1909 | #define PCI_DEVICE_ID_TITAN_400EH 0xA009 |
1907 | #define PCI_DEVICE_ID_TITAN_100E 0xA010 | 1910 | #define PCI_DEVICE_ID_TITAN_100E 0xA010 |
1908 | #define PCI_DEVICE_ID_TITAN_200E 0xA012 | 1911 | #define PCI_DEVICE_ID_TITAN_200E 0xA012 |
1909 | #define PCI_DEVICE_ID_TITAN_400E 0xA013 | 1912 | #define PCI_DEVICE_ID_TITAN_400E 0xA013 |
1910 | #define PCI_DEVICE_ID_TITAN_800E 0xA014 | 1913 | #define PCI_DEVICE_ID_TITAN_800E 0xA014 |
1911 | #define PCI_DEVICE_ID_TITAN_200EI 0xA016 | 1914 | #define PCI_DEVICE_ID_TITAN_200EI 0xA016 |
1912 | #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 | 1915 | #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 |
1913 | #define PCI_DEVICE_ID_TITAN_200V3 0xA306 | 1916 | #define PCI_DEVICE_ID_TITAN_200V3 0xA306 |
1914 | #define PCI_DEVICE_ID_TITAN_400V3 0xA310 | 1917 | #define PCI_DEVICE_ID_TITAN_400V3 0xA310 |
1915 | #define PCI_DEVICE_ID_TITAN_410V3 0xA312 | 1918 | #define PCI_DEVICE_ID_TITAN_410V3 0xA312 |
1916 | #define PCI_DEVICE_ID_TITAN_800V3 0xA314 | 1919 | #define PCI_DEVICE_ID_TITAN_800V3 0xA314 |
1917 | #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 | 1920 | #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 |
1918 | #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 | 1921 | #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 |
1919 | #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 | 1922 | #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 |
1920 | #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 | 1923 | #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 |
1921 | #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d | 1924 | #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d |
1922 | #define PCI_VENDOR_ID_WCH 0x4348 | 1925 | #define PCI_VENDOR_ID_WCH 0x4348 |
1923 | #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 | 1926 | #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 |
1924 | #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 | 1927 | #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 |
1925 | #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 | 1928 | #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 |
1926 | #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 | 1929 | #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 |
1927 | #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 | 1930 | #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 |
1928 | #define PCI_VENDOR_ID_AGESTAR 0x5372 | 1931 | #define PCI_VENDOR_ID_AGESTAR 0x5372 |
1929 | #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 | 1932 | #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 |
1930 | #define PCI_VENDOR_ID_ASIX 0x9710 | 1933 | #define PCI_VENDOR_ID_ASIX 0x9710 |
1931 | #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 | 1934 | #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 |
1932 | #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 | 1935 | #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 |
1933 | #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 | 1936 | #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 |
1934 | #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a | 1937 | #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a |
1935 | #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e | 1938 | #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e |
1936 | #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 | 1939 | #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 |
1937 | 1940 | ||
1938 | #define PCI_VENDOR_ID_SUNIX 0x1fd4 | 1941 | #define PCI_VENDOR_ID_SUNIX 0x1fd4 |
1939 | #define PCI_DEVICE_ID_SUNIX_1999 0x1999 | 1942 | #define PCI_DEVICE_ID_SUNIX_1999 0x1999 |
1940 | 1943 | ||
1941 | #define PCIE_VENDOR_ID_WCH 0x1c00 | 1944 | #define PCIE_VENDOR_ID_WCH 0x1c00 |
1942 | #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 | 1945 | #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 |
1943 | #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 | 1946 | #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 |
1944 | #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 | 1947 | #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 |
1945 | 1948 | ||
1946 | #define PCI_VENDOR_ID_PERICOM 0x12D8 | 1949 | #define PCI_VENDOR_ID_PERICOM 0x12D8 |
1947 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 | 1950 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 |
1948 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 | 1951 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 |
1949 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 | 1952 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 |
1950 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 | 1953 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 |
1951 | 1954 | ||
1952 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ | 1955 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ |
1953 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 | 1956 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 |
1954 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 | 1957 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 |
1955 | 1958 | ||
1956 | /* | 1959 | /* |
1957 | * Master list of serial port init/setup/exit quirks. | 1960 | * Master list of serial port init/setup/exit quirks. |
1958 | * This does not describe the general nature of the port. | 1961 | * This does not describe the general nature of the port. |
1959 | * (ie, baud base, number and location of ports, etc) | 1962 | * (ie, baud base, number and location of ports, etc) |
1960 | * | 1963 | * |
1961 | * This list is ordered alphabetically by vendor then device. | 1964 | * This list is ordered alphabetically by vendor then device. |
1962 | * Specific entries must come before more generic entries. | 1965 | * Specific entries must come before more generic entries. |
1963 | */ | 1966 | */ |
1964 | static struct pci_serial_quirk pci_serial_quirks[] __refdata = { | 1967 | static struct pci_serial_quirk pci_serial_quirks[] __refdata = { |
1965 | /* | 1968 | /* |
1966 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | 1969 | * ADDI-DATA GmbH communication cards <info@addi-data.com> |
1967 | */ | 1970 | */ |
1968 | { | 1971 | { |
1969 | .vendor = PCI_VENDOR_ID_AMCC, | 1972 | .vendor = PCI_VENDOR_ID_AMCC, |
1970 | .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, | 1973 | .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, |
1971 | .subvendor = PCI_ANY_ID, | 1974 | .subvendor = PCI_ANY_ID, |
1972 | .subdevice = PCI_ANY_ID, | 1975 | .subdevice = PCI_ANY_ID, |
1973 | .setup = addidata_apci7800_setup, | 1976 | .setup = addidata_apci7800_setup, |
1974 | }, | 1977 | }, |
1975 | /* | 1978 | /* |
1976 | * AFAVLAB cards - these may be called via parport_serial | 1979 | * AFAVLAB cards - these may be called via parport_serial |
1977 | * It is not clear whether this applies to all products. | 1980 | * It is not clear whether this applies to all products. |
1978 | */ | 1981 | */ |
1979 | { | 1982 | { |
1980 | .vendor = PCI_VENDOR_ID_AFAVLAB, | 1983 | .vendor = PCI_VENDOR_ID_AFAVLAB, |
1981 | .device = PCI_ANY_ID, | 1984 | .device = PCI_ANY_ID, |
1982 | .subvendor = PCI_ANY_ID, | 1985 | .subvendor = PCI_ANY_ID, |
1983 | .subdevice = PCI_ANY_ID, | 1986 | .subdevice = PCI_ANY_ID, |
1984 | .setup = afavlab_setup, | 1987 | .setup = afavlab_setup, |
1985 | }, | 1988 | }, |
1986 | /* | 1989 | /* |
1987 | * HP Diva | 1990 | * HP Diva |
1988 | */ | 1991 | */ |
1989 | { | 1992 | { |
1990 | .vendor = PCI_VENDOR_ID_HP, | 1993 | .vendor = PCI_VENDOR_ID_HP, |
1991 | .device = PCI_DEVICE_ID_HP_DIVA, | 1994 | .device = PCI_DEVICE_ID_HP_DIVA, |
1992 | .subvendor = PCI_ANY_ID, | 1995 | .subvendor = PCI_ANY_ID, |
1993 | .subdevice = PCI_ANY_ID, | 1996 | .subdevice = PCI_ANY_ID, |
1994 | .init = pci_hp_diva_init, | 1997 | .init = pci_hp_diva_init, |
1995 | .setup = pci_hp_diva_setup, | 1998 | .setup = pci_hp_diva_setup, |
1996 | }, | 1999 | }, |
1997 | /* | 2000 | /* |
1998 | * Intel | 2001 | * Intel |
1999 | */ | 2002 | */ |
2000 | { | 2003 | { |
2001 | .vendor = PCI_VENDOR_ID_INTEL, | 2004 | .vendor = PCI_VENDOR_ID_INTEL, |
2002 | .device = PCI_DEVICE_ID_INTEL_80960_RP, | 2005 | .device = PCI_DEVICE_ID_INTEL_80960_RP, |
2003 | .subvendor = 0xe4bf, | 2006 | .subvendor = 0xe4bf, |
2004 | .subdevice = PCI_ANY_ID, | 2007 | .subdevice = PCI_ANY_ID, |
2005 | .init = pci_inteli960ni_init, | 2008 | .init = pci_inteli960ni_init, |
2006 | .setup = pci_default_setup, | 2009 | .setup = pci_default_setup, |
2007 | }, | 2010 | }, |
2008 | { | 2011 | { |
2009 | .vendor = PCI_VENDOR_ID_INTEL, | 2012 | .vendor = PCI_VENDOR_ID_INTEL, |
2010 | .device = PCI_DEVICE_ID_INTEL_8257X_SOL, | 2013 | .device = PCI_DEVICE_ID_INTEL_8257X_SOL, |
2011 | .subvendor = PCI_ANY_ID, | 2014 | .subvendor = PCI_ANY_ID, |
2012 | .subdevice = PCI_ANY_ID, | 2015 | .subdevice = PCI_ANY_ID, |
2013 | .setup = skip_tx_en_setup, | 2016 | .setup = skip_tx_en_setup, |
2014 | }, | 2017 | }, |
2015 | { | 2018 | { |
2016 | .vendor = PCI_VENDOR_ID_INTEL, | 2019 | .vendor = PCI_VENDOR_ID_INTEL, |
2017 | .device = PCI_DEVICE_ID_INTEL_82573L_SOL, | 2020 | .device = PCI_DEVICE_ID_INTEL_82573L_SOL, |
2018 | .subvendor = PCI_ANY_ID, | 2021 | .subvendor = PCI_ANY_ID, |
2019 | .subdevice = PCI_ANY_ID, | 2022 | .subdevice = PCI_ANY_ID, |
2020 | .setup = skip_tx_en_setup, | 2023 | .setup = skip_tx_en_setup, |
2021 | }, | 2024 | }, |
2022 | { | 2025 | { |
2023 | .vendor = PCI_VENDOR_ID_INTEL, | 2026 | .vendor = PCI_VENDOR_ID_INTEL, |
2024 | .device = PCI_DEVICE_ID_INTEL_82573E_SOL, | 2027 | .device = PCI_DEVICE_ID_INTEL_82573E_SOL, |
2025 | .subvendor = PCI_ANY_ID, | 2028 | .subvendor = PCI_ANY_ID, |
2026 | .subdevice = PCI_ANY_ID, | 2029 | .subdevice = PCI_ANY_ID, |
2027 | .setup = skip_tx_en_setup, | 2030 | .setup = skip_tx_en_setup, |
2028 | }, | 2031 | }, |
2029 | { | 2032 | { |
2030 | .vendor = PCI_VENDOR_ID_INTEL, | 2033 | .vendor = PCI_VENDOR_ID_INTEL, |
2031 | .device = PCI_DEVICE_ID_INTEL_CE4100_UART, | 2034 | .device = PCI_DEVICE_ID_INTEL_CE4100_UART, |
2032 | .subvendor = PCI_ANY_ID, | 2035 | .subvendor = PCI_ANY_ID, |
2033 | .subdevice = PCI_ANY_ID, | 2036 | .subdevice = PCI_ANY_ID, |
2034 | .setup = ce4100_serial_setup, | 2037 | .setup = ce4100_serial_setup, |
2035 | }, | 2038 | }, |
2036 | { | 2039 | { |
2037 | .vendor = PCI_VENDOR_ID_INTEL, | 2040 | .vendor = PCI_VENDOR_ID_INTEL, |
2038 | .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, | 2041 | .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, |
2039 | .subvendor = PCI_ANY_ID, | 2042 | .subvendor = PCI_ANY_ID, |
2040 | .subdevice = PCI_ANY_ID, | 2043 | .subdevice = PCI_ANY_ID, |
2041 | .setup = kt_serial_setup, | 2044 | .setup = kt_serial_setup, |
2042 | }, | 2045 | }, |
2043 | { | 2046 | { |
2044 | .vendor = PCI_VENDOR_ID_INTEL, | 2047 | .vendor = PCI_VENDOR_ID_INTEL, |
2045 | .device = PCI_DEVICE_ID_INTEL_BYT_UART1, | 2048 | .device = PCI_DEVICE_ID_INTEL_BYT_UART1, |
2046 | .subvendor = PCI_ANY_ID, | 2049 | .subvendor = PCI_ANY_ID, |
2047 | .subdevice = PCI_ANY_ID, | 2050 | .subdevice = PCI_ANY_ID, |
2048 | .setup = byt_serial_setup, | 2051 | .setup = byt_serial_setup, |
2049 | }, | 2052 | }, |
2050 | { | 2053 | { |
2051 | .vendor = PCI_VENDOR_ID_INTEL, | 2054 | .vendor = PCI_VENDOR_ID_INTEL, |
2052 | .device = PCI_DEVICE_ID_INTEL_BYT_UART2, | 2055 | .device = PCI_DEVICE_ID_INTEL_BYT_UART2, |
2053 | .subvendor = PCI_ANY_ID, | 2056 | .subvendor = PCI_ANY_ID, |
2054 | .subdevice = PCI_ANY_ID, | 2057 | .subdevice = PCI_ANY_ID, |
2055 | .setup = byt_serial_setup, | 2058 | .setup = byt_serial_setup, |
2056 | }, | 2059 | }, |
2057 | { | 2060 | { |
2058 | .vendor = PCI_VENDOR_ID_INTEL, | 2061 | .vendor = PCI_VENDOR_ID_INTEL, |
2059 | .device = PCI_DEVICE_ID_INTEL_BSW_UART1, | 2062 | .device = PCI_DEVICE_ID_INTEL_BSW_UART1, |
2060 | .subvendor = PCI_ANY_ID, | 2063 | .subvendor = PCI_ANY_ID, |
2061 | .subdevice = PCI_ANY_ID, | 2064 | .subdevice = PCI_ANY_ID, |
2062 | .setup = byt_serial_setup, | 2065 | .setup = byt_serial_setup, |
2063 | }, | 2066 | }, |
2064 | { | 2067 | { |
2065 | .vendor = PCI_VENDOR_ID_INTEL, | 2068 | .vendor = PCI_VENDOR_ID_INTEL, |
2066 | .device = PCI_DEVICE_ID_INTEL_BSW_UART2, | 2069 | .device = PCI_DEVICE_ID_INTEL_BSW_UART2, |
2067 | .subvendor = PCI_ANY_ID, | 2070 | .subvendor = PCI_ANY_ID, |
2068 | .subdevice = PCI_ANY_ID, | 2071 | .subdevice = PCI_ANY_ID, |
2069 | .setup = byt_serial_setup, | 2072 | .setup = byt_serial_setup, |
2070 | }, | 2073 | }, |
2071 | { | 2074 | { |
2072 | .vendor = PCI_VENDOR_ID_INTEL, | 2075 | .vendor = PCI_VENDOR_ID_INTEL, |
2073 | .device = PCI_DEVICE_ID_INTEL_BDW_UART1, | 2076 | .device = PCI_DEVICE_ID_INTEL_BDW_UART1, |
2074 | .subvendor = PCI_ANY_ID, | 2077 | .subvendor = PCI_ANY_ID, |
2075 | .subdevice = PCI_ANY_ID, | 2078 | .subdevice = PCI_ANY_ID, |
2076 | .setup = byt_serial_setup, | 2079 | .setup = byt_serial_setup, |
2077 | }, | 2080 | }, |
2078 | { | 2081 | { |
2079 | .vendor = PCI_VENDOR_ID_INTEL, | 2082 | .vendor = PCI_VENDOR_ID_INTEL, |
2080 | .device = PCI_DEVICE_ID_INTEL_BDW_UART2, | 2083 | .device = PCI_DEVICE_ID_INTEL_BDW_UART2, |
2081 | .subvendor = PCI_ANY_ID, | 2084 | .subvendor = PCI_ANY_ID, |
2082 | .subdevice = PCI_ANY_ID, | 2085 | .subdevice = PCI_ANY_ID, |
2083 | .setup = byt_serial_setup, | 2086 | .setup = byt_serial_setup, |
2084 | }, | 2087 | }, |
2085 | /* | 2088 | /* |
2086 | * ITE | 2089 | * ITE |
2087 | */ | 2090 | */ |
2088 | { | 2091 | { |
2089 | .vendor = PCI_VENDOR_ID_ITE, | 2092 | .vendor = PCI_VENDOR_ID_ITE, |
2090 | .device = PCI_DEVICE_ID_ITE_8872, | 2093 | .device = PCI_DEVICE_ID_ITE_8872, |
2091 | .subvendor = PCI_ANY_ID, | 2094 | .subvendor = PCI_ANY_ID, |
2092 | .subdevice = PCI_ANY_ID, | 2095 | .subdevice = PCI_ANY_ID, |
2093 | .init = pci_ite887x_init, | 2096 | .init = pci_ite887x_init, |
2094 | .setup = pci_default_setup, | 2097 | .setup = pci_default_setup, |
2095 | .exit = pci_ite887x_exit, | 2098 | .exit = pci_ite887x_exit, |
2096 | }, | 2099 | }, |
2097 | /* | 2100 | /* |
2098 | * National Instruments | 2101 | * National Instruments |
2099 | */ | 2102 | */ |
2100 | { | 2103 | { |
2101 | .vendor = PCI_VENDOR_ID_NI, | 2104 | .vendor = PCI_VENDOR_ID_NI, |
2102 | .device = PCI_DEVICE_ID_NI_PCI23216, | 2105 | .device = PCI_DEVICE_ID_NI_PCI23216, |
2103 | .subvendor = PCI_ANY_ID, | 2106 | .subvendor = PCI_ANY_ID, |
2104 | .subdevice = PCI_ANY_ID, | 2107 | .subdevice = PCI_ANY_ID, |
2105 | .init = pci_ni8420_init, | 2108 | .init = pci_ni8420_init, |
2106 | .setup = pci_default_setup, | 2109 | .setup = pci_default_setup, |
2107 | .exit = pci_ni8420_exit, | 2110 | .exit = pci_ni8420_exit, |
2108 | }, | 2111 | }, |
2109 | { | 2112 | { |
2110 | .vendor = PCI_VENDOR_ID_NI, | 2113 | .vendor = PCI_VENDOR_ID_NI, |
2111 | .device = PCI_DEVICE_ID_NI_PCI2328, | 2114 | .device = PCI_DEVICE_ID_NI_PCI2328, |
2112 | .subvendor = PCI_ANY_ID, | 2115 | .subvendor = PCI_ANY_ID, |
2113 | .subdevice = PCI_ANY_ID, | 2116 | .subdevice = PCI_ANY_ID, |
2114 | .init = pci_ni8420_init, | 2117 | .init = pci_ni8420_init, |
2115 | .setup = pci_default_setup, | 2118 | .setup = pci_default_setup, |
2116 | .exit = pci_ni8420_exit, | 2119 | .exit = pci_ni8420_exit, |
2117 | }, | 2120 | }, |
2118 | { | 2121 | { |
2119 | .vendor = PCI_VENDOR_ID_NI, | 2122 | .vendor = PCI_VENDOR_ID_NI, |
2120 | .device = PCI_DEVICE_ID_NI_PCI2324, | 2123 | .device = PCI_DEVICE_ID_NI_PCI2324, |
2121 | .subvendor = PCI_ANY_ID, | 2124 | .subvendor = PCI_ANY_ID, |
2122 | .subdevice = PCI_ANY_ID, | 2125 | .subdevice = PCI_ANY_ID, |
2123 | .init = pci_ni8420_init, | 2126 | .init = pci_ni8420_init, |
2124 | .setup = pci_default_setup, | 2127 | .setup = pci_default_setup, |
2125 | .exit = pci_ni8420_exit, | 2128 | .exit = pci_ni8420_exit, |
2126 | }, | 2129 | }, |
2127 | { | 2130 | { |
2128 | .vendor = PCI_VENDOR_ID_NI, | 2131 | .vendor = PCI_VENDOR_ID_NI, |
2129 | .device = PCI_DEVICE_ID_NI_PCI2322, | 2132 | .device = PCI_DEVICE_ID_NI_PCI2322, |
2130 | .subvendor = PCI_ANY_ID, | 2133 | .subvendor = PCI_ANY_ID, |
2131 | .subdevice = PCI_ANY_ID, | 2134 | .subdevice = PCI_ANY_ID, |
2132 | .init = pci_ni8420_init, | 2135 | .init = pci_ni8420_init, |
2133 | .setup = pci_default_setup, | 2136 | .setup = pci_default_setup, |
2134 | .exit = pci_ni8420_exit, | 2137 | .exit = pci_ni8420_exit, |
2135 | }, | 2138 | }, |
2136 | { | 2139 | { |
2137 | .vendor = PCI_VENDOR_ID_NI, | 2140 | .vendor = PCI_VENDOR_ID_NI, |
2138 | .device = PCI_DEVICE_ID_NI_PCI2324I, | 2141 | .device = PCI_DEVICE_ID_NI_PCI2324I, |
2139 | .subvendor = PCI_ANY_ID, | 2142 | .subvendor = PCI_ANY_ID, |
2140 | .subdevice = PCI_ANY_ID, | 2143 | .subdevice = PCI_ANY_ID, |
2141 | .init = pci_ni8420_init, | 2144 | .init = pci_ni8420_init, |
2142 | .setup = pci_default_setup, | 2145 | .setup = pci_default_setup, |
2143 | .exit = pci_ni8420_exit, | 2146 | .exit = pci_ni8420_exit, |
2144 | }, | 2147 | }, |
2145 | { | 2148 | { |
2146 | .vendor = PCI_VENDOR_ID_NI, | 2149 | .vendor = PCI_VENDOR_ID_NI, |
2147 | .device = PCI_DEVICE_ID_NI_PCI2322I, | 2150 | .device = PCI_DEVICE_ID_NI_PCI2322I, |
2148 | .subvendor = PCI_ANY_ID, | 2151 | .subvendor = PCI_ANY_ID, |
2149 | .subdevice = PCI_ANY_ID, | 2152 | .subdevice = PCI_ANY_ID, |
2150 | .init = pci_ni8420_init, | 2153 | .init = pci_ni8420_init, |
2151 | .setup = pci_default_setup, | 2154 | .setup = pci_default_setup, |
2152 | .exit = pci_ni8420_exit, | 2155 | .exit = pci_ni8420_exit, |
2153 | }, | 2156 | }, |
2154 | { | 2157 | { |
2155 | .vendor = PCI_VENDOR_ID_NI, | 2158 | .vendor = PCI_VENDOR_ID_NI, |
2156 | .device = PCI_DEVICE_ID_NI_PXI8420_23216, | 2159 | .device = PCI_DEVICE_ID_NI_PXI8420_23216, |
2157 | .subvendor = PCI_ANY_ID, | 2160 | .subvendor = PCI_ANY_ID, |
2158 | .subdevice = PCI_ANY_ID, | 2161 | .subdevice = PCI_ANY_ID, |
2159 | .init = pci_ni8420_init, | 2162 | .init = pci_ni8420_init, |
2160 | .setup = pci_default_setup, | 2163 | .setup = pci_default_setup, |
2161 | .exit = pci_ni8420_exit, | 2164 | .exit = pci_ni8420_exit, |
2162 | }, | 2165 | }, |
2163 | { | 2166 | { |
2164 | .vendor = PCI_VENDOR_ID_NI, | 2167 | .vendor = PCI_VENDOR_ID_NI, |
2165 | .device = PCI_DEVICE_ID_NI_PXI8420_2328, | 2168 | .device = PCI_DEVICE_ID_NI_PXI8420_2328, |
2166 | .subvendor = PCI_ANY_ID, | 2169 | .subvendor = PCI_ANY_ID, |
2167 | .subdevice = PCI_ANY_ID, | 2170 | .subdevice = PCI_ANY_ID, |
2168 | .init = pci_ni8420_init, | 2171 | .init = pci_ni8420_init, |
2169 | .setup = pci_default_setup, | 2172 | .setup = pci_default_setup, |
2170 | .exit = pci_ni8420_exit, | 2173 | .exit = pci_ni8420_exit, |
2171 | }, | 2174 | }, |
2172 | { | 2175 | { |
2173 | .vendor = PCI_VENDOR_ID_NI, | 2176 | .vendor = PCI_VENDOR_ID_NI, |
2174 | .device = PCI_DEVICE_ID_NI_PXI8420_2324, | 2177 | .device = PCI_DEVICE_ID_NI_PXI8420_2324, |
2175 | .subvendor = PCI_ANY_ID, | 2178 | .subvendor = PCI_ANY_ID, |
2176 | .subdevice = PCI_ANY_ID, | 2179 | .subdevice = PCI_ANY_ID, |
2177 | .init = pci_ni8420_init, | 2180 | .init = pci_ni8420_init, |
2178 | .setup = pci_default_setup, | 2181 | .setup = pci_default_setup, |
2179 | .exit = pci_ni8420_exit, | 2182 | .exit = pci_ni8420_exit, |
2180 | }, | 2183 | }, |
2181 | { | 2184 | { |
2182 | .vendor = PCI_VENDOR_ID_NI, | 2185 | .vendor = PCI_VENDOR_ID_NI, |
2183 | .device = PCI_DEVICE_ID_NI_PXI8420_2322, | 2186 | .device = PCI_DEVICE_ID_NI_PXI8420_2322, |
2184 | .subvendor = PCI_ANY_ID, | 2187 | .subvendor = PCI_ANY_ID, |
2185 | .subdevice = PCI_ANY_ID, | 2188 | .subdevice = PCI_ANY_ID, |
2186 | .init = pci_ni8420_init, | 2189 | .init = pci_ni8420_init, |
2187 | .setup = pci_default_setup, | 2190 | .setup = pci_default_setup, |
2188 | .exit = pci_ni8420_exit, | 2191 | .exit = pci_ni8420_exit, |
2189 | }, | 2192 | }, |
2190 | { | 2193 | { |
2191 | .vendor = PCI_VENDOR_ID_NI, | 2194 | .vendor = PCI_VENDOR_ID_NI, |
2192 | .device = PCI_DEVICE_ID_NI_PXI8422_2324, | 2195 | .device = PCI_DEVICE_ID_NI_PXI8422_2324, |
2193 | .subvendor = PCI_ANY_ID, | 2196 | .subvendor = PCI_ANY_ID, |
2194 | .subdevice = PCI_ANY_ID, | 2197 | .subdevice = PCI_ANY_ID, |
2195 | .init = pci_ni8420_init, | 2198 | .init = pci_ni8420_init, |
2196 | .setup = pci_default_setup, | 2199 | .setup = pci_default_setup, |
2197 | .exit = pci_ni8420_exit, | 2200 | .exit = pci_ni8420_exit, |
2198 | }, | 2201 | }, |
2199 | { | 2202 | { |
2200 | .vendor = PCI_VENDOR_ID_NI, | 2203 | .vendor = PCI_VENDOR_ID_NI, |
2201 | .device = PCI_DEVICE_ID_NI_PXI8422_2322, | 2204 | .device = PCI_DEVICE_ID_NI_PXI8422_2322, |
2202 | .subvendor = PCI_ANY_ID, | 2205 | .subvendor = PCI_ANY_ID, |
2203 | .subdevice = PCI_ANY_ID, | 2206 | .subdevice = PCI_ANY_ID, |
2204 | .init = pci_ni8420_init, | 2207 | .init = pci_ni8420_init, |
2205 | .setup = pci_default_setup, | 2208 | .setup = pci_default_setup, |
2206 | .exit = pci_ni8420_exit, | 2209 | .exit = pci_ni8420_exit, |
2207 | }, | 2210 | }, |
2208 | { | 2211 | { |
2209 | .vendor = PCI_VENDOR_ID_NI, | 2212 | .vendor = PCI_VENDOR_ID_NI, |
2210 | .device = PCI_ANY_ID, | 2213 | .device = PCI_ANY_ID, |
2211 | .subvendor = PCI_ANY_ID, | 2214 | .subvendor = PCI_ANY_ID, |
2212 | .subdevice = PCI_ANY_ID, | 2215 | .subdevice = PCI_ANY_ID, |
2213 | .init = pci_ni8430_init, | 2216 | .init = pci_ni8430_init, |
2214 | .setup = pci_ni8430_setup, | 2217 | .setup = pci_ni8430_setup, |
2215 | .exit = pci_ni8430_exit, | 2218 | .exit = pci_ni8430_exit, |
2216 | }, | 2219 | }, |
2217 | /* Quatech */ | 2220 | /* Quatech */ |
2218 | { | 2221 | { |
2219 | .vendor = PCI_VENDOR_ID_QUATECH, | 2222 | .vendor = PCI_VENDOR_ID_QUATECH, |
2220 | .device = PCI_ANY_ID, | 2223 | .device = PCI_ANY_ID, |
2221 | .subvendor = PCI_ANY_ID, | 2224 | .subvendor = PCI_ANY_ID, |
2222 | .subdevice = PCI_ANY_ID, | 2225 | .subdevice = PCI_ANY_ID, |
2223 | .init = pci_quatech_init, | 2226 | .init = pci_quatech_init, |
2224 | .setup = pci_quatech_setup, | 2227 | .setup = pci_quatech_setup, |
2225 | .exit = pci_quatech_exit, | 2228 | .exit = pci_quatech_exit, |
2226 | }, | 2229 | }, |
2227 | /* | 2230 | /* |
2228 | * Panacom | 2231 | * Panacom |
2229 | */ | 2232 | */ |
2230 | { | 2233 | { |
2231 | .vendor = PCI_VENDOR_ID_PANACOM, | 2234 | .vendor = PCI_VENDOR_ID_PANACOM, |
2232 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, | 2235 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, |
2233 | .subvendor = PCI_ANY_ID, | 2236 | .subvendor = PCI_ANY_ID, |
2234 | .subdevice = PCI_ANY_ID, | 2237 | .subdevice = PCI_ANY_ID, |
2235 | .init = pci_plx9050_init, | 2238 | .init = pci_plx9050_init, |
2236 | .setup = pci_default_setup, | 2239 | .setup = pci_default_setup, |
2237 | .exit = pci_plx9050_exit, | 2240 | .exit = pci_plx9050_exit, |
2238 | }, | 2241 | }, |
2239 | { | 2242 | { |
2240 | .vendor = PCI_VENDOR_ID_PANACOM, | 2243 | .vendor = PCI_VENDOR_ID_PANACOM, |
2241 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, | 2244 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, |
2242 | .subvendor = PCI_ANY_ID, | 2245 | .subvendor = PCI_ANY_ID, |
2243 | .subdevice = PCI_ANY_ID, | 2246 | .subdevice = PCI_ANY_ID, |
2244 | .init = pci_plx9050_init, | 2247 | .init = pci_plx9050_init, |
2245 | .setup = pci_default_setup, | 2248 | .setup = pci_default_setup, |
2246 | .exit = pci_plx9050_exit, | 2249 | .exit = pci_plx9050_exit, |
2247 | }, | 2250 | }, |
2248 | /* | 2251 | /* |
2249 | * Pericom | 2252 | * Pericom |
2250 | */ | 2253 | */ |
2251 | { | 2254 | { |
2252 | .vendor = PCI_VENDOR_ID_PERICOM, | 2255 | .vendor = PCI_VENDOR_ID_PERICOM, |
2253 | .device = PCI_ANY_ID, | 2256 | .device = PCI_ANY_ID, |
2254 | .subvendor = PCI_ANY_ID, | 2257 | .subvendor = PCI_ANY_ID, |
2255 | .subdevice = PCI_ANY_ID, | 2258 | .subdevice = PCI_ANY_ID, |
2256 | .setup = pci_pericom_setup, | 2259 | .setup = pci_pericom_setup, |
2257 | }, | 2260 | }, |
2258 | /* | 2261 | /* |
2259 | * PLX | 2262 | * PLX |
2260 | */ | 2263 | */ |
2261 | { | 2264 | { |
2262 | .vendor = PCI_VENDOR_ID_PLX, | 2265 | .vendor = PCI_VENDOR_ID_PLX, |
2263 | .device = PCI_DEVICE_ID_PLX_9050, | 2266 | .device = PCI_DEVICE_ID_PLX_9050, |
2264 | .subvendor = PCI_SUBVENDOR_ID_EXSYS, | 2267 | .subvendor = PCI_SUBVENDOR_ID_EXSYS, |
2265 | .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, | 2268 | .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, |
2266 | .init = pci_plx9050_init, | 2269 | .init = pci_plx9050_init, |
2267 | .setup = pci_default_setup, | 2270 | .setup = pci_default_setup, |
2268 | .exit = pci_plx9050_exit, | 2271 | .exit = pci_plx9050_exit, |
2269 | }, | 2272 | }, |
2270 | { | 2273 | { |
2271 | .vendor = PCI_VENDOR_ID_PLX, | 2274 | .vendor = PCI_VENDOR_ID_PLX, |
2272 | .device = PCI_DEVICE_ID_PLX_9050, | 2275 | .device = PCI_DEVICE_ID_PLX_9050, |
2273 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, | 2276 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, |
2274 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, | 2277 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, |
2275 | .init = pci_plx9050_init, | 2278 | .init = pci_plx9050_init, |
2276 | .setup = pci_default_setup, | 2279 | .setup = pci_default_setup, |
2277 | .exit = pci_plx9050_exit, | 2280 | .exit = pci_plx9050_exit, |
2278 | }, | 2281 | }, |
2279 | { | 2282 | { |
2280 | .vendor = PCI_VENDOR_ID_PLX, | 2283 | .vendor = PCI_VENDOR_ID_PLX, |
2281 | .device = PCI_DEVICE_ID_PLX_ROMULUS, | 2284 | .device = PCI_DEVICE_ID_PLX_ROMULUS, |
2282 | .subvendor = PCI_VENDOR_ID_PLX, | 2285 | .subvendor = PCI_VENDOR_ID_PLX, |
2283 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, | 2286 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, |
2284 | .init = pci_plx9050_init, | 2287 | .init = pci_plx9050_init, |
2285 | .setup = pci_default_setup, | 2288 | .setup = pci_default_setup, |
2286 | .exit = pci_plx9050_exit, | 2289 | .exit = pci_plx9050_exit, |
2287 | }, | 2290 | }, |
2288 | /* | 2291 | /* |
2289 | * SBS Technologies, Inc., PMC-OCTALPRO 232 | 2292 | * SBS Technologies, Inc., PMC-OCTALPRO 232 |
2290 | */ | 2293 | */ |
2291 | { | 2294 | { |
2292 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | 2295 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
2293 | .device = PCI_DEVICE_ID_OCTPRO, | 2296 | .device = PCI_DEVICE_ID_OCTPRO, |
2294 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | 2297 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
2295 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, | 2298 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, |
2296 | .init = sbs_init, | 2299 | .init = sbs_init, |
2297 | .setup = sbs_setup, | 2300 | .setup = sbs_setup, |
2298 | .exit = sbs_exit, | 2301 | .exit = sbs_exit, |
2299 | }, | 2302 | }, |
2300 | /* | 2303 | /* |
2301 | * SBS Technologies, Inc., PMC-OCTALPRO 422 | 2304 | * SBS Technologies, Inc., PMC-OCTALPRO 422 |
2302 | */ | 2305 | */ |
2303 | { | 2306 | { |
2304 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | 2307 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
2305 | .device = PCI_DEVICE_ID_OCTPRO, | 2308 | .device = PCI_DEVICE_ID_OCTPRO, |
2306 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | 2309 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
2307 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, | 2310 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, |
2308 | .init = sbs_init, | 2311 | .init = sbs_init, |
2309 | .setup = sbs_setup, | 2312 | .setup = sbs_setup, |
2310 | .exit = sbs_exit, | 2313 | .exit = sbs_exit, |
2311 | }, | 2314 | }, |
2312 | /* | 2315 | /* |
2313 | * SBS Technologies, Inc., P-Octal 232 | 2316 | * SBS Technologies, Inc., P-Octal 232 |
2314 | */ | 2317 | */ |
2315 | { | 2318 | { |
2316 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | 2319 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
2317 | .device = PCI_DEVICE_ID_OCTPRO, | 2320 | .device = PCI_DEVICE_ID_OCTPRO, |
2318 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | 2321 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
2319 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, | 2322 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, |
2320 | .init = sbs_init, | 2323 | .init = sbs_init, |
2321 | .setup = sbs_setup, | 2324 | .setup = sbs_setup, |
2322 | .exit = sbs_exit, | 2325 | .exit = sbs_exit, |
2323 | }, | 2326 | }, |
2324 | /* | 2327 | /* |
2325 | * SBS Technologies, Inc., P-Octal 422 | 2328 | * SBS Technologies, Inc., P-Octal 422 |
2326 | */ | 2329 | */ |
2327 | { | 2330 | { |
2328 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | 2331 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
2329 | .device = PCI_DEVICE_ID_OCTPRO, | 2332 | .device = PCI_DEVICE_ID_OCTPRO, |
2330 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | 2333 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
2331 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, | 2334 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, |
2332 | .init = sbs_init, | 2335 | .init = sbs_init, |
2333 | .setup = sbs_setup, | 2336 | .setup = sbs_setup, |
2334 | .exit = sbs_exit, | 2337 | .exit = sbs_exit, |
2335 | }, | 2338 | }, |
2336 | /* | 2339 | /* |
2337 | * SIIG cards - these may be called via parport_serial | 2340 | * SIIG cards - these may be called via parport_serial |
2338 | */ | 2341 | */ |
2339 | { | 2342 | { |
2340 | .vendor = PCI_VENDOR_ID_SIIG, | 2343 | .vendor = PCI_VENDOR_ID_SIIG, |
2341 | .device = PCI_ANY_ID, | 2344 | .device = PCI_ANY_ID, |
2342 | .subvendor = PCI_ANY_ID, | 2345 | .subvendor = PCI_ANY_ID, |
2343 | .subdevice = PCI_ANY_ID, | 2346 | .subdevice = PCI_ANY_ID, |
2344 | .init = pci_siig_init, | 2347 | .init = pci_siig_init, |
2345 | .setup = pci_siig_setup, | 2348 | .setup = pci_siig_setup, |
2346 | }, | 2349 | }, |
2347 | /* | 2350 | /* |
2348 | * Titan cards | 2351 | * Titan cards |
2349 | */ | 2352 | */ |
2350 | { | 2353 | { |
2351 | .vendor = PCI_VENDOR_ID_TITAN, | 2354 | .vendor = PCI_VENDOR_ID_TITAN, |
2352 | .device = PCI_DEVICE_ID_TITAN_400L, | 2355 | .device = PCI_DEVICE_ID_TITAN_400L, |
2353 | .subvendor = PCI_ANY_ID, | 2356 | .subvendor = PCI_ANY_ID, |
2354 | .subdevice = PCI_ANY_ID, | 2357 | .subdevice = PCI_ANY_ID, |
2355 | .setup = titan_400l_800l_setup, | 2358 | .setup = titan_400l_800l_setup, |
2356 | }, | 2359 | }, |
2357 | { | 2360 | { |
2358 | .vendor = PCI_VENDOR_ID_TITAN, | 2361 | .vendor = PCI_VENDOR_ID_TITAN, |
2359 | .device = PCI_DEVICE_ID_TITAN_800L, | 2362 | .device = PCI_DEVICE_ID_TITAN_800L, |
2360 | .subvendor = PCI_ANY_ID, | 2363 | .subvendor = PCI_ANY_ID, |
2361 | .subdevice = PCI_ANY_ID, | 2364 | .subdevice = PCI_ANY_ID, |
2362 | .setup = titan_400l_800l_setup, | 2365 | .setup = titan_400l_800l_setup, |
2363 | }, | 2366 | }, |
2364 | /* | 2367 | /* |
2365 | * Timedia cards | 2368 | * Timedia cards |
2366 | */ | 2369 | */ |
2367 | { | 2370 | { |
2368 | .vendor = PCI_VENDOR_ID_TIMEDIA, | 2371 | .vendor = PCI_VENDOR_ID_TIMEDIA, |
2369 | .device = PCI_DEVICE_ID_TIMEDIA_1889, | 2372 | .device = PCI_DEVICE_ID_TIMEDIA_1889, |
2370 | .subvendor = PCI_VENDOR_ID_TIMEDIA, | 2373 | .subvendor = PCI_VENDOR_ID_TIMEDIA, |
2371 | .subdevice = PCI_ANY_ID, | 2374 | .subdevice = PCI_ANY_ID, |
2372 | .probe = pci_timedia_probe, | 2375 | .probe = pci_timedia_probe, |
2373 | .init = pci_timedia_init, | 2376 | .init = pci_timedia_init, |
2374 | .setup = pci_timedia_setup, | 2377 | .setup = pci_timedia_setup, |
2375 | }, | 2378 | }, |
2376 | { | 2379 | { |
2377 | .vendor = PCI_VENDOR_ID_TIMEDIA, | 2380 | .vendor = PCI_VENDOR_ID_TIMEDIA, |
2378 | .device = PCI_ANY_ID, | 2381 | .device = PCI_ANY_ID, |
2379 | .subvendor = PCI_ANY_ID, | 2382 | .subvendor = PCI_ANY_ID, |
2380 | .subdevice = PCI_ANY_ID, | 2383 | .subdevice = PCI_ANY_ID, |
2381 | .setup = pci_timedia_setup, | 2384 | .setup = pci_timedia_setup, |
2382 | }, | 2385 | }, |
2383 | /* | 2386 | /* |
2384 | * SUNIX (Timedia) cards | 2387 | * SUNIX (Timedia) cards |
2385 | * Do not "probe" for these cards as there is at least one combination | 2388 | * Do not "probe" for these cards as there is at least one combination |
2386 | * card that should be handled by parport_pc that doesn't match the | 2389 | * card that should be handled by parport_pc that doesn't match the |
2387 | * rule in pci_timedia_probe. | 2390 | * rule in pci_timedia_probe. |
2388 | * It is part number is MIO5079A but its subdevice ID is 0x0102. | 2391 | * It is part number is MIO5079A but its subdevice ID is 0x0102. |
2389 | * There are some boards with part number SER5037AL that report | 2392 | * There are some boards with part number SER5037AL that report |
2390 | * subdevice ID 0x0002. | 2393 | * subdevice ID 0x0002. |
2391 | */ | 2394 | */ |
2392 | { | 2395 | { |
2393 | .vendor = PCI_VENDOR_ID_SUNIX, | 2396 | .vendor = PCI_VENDOR_ID_SUNIX, |
2394 | .device = PCI_DEVICE_ID_SUNIX_1999, | 2397 | .device = PCI_DEVICE_ID_SUNIX_1999, |
2395 | .subvendor = PCI_VENDOR_ID_SUNIX, | 2398 | .subvendor = PCI_VENDOR_ID_SUNIX, |
2396 | .subdevice = PCI_ANY_ID, | 2399 | .subdevice = PCI_ANY_ID, |
2397 | .init = pci_timedia_init, | 2400 | .init = pci_timedia_init, |
2398 | .setup = pci_timedia_setup, | 2401 | .setup = pci_timedia_setup, |
2399 | }, | 2402 | }, |
2400 | /* | 2403 | /* |
2401 | * Exar cards | 2404 | * Exar cards |
2402 | */ | 2405 | */ |
2403 | { | 2406 | { |
2404 | .vendor = PCI_VENDOR_ID_EXAR, | 2407 | .vendor = PCI_VENDOR_ID_EXAR, |
2405 | .device = PCI_DEVICE_ID_EXAR_XR17C152, | 2408 | .device = PCI_DEVICE_ID_EXAR_XR17C152, |
2406 | .subvendor = PCI_ANY_ID, | 2409 | .subvendor = PCI_ANY_ID, |
2407 | .subdevice = PCI_ANY_ID, | 2410 | .subdevice = PCI_ANY_ID, |
2408 | .setup = pci_xr17c154_setup, | 2411 | .setup = pci_xr17c154_setup, |
2409 | }, | 2412 | }, |
2410 | { | 2413 | { |
2411 | .vendor = PCI_VENDOR_ID_EXAR, | 2414 | .vendor = PCI_VENDOR_ID_EXAR, |
2412 | .device = PCI_DEVICE_ID_EXAR_XR17C154, | 2415 | .device = PCI_DEVICE_ID_EXAR_XR17C154, |
2413 | .subvendor = PCI_ANY_ID, | 2416 | .subvendor = PCI_ANY_ID, |
2414 | .subdevice = PCI_ANY_ID, | 2417 | .subdevice = PCI_ANY_ID, |
2415 | .setup = pci_xr17c154_setup, | 2418 | .setup = pci_xr17c154_setup, |
2416 | }, | 2419 | }, |
2417 | { | 2420 | { |
2418 | .vendor = PCI_VENDOR_ID_EXAR, | 2421 | .vendor = PCI_VENDOR_ID_EXAR, |
2419 | .device = PCI_DEVICE_ID_EXAR_XR17C158, | 2422 | .device = PCI_DEVICE_ID_EXAR_XR17C158, |
2420 | .subvendor = PCI_ANY_ID, | 2423 | .subvendor = PCI_ANY_ID, |
2421 | .subdevice = PCI_ANY_ID, | 2424 | .subdevice = PCI_ANY_ID, |
2422 | .setup = pci_xr17c154_setup, | 2425 | .setup = pci_xr17c154_setup, |
2423 | }, | 2426 | }, |
2424 | { | 2427 | { |
2425 | .vendor = PCI_VENDOR_ID_EXAR, | 2428 | .vendor = PCI_VENDOR_ID_EXAR, |
2426 | .device = PCI_DEVICE_ID_EXAR_XR17V352, | 2429 | .device = PCI_DEVICE_ID_EXAR_XR17V352, |
2427 | .subvendor = PCI_ANY_ID, | 2430 | .subvendor = PCI_ANY_ID, |
2428 | .subdevice = PCI_ANY_ID, | 2431 | .subdevice = PCI_ANY_ID, |
2429 | .setup = pci_xr17v35x_setup, | 2432 | .setup = pci_xr17v35x_setup, |
2430 | }, | 2433 | }, |
2431 | { | 2434 | { |
2432 | .vendor = PCI_VENDOR_ID_EXAR, | 2435 | .vendor = PCI_VENDOR_ID_EXAR, |
2433 | .device = PCI_DEVICE_ID_EXAR_XR17V354, | 2436 | .device = PCI_DEVICE_ID_EXAR_XR17V354, |
2434 | .subvendor = PCI_ANY_ID, | 2437 | .subvendor = PCI_ANY_ID, |
2435 | .subdevice = PCI_ANY_ID, | 2438 | .subdevice = PCI_ANY_ID, |
2436 | .setup = pci_xr17v35x_setup, | 2439 | .setup = pci_xr17v35x_setup, |
2437 | }, | 2440 | }, |
2438 | { | 2441 | { |
2439 | .vendor = PCI_VENDOR_ID_EXAR, | 2442 | .vendor = PCI_VENDOR_ID_EXAR, |
2440 | .device = PCI_DEVICE_ID_EXAR_XR17V358, | 2443 | .device = PCI_DEVICE_ID_EXAR_XR17V358, |
2441 | .subvendor = PCI_ANY_ID, | 2444 | .subvendor = PCI_ANY_ID, |
2442 | .subdevice = PCI_ANY_ID, | 2445 | .subdevice = PCI_ANY_ID, |
2443 | .setup = pci_xr17v35x_setup, | 2446 | .setup = pci_xr17v35x_setup, |
2444 | }, | 2447 | }, |
2445 | { | 2448 | { |
2446 | .vendor = PCI_VENDOR_ID_EXAR, | 2449 | .vendor = PCI_VENDOR_ID_EXAR, |
2447 | .device = PCI_DEVICE_ID_EXAR_XR17V4358, | 2450 | .device = PCI_DEVICE_ID_EXAR_XR17V4358, |
2448 | .subvendor = PCI_ANY_ID, | 2451 | .subvendor = PCI_ANY_ID, |
2449 | .subdevice = PCI_ANY_ID, | 2452 | .subdevice = PCI_ANY_ID, |
2450 | .setup = pci_xr17v35x_setup, | 2453 | .setup = pci_xr17v35x_setup, |
2451 | }, | 2454 | }, |
2452 | { | 2455 | { |
2453 | .vendor = PCI_VENDOR_ID_EXAR, | 2456 | .vendor = PCI_VENDOR_ID_EXAR, |
2454 | .device = PCI_DEVICE_ID_EXAR_XR17V8358, | 2457 | .device = PCI_DEVICE_ID_EXAR_XR17V8358, |
2455 | .subvendor = PCI_ANY_ID, | 2458 | .subvendor = PCI_ANY_ID, |
2456 | .subdevice = PCI_ANY_ID, | 2459 | .subdevice = PCI_ANY_ID, |
2457 | .setup = pci_xr17v35x_setup, | 2460 | .setup = pci_xr17v35x_setup, |
2458 | }, | 2461 | }, |
2459 | /* | 2462 | /* |
2460 | * Xircom cards | 2463 | * Xircom cards |
2461 | */ | 2464 | */ |
2462 | { | 2465 | { |
2463 | .vendor = PCI_VENDOR_ID_XIRCOM, | 2466 | .vendor = PCI_VENDOR_ID_XIRCOM, |
2464 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, | 2467 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, |
2465 | .subvendor = PCI_ANY_ID, | 2468 | .subvendor = PCI_ANY_ID, |
2466 | .subdevice = PCI_ANY_ID, | 2469 | .subdevice = PCI_ANY_ID, |
2467 | .init = pci_xircom_init, | 2470 | .init = pci_xircom_init, |
2468 | .setup = pci_default_setup, | 2471 | .setup = pci_default_setup, |
2469 | }, | 2472 | }, |
2470 | /* | 2473 | /* |
2471 | * Netmos cards - these may be called via parport_serial | 2474 | * Netmos cards - these may be called via parport_serial |
2472 | */ | 2475 | */ |
2473 | { | 2476 | { |
2474 | .vendor = PCI_VENDOR_ID_NETMOS, | 2477 | .vendor = PCI_VENDOR_ID_NETMOS, |
2475 | .device = PCI_ANY_ID, | 2478 | .device = PCI_ANY_ID, |
2476 | .subvendor = PCI_ANY_ID, | 2479 | .subvendor = PCI_ANY_ID, |
2477 | .subdevice = PCI_ANY_ID, | 2480 | .subdevice = PCI_ANY_ID, |
2478 | .init = pci_netmos_init, | 2481 | .init = pci_netmos_init, |
2479 | .setup = pci_netmos_9900_setup, | 2482 | .setup = pci_netmos_9900_setup, |
2480 | }, | 2483 | }, |
2481 | /* | 2484 | /* |
2482 | * EndRun Technologies | 2485 | * EndRun Technologies |
2483 | */ | 2486 | */ |
2484 | { | 2487 | { |
2485 | .vendor = PCI_VENDOR_ID_ENDRUN, | 2488 | .vendor = PCI_VENDOR_ID_ENDRUN, |
2486 | .device = PCI_ANY_ID, | 2489 | .device = PCI_ANY_ID, |
2487 | .subvendor = PCI_ANY_ID, | 2490 | .subvendor = PCI_ANY_ID, |
2488 | .subdevice = PCI_ANY_ID, | 2491 | .subdevice = PCI_ANY_ID, |
2489 | .init = pci_endrun_init, | 2492 | .init = pci_endrun_init, |
2490 | .setup = pci_default_setup, | 2493 | .setup = pci_default_setup, |
2491 | }, | 2494 | }, |
2492 | /* | 2495 | /* |
2493 | * For Oxford Semiconductor Tornado based devices | 2496 | * For Oxford Semiconductor Tornado based devices |
2494 | */ | 2497 | */ |
2495 | { | 2498 | { |
2496 | .vendor = PCI_VENDOR_ID_OXSEMI, | 2499 | .vendor = PCI_VENDOR_ID_OXSEMI, |
2497 | .device = PCI_ANY_ID, | 2500 | .device = PCI_ANY_ID, |
2498 | .subvendor = PCI_ANY_ID, | 2501 | .subvendor = PCI_ANY_ID, |
2499 | .subdevice = PCI_ANY_ID, | 2502 | .subdevice = PCI_ANY_ID, |
2500 | .init = pci_oxsemi_tornado_init, | 2503 | .init = pci_oxsemi_tornado_init, |
2501 | .setup = pci_default_setup, | 2504 | .setup = pci_default_setup, |
2502 | }, | 2505 | }, |
2503 | { | 2506 | { |
2504 | .vendor = PCI_VENDOR_ID_MAINPINE, | 2507 | .vendor = PCI_VENDOR_ID_MAINPINE, |
2505 | .device = PCI_ANY_ID, | 2508 | .device = PCI_ANY_ID, |
2506 | .subvendor = PCI_ANY_ID, | 2509 | .subvendor = PCI_ANY_ID, |
2507 | .subdevice = PCI_ANY_ID, | 2510 | .subdevice = PCI_ANY_ID, |
2508 | .init = pci_oxsemi_tornado_init, | 2511 | .init = pci_oxsemi_tornado_init, |
2509 | .setup = pci_default_setup, | 2512 | .setup = pci_default_setup, |
2510 | }, | 2513 | }, |
2511 | { | 2514 | { |
2512 | .vendor = PCI_VENDOR_ID_DIGI, | 2515 | .vendor = PCI_VENDOR_ID_DIGI, |
2513 | .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, | 2516 | .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, |
2514 | .subvendor = PCI_SUBVENDOR_ID_IBM, | 2517 | .subvendor = PCI_SUBVENDOR_ID_IBM, |
2515 | .subdevice = PCI_ANY_ID, | 2518 | .subdevice = PCI_ANY_ID, |
2516 | .init = pci_oxsemi_tornado_init, | 2519 | .init = pci_oxsemi_tornado_init, |
2517 | .setup = pci_default_setup, | 2520 | .setup = pci_default_setup, |
2518 | }, | 2521 | }, |
2519 | { | 2522 | { |
2520 | .vendor = PCI_VENDOR_ID_INTEL, | 2523 | .vendor = PCI_VENDOR_ID_INTEL, |
2521 | .device = 0x8811, | 2524 | .device = 0x8811, |
2522 | .subvendor = PCI_ANY_ID, | 2525 | .subvendor = PCI_ANY_ID, |
2523 | .subdevice = PCI_ANY_ID, | 2526 | .subdevice = PCI_ANY_ID, |
2524 | .init = pci_eg20t_init, | 2527 | .init = pci_eg20t_init, |
2525 | .setup = pci_default_setup, | 2528 | .setup = pci_default_setup, |
2526 | }, | 2529 | }, |
2527 | { | 2530 | { |
2528 | .vendor = PCI_VENDOR_ID_INTEL, | 2531 | .vendor = PCI_VENDOR_ID_INTEL, |
2529 | .device = 0x8812, | 2532 | .device = 0x8812, |
2530 | .subvendor = PCI_ANY_ID, | 2533 | .subvendor = PCI_ANY_ID, |
2531 | .subdevice = PCI_ANY_ID, | 2534 | .subdevice = PCI_ANY_ID, |
2532 | .init = pci_eg20t_init, | 2535 | .init = pci_eg20t_init, |
2533 | .setup = pci_default_setup, | 2536 | .setup = pci_default_setup, |
2534 | }, | 2537 | }, |
2535 | { | 2538 | { |
2536 | .vendor = PCI_VENDOR_ID_INTEL, | 2539 | .vendor = PCI_VENDOR_ID_INTEL, |
2537 | .device = 0x8813, | 2540 | .device = 0x8813, |
2538 | .subvendor = PCI_ANY_ID, | 2541 | .subvendor = PCI_ANY_ID, |
2539 | .subdevice = PCI_ANY_ID, | 2542 | .subdevice = PCI_ANY_ID, |
2540 | .init = pci_eg20t_init, | 2543 | .init = pci_eg20t_init, |
2541 | .setup = pci_default_setup, | 2544 | .setup = pci_default_setup, |
2542 | }, | 2545 | }, |
2543 | { | 2546 | { |
2544 | .vendor = PCI_VENDOR_ID_INTEL, | 2547 | .vendor = PCI_VENDOR_ID_INTEL, |
2545 | .device = 0x8814, | 2548 | .device = 0x8814, |
2546 | .subvendor = PCI_ANY_ID, | 2549 | .subvendor = PCI_ANY_ID, |
2547 | .subdevice = PCI_ANY_ID, | 2550 | .subdevice = PCI_ANY_ID, |
2548 | .init = pci_eg20t_init, | 2551 | .init = pci_eg20t_init, |
2549 | .setup = pci_default_setup, | 2552 | .setup = pci_default_setup, |
2550 | }, | 2553 | }, |
2551 | { | 2554 | { |
2552 | .vendor = 0x10DB, | 2555 | .vendor = 0x10DB, |
2553 | .device = 0x8027, | 2556 | .device = 0x8027, |
2554 | .subvendor = PCI_ANY_ID, | 2557 | .subvendor = PCI_ANY_ID, |
2555 | .subdevice = PCI_ANY_ID, | 2558 | .subdevice = PCI_ANY_ID, |
2556 | .init = pci_eg20t_init, | 2559 | .init = pci_eg20t_init, |
2557 | .setup = pci_default_setup, | 2560 | .setup = pci_default_setup, |
2558 | }, | 2561 | }, |
2559 | { | 2562 | { |
2560 | .vendor = 0x10DB, | 2563 | .vendor = 0x10DB, |
2561 | .device = 0x8028, | 2564 | .device = 0x8028, |
2562 | .subvendor = PCI_ANY_ID, | 2565 | .subvendor = PCI_ANY_ID, |
2563 | .subdevice = PCI_ANY_ID, | 2566 | .subdevice = PCI_ANY_ID, |
2564 | .init = pci_eg20t_init, | 2567 | .init = pci_eg20t_init, |
2565 | .setup = pci_default_setup, | 2568 | .setup = pci_default_setup, |
2566 | }, | 2569 | }, |
2567 | { | 2570 | { |
2568 | .vendor = 0x10DB, | 2571 | .vendor = 0x10DB, |
2569 | .device = 0x8029, | 2572 | .device = 0x8029, |
2570 | .subvendor = PCI_ANY_ID, | 2573 | .subvendor = PCI_ANY_ID, |
2571 | .subdevice = PCI_ANY_ID, | 2574 | .subdevice = PCI_ANY_ID, |
2572 | .init = pci_eg20t_init, | 2575 | .init = pci_eg20t_init, |
2573 | .setup = pci_default_setup, | 2576 | .setup = pci_default_setup, |
2574 | }, | 2577 | }, |
2575 | { | 2578 | { |
2576 | .vendor = 0x10DB, | 2579 | .vendor = 0x10DB, |
2577 | .device = 0x800C, | 2580 | .device = 0x800C, |
2578 | .subvendor = PCI_ANY_ID, | 2581 | .subvendor = PCI_ANY_ID, |
2579 | .subdevice = PCI_ANY_ID, | 2582 | .subdevice = PCI_ANY_ID, |
2580 | .init = pci_eg20t_init, | 2583 | .init = pci_eg20t_init, |
2581 | .setup = pci_default_setup, | 2584 | .setup = pci_default_setup, |
2582 | }, | 2585 | }, |
2583 | { | 2586 | { |
2584 | .vendor = 0x10DB, | 2587 | .vendor = 0x10DB, |
2585 | .device = 0x800D, | 2588 | .device = 0x800D, |
2586 | .subvendor = PCI_ANY_ID, | 2589 | .subvendor = PCI_ANY_ID, |
2587 | .subdevice = PCI_ANY_ID, | 2590 | .subdevice = PCI_ANY_ID, |
2588 | .init = pci_eg20t_init, | 2591 | .init = pci_eg20t_init, |
2589 | .setup = pci_default_setup, | 2592 | .setup = pci_default_setup, |
2590 | }, | 2593 | }, |
2591 | /* | 2594 | /* |
2592 | * Cronyx Omega PCI (PLX-chip based) | 2595 | * Cronyx Omega PCI (PLX-chip based) |
2593 | */ | 2596 | */ |
2594 | { | 2597 | { |
2595 | .vendor = PCI_VENDOR_ID_PLX, | 2598 | .vendor = PCI_VENDOR_ID_PLX, |
2596 | .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, | 2599 | .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, |
2597 | .subvendor = PCI_ANY_ID, | 2600 | .subvendor = PCI_ANY_ID, |
2598 | .subdevice = PCI_ANY_ID, | 2601 | .subdevice = PCI_ANY_ID, |
2599 | .setup = pci_omegapci_setup, | 2602 | .setup = pci_omegapci_setup, |
2600 | }, | 2603 | }, |
2601 | /* WCH CH353 1S1P card (16550 clone) */ | 2604 | /* WCH CH353 1S1P card (16550 clone) */ |
2602 | { | 2605 | { |
2603 | .vendor = PCI_VENDOR_ID_WCH, | 2606 | .vendor = PCI_VENDOR_ID_WCH, |
2604 | .device = PCI_DEVICE_ID_WCH_CH353_1S1P, | 2607 | .device = PCI_DEVICE_ID_WCH_CH353_1S1P, |
2605 | .subvendor = PCI_ANY_ID, | 2608 | .subvendor = PCI_ANY_ID, |
2606 | .subdevice = PCI_ANY_ID, | 2609 | .subdevice = PCI_ANY_ID, |
2607 | .setup = pci_wch_ch353_setup, | 2610 | .setup = pci_wch_ch353_setup, |
2608 | }, | 2611 | }, |
2609 | /* WCH CH353 2S1P card (16550 clone) */ | 2612 | /* WCH CH353 2S1P card (16550 clone) */ |
2610 | { | 2613 | { |
2611 | .vendor = PCI_VENDOR_ID_WCH, | 2614 | .vendor = PCI_VENDOR_ID_WCH, |
2612 | .device = PCI_DEVICE_ID_WCH_CH353_2S1P, | 2615 | .device = PCI_DEVICE_ID_WCH_CH353_2S1P, |
2613 | .subvendor = PCI_ANY_ID, | 2616 | .subvendor = PCI_ANY_ID, |
2614 | .subdevice = PCI_ANY_ID, | 2617 | .subdevice = PCI_ANY_ID, |
2615 | .setup = pci_wch_ch353_setup, | 2618 | .setup = pci_wch_ch353_setup, |
2616 | }, | 2619 | }, |
2617 | /* WCH CH353 4S card (16550 clone) */ | 2620 | /* WCH CH353 4S card (16550 clone) */ |
2618 | { | 2621 | { |
2619 | .vendor = PCI_VENDOR_ID_WCH, | 2622 | .vendor = PCI_VENDOR_ID_WCH, |
2620 | .device = PCI_DEVICE_ID_WCH_CH353_4S, | 2623 | .device = PCI_DEVICE_ID_WCH_CH353_4S, |
2621 | .subvendor = PCI_ANY_ID, | 2624 | .subvendor = PCI_ANY_ID, |
2622 | .subdevice = PCI_ANY_ID, | 2625 | .subdevice = PCI_ANY_ID, |
2623 | .setup = pci_wch_ch353_setup, | 2626 | .setup = pci_wch_ch353_setup, |
2624 | }, | 2627 | }, |
2625 | /* WCH CH353 2S1PF card (16550 clone) */ | 2628 | /* WCH CH353 2S1PF card (16550 clone) */ |
2626 | { | 2629 | { |
2627 | .vendor = PCI_VENDOR_ID_WCH, | 2630 | .vendor = PCI_VENDOR_ID_WCH, |
2628 | .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, | 2631 | .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, |
2629 | .subvendor = PCI_ANY_ID, | 2632 | .subvendor = PCI_ANY_ID, |
2630 | .subdevice = PCI_ANY_ID, | 2633 | .subdevice = PCI_ANY_ID, |
2631 | .setup = pci_wch_ch353_setup, | 2634 | .setup = pci_wch_ch353_setup, |
2632 | }, | 2635 | }, |
2633 | /* WCH CH352 2S card (16550 clone) */ | 2636 | /* WCH CH352 2S card (16550 clone) */ |
2634 | { | 2637 | { |
2635 | .vendor = PCI_VENDOR_ID_WCH, | 2638 | .vendor = PCI_VENDOR_ID_WCH, |
2636 | .device = PCI_DEVICE_ID_WCH_CH352_2S, | 2639 | .device = PCI_DEVICE_ID_WCH_CH352_2S, |
2637 | .subvendor = PCI_ANY_ID, | 2640 | .subvendor = PCI_ANY_ID, |
2638 | .subdevice = PCI_ANY_ID, | 2641 | .subdevice = PCI_ANY_ID, |
2639 | .setup = pci_wch_ch353_setup, | 2642 | .setup = pci_wch_ch353_setup, |
2640 | }, | 2643 | }, |
2641 | /* WCH CH382 2S card (16850 clone) */ | 2644 | /* WCH CH382 2S card (16850 clone) */ |
2642 | { | 2645 | { |
2643 | .vendor = PCIE_VENDOR_ID_WCH, | 2646 | .vendor = PCIE_VENDOR_ID_WCH, |
2644 | .device = PCIE_DEVICE_ID_WCH_CH382_2S, | 2647 | .device = PCIE_DEVICE_ID_WCH_CH382_2S, |
2645 | .subvendor = PCI_ANY_ID, | 2648 | .subvendor = PCI_ANY_ID, |
2646 | .subdevice = PCI_ANY_ID, | 2649 | .subdevice = PCI_ANY_ID, |
2647 | .setup = pci_wch_ch38x_setup, | 2650 | .setup = pci_wch_ch38x_setup, |
2648 | }, | 2651 | }, |
2649 | /* WCH CH382 2S1P card (16850 clone) */ | 2652 | /* WCH CH382 2S1P card (16850 clone) */ |
2650 | { | 2653 | { |
2651 | .vendor = PCIE_VENDOR_ID_WCH, | 2654 | .vendor = PCIE_VENDOR_ID_WCH, |
2652 | .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, | 2655 | .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, |
2653 | .subvendor = PCI_ANY_ID, | 2656 | .subvendor = PCI_ANY_ID, |
2654 | .subdevice = PCI_ANY_ID, | 2657 | .subdevice = PCI_ANY_ID, |
2655 | .setup = pci_wch_ch38x_setup, | 2658 | .setup = pci_wch_ch38x_setup, |
2656 | }, | 2659 | }, |
2657 | /* WCH CH384 4S card (16850 clone) */ | 2660 | /* WCH CH384 4S card (16850 clone) */ |
2658 | { | 2661 | { |
2659 | .vendor = PCIE_VENDOR_ID_WCH, | 2662 | .vendor = PCIE_VENDOR_ID_WCH, |
2660 | .device = PCIE_DEVICE_ID_WCH_CH384_4S, | 2663 | .device = PCIE_DEVICE_ID_WCH_CH384_4S, |
2661 | .subvendor = PCI_ANY_ID, | 2664 | .subvendor = PCI_ANY_ID, |
2662 | .subdevice = PCI_ANY_ID, | 2665 | .subdevice = PCI_ANY_ID, |
2663 | .setup = pci_wch_ch38x_setup, | 2666 | .setup = pci_wch_ch38x_setup, |
2664 | }, | 2667 | }, |
2665 | /* | 2668 | /* |
2666 | * ASIX devices with FIFO bug | 2669 | * ASIX devices with FIFO bug |
2667 | */ | 2670 | */ |
2668 | { | 2671 | { |
2669 | .vendor = PCI_VENDOR_ID_ASIX, | 2672 | .vendor = PCI_VENDOR_ID_ASIX, |
2670 | .device = PCI_ANY_ID, | 2673 | .device = PCI_ANY_ID, |
2671 | .subvendor = PCI_ANY_ID, | 2674 | .subvendor = PCI_ANY_ID, |
2672 | .subdevice = PCI_ANY_ID, | 2675 | .subdevice = PCI_ANY_ID, |
2673 | .setup = pci_asix_setup, | 2676 | .setup = pci_asix_setup, |
2674 | }, | 2677 | }, |
2675 | /* | 2678 | /* |
2676 | * Commtech, Inc. Fastcom adapters | 2679 | * Commtech, Inc. Fastcom adapters |
2677 | * | 2680 | * |
2678 | */ | 2681 | */ |
2679 | { | 2682 | { |
2680 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2683 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2681 | .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, | 2684 | .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, |
2682 | .subvendor = PCI_ANY_ID, | 2685 | .subvendor = PCI_ANY_ID, |
2683 | .subdevice = PCI_ANY_ID, | 2686 | .subdevice = PCI_ANY_ID, |
2684 | .setup = pci_fastcom335_setup, | 2687 | .setup = pci_fastcom335_setup, |
2685 | }, | 2688 | }, |
2686 | { | 2689 | { |
2687 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2690 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2688 | .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, | 2691 | .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, |
2689 | .subvendor = PCI_ANY_ID, | 2692 | .subvendor = PCI_ANY_ID, |
2690 | .subdevice = PCI_ANY_ID, | 2693 | .subdevice = PCI_ANY_ID, |
2691 | .setup = pci_fastcom335_setup, | 2694 | .setup = pci_fastcom335_setup, |
2692 | }, | 2695 | }, |
2693 | { | 2696 | { |
2694 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2697 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2695 | .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, | 2698 | .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, |
2696 | .subvendor = PCI_ANY_ID, | 2699 | .subvendor = PCI_ANY_ID, |
2697 | .subdevice = PCI_ANY_ID, | 2700 | .subdevice = PCI_ANY_ID, |
2698 | .setup = pci_fastcom335_setup, | 2701 | .setup = pci_fastcom335_setup, |
2699 | }, | 2702 | }, |
2700 | { | 2703 | { |
2701 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2704 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2702 | .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, | 2705 | .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, |
2703 | .subvendor = PCI_ANY_ID, | 2706 | .subvendor = PCI_ANY_ID, |
2704 | .subdevice = PCI_ANY_ID, | 2707 | .subdevice = PCI_ANY_ID, |
2705 | .setup = pci_fastcom335_setup, | 2708 | .setup = pci_fastcom335_setup, |
2706 | }, | 2709 | }, |
2707 | { | 2710 | { |
2708 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2711 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2709 | .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, | 2712 | .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, |
2710 | .subvendor = PCI_ANY_ID, | 2713 | .subvendor = PCI_ANY_ID, |
2711 | .subdevice = PCI_ANY_ID, | 2714 | .subdevice = PCI_ANY_ID, |
2712 | .setup = pci_xr17v35x_setup, | 2715 | .setup = pci_xr17v35x_setup, |
2713 | }, | 2716 | }, |
2714 | { | 2717 | { |
2715 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2718 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2716 | .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, | 2719 | .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, |
2717 | .subvendor = PCI_ANY_ID, | 2720 | .subvendor = PCI_ANY_ID, |
2718 | .subdevice = PCI_ANY_ID, | 2721 | .subdevice = PCI_ANY_ID, |
2719 | .setup = pci_xr17v35x_setup, | 2722 | .setup = pci_xr17v35x_setup, |
2720 | }, | 2723 | }, |
2721 | { | 2724 | { |
2722 | .vendor = PCI_VENDOR_ID_COMMTECH, | 2725 | .vendor = PCI_VENDOR_ID_COMMTECH, |
2723 | .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, | 2726 | .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, |
2724 | .subvendor = PCI_ANY_ID, | 2727 | .subvendor = PCI_ANY_ID, |
2725 | .subdevice = PCI_ANY_ID, | 2728 | .subdevice = PCI_ANY_ID, |
2726 | .setup = pci_xr17v35x_setup, | 2729 | .setup = pci_xr17v35x_setup, |
2727 | }, | 2730 | }, |
2728 | /* | 2731 | /* |
2729 | * Broadcom TruManage (NetXtreme) | 2732 | * Broadcom TruManage (NetXtreme) |
2730 | */ | 2733 | */ |
2731 | { | 2734 | { |
2732 | .vendor = PCI_VENDOR_ID_BROADCOM, | 2735 | .vendor = PCI_VENDOR_ID_BROADCOM, |
2733 | .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, | 2736 | .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, |
2734 | .subvendor = PCI_ANY_ID, | 2737 | .subvendor = PCI_ANY_ID, |
2735 | .subdevice = PCI_ANY_ID, | 2738 | .subdevice = PCI_ANY_ID, |
2736 | .setup = pci_brcm_trumanage_setup, | 2739 | .setup = pci_brcm_trumanage_setup, |
2737 | }, | 2740 | }, |
2738 | { | 2741 | { |
2739 | .vendor = 0x1c29, | 2742 | .vendor = 0x1c29, |
2740 | .device = 0x1104, | 2743 | .device = 0x1104, |
2741 | .subvendor = PCI_ANY_ID, | 2744 | .subvendor = PCI_ANY_ID, |
2742 | .subdevice = PCI_ANY_ID, | 2745 | .subdevice = PCI_ANY_ID, |
2743 | .setup = pci_fintek_setup, | 2746 | .setup = pci_fintek_setup, |
2744 | .init = pci_fintek_init, | 2747 | .init = pci_fintek_init, |
2745 | }, | 2748 | }, |
2746 | { | 2749 | { |
2747 | .vendor = 0x1c29, | 2750 | .vendor = 0x1c29, |
2748 | .device = 0x1108, | 2751 | .device = 0x1108, |
2749 | .subvendor = PCI_ANY_ID, | 2752 | .subvendor = PCI_ANY_ID, |
2750 | .subdevice = PCI_ANY_ID, | 2753 | .subdevice = PCI_ANY_ID, |
2751 | .setup = pci_fintek_setup, | 2754 | .setup = pci_fintek_setup, |
2752 | .init = pci_fintek_init, | 2755 | .init = pci_fintek_init, |
2753 | }, | 2756 | }, |
2754 | { | 2757 | { |
2755 | .vendor = 0x1c29, | 2758 | .vendor = 0x1c29, |
2756 | .device = 0x1112, | 2759 | .device = 0x1112, |
2757 | .subvendor = PCI_ANY_ID, | 2760 | .subvendor = PCI_ANY_ID, |
2758 | .subdevice = PCI_ANY_ID, | 2761 | .subdevice = PCI_ANY_ID, |
2759 | .setup = pci_fintek_setup, | 2762 | .setup = pci_fintek_setup, |
2760 | .init = pci_fintek_init, | 2763 | .init = pci_fintek_init, |
2761 | }, | 2764 | }, |
2762 | 2765 | ||
2763 | /* | 2766 | /* |
2764 | * Default "match everything" terminator entry | 2767 | * Default "match everything" terminator entry |
2765 | */ | 2768 | */ |
2766 | { | 2769 | { |
2767 | .vendor = PCI_ANY_ID, | 2770 | .vendor = PCI_ANY_ID, |
2768 | .device = PCI_ANY_ID, | 2771 | .device = PCI_ANY_ID, |
2769 | .subvendor = PCI_ANY_ID, | 2772 | .subvendor = PCI_ANY_ID, |
2770 | .subdevice = PCI_ANY_ID, | 2773 | .subdevice = PCI_ANY_ID, |
2771 | .setup = pci_default_setup, | 2774 | .setup = pci_default_setup, |
2772 | } | 2775 | } |
2773 | }; | 2776 | }; |
2774 | 2777 | ||
2775 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) | 2778 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) |
2776 | { | 2779 | { |
2777 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; | 2780 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; |
2778 | } | 2781 | } |
2779 | 2782 | ||
2780 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) | 2783 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) |
2781 | { | 2784 | { |
2782 | struct pci_serial_quirk *quirk; | 2785 | struct pci_serial_quirk *quirk; |
2783 | 2786 | ||
2784 | for (quirk = pci_serial_quirks; ; quirk++) | 2787 | for (quirk = pci_serial_quirks; ; quirk++) |
2785 | if (quirk_id_matches(quirk->vendor, dev->vendor) && | 2788 | if (quirk_id_matches(quirk->vendor, dev->vendor) && |
2786 | quirk_id_matches(quirk->device, dev->device) && | 2789 | quirk_id_matches(quirk->device, dev->device) && |
2787 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && | 2790 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && |
2788 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) | 2791 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) |
2789 | break; | 2792 | break; |
2790 | return quirk; | 2793 | return quirk; |
2791 | } | 2794 | } |
2792 | 2795 | ||
2793 | static inline int get_pci_irq(struct pci_dev *dev, | 2796 | static inline int get_pci_irq(struct pci_dev *dev, |
2794 | const struct pciserial_board *board) | 2797 | const struct pciserial_board *board) |
2795 | { | 2798 | { |
2796 | if (board->flags & FL_NOIRQ) | 2799 | if (board->flags & FL_NOIRQ) |
2797 | return 0; | 2800 | return 0; |
2798 | else | 2801 | else |
2799 | return dev->irq; | 2802 | return dev->irq; |
2800 | } | 2803 | } |
2801 | 2804 | ||
2802 | /* | 2805 | /* |
2803 | * This is the configuration table for all of the PCI serial boards | 2806 | * This is the configuration table for all of the PCI serial boards |
2804 | * which we support. It is directly indexed by the pci_board_num_t enum | 2807 | * which we support. It is directly indexed by the pci_board_num_t enum |
2805 | * value, which is encoded in the pci_device_id PCI probe table's | 2808 | * value, which is encoded in the pci_device_id PCI probe table's |
2806 | * driver_data member. | 2809 | * driver_data member. |
2807 | * | 2810 | * |
2808 | * The makeup of these names are: | 2811 | * The makeup of these names are: |
2809 | * pbn_bn{_bt}_n_baud{_offsetinhex} | 2812 | * pbn_bn{_bt}_n_baud{_offsetinhex} |
2810 | * | 2813 | * |
2811 | * bn = PCI BAR number | 2814 | * bn = PCI BAR number |
2812 | * bt = Index using PCI BARs | 2815 | * bt = Index using PCI BARs |
2813 | * n = number of serial ports | 2816 | * n = number of serial ports |
2814 | * baud = baud rate | 2817 | * baud = baud rate |
2815 | * offsetinhex = offset for each sequential port (in hex) | 2818 | * offsetinhex = offset for each sequential port (in hex) |
2816 | * | 2819 | * |
2817 | * This table is sorted by (in order): bn, bt, baud, offsetindex, n. | 2820 | * This table is sorted by (in order): bn, bt, baud, offsetindex, n. |
2818 | * | 2821 | * |
2819 | * Please note: in theory if n = 1, _bt infix should make no difference. | 2822 | * Please note: in theory if n = 1, _bt infix should make no difference. |
2820 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 | 2823 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 |
2821 | */ | 2824 | */ |
2822 | enum pci_board_num_t { | 2825 | enum pci_board_num_t { |
2823 | pbn_default = 0, | 2826 | pbn_default = 0, |
2824 | 2827 | ||
2825 | pbn_b0_1_115200, | 2828 | pbn_b0_1_115200, |
2826 | pbn_b0_2_115200, | 2829 | pbn_b0_2_115200, |
2827 | pbn_b0_4_115200, | 2830 | pbn_b0_4_115200, |
2828 | pbn_b0_5_115200, | 2831 | pbn_b0_5_115200, |
2829 | pbn_b0_8_115200, | 2832 | pbn_b0_8_115200, |
2830 | 2833 | ||
2831 | pbn_b0_1_921600, | 2834 | pbn_b0_1_921600, |
2832 | pbn_b0_2_921600, | 2835 | pbn_b0_2_921600, |
2833 | pbn_b0_4_921600, | 2836 | pbn_b0_4_921600, |
2834 | 2837 | ||
2835 | pbn_b0_2_1130000, | 2838 | pbn_b0_2_1130000, |
2836 | 2839 | ||
2837 | pbn_b0_4_1152000, | 2840 | pbn_b0_4_1152000, |
2838 | 2841 | ||
2839 | pbn_b0_2_1152000_200, | 2842 | pbn_b0_2_1152000_200, |
2840 | pbn_b0_4_1152000_200, | 2843 | pbn_b0_4_1152000_200, |
2841 | pbn_b0_8_1152000_200, | 2844 | pbn_b0_8_1152000_200, |
2842 | 2845 | ||
2843 | pbn_b0_2_1843200, | 2846 | pbn_b0_2_1843200, |
2844 | pbn_b0_4_1843200, | 2847 | pbn_b0_4_1843200, |
2845 | 2848 | ||
2846 | pbn_b0_2_1843200_200, | 2849 | pbn_b0_2_1843200_200, |
2847 | pbn_b0_4_1843200_200, | 2850 | pbn_b0_4_1843200_200, |
2848 | pbn_b0_8_1843200_200, | 2851 | pbn_b0_8_1843200_200, |
2849 | 2852 | ||
2850 | pbn_b0_1_4000000, | 2853 | pbn_b0_1_4000000, |
2851 | 2854 | ||
2852 | pbn_b0_bt_1_115200, | 2855 | pbn_b0_bt_1_115200, |
2853 | pbn_b0_bt_2_115200, | 2856 | pbn_b0_bt_2_115200, |
2854 | pbn_b0_bt_4_115200, | 2857 | pbn_b0_bt_4_115200, |
2855 | pbn_b0_bt_8_115200, | 2858 | pbn_b0_bt_8_115200, |
2856 | 2859 | ||
2857 | pbn_b0_bt_1_460800, | 2860 | pbn_b0_bt_1_460800, |
2858 | pbn_b0_bt_2_460800, | 2861 | pbn_b0_bt_2_460800, |
2859 | pbn_b0_bt_4_460800, | 2862 | pbn_b0_bt_4_460800, |
2860 | 2863 | ||
2861 | pbn_b0_bt_1_921600, | 2864 | pbn_b0_bt_1_921600, |
2862 | pbn_b0_bt_2_921600, | 2865 | pbn_b0_bt_2_921600, |
2863 | pbn_b0_bt_4_921600, | 2866 | pbn_b0_bt_4_921600, |
2864 | pbn_b0_bt_8_921600, | 2867 | pbn_b0_bt_8_921600, |
2865 | 2868 | ||
2866 | pbn_b1_1_115200, | 2869 | pbn_b1_1_115200, |
2867 | pbn_b1_2_115200, | 2870 | pbn_b1_2_115200, |
2868 | pbn_b1_4_115200, | 2871 | pbn_b1_4_115200, |
2869 | pbn_b1_8_115200, | 2872 | pbn_b1_8_115200, |
2870 | pbn_b1_16_115200, | 2873 | pbn_b1_16_115200, |
2871 | 2874 | ||
2872 | pbn_b1_1_921600, | 2875 | pbn_b1_1_921600, |
2873 | pbn_b1_2_921600, | 2876 | pbn_b1_2_921600, |
2874 | pbn_b1_4_921600, | 2877 | pbn_b1_4_921600, |
2875 | pbn_b1_8_921600, | 2878 | pbn_b1_8_921600, |
2876 | 2879 | ||
2877 | pbn_b1_2_1250000, | 2880 | pbn_b1_2_1250000, |
2878 | 2881 | ||
2879 | pbn_b1_bt_1_115200, | 2882 | pbn_b1_bt_1_115200, |
2880 | pbn_b1_bt_2_115200, | 2883 | pbn_b1_bt_2_115200, |
2881 | pbn_b1_bt_4_115200, | 2884 | pbn_b1_bt_4_115200, |
2882 | 2885 | ||
2883 | pbn_b1_bt_2_921600, | 2886 | pbn_b1_bt_2_921600, |
2884 | 2887 | ||
2885 | pbn_b1_1_1382400, | 2888 | pbn_b1_1_1382400, |
2886 | pbn_b1_2_1382400, | 2889 | pbn_b1_2_1382400, |
2887 | pbn_b1_4_1382400, | 2890 | pbn_b1_4_1382400, |
2888 | pbn_b1_8_1382400, | 2891 | pbn_b1_8_1382400, |
2889 | 2892 | ||
2890 | pbn_b2_1_115200, | 2893 | pbn_b2_1_115200, |
2891 | pbn_b2_2_115200, | 2894 | pbn_b2_2_115200, |
2892 | pbn_b2_4_115200, | 2895 | pbn_b2_4_115200, |
2893 | pbn_b2_8_115200, | 2896 | pbn_b2_8_115200, |
2894 | 2897 | ||
2895 | pbn_b2_1_460800, | 2898 | pbn_b2_1_460800, |
2896 | pbn_b2_4_460800, | 2899 | pbn_b2_4_460800, |
2897 | pbn_b2_8_460800, | 2900 | pbn_b2_8_460800, |
2898 | pbn_b2_16_460800, | 2901 | pbn_b2_16_460800, |
2899 | 2902 | ||
2900 | pbn_b2_1_921600, | 2903 | pbn_b2_1_921600, |
2901 | pbn_b2_4_921600, | 2904 | pbn_b2_4_921600, |
2902 | pbn_b2_8_921600, | 2905 | pbn_b2_8_921600, |
2903 | 2906 | ||
2904 | pbn_b2_8_1152000, | 2907 | pbn_b2_8_1152000, |
2905 | 2908 | ||
2906 | pbn_b2_bt_1_115200, | 2909 | pbn_b2_bt_1_115200, |
2907 | pbn_b2_bt_2_115200, | 2910 | pbn_b2_bt_2_115200, |
2908 | pbn_b2_bt_4_115200, | 2911 | pbn_b2_bt_4_115200, |
2909 | 2912 | ||
2910 | pbn_b2_bt_2_921600, | 2913 | pbn_b2_bt_2_921600, |
2911 | pbn_b2_bt_4_921600, | 2914 | pbn_b2_bt_4_921600, |
2912 | 2915 | ||
2913 | pbn_b3_2_115200, | 2916 | pbn_b3_2_115200, |
2914 | pbn_b3_4_115200, | 2917 | pbn_b3_4_115200, |
2915 | pbn_b3_8_115200, | 2918 | pbn_b3_8_115200, |
2916 | 2919 | ||
2917 | pbn_b4_bt_2_921600, | 2920 | pbn_b4_bt_2_921600, |
2918 | pbn_b4_bt_4_921600, | 2921 | pbn_b4_bt_4_921600, |
2919 | pbn_b4_bt_8_921600, | 2922 | pbn_b4_bt_8_921600, |
2920 | 2923 | ||
2921 | /* | 2924 | /* |
2922 | * Board-specific versions. | 2925 | * Board-specific versions. |
2923 | */ | 2926 | */ |
2924 | pbn_panacom, | 2927 | pbn_panacom, |
2925 | pbn_panacom2, | 2928 | pbn_panacom2, |
2926 | pbn_panacom4, | 2929 | pbn_panacom4, |
2927 | pbn_plx_romulus, | 2930 | pbn_plx_romulus, |
2928 | pbn_endrun_2_4000000, | 2931 | pbn_endrun_2_4000000, |
2929 | pbn_oxsemi, | 2932 | pbn_oxsemi, |
2930 | pbn_oxsemi_1_4000000, | 2933 | pbn_oxsemi_1_4000000, |
2931 | pbn_oxsemi_2_4000000, | 2934 | pbn_oxsemi_2_4000000, |
2932 | pbn_oxsemi_4_4000000, | 2935 | pbn_oxsemi_4_4000000, |
2933 | pbn_oxsemi_8_4000000, | 2936 | pbn_oxsemi_8_4000000, |
2934 | pbn_intel_i960, | 2937 | pbn_intel_i960, |
2935 | pbn_sgi_ioc3, | 2938 | pbn_sgi_ioc3, |
2936 | pbn_computone_4, | 2939 | pbn_computone_4, |
2937 | pbn_computone_6, | 2940 | pbn_computone_6, |
2938 | pbn_computone_8, | 2941 | pbn_computone_8, |
2939 | pbn_sbsxrsio, | 2942 | pbn_sbsxrsio, |
2940 | pbn_exar_XR17C152, | 2943 | pbn_exar_XR17C152, |
2941 | pbn_exar_XR17C154, | 2944 | pbn_exar_XR17C154, |
2942 | pbn_exar_XR17C158, | 2945 | pbn_exar_XR17C158, |
2943 | pbn_exar_XR17V352, | 2946 | pbn_exar_XR17V352, |
2944 | pbn_exar_XR17V354, | 2947 | pbn_exar_XR17V354, |
2945 | pbn_exar_XR17V358, | 2948 | pbn_exar_XR17V358, |
2946 | pbn_exar_XR17V4358, | 2949 | pbn_exar_XR17V4358, |
2947 | pbn_exar_XR17V8358, | 2950 | pbn_exar_XR17V8358, |
2948 | pbn_exar_ibm_saturn, | 2951 | pbn_exar_ibm_saturn, |
2949 | pbn_pasemi_1682M, | 2952 | pbn_pasemi_1682M, |
2950 | pbn_ni8430_2, | 2953 | pbn_ni8430_2, |
2951 | pbn_ni8430_4, | 2954 | pbn_ni8430_4, |
2952 | pbn_ni8430_8, | 2955 | pbn_ni8430_8, |
2953 | pbn_ni8430_16, | 2956 | pbn_ni8430_16, |
2954 | pbn_ADDIDATA_PCIe_1_3906250, | 2957 | pbn_ADDIDATA_PCIe_1_3906250, |
2955 | pbn_ADDIDATA_PCIe_2_3906250, | 2958 | pbn_ADDIDATA_PCIe_2_3906250, |
2956 | pbn_ADDIDATA_PCIe_4_3906250, | 2959 | pbn_ADDIDATA_PCIe_4_3906250, |
2957 | pbn_ADDIDATA_PCIe_8_3906250, | 2960 | pbn_ADDIDATA_PCIe_8_3906250, |
2958 | pbn_ce4100_1_115200, | 2961 | pbn_ce4100_1_115200, |
2959 | pbn_byt, | 2962 | pbn_byt, |
2960 | pbn_qrk, | 2963 | pbn_qrk, |
2961 | pbn_omegapci, | 2964 | pbn_omegapci, |
2962 | pbn_NETMOS9900_2s_115200, | 2965 | pbn_NETMOS9900_2s_115200, |
2963 | pbn_brcm_trumanage, | 2966 | pbn_brcm_trumanage, |
2964 | pbn_fintek_4, | 2967 | pbn_fintek_4, |
2965 | pbn_fintek_8, | 2968 | pbn_fintek_8, |
2966 | pbn_fintek_12, | 2969 | pbn_fintek_12, |
2967 | pbn_wch382_2, | 2970 | pbn_wch382_2, |
2968 | pbn_wch384_4, | 2971 | pbn_wch384_4, |
2969 | pbn_pericom_PI7C9X7951, | 2972 | pbn_pericom_PI7C9X7951, |
2970 | pbn_pericom_PI7C9X7952, | 2973 | pbn_pericom_PI7C9X7952, |
2971 | pbn_pericom_PI7C9X7954, | 2974 | pbn_pericom_PI7C9X7954, |
2972 | pbn_pericom_PI7C9X7958, | 2975 | pbn_pericom_PI7C9X7958, |
2973 | }; | 2976 | }; |
2974 | 2977 | ||
2975 | /* | 2978 | /* |
2976 | * uart_offset - the space between channels | 2979 | * uart_offset - the space between channels |
2977 | * reg_shift - describes how the UART registers are mapped | 2980 | * reg_shift - describes how the UART registers are mapped |
2978 | * to PCI memory by the card. | 2981 | * to PCI memory by the card. |
2979 | * For example IER register on SBS, Inc. PMC-OctPro is located at | 2982 | * For example IER register on SBS, Inc. PMC-OctPro is located at |
2980 | * offset 0x10 from the UART base, while UART_IER is defined as 1 | 2983 | * offset 0x10 from the UART base, while UART_IER is defined as 1 |
2981 | * in include/linux/serial_reg.h, | 2984 | * in include/linux/serial_reg.h, |
2982 | * see first lines of serial_in() and serial_out() in 8250.c | 2985 | * see first lines of serial_in() and serial_out() in 8250.c |
2983 | */ | 2986 | */ |
2984 | 2987 | ||
2985 | static struct pciserial_board pci_boards[] = { | 2988 | static struct pciserial_board pci_boards[] = { |
2986 | [pbn_default] = { | 2989 | [pbn_default] = { |
2987 | .flags = FL_BASE0, | 2990 | .flags = FL_BASE0, |
2988 | .num_ports = 1, | 2991 | .num_ports = 1, |
2989 | .base_baud = 115200, | 2992 | .base_baud = 115200, |
2990 | .uart_offset = 8, | 2993 | .uart_offset = 8, |
2991 | }, | 2994 | }, |
2992 | [pbn_b0_1_115200] = { | 2995 | [pbn_b0_1_115200] = { |
2993 | .flags = FL_BASE0, | 2996 | .flags = FL_BASE0, |
2994 | .num_ports = 1, | 2997 | .num_ports = 1, |
2995 | .base_baud = 115200, | 2998 | .base_baud = 115200, |
2996 | .uart_offset = 8, | 2999 | .uart_offset = 8, |
2997 | }, | 3000 | }, |
2998 | [pbn_b0_2_115200] = { | 3001 | [pbn_b0_2_115200] = { |
2999 | .flags = FL_BASE0, | 3002 | .flags = FL_BASE0, |
3000 | .num_ports = 2, | 3003 | .num_ports = 2, |
3001 | .base_baud = 115200, | 3004 | .base_baud = 115200, |
3002 | .uart_offset = 8, | 3005 | .uart_offset = 8, |
3003 | }, | 3006 | }, |
3004 | [pbn_b0_4_115200] = { | 3007 | [pbn_b0_4_115200] = { |
3005 | .flags = FL_BASE0, | 3008 | .flags = FL_BASE0, |
3006 | .num_ports = 4, | 3009 | .num_ports = 4, |
3007 | .base_baud = 115200, | 3010 | .base_baud = 115200, |
3008 | .uart_offset = 8, | 3011 | .uart_offset = 8, |
3009 | }, | 3012 | }, |
3010 | [pbn_b0_5_115200] = { | 3013 | [pbn_b0_5_115200] = { |
3011 | .flags = FL_BASE0, | 3014 | .flags = FL_BASE0, |
3012 | .num_ports = 5, | 3015 | .num_ports = 5, |
3013 | .base_baud = 115200, | 3016 | .base_baud = 115200, |
3014 | .uart_offset = 8, | 3017 | .uart_offset = 8, |
3015 | }, | 3018 | }, |
3016 | [pbn_b0_8_115200] = { | 3019 | [pbn_b0_8_115200] = { |
3017 | .flags = FL_BASE0, | 3020 | .flags = FL_BASE0, |
3018 | .num_ports = 8, | 3021 | .num_ports = 8, |
3019 | .base_baud = 115200, | 3022 | .base_baud = 115200, |
3020 | .uart_offset = 8, | 3023 | .uart_offset = 8, |
3021 | }, | 3024 | }, |
3022 | [pbn_b0_1_921600] = { | 3025 | [pbn_b0_1_921600] = { |
3023 | .flags = FL_BASE0, | 3026 | .flags = FL_BASE0, |
3024 | .num_ports = 1, | 3027 | .num_ports = 1, |
3025 | .base_baud = 921600, | 3028 | .base_baud = 921600, |
3026 | .uart_offset = 8, | 3029 | .uart_offset = 8, |
3027 | }, | 3030 | }, |
3028 | [pbn_b0_2_921600] = { | 3031 | [pbn_b0_2_921600] = { |
3029 | .flags = FL_BASE0, | 3032 | .flags = FL_BASE0, |
3030 | .num_ports = 2, | 3033 | .num_ports = 2, |
3031 | .base_baud = 921600, | 3034 | .base_baud = 921600, |
3032 | .uart_offset = 8, | 3035 | .uart_offset = 8, |
3033 | }, | 3036 | }, |
3034 | [pbn_b0_4_921600] = { | 3037 | [pbn_b0_4_921600] = { |
3035 | .flags = FL_BASE0, | 3038 | .flags = FL_BASE0, |
3036 | .num_ports = 4, | 3039 | .num_ports = 4, |
3037 | .base_baud = 921600, | 3040 | .base_baud = 921600, |
3038 | .uart_offset = 8, | 3041 | .uart_offset = 8, |
3039 | }, | 3042 | }, |
3040 | 3043 | ||
3041 | [pbn_b0_2_1130000] = { | 3044 | [pbn_b0_2_1130000] = { |
3042 | .flags = FL_BASE0, | 3045 | .flags = FL_BASE0, |
3043 | .num_ports = 2, | 3046 | .num_ports = 2, |
3044 | .base_baud = 1130000, | 3047 | .base_baud = 1130000, |
3045 | .uart_offset = 8, | 3048 | .uart_offset = 8, |
3046 | }, | 3049 | }, |
3047 | 3050 | ||
3048 | [pbn_b0_4_1152000] = { | 3051 | [pbn_b0_4_1152000] = { |
3049 | .flags = FL_BASE0, | 3052 | .flags = FL_BASE0, |
3050 | .num_ports = 4, | 3053 | .num_ports = 4, |
3051 | .base_baud = 1152000, | 3054 | .base_baud = 1152000, |
3052 | .uart_offset = 8, | 3055 | .uart_offset = 8, |
3053 | }, | 3056 | }, |
3054 | 3057 | ||
3055 | [pbn_b0_2_1152000_200] = { | 3058 | [pbn_b0_2_1152000_200] = { |
3056 | .flags = FL_BASE0, | 3059 | .flags = FL_BASE0, |
3057 | .num_ports = 2, | 3060 | .num_ports = 2, |
3058 | .base_baud = 1152000, | 3061 | .base_baud = 1152000, |
3059 | .uart_offset = 0x200, | 3062 | .uart_offset = 0x200, |
3060 | }, | 3063 | }, |
3061 | 3064 | ||
3062 | [pbn_b0_4_1152000_200] = { | 3065 | [pbn_b0_4_1152000_200] = { |
3063 | .flags = FL_BASE0, | 3066 | .flags = FL_BASE0, |
3064 | .num_ports = 4, | 3067 | .num_ports = 4, |
3065 | .base_baud = 1152000, | 3068 | .base_baud = 1152000, |
3066 | .uart_offset = 0x200, | 3069 | .uart_offset = 0x200, |
3067 | }, | 3070 | }, |
3068 | 3071 | ||
3069 | [pbn_b0_8_1152000_200] = { | 3072 | [pbn_b0_8_1152000_200] = { |
3070 | .flags = FL_BASE0, | 3073 | .flags = FL_BASE0, |
3071 | .num_ports = 8, | 3074 | .num_ports = 8, |
3072 | .base_baud = 1152000, | 3075 | .base_baud = 1152000, |
3073 | .uart_offset = 0x200, | 3076 | .uart_offset = 0x200, |
3074 | }, | 3077 | }, |
3075 | 3078 | ||
3076 | [pbn_b0_2_1843200] = { | 3079 | [pbn_b0_2_1843200] = { |
3077 | .flags = FL_BASE0, | 3080 | .flags = FL_BASE0, |
3078 | .num_ports = 2, | 3081 | .num_ports = 2, |
3079 | .base_baud = 1843200, | 3082 | .base_baud = 1843200, |
3080 | .uart_offset = 8, | 3083 | .uart_offset = 8, |
3081 | }, | 3084 | }, |
3082 | [pbn_b0_4_1843200] = { | 3085 | [pbn_b0_4_1843200] = { |
3083 | .flags = FL_BASE0, | 3086 | .flags = FL_BASE0, |
3084 | .num_ports = 4, | 3087 | .num_ports = 4, |
3085 | .base_baud = 1843200, | 3088 | .base_baud = 1843200, |
3086 | .uart_offset = 8, | 3089 | .uart_offset = 8, |
3087 | }, | 3090 | }, |
3088 | 3091 | ||
3089 | [pbn_b0_2_1843200_200] = { | 3092 | [pbn_b0_2_1843200_200] = { |
3090 | .flags = FL_BASE0, | 3093 | .flags = FL_BASE0, |
3091 | .num_ports = 2, | 3094 | .num_ports = 2, |
3092 | .base_baud = 1843200, | 3095 | .base_baud = 1843200, |
3093 | .uart_offset = 0x200, | 3096 | .uart_offset = 0x200, |
3094 | }, | 3097 | }, |
3095 | [pbn_b0_4_1843200_200] = { | 3098 | [pbn_b0_4_1843200_200] = { |
3096 | .flags = FL_BASE0, | 3099 | .flags = FL_BASE0, |
3097 | .num_ports = 4, | 3100 | .num_ports = 4, |
3098 | .base_baud = 1843200, | 3101 | .base_baud = 1843200, |
3099 | .uart_offset = 0x200, | 3102 | .uart_offset = 0x200, |
3100 | }, | 3103 | }, |
3101 | [pbn_b0_8_1843200_200] = { | 3104 | [pbn_b0_8_1843200_200] = { |
3102 | .flags = FL_BASE0, | 3105 | .flags = FL_BASE0, |
3103 | .num_ports = 8, | 3106 | .num_ports = 8, |
3104 | .base_baud = 1843200, | 3107 | .base_baud = 1843200, |
3105 | .uart_offset = 0x200, | 3108 | .uart_offset = 0x200, |
3106 | }, | 3109 | }, |
3107 | [pbn_b0_1_4000000] = { | 3110 | [pbn_b0_1_4000000] = { |
3108 | .flags = FL_BASE0, | 3111 | .flags = FL_BASE0, |
3109 | .num_ports = 1, | 3112 | .num_ports = 1, |
3110 | .base_baud = 4000000, | 3113 | .base_baud = 4000000, |
3111 | .uart_offset = 8, | 3114 | .uart_offset = 8, |
3112 | }, | 3115 | }, |
3113 | 3116 | ||
3114 | [pbn_b0_bt_1_115200] = { | 3117 | [pbn_b0_bt_1_115200] = { |
3115 | .flags = FL_BASE0|FL_BASE_BARS, | 3118 | .flags = FL_BASE0|FL_BASE_BARS, |
3116 | .num_ports = 1, | 3119 | .num_ports = 1, |
3117 | .base_baud = 115200, | 3120 | .base_baud = 115200, |
3118 | .uart_offset = 8, | 3121 | .uart_offset = 8, |
3119 | }, | 3122 | }, |
3120 | [pbn_b0_bt_2_115200] = { | 3123 | [pbn_b0_bt_2_115200] = { |
3121 | .flags = FL_BASE0|FL_BASE_BARS, | 3124 | .flags = FL_BASE0|FL_BASE_BARS, |
3122 | .num_ports = 2, | 3125 | .num_ports = 2, |
3123 | .base_baud = 115200, | 3126 | .base_baud = 115200, |
3124 | .uart_offset = 8, | 3127 | .uart_offset = 8, |
3125 | }, | 3128 | }, |
3126 | [pbn_b0_bt_4_115200] = { | 3129 | [pbn_b0_bt_4_115200] = { |
3127 | .flags = FL_BASE0|FL_BASE_BARS, | 3130 | .flags = FL_BASE0|FL_BASE_BARS, |
3128 | .num_ports = 4, | 3131 | .num_ports = 4, |
3129 | .base_baud = 115200, | 3132 | .base_baud = 115200, |
3130 | .uart_offset = 8, | 3133 | .uart_offset = 8, |
3131 | }, | 3134 | }, |
3132 | [pbn_b0_bt_8_115200] = { | 3135 | [pbn_b0_bt_8_115200] = { |
3133 | .flags = FL_BASE0|FL_BASE_BARS, | 3136 | .flags = FL_BASE0|FL_BASE_BARS, |
3134 | .num_ports = 8, | 3137 | .num_ports = 8, |
3135 | .base_baud = 115200, | 3138 | .base_baud = 115200, |
3136 | .uart_offset = 8, | 3139 | .uart_offset = 8, |
3137 | }, | 3140 | }, |
3138 | 3141 | ||
3139 | [pbn_b0_bt_1_460800] = { | 3142 | [pbn_b0_bt_1_460800] = { |
3140 | .flags = FL_BASE0|FL_BASE_BARS, | 3143 | .flags = FL_BASE0|FL_BASE_BARS, |
3141 | .num_ports = 1, | 3144 | .num_ports = 1, |
3142 | .base_baud = 460800, | 3145 | .base_baud = 460800, |
3143 | .uart_offset = 8, | 3146 | .uart_offset = 8, |
3144 | }, | 3147 | }, |
3145 | [pbn_b0_bt_2_460800] = { | 3148 | [pbn_b0_bt_2_460800] = { |
3146 | .flags = FL_BASE0|FL_BASE_BARS, | 3149 | .flags = FL_BASE0|FL_BASE_BARS, |
3147 | .num_ports = 2, | 3150 | .num_ports = 2, |
3148 | .base_baud = 460800, | 3151 | .base_baud = 460800, |
3149 | .uart_offset = 8, | 3152 | .uart_offset = 8, |
3150 | }, | 3153 | }, |
3151 | [pbn_b0_bt_4_460800] = { | 3154 | [pbn_b0_bt_4_460800] = { |
3152 | .flags = FL_BASE0|FL_BASE_BARS, | 3155 | .flags = FL_BASE0|FL_BASE_BARS, |
3153 | .num_ports = 4, | 3156 | .num_ports = 4, |
3154 | .base_baud = 460800, | 3157 | .base_baud = 460800, |
3155 | .uart_offset = 8, | 3158 | .uart_offset = 8, |
3156 | }, | 3159 | }, |
3157 | 3160 | ||
3158 | [pbn_b0_bt_1_921600] = { | 3161 | [pbn_b0_bt_1_921600] = { |
3159 | .flags = FL_BASE0|FL_BASE_BARS, | 3162 | .flags = FL_BASE0|FL_BASE_BARS, |
3160 | .num_ports = 1, | 3163 | .num_ports = 1, |
3161 | .base_baud = 921600, | 3164 | .base_baud = 921600, |
3162 | .uart_offset = 8, | 3165 | .uart_offset = 8, |
3163 | }, | 3166 | }, |
3164 | [pbn_b0_bt_2_921600] = { | 3167 | [pbn_b0_bt_2_921600] = { |
3165 | .flags = FL_BASE0|FL_BASE_BARS, | 3168 | .flags = FL_BASE0|FL_BASE_BARS, |
3166 | .num_ports = 2, | 3169 | .num_ports = 2, |
3167 | .base_baud = 921600, | 3170 | .base_baud = 921600, |
3168 | .uart_offset = 8, | 3171 | .uart_offset = 8, |
3169 | }, | 3172 | }, |
3170 | [pbn_b0_bt_4_921600] = { | 3173 | [pbn_b0_bt_4_921600] = { |
3171 | .flags = FL_BASE0|FL_BASE_BARS, | 3174 | .flags = FL_BASE0|FL_BASE_BARS, |
3172 | .num_ports = 4, | 3175 | .num_ports = 4, |
3173 | .base_baud = 921600, | 3176 | .base_baud = 921600, |
3174 | .uart_offset = 8, | 3177 | .uart_offset = 8, |
3175 | }, | 3178 | }, |
3176 | [pbn_b0_bt_8_921600] = { | 3179 | [pbn_b0_bt_8_921600] = { |
3177 | .flags = FL_BASE0|FL_BASE_BARS, | 3180 | .flags = FL_BASE0|FL_BASE_BARS, |
3178 | .num_ports = 8, | 3181 | .num_ports = 8, |
3179 | .base_baud = 921600, | 3182 | .base_baud = 921600, |
3180 | .uart_offset = 8, | 3183 | .uart_offset = 8, |
3181 | }, | 3184 | }, |
3182 | 3185 | ||
3183 | [pbn_b1_1_115200] = { | 3186 | [pbn_b1_1_115200] = { |
3184 | .flags = FL_BASE1, | 3187 | .flags = FL_BASE1, |
3185 | .num_ports = 1, | 3188 | .num_ports = 1, |
3186 | .base_baud = 115200, | 3189 | .base_baud = 115200, |
3187 | .uart_offset = 8, | 3190 | .uart_offset = 8, |
3188 | }, | 3191 | }, |
3189 | [pbn_b1_2_115200] = { | 3192 | [pbn_b1_2_115200] = { |
3190 | .flags = FL_BASE1, | 3193 | .flags = FL_BASE1, |
3191 | .num_ports = 2, | 3194 | .num_ports = 2, |
3192 | .base_baud = 115200, | 3195 | .base_baud = 115200, |
3193 | .uart_offset = 8, | 3196 | .uart_offset = 8, |
3194 | }, | 3197 | }, |
3195 | [pbn_b1_4_115200] = { | 3198 | [pbn_b1_4_115200] = { |
3196 | .flags = FL_BASE1, | 3199 | .flags = FL_BASE1, |
3197 | .num_ports = 4, | 3200 | .num_ports = 4, |
3198 | .base_baud = 115200, | 3201 | .base_baud = 115200, |
3199 | .uart_offset = 8, | 3202 | .uart_offset = 8, |
3200 | }, | 3203 | }, |
3201 | [pbn_b1_8_115200] = { | 3204 | [pbn_b1_8_115200] = { |
3202 | .flags = FL_BASE1, | 3205 | .flags = FL_BASE1, |
3203 | .num_ports = 8, | 3206 | .num_ports = 8, |
3204 | .base_baud = 115200, | 3207 | .base_baud = 115200, |
3205 | .uart_offset = 8, | 3208 | .uart_offset = 8, |
3206 | }, | 3209 | }, |
3207 | [pbn_b1_16_115200] = { | 3210 | [pbn_b1_16_115200] = { |
3208 | .flags = FL_BASE1, | 3211 | .flags = FL_BASE1, |
3209 | .num_ports = 16, | 3212 | .num_ports = 16, |
3210 | .base_baud = 115200, | 3213 | .base_baud = 115200, |
3211 | .uart_offset = 8, | 3214 | .uart_offset = 8, |
3212 | }, | 3215 | }, |
3213 | 3216 | ||
3214 | [pbn_b1_1_921600] = { | 3217 | [pbn_b1_1_921600] = { |
3215 | .flags = FL_BASE1, | 3218 | .flags = FL_BASE1, |
3216 | .num_ports = 1, | 3219 | .num_ports = 1, |
3217 | .base_baud = 921600, | 3220 | .base_baud = 921600, |
3218 | .uart_offset = 8, | 3221 | .uart_offset = 8, |
3219 | }, | 3222 | }, |
3220 | [pbn_b1_2_921600] = { | 3223 | [pbn_b1_2_921600] = { |
3221 | .flags = FL_BASE1, | 3224 | .flags = FL_BASE1, |
3222 | .num_ports = 2, | 3225 | .num_ports = 2, |
3223 | .base_baud = 921600, | 3226 | .base_baud = 921600, |
3224 | .uart_offset = 8, | 3227 | .uart_offset = 8, |
3225 | }, | 3228 | }, |
3226 | [pbn_b1_4_921600] = { | 3229 | [pbn_b1_4_921600] = { |
3227 | .flags = FL_BASE1, | 3230 | .flags = FL_BASE1, |
3228 | .num_ports = 4, | 3231 | .num_ports = 4, |
3229 | .base_baud = 921600, | 3232 | .base_baud = 921600, |
3230 | .uart_offset = 8, | 3233 | .uart_offset = 8, |
3231 | }, | 3234 | }, |
3232 | [pbn_b1_8_921600] = { | 3235 | [pbn_b1_8_921600] = { |
3233 | .flags = FL_BASE1, | 3236 | .flags = FL_BASE1, |
3234 | .num_ports = 8, | 3237 | .num_ports = 8, |
3235 | .base_baud = 921600, | 3238 | .base_baud = 921600, |
3236 | .uart_offset = 8, | 3239 | .uart_offset = 8, |
3237 | }, | 3240 | }, |
3238 | [pbn_b1_2_1250000] = { | 3241 | [pbn_b1_2_1250000] = { |
3239 | .flags = FL_BASE1, | 3242 | .flags = FL_BASE1, |
3240 | .num_ports = 2, | 3243 | .num_ports = 2, |
3241 | .base_baud = 1250000, | 3244 | .base_baud = 1250000, |
3242 | .uart_offset = 8, | 3245 | .uart_offset = 8, |
3243 | }, | 3246 | }, |
3244 | 3247 | ||
3245 | [pbn_b1_bt_1_115200] = { | 3248 | [pbn_b1_bt_1_115200] = { |
3246 | .flags = FL_BASE1|FL_BASE_BARS, | 3249 | .flags = FL_BASE1|FL_BASE_BARS, |
3247 | .num_ports = 1, | 3250 | .num_ports = 1, |
3248 | .base_baud = 115200, | 3251 | .base_baud = 115200, |
3249 | .uart_offset = 8, | 3252 | .uart_offset = 8, |
3250 | }, | 3253 | }, |
3251 | [pbn_b1_bt_2_115200] = { | 3254 | [pbn_b1_bt_2_115200] = { |
3252 | .flags = FL_BASE1|FL_BASE_BARS, | 3255 | .flags = FL_BASE1|FL_BASE_BARS, |
3253 | .num_ports = 2, | 3256 | .num_ports = 2, |
3254 | .base_baud = 115200, | 3257 | .base_baud = 115200, |
3255 | .uart_offset = 8, | 3258 | .uart_offset = 8, |
3256 | }, | 3259 | }, |
3257 | [pbn_b1_bt_4_115200] = { | 3260 | [pbn_b1_bt_4_115200] = { |
3258 | .flags = FL_BASE1|FL_BASE_BARS, | 3261 | .flags = FL_BASE1|FL_BASE_BARS, |
3259 | .num_ports = 4, | 3262 | .num_ports = 4, |
3260 | .base_baud = 115200, | 3263 | .base_baud = 115200, |
3261 | .uart_offset = 8, | 3264 | .uart_offset = 8, |
3262 | }, | 3265 | }, |
3263 | 3266 | ||
3264 | [pbn_b1_bt_2_921600] = { | 3267 | [pbn_b1_bt_2_921600] = { |
3265 | .flags = FL_BASE1|FL_BASE_BARS, | 3268 | .flags = FL_BASE1|FL_BASE_BARS, |
3266 | .num_ports = 2, | 3269 | .num_ports = 2, |
3267 | .base_baud = 921600, | 3270 | .base_baud = 921600, |
3268 | .uart_offset = 8, | 3271 | .uart_offset = 8, |
3269 | }, | 3272 | }, |
3270 | 3273 | ||
3271 | [pbn_b1_1_1382400] = { | 3274 | [pbn_b1_1_1382400] = { |
3272 | .flags = FL_BASE1, | 3275 | .flags = FL_BASE1, |
3273 | .num_ports = 1, | 3276 | .num_ports = 1, |
3274 | .base_baud = 1382400, | 3277 | .base_baud = 1382400, |
3275 | .uart_offset = 8, | 3278 | .uart_offset = 8, |
3276 | }, | 3279 | }, |
3277 | [pbn_b1_2_1382400] = { | 3280 | [pbn_b1_2_1382400] = { |
3278 | .flags = FL_BASE1, | 3281 | .flags = FL_BASE1, |
3279 | .num_ports = 2, | 3282 | .num_ports = 2, |
3280 | .base_baud = 1382400, | 3283 | .base_baud = 1382400, |
3281 | .uart_offset = 8, | 3284 | .uart_offset = 8, |
3282 | }, | 3285 | }, |
3283 | [pbn_b1_4_1382400] = { | 3286 | [pbn_b1_4_1382400] = { |
3284 | .flags = FL_BASE1, | 3287 | .flags = FL_BASE1, |
3285 | .num_ports = 4, | 3288 | .num_ports = 4, |
3286 | .base_baud = 1382400, | 3289 | .base_baud = 1382400, |
3287 | .uart_offset = 8, | 3290 | .uart_offset = 8, |
3288 | }, | 3291 | }, |
3289 | [pbn_b1_8_1382400] = { | 3292 | [pbn_b1_8_1382400] = { |
3290 | .flags = FL_BASE1, | 3293 | .flags = FL_BASE1, |
3291 | .num_ports = 8, | 3294 | .num_ports = 8, |
3292 | .base_baud = 1382400, | 3295 | .base_baud = 1382400, |
3293 | .uart_offset = 8, | 3296 | .uart_offset = 8, |
3294 | }, | 3297 | }, |
3295 | 3298 | ||
3296 | [pbn_b2_1_115200] = { | 3299 | [pbn_b2_1_115200] = { |
3297 | .flags = FL_BASE2, | 3300 | .flags = FL_BASE2, |
3298 | .num_ports = 1, | 3301 | .num_ports = 1, |
3299 | .base_baud = 115200, | 3302 | .base_baud = 115200, |
3300 | .uart_offset = 8, | 3303 | .uart_offset = 8, |
3301 | }, | 3304 | }, |
3302 | [pbn_b2_2_115200] = { | 3305 | [pbn_b2_2_115200] = { |
3303 | .flags = FL_BASE2, | 3306 | .flags = FL_BASE2, |
3304 | .num_ports = 2, | 3307 | .num_ports = 2, |
3305 | .base_baud = 115200, | 3308 | .base_baud = 115200, |
3306 | .uart_offset = 8, | 3309 | .uart_offset = 8, |
3307 | }, | 3310 | }, |
3308 | [pbn_b2_4_115200] = { | 3311 | [pbn_b2_4_115200] = { |
3309 | .flags = FL_BASE2, | 3312 | .flags = FL_BASE2, |
3310 | .num_ports = 4, | 3313 | .num_ports = 4, |
3311 | .base_baud = 115200, | 3314 | .base_baud = 115200, |
3312 | .uart_offset = 8, | 3315 | .uart_offset = 8, |
3313 | }, | 3316 | }, |
3314 | [pbn_b2_8_115200] = { | 3317 | [pbn_b2_8_115200] = { |
3315 | .flags = FL_BASE2, | 3318 | .flags = FL_BASE2, |
3316 | .num_ports = 8, | 3319 | .num_ports = 8, |
3317 | .base_baud = 115200, | 3320 | .base_baud = 115200, |
3318 | .uart_offset = 8, | 3321 | .uart_offset = 8, |
3319 | }, | 3322 | }, |
3320 | 3323 | ||
3321 | [pbn_b2_1_460800] = { | 3324 | [pbn_b2_1_460800] = { |
3322 | .flags = FL_BASE2, | 3325 | .flags = FL_BASE2, |
3323 | .num_ports = 1, | 3326 | .num_ports = 1, |
3324 | .base_baud = 460800, | 3327 | .base_baud = 460800, |
3325 | .uart_offset = 8, | 3328 | .uart_offset = 8, |
3326 | }, | 3329 | }, |
3327 | [pbn_b2_4_460800] = { | 3330 | [pbn_b2_4_460800] = { |
3328 | .flags = FL_BASE2, | 3331 | .flags = FL_BASE2, |
3329 | .num_ports = 4, | 3332 | .num_ports = 4, |
3330 | .base_baud = 460800, | 3333 | .base_baud = 460800, |
3331 | .uart_offset = 8, | 3334 | .uart_offset = 8, |
3332 | }, | 3335 | }, |
3333 | [pbn_b2_8_460800] = { | 3336 | [pbn_b2_8_460800] = { |
3334 | .flags = FL_BASE2, | 3337 | .flags = FL_BASE2, |
3335 | .num_ports = 8, | 3338 | .num_ports = 8, |
3336 | .base_baud = 460800, | 3339 | .base_baud = 460800, |
3337 | .uart_offset = 8, | 3340 | .uart_offset = 8, |
3338 | }, | 3341 | }, |
3339 | [pbn_b2_16_460800] = { | 3342 | [pbn_b2_16_460800] = { |
3340 | .flags = FL_BASE2, | 3343 | .flags = FL_BASE2, |
3341 | .num_ports = 16, | 3344 | .num_ports = 16, |
3342 | .base_baud = 460800, | 3345 | .base_baud = 460800, |
3343 | .uart_offset = 8, | 3346 | .uart_offset = 8, |
3344 | }, | 3347 | }, |
3345 | 3348 | ||
3346 | [pbn_b2_1_921600] = { | 3349 | [pbn_b2_1_921600] = { |
3347 | .flags = FL_BASE2, | 3350 | .flags = FL_BASE2, |
3348 | .num_ports = 1, | 3351 | .num_ports = 1, |
3349 | .base_baud = 921600, | 3352 | .base_baud = 921600, |
3350 | .uart_offset = 8, | 3353 | .uart_offset = 8, |
3351 | }, | 3354 | }, |
3352 | [pbn_b2_4_921600] = { | 3355 | [pbn_b2_4_921600] = { |
3353 | .flags = FL_BASE2, | 3356 | .flags = FL_BASE2, |
3354 | .num_ports = 4, | 3357 | .num_ports = 4, |
3355 | .base_baud = 921600, | 3358 | .base_baud = 921600, |
3356 | .uart_offset = 8, | 3359 | .uart_offset = 8, |
3357 | }, | 3360 | }, |
3358 | [pbn_b2_8_921600] = { | 3361 | [pbn_b2_8_921600] = { |
3359 | .flags = FL_BASE2, | 3362 | .flags = FL_BASE2, |
3360 | .num_ports = 8, | 3363 | .num_ports = 8, |
3361 | .base_baud = 921600, | 3364 | .base_baud = 921600, |
3362 | .uart_offset = 8, | 3365 | .uart_offset = 8, |
3363 | }, | 3366 | }, |
3364 | 3367 | ||
3365 | [pbn_b2_8_1152000] = { | 3368 | [pbn_b2_8_1152000] = { |
3366 | .flags = FL_BASE2, | 3369 | .flags = FL_BASE2, |
3367 | .num_ports = 8, | 3370 | .num_ports = 8, |
3368 | .base_baud = 1152000, | 3371 | .base_baud = 1152000, |
3369 | .uart_offset = 8, | 3372 | .uart_offset = 8, |
3370 | }, | 3373 | }, |
3371 | 3374 | ||
3372 | [pbn_b2_bt_1_115200] = { | 3375 | [pbn_b2_bt_1_115200] = { |
3373 | .flags = FL_BASE2|FL_BASE_BARS, | 3376 | .flags = FL_BASE2|FL_BASE_BARS, |
3374 | .num_ports = 1, | 3377 | .num_ports = 1, |
3375 | .base_baud = 115200, | 3378 | .base_baud = 115200, |
3376 | .uart_offset = 8, | 3379 | .uart_offset = 8, |
3377 | }, | 3380 | }, |
3378 | [pbn_b2_bt_2_115200] = { | 3381 | [pbn_b2_bt_2_115200] = { |
3379 | .flags = FL_BASE2|FL_BASE_BARS, | 3382 | .flags = FL_BASE2|FL_BASE_BARS, |
3380 | .num_ports = 2, | 3383 | .num_ports = 2, |
3381 | .base_baud = 115200, | 3384 | .base_baud = 115200, |
3382 | .uart_offset = 8, | 3385 | .uart_offset = 8, |
3383 | }, | 3386 | }, |
3384 | [pbn_b2_bt_4_115200] = { | 3387 | [pbn_b2_bt_4_115200] = { |
3385 | .flags = FL_BASE2|FL_BASE_BARS, | 3388 | .flags = FL_BASE2|FL_BASE_BARS, |
3386 | .num_ports = 4, | 3389 | .num_ports = 4, |
3387 | .base_baud = 115200, | 3390 | .base_baud = 115200, |
3388 | .uart_offset = 8, | 3391 | .uart_offset = 8, |
3389 | }, | 3392 | }, |
3390 | 3393 | ||
3391 | [pbn_b2_bt_2_921600] = { | 3394 | [pbn_b2_bt_2_921600] = { |
3392 | .flags = FL_BASE2|FL_BASE_BARS, | 3395 | .flags = FL_BASE2|FL_BASE_BARS, |
3393 | .num_ports = 2, | 3396 | .num_ports = 2, |
3394 | .base_baud = 921600, | 3397 | .base_baud = 921600, |
3395 | .uart_offset = 8, | 3398 | .uart_offset = 8, |
3396 | }, | 3399 | }, |
3397 | [pbn_b2_bt_4_921600] = { | 3400 | [pbn_b2_bt_4_921600] = { |
3398 | .flags = FL_BASE2|FL_BASE_BARS, | 3401 | .flags = FL_BASE2|FL_BASE_BARS, |
3399 | .num_ports = 4, | 3402 | .num_ports = 4, |
3400 | .base_baud = 921600, | 3403 | .base_baud = 921600, |
3401 | .uart_offset = 8, | 3404 | .uart_offset = 8, |
3402 | }, | 3405 | }, |
3403 | 3406 | ||
3404 | [pbn_b3_2_115200] = { | 3407 | [pbn_b3_2_115200] = { |
3405 | .flags = FL_BASE3, | 3408 | .flags = FL_BASE3, |
3406 | .num_ports = 2, | 3409 | .num_ports = 2, |
3407 | .base_baud = 115200, | 3410 | .base_baud = 115200, |
3408 | .uart_offset = 8, | 3411 | .uart_offset = 8, |
3409 | }, | 3412 | }, |
3410 | [pbn_b3_4_115200] = { | 3413 | [pbn_b3_4_115200] = { |
3411 | .flags = FL_BASE3, | 3414 | .flags = FL_BASE3, |
3412 | .num_ports = 4, | 3415 | .num_ports = 4, |
3413 | .base_baud = 115200, | 3416 | .base_baud = 115200, |
3414 | .uart_offset = 8, | 3417 | .uart_offset = 8, |
3415 | }, | 3418 | }, |
3416 | [pbn_b3_8_115200] = { | 3419 | [pbn_b3_8_115200] = { |
3417 | .flags = FL_BASE3, | 3420 | .flags = FL_BASE3, |
3418 | .num_ports = 8, | 3421 | .num_ports = 8, |
3419 | .base_baud = 115200, | 3422 | .base_baud = 115200, |
3420 | .uart_offset = 8, | 3423 | .uart_offset = 8, |
3421 | }, | 3424 | }, |
3422 | 3425 | ||
3423 | [pbn_b4_bt_2_921600] = { | 3426 | [pbn_b4_bt_2_921600] = { |
3424 | .flags = FL_BASE4, | 3427 | .flags = FL_BASE4, |
3425 | .num_ports = 2, | 3428 | .num_ports = 2, |
3426 | .base_baud = 921600, | 3429 | .base_baud = 921600, |
3427 | .uart_offset = 8, | 3430 | .uart_offset = 8, |
3428 | }, | 3431 | }, |
3429 | [pbn_b4_bt_4_921600] = { | 3432 | [pbn_b4_bt_4_921600] = { |
3430 | .flags = FL_BASE4, | 3433 | .flags = FL_BASE4, |
3431 | .num_ports = 4, | 3434 | .num_ports = 4, |
3432 | .base_baud = 921600, | 3435 | .base_baud = 921600, |
3433 | .uart_offset = 8, | 3436 | .uart_offset = 8, |
3434 | }, | 3437 | }, |
3435 | [pbn_b4_bt_8_921600] = { | 3438 | [pbn_b4_bt_8_921600] = { |
3436 | .flags = FL_BASE4, | 3439 | .flags = FL_BASE4, |
3437 | .num_ports = 8, | 3440 | .num_ports = 8, |
3438 | .base_baud = 921600, | 3441 | .base_baud = 921600, |
3439 | .uart_offset = 8, | 3442 | .uart_offset = 8, |
3440 | }, | 3443 | }, |
3441 | 3444 | ||
3442 | /* | 3445 | /* |
3443 | * Entries following this are board-specific. | 3446 | * Entries following this are board-specific. |
3444 | */ | 3447 | */ |
3445 | 3448 | ||
3446 | /* | 3449 | /* |
3447 | * Panacom - IOMEM | 3450 | * Panacom - IOMEM |
3448 | */ | 3451 | */ |
3449 | [pbn_panacom] = { | 3452 | [pbn_panacom] = { |
3450 | .flags = FL_BASE2, | 3453 | .flags = FL_BASE2, |
3451 | .num_ports = 2, | 3454 | .num_ports = 2, |
3452 | .base_baud = 921600, | 3455 | .base_baud = 921600, |
3453 | .uart_offset = 0x400, | 3456 | .uart_offset = 0x400, |
3454 | .reg_shift = 7, | 3457 | .reg_shift = 7, |
3455 | }, | 3458 | }, |
3456 | [pbn_panacom2] = { | 3459 | [pbn_panacom2] = { |
3457 | .flags = FL_BASE2|FL_BASE_BARS, | 3460 | .flags = FL_BASE2|FL_BASE_BARS, |
3458 | .num_ports = 2, | 3461 | .num_ports = 2, |
3459 | .base_baud = 921600, | 3462 | .base_baud = 921600, |
3460 | .uart_offset = 0x400, | 3463 | .uart_offset = 0x400, |
3461 | .reg_shift = 7, | 3464 | .reg_shift = 7, |
3462 | }, | 3465 | }, |
3463 | [pbn_panacom4] = { | 3466 | [pbn_panacom4] = { |
3464 | .flags = FL_BASE2|FL_BASE_BARS, | 3467 | .flags = FL_BASE2|FL_BASE_BARS, |
3465 | .num_ports = 4, | 3468 | .num_ports = 4, |
3466 | .base_baud = 921600, | 3469 | .base_baud = 921600, |
3467 | .uart_offset = 0x400, | 3470 | .uart_offset = 0x400, |
3468 | .reg_shift = 7, | 3471 | .reg_shift = 7, |
3469 | }, | 3472 | }, |
3470 | 3473 | ||
3471 | /* I think this entry is broken - the first_offset looks wrong --rmk */ | 3474 | /* I think this entry is broken - the first_offset looks wrong --rmk */ |
3472 | [pbn_plx_romulus] = { | 3475 | [pbn_plx_romulus] = { |
3473 | .flags = FL_BASE2, | 3476 | .flags = FL_BASE2, |
3474 | .num_ports = 4, | 3477 | .num_ports = 4, |
3475 | .base_baud = 921600, | 3478 | .base_baud = 921600, |
3476 | .uart_offset = 8 << 2, | 3479 | .uart_offset = 8 << 2, |
3477 | .reg_shift = 2, | 3480 | .reg_shift = 2, |
3478 | .first_offset = 0x03, | 3481 | .first_offset = 0x03, |
3479 | }, | 3482 | }, |
3480 | 3483 | ||
3481 | /* | 3484 | /* |
3482 | * EndRun Technologies | 3485 | * EndRun Technologies |
3483 | * Uses the size of PCI Base region 0 to | 3486 | * Uses the size of PCI Base region 0 to |
3484 | * signal now many ports are available | 3487 | * signal now many ports are available |
3485 | * 2 port 952 Uart support | 3488 | * 2 port 952 Uart support |
3486 | */ | 3489 | */ |
3487 | [pbn_endrun_2_4000000] = { | 3490 | [pbn_endrun_2_4000000] = { |
3488 | .flags = FL_BASE0, | 3491 | .flags = FL_BASE0, |
3489 | .num_ports = 2, | 3492 | .num_ports = 2, |
3490 | .base_baud = 4000000, | 3493 | .base_baud = 4000000, |
3491 | .uart_offset = 0x200, | 3494 | .uart_offset = 0x200, |
3492 | .first_offset = 0x1000, | 3495 | .first_offset = 0x1000, |
3493 | }, | 3496 | }, |
3494 | 3497 | ||
3495 | /* | 3498 | /* |
3496 | * This board uses the size of PCI Base region 0 to | 3499 | * This board uses the size of PCI Base region 0 to |
3497 | * signal now many ports are available | 3500 | * signal now many ports are available |
3498 | */ | 3501 | */ |
3499 | [pbn_oxsemi] = { | 3502 | [pbn_oxsemi] = { |
3500 | .flags = FL_BASE0|FL_REGION_SZ_CAP, | 3503 | .flags = FL_BASE0|FL_REGION_SZ_CAP, |
3501 | .num_ports = 32, | 3504 | .num_ports = 32, |
3502 | .base_baud = 115200, | 3505 | .base_baud = 115200, |
3503 | .uart_offset = 8, | 3506 | .uart_offset = 8, |
3504 | }, | 3507 | }, |
3505 | [pbn_oxsemi_1_4000000] = { | 3508 | [pbn_oxsemi_1_4000000] = { |
3506 | .flags = FL_BASE0, | 3509 | .flags = FL_BASE0, |
3507 | .num_ports = 1, | 3510 | .num_ports = 1, |
3508 | .base_baud = 4000000, | 3511 | .base_baud = 4000000, |
3509 | .uart_offset = 0x200, | 3512 | .uart_offset = 0x200, |
3510 | .first_offset = 0x1000, | 3513 | .first_offset = 0x1000, |
3511 | }, | 3514 | }, |
3512 | [pbn_oxsemi_2_4000000] = { | 3515 | [pbn_oxsemi_2_4000000] = { |
3513 | .flags = FL_BASE0, | 3516 | .flags = FL_BASE0, |
3514 | .num_ports = 2, | 3517 | .num_ports = 2, |
3515 | .base_baud = 4000000, | 3518 | .base_baud = 4000000, |
3516 | .uart_offset = 0x200, | 3519 | .uart_offset = 0x200, |
3517 | .first_offset = 0x1000, | 3520 | .first_offset = 0x1000, |
3518 | }, | 3521 | }, |
3519 | [pbn_oxsemi_4_4000000] = { | 3522 | [pbn_oxsemi_4_4000000] = { |
3520 | .flags = FL_BASE0, | 3523 | .flags = FL_BASE0, |
3521 | .num_ports = 4, | 3524 | .num_ports = 4, |
3522 | .base_baud = 4000000, | 3525 | .base_baud = 4000000, |
3523 | .uart_offset = 0x200, | 3526 | .uart_offset = 0x200, |
3524 | .first_offset = 0x1000, | 3527 | .first_offset = 0x1000, |
3525 | }, | 3528 | }, |
3526 | [pbn_oxsemi_8_4000000] = { | 3529 | [pbn_oxsemi_8_4000000] = { |
3527 | .flags = FL_BASE0, | 3530 | .flags = FL_BASE0, |
3528 | .num_ports = 8, | 3531 | .num_ports = 8, |
3529 | .base_baud = 4000000, | 3532 | .base_baud = 4000000, |
3530 | .uart_offset = 0x200, | 3533 | .uart_offset = 0x200, |
3531 | .first_offset = 0x1000, | 3534 | .first_offset = 0x1000, |
3532 | }, | 3535 | }, |
3533 | 3536 | ||
3534 | 3537 | ||
3535 | /* | 3538 | /* |
3536 | * EKF addition for i960 Boards form EKF with serial port. | 3539 | * EKF addition for i960 Boards form EKF with serial port. |
3537 | * Max 256 ports. | 3540 | * Max 256 ports. |
3538 | */ | 3541 | */ |
3539 | [pbn_intel_i960] = { | 3542 | [pbn_intel_i960] = { |
3540 | .flags = FL_BASE0, | 3543 | .flags = FL_BASE0, |
3541 | .num_ports = 32, | 3544 | .num_ports = 32, |
3542 | .base_baud = 921600, | 3545 | .base_baud = 921600, |
3543 | .uart_offset = 8 << 2, | 3546 | .uart_offset = 8 << 2, |
3544 | .reg_shift = 2, | 3547 | .reg_shift = 2, |
3545 | .first_offset = 0x10000, | 3548 | .first_offset = 0x10000, |
3546 | }, | 3549 | }, |
3547 | [pbn_sgi_ioc3] = { | 3550 | [pbn_sgi_ioc3] = { |
3548 | .flags = FL_BASE0|FL_NOIRQ, | 3551 | .flags = FL_BASE0|FL_NOIRQ, |
3549 | .num_ports = 1, | 3552 | .num_ports = 1, |
3550 | .base_baud = 458333, | 3553 | .base_baud = 458333, |
3551 | .uart_offset = 8, | 3554 | .uart_offset = 8, |
3552 | .reg_shift = 0, | 3555 | .reg_shift = 0, |
3553 | .first_offset = 0x20178, | 3556 | .first_offset = 0x20178, |
3554 | }, | 3557 | }, |
3555 | 3558 | ||
3556 | /* | 3559 | /* |
3557 | * Computone - uses IOMEM. | 3560 | * Computone - uses IOMEM. |
3558 | */ | 3561 | */ |
3559 | [pbn_computone_4] = { | 3562 | [pbn_computone_4] = { |
3560 | .flags = FL_BASE0, | 3563 | .flags = FL_BASE0, |
3561 | .num_ports = 4, | 3564 | .num_ports = 4, |
3562 | .base_baud = 921600, | 3565 | .base_baud = 921600, |
3563 | .uart_offset = 0x40, | 3566 | .uart_offset = 0x40, |
3564 | .reg_shift = 2, | 3567 | .reg_shift = 2, |
3565 | .first_offset = 0x200, | 3568 | .first_offset = 0x200, |
3566 | }, | 3569 | }, |
3567 | [pbn_computone_6] = { | 3570 | [pbn_computone_6] = { |
3568 | .flags = FL_BASE0, | 3571 | .flags = FL_BASE0, |
3569 | .num_ports = 6, | 3572 | .num_ports = 6, |
3570 | .base_baud = 921600, | 3573 | .base_baud = 921600, |
3571 | .uart_offset = 0x40, | 3574 | .uart_offset = 0x40, |
3572 | .reg_shift = 2, | 3575 | .reg_shift = 2, |
3573 | .first_offset = 0x200, | 3576 | .first_offset = 0x200, |
3574 | }, | 3577 | }, |
3575 | [pbn_computone_8] = { | 3578 | [pbn_computone_8] = { |
3576 | .flags = FL_BASE0, | 3579 | .flags = FL_BASE0, |
3577 | .num_ports = 8, | 3580 | .num_ports = 8, |
3578 | .base_baud = 921600, | 3581 | .base_baud = 921600, |
3579 | .uart_offset = 0x40, | 3582 | .uart_offset = 0x40, |
3580 | .reg_shift = 2, | 3583 | .reg_shift = 2, |
3581 | .first_offset = 0x200, | 3584 | .first_offset = 0x200, |
3582 | }, | 3585 | }, |
3583 | [pbn_sbsxrsio] = { | 3586 | [pbn_sbsxrsio] = { |
3584 | .flags = FL_BASE0, | 3587 | .flags = FL_BASE0, |
3585 | .num_ports = 8, | 3588 | .num_ports = 8, |
3586 | .base_baud = 460800, | 3589 | .base_baud = 460800, |
3587 | .uart_offset = 256, | 3590 | .uart_offset = 256, |
3588 | .reg_shift = 4, | 3591 | .reg_shift = 4, |
3589 | }, | 3592 | }, |
3590 | /* | 3593 | /* |
3591 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | 3594 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART |
3592 | * Only basic 16550A support. | 3595 | * Only basic 16550A support. |
3593 | * XR17C15[24] are not tested, but they should work. | 3596 | * XR17C15[24] are not tested, but they should work. |
3594 | */ | 3597 | */ |
3595 | [pbn_exar_XR17C152] = { | 3598 | [pbn_exar_XR17C152] = { |
3596 | .flags = FL_BASE0, | 3599 | .flags = FL_BASE0, |
3597 | .num_ports = 2, | 3600 | .num_ports = 2, |
3598 | .base_baud = 921600, | 3601 | .base_baud = 921600, |
3599 | .uart_offset = 0x200, | 3602 | .uart_offset = 0x200, |
3600 | }, | 3603 | }, |
3601 | [pbn_exar_XR17C154] = { | 3604 | [pbn_exar_XR17C154] = { |
3602 | .flags = FL_BASE0, | 3605 | .flags = FL_BASE0, |
3603 | .num_ports = 4, | 3606 | .num_ports = 4, |
3604 | .base_baud = 921600, | 3607 | .base_baud = 921600, |
3605 | .uart_offset = 0x200, | 3608 | .uart_offset = 0x200, |
3606 | }, | 3609 | }, |
3607 | [pbn_exar_XR17C158] = { | 3610 | [pbn_exar_XR17C158] = { |
3608 | .flags = FL_BASE0, | 3611 | .flags = FL_BASE0, |
3609 | .num_ports = 8, | 3612 | .num_ports = 8, |
3610 | .base_baud = 921600, | 3613 | .base_baud = 921600, |
3611 | .uart_offset = 0x200, | 3614 | .uart_offset = 0x200, |
3612 | }, | 3615 | }, |
3613 | [pbn_exar_XR17V352] = { | 3616 | [pbn_exar_XR17V352] = { |
3614 | .flags = FL_BASE0, | 3617 | .flags = FL_BASE0, |
3615 | .num_ports = 2, | 3618 | .num_ports = 2, |
3616 | .base_baud = 7812500, | 3619 | .base_baud = 7812500, |
3617 | .uart_offset = 0x400, | 3620 | .uart_offset = 0x400, |
3618 | .reg_shift = 0, | 3621 | .reg_shift = 0, |
3619 | .first_offset = 0, | 3622 | .first_offset = 0, |
3620 | }, | 3623 | }, |
3621 | [pbn_exar_XR17V354] = { | 3624 | [pbn_exar_XR17V354] = { |
3622 | .flags = FL_BASE0, | 3625 | .flags = FL_BASE0, |
3623 | .num_ports = 4, | 3626 | .num_ports = 4, |
3624 | .base_baud = 7812500, | 3627 | .base_baud = 7812500, |
3625 | .uart_offset = 0x400, | 3628 | .uart_offset = 0x400, |
3626 | .reg_shift = 0, | 3629 | .reg_shift = 0, |
3627 | .first_offset = 0, | 3630 | .first_offset = 0, |
3628 | }, | 3631 | }, |
3629 | [pbn_exar_XR17V358] = { | 3632 | [pbn_exar_XR17V358] = { |
3630 | .flags = FL_BASE0, | 3633 | .flags = FL_BASE0, |
3631 | .num_ports = 8, | 3634 | .num_ports = 8, |
3632 | .base_baud = 7812500, | 3635 | .base_baud = 7812500, |
3633 | .uart_offset = 0x400, | 3636 | .uart_offset = 0x400, |
3634 | .reg_shift = 0, | 3637 | .reg_shift = 0, |
3635 | .first_offset = 0, | 3638 | .first_offset = 0, |
3636 | }, | 3639 | }, |
3637 | [pbn_exar_XR17V4358] = { | 3640 | [pbn_exar_XR17V4358] = { |
3638 | .flags = FL_BASE0, | 3641 | .flags = FL_BASE0, |
3639 | .num_ports = 12, | 3642 | .num_ports = 12, |
3640 | .base_baud = 7812500, | 3643 | .base_baud = 7812500, |
3641 | .uart_offset = 0x400, | 3644 | .uart_offset = 0x400, |
3642 | .reg_shift = 0, | 3645 | .reg_shift = 0, |
3643 | .first_offset = 0, | 3646 | .first_offset = 0, |
3644 | }, | 3647 | }, |
3645 | [pbn_exar_XR17V8358] = { | 3648 | [pbn_exar_XR17V8358] = { |
3646 | .flags = FL_BASE0, | 3649 | .flags = FL_BASE0, |
3647 | .num_ports = 16, | 3650 | .num_ports = 16, |
3648 | .base_baud = 7812500, | 3651 | .base_baud = 7812500, |
3649 | .uart_offset = 0x400, | 3652 | .uart_offset = 0x400, |
3650 | .reg_shift = 0, | 3653 | .reg_shift = 0, |
3651 | .first_offset = 0, | 3654 | .first_offset = 0, |
3652 | }, | 3655 | }, |
3653 | [pbn_exar_ibm_saturn] = { | 3656 | [pbn_exar_ibm_saturn] = { |
3654 | .flags = FL_BASE0, | 3657 | .flags = FL_BASE0, |
3655 | .num_ports = 1, | 3658 | .num_ports = 1, |
3656 | .base_baud = 921600, | 3659 | .base_baud = 921600, |
3657 | .uart_offset = 0x200, | 3660 | .uart_offset = 0x200, |
3658 | }, | 3661 | }, |
3659 | 3662 | ||
3660 | /* | 3663 | /* |
3661 | * PA Semi PWRficient PA6T-1682M on-chip UART | 3664 | * PA Semi PWRficient PA6T-1682M on-chip UART |
3662 | */ | 3665 | */ |
3663 | [pbn_pasemi_1682M] = { | 3666 | [pbn_pasemi_1682M] = { |
3664 | .flags = FL_BASE0, | 3667 | .flags = FL_BASE0, |
3665 | .num_ports = 1, | 3668 | .num_ports = 1, |
3666 | .base_baud = 8333333, | 3669 | .base_baud = 8333333, |
3667 | }, | 3670 | }, |
3668 | /* | 3671 | /* |
3669 | * National Instruments 843x | 3672 | * National Instruments 843x |
3670 | */ | 3673 | */ |
3671 | [pbn_ni8430_16] = { | 3674 | [pbn_ni8430_16] = { |
3672 | .flags = FL_BASE0, | 3675 | .flags = FL_BASE0, |
3673 | .num_ports = 16, | 3676 | .num_ports = 16, |
3674 | .base_baud = 3686400, | 3677 | .base_baud = 3686400, |
3675 | .uart_offset = 0x10, | 3678 | .uart_offset = 0x10, |
3676 | .first_offset = 0x800, | 3679 | .first_offset = 0x800, |
3677 | }, | 3680 | }, |
3678 | [pbn_ni8430_8] = { | 3681 | [pbn_ni8430_8] = { |
3679 | .flags = FL_BASE0, | 3682 | .flags = FL_BASE0, |
3680 | .num_ports = 8, | 3683 | .num_ports = 8, |
3681 | .base_baud = 3686400, | 3684 | .base_baud = 3686400, |
3682 | .uart_offset = 0x10, | 3685 | .uart_offset = 0x10, |
3683 | .first_offset = 0x800, | 3686 | .first_offset = 0x800, |
3684 | }, | 3687 | }, |
3685 | [pbn_ni8430_4] = { | 3688 | [pbn_ni8430_4] = { |
3686 | .flags = FL_BASE0, | 3689 | .flags = FL_BASE0, |
3687 | .num_ports = 4, | 3690 | .num_ports = 4, |
3688 | .base_baud = 3686400, | 3691 | .base_baud = 3686400, |
3689 | .uart_offset = 0x10, | 3692 | .uart_offset = 0x10, |
3690 | .first_offset = 0x800, | 3693 | .first_offset = 0x800, |
3691 | }, | 3694 | }, |
3692 | [pbn_ni8430_2] = { | 3695 | [pbn_ni8430_2] = { |
3693 | .flags = FL_BASE0, | 3696 | .flags = FL_BASE0, |
3694 | .num_ports = 2, | 3697 | .num_ports = 2, |
3695 | .base_baud = 3686400, | 3698 | .base_baud = 3686400, |
3696 | .uart_offset = 0x10, | 3699 | .uart_offset = 0x10, |
3697 | .first_offset = 0x800, | 3700 | .first_offset = 0x800, |
3698 | }, | 3701 | }, |
3699 | /* | 3702 | /* |
3700 | * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> | 3703 | * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> |
3701 | */ | 3704 | */ |
3702 | [pbn_ADDIDATA_PCIe_1_3906250] = { | 3705 | [pbn_ADDIDATA_PCIe_1_3906250] = { |
3703 | .flags = FL_BASE0, | 3706 | .flags = FL_BASE0, |
3704 | .num_ports = 1, | 3707 | .num_ports = 1, |
3705 | .base_baud = 3906250, | 3708 | .base_baud = 3906250, |
3706 | .uart_offset = 0x200, | 3709 | .uart_offset = 0x200, |
3707 | .first_offset = 0x1000, | 3710 | .first_offset = 0x1000, |
3708 | }, | 3711 | }, |
3709 | [pbn_ADDIDATA_PCIe_2_3906250] = { | 3712 | [pbn_ADDIDATA_PCIe_2_3906250] = { |
3710 | .flags = FL_BASE0, | 3713 | .flags = FL_BASE0, |
3711 | .num_ports = 2, | 3714 | .num_ports = 2, |
3712 | .base_baud = 3906250, | 3715 | .base_baud = 3906250, |
3713 | .uart_offset = 0x200, | 3716 | .uart_offset = 0x200, |
3714 | .first_offset = 0x1000, | 3717 | .first_offset = 0x1000, |
3715 | }, | 3718 | }, |
3716 | [pbn_ADDIDATA_PCIe_4_3906250] = { | 3719 | [pbn_ADDIDATA_PCIe_4_3906250] = { |
3717 | .flags = FL_BASE0, | 3720 | .flags = FL_BASE0, |
3718 | .num_ports = 4, | 3721 | .num_ports = 4, |
3719 | .base_baud = 3906250, | 3722 | .base_baud = 3906250, |
3720 | .uart_offset = 0x200, | 3723 | .uart_offset = 0x200, |
3721 | .first_offset = 0x1000, | 3724 | .first_offset = 0x1000, |
3722 | }, | 3725 | }, |
3723 | [pbn_ADDIDATA_PCIe_8_3906250] = { | 3726 | [pbn_ADDIDATA_PCIe_8_3906250] = { |
3724 | .flags = FL_BASE0, | 3727 | .flags = FL_BASE0, |
3725 | .num_ports = 8, | 3728 | .num_ports = 8, |
3726 | .base_baud = 3906250, | 3729 | .base_baud = 3906250, |
3727 | .uart_offset = 0x200, | 3730 | .uart_offset = 0x200, |
3728 | .first_offset = 0x1000, | 3731 | .first_offset = 0x1000, |
3729 | }, | 3732 | }, |
3730 | [pbn_ce4100_1_115200] = { | 3733 | [pbn_ce4100_1_115200] = { |
3731 | .flags = FL_BASE_BARS, | 3734 | .flags = FL_BASE_BARS, |
3732 | .num_ports = 2, | 3735 | .num_ports = 2, |
3733 | .base_baud = 921600, | 3736 | .base_baud = 921600, |
3734 | .reg_shift = 2, | 3737 | .reg_shift = 2, |
3735 | }, | 3738 | }, |
3736 | /* | 3739 | /* |
3737 | * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, | 3740 | * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, |
3738 | * but is overridden by byt_set_termios. | 3741 | * but is overridden by byt_set_termios. |
3739 | */ | 3742 | */ |
3740 | [pbn_byt] = { | 3743 | [pbn_byt] = { |
3741 | .flags = FL_BASE0, | 3744 | .flags = FL_BASE0, |
3742 | .num_ports = 1, | 3745 | .num_ports = 1, |
3743 | .base_baud = 2764800, | 3746 | .base_baud = 2764800, |
3744 | .uart_offset = 0x80, | 3747 | .uart_offset = 0x80, |
3745 | .reg_shift = 2, | 3748 | .reg_shift = 2, |
3746 | }, | 3749 | }, |
3747 | [pbn_qrk] = { | 3750 | [pbn_qrk] = { |
3748 | .flags = FL_BASE0, | 3751 | .flags = FL_BASE0, |
3749 | .num_ports = 1, | 3752 | .num_ports = 1, |
3750 | .base_baud = 2764800, | 3753 | .base_baud = 2764800, |
3751 | .reg_shift = 2, | 3754 | .reg_shift = 2, |
3752 | }, | 3755 | }, |
3753 | [pbn_omegapci] = { | 3756 | [pbn_omegapci] = { |
3754 | .flags = FL_BASE0, | 3757 | .flags = FL_BASE0, |
3755 | .num_ports = 8, | 3758 | .num_ports = 8, |
3756 | .base_baud = 115200, | 3759 | .base_baud = 115200, |
3757 | .uart_offset = 0x200, | 3760 | .uart_offset = 0x200, |
3758 | }, | 3761 | }, |
3759 | [pbn_NETMOS9900_2s_115200] = { | 3762 | [pbn_NETMOS9900_2s_115200] = { |
3760 | .flags = FL_BASE0, | 3763 | .flags = FL_BASE0, |
3761 | .num_ports = 2, | 3764 | .num_ports = 2, |
3762 | .base_baud = 115200, | 3765 | .base_baud = 115200, |
3763 | }, | 3766 | }, |
3764 | [pbn_brcm_trumanage] = { | 3767 | [pbn_brcm_trumanage] = { |
3765 | .flags = FL_BASE0, | 3768 | .flags = FL_BASE0, |
3766 | .num_ports = 1, | 3769 | .num_ports = 1, |
3767 | .reg_shift = 2, | 3770 | .reg_shift = 2, |
3768 | .base_baud = 115200, | 3771 | .base_baud = 115200, |
3769 | }, | 3772 | }, |
3770 | [pbn_fintek_4] = { | 3773 | [pbn_fintek_4] = { |
3771 | .num_ports = 4, | 3774 | .num_ports = 4, |
3772 | .uart_offset = 8, | 3775 | .uart_offset = 8, |
3773 | .base_baud = 115200, | 3776 | .base_baud = 115200, |
3774 | .first_offset = 0x40, | 3777 | .first_offset = 0x40, |
3775 | }, | 3778 | }, |
3776 | [pbn_fintek_8] = { | 3779 | [pbn_fintek_8] = { |
3777 | .num_ports = 8, | 3780 | .num_ports = 8, |
3778 | .uart_offset = 8, | 3781 | .uart_offset = 8, |
3779 | .base_baud = 115200, | 3782 | .base_baud = 115200, |
3780 | .first_offset = 0x40, | 3783 | .first_offset = 0x40, |
3781 | }, | 3784 | }, |
3782 | [pbn_fintek_12] = { | 3785 | [pbn_fintek_12] = { |
3783 | .num_ports = 12, | 3786 | .num_ports = 12, |
3784 | .uart_offset = 8, | 3787 | .uart_offset = 8, |
3785 | .base_baud = 115200, | 3788 | .base_baud = 115200, |
3786 | .first_offset = 0x40, | 3789 | .first_offset = 0x40, |
3787 | }, | 3790 | }, |
3788 | [pbn_wch382_2] = { | 3791 | [pbn_wch382_2] = { |
3789 | .flags = FL_BASE0, | 3792 | .flags = FL_BASE0, |
3790 | .num_ports = 2, | 3793 | .num_ports = 2, |
3791 | .base_baud = 115200, | 3794 | .base_baud = 115200, |
3792 | .uart_offset = 8, | 3795 | .uart_offset = 8, |
3793 | .first_offset = 0xC0, | 3796 | .first_offset = 0xC0, |
3794 | }, | 3797 | }, |
3795 | [pbn_wch384_4] = { | 3798 | [pbn_wch384_4] = { |
3796 | .flags = FL_BASE0, | 3799 | .flags = FL_BASE0, |
3797 | .num_ports = 4, | 3800 | .num_ports = 4, |
3798 | .base_baud = 115200, | 3801 | .base_baud = 115200, |
3799 | .uart_offset = 8, | 3802 | .uart_offset = 8, |
3800 | .first_offset = 0xC0, | 3803 | .first_offset = 0xC0, |
3801 | }, | 3804 | }, |
3802 | /* | 3805 | /* |
3803 | * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART | 3806 | * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART |
3804 | */ | 3807 | */ |
3805 | [pbn_pericom_PI7C9X7951] = { | 3808 | [pbn_pericom_PI7C9X7951] = { |
3806 | .flags = FL_BASE0, | 3809 | .flags = FL_BASE0, |
3807 | .num_ports = 1, | 3810 | .num_ports = 1, |
3808 | .base_baud = 921600, | 3811 | .base_baud = 921600, |
3809 | .uart_offset = 0x8, | 3812 | .uart_offset = 0x8, |
3810 | }, | 3813 | }, |
3811 | [pbn_pericom_PI7C9X7952] = { | 3814 | [pbn_pericom_PI7C9X7952] = { |
3812 | .flags = FL_BASE0, | 3815 | .flags = FL_BASE0, |
3813 | .num_ports = 2, | 3816 | .num_ports = 2, |
3814 | .base_baud = 921600, | 3817 | .base_baud = 921600, |
3815 | .uart_offset = 0x8, | 3818 | .uart_offset = 0x8, |
3816 | }, | 3819 | }, |
3817 | [pbn_pericom_PI7C9X7954] = { | 3820 | [pbn_pericom_PI7C9X7954] = { |
3818 | .flags = FL_BASE0, | 3821 | .flags = FL_BASE0, |
3819 | .num_ports = 4, | 3822 | .num_ports = 4, |
3820 | .base_baud = 921600, | 3823 | .base_baud = 921600, |
3821 | .uart_offset = 0x8, | 3824 | .uart_offset = 0x8, |
3822 | }, | 3825 | }, |
3823 | [pbn_pericom_PI7C9X7958] = { | 3826 | [pbn_pericom_PI7C9X7958] = { |
3824 | .flags = FL_BASE0, | 3827 | .flags = FL_BASE0, |
3825 | .num_ports = 8, | 3828 | .num_ports = 8, |
3826 | .base_baud = 921600, | 3829 | .base_baud = 921600, |
3827 | .uart_offset = 0x8, | 3830 | .uart_offset = 0x8, |
3828 | }, | 3831 | }, |
3829 | }; | 3832 | }; |
3830 | 3833 | ||
3831 | static const struct pci_device_id blacklist[] = { | 3834 | static const struct pci_device_id blacklist[] = { |
3832 | /* softmodems */ | 3835 | /* softmodems */ |
3833 | { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ | 3836 | { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ |
3834 | { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ | 3837 | { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ |
3835 | { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ | 3838 | { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ |
3836 | 3839 | ||
3837 | /* multi-io cards handled by parport_serial */ | 3840 | /* multi-io cards handled by parport_serial */ |
3838 | { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ | 3841 | { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ |
3839 | { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ | 3842 | { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ |
3840 | { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ | 3843 | { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ |
3841 | { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ | 3844 | { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ |
3842 | 3845 | ||
3843 | /* Intel platforms with MID UART */ | 3846 | /* Intel platforms with MID UART */ |
3844 | { PCI_VDEVICE(INTEL, 0x081b), }, | 3847 | { PCI_VDEVICE(INTEL, 0x081b), }, |
3845 | { PCI_VDEVICE(INTEL, 0x081c), }, | 3848 | { PCI_VDEVICE(INTEL, 0x081c), }, |
3846 | { PCI_VDEVICE(INTEL, 0x081d), }, | 3849 | { PCI_VDEVICE(INTEL, 0x081d), }, |
3847 | { PCI_VDEVICE(INTEL, 0x1191), }, | 3850 | { PCI_VDEVICE(INTEL, 0x1191), }, |
3848 | { PCI_VDEVICE(INTEL, 0x19d8), }, | 3851 | { PCI_VDEVICE(INTEL, 0x19d8), }, |
3849 | }; | 3852 | }; |
3850 | 3853 | ||
3851 | /* | 3854 | /* |
3852 | * Given a complete unknown PCI device, try to use some heuristics to | 3855 | * Given a complete unknown PCI device, try to use some heuristics to |
3853 | * guess what the configuration might be, based on the pitiful PCI | 3856 | * guess what the configuration might be, based on the pitiful PCI |
3854 | * serial specs. Returns 0 on success, 1 on failure. | 3857 | * serial specs. Returns 0 on success, 1 on failure. |
3855 | */ | 3858 | */ |
3856 | static int | 3859 | static int |
3857 | serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) | 3860 | serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) |
3858 | { | 3861 | { |
3859 | const struct pci_device_id *bldev; | 3862 | const struct pci_device_id *bldev; |
3860 | int num_iomem, num_port, first_port = -1, i; | 3863 | int num_iomem, num_port, first_port = -1, i; |
3861 | 3864 | ||
3862 | /* | 3865 | /* |
3863 | * If it is not a communications device or the programming | 3866 | * If it is not a communications device or the programming |
3864 | * interface is greater than 6, give up. | 3867 | * interface is greater than 6, give up. |
3865 | * | 3868 | * |
3866 | * (Should we try to make guesses for multiport serial devices | 3869 | * (Should we try to make guesses for multiport serial devices |
3867 | * later?) | 3870 | * later?) |
3868 | */ | 3871 | */ |
3869 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && | 3872 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && |
3870 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || | 3873 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || |
3871 | (dev->class & 0xff) > 6) | 3874 | (dev->class & 0xff) > 6) |
3872 | return -ENODEV; | 3875 | return -ENODEV; |
3873 | 3876 | ||
3874 | /* | 3877 | /* |
3875 | * Do not access blacklisted devices that are known not to | 3878 | * Do not access blacklisted devices that are known not to |
3876 | * feature serial ports or are handled by other modules. | 3879 | * feature serial ports or are handled by other modules. |
3877 | */ | 3880 | */ |
3878 | for (bldev = blacklist; | 3881 | for (bldev = blacklist; |
3879 | bldev < blacklist + ARRAY_SIZE(blacklist); | 3882 | bldev < blacklist + ARRAY_SIZE(blacklist); |
3880 | bldev++) { | 3883 | bldev++) { |
3881 | if (dev->vendor == bldev->vendor && | 3884 | if (dev->vendor == bldev->vendor && |
3882 | dev->device == bldev->device) | 3885 | dev->device == bldev->device) |
3883 | return -ENODEV; | 3886 | return -ENODEV; |
3884 | } | 3887 | } |
3885 | 3888 | ||
3886 | num_iomem = num_port = 0; | 3889 | num_iomem = num_port = 0; |
3887 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | 3890 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
3888 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { | 3891 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { |
3889 | num_port++; | 3892 | num_port++; |
3890 | if (first_port == -1) | 3893 | if (first_port == -1) |
3891 | first_port = i; | 3894 | first_port = i; |
3892 | } | 3895 | } |
3893 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) | 3896 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) |
3894 | num_iomem++; | 3897 | num_iomem++; |
3895 | } | 3898 | } |
3896 | 3899 | ||
3897 | /* | 3900 | /* |
3898 | * If there is 1 or 0 iomem regions, and exactly one port, | 3901 | * If there is 1 or 0 iomem regions, and exactly one port, |
3899 | * use it. We guess the number of ports based on the IO | 3902 | * use it. We guess the number of ports based on the IO |
3900 | * region size. | 3903 | * region size. |
3901 | */ | 3904 | */ |
3902 | if (num_iomem <= 1 && num_port == 1) { | 3905 | if (num_iomem <= 1 && num_port == 1) { |
3903 | board->flags = first_port; | 3906 | board->flags = first_port; |
3904 | board->num_ports = pci_resource_len(dev, first_port) / 8; | 3907 | board->num_ports = pci_resource_len(dev, first_port) / 8; |
3905 | return 0; | 3908 | return 0; |
3906 | } | 3909 | } |
3907 | 3910 | ||
3908 | /* | 3911 | /* |
3909 | * Now guess if we've got a board which indexes by BARs. | 3912 | * Now guess if we've got a board which indexes by BARs. |
3910 | * Each IO BAR should be 8 bytes, and they should follow | 3913 | * Each IO BAR should be 8 bytes, and they should follow |
3911 | * consecutively. | 3914 | * consecutively. |
3912 | */ | 3915 | */ |
3913 | first_port = -1; | 3916 | first_port = -1; |
3914 | num_port = 0; | 3917 | num_port = 0; |
3915 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | 3918 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
3916 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && | 3919 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && |
3917 | pci_resource_len(dev, i) == 8 && | 3920 | pci_resource_len(dev, i) == 8 && |
3918 | (first_port == -1 || (first_port + num_port) == i)) { | 3921 | (first_port == -1 || (first_port + num_port) == i)) { |
3919 | num_port++; | 3922 | num_port++; |
3920 | if (first_port == -1) | 3923 | if (first_port == -1) |
3921 | first_port = i; | 3924 | first_port = i; |
3922 | } | 3925 | } |
3923 | } | 3926 | } |
3924 | 3927 | ||
3925 | if (num_port > 1) { | 3928 | if (num_port > 1) { |
3926 | board->flags = first_port | FL_BASE_BARS; | 3929 | board->flags = first_port | FL_BASE_BARS; |
3927 | board->num_ports = num_port; | 3930 | board->num_ports = num_port; |
3928 | return 0; | 3931 | return 0; |
3929 | } | 3932 | } |
3930 | 3933 | ||
3931 | return -ENODEV; | 3934 | return -ENODEV; |
3932 | } | 3935 | } |
3933 | 3936 | ||
3934 | static inline int | 3937 | static inline int |
3935 | serial_pci_matches(const struct pciserial_board *board, | 3938 | serial_pci_matches(const struct pciserial_board *board, |
3936 | const struct pciserial_board *guessed) | 3939 | const struct pciserial_board *guessed) |
3937 | { | 3940 | { |
3938 | return | 3941 | return |
3939 | board->num_ports == guessed->num_ports && | 3942 | board->num_ports == guessed->num_ports && |
3940 | board->base_baud == guessed->base_baud && | 3943 | board->base_baud == guessed->base_baud && |
3941 | board->uart_offset == guessed->uart_offset && | 3944 | board->uart_offset == guessed->uart_offset && |
3942 | board->reg_shift == guessed->reg_shift && | 3945 | board->reg_shift == guessed->reg_shift && |
3943 | board->first_offset == guessed->first_offset; | 3946 | board->first_offset == guessed->first_offset; |
3944 | } | 3947 | } |
3945 | 3948 | ||
3946 | struct serial_private * | 3949 | struct serial_private * |
3947 | pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) | 3950 | pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) |
3948 | { | 3951 | { |
3949 | struct uart_8250_port uart; | 3952 | struct uart_8250_port uart; |
3950 | struct serial_private *priv; | 3953 | struct serial_private *priv; |
3951 | struct pci_serial_quirk *quirk; | 3954 | struct pci_serial_quirk *quirk; |
3952 | int rc, nr_ports, i; | 3955 | int rc, nr_ports, i; |
3953 | 3956 | ||
3954 | nr_ports = board->num_ports; | 3957 | nr_ports = board->num_ports; |
3955 | 3958 | ||
3956 | /* | 3959 | /* |
3957 | * Find an init and setup quirks. | 3960 | * Find an init and setup quirks. |
3958 | */ | 3961 | */ |
3959 | quirk = find_quirk(dev); | 3962 | quirk = find_quirk(dev); |
3960 | 3963 | ||
3961 | /* | 3964 | /* |
3962 | * Run the new-style initialization function. | 3965 | * Run the new-style initialization function. |
3963 | * The initialization function returns: | 3966 | * The initialization function returns: |
3964 | * <0 - error | 3967 | * <0 - error |
3965 | * 0 - use board->num_ports | 3968 | * 0 - use board->num_ports |
3966 | * >0 - number of ports | 3969 | * >0 - number of ports |
3967 | */ | 3970 | */ |
3968 | if (quirk->init) { | 3971 | if (quirk->init) { |
3969 | rc = quirk->init(dev); | 3972 | rc = quirk->init(dev); |
3970 | if (rc < 0) { | 3973 | if (rc < 0) { |
3971 | priv = ERR_PTR(rc); | 3974 | priv = ERR_PTR(rc); |
3972 | goto err_out; | 3975 | goto err_out; |
3973 | } | 3976 | } |
3974 | if (rc) | 3977 | if (rc) |
3975 | nr_ports = rc; | 3978 | nr_ports = rc; |
3976 | } | 3979 | } |
3977 | 3980 | ||
3978 | priv = kzalloc(sizeof(struct serial_private) + | 3981 | priv = kzalloc(sizeof(struct serial_private) + |
3979 | sizeof(unsigned int) * nr_ports, | 3982 | sizeof(unsigned int) * nr_ports, |
3980 | GFP_KERNEL); | 3983 | GFP_KERNEL); |
3981 | if (!priv) { | 3984 | if (!priv) { |
3982 | priv = ERR_PTR(-ENOMEM); | 3985 | priv = ERR_PTR(-ENOMEM); |
3983 | goto err_deinit; | 3986 | goto err_deinit; |
3984 | } | 3987 | } |
3985 | 3988 | ||
3986 | priv->dev = dev; | 3989 | priv->dev = dev; |
3987 | priv->quirk = quirk; | 3990 | priv->quirk = quirk; |
3988 | 3991 | ||
3989 | memset(&uart, 0, sizeof(uart)); | 3992 | memset(&uart, 0, sizeof(uart)); |
3990 | uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | 3993 | uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; |
3991 | uart.port.uartclk = board->base_baud * 16; | 3994 | uart.port.uartclk = board->base_baud * 16; |
3992 | uart.port.irq = get_pci_irq(dev, board); | 3995 | uart.port.irq = get_pci_irq(dev, board); |
3993 | uart.port.dev = &dev->dev; | 3996 | uart.port.dev = &dev->dev; |
3994 | 3997 | ||
3995 | for (i = 0; i < nr_ports; i++) { | 3998 | for (i = 0; i < nr_ports; i++) { |
3996 | if (quirk->setup(priv, board, &uart, i)) | 3999 | if (quirk->setup(priv, board, &uart, i)) |
3997 | break; | 4000 | break; |
3998 | 4001 | ||
3999 | dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", | 4002 | dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", |
4000 | uart.port.iobase, uart.port.irq, uart.port.iotype); | 4003 | uart.port.iobase, uart.port.irq, uart.port.iotype); |
4001 | 4004 | ||
4002 | priv->line[i] = serial8250_register_8250_port(&uart); | 4005 | priv->line[i] = serial8250_register_8250_port(&uart); |
4003 | if (priv->line[i] < 0) { | 4006 | if (priv->line[i] < 0) { |
4004 | dev_err(&dev->dev, | 4007 | dev_err(&dev->dev, |
4005 | "Couldn't register serial port %lx, irq %d, type %d, error %d\n", | 4008 | "Couldn't register serial port %lx, irq %d, type %d, error %d\n", |
4006 | uart.port.iobase, uart.port.irq, | 4009 | uart.port.iobase, uart.port.irq, |
4007 | uart.port.iotype, priv->line[i]); | 4010 | uart.port.iotype, priv->line[i]); |
4008 | break; | 4011 | break; |
4009 | } | 4012 | } |
4010 | } | 4013 | } |
4011 | priv->nr = i; | 4014 | priv->nr = i; |
4012 | return priv; | 4015 | return priv; |
4013 | 4016 | ||
4014 | err_deinit: | 4017 | err_deinit: |
4015 | if (quirk->exit) | 4018 | if (quirk->exit) |
4016 | quirk->exit(dev); | 4019 | quirk->exit(dev); |
4017 | err_out: | 4020 | err_out: |
4018 | return priv; | 4021 | return priv; |
4019 | } | 4022 | } |
4020 | EXPORT_SYMBOL_GPL(pciserial_init_ports); | 4023 | EXPORT_SYMBOL_GPL(pciserial_init_ports); |
4021 | 4024 | ||
4022 | void pciserial_remove_ports(struct serial_private *priv) | 4025 | void pciserial_remove_ports(struct serial_private *priv) |
4023 | { | 4026 | { |
4024 | struct pci_serial_quirk *quirk; | 4027 | struct pci_serial_quirk *quirk; |
4025 | int i; | 4028 | int i; |
4026 | 4029 | ||
4027 | for (i = 0; i < priv->nr; i++) | 4030 | for (i = 0; i < priv->nr; i++) |
4028 | serial8250_unregister_port(priv->line[i]); | 4031 | serial8250_unregister_port(priv->line[i]); |
4029 | 4032 | ||
4030 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | 4033 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
4031 | if (priv->remapped_bar[i]) | 4034 | if (priv->remapped_bar[i]) |
4032 | iounmap(priv->remapped_bar[i]); | 4035 | iounmap(priv->remapped_bar[i]); |
4033 | priv->remapped_bar[i] = NULL; | 4036 | priv->remapped_bar[i] = NULL; |
4034 | } | 4037 | } |
4035 | 4038 | ||
4036 | /* | 4039 | /* |
4037 | * Find the exit quirks. | 4040 | * Find the exit quirks. |
4038 | */ | 4041 | */ |
4039 | quirk = find_quirk(priv->dev); | 4042 | quirk = find_quirk(priv->dev); |
4040 | if (quirk->exit) | 4043 | if (quirk->exit) |
4041 | quirk->exit(priv->dev); | 4044 | quirk->exit(priv->dev); |
4042 | 4045 | ||
4043 | kfree(priv); | 4046 | kfree(priv); |
4044 | } | 4047 | } |
4045 | EXPORT_SYMBOL_GPL(pciserial_remove_ports); | 4048 | EXPORT_SYMBOL_GPL(pciserial_remove_ports); |
4046 | 4049 | ||
4047 | void pciserial_suspend_ports(struct serial_private *priv) | 4050 | void pciserial_suspend_ports(struct serial_private *priv) |
4048 | { | 4051 | { |
4049 | int i; | 4052 | int i; |
4050 | 4053 | ||
4051 | for (i = 0; i < priv->nr; i++) | 4054 | for (i = 0; i < priv->nr; i++) |
4052 | if (priv->line[i] >= 0) | 4055 | if (priv->line[i] >= 0) |
4053 | serial8250_suspend_port(priv->line[i]); | 4056 | serial8250_suspend_port(priv->line[i]); |
4054 | 4057 | ||
4055 | /* | 4058 | /* |
4056 | * Ensure that every init quirk is properly torn down | 4059 | * Ensure that every init quirk is properly torn down |
4057 | */ | 4060 | */ |
4058 | if (priv->quirk->exit) | 4061 | if (priv->quirk->exit) |
4059 | priv->quirk->exit(priv->dev); | 4062 | priv->quirk->exit(priv->dev); |
4060 | } | 4063 | } |
4061 | EXPORT_SYMBOL_GPL(pciserial_suspend_ports); | 4064 | EXPORT_SYMBOL_GPL(pciserial_suspend_ports); |
4062 | 4065 | ||
4063 | void pciserial_resume_ports(struct serial_private *priv) | 4066 | void pciserial_resume_ports(struct serial_private *priv) |
4064 | { | 4067 | { |
4065 | int i; | 4068 | int i; |
4066 | 4069 | ||
4067 | /* | 4070 | /* |
4068 | * Ensure that the board is correctly configured. | 4071 | * Ensure that the board is correctly configured. |
4069 | */ | 4072 | */ |
4070 | if (priv->quirk->init) | 4073 | if (priv->quirk->init) |
4071 | priv->quirk->init(priv->dev); | 4074 | priv->quirk->init(priv->dev); |
4072 | 4075 | ||
4073 | for (i = 0; i < priv->nr; i++) | 4076 | for (i = 0; i < priv->nr; i++) |
4074 | if (priv->line[i] >= 0) | 4077 | if (priv->line[i] >= 0) |
4075 | serial8250_resume_port(priv->line[i]); | 4078 | serial8250_resume_port(priv->line[i]); |
4076 | } | 4079 | } |
4077 | EXPORT_SYMBOL_GPL(pciserial_resume_ports); | 4080 | EXPORT_SYMBOL_GPL(pciserial_resume_ports); |
4078 | 4081 | ||
4079 | /* | 4082 | /* |
4080 | * Probe one serial board. Unfortunately, there is no rhyme nor reason | 4083 | * Probe one serial board. Unfortunately, there is no rhyme nor reason |
4081 | * to the arrangement of serial ports on a PCI card. | 4084 | * to the arrangement of serial ports on a PCI card. |
4082 | */ | 4085 | */ |
4083 | static int | 4086 | static int |
4084 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) | 4087 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) |
4085 | { | 4088 | { |
4086 | struct pci_serial_quirk *quirk; | 4089 | struct pci_serial_quirk *quirk; |
4087 | struct serial_private *priv; | 4090 | struct serial_private *priv; |
4088 | const struct pciserial_board *board; | 4091 | const struct pciserial_board *board; |
4089 | struct pciserial_board tmp; | 4092 | struct pciserial_board tmp; |
4090 | int rc; | 4093 | int rc; |
4091 | 4094 | ||
4092 | quirk = find_quirk(dev); | 4095 | quirk = find_quirk(dev); |
4093 | if (quirk->probe) { | 4096 | if (quirk->probe) { |
4094 | rc = quirk->probe(dev); | 4097 | rc = quirk->probe(dev); |
4095 | if (rc) | 4098 | if (rc) |
4096 | return rc; | 4099 | return rc; |
4097 | } | 4100 | } |
4098 | 4101 | ||
4099 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { | 4102 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { |
4100 | dev_err(&dev->dev, "invalid driver_data: %ld\n", | 4103 | dev_err(&dev->dev, "invalid driver_data: %ld\n", |
4101 | ent->driver_data); | 4104 | ent->driver_data); |
4102 | return -EINVAL; | 4105 | return -EINVAL; |
4103 | } | 4106 | } |
4104 | 4107 | ||
4105 | board = &pci_boards[ent->driver_data]; | 4108 | board = &pci_boards[ent->driver_data]; |
4106 | 4109 | ||
4107 | rc = pci_enable_device(dev); | 4110 | rc = pci_enable_device(dev); |
4108 | pci_save_state(dev); | 4111 | pci_save_state(dev); |
4109 | if (rc) | 4112 | if (rc) |
4110 | return rc; | 4113 | return rc; |
4111 | 4114 | ||
4112 | if (ent->driver_data == pbn_default) { | 4115 | if (ent->driver_data == pbn_default) { |
4113 | /* | 4116 | /* |
4114 | * Use a copy of the pci_board entry for this; | 4117 | * Use a copy of the pci_board entry for this; |
4115 | * avoid changing entries in the table. | 4118 | * avoid changing entries in the table. |
4116 | */ | 4119 | */ |
4117 | memcpy(&tmp, board, sizeof(struct pciserial_board)); | 4120 | memcpy(&tmp, board, sizeof(struct pciserial_board)); |
4118 | board = &tmp; | 4121 | board = &tmp; |
4119 | 4122 | ||
4120 | /* | 4123 | /* |
4121 | * We matched one of our class entries. Try to | 4124 | * We matched one of our class entries. Try to |
4122 | * determine the parameters of this board. | 4125 | * determine the parameters of this board. |
4123 | */ | 4126 | */ |
4124 | rc = serial_pci_guess_board(dev, &tmp); | 4127 | rc = serial_pci_guess_board(dev, &tmp); |
4125 | if (rc) | 4128 | if (rc) |
4126 | goto disable; | 4129 | goto disable; |
4127 | } else { | 4130 | } else { |
4128 | /* | 4131 | /* |
4129 | * We matched an explicit entry. If we are able to | 4132 | * We matched an explicit entry. If we are able to |
4130 | * detect this boards settings with our heuristic, | 4133 | * detect this boards settings with our heuristic, |
4131 | * then we no longer need this entry. | 4134 | * then we no longer need this entry. |
4132 | */ | 4135 | */ |
4133 | memcpy(&tmp, &pci_boards[pbn_default], | 4136 | memcpy(&tmp, &pci_boards[pbn_default], |
4134 | sizeof(struct pciserial_board)); | 4137 | sizeof(struct pciserial_board)); |
4135 | rc = serial_pci_guess_board(dev, &tmp); | 4138 | rc = serial_pci_guess_board(dev, &tmp); |
4136 | if (rc == 0 && serial_pci_matches(board, &tmp)) | 4139 | if (rc == 0 && serial_pci_matches(board, &tmp)) |
4137 | moan_device("Redundant entry in serial pci_table.", | 4140 | moan_device("Redundant entry in serial pci_table.", |
4138 | dev); | 4141 | dev); |
4139 | } | 4142 | } |
4140 | 4143 | ||
4141 | priv = pciserial_init_ports(dev, board); | 4144 | priv = pciserial_init_ports(dev, board); |
4142 | if (!IS_ERR(priv)) { | 4145 | if (!IS_ERR(priv)) { |
4143 | pci_set_drvdata(dev, priv); | 4146 | pci_set_drvdata(dev, priv); |
4144 | return 0; | 4147 | return 0; |
4145 | } | 4148 | } |
4146 | 4149 | ||
4147 | rc = PTR_ERR(priv); | 4150 | rc = PTR_ERR(priv); |
4148 | 4151 | ||
4149 | disable: | 4152 | disable: |
4150 | pci_disable_device(dev); | 4153 | pci_disable_device(dev); |
4151 | return rc; | 4154 | return rc; |
4152 | } | 4155 | } |
4153 | 4156 | ||
4154 | static void pciserial_remove_one(struct pci_dev *dev) | 4157 | static void pciserial_remove_one(struct pci_dev *dev) |
4155 | { | 4158 | { |
4156 | struct serial_private *priv = pci_get_drvdata(dev); | 4159 | struct serial_private *priv = pci_get_drvdata(dev); |
4157 | 4160 | ||
4158 | pciserial_remove_ports(priv); | 4161 | pciserial_remove_ports(priv); |
4159 | 4162 | ||
4160 | pci_disable_device(dev); | 4163 | pci_disable_device(dev); |
4161 | } | 4164 | } |
4162 | 4165 | ||
4163 | #ifdef CONFIG_PM_SLEEP | 4166 | #ifdef CONFIG_PM_SLEEP |
4164 | static int pciserial_suspend_one(struct device *dev) | 4167 | static int pciserial_suspend_one(struct device *dev) |
4165 | { | 4168 | { |
4166 | struct pci_dev *pdev = to_pci_dev(dev); | 4169 | struct pci_dev *pdev = to_pci_dev(dev); |
4167 | struct serial_private *priv = pci_get_drvdata(pdev); | 4170 | struct serial_private *priv = pci_get_drvdata(pdev); |
4168 | 4171 | ||
4169 | if (priv) | 4172 | if (priv) |
4170 | pciserial_suspend_ports(priv); | 4173 | pciserial_suspend_ports(priv); |
4171 | 4174 | ||
4172 | return 0; | 4175 | return 0; |
4173 | } | 4176 | } |
4174 | 4177 | ||
4175 | static int pciserial_resume_one(struct device *dev) | 4178 | static int pciserial_resume_one(struct device *dev) |
4176 | { | 4179 | { |
4177 | struct pci_dev *pdev = to_pci_dev(dev); | 4180 | struct pci_dev *pdev = to_pci_dev(dev); |
4178 | struct serial_private *priv = pci_get_drvdata(pdev); | 4181 | struct serial_private *priv = pci_get_drvdata(pdev); |
4179 | int err; | 4182 | int err; |
4180 | 4183 | ||
4181 | if (priv) { | 4184 | if (priv) { |
4182 | /* | 4185 | /* |
4183 | * The device may have been disabled. Re-enable it. | 4186 | * The device may have been disabled. Re-enable it. |
4184 | */ | 4187 | */ |
4185 | err = pci_enable_device(pdev); | 4188 | err = pci_enable_device(pdev); |
4186 | /* FIXME: We cannot simply error out here */ | 4189 | /* FIXME: We cannot simply error out here */ |
4187 | if (err) | 4190 | if (err) |
4188 | dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); | 4191 | dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); |
4189 | pciserial_resume_ports(priv); | 4192 | pciserial_resume_ports(priv); |
4190 | } | 4193 | } |
4191 | return 0; | 4194 | return 0; |
4192 | } | 4195 | } |
4193 | #endif | 4196 | #endif |
4194 | 4197 | ||
4195 | static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, | 4198 | static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, |
4196 | pciserial_resume_one); | 4199 | pciserial_resume_one); |
4197 | 4200 | ||
4198 | static struct pci_device_id serial_pci_tbl[] = { | 4201 | static struct pci_device_id serial_pci_tbl[] = { |
4199 | /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ | 4202 | /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ |
4200 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, | 4203 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, |
4201 | PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, | 4204 | PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, |
4202 | pbn_b2_8_921600 }, | 4205 | pbn_b2_8_921600 }, |
4203 | /* Advantech also use 0x3618 and 0xf618 */ | 4206 | /* Advantech also use 0x3618 and 0xf618 */ |
4204 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, | 4207 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, |
4205 | PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, | 4208 | PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, |
4206 | pbn_b0_4_921600 }, | 4209 | pbn_b0_4_921600 }, |
4207 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, | 4210 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, |
4208 | PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, | 4211 | PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, |
4209 | pbn_b0_4_921600 }, | 4212 | pbn_b0_4_921600 }, |
4210 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | 4213 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
4211 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4214 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4212 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | 4215 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, |
4213 | pbn_b1_8_1382400 }, | 4216 | pbn_b1_8_1382400 }, |
4214 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | 4217 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
4215 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4218 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4216 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | 4219 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, |
4217 | pbn_b1_4_1382400 }, | 4220 | pbn_b1_4_1382400 }, |
4218 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | 4221 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
4219 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4222 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4220 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | 4223 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, |
4221 | pbn_b1_2_1382400 }, | 4224 | pbn_b1_2_1382400 }, |
4222 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4225 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4223 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4226 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4224 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | 4227 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, |
4225 | pbn_b1_8_1382400 }, | 4228 | pbn_b1_8_1382400 }, |
4226 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4229 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4227 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4230 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4228 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | 4231 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, |
4229 | pbn_b1_4_1382400 }, | 4232 | pbn_b1_4_1382400 }, |
4230 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4233 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4231 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4234 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4232 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | 4235 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, |
4233 | pbn_b1_2_1382400 }, | 4236 | pbn_b1_2_1382400 }, |
4234 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4237 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4235 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4238 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4236 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, | 4239 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, |
4237 | pbn_b1_8_921600 }, | 4240 | pbn_b1_8_921600 }, |
4238 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4241 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4239 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4242 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4240 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, | 4243 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, |
4241 | pbn_b1_8_921600 }, | 4244 | pbn_b1_8_921600 }, |
4242 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4245 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4243 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4246 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4244 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, | 4247 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, |
4245 | pbn_b1_4_921600 }, | 4248 | pbn_b1_4_921600 }, |
4246 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4249 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4247 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4250 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4248 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, | 4251 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, |
4249 | pbn_b1_4_921600 }, | 4252 | pbn_b1_4_921600 }, |
4250 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4253 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4251 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4254 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4252 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, | 4255 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, |
4253 | pbn_b1_2_921600 }, | 4256 | pbn_b1_2_921600 }, |
4254 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4257 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4255 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4258 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4256 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, | 4259 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, |
4257 | pbn_b1_8_921600 }, | 4260 | pbn_b1_8_921600 }, |
4258 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4261 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4259 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4262 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4260 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, | 4263 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, |
4261 | pbn_b1_8_921600 }, | 4264 | pbn_b1_8_921600 }, |
4262 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4265 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4263 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4266 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4264 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, | 4267 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, |
4265 | pbn_b1_4_921600 }, | 4268 | pbn_b1_4_921600 }, |
4266 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | 4269 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
4267 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4270 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4268 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, | 4271 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, |
4269 | pbn_b1_2_1250000 }, | 4272 | pbn_b1_2_1250000 }, |
4270 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | 4273 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4271 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4274 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4272 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, | 4275 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, |
4273 | pbn_b0_2_1843200 }, | 4276 | pbn_b0_2_1843200 }, |
4274 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | 4277 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4275 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4278 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4276 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, | 4279 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, |
4277 | pbn_b0_4_1843200 }, | 4280 | pbn_b0_4_1843200 }, |
4278 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | 4281 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4279 | PCI_VENDOR_ID_AFAVLAB, | 4282 | PCI_VENDOR_ID_AFAVLAB, |
4280 | PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, | 4283 | PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, |
4281 | pbn_b0_4_1152000 }, | 4284 | pbn_b0_4_1152000 }, |
4282 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | 4285 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
4283 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4286 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4284 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, | 4287 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, |
4285 | pbn_b0_2_1843200_200 }, | 4288 | pbn_b0_2_1843200_200 }, |
4286 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | 4289 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
4287 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4290 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4288 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, | 4291 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, |
4289 | pbn_b0_4_1843200_200 }, | 4292 | pbn_b0_4_1843200_200 }, |
4290 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | 4293 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
4291 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4294 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4292 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, | 4295 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, |
4293 | pbn_b0_8_1843200_200 }, | 4296 | pbn_b0_8_1843200_200 }, |
4294 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | 4297 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
4295 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4298 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4296 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, | 4299 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, |
4297 | pbn_b0_2_1843200_200 }, | 4300 | pbn_b0_2_1843200_200 }, |
4298 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | 4301 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
4299 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4302 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4300 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, | 4303 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, |
4301 | pbn_b0_4_1843200_200 }, | 4304 | pbn_b0_4_1843200_200 }, |
4302 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | 4305 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
4303 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4306 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4304 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, | 4307 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, |
4305 | pbn_b0_8_1843200_200 }, | 4308 | pbn_b0_8_1843200_200 }, |
4306 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | 4309 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
4307 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4310 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4308 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, | 4311 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, |
4309 | pbn_b0_2_1843200_200 }, | 4312 | pbn_b0_2_1843200_200 }, |
4310 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | 4313 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
4311 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4314 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4312 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, | 4315 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, |
4313 | pbn_b0_4_1843200_200 }, | 4316 | pbn_b0_4_1843200_200 }, |
4314 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | 4317 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
4315 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4318 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4316 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, | 4319 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, |
4317 | pbn_b0_8_1843200_200 }, | 4320 | pbn_b0_8_1843200_200 }, |
4318 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | 4321 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
4319 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4322 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4320 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, | 4323 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, |
4321 | pbn_b0_2_1843200_200 }, | 4324 | pbn_b0_2_1843200_200 }, |
4322 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | 4325 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
4323 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4326 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4324 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, | 4327 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, |
4325 | pbn_b0_4_1843200_200 }, | 4328 | pbn_b0_4_1843200_200 }, |
4326 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | 4329 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
4327 | PCI_SUBVENDOR_ID_CONNECT_TECH, | 4330 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
4328 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, | 4331 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, |
4329 | pbn_b0_8_1843200_200 }, | 4332 | pbn_b0_8_1843200_200 }, |
4330 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | 4333 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
4331 | PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, | 4334 | PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, |
4332 | 0, 0, pbn_exar_ibm_saturn }, | 4335 | 0, 0, pbn_exar_ibm_saturn }, |
4333 | 4336 | ||
4334 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, | 4337 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, |
4335 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4338 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4336 | pbn_b2_bt_1_115200 }, | 4339 | pbn_b2_bt_1_115200 }, |
4337 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, | 4340 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, |
4338 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4341 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4339 | pbn_b2_bt_2_115200 }, | 4342 | pbn_b2_bt_2_115200 }, |
4340 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, | 4343 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, |
4341 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4344 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4342 | pbn_b2_bt_4_115200 }, | 4345 | pbn_b2_bt_4_115200 }, |
4343 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, | 4346 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, |
4344 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4347 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4345 | pbn_b2_bt_2_115200 }, | 4348 | pbn_b2_bt_2_115200 }, |
4346 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, | 4349 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, |
4347 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4350 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4348 | pbn_b2_bt_4_115200 }, | 4351 | pbn_b2_bt_4_115200 }, |
4349 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, | 4352 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, |
4350 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4353 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4351 | pbn_b2_8_115200 }, | 4354 | pbn_b2_8_115200 }, |
4352 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, | 4355 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, |
4353 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4356 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4354 | pbn_b2_8_460800 }, | 4357 | pbn_b2_8_460800 }, |
4355 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, | 4358 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, |
4356 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4359 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4357 | pbn_b2_8_115200 }, | 4360 | pbn_b2_8_115200 }, |
4358 | 4361 | ||
4359 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, | 4362 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, |
4360 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4363 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4361 | pbn_b2_bt_2_115200 }, | 4364 | pbn_b2_bt_2_115200 }, |
4362 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, | 4365 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, |
4363 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4366 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4364 | pbn_b2_bt_2_921600 }, | 4367 | pbn_b2_bt_2_921600 }, |
4365 | /* | 4368 | /* |
4366 | * VScom SPCOM800, from sl@s.pl | 4369 | * VScom SPCOM800, from sl@s.pl |
4367 | */ | 4370 | */ |
4368 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, | 4371 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, |
4369 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4372 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4370 | pbn_b2_8_921600 }, | 4373 | pbn_b2_8_921600 }, |
4371 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, | 4374 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, |
4372 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4375 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4373 | pbn_b2_4_921600 }, | 4376 | pbn_b2_4_921600 }, |
4374 | /* Unknown card - subdevice 0x1584 */ | 4377 | /* Unknown card - subdevice 0x1584 */ |
4375 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4378 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4376 | PCI_VENDOR_ID_PLX, | 4379 | PCI_VENDOR_ID_PLX, |
4377 | PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, | 4380 | PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, |
4378 | pbn_b2_4_115200 }, | 4381 | pbn_b2_4_115200 }, |
4379 | /* Unknown card - subdevice 0x1588 */ | 4382 | /* Unknown card - subdevice 0x1588 */ |
4380 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4383 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4381 | PCI_VENDOR_ID_PLX, | 4384 | PCI_VENDOR_ID_PLX, |
4382 | PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, | 4385 | PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, |
4383 | pbn_b2_8_115200 }, | 4386 | pbn_b2_8_115200 }, |
4384 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4387 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4385 | PCI_SUBVENDOR_ID_KEYSPAN, | 4388 | PCI_SUBVENDOR_ID_KEYSPAN, |
4386 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, | 4389 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, |
4387 | pbn_panacom }, | 4390 | pbn_panacom }, |
4388 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, | 4391 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, |
4389 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4392 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4390 | pbn_panacom4 }, | 4393 | pbn_panacom4 }, |
4391 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, | 4394 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, |
4392 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4395 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4393 | pbn_panacom2 }, | 4396 | pbn_panacom2 }, |
4394 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | 4397 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
4395 | PCI_VENDOR_ID_ESDGMBH, | 4398 | PCI_VENDOR_ID_ESDGMBH, |
4396 | PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, | 4399 | PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, |
4397 | pbn_b2_4_115200 }, | 4400 | pbn_b2_4_115200 }, |
4398 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4401 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4399 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | 4402 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
4400 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, | 4403 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, |
4401 | pbn_b2_4_460800 }, | 4404 | pbn_b2_4_460800 }, |
4402 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4405 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4403 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | 4406 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
4404 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, | 4407 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, |
4405 | pbn_b2_8_460800 }, | 4408 | pbn_b2_8_460800 }, |
4406 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4409 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4407 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | 4410 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
4408 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, | 4411 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, |
4409 | pbn_b2_16_460800 }, | 4412 | pbn_b2_16_460800 }, |
4410 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4413 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4411 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | 4414 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
4412 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, | 4415 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, |
4413 | pbn_b2_16_460800 }, | 4416 | pbn_b2_16_460800 }, |
4414 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4417 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4415 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | 4418 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, |
4416 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, | 4419 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, |
4417 | pbn_b2_4_460800 }, | 4420 | pbn_b2_4_460800 }, |
4418 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4421 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4419 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | 4422 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, |
4420 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, | 4423 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, |
4421 | pbn_b2_8_460800 }, | 4424 | pbn_b2_8_460800 }, |
4422 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | 4425 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
4423 | PCI_SUBVENDOR_ID_EXSYS, | 4426 | PCI_SUBVENDOR_ID_EXSYS, |
4424 | PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, | 4427 | PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, |
4425 | pbn_b2_4_115200 }, | 4428 | pbn_b2_4_115200 }, |
4426 | /* | 4429 | /* |
4427 | * Megawolf Romulus PCI Serial Card, from Mike Hudson | 4430 | * Megawolf Romulus PCI Serial Card, from Mike Hudson |
4428 | * (Exoray@isys.ca) | 4431 | * (Exoray@isys.ca) |
4429 | */ | 4432 | */ |
4430 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, | 4433 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, |
4431 | 0x10b5, 0x106a, 0, 0, | 4434 | 0x10b5, 0x106a, 0, 0, |
4432 | pbn_plx_romulus }, | 4435 | pbn_plx_romulus }, |
4433 | /* | 4436 | /* |
4434 | * EndRun Technologies. PCI express device range. | 4437 | * EndRun Technologies. PCI express device range. |
4435 | * EndRun PTP/1588 has 2 Native UARTs. | 4438 | * EndRun PTP/1588 has 2 Native UARTs. |
4436 | */ | 4439 | */ |
4437 | { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, | 4440 | { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, |
4438 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4441 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4439 | pbn_endrun_2_4000000 }, | 4442 | pbn_endrun_2_4000000 }, |
4440 | /* | 4443 | /* |
4441 | * Quatech cards. These actually have configurable clocks but for | 4444 | * Quatech cards. These actually have configurable clocks but for |
4442 | * now we just use the default. | 4445 | * now we just use the default. |
4443 | * | 4446 | * |
4444 | * 100 series are RS232, 200 series RS422, | 4447 | * 100 series are RS232, 200 series RS422, |
4445 | */ | 4448 | */ |
4446 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, | 4449 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, |
4447 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4450 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4448 | pbn_b1_4_115200 }, | 4451 | pbn_b1_4_115200 }, |
4449 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, | 4452 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, |
4450 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4453 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4451 | pbn_b1_2_115200 }, | 4454 | pbn_b1_2_115200 }, |
4452 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, | 4455 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, |
4453 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4456 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4454 | pbn_b2_2_115200 }, | 4457 | pbn_b2_2_115200 }, |
4455 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, | 4458 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, |
4456 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4459 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4457 | pbn_b1_2_115200 }, | 4460 | pbn_b1_2_115200 }, |
4458 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, | 4461 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, |
4459 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4462 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4460 | pbn_b2_2_115200 }, | 4463 | pbn_b2_2_115200 }, |
4461 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, | 4464 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, |
4462 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4465 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4463 | pbn_b1_4_115200 }, | 4466 | pbn_b1_4_115200 }, |
4464 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, | 4467 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, |
4465 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4468 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4466 | pbn_b1_8_115200 }, | 4469 | pbn_b1_8_115200 }, |
4467 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, | 4470 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, |
4468 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4471 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4469 | pbn_b1_8_115200 }, | 4472 | pbn_b1_8_115200 }, |
4470 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, | 4473 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, |
4471 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4474 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4472 | pbn_b1_4_115200 }, | 4475 | pbn_b1_4_115200 }, |
4473 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, | 4476 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, |
4474 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4477 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4475 | pbn_b1_2_115200 }, | 4478 | pbn_b1_2_115200 }, |
4476 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, | 4479 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, |
4477 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4480 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4478 | pbn_b1_4_115200 }, | 4481 | pbn_b1_4_115200 }, |
4479 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, | 4482 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, |
4480 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4483 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4481 | pbn_b1_2_115200 }, | 4484 | pbn_b1_2_115200 }, |
4482 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, | 4485 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, |
4483 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4486 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4484 | pbn_b2_4_115200 }, | 4487 | pbn_b2_4_115200 }, |
4485 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, | 4488 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, |
4486 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4489 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4487 | pbn_b2_2_115200 }, | 4490 | pbn_b2_2_115200 }, |
4488 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, | 4491 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, |
4489 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4492 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4490 | pbn_b2_1_115200 }, | 4493 | pbn_b2_1_115200 }, |
4491 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, | 4494 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, |
4492 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4495 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4493 | pbn_b2_4_115200 }, | 4496 | pbn_b2_4_115200 }, |
4494 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, | 4497 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, |
4495 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4498 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4496 | pbn_b2_2_115200 }, | 4499 | pbn_b2_2_115200 }, |
4497 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, | 4500 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, |
4498 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4501 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4499 | pbn_b2_1_115200 }, | 4502 | pbn_b2_1_115200 }, |
4500 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, | 4503 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, |
4501 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4504 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4502 | pbn_b0_8_115200 }, | 4505 | pbn_b0_8_115200 }, |
4503 | 4506 | ||
4504 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, | 4507 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4505 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, | 4508 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, |
4506 | 0, 0, | 4509 | 0, 0, |
4507 | pbn_b0_4_921600 }, | 4510 | pbn_b0_4_921600 }, |
4508 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | 4511 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4509 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, | 4512 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, |
4510 | 0, 0, | 4513 | 0, 0, |
4511 | pbn_b0_4_1152000 }, | 4514 | pbn_b0_4_1152000 }, |
4512 | { PCI_VENDOR_ID_OXSEMI, 0x9505, | 4515 | { PCI_VENDOR_ID_OXSEMI, 0x9505, |
4513 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4516 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4514 | pbn_b0_bt_2_921600 }, | 4517 | pbn_b0_bt_2_921600 }, |
4515 | 4518 | ||
4516 | /* | 4519 | /* |
4517 | * The below card is a little controversial since it is the | 4520 | * The below card is a little controversial since it is the |
4518 | * subject of a PCI vendor/device ID clash. (See | 4521 | * subject of a PCI vendor/device ID clash. (See |
4519 | * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). | 4522 | * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). |
4520 | * For now just used the hex ID 0x950a. | 4523 | * For now just used the hex ID 0x950a. |
4521 | */ | 4524 | */ |
4522 | { PCI_VENDOR_ID_OXSEMI, 0x950a, | 4525 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
4523 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, | 4526 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, |
4524 | 0, 0, pbn_b0_2_115200 }, | 4527 | 0, 0, pbn_b0_2_115200 }, |
4525 | { PCI_VENDOR_ID_OXSEMI, 0x950a, | 4528 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
4526 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, | 4529 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, |
4527 | 0, 0, pbn_b0_2_115200 }, | 4530 | 0, 0, pbn_b0_2_115200 }, |
4528 | { PCI_VENDOR_ID_OXSEMI, 0x950a, | 4531 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
4529 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4532 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4530 | pbn_b0_2_1130000 }, | 4533 | pbn_b0_2_1130000 }, |
4531 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, | 4534 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, |
4532 | PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, | 4535 | PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, |
4533 | pbn_b0_1_921600 }, | 4536 | pbn_b0_1_921600 }, |
4534 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | 4537 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4535 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4538 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4536 | pbn_b0_4_115200 }, | 4539 | pbn_b0_4_115200 }, |
4537 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, | 4540 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, |
4538 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4541 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4539 | pbn_b0_bt_2_921600 }, | 4542 | pbn_b0_bt_2_921600 }, |
4540 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, | 4543 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, |
4541 | PCI_ANY_ID , PCI_ANY_ID, 0, 0, | 4544 | PCI_ANY_ID , PCI_ANY_ID, 0, 0, |
4542 | pbn_b2_8_1152000 }, | 4545 | pbn_b2_8_1152000 }, |
4543 | 4546 | ||
4544 | /* | 4547 | /* |
4545 | * Oxford Semiconductor Inc. Tornado PCI express device range. | 4548 | * Oxford Semiconductor Inc. Tornado PCI express device range. |
4546 | */ | 4549 | */ |
4547 | { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ | 4550 | { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ |
4548 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4551 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4549 | pbn_b0_1_4000000 }, | 4552 | pbn_b0_1_4000000 }, |
4550 | { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ | 4553 | { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ |
4551 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4554 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4552 | pbn_b0_1_4000000 }, | 4555 | pbn_b0_1_4000000 }, |
4553 | { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ | 4556 | { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ |
4554 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4557 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4555 | pbn_oxsemi_1_4000000 }, | 4558 | pbn_oxsemi_1_4000000 }, |
4556 | { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ | 4559 | { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ |
4557 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4560 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4558 | pbn_oxsemi_1_4000000 }, | 4561 | pbn_oxsemi_1_4000000 }, |
4559 | { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ | 4562 | { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ |
4560 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4563 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4561 | pbn_b0_1_4000000 }, | 4564 | pbn_b0_1_4000000 }, |
4562 | { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ | 4565 | { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ |
4563 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4566 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4564 | pbn_b0_1_4000000 }, | 4567 | pbn_b0_1_4000000 }, |
4565 | { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ | 4568 | { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ |
4566 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4569 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4567 | pbn_oxsemi_1_4000000 }, | 4570 | pbn_oxsemi_1_4000000 }, |
4568 | { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ | 4571 | { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ |
4569 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4572 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4570 | pbn_oxsemi_1_4000000 }, | 4573 | pbn_oxsemi_1_4000000 }, |
4571 | { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ | 4574 | { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ |
4572 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4575 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4573 | pbn_b0_1_4000000 }, | 4576 | pbn_b0_1_4000000 }, |
4574 | { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ | 4577 | { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ |
4575 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4578 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4576 | pbn_b0_1_4000000 }, | 4579 | pbn_b0_1_4000000 }, |
4577 | { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ | 4580 | { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ |
4578 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4581 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4579 | pbn_b0_1_4000000 }, | 4582 | pbn_b0_1_4000000 }, |
4580 | { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ | 4583 | { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ |
4581 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4584 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4582 | pbn_b0_1_4000000 }, | 4585 | pbn_b0_1_4000000 }, |
4583 | { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ | 4586 | { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ |
4584 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4587 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4585 | pbn_oxsemi_2_4000000 }, | 4588 | pbn_oxsemi_2_4000000 }, |
4586 | { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ | 4589 | { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ |
4587 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4590 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4588 | pbn_oxsemi_2_4000000 }, | 4591 | pbn_oxsemi_2_4000000 }, |
4589 | { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ | 4592 | { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ |
4590 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4593 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4591 | pbn_oxsemi_4_4000000 }, | 4594 | pbn_oxsemi_4_4000000 }, |
4592 | { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ | 4595 | { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ |
4593 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4596 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4594 | pbn_oxsemi_4_4000000 }, | 4597 | pbn_oxsemi_4_4000000 }, |
4595 | { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ | 4598 | { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ |
4596 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4599 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4597 | pbn_oxsemi_8_4000000 }, | 4600 | pbn_oxsemi_8_4000000 }, |
4598 | { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ | 4601 | { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ |
4599 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4602 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4600 | pbn_oxsemi_8_4000000 }, | 4603 | pbn_oxsemi_8_4000000 }, |
4601 | { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ | 4604 | { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ |
4602 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4605 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4603 | pbn_oxsemi_1_4000000 }, | 4606 | pbn_oxsemi_1_4000000 }, |
4604 | { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ | 4607 | { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ |
4605 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4608 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4606 | pbn_oxsemi_1_4000000 }, | 4609 | pbn_oxsemi_1_4000000 }, |
4607 | { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ | 4610 | { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ |
4608 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4611 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4609 | pbn_oxsemi_1_4000000 }, | 4612 | pbn_oxsemi_1_4000000 }, |
4610 | { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ | 4613 | { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ |
4611 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4614 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4612 | pbn_oxsemi_1_4000000 }, | 4615 | pbn_oxsemi_1_4000000 }, |
4613 | { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ | 4616 | { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ |
4614 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4617 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4615 | pbn_oxsemi_1_4000000 }, | 4618 | pbn_oxsemi_1_4000000 }, |
4616 | { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ | 4619 | { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ |
4617 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4620 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4618 | pbn_oxsemi_1_4000000 }, | 4621 | pbn_oxsemi_1_4000000 }, |
4619 | { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ | 4622 | { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ |
4620 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4623 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4621 | pbn_oxsemi_1_4000000 }, | 4624 | pbn_oxsemi_1_4000000 }, |
4622 | { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ | 4625 | { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ |
4623 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4626 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4624 | pbn_oxsemi_1_4000000 }, | 4627 | pbn_oxsemi_1_4000000 }, |
4625 | { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ | 4628 | { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ |
4626 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4629 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4627 | pbn_oxsemi_1_4000000 }, | 4630 | pbn_oxsemi_1_4000000 }, |
4628 | { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ | 4631 | { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ |
4629 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4632 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4630 | pbn_oxsemi_1_4000000 }, | 4633 | pbn_oxsemi_1_4000000 }, |
4631 | { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ | 4634 | { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ |
4632 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4635 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4633 | pbn_oxsemi_1_4000000 }, | 4636 | pbn_oxsemi_1_4000000 }, |
4634 | { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ | 4637 | { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ |
4635 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4638 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4636 | pbn_oxsemi_1_4000000 }, | 4639 | pbn_oxsemi_1_4000000 }, |
4637 | { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ | 4640 | { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ |
4638 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4641 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4639 | pbn_oxsemi_1_4000000 }, | 4642 | pbn_oxsemi_1_4000000 }, |
4640 | { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ | 4643 | { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ |
4641 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4644 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4642 | pbn_oxsemi_1_4000000 }, | 4645 | pbn_oxsemi_1_4000000 }, |
4643 | { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ | 4646 | { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ |
4644 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4647 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4645 | pbn_oxsemi_1_4000000 }, | 4648 | pbn_oxsemi_1_4000000 }, |
4646 | { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ | 4649 | { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ |
4647 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4650 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4648 | pbn_oxsemi_1_4000000 }, | 4651 | pbn_oxsemi_1_4000000 }, |
4649 | { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ | 4652 | { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ |
4650 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4653 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4651 | pbn_oxsemi_1_4000000 }, | 4654 | pbn_oxsemi_1_4000000 }, |
4652 | { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ | 4655 | { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ |
4653 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4656 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4654 | pbn_oxsemi_1_4000000 }, | 4657 | pbn_oxsemi_1_4000000 }, |
4655 | { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ | 4658 | { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ |
4656 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4659 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4657 | pbn_oxsemi_1_4000000 }, | 4660 | pbn_oxsemi_1_4000000 }, |
4658 | { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ | 4661 | { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ |
4659 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4662 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4660 | pbn_oxsemi_1_4000000 }, | 4663 | pbn_oxsemi_1_4000000 }, |
4661 | { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ | 4664 | { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ |
4662 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4665 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4663 | pbn_oxsemi_1_4000000 }, | 4666 | pbn_oxsemi_1_4000000 }, |
4664 | { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ | 4667 | { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ |
4665 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4668 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4666 | pbn_oxsemi_1_4000000 }, | 4669 | pbn_oxsemi_1_4000000 }, |
4667 | { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ | 4670 | { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ |
4668 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4671 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4669 | pbn_oxsemi_1_4000000 }, | 4672 | pbn_oxsemi_1_4000000 }, |
4670 | { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ | 4673 | { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ |
4671 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4674 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4672 | pbn_oxsemi_1_4000000 }, | 4675 | pbn_oxsemi_1_4000000 }, |
4673 | { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ | 4676 | { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ |
4674 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4677 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4675 | pbn_oxsemi_1_4000000 }, | 4678 | pbn_oxsemi_1_4000000 }, |
4676 | { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ | 4679 | { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ |
4677 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4680 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4678 | pbn_oxsemi_1_4000000 }, | 4681 | pbn_oxsemi_1_4000000 }, |
4679 | /* | 4682 | /* |
4680 | * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado | 4683 | * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado |
4681 | */ | 4684 | */ |
4682 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ | 4685 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ |
4683 | PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, | 4686 | PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, |
4684 | pbn_oxsemi_1_4000000 }, | 4687 | pbn_oxsemi_1_4000000 }, |
4685 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ | 4688 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ |
4686 | PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, | 4689 | PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, |
4687 | pbn_oxsemi_2_4000000 }, | 4690 | pbn_oxsemi_2_4000000 }, |
4688 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ | 4691 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ |
4689 | PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, | 4692 | PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, |
4690 | pbn_oxsemi_4_4000000 }, | 4693 | pbn_oxsemi_4_4000000 }, |
4691 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ | 4694 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ |
4692 | PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, | 4695 | PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, |
4693 | pbn_oxsemi_8_4000000 }, | 4696 | pbn_oxsemi_8_4000000 }, |
4694 | 4697 | ||
4695 | /* | 4698 | /* |
4696 | * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado | 4699 | * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado |
4697 | */ | 4700 | */ |
4698 | { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, | 4701 | { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, |
4699 | PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, | 4702 | PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, |
4700 | pbn_oxsemi_2_4000000 }, | 4703 | pbn_oxsemi_2_4000000 }, |
4701 | 4704 | ||
4702 | /* | 4705 | /* |
4703 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, | 4706 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, |
4704 | * from skokodyn@yahoo.com | 4707 | * from skokodyn@yahoo.com |
4705 | */ | 4708 | */ |
4706 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | 4709 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
4707 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, | 4710 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, |
4708 | pbn_sbsxrsio }, | 4711 | pbn_sbsxrsio }, |
4709 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | 4712 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
4710 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, | 4713 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, |
4711 | pbn_sbsxrsio }, | 4714 | pbn_sbsxrsio }, |
4712 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | 4715 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
4713 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, | 4716 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, |
4714 | pbn_sbsxrsio }, | 4717 | pbn_sbsxrsio }, |
4715 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | 4718 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
4716 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, | 4719 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, |
4717 | pbn_sbsxrsio }, | 4720 | pbn_sbsxrsio }, |
4718 | 4721 | ||
4719 | /* | 4722 | /* |
4720 | * Digitan DS560-558, from jimd@esoft.com | 4723 | * Digitan DS560-558, from jimd@esoft.com |
4721 | */ | 4724 | */ |
4722 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, | 4725 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, |
4723 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4726 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4724 | pbn_b1_1_115200 }, | 4727 | pbn_b1_1_115200 }, |
4725 | 4728 | ||
4726 | /* | 4729 | /* |
4727 | * Titan Electronic cards | 4730 | * Titan Electronic cards |
4728 | * The 400L and 800L have a custom setup quirk. | 4731 | * The 400L and 800L have a custom setup quirk. |
4729 | */ | 4732 | */ |
4730 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, | 4733 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, |
4731 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4734 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4732 | pbn_b0_1_921600 }, | 4735 | pbn_b0_1_921600 }, |
4733 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, | 4736 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, |
4734 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4737 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4735 | pbn_b0_2_921600 }, | 4738 | pbn_b0_2_921600 }, |
4736 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, | 4739 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, |
4737 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4740 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4738 | pbn_b0_4_921600 }, | 4741 | pbn_b0_4_921600 }, |
4739 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, | 4742 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, |
4740 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4743 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4741 | pbn_b0_4_921600 }, | 4744 | pbn_b0_4_921600 }, |
4742 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, | 4745 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, |
4743 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4746 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4744 | pbn_b1_1_921600 }, | 4747 | pbn_b1_1_921600 }, |
4745 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, | 4748 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, |
4746 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4749 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4747 | pbn_b1_bt_2_921600 }, | 4750 | pbn_b1_bt_2_921600 }, |
4748 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, | 4751 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, |
4749 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4752 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4750 | pbn_b0_bt_4_921600 }, | 4753 | pbn_b0_bt_4_921600 }, |
4751 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, | 4754 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, |
4752 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4755 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4753 | pbn_b0_bt_8_921600 }, | 4756 | pbn_b0_bt_8_921600 }, |
4754 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, | 4757 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, |
4755 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4758 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4756 | pbn_b4_bt_2_921600 }, | 4759 | pbn_b4_bt_2_921600 }, |
4757 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, | 4760 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, |
4758 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4761 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4759 | pbn_b4_bt_4_921600 }, | 4762 | pbn_b4_bt_4_921600 }, |
4760 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, | 4763 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, |
4761 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4764 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4762 | pbn_b4_bt_8_921600 }, | 4765 | pbn_b4_bt_8_921600 }, |
4763 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, | 4766 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, |
4764 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4767 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4765 | pbn_b0_4_921600 }, | 4768 | pbn_b0_4_921600 }, |
4766 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, | 4769 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, |
4767 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4770 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4768 | pbn_b0_4_921600 }, | 4771 | pbn_b0_4_921600 }, |
4769 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, | 4772 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, |
4770 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4773 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4771 | pbn_b0_4_921600 }, | 4774 | pbn_b0_4_921600 }, |
4772 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, | 4775 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, |
4773 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4776 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4774 | pbn_oxsemi_1_4000000 }, | 4777 | pbn_oxsemi_1_4000000 }, |
4775 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, | 4778 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, |
4776 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4779 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4777 | pbn_oxsemi_2_4000000 }, | 4780 | pbn_oxsemi_2_4000000 }, |
4778 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, | 4781 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, |
4779 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4782 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4780 | pbn_oxsemi_4_4000000 }, | 4783 | pbn_oxsemi_4_4000000 }, |
4781 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, | 4784 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, |
4782 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4785 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4783 | pbn_oxsemi_8_4000000 }, | 4786 | pbn_oxsemi_8_4000000 }, |
4784 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, | 4787 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, |
4785 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4788 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4786 | pbn_oxsemi_2_4000000 }, | 4789 | pbn_oxsemi_2_4000000 }, |
4787 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, | 4790 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, |
4788 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4791 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4789 | pbn_oxsemi_2_4000000 }, | 4792 | pbn_oxsemi_2_4000000 }, |
4790 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, | 4793 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, |
4791 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4794 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4792 | pbn_b0_bt_2_921600 }, | 4795 | pbn_b0_bt_2_921600 }, |
4793 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, | 4796 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, |
4794 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4797 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4795 | pbn_b0_4_921600 }, | 4798 | pbn_b0_4_921600 }, |
4796 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, | 4799 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, |
4797 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4800 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4798 | pbn_b0_4_921600 }, | 4801 | pbn_b0_4_921600 }, |
4799 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, | 4802 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, |
4800 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4803 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4801 | pbn_b0_4_921600 }, | 4804 | pbn_b0_4_921600 }, |
4802 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, | 4805 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, |
4803 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4806 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4804 | pbn_b0_4_921600 }, | 4807 | pbn_b0_4_921600 }, |
4805 | 4808 | ||
4806 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, | 4809 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, |
4807 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4810 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4808 | pbn_b2_1_460800 }, | 4811 | pbn_b2_1_460800 }, |
4809 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, | 4812 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, |
4810 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4813 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4811 | pbn_b2_1_460800 }, | 4814 | pbn_b2_1_460800 }, |
4812 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, | 4815 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, |
4813 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4816 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4814 | pbn_b2_1_460800 }, | 4817 | pbn_b2_1_460800 }, |
4815 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, | 4818 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, |
4816 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4819 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4817 | pbn_b2_bt_2_921600 }, | 4820 | pbn_b2_bt_2_921600 }, |
4818 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, | 4821 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, |
4819 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4822 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4820 | pbn_b2_bt_2_921600 }, | 4823 | pbn_b2_bt_2_921600 }, |
4821 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, | 4824 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, |
4822 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4825 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4823 | pbn_b2_bt_2_921600 }, | 4826 | pbn_b2_bt_2_921600 }, |
4824 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, | 4827 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, |
4825 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4828 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4826 | pbn_b2_bt_4_921600 }, | 4829 | pbn_b2_bt_4_921600 }, |
4827 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, | 4830 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, |
4828 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4831 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4829 | pbn_b2_bt_4_921600 }, | 4832 | pbn_b2_bt_4_921600 }, |
4830 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, | 4833 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, |
4831 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4834 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4832 | pbn_b2_bt_4_921600 }, | 4835 | pbn_b2_bt_4_921600 }, |
4833 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, | 4836 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, |
4834 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4837 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4835 | pbn_b0_1_921600 }, | 4838 | pbn_b0_1_921600 }, |
4836 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, | 4839 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, |
4837 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4840 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4838 | pbn_b0_1_921600 }, | 4841 | pbn_b0_1_921600 }, |
4839 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, | 4842 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, |
4840 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4843 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4841 | pbn_b0_1_921600 }, | 4844 | pbn_b0_1_921600 }, |
4842 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, | 4845 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, |
4843 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4846 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4844 | pbn_b0_bt_2_921600 }, | 4847 | pbn_b0_bt_2_921600 }, |
4845 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, | 4848 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, |
4846 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4849 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4847 | pbn_b0_bt_2_921600 }, | 4850 | pbn_b0_bt_2_921600 }, |
4848 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, | 4851 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, |
4849 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4852 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4850 | pbn_b0_bt_2_921600 }, | 4853 | pbn_b0_bt_2_921600 }, |
4851 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, | 4854 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, |
4852 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4855 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4853 | pbn_b0_bt_4_921600 }, | 4856 | pbn_b0_bt_4_921600 }, |
4854 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, | 4857 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, |
4855 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4858 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4856 | pbn_b0_bt_4_921600 }, | 4859 | pbn_b0_bt_4_921600 }, |
4857 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, | 4860 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, |
4858 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4861 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4859 | pbn_b0_bt_4_921600 }, | 4862 | pbn_b0_bt_4_921600 }, |
4860 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, | 4863 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, |
4861 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4864 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4862 | pbn_b0_bt_8_921600 }, | 4865 | pbn_b0_bt_8_921600 }, |
4863 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, | 4866 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, |
4864 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4867 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4865 | pbn_b0_bt_8_921600 }, | 4868 | pbn_b0_bt_8_921600 }, |
4866 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, | 4869 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, |
4867 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4870 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4868 | pbn_b0_bt_8_921600 }, | 4871 | pbn_b0_bt_8_921600 }, |
4869 | 4872 | ||
4870 | /* | 4873 | /* |
4871 | * Computone devices submitted by Doug McNash dmcnash@computone.com | 4874 | * Computone devices submitted by Doug McNash dmcnash@computone.com |
4872 | */ | 4875 | */ |
4873 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | 4876 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, |
4874 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, | 4877 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, |
4875 | 0, 0, pbn_computone_4 }, | 4878 | 0, 0, pbn_computone_4 }, |
4876 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | 4879 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, |
4877 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, | 4880 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, |
4878 | 0, 0, pbn_computone_8 }, | 4881 | 0, 0, pbn_computone_8 }, |
4879 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | 4882 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, |
4880 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, | 4883 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, |
4881 | 0, 0, pbn_computone_6 }, | 4884 | 0, 0, pbn_computone_6 }, |
4882 | 4885 | ||
4883 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, | 4886 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, |
4884 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4887 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4885 | pbn_oxsemi }, | 4888 | pbn_oxsemi }, |
4886 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, | 4889 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, |
4887 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, | 4890 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, |
4888 | pbn_b0_bt_1_921600 }, | 4891 | pbn_b0_bt_1_921600 }, |
4889 | 4892 | ||
4890 | /* | 4893 | /* |
4891 | * SUNIX (TIMEDIA) | 4894 | * SUNIX (TIMEDIA) |
4892 | */ | 4895 | */ |
4893 | { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, | 4896 | { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, |
4894 | PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, | 4897 | PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, |
4895 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, | 4898 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, |
4896 | pbn_b0_bt_1_921600 }, | 4899 | pbn_b0_bt_1_921600 }, |
4897 | 4900 | ||
4898 | { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, | 4901 | { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, |
4899 | PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, | 4902 | PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, |
4900 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, | 4903 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, |
4901 | pbn_b0_bt_1_921600 }, | 4904 | pbn_b0_bt_1_921600 }, |
4902 | 4905 | ||
4903 | /* | 4906 | /* |
4904 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> | 4907 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> |
4905 | */ | 4908 | */ |
4906 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, | 4909 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, |
4907 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4910 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4908 | pbn_b0_bt_8_115200 }, | 4911 | pbn_b0_bt_8_115200 }, |
4909 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, | 4912 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, |
4910 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4913 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4911 | pbn_b0_bt_8_115200 }, | 4914 | pbn_b0_bt_8_115200 }, |
4912 | 4915 | ||
4913 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, | 4916 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, |
4914 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4917 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4915 | pbn_b0_bt_2_115200 }, | 4918 | pbn_b0_bt_2_115200 }, |
4916 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, | 4919 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, |
4917 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4920 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4918 | pbn_b0_bt_2_115200 }, | 4921 | pbn_b0_bt_2_115200 }, |
4919 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, | 4922 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, |
4920 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4923 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4921 | pbn_b0_bt_2_115200 }, | 4924 | pbn_b0_bt_2_115200 }, |
4922 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, | 4925 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, |
4923 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4926 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4924 | pbn_b0_bt_2_115200 }, | 4927 | pbn_b0_bt_2_115200 }, |
4925 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, | 4928 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, |
4926 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4929 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4927 | pbn_b0_bt_2_115200 }, | 4930 | pbn_b0_bt_2_115200 }, |
4928 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, | 4931 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, |
4929 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4932 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4930 | pbn_b0_bt_4_460800 }, | 4933 | pbn_b0_bt_4_460800 }, |
4931 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, | 4934 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, |
4932 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4935 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4933 | pbn_b0_bt_4_460800 }, | 4936 | pbn_b0_bt_4_460800 }, |
4934 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, | 4937 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, |
4935 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4938 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4936 | pbn_b0_bt_2_460800 }, | 4939 | pbn_b0_bt_2_460800 }, |
4937 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, | 4940 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, |
4938 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4941 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4939 | pbn_b0_bt_2_460800 }, | 4942 | pbn_b0_bt_2_460800 }, |
4940 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, | 4943 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, |
4941 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4944 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4942 | pbn_b0_bt_2_460800 }, | 4945 | pbn_b0_bt_2_460800 }, |
4943 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, | 4946 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, |
4944 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4947 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4945 | pbn_b0_bt_1_115200 }, | 4948 | pbn_b0_bt_1_115200 }, |
4946 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, | 4949 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, |
4947 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4950 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4948 | pbn_b0_bt_1_460800 }, | 4951 | pbn_b0_bt_1_460800 }, |
4949 | 4952 | ||
4950 | /* | 4953 | /* |
4951 | * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). | 4954 | * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). |
4952 | * Cards are identified by their subsystem vendor IDs, which | 4955 | * Cards are identified by their subsystem vendor IDs, which |
4953 | * (in hex) match the model number. | 4956 | * (in hex) match the model number. |
4954 | * | 4957 | * |
4955 | * Note that JC140x are RS422/485 cards which require ox950 | 4958 | * Note that JC140x are RS422/485 cards which require ox950 |
4956 | * ACR = 0x10, and as such are not currently fully supported. | 4959 | * ACR = 0x10, and as such are not currently fully supported. |
4957 | */ | 4960 | */ |
4958 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | 4961 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
4959 | 0x1204, 0x0004, 0, 0, | 4962 | 0x1204, 0x0004, 0, 0, |
4960 | pbn_b0_4_921600 }, | 4963 | pbn_b0_4_921600 }, |
4961 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | 4964 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
4962 | 0x1208, 0x0004, 0, 0, | 4965 | 0x1208, 0x0004, 0, 0, |
4963 | pbn_b0_4_921600 }, | 4966 | pbn_b0_4_921600 }, |
4964 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | 4967 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
4965 | 0x1402, 0x0002, 0, 0, | 4968 | 0x1402, 0x0002, 0, 0, |
4966 | pbn_b0_2_921600 }, */ | 4969 | pbn_b0_2_921600 }, */ |
4967 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | 4970 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
4968 | 0x1404, 0x0004, 0, 0, | 4971 | 0x1404, 0x0004, 0, 0, |
4969 | pbn_b0_4_921600 }, */ | 4972 | pbn_b0_4_921600 }, */ |
4970 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, | 4973 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, |
4971 | 0x1208, 0x0004, 0, 0, | 4974 | 0x1208, 0x0004, 0, 0, |
4972 | pbn_b0_4_921600 }, | 4975 | pbn_b0_4_921600 }, |
4973 | 4976 | ||
4974 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, | 4977 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, |
4975 | 0x1204, 0x0004, 0, 0, | 4978 | 0x1204, 0x0004, 0, 0, |
4976 | pbn_b0_4_921600 }, | 4979 | pbn_b0_4_921600 }, |
4977 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, | 4980 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, |
4978 | 0x1208, 0x0004, 0, 0, | 4981 | 0x1208, 0x0004, 0, 0, |
4979 | pbn_b0_4_921600 }, | 4982 | pbn_b0_4_921600 }, |
4980 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, | 4983 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, |
4981 | 0x1208, 0x0004, 0, 0, | 4984 | 0x1208, 0x0004, 0, 0, |
4982 | pbn_b0_4_921600 }, | 4985 | pbn_b0_4_921600 }, |
4983 | /* | 4986 | /* |
4984 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com | 4987 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com |
4985 | */ | 4988 | */ |
4986 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, | 4989 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, |
4987 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4990 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4988 | pbn_b1_1_1382400 }, | 4991 | pbn_b1_1_1382400 }, |
4989 | 4992 | ||
4990 | /* | 4993 | /* |
4991 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com | 4994 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com |
4992 | */ | 4995 | */ |
4993 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, | 4996 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, |
4994 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 4997 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
4995 | pbn_b1_1_1382400 }, | 4998 | pbn_b1_1_1382400 }, |
4996 | 4999 | ||
4997 | /* | 5000 | /* |
4998 | * RAStel 2 port modem, gerg@moreton.com.au | 5001 | * RAStel 2 port modem, gerg@moreton.com.au |
4999 | */ | 5002 | */ |
5000 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, | 5003 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, |
5001 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5004 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5002 | pbn_b2_bt_2_115200 }, | 5005 | pbn_b2_bt_2_115200 }, |
5003 | 5006 | ||
5004 | /* | 5007 | /* |
5005 | * EKF addition for i960 Boards form EKF with serial port | 5008 | * EKF addition for i960 Boards form EKF with serial port |
5006 | */ | 5009 | */ |
5007 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, | 5010 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, |
5008 | 0xE4BF, PCI_ANY_ID, 0, 0, | 5011 | 0xE4BF, PCI_ANY_ID, 0, 0, |
5009 | pbn_intel_i960 }, | 5012 | pbn_intel_i960 }, |
5010 | 5013 | ||
5011 | /* | 5014 | /* |
5012 | * Xircom Cardbus/Ethernet combos | 5015 | * Xircom Cardbus/Ethernet combos |
5013 | */ | 5016 | */ |
5014 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, | 5017 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, |
5015 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5018 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5016 | pbn_b0_1_115200 }, | 5019 | pbn_b0_1_115200 }, |
5017 | /* | 5020 | /* |
5018 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) | 5021 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) |
5019 | */ | 5022 | */ |
5020 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, | 5023 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, |
5021 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5024 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5022 | pbn_b0_1_115200 }, | 5025 | pbn_b0_1_115200 }, |
5023 | 5026 | ||
5024 | /* | 5027 | /* |
5025 | * Untested PCI modems, sent in from various folks... | 5028 | * Untested PCI modems, sent in from various folks... |
5026 | */ | 5029 | */ |
5027 | 5030 | ||
5028 | /* | 5031 | /* |
5029 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> | 5032 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> |
5030 | */ | 5033 | */ |
5031 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, | 5034 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, |
5032 | 0x1048, 0x1500, 0, 0, | 5035 | 0x1048, 0x1500, 0, 0, |
5033 | pbn_b1_1_115200 }, | 5036 | pbn_b1_1_115200 }, |
5034 | 5037 | ||
5035 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, | 5038 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, |
5036 | 0xFF00, 0, 0, 0, | 5039 | 0xFF00, 0, 0, 0, |
5037 | pbn_sgi_ioc3 }, | 5040 | pbn_sgi_ioc3 }, |
5038 | 5041 | ||
5039 | /* | 5042 | /* |
5040 | * HP Diva card | 5043 | * HP Diva card |
5041 | */ | 5044 | */ |
5042 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | 5045 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, |
5043 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, | 5046 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, |
5044 | pbn_b1_1_115200 }, | 5047 | pbn_b1_1_115200 }, |
5045 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | 5048 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, |
5046 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5049 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5047 | pbn_b0_5_115200 }, | 5050 | pbn_b0_5_115200 }, |
5048 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, | 5051 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, |
5049 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5052 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5050 | pbn_b2_1_115200 }, | 5053 | pbn_b2_1_115200 }, |
5051 | 5054 | ||
5052 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, | 5055 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, |
5053 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5056 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5054 | pbn_b3_2_115200 }, | 5057 | pbn_b3_2_115200 }, |
5055 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, | 5058 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, |
5056 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5059 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5057 | pbn_b3_4_115200 }, | 5060 | pbn_b3_4_115200 }, |
5058 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, | 5061 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, |
5059 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5062 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5060 | pbn_b3_8_115200 }, | 5063 | pbn_b3_8_115200 }, |
5061 | 5064 | ||
5062 | /* | 5065 | /* |
5063 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | 5066 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART |
5064 | */ | 5067 | */ |
5065 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | 5068 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
5066 | PCI_ANY_ID, PCI_ANY_ID, | 5069 | PCI_ANY_ID, PCI_ANY_ID, |
5067 | 0, | 5070 | 0, |
5068 | 0, pbn_exar_XR17C152 }, | 5071 | 0, pbn_exar_XR17C152 }, |
5069 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | 5072 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
5070 | PCI_ANY_ID, PCI_ANY_ID, | 5073 | PCI_ANY_ID, PCI_ANY_ID, |
5071 | 0, | 5074 | 0, |
5072 | 0, pbn_exar_XR17C154 }, | 5075 | 0, pbn_exar_XR17C154 }, |
5073 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | 5076 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
5074 | PCI_ANY_ID, PCI_ANY_ID, | 5077 | PCI_ANY_ID, PCI_ANY_ID, |
5075 | 0, | 5078 | 0, |
5076 | 0, pbn_exar_XR17C158 }, | 5079 | 0, pbn_exar_XR17C158 }, |
5077 | /* | 5080 | /* |
5078 | * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs | 5081 | * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs |
5079 | */ | 5082 | */ |
5080 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, | 5083 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, |
5081 | PCI_ANY_ID, PCI_ANY_ID, | 5084 | PCI_ANY_ID, PCI_ANY_ID, |
5082 | 0, | 5085 | 0, |
5083 | 0, pbn_exar_XR17V352 }, | 5086 | 0, pbn_exar_XR17V352 }, |
5084 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, | 5087 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, |
5085 | PCI_ANY_ID, PCI_ANY_ID, | 5088 | PCI_ANY_ID, PCI_ANY_ID, |
5086 | 0, | 5089 | 0, |
5087 | 0, pbn_exar_XR17V354 }, | 5090 | 0, pbn_exar_XR17V354 }, |
5088 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, | 5091 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, |
5089 | PCI_ANY_ID, PCI_ANY_ID, | 5092 | PCI_ANY_ID, PCI_ANY_ID, |
5090 | 0, | 5093 | 0, |
5091 | 0, pbn_exar_XR17V358 }, | 5094 | 0, pbn_exar_XR17V358 }, |
5092 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358, | 5095 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358, |
5093 | PCI_ANY_ID, PCI_ANY_ID, | 5096 | PCI_ANY_ID, PCI_ANY_ID, |
5094 | 0, | 5097 | 0, |
5095 | 0, pbn_exar_XR17V4358 }, | 5098 | 0, pbn_exar_XR17V4358 }, |
5096 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358, | 5099 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358, |
5097 | PCI_ANY_ID, PCI_ANY_ID, | 5100 | PCI_ANY_ID, PCI_ANY_ID, |
5098 | 0, | 5101 | 0, |
5099 | 0, pbn_exar_XR17V8358 }, | 5102 | 0, pbn_exar_XR17V8358 }, |
5100 | /* | 5103 | /* |
5101 | * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART | 5104 | * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART |
5102 | */ | 5105 | */ |
5103 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, | 5106 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, |
5104 | PCI_ANY_ID, PCI_ANY_ID, | 5107 | PCI_ANY_ID, PCI_ANY_ID, |
5105 | 0, | 5108 | 0, |
5106 | 0, pbn_pericom_PI7C9X7951 }, | 5109 | 0, pbn_pericom_PI7C9X7951 }, |
5107 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, | 5110 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, |
5108 | PCI_ANY_ID, PCI_ANY_ID, | 5111 | PCI_ANY_ID, PCI_ANY_ID, |
5109 | 0, | 5112 | 0, |
5110 | 0, pbn_pericom_PI7C9X7952 }, | 5113 | 0, pbn_pericom_PI7C9X7952 }, |
5111 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, | 5114 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, |
5112 | PCI_ANY_ID, PCI_ANY_ID, | 5115 | PCI_ANY_ID, PCI_ANY_ID, |
5113 | 0, | 5116 | 0, |
5114 | 0, pbn_pericom_PI7C9X7954 }, | 5117 | 0, pbn_pericom_PI7C9X7954 }, |
5115 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, | 5118 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, |
5116 | PCI_ANY_ID, PCI_ANY_ID, | 5119 | PCI_ANY_ID, PCI_ANY_ID, |
5117 | 0, | 5120 | 0, |
5118 | 0, pbn_pericom_PI7C9X7958 }, | 5121 | 0, pbn_pericom_PI7C9X7958 }, |
5119 | /* | 5122 | /* |
5120 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) | 5123 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) |
5121 | */ | 5124 | */ |
5122 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, | 5125 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, |
5123 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5126 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5124 | pbn_b0_1_115200 }, | 5127 | pbn_b0_1_115200 }, |
5125 | /* | 5128 | /* |
5126 | * ITE | 5129 | * ITE |
5127 | */ | 5130 | */ |
5128 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | 5131 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, |
5129 | PCI_ANY_ID, PCI_ANY_ID, | 5132 | PCI_ANY_ID, PCI_ANY_ID, |
5130 | 0, 0, | 5133 | 0, 0, |
5131 | pbn_b1_bt_1_115200 }, | 5134 | pbn_b1_bt_1_115200 }, |
5132 | 5135 | ||
5133 | /* | 5136 | /* |
5134 | * IntaShield IS-200 | 5137 | * IntaShield IS-200 |
5135 | */ | 5138 | */ |
5136 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, | 5139 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, |
5137 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ | 5140 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ |
5138 | pbn_b2_2_115200 }, | 5141 | pbn_b2_2_115200 }, |
5139 | /* | 5142 | /* |
5140 | * IntaShield IS-400 | 5143 | * IntaShield IS-400 |
5141 | */ | 5144 | */ |
5142 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, | 5145 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, |
5143 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ | 5146 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ |
5144 | pbn_b2_4_115200 }, | 5147 | pbn_b2_4_115200 }, |
5145 | /* | 5148 | /* |
5146 | * Perle PCI-RAS cards | 5149 | * Perle PCI-RAS cards |
5147 | */ | 5150 | */ |
5148 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | 5151 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
5149 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, | 5152 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, |
5150 | 0, 0, pbn_b2_4_921600 }, | 5153 | 0, 0, pbn_b2_4_921600 }, |
5151 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | 5154 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
5152 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, | 5155 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, |
5153 | 0, 0, pbn_b2_8_921600 }, | 5156 | 0, 0, pbn_b2_8_921600 }, |
5154 | 5157 | ||
5155 | /* | 5158 | /* |
5156 | * Mainpine series cards: Fairly standard layout but fools | 5159 | * Mainpine series cards: Fairly standard layout but fools |
5157 | * parts of the autodetect in some cases and uses otherwise | 5160 | * parts of the autodetect in some cases and uses otherwise |
5158 | * unmatched communications subclasses in the PCI Express case | 5161 | * unmatched communications subclasses in the PCI Express case |
5159 | */ | 5162 | */ |
5160 | 5163 | ||
5161 | { /* RockForceDUO */ | 5164 | { /* RockForceDUO */ |
5162 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5165 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5163 | PCI_VENDOR_ID_MAINPINE, 0x0200, | 5166 | PCI_VENDOR_ID_MAINPINE, 0x0200, |
5164 | 0, 0, pbn_b0_2_115200 }, | 5167 | 0, 0, pbn_b0_2_115200 }, |
5165 | { /* RockForceQUATRO */ | 5168 | { /* RockForceQUATRO */ |
5166 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5169 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5167 | PCI_VENDOR_ID_MAINPINE, 0x0300, | 5170 | PCI_VENDOR_ID_MAINPINE, 0x0300, |
5168 | 0, 0, pbn_b0_4_115200 }, | 5171 | 0, 0, pbn_b0_4_115200 }, |
5169 | { /* RockForceDUO+ */ | 5172 | { /* RockForceDUO+ */ |
5170 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5173 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5171 | PCI_VENDOR_ID_MAINPINE, 0x0400, | 5174 | PCI_VENDOR_ID_MAINPINE, 0x0400, |
5172 | 0, 0, pbn_b0_2_115200 }, | 5175 | 0, 0, pbn_b0_2_115200 }, |
5173 | { /* RockForceQUATRO+ */ | 5176 | { /* RockForceQUATRO+ */ |
5174 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5177 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5175 | PCI_VENDOR_ID_MAINPINE, 0x0500, | 5178 | PCI_VENDOR_ID_MAINPINE, 0x0500, |
5176 | 0, 0, pbn_b0_4_115200 }, | 5179 | 0, 0, pbn_b0_4_115200 }, |
5177 | { /* RockForce+ */ | 5180 | { /* RockForce+ */ |
5178 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5181 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5179 | PCI_VENDOR_ID_MAINPINE, 0x0600, | 5182 | PCI_VENDOR_ID_MAINPINE, 0x0600, |
5180 | 0, 0, pbn_b0_2_115200 }, | 5183 | 0, 0, pbn_b0_2_115200 }, |
5181 | { /* RockForce+ */ | 5184 | { /* RockForce+ */ |
5182 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5185 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5183 | PCI_VENDOR_ID_MAINPINE, 0x0700, | 5186 | PCI_VENDOR_ID_MAINPINE, 0x0700, |
5184 | 0, 0, pbn_b0_4_115200 }, | 5187 | 0, 0, pbn_b0_4_115200 }, |
5185 | { /* RockForceOCTO+ */ | 5188 | { /* RockForceOCTO+ */ |
5186 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5189 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5187 | PCI_VENDOR_ID_MAINPINE, 0x0800, | 5190 | PCI_VENDOR_ID_MAINPINE, 0x0800, |
5188 | 0, 0, pbn_b0_8_115200 }, | 5191 | 0, 0, pbn_b0_8_115200 }, |
5189 | { /* RockForceDUO+ */ | 5192 | { /* RockForceDUO+ */ |
5190 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5193 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5191 | PCI_VENDOR_ID_MAINPINE, 0x0C00, | 5194 | PCI_VENDOR_ID_MAINPINE, 0x0C00, |
5192 | 0, 0, pbn_b0_2_115200 }, | 5195 | 0, 0, pbn_b0_2_115200 }, |
5193 | { /* RockForceQUARTRO+ */ | 5196 | { /* RockForceQUARTRO+ */ |
5194 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5197 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5195 | PCI_VENDOR_ID_MAINPINE, 0x0D00, | 5198 | PCI_VENDOR_ID_MAINPINE, 0x0D00, |
5196 | 0, 0, pbn_b0_4_115200 }, | 5199 | 0, 0, pbn_b0_4_115200 }, |
5197 | { /* RockForceOCTO+ */ | 5200 | { /* RockForceOCTO+ */ |
5198 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5201 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5199 | PCI_VENDOR_ID_MAINPINE, 0x1D00, | 5202 | PCI_VENDOR_ID_MAINPINE, 0x1D00, |
5200 | 0, 0, pbn_b0_8_115200 }, | 5203 | 0, 0, pbn_b0_8_115200 }, |
5201 | { /* RockForceD1 */ | 5204 | { /* RockForceD1 */ |
5202 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5205 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5203 | PCI_VENDOR_ID_MAINPINE, 0x2000, | 5206 | PCI_VENDOR_ID_MAINPINE, 0x2000, |
5204 | 0, 0, pbn_b0_1_115200 }, | 5207 | 0, 0, pbn_b0_1_115200 }, |
5205 | { /* RockForceF1 */ | 5208 | { /* RockForceF1 */ |
5206 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5209 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5207 | PCI_VENDOR_ID_MAINPINE, 0x2100, | 5210 | PCI_VENDOR_ID_MAINPINE, 0x2100, |
5208 | 0, 0, pbn_b0_1_115200 }, | 5211 | 0, 0, pbn_b0_1_115200 }, |
5209 | { /* RockForceD2 */ | 5212 | { /* RockForceD2 */ |
5210 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5213 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5211 | PCI_VENDOR_ID_MAINPINE, 0x2200, | 5214 | PCI_VENDOR_ID_MAINPINE, 0x2200, |
5212 | 0, 0, pbn_b0_2_115200 }, | 5215 | 0, 0, pbn_b0_2_115200 }, |
5213 | { /* RockForceF2 */ | 5216 | { /* RockForceF2 */ |
5214 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5217 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5215 | PCI_VENDOR_ID_MAINPINE, 0x2300, | 5218 | PCI_VENDOR_ID_MAINPINE, 0x2300, |
5216 | 0, 0, pbn_b0_2_115200 }, | 5219 | 0, 0, pbn_b0_2_115200 }, |
5217 | { /* RockForceD4 */ | 5220 | { /* RockForceD4 */ |
5218 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5221 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5219 | PCI_VENDOR_ID_MAINPINE, 0x2400, | 5222 | PCI_VENDOR_ID_MAINPINE, 0x2400, |
5220 | 0, 0, pbn_b0_4_115200 }, | 5223 | 0, 0, pbn_b0_4_115200 }, |
5221 | { /* RockForceF4 */ | 5224 | { /* RockForceF4 */ |
5222 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5225 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5223 | PCI_VENDOR_ID_MAINPINE, 0x2500, | 5226 | PCI_VENDOR_ID_MAINPINE, 0x2500, |
5224 | 0, 0, pbn_b0_4_115200 }, | 5227 | 0, 0, pbn_b0_4_115200 }, |
5225 | { /* RockForceD8 */ | 5228 | { /* RockForceD8 */ |
5226 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5229 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5227 | PCI_VENDOR_ID_MAINPINE, 0x2600, | 5230 | PCI_VENDOR_ID_MAINPINE, 0x2600, |
5228 | 0, 0, pbn_b0_8_115200 }, | 5231 | 0, 0, pbn_b0_8_115200 }, |
5229 | { /* RockForceF8 */ | 5232 | { /* RockForceF8 */ |
5230 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5233 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5231 | PCI_VENDOR_ID_MAINPINE, 0x2700, | 5234 | PCI_VENDOR_ID_MAINPINE, 0x2700, |
5232 | 0, 0, pbn_b0_8_115200 }, | 5235 | 0, 0, pbn_b0_8_115200 }, |
5233 | { /* IQ Express D1 */ | 5236 | { /* IQ Express D1 */ |
5234 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5237 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5235 | PCI_VENDOR_ID_MAINPINE, 0x3000, | 5238 | PCI_VENDOR_ID_MAINPINE, 0x3000, |
5236 | 0, 0, pbn_b0_1_115200 }, | 5239 | 0, 0, pbn_b0_1_115200 }, |
5237 | { /* IQ Express F1 */ | 5240 | { /* IQ Express F1 */ |
5238 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5241 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5239 | PCI_VENDOR_ID_MAINPINE, 0x3100, | 5242 | PCI_VENDOR_ID_MAINPINE, 0x3100, |
5240 | 0, 0, pbn_b0_1_115200 }, | 5243 | 0, 0, pbn_b0_1_115200 }, |
5241 | { /* IQ Express D2 */ | 5244 | { /* IQ Express D2 */ |
5242 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5245 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5243 | PCI_VENDOR_ID_MAINPINE, 0x3200, | 5246 | PCI_VENDOR_ID_MAINPINE, 0x3200, |
5244 | 0, 0, pbn_b0_2_115200 }, | 5247 | 0, 0, pbn_b0_2_115200 }, |
5245 | { /* IQ Express F2 */ | 5248 | { /* IQ Express F2 */ |
5246 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5249 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5247 | PCI_VENDOR_ID_MAINPINE, 0x3300, | 5250 | PCI_VENDOR_ID_MAINPINE, 0x3300, |
5248 | 0, 0, pbn_b0_2_115200 }, | 5251 | 0, 0, pbn_b0_2_115200 }, |
5249 | { /* IQ Express D4 */ | 5252 | { /* IQ Express D4 */ |
5250 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5253 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5251 | PCI_VENDOR_ID_MAINPINE, 0x3400, | 5254 | PCI_VENDOR_ID_MAINPINE, 0x3400, |
5252 | 0, 0, pbn_b0_4_115200 }, | 5255 | 0, 0, pbn_b0_4_115200 }, |
5253 | { /* IQ Express F4 */ | 5256 | { /* IQ Express F4 */ |
5254 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5257 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5255 | PCI_VENDOR_ID_MAINPINE, 0x3500, | 5258 | PCI_VENDOR_ID_MAINPINE, 0x3500, |
5256 | 0, 0, pbn_b0_4_115200 }, | 5259 | 0, 0, pbn_b0_4_115200 }, |
5257 | { /* IQ Express D8 */ | 5260 | { /* IQ Express D8 */ |
5258 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5261 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5259 | PCI_VENDOR_ID_MAINPINE, 0x3C00, | 5262 | PCI_VENDOR_ID_MAINPINE, 0x3C00, |
5260 | 0, 0, pbn_b0_8_115200 }, | 5263 | 0, 0, pbn_b0_8_115200 }, |
5261 | { /* IQ Express F8 */ | 5264 | { /* IQ Express F8 */ |
5262 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | 5265 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
5263 | PCI_VENDOR_ID_MAINPINE, 0x3D00, | 5266 | PCI_VENDOR_ID_MAINPINE, 0x3D00, |
5264 | 0, 0, pbn_b0_8_115200 }, | 5267 | 0, 0, pbn_b0_8_115200 }, |
5265 | 5268 | ||
5266 | 5269 | ||
5267 | /* | 5270 | /* |
5268 | * PA Semi PA6T-1682M on-chip UART | 5271 | * PA Semi PA6T-1682M on-chip UART |
5269 | */ | 5272 | */ |
5270 | { PCI_VENDOR_ID_PASEMI, 0xa004, | 5273 | { PCI_VENDOR_ID_PASEMI, 0xa004, |
5271 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5274 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5272 | pbn_pasemi_1682M }, | 5275 | pbn_pasemi_1682M }, |
5273 | 5276 | ||
5274 | /* | 5277 | /* |
5275 | * National Instruments | 5278 | * National Instruments |
5276 | */ | 5279 | */ |
5277 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, | 5280 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, |
5278 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5281 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5279 | pbn_b1_16_115200 }, | 5282 | pbn_b1_16_115200 }, |
5280 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, | 5283 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, |
5281 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5284 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5282 | pbn_b1_8_115200 }, | 5285 | pbn_b1_8_115200 }, |
5283 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, | 5286 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, |
5284 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5287 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5285 | pbn_b1_bt_4_115200 }, | 5288 | pbn_b1_bt_4_115200 }, |
5286 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, | 5289 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, |
5287 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5290 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5288 | pbn_b1_bt_2_115200 }, | 5291 | pbn_b1_bt_2_115200 }, |
5289 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, | 5292 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, |
5290 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5293 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5291 | pbn_b1_bt_4_115200 }, | 5294 | pbn_b1_bt_4_115200 }, |
5292 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, | 5295 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, |
5293 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5296 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5294 | pbn_b1_bt_2_115200 }, | 5297 | pbn_b1_bt_2_115200 }, |
5295 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, | 5298 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, |
5296 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5299 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5297 | pbn_b1_16_115200 }, | 5300 | pbn_b1_16_115200 }, |
5298 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, | 5301 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, |
5299 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5302 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5300 | pbn_b1_8_115200 }, | 5303 | pbn_b1_8_115200 }, |
5301 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, | 5304 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, |
5302 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5305 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5303 | pbn_b1_bt_4_115200 }, | 5306 | pbn_b1_bt_4_115200 }, |
5304 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, | 5307 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, |
5305 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5308 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5306 | pbn_b1_bt_2_115200 }, | 5309 | pbn_b1_bt_2_115200 }, |
5307 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, | 5310 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, |
5308 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5311 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5309 | pbn_b1_bt_4_115200 }, | 5312 | pbn_b1_bt_4_115200 }, |
5310 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, | 5313 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, |
5311 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5314 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5312 | pbn_b1_bt_2_115200 }, | 5315 | pbn_b1_bt_2_115200 }, |
5313 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, | 5316 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, |
5314 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5317 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5315 | pbn_ni8430_2 }, | 5318 | pbn_ni8430_2 }, |
5316 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, | 5319 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, |
5317 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5320 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5318 | pbn_ni8430_2 }, | 5321 | pbn_ni8430_2 }, |
5319 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, | 5322 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, |
5320 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5323 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5321 | pbn_ni8430_4 }, | 5324 | pbn_ni8430_4 }, |
5322 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, | 5325 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, |
5323 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5326 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5324 | pbn_ni8430_4 }, | 5327 | pbn_ni8430_4 }, |
5325 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, | 5328 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, |
5326 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5329 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5327 | pbn_ni8430_8 }, | 5330 | pbn_ni8430_8 }, |
5328 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, | 5331 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, |
5329 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5332 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5330 | pbn_ni8430_8 }, | 5333 | pbn_ni8430_8 }, |
5331 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, | 5334 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, |
5332 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5335 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5333 | pbn_ni8430_16 }, | 5336 | pbn_ni8430_16 }, |
5334 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, | 5337 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, |
5335 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5338 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5336 | pbn_ni8430_16 }, | 5339 | pbn_ni8430_16 }, |
5337 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, | 5340 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, |
5338 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5341 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5339 | pbn_ni8430_2 }, | 5342 | pbn_ni8430_2 }, |
5340 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, | 5343 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, |
5341 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5344 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5342 | pbn_ni8430_2 }, | 5345 | pbn_ni8430_2 }, |
5343 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, | 5346 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, |
5344 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5347 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5345 | pbn_ni8430_4 }, | 5348 | pbn_ni8430_4 }, |
5346 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, | 5349 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, |
5347 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5350 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5348 | pbn_ni8430_4 }, | 5351 | pbn_ni8430_4 }, |
5349 | 5352 | ||
5350 | /* | 5353 | /* |
5351 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | 5354 | * ADDI-DATA GmbH communication cards <info@addi-data.com> |
5352 | */ | 5355 | */ |
5353 | { PCI_VENDOR_ID_ADDIDATA, | 5356 | { PCI_VENDOR_ID_ADDIDATA, |
5354 | PCI_DEVICE_ID_ADDIDATA_APCI7500, | 5357 | PCI_DEVICE_ID_ADDIDATA_APCI7500, |
5355 | PCI_ANY_ID, | 5358 | PCI_ANY_ID, |
5356 | PCI_ANY_ID, | 5359 | PCI_ANY_ID, |
5357 | 0, | 5360 | 0, |
5358 | 0, | 5361 | 0, |
5359 | pbn_b0_4_115200 }, | 5362 | pbn_b0_4_115200 }, |
5360 | 5363 | ||
5361 | { PCI_VENDOR_ID_ADDIDATA, | 5364 | { PCI_VENDOR_ID_ADDIDATA, |
5362 | PCI_DEVICE_ID_ADDIDATA_APCI7420, | 5365 | PCI_DEVICE_ID_ADDIDATA_APCI7420, |
5363 | PCI_ANY_ID, | 5366 | PCI_ANY_ID, |
5364 | PCI_ANY_ID, | 5367 | PCI_ANY_ID, |
5365 | 0, | 5368 | 0, |
5366 | 0, | 5369 | 0, |
5367 | pbn_b0_2_115200 }, | 5370 | pbn_b0_2_115200 }, |
5368 | 5371 | ||
5369 | { PCI_VENDOR_ID_ADDIDATA, | 5372 | { PCI_VENDOR_ID_ADDIDATA, |
5370 | PCI_DEVICE_ID_ADDIDATA_APCI7300, | 5373 | PCI_DEVICE_ID_ADDIDATA_APCI7300, |
5371 | PCI_ANY_ID, | 5374 | PCI_ANY_ID, |
5372 | PCI_ANY_ID, | 5375 | PCI_ANY_ID, |
5373 | 0, | 5376 | 0, |
5374 | 0, | 5377 | 0, |
5375 | pbn_b0_1_115200 }, | 5378 | pbn_b0_1_115200 }, |
5376 | 5379 | ||
5377 | { PCI_VENDOR_ID_AMCC, | 5380 | { PCI_VENDOR_ID_AMCC, |
5378 | PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, | 5381 | PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, |
5379 | PCI_ANY_ID, | 5382 | PCI_ANY_ID, |
5380 | PCI_ANY_ID, | 5383 | PCI_ANY_ID, |
5381 | 0, | 5384 | 0, |
5382 | 0, | 5385 | 0, |
5383 | pbn_b1_8_115200 }, | 5386 | pbn_b1_8_115200 }, |
5384 | 5387 | ||
5385 | { PCI_VENDOR_ID_ADDIDATA, | 5388 | { PCI_VENDOR_ID_ADDIDATA, |
5386 | PCI_DEVICE_ID_ADDIDATA_APCI7500_2, | 5389 | PCI_DEVICE_ID_ADDIDATA_APCI7500_2, |
5387 | PCI_ANY_ID, | 5390 | PCI_ANY_ID, |
5388 | PCI_ANY_ID, | 5391 | PCI_ANY_ID, |
5389 | 0, | 5392 | 0, |
5390 | 0, | 5393 | 0, |
5391 | pbn_b0_4_115200 }, | 5394 | pbn_b0_4_115200 }, |
5392 | 5395 | ||
5393 | { PCI_VENDOR_ID_ADDIDATA, | 5396 | { PCI_VENDOR_ID_ADDIDATA, |
5394 | PCI_DEVICE_ID_ADDIDATA_APCI7420_2, | 5397 | PCI_DEVICE_ID_ADDIDATA_APCI7420_2, |
5395 | PCI_ANY_ID, | 5398 | PCI_ANY_ID, |
5396 | PCI_ANY_ID, | 5399 | PCI_ANY_ID, |
5397 | 0, | 5400 | 0, |
5398 | 0, | 5401 | 0, |
5399 | pbn_b0_2_115200 }, | 5402 | pbn_b0_2_115200 }, |
5400 | 5403 | ||
5401 | { PCI_VENDOR_ID_ADDIDATA, | 5404 | { PCI_VENDOR_ID_ADDIDATA, |
5402 | PCI_DEVICE_ID_ADDIDATA_APCI7300_2, | 5405 | PCI_DEVICE_ID_ADDIDATA_APCI7300_2, |
5403 | PCI_ANY_ID, | 5406 | PCI_ANY_ID, |
5404 | PCI_ANY_ID, | 5407 | PCI_ANY_ID, |
5405 | 0, | 5408 | 0, |
5406 | 0, | 5409 | 0, |
5407 | pbn_b0_1_115200 }, | 5410 | pbn_b0_1_115200 }, |
5408 | 5411 | ||
5409 | { PCI_VENDOR_ID_ADDIDATA, | 5412 | { PCI_VENDOR_ID_ADDIDATA, |
5410 | PCI_DEVICE_ID_ADDIDATA_APCI7500_3, | 5413 | PCI_DEVICE_ID_ADDIDATA_APCI7500_3, |
5411 | PCI_ANY_ID, | 5414 | PCI_ANY_ID, |
5412 | PCI_ANY_ID, | 5415 | PCI_ANY_ID, |
5413 | 0, | 5416 | 0, |
5414 | 0, | 5417 | 0, |
5415 | pbn_b0_4_115200 }, | 5418 | pbn_b0_4_115200 }, |
5416 | 5419 | ||
5417 | { PCI_VENDOR_ID_ADDIDATA, | 5420 | { PCI_VENDOR_ID_ADDIDATA, |
5418 | PCI_DEVICE_ID_ADDIDATA_APCI7420_3, | 5421 | PCI_DEVICE_ID_ADDIDATA_APCI7420_3, |
5419 | PCI_ANY_ID, | 5422 | PCI_ANY_ID, |
5420 | PCI_ANY_ID, | 5423 | PCI_ANY_ID, |
5421 | 0, | 5424 | 0, |
5422 | 0, | 5425 | 0, |
5423 | pbn_b0_2_115200 }, | 5426 | pbn_b0_2_115200 }, |
5424 | 5427 | ||
5425 | { PCI_VENDOR_ID_ADDIDATA, | 5428 | { PCI_VENDOR_ID_ADDIDATA, |
5426 | PCI_DEVICE_ID_ADDIDATA_APCI7300_3, | 5429 | PCI_DEVICE_ID_ADDIDATA_APCI7300_3, |
5427 | PCI_ANY_ID, | 5430 | PCI_ANY_ID, |
5428 | PCI_ANY_ID, | 5431 | PCI_ANY_ID, |
5429 | 0, | 5432 | 0, |
5430 | 0, | 5433 | 0, |
5431 | pbn_b0_1_115200 }, | 5434 | pbn_b0_1_115200 }, |
5432 | 5435 | ||
5433 | { PCI_VENDOR_ID_ADDIDATA, | 5436 | { PCI_VENDOR_ID_ADDIDATA, |
5434 | PCI_DEVICE_ID_ADDIDATA_APCI7800_3, | 5437 | PCI_DEVICE_ID_ADDIDATA_APCI7800_3, |
5435 | PCI_ANY_ID, | 5438 | PCI_ANY_ID, |
5436 | PCI_ANY_ID, | 5439 | PCI_ANY_ID, |
5437 | 0, | 5440 | 0, |
5438 | 0, | 5441 | 0, |
5439 | pbn_b0_8_115200 }, | 5442 | pbn_b0_8_115200 }, |
5440 | 5443 | ||
5441 | { PCI_VENDOR_ID_ADDIDATA, | 5444 | { PCI_VENDOR_ID_ADDIDATA, |
5442 | PCI_DEVICE_ID_ADDIDATA_APCIe7500, | 5445 | PCI_DEVICE_ID_ADDIDATA_APCIe7500, |
5443 | PCI_ANY_ID, | 5446 | PCI_ANY_ID, |
5444 | PCI_ANY_ID, | 5447 | PCI_ANY_ID, |
5445 | 0, | 5448 | 0, |
5446 | 0, | 5449 | 0, |
5447 | pbn_ADDIDATA_PCIe_4_3906250 }, | 5450 | pbn_ADDIDATA_PCIe_4_3906250 }, |
5448 | 5451 | ||
5449 | { PCI_VENDOR_ID_ADDIDATA, | 5452 | { PCI_VENDOR_ID_ADDIDATA, |
5450 | PCI_DEVICE_ID_ADDIDATA_APCIe7420, | 5453 | PCI_DEVICE_ID_ADDIDATA_APCIe7420, |
5451 | PCI_ANY_ID, | 5454 | PCI_ANY_ID, |
5452 | PCI_ANY_ID, | 5455 | PCI_ANY_ID, |
5453 | 0, | 5456 | 0, |
5454 | 0, | 5457 | 0, |
5455 | pbn_ADDIDATA_PCIe_2_3906250 }, | 5458 | pbn_ADDIDATA_PCIe_2_3906250 }, |
5456 | 5459 | ||
5457 | { PCI_VENDOR_ID_ADDIDATA, | 5460 | { PCI_VENDOR_ID_ADDIDATA, |
5458 | PCI_DEVICE_ID_ADDIDATA_APCIe7300, | 5461 | PCI_DEVICE_ID_ADDIDATA_APCIe7300, |
5459 | PCI_ANY_ID, | 5462 | PCI_ANY_ID, |
5460 | PCI_ANY_ID, | 5463 | PCI_ANY_ID, |
5461 | 0, | 5464 | 0, |
5462 | 0, | 5465 | 0, |
5463 | pbn_ADDIDATA_PCIe_1_3906250 }, | 5466 | pbn_ADDIDATA_PCIe_1_3906250 }, |
5464 | 5467 | ||
5465 | { PCI_VENDOR_ID_ADDIDATA, | 5468 | { PCI_VENDOR_ID_ADDIDATA, |
5466 | PCI_DEVICE_ID_ADDIDATA_APCIe7800, | 5469 | PCI_DEVICE_ID_ADDIDATA_APCIe7800, |
5467 | PCI_ANY_ID, | 5470 | PCI_ANY_ID, |
5468 | PCI_ANY_ID, | 5471 | PCI_ANY_ID, |
5469 | 0, | 5472 | 0, |
5470 | 0, | 5473 | 0, |
5471 | pbn_ADDIDATA_PCIe_8_3906250 }, | 5474 | pbn_ADDIDATA_PCIe_8_3906250 }, |
5472 | 5475 | ||
5473 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, | 5476 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, |
5474 | PCI_VENDOR_ID_IBM, 0x0299, | 5477 | PCI_VENDOR_ID_IBM, 0x0299, |
5475 | 0, 0, pbn_b0_bt_2_115200 }, | 5478 | 0, 0, pbn_b0_bt_2_115200 }, |
5476 | 5479 | ||
5477 | /* | 5480 | /* |
5478 | * other NetMos 9835 devices are most likely handled by the | 5481 | * other NetMos 9835 devices are most likely handled by the |
5479 | * parport_serial driver, check drivers/parport/parport_serial.c | 5482 | * parport_serial driver, check drivers/parport/parport_serial.c |
5480 | * before adding them here. | 5483 | * before adding them here. |
5481 | */ | 5484 | */ |
5482 | 5485 | ||
5483 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, | 5486 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, |
5484 | 0xA000, 0x1000, | 5487 | 0xA000, 0x1000, |
5485 | 0, 0, pbn_b0_1_115200 }, | 5488 | 0, 0, pbn_b0_1_115200 }, |
5486 | 5489 | ||
5487 | /* the 9901 is a rebranded 9912 */ | 5490 | /* the 9901 is a rebranded 9912 */ |
5488 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, | 5491 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, |
5489 | 0xA000, 0x1000, | 5492 | 0xA000, 0x1000, |
5490 | 0, 0, pbn_b0_1_115200 }, | 5493 | 0, 0, pbn_b0_1_115200 }, |
5491 | 5494 | ||
5492 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, | 5495 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, |
5493 | 0xA000, 0x1000, | 5496 | 0xA000, 0x1000, |
5494 | 0, 0, pbn_b0_1_115200 }, | 5497 | 0, 0, pbn_b0_1_115200 }, |
5495 | 5498 | ||
5496 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, | 5499 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, |
5497 | 0xA000, 0x1000, | 5500 | 0xA000, 0x1000, |
5498 | 0, 0, pbn_b0_1_115200 }, | 5501 | 0, 0, pbn_b0_1_115200 }, |
5499 | 5502 | ||
5500 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, | 5503 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, |
5501 | 0xA000, 0x1000, | 5504 | 0xA000, 0x1000, |
5502 | 0, 0, pbn_b0_1_115200 }, | 5505 | 0, 0, pbn_b0_1_115200 }, |
5503 | 5506 | ||
5504 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, | 5507 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, |
5505 | 0xA000, 0x3002, | 5508 | 0xA000, 0x3002, |
5506 | 0, 0, pbn_NETMOS9900_2s_115200 }, | 5509 | 0, 0, pbn_NETMOS9900_2s_115200 }, |
5507 | 5510 | ||
5508 | /* | 5511 | /* |
5509 | * Best Connectivity and Rosewill PCI Multi I/O cards | 5512 | * Best Connectivity and Rosewill PCI Multi I/O cards |
5510 | */ | 5513 | */ |
5511 | 5514 | ||
5512 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | 5515 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, |
5513 | 0xA000, 0x1000, | 5516 | 0xA000, 0x1000, |
5514 | 0, 0, pbn_b0_1_115200 }, | 5517 | 0, 0, pbn_b0_1_115200 }, |
5515 | 5518 | ||
5516 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | 5519 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, |
5517 | 0xA000, 0x3002, | 5520 | 0xA000, 0x3002, |
5518 | 0, 0, pbn_b0_bt_2_115200 }, | 5521 | 0, 0, pbn_b0_bt_2_115200 }, |
5519 | 5522 | ||
5520 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | 5523 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, |
5521 | 0xA000, 0x3004, | 5524 | 0xA000, 0x3004, |
5522 | 0, 0, pbn_b0_bt_4_115200 }, | 5525 | 0, 0, pbn_b0_bt_4_115200 }, |
5523 | /* Intel CE4100 */ | 5526 | /* Intel CE4100 */ |
5524 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, | 5527 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, |
5525 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5528 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5526 | pbn_ce4100_1_115200 }, | 5529 | pbn_ce4100_1_115200 }, |
5527 | /* Intel BayTrail */ | 5530 | /* Intel BayTrail */ |
5528 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, | 5531 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, |
5529 | PCI_ANY_ID, PCI_ANY_ID, | 5532 | PCI_ANY_ID, PCI_ANY_ID, |
5530 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, | 5533 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, |
5531 | pbn_byt }, | 5534 | pbn_byt }, |
5532 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, | 5535 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, |
5533 | PCI_ANY_ID, PCI_ANY_ID, | 5536 | PCI_ANY_ID, PCI_ANY_ID, |
5534 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, | 5537 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, |
5535 | pbn_byt }, | 5538 | pbn_byt }, |
5536 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, | 5539 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, |
5537 | PCI_ANY_ID, PCI_ANY_ID, | 5540 | PCI_ANY_ID, PCI_ANY_ID, |
5538 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, | 5541 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, |
5539 | pbn_byt }, | 5542 | pbn_byt }, |
5540 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, | 5543 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, |
5541 | PCI_ANY_ID, PCI_ANY_ID, | 5544 | PCI_ANY_ID, PCI_ANY_ID, |
5542 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, | 5545 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, |
5543 | pbn_byt }, | 5546 | pbn_byt }, |
5544 | 5547 | ||
5545 | /* Intel Broadwell */ | 5548 | /* Intel Broadwell */ |
5546 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1, | 5549 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1, |
5547 | PCI_ANY_ID, PCI_ANY_ID, | 5550 | PCI_ANY_ID, PCI_ANY_ID, |
5548 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, | 5551 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, |
5549 | pbn_byt }, | 5552 | pbn_byt }, |
5550 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2, | 5553 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2, |
5551 | PCI_ANY_ID, PCI_ANY_ID, | 5554 | PCI_ANY_ID, PCI_ANY_ID, |
5552 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, | 5555 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, |
5553 | pbn_byt }, | 5556 | pbn_byt }, |
5554 | 5557 | ||
5555 | /* | 5558 | /* |
5556 | * Intel Quark x1000 | 5559 | * Intel Quark x1000 |
5557 | */ | 5560 | */ |
5558 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, | 5561 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, |
5559 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5562 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5560 | pbn_qrk }, | 5563 | pbn_qrk }, |
5561 | /* | 5564 | /* |
5562 | * Cronyx Omega PCI | 5565 | * Cronyx Omega PCI |
5563 | */ | 5566 | */ |
5564 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, | 5567 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, |
5565 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5568 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5566 | pbn_omegapci }, | 5569 | pbn_omegapci }, |
5567 | 5570 | ||
5568 | /* | 5571 | /* |
5569 | * Broadcom TruManage | 5572 | * Broadcom TruManage |
5570 | */ | 5573 | */ |
5571 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, | 5574 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, |
5572 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 5575 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
5573 | pbn_brcm_trumanage }, | 5576 | pbn_brcm_trumanage }, |
5574 | 5577 | ||
5575 | /* | 5578 | /* |
5576 | * AgeStar as-prs2-009 | 5579 | * AgeStar as-prs2-009 |
5577 | */ | 5580 | */ |
5578 | { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, | 5581 | { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, |
5579 | PCI_ANY_ID, PCI_ANY_ID, | 5582 | PCI_ANY_ID, PCI_ANY_ID, |
5580 | 0, 0, pbn_b0_bt_2_115200 }, | 5583 | 0, 0, pbn_b0_bt_2_115200 }, |
5581 | 5584 | ||
5582 | /* | 5585 | /* |
5583 | * WCH CH353 series devices: The 2S1P is handled by parport_serial | 5586 | * WCH CH353 series devices: The 2S1P is handled by parport_serial |
5584 | * so not listed here. | 5587 | * so not listed here. |
5585 | */ | 5588 | */ |
5586 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, | 5589 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, |
5587 | PCI_ANY_ID, PCI_ANY_ID, | 5590 | PCI_ANY_ID, PCI_ANY_ID, |
5588 | 0, 0, pbn_b0_bt_4_115200 }, | 5591 | 0, 0, pbn_b0_bt_4_115200 }, |
5589 | 5592 | ||
5590 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, | 5593 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, |
5591 | PCI_ANY_ID, PCI_ANY_ID, | 5594 | PCI_ANY_ID, PCI_ANY_ID, |
5592 | 0, 0, pbn_b0_bt_2_115200 }, | 5595 | 0, 0, pbn_b0_bt_2_115200 }, |
5593 | 5596 | ||
5594 | { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, | 5597 | { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, |
5595 | PCI_ANY_ID, PCI_ANY_ID, | 5598 | PCI_ANY_ID, PCI_ANY_ID, |
5596 | 0, 0, pbn_wch382_2 }, | 5599 | 0, 0, pbn_wch382_2 }, |
5597 | 5600 | ||
5598 | { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, | 5601 | { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, |
5599 | PCI_ANY_ID, PCI_ANY_ID, | 5602 | PCI_ANY_ID, PCI_ANY_ID, |
5600 | 0, 0, pbn_wch384_4 }, | 5603 | 0, 0, pbn_wch384_4 }, |
5601 | 5604 | ||
5602 | /* | 5605 | /* |
5603 | * Commtech, Inc. Fastcom adapters | 5606 | * Commtech, Inc. Fastcom adapters |
5604 | */ | 5607 | */ |
5605 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, | 5608 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, |
5606 | PCI_ANY_ID, PCI_ANY_ID, | 5609 | PCI_ANY_ID, PCI_ANY_ID, |
5607 | 0, | 5610 | 0, |
5608 | 0, pbn_b0_2_1152000_200 }, | 5611 | 0, pbn_b0_2_1152000_200 }, |
5609 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, | 5612 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, |
5610 | PCI_ANY_ID, PCI_ANY_ID, | 5613 | PCI_ANY_ID, PCI_ANY_ID, |
5611 | 0, | 5614 | 0, |
5612 | 0, pbn_b0_4_1152000_200 }, | 5615 | 0, pbn_b0_4_1152000_200 }, |
5613 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, | 5616 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, |
5614 | PCI_ANY_ID, PCI_ANY_ID, | 5617 | PCI_ANY_ID, PCI_ANY_ID, |
5615 | 0, | 5618 | 0, |
5616 | 0, pbn_b0_4_1152000_200 }, | 5619 | 0, pbn_b0_4_1152000_200 }, |
5617 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, | 5620 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, |
5618 | PCI_ANY_ID, PCI_ANY_ID, | 5621 | PCI_ANY_ID, PCI_ANY_ID, |
5619 | 0, | 5622 | 0, |
5620 | 0, pbn_b0_8_1152000_200 }, | 5623 | 0, pbn_b0_8_1152000_200 }, |
5621 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, | 5624 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, |
5622 | PCI_ANY_ID, PCI_ANY_ID, | 5625 | PCI_ANY_ID, PCI_ANY_ID, |
5623 | 0, | 5626 | 0, |
5624 | 0, pbn_exar_XR17V352 }, | 5627 | 0, pbn_exar_XR17V352 }, |
5625 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, | 5628 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, |
5626 | PCI_ANY_ID, PCI_ANY_ID, | 5629 | PCI_ANY_ID, PCI_ANY_ID, |
5627 | 0, | 5630 | 0, |
5628 | 0, pbn_exar_XR17V354 }, | 5631 | 0, pbn_exar_XR17V354 }, |
5629 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, | 5632 | { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, |
5630 | PCI_ANY_ID, PCI_ANY_ID, | 5633 | PCI_ANY_ID, PCI_ANY_ID, |
5631 | 0, | 5634 | 0, |
5632 | 0, pbn_exar_XR17V358 }, | 5635 | 0, pbn_exar_XR17V358 }, |
5633 | 5636 | ||
5634 | /* Fintek PCI serial cards */ | 5637 | /* Fintek PCI serial cards */ |
5635 | { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, | 5638 | { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, |
5636 | { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, | 5639 | { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, |
5637 | { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, | 5640 | { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, |
5638 | 5641 | ||
5639 | /* | 5642 | /* |
5640 | * These entries match devices with class COMMUNICATION_SERIAL, | 5643 | * These entries match devices with class COMMUNICATION_SERIAL, |
5641 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL | 5644 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL |
5642 | */ | 5645 | */ |
5643 | { PCI_ANY_ID, PCI_ANY_ID, | 5646 | { PCI_ANY_ID, PCI_ANY_ID, |
5644 | PCI_ANY_ID, PCI_ANY_ID, | 5647 | PCI_ANY_ID, PCI_ANY_ID, |
5645 | PCI_CLASS_COMMUNICATION_SERIAL << 8, | 5648 | PCI_CLASS_COMMUNICATION_SERIAL << 8, |
5646 | 0xffff00, pbn_default }, | 5649 | 0xffff00, pbn_default }, |
5647 | { PCI_ANY_ID, PCI_ANY_ID, | 5650 | { PCI_ANY_ID, PCI_ANY_ID, |
5648 | PCI_ANY_ID, PCI_ANY_ID, | 5651 | PCI_ANY_ID, PCI_ANY_ID, |
5649 | PCI_CLASS_COMMUNICATION_MODEM << 8, | 5652 | PCI_CLASS_COMMUNICATION_MODEM << 8, |
5650 | 0xffff00, pbn_default }, | 5653 | 0xffff00, pbn_default }, |
5651 | { PCI_ANY_ID, PCI_ANY_ID, | 5654 | { PCI_ANY_ID, PCI_ANY_ID, |
5652 | PCI_ANY_ID, PCI_ANY_ID, | 5655 | PCI_ANY_ID, PCI_ANY_ID, |
5653 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, | 5656 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, |
5654 | 0xffff00, pbn_default }, | 5657 | 0xffff00, pbn_default }, |
5655 | { 0, } | 5658 | { 0, } |
5656 | }; | 5659 | }; |
5657 | 5660 | ||
5658 | static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, | 5661 | static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, |
5659 | pci_channel_state_t state) | 5662 | pci_channel_state_t state) |
5660 | { | 5663 | { |
5661 | struct serial_private *priv = pci_get_drvdata(dev); | 5664 | struct serial_private *priv = pci_get_drvdata(dev); |
5662 | 5665 | ||
5663 | if (state == pci_channel_io_perm_failure) | 5666 | if (state == pci_channel_io_perm_failure) |
5664 | return PCI_ERS_RESULT_DISCONNECT; | 5667 | return PCI_ERS_RESULT_DISCONNECT; |
5665 | 5668 | ||
5666 | if (priv) | 5669 | if (priv) |
5667 | pciserial_suspend_ports(priv); | 5670 | pciserial_suspend_ports(priv); |
5668 | 5671 | ||
5669 | pci_disable_device(dev); | 5672 | pci_disable_device(dev); |
5670 | 5673 | ||
5671 | return PCI_ERS_RESULT_NEED_RESET; | 5674 | return PCI_ERS_RESULT_NEED_RESET; |
5672 | } | 5675 | } |
5673 | 5676 | ||
5674 | static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) | 5677 | static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) |
5675 | { | 5678 | { |
5676 | int rc; | 5679 | int rc; |
5677 | 5680 | ||
5678 | rc = pci_enable_device(dev); | 5681 | rc = pci_enable_device(dev); |
5679 | 5682 | ||
5680 | if (rc) | 5683 | if (rc) |
5681 | return PCI_ERS_RESULT_DISCONNECT; | 5684 | return PCI_ERS_RESULT_DISCONNECT; |
5682 | 5685 | ||
5683 | pci_restore_state(dev); | 5686 | pci_restore_state(dev); |
5684 | pci_save_state(dev); | 5687 | pci_save_state(dev); |
5685 | 5688 | ||
5686 | return PCI_ERS_RESULT_RECOVERED; | 5689 | return PCI_ERS_RESULT_RECOVERED; |
5687 | } | 5690 | } |
5688 | 5691 | ||
5689 | static void serial8250_io_resume(struct pci_dev *dev) | 5692 | static void serial8250_io_resume(struct pci_dev *dev) |
5690 | { | 5693 | { |
5691 | struct serial_private *priv = pci_get_drvdata(dev); | 5694 | struct serial_private *priv = pci_get_drvdata(dev); |
5692 | 5695 | ||
5693 | if (priv) | 5696 | if (priv) |
5694 | pciserial_resume_ports(priv); | 5697 | pciserial_resume_ports(priv); |
5695 | } | 5698 | } |
5696 | 5699 | ||
5697 | static const struct pci_error_handlers serial8250_err_handler = { | 5700 | static const struct pci_error_handlers serial8250_err_handler = { |
5698 | .error_detected = serial8250_io_error_detected, | 5701 | .error_detected = serial8250_io_error_detected, |
5699 | .slot_reset = serial8250_io_slot_reset, | 5702 | .slot_reset = serial8250_io_slot_reset, |
5700 | .resume = serial8250_io_resume, | 5703 | .resume = serial8250_io_resume, |
5701 | }; | 5704 | }; |
5702 | 5705 | ||
5703 | static struct pci_driver serial_pci_driver = { | 5706 | static struct pci_driver serial_pci_driver = { |
5704 | .name = "serial", | 5707 | .name = "serial", |
5705 | .probe = pciserial_init_one, | 5708 | .probe = pciserial_init_one, |
5706 | .remove = pciserial_remove_one, | 5709 | .remove = pciserial_remove_one, |
5707 | .driver = { | 5710 | .driver = { |
5708 | .pm = &pciserial_pm_ops, | 5711 | .pm = &pciserial_pm_ops, |
5709 | }, | 5712 | }, |
5710 | .id_table = serial_pci_tbl, | 5713 | .id_table = serial_pci_tbl, |
5711 | .err_handler = &serial8250_err_handler, | 5714 | .err_handler = &serial8250_err_handler, |
5712 | }; | 5715 | }; |
5713 | 5716 | ||
5714 | module_pci_driver(serial_pci_driver); | 5717 | module_pci_driver(serial_pci_driver); |
5715 | 5718 | ||
5716 | MODULE_LICENSE("GPL"); | 5719 | MODULE_LICENSE("GPL"); |
5717 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); | 5720 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); |
5718 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); | 5721 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); |
5719 | 5722 |