Eric Lee / smarc-ti-linux-kernel

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Commit 14ed5c86d20d0e7660b3ee6c575513128aebda8a

Authored by Dan Murphy
2 parents 0e5217614e ac238cacdb
Exists in ti-linux-3.14.y and in 2 other branches processor-sdk-linux-01.00.00, smarc-ti-linux-3.14.y

Merge branch 'pm-ti-linux-3.14.y' of git://git.ti.com/~kristo/ti-linux-kernel/pm… 

…-linux-feature-tree into ti-linux-3.14.y

TI-Feature: power_management_base
TI-Tree: git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree.git
TI-Branch: pm-ti-linux-3.14.y

* 'pm-ti-linux-3.14.y' of git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree:
  ARM: OMAP2: pm33xx: Bump firmware version requirement to 0x190
  remoteproc: wkup_m3_rproc: Modify wkup_m3_ping to not use interrupts
  remoteproc: wkup_m3: Defer probe until wkup_m3_pm_ops are populated
  ARM: OMAP2+: pm33xx: Only pass i2c volt scale offsets for DeepSleep
  ARM: dts: AM4372: Add ti,mbox-send-noirq to wkup_m3 mailbox
  ARM: dts: AM33XX: Add ti,mbox-send-noirq to wkup_m3 mailbox
  mailbox/omap: Add ti,mbox-send-noirq quirk to fix AM33xx CPU Idle

Signed-off-by: Dan Murphy <DMurphy@ti.com>

Showing 7 changed files Inline Diff

Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
Diff comments   View file @ 14ed5c8
1 OMAP2+ Mailbox Driver 1 OMAP2+ Mailbox Driver
2 ===================== 2 =====================
3 3
4 The OMAP mailbox hardware facilitates communication between different processors 4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the 5 using a queued mailbox interrupt mechanism. The IP block is external to the
6 various processor subsystems and is connected on an interconnect bus. The 6 various processor subsystems and is connected on an interconnect bus. The
7 communication is achieved through a set of registers for message storage and 7 communication is achieved through a set of registers for message storage and
8 interrupt configuration registers. 8 interrupt configuration registers.
9 9
10 Each mailbox IP block has a certain number of h/w fifo queues and output 10 Each mailbox IP block has a certain number of h/w fifo queues and output
11 interrupt lines. An output interrupt line is routed to an interrupt controller 11 interrupt lines. An output interrupt line is routed to an interrupt controller
12 within a processor subsystem, and there can be more than one line going to a 12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are 13 specific processor's interrupt controller. The interrupt line connections are
14 fixed for an instance and are dictated by the IP integration into the SoC 14 fixed for an instance and are dictated by the IP integration into the SoC
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is 15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx 16 programmable through a set of interrupt configuration registers, and have a rx
17 and tx interrupt source per h/w fifo. Communication between different processors 17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt 18 is achieved through the appropriate programming of the rx and tx interrupt
19 sources on the appropriate interrupt lines. 19 sources on the appropriate interrupt lines.
20 20
21 The number of h/w fifo queues and interrupt lines dictate the usable registers. 21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
22 All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP 22 All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
23 instance. DRA7xx has multiple instances with different number of h/w fifo queues 23 instance. DRA7xx has multiple instances with different number of h/w fifo queues
24 and interrupt lines between different instances. The interrupt lines can also be 24 and interrupt lines between different instances. The interrupt lines can also be
25 routed to different processor sub-systems on DRA7xx as they are routed through 25 routed to different processor sub-systems on DRA7xx as they are routed through
26 the Crossbar, a kind of interrupt router/multiplexer. 26 the Crossbar, a kind of interrupt router/multiplexer.
27 27
28 Mailbox Device Node: 28 Mailbox Device Node:
29 ==================== 29 ====================
30 A Mailbox device node is used to represent a Mailbox IP instance within a SoC. 30 A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
31 The sub-mailboxes are represented as child nodes of this parent node. 31 The sub-mailboxes are represented as child nodes of this parent node.
32 32
33 Required properties: 33 Required properties:
34 -------------------- 34 --------------------
35 - compatible: Should be one of the following, 35 - compatible: Should be one of the following,
36 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs 36 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
37 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs 37 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
38 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, 38 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
39 AM43xx and DRA7xx SoCs 39 AM43xx and DRA7xx SoCs
40 - reg: Contains the mailbox register address range (base 40 - reg: Contains the mailbox register address range (base
41 address and length) 41 address and length)
42 - interrupts: Contains the interrupt information for the mailbox 42 - interrupts: Contains the interrupt information for the mailbox
43 device. The format is dependent on which interrupt 43 device. The format is dependent on which interrupt
44 controller the OMAP device uses 44 controller the OMAP device uses
45 - ti,hwmods: Name of the hwmod associated with the mailbox 45 - ti,hwmods: Name of the hwmod associated with the mailbox
46 - #mbox-cells: Common mailbox binding property to identify the number 46 - #mbox-cells: Common mailbox binding property to identify the number
47 of cells required for the mailbox specifier. Should be 47 of cells required for the mailbox specifier. Should be
48 1 48 1
49 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox 49 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
50 device can interrupt 50 device can interrupt
51 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block 51 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
52 52
53 Child Nodes: 53 Child Nodes:
54 ============ 54 ============
55 A child node is used for representing the actual sub-mailbox device that is 55 A child node is used for representing the actual sub-mailbox device that is
56 used for the communication between the host processor and a remote processor. 56 used for the communication between the host processor and a remote processor.
57 Each child node should have a unique node name across all the different 57 Each child node should have a unique node name across all the different
58 mailbox device nodes. 58 mailbox device nodes.
59 59
60 Required properties: 60 Required properties:
61 -------------------- 61 --------------------
62 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo 62 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
63 - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo 63 - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
64 64
65 Sub-mailbox Descriptor Data 65 Sub-mailbox Descriptor Data
66 --------------------------- 66 ---------------------------
67 Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of 67 Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
68 data that represent the following: 68 data that represent the following:
69 Cell #1 (fifo_id) - mailbox fifo id used either for transmitting 69 Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
70 (ti,mbox-tx) or for receiving (ti,mbox-rx) 70 (ti,mbox-tx) or for receiving (ti,mbox-rx)
71 Cell #2 (irq_id) - irq identifier index number to use from the parent's 71 Cell #2 (irq_id) - irq identifier index number to use from the parent's
72 interrupts data. Should be 0 for most of the cases, a 72 interrupts data. Should be 0 for most of the cases, a
73 positive index value is seen only on mailboxes that have 73 positive index value is seen only on mailboxes that have
74 multiple interrupt lines connected to the MPU processor. 74 multiple interrupt lines connected to the MPU processor.
75 Cell #3 (usr_id) - mailbox user id for identifying the interrupt line 75 Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
76 associated with generating a tx/rx fifo interrupt. 76 associated with generating a tx/rx fifo interrupt.
77 77
78 Optional Properties:
79 --------------------
80 - ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
81 to send messages without triggering a Tx ready interrupt,
82 and to control the Tx ticker. Should be used only on
83 sub-mailboxes used to communicate with WkupM3 remote
84 processor on AM33xx/AM43xx SoCs.
85
78 Mailbox Users: 86 Mailbox Users:
79 ============== 87 ==============
80 A device needing to communicate with a target processor device should specify 88 A device needing to communicate with a target processor device should specify
81 them using the common mailbox binding properties, "mboxes" and the optional 89 them using the common mailbox binding properties, "mboxes" and the optional
82 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt 90 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
83 for details). Each value of the mboxes property should contain a phandle to the 91 for details). Each value of the mboxes property should contain a phandle to the
84 mailbox controller device node and an args specifier that will be the phandle to 92 mailbox controller device node and an args specifier that will be the phandle to
85 the intended sub-mailbox child node to be used for communication. The equivalent 93 the intended sub-mailbox child node to be used for communication. The equivalent
86 "mbox-names" property value can be used to give a name to the communication channel 94 "mbox-names" property value can be used to give a name to the communication channel
87 to be used by the client user. 95 to be used by the client user.
88 96
89 97
90 Example: 98 Example:
91 -------- 99 --------
92 100
93 /* OMAP4 */ 101 /* OMAP4 */
94 mailbox: mailbox@4a0f4000 { 102 mailbox: mailbox@4a0f4000 {
95 compatible = "ti,omap4-mailbox"; 103 compatible = "ti,omap4-mailbox";
96 reg = <0x4a0f4000 0x200>; 104 reg = <0x4a0f4000 0x200>;
97 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 105 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
98 ti,hwmods = "mailbox"; 106 ti,hwmods = "mailbox";
99 #mbox-cells = <1>; 107 #mbox-cells = <1>;
100 ti,mbox-num-users = <3>; 108 ti,mbox-num-users = <3>;
101 ti,mbox-num-fifos = <8>; 109 ti,mbox-num-fifos = <8>;
102 mbox_ipu: mbox_ipu { 110 mbox_ipu: mbox_ipu {
103 ti,mbox-tx = <0 0 0>; 111 ti,mbox-tx = <0 0 0>;
104 ti,mbox-rx = <1 0 0>; 112 ti,mbox-rx = <1 0 0>;
105 }; 113 };
106 mbox_dsp: mbox_dsp { 114 mbox_dsp: mbox_dsp {
107 ti,mbox-tx = <3 0 0>; 115 ti,mbox-tx = <3 0 0>;
108 ti,mbox-rx = <2 0 0>; 116 ti,mbox-rx = <2 0 0>;
109 }; 117 };
110 }; 118 };
111 119
112 /* AM33xx */ 120 /* AM33xx */
113 mailbox: mailbox@480C8000 { 121 mailbox: mailbox@480C8000 {
114 compatible = "ti,omap4-mailbox"; 122 compatible = "ti,omap4-mailbox";
115 reg = <0x480C8000 0x200>; 123 reg = <0x480C8000 0x200>;
116 interrupts = <77>; 124 interrupts = <77>;
117 ti,hwmods = "mailbox"; 125 ti,hwmods = "mailbox";
118 #mbox-cells = <1>; 126 #mbox-cells = <1>;
119 ti,mbox-num-users = <4>; 127 ti,mbox-num-users = <4>;
120 ti,mbox-num-fifos = <8>; 128 ti,mbox-num-fifos = <8>;
121 mbox_wkupm3: wkup_m3 { 129 mbox_wkupm3: wkup_m3 {
122 ti,mbox-tx = <0 0 0>; 130 ti,mbox-tx = <0 0 0>;
123 ti,mbox-rx = <0 0 3>; 131 ti,mbox-rx = <0 0 3>;
124 }; 132 };
125 }; 133 };
126 134
127 wkup_m3: wkup_m3@44d00000 { 135 wkup_m3: wkup_m3@44d00000 {
128 ... 136 ...
129 mbox-names = "wkup_m3"; 137 mbox-names = "wkup_m3";
130 mboxes = <&mailbox &mbox_wkupm3>; 138 mboxes = <&mailbox &mbox_wkupm3>;
131 ... 139 ...
132 }; 140 };
133 141
arch/arm/boot/dts/am33xx.dtsi
Diff comments   View file @ 14ed5c8
1 /* 1 /*
2 * Device Tree Source for AM33XX SoC 2 * Device Tree Source for AM33XX SoC
3 * 3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public License 6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any 7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/am33xx.h> 12 #include <dt-bindings/pinctrl/am33xx.h>
13 13
14 #include "skeleton.dtsi" 14 #include "skeleton.dtsi"
15 15
16 / { 16 / {
17 compatible = "ti,am33xx"; 17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
19 19
20 aliases { 20 aliases {
21 i2c0 = &i2c0; 21 i2c0 = &i2c0;
22 i2c1 = &i2c1; 22 i2c1 = &i2c1;
23 i2c2 = &i2c2; 23 i2c2 = &i2c2;
24 serial0 = &uart0; 24 serial0 = &uart0;
25 serial1 = &uart1; 25 serial1 = &uart1;
26 serial2 = &uart2; 26 serial2 = &uart2;
27 serial3 = &uart3; 27 serial3 = &uart3;
28 serial4 = &uart4; 28 serial4 = &uart4;
29 serial5 = &uart5; 29 serial5 = &uart5;
30 d_can0 = &dcan0; 30 d_can0 = &dcan0;
31 d_can1 = &dcan1; 31 d_can1 = &dcan1;
32 usb0 = &usb0; 32 usb0 = &usb0;
33 usb1 = &usb1; 33 usb1 = &usb1;
34 phy0 = &usb0_phy; 34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy; 35 phy1 = &usb1_phy;
36 ethernet0 = &cpsw_emac0; 36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1; 37 ethernet1 = &cpsw_emac1;
38 }; 38 };
39 39
40 cpus { 40 cpus {
41 #address-cells = <1>; 41 #address-cells = <1>;
42 #size-cells = <0>; 42 #size-cells = <0>;
43 cpu@0 { 43 cpu@0 {
44 compatible = "arm,cortex-a8"; 44 compatible = "arm,cortex-a8";
45 device_type = "cpu"; 45 device_type = "cpu";
46 reg = <0>; 46 reg = <0>;
47 47
48 voltage-tolerance = <2>; /* 2 percentage */ 48 voltage-tolerance = <2>; /* 2 percentage */
49 49
50 clocks = <&dpll_mpu_ck>; 50 clocks = <&dpll_mpu_ck>;
51 clock-names = "cpu"; 51 clock-names = "cpu";
52 52
53 clock-latency = <300000>; /* From omap-cpufreq driver */ 53 clock-latency = <300000>; /* From omap-cpufreq driver */
54 }; 54 };
55 }; 55 };
56 56
57 pmu { 57 pmu {
58 compatible = "arm,cortex-a8-pmu"; 58 compatible = "arm,cortex-a8-pmu";
59 interrupts = <3>; 59 interrupts = <3>;
60 }; 60 };
61 61
62 /* 62 /*
63 * The soc node represents the soc top level view. It is uses for IPs 63 * The soc node represents the soc top level view. It is uses for IPs
64 * that are not memory mapped in the MPU view or for the MPU itself. 64 * that are not memory mapped in the MPU view or for the MPU itself.
65 */ 65 */
66 soc { 66 soc {
67 compatible = "ti,omap-infra"; 67 compatible = "ti,omap-infra";
68 mpu { 68 mpu {
69 compatible = "ti,omap3-mpu"; 69 compatible = "ti,omap3-mpu";
70 ti,hwmods = "mpu"; 70 ti,hwmods = "mpu";
71 }; 71 };
72 }; 72 };
73 73
74 am33xx_control_module: control_module@4a002000 { 74 am33xx_control_module: control_module@4a002000 {
75 compatible = "syscon"; 75 compatible = "syscon";
76 reg = <0x44e10000 0x7fc>; 76 reg = <0x44e10000 0x7fc>;
77 }; 77 };
78 78
79 am33xx_pinmux: pinmux@44e10800 { 79 am33xx_pinmux: pinmux@44e10800 {
80 compatible = "pinctrl-single"; 80 compatible = "pinctrl-single";
81 reg = <0x44e10800 0x0238>; 81 reg = <0x44e10800 0x0238>;
82 #address-cells = <1>; 82 #address-cells = <1>;
83 #size-cells = <0>; 83 #size-cells = <0>;
84 pinctrl-single,register-width = <32>; 84 pinctrl-single,register-width = <32>;
85 pinctrl-single,function-mask = <0x7f>; 85 pinctrl-single,function-mask = <0x7f>;
86 }; 86 };
87 87
88 /* 88 /*
89 * XXX: Use a flat representation of the AM33XX interconnect. 89 * XXX: Use a flat representation of the AM33XX interconnect.
90 * The real AM33XX interconnect network is quite complex.Since 90 * The real AM33XX interconnect network is quite complex.Since
91 * that will not bring real advantage to represent that in DT 91 * that will not bring real advantage to represent that in DT
92 * for the moment, just use a fake OCP bus entry to represent 92 * for the moment, just use a fake OCP bus entry to represent
93 * the whole bus hierarchy. 93 * the whole bus hierarchy.
94 */ 94 */
95 ocp { 95 ocp {
96 compatible = "simple-bus"; 96 compatible = "simple-bus";
97 #address-cells = <1>; 97 #address-cells = <1>;
98 #size-cells = <1>; 98 #size-cells = <1>;
99 ranges; 99 ranges;
100 ti,hwmods = "l3_main"; 100 ti,hwmods = "l3_main";
101 101
102 prcm: prcm@44e00000 { 102 prcm: prcm@44e00000 {
103 compatible = "ti,am3-prcm"; 103 compatible = "ti,am3-prcm";
104 reg = <0x44e00000 0x4000>; 104 reg = <0x44e00000 0x4000>;
105 105
106 prcm_clocks: clocks { 106 prcm_clocks: clocks {
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <0>; 108 #size-cells = <0>;
109 }; 109 };
110 110
111 prcm_clockdomains: clockdomains { 111 prcm_clockdomains: clockdomains {
112 }; 112 };
113 }; 113 };
114 114
115 scrm: scrm@44e10000 { 115 scrm: scrm@44e10000 {
116 compatible = "ti,am3-scrm"; 116 compatible = "ti,am3-scrm";
117 reg = <0x44e10000 0x2000>; 117 reg = <0x44e10000 0x2000>;
118 118
119 scrm_clocks: clocks { 119 scrm_clocks: clocks {
120 #address-cells = <1>; 120 #address-cells = <1>;
121 #size-cells = <0>; 121 #size-cells = <0>;
122 }; 122 };
123 123
124 scrm_clockdomains: clockdomains { 124 scrm_clockdomains: clockdomains {
125 }; 125 };
126 }; 126 };
127 127
128 intc: interrupt-controller@48200000 { 128 intc: interrupt-controller@48200000 {
129 compatible = "ti,omap2-intc"; 129 compatible = "ti,omap2-intc";
130 interrupt-controller; 130 interrupt-controller;
131 #interrupt-cells = <1>; 131 #interrupt-cells = <1>;
132 ti,intc-size = <128>; 132 ti,intc-size = <128>;
133 reg = <0x48200000 0x1000>; 133 reg = <0x48200000 0x1000>;
134 }; 134 };
135 135
136 edma: edma@49000000 { 136 edma: edma@49000000 {
137 compatible = "ti,edma3"; 137 compatible = "ti,edma3";
138 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; 138 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
139 reg = <0x49000000 0x10000>, 139 reg = <0x49000000 0x10000>,
140 <0x44e10f90 0x40>; 140 <0x44e10f90 0x40>;
141 interrupts = <12 13 14>; 141 interrupts = <12 13 14>;
142 #dma-cells = <1>; 142 #dma-cells = <1>;
143 }; 143 };
144 144
145 gpio0: gpio@44e07000 { 145 gpio0: gpio@44e07000 {
146 compatible = "ti,omap4-gpio"; 146 compatible = "ti,omap4-gpio";
147 ti,hwmods = "gpio1"; 147 ti,hwmods = "gpio1";
148 gpio-controller; 148 gpio-controller;
149 #gpio-cells = <2>; 149 #gpio-cells = <2>;
150 interrupt-controller; 150 interrupt-controller;
151 #interrupt-cells = <2>; 151 #interrupt-cells = <2>;
152 reg = <0x44e07000 0x1000>; 152 reg = <0x44e07000 0x1000>;
153 interrupts = <96>; 153 interrupts = <96>;
154 }; 154 };
155 155
156 gpio1: gpio@4804c000 { 156 gpio1: gpio@4804c000 {
157 compatible = "ti,omap4-gpio"; 157 compatible = "ti,omap4-gpio";
158 ti,hwmods = "gpio2"; 158 ti,hwmods = "gpio2";
159 gpio-controller; 159 gpio-controller;
160 #gpio-cells = <2>; 160 #gpio-cells = <2>;
161 interrupt-controller; 161 interrupt-controller;
162 #interrupt-cells = <2>; 162 #interrupt-cells = <2>;
163 reg = <0x4804c000 0x1000>; 163 reg = <0x4804c000 0x1000>;
164 interrupts = <98>; 164 interrupts = <98>;
165 }; 165 };
166 166
167 gpio2: gpio@481ac000 { 167 gpio2: gpio@481ac000 {
168 compatible = "ti,omap4-gpio"; 168 compatible = "ti,omap4-gpio";
169 ti,hwmods = "gpio3"; 169 ti,hwmods = "gpio3";
170 gpio-controller; 170 gpio-controller;
171 #gpio-cells = <2>; 171 #gpio-cells = <2>;
172 interrupt-controller; 172 interrupt-controller;
173 #interrupt-cells = <2>; 173 #interrupt-cells = <2>;
174 reg = <0x481ac000 0x1000>; 174 reg = <0x481ac000 0x1000>;
175 interrupts = <32>; 175 interrupts = <32>;
176 }; 176 };
177 177
178 gpio3: gpio@481ae000 { 178 gpio3: gpio@481ae000 {
179 compatible = "ti,omap4-gpio"; 179 compatible = "ti,omap4-gpio";
180 ti,hwmods = "gpio4"; 180 ti,hwmods = "gpio4";
181 gpio-controller; 181 gpio-controller;
182 #gpio-cells = <2>; 182 #gpio-cells = <2>;
183 interrupt-controller; 183 interrupt-controller;
184 #interrupt-cells = <2>; 184 #interrupt-cells = <2>;
185 reg = <0x481ae000 0x1000>; 185 reg = <0x481ae000 0x1000>;
186 interrupts = <62>; 186 interrupts = <62>;
187 }; 187 };
188 188
189 uart0: serial@44e09000 { 189 uart0: serial@44e09000 {
190 compatible = "ti,omap3-uart"; 190 compatible = "ti,omap3-uart";
191 ti,hwmods = "uart1"; 191 ti,hwmods = "uart1";
192 clock-frequency = <48000000>; 192 clock-frequency = <48000000>;
193 reg = <0x44e09000 0x2000>; 193 reg = <0x44e09000 0x2000>;
194 interrupts = <72>; 194 interrupts = <72>;
195 status = "disabled"; 195 status = "disabled";
196 dmas = <&edma 26>, <&edma 27>; 196 dmas = <&edma 26>, <&edma 27>;
197 dma-names = "tx", "rx"; 197 dma-names = "tx", "rx";
198 }; 198 };
199 199
200 uart1: serial@48022000 { 200 uart1: serial@48022000 {
201 compatible = "ti,omap3-uart"; 201 compatible = "ti,omap3-uart";
202 ti,hwmods = "uart2"; 202 ti,hwmods = "uart2";
203 clock-frequency = <48000000>; 203 clock-frequency = <48000000>;
204 reg = <0x48022000 0x2000>; 204 reg = <0x48022000 0x2000>;
205 interrupts = <73>; 205 interrupts = <73>;
206 status = "disabled"; 206 status = "disabled";
207 dmas = <&edma 28>, <&edma 29>; 207 dmas = <&edma 28>, <&edma 29>;
208 dma-names = "tx", "rx"; 208 dma-names = "tx", "rx";
209 }; 209 };
210 210
211 uart2: serial@48024000 { 211 uart2: serial@48024000 {
212 compatible = "ti,omap3-uart"; 212 compatible = "ti,omap3-uart";
213 ti,hwmods = "uart3"; 213 ti,hwmods = "uart3";
214 clock-frequency = <48000000>; 214 clock-frequency = <48000000>;
215 reg = <0x48024000 0x2000>; 215 reg = <0x48024000 0x2000>;
216 interrupts = <74>; 216 interrupts = <74>;
217 status = "disabled"; 217 status = "disabled";
218 dmas = <&edma 30>, <&edma 31>; 218 dmas = <&edma 30>, <&edma 31>;
219 dma-names = "tx", "rx"; 219 dma-names = "tx", "rx";
220 }; 220 };
221 221
222 uart3: serial@481a6000 { 222 uart3: serial@481a6000 {
223 compatible = "ti,omap3-uart"; 223 compatible = "ti,omap3-uart";
224 ti,hwmods = "uart4"; 224 ti,hwmods = "uart4";
225 clock-frequency = <48000000>; 225 clock-frequency = <48000000>;
226 reg = <0x481a6000 0x2000>; 226 reg = <0x481a6000 0x2000>;
227 interrupts = <44>; 227 interrupts = <44>;
228 status = "disabled"; 228 status = "disabled";
229 }; 229 };
230 230
231 uart4: serial@481a8000 { 231 uart4: serial@481a8000 {
232 compatible = "ti,omap3-uart"; 232 compatible = "ti,omap3-uart";
233 ti,hwmods = "uart5"; 233 ti,hwmods = "uart5";
234 clock-frequency = <48000000>; 234 clock-frequency = <48000000>;
235 reg = <0x481a8000 0x2000>; 235 reg = <0x481a8000 0x2000>;
236 interrupts = <45>; 236 interrupts = <45>;
237 status = "disabled"; 237 status = "disabled";
238 }; 238 };
239 239
240 uart5: serial@481aa000 { 240 uart5: serial@481aa000 {
241 compatible = "ti,omap3-uart"; 241 compatible = "ti,omap3-uart";
242 ti,hwmods = "uart6"; 242 ti,hwmods = "uart6";
243 clock-frequency = <48000000>; 243 clock-frequency = <48000000>;
244 reg = <0x481aa000 0x2000>; 244 reg = <0x481aa000 0x2000>;
245 interrupts = <46>; 245 interrupts = <46>;
246 status = "disabled"; 246 status = "disabled";
247 }; 247 };
248 248
249 i2c0: i2c@44e0b000 { 249 i2c0: i2c@44e0b000 {
250 compatible = "ti,omap4-i2c"; 250 compatible = "ti,omap4-i2c";
251 #address-cells = <1>; 251 #address-cells = <1>;
252 #size-cells = <0>; 252 #size-cells = <0>;
253 ti,hwmods = "i2c1"; 253 ti,hwmods = "i2c1";
254 reg = <0x44e0b000 0x1000>; 254 reg = <0x44e0b000 0x1000>;
255 interrupts = <70>; 255 interrupts = <70>;
256 status = "disabled"; 256 status = "disabled";
257 }; 257 };
258 258
259 i2c1: i2c@4802a000 { 259 i2c1: i2c@4802a000 {
260 compatible = "ti,omap4-i2c"; 260 compatible = "ti,omap4-i2c";
261 #address-cells = <1>; 261 #address-cells = <1>;
262 #size-cells = <0>; 262 #size-cells = <0>;
263 ti,hwmods = "i2c2"; 263 ti,hwmods = "i2c2";
264 reg = <0x4802a000 0x1000>; 264 reg = <0x4802a000 0x1000>;
265 interrupts = <71>; 265 interrupts = <71>;
266 status = "disabled"; 266 status = "disabled";
267 }; 267 };
268 268
269 i2c2: i2c@4819c000 { 269 i2c2: i2c@4819c000 {
270 compatible = "ti,omap4-i2c"; 270 compatible = "ti,omap4-i2c";
271 #address-cells = <1>; 271 #address-cells = <1>;
272 #size-cells = <0>; 272 #size-cells = <0>;
273 ti,hwmods = "i2c3"; 273 ti,hwmods = "i2c3";
274 reg = <0x4819c000 0x1000>; 274 reg = <0x4819c000 0x1000>;
275 interrupts = <30>; 275 interrupts = <30>;
276 status = "disabled"; 276 status = "disabled";
277 }; 277 };
278 278
279 mmc1: mmc@48060000 { 279 mmc1: mmc@48060000 {
280 compatible = "ti,omap4-hsmmc"; 280 compatible = "ti,omap4-hsmmc";
281 ti,hwmods = "mmc1"; 281 ti,hwmods = "mmc1";
282 ti,dual-volt; 282 ti,dual-volt;
283 ti,needs-special-reset; 283 ti,needs-special-reset;
284 ti,needs-special-hs-handling; 284 ti,needs-special-hs-handling;
285 dmas = <&edma 24 285 dmas = <&edma 24
286 &edma 25>; 286 &edma 25>;
287 dma-names = "tx", "rx"; 287 dma-names = "tx", "rx";
288 interrupts = <64>; 288 interrupts = <64>;
289 interrupt-parent = <&intc>; 289 interrupt-parent = <&intc>;
290 reg = <0x48060000 0x1000>; 290 reg = <0x48060000 0x1000>;
291 status = "disabled"; 291 status = "disabled";
292 }; 292 };
293 293
294 mmc2: mmc@481d8000 { 294 mmc2: mmc@481d8000 {
295 compatible = "ti,omap4-hsmmc"; 295 compatible = "ti,omap4-hsmmc";
296 ti,hwmods = "mmc2"; 296 ti,hwmods = "mmc2";
297 ti,needs-special-reset; 297 ti,needs-special-reset;
298 dmas = <&edma 2 298 dmas = <&edma 2
299 &edma 3>; 299 &edma 3>;
300 dma-names = "tx", "rx"; 300 dma-names = "tx", "rx";
301 interrupts = <28>; 301 interrupts = <28>;
302 interrupt-parent = <&intc>; 302 interrupt-parent = <&intc>;
303 reg = <0x481d8000 0x1000>; 303 reg = <0x481d8000 0x1000>;
304 status = "disabled"; 304 status = "disabled";
305 }; 305 };
306 306
307 mmc3: mmc@47810000 { 307 mmc3: mmc@47810000 {
308 compatible = "ti,omap4-hsmmc"; 308 compatible = "ti,omap4-hsmmc";
309 ti,hwmods = "mmc3"; 309 ti,hwmods = "mmc3";
310 ti,needs-special-reset; 310 ti,needs-special-reset;
311 interrupts = <29>; 311 interrupts = <29>;
312 interrupt-parent = <&intc>; 312 interrupt-parent = <&intc>;
313 reg = <0x47810000 0x1000>; 313 reg = <0x47810000 0x1000>;
314 status = "disabled"; 314 status = "disabled";
315 }; 315 };
316 316
317 hwspinlock: spinlock@480ca000 { 317 hwspinlock: spinlock@480ca000 {
318 compatible = "ti,omap4-hwspinlock"; 318 compatible = "ti,omap4-hwspinlock";
319 reg = <0x480ca000 0x1000>; 319 reg = <0x480ca000 0x1000>;
320 ti,hwmods = "spinlock"; 320 ti,hwmods = "spinlock";
321 #hwlock-cells = <1>; 321 #hwlock-cells = <1>;
322 }; 322 };
323 323
324 wdt2: wdt@44e35000 { 324 wdt2: wdt@44e35000 {
325 compatible = "ti,omap3-wdt"; 325 compatible = "ti,omap3-wdt";
326 ti,hwmods = "wd_timer2"; 326 ti,hwmods = "wd_timer2";
327 reg = <0x44e35000 0x1000>; 327 reg = <0x44e35000 0x1000>;
328 interrupts = <91>; 328 interrupts = <91>;
329 }; 329 };
330 330
331 dcan0: can@481cc000 { 331 dcan0: can@481cc000 {
332 compatible = "ti,am3352-d_can"; 332 compatible = "ti,am3352-d_can";
333 ti,hwmods = "d_can0"; 333 ti,hwmods = "d_can0";
334 clocks = <&dcan0_fck>; 334 clocks = <&dcan0_fck>;
335 clock-names = "fck"; 335 clock-names = "fck";
336 reg = <0x481cc000 0x2000>; 336 reg = <0x481cc000 0x2000>;
337 syscon-raminit = <&am33xx_control_module 0x644 0>; 337 syscon-raminit = <&am33xx_control_module 0x644 0>;
338 interrupts = <52>; 338 interrupts = <52>;
339 status = "disabled"; 339 status = "disabled";
340 }; 340 };
341 341
342 dcan1: can@481d0000 { 342 dcan1: can@481d0000 {
343 compatible = "ti,am3352-d_can"; 343 compatible = "ti,am3352-d_can";
344 ti,hwmods = "d_can1"; 344 ti,hwmods = "d_can1";
345 clocks = <&dcan1_fck>; 345 clocks = <&dcan1_fck>;
346 clock-names = "fck"; 346 clock-names = "fck";
347 reg = <0x481d0000 0x2000>; 347 reg = <0x481d0000 0x2000>;
348 syscon-raminit = <&am33xx_control_module 0x644 1>; 348 syscon-raminit = <&am33xx_control_module 0x644 1>;
349 interrupts = <55>; 349 interrupts = <55>;
350 status = "disabled"; 350 status = "disabled";
351 }; 351 };
352 352
353 mailbox: mailbox@480C8000 { 353 mailbox: mailbox@480C8000 {
354 compatible = "ti,omap4-mailbox"; 354 compatible = "ti,omap4-mailbox";
355 reg = <0x480C8000 0x200>; 355 reg = <0x480C8000 0x200>;
356 interrupts = <77>; 356 interrupts = <77>;
357 ti,hwmods = "mailbox"; 357 ti,hwmods = "mailbox";
358 #mbox-cells = <1>; 358 #mbox-cells = <1>;
359 ti,mbox-num-users = <4>; 359 ti,mbox-num-users = <4>;
360 ti,mbox-num-fifos = <8>; 360 ti,mbox-num-fifos = <8>;
361 mbox_wkupm3: wkup_m3 { 361 mbox_wkupm3: wkup_m3 {
362 ti,mbox-send-noirq;
362 ti,mbox-tx = <0 0 0>; 363 ti,mbox-tx = <0 0 0>;
363 ti,mbox-rx = <0 0 3>; 364 ti,mbox-rx = <0 0 3>;
364 }; 365 };
365 mbox_pru0: mbox_pru0 { 366 mbox_pru0: mbox_pru0 {
366 ti,mbox-tx = <2 0 0>; 367 ti,mbox-tx = <2 0 0>;
367 ti,mbox-rx = <3 0 0>; 368 ti,mbox-rx = <3 0 0>;
368 }; 369 };
369 mbox_pru1: mbox_pru1 { 370 mbox_pru1: mbox_pru1 {
370 ti,mbox-tx = <4 0 0>; 371 ti,mbox-tx = <4 0 0>;
371 ti,mbox-rx = <5 0 0>; 372 ti,mbox-rx = <5 0 0>;
372 }; 373 };
373 }; 374 };
374 375
375 timer1: timer@44e31000 { 376 timer1: timer@44e31000 {
376 compatible = "ti,am335x-timer-1ms"; 377 compatible = "ti,am335x-timer-1ms";
377 reg = <0x44e31000 0x400>; 378 reg = <0x44e31000 0x400>;
378 interrupts = <67>; 379 interrupts = <67>;
379 ti,hwmods = "timer1"; 380 ti,hwmods = "timer1";
380 ti,timer-alwon; 381 ti,timer-alwon;
381 }; 382 };
382 383
383 timer2: timer@48040000 { 384 timer2: timer@48040000 {
384 compatible = "ti,am335x-timer"; 385 compatible = "ti,am335x-timer";
385 reg = <0x48040000 0x400>; 386 reg = <0x48040000 0x400>;
386 interrupts = <68>; 387 interrupts = <68>;
387 ti,hwmods = "timer2"; 388 ti,hwmods = "timer2";
388 }; 389 };
389 390
390 timer3: timer@48042000 { 391 timer3: timer@48042000 {
391 compatible = "ti,am335x-timer"; 392 compatible = "ti,am335x-timer";
392 reg = <0x48042000 0x400>; 393 reg = <0x48042000 0x400>;
393 interrupts = <69>; 394 interrupts = <69>;
394 ti,hwmods = "timer3"; 395 ti,hwmods = "timer3";
395 }; 396 };
396 397
397 timer4: timer@48044000 { 398 timer4: timer@48044000 {
398 compatible = "ti,am335x-timer"; 399 compatible = "ti,am335x-timer";
399 reg = <0x48044000 0x400>; 400 reg = <0x48044000 0x400>;
400 interrupts = <92>; 401 interrupts = <92>;
401 ti,hwmods = "timer4"; 402 ti,hwmods = "timer4";
402 ti,timer-pwm; 403 ti,timer-pwm;
403 }; 404 };
404 405
405 timer5: timer@48046000 { 406 timer5: timer@48046000 {
406 compatible = "ti,am335x-timer"; 407 compatible = "ti,am335x-timer";
407 reg = <0x48046000 0x400>; 408 reg = <0x48046000 0x400>;
408 interrupts = <93>; 409 interrupts = <93>;
409 ti,hwmods = "timer5"; 410 ti,hwmods = "timer5";
410 ti,timer-pwm; 411 ti,timer-pwm;
411 }; 412 };
412 413
413 timer6: timer@48048000 { 414 timer6: timer@48048000 {
414 compatible = "ti,am335x-timer"; 415 compatible = "ti,am335x-timer";
415 reg = <0x48048000 0x400>; 416 reg = <0x48048000 0x400>;
416 interrupts = <94>; 417 interrupts = <94>;
417 ti,hwmods = "timer6"; 418 ti,hwmods = "timer6";
418 ti,timer-pwm; 419 ti,timer-pwm;
419 }; 420 };
420 421
421 timer7: timer@4804a000 { 422 timer7: timer@4804a000 {
422 compatible = "ti,am335x-timer"; 423 compatible = "ti,am335x-timer";
423 reg = <0x4804a000 0x400>; 424 reg = <0x4804a000 0x400>;
424 interrupts = <95>; 425 interrupts = <95>;
425 ti,hwmods = "timer7"; 426 ti,hwmods = "timer7";
426 ti,timer-pwm; 427 ti,timer-pwm;
427 }; 428 };
428 429
429 rtc@44e3e000 { 430 rtc@44e3e000 {
430 compatible = "ti,am3352-rtc"; 431 compatible = "ti,am3352-rtc";
431 reg = <0x44e3e000 0x1000>; 432 reg = <0x44e3e000 0x1000>;
432 interrupts = <75 433 interrupts = <75
433 76>; 434 76>;
434 ti,hwmods = "rtc"; 435 ti,hwmods = "rtc";
435 }; 436 };
436 437
437 spi0: spi@48030000 { 438 spi0: spi@48030000 {
438 compatible = "ti,omap4-mcspi"; 439 compatible = "ti,omap4-mcspi";
439 #address-cells = <1>; 440 #address-cells = <1>;
440 #size-cells = <0>; 441 #size-cells = <0>;
441 reg = <0x48030000 0x400>; 442 reg = <0x48030000 0x400>;
442 interrupts = <65>; 443 interrupts = <65>;
443 ti,spi-num-cs = <2>; 444 ti,spi-num-cs = <2>;
444 ti,hwmods = "spi0"; 445 ti,hwmods = "spi0";
445 dmas = <&edma 16 446 dmas = <&edma 16
446 &edma 17 447 &edma 17
447 &edma 18 448 &edma 18
448 &edma 19>; 449 &edma 19>;
449 dma-names = "tx0", "rx0", "tx1", "rx1"; 450 dma-names = "tx0", "rx0", "tx1", "rx1";
450 status = "disabled"; 451 status = "disabled";
451 }; 452 };
452 453
453 spi1: spi@481a0000 { 454 spi1: spi@481a0000 {
454 compatible = "ti,omap4-mcspi"; 455 compatible = "ti,omap4-mcspi";
455 #address-cells = <1>; 456 #address-cells = <1>;
456 #size-cells = <0>; 457 #size-cells = <0>;
457 reg = <0x481a0000 0x400>; 458 reg = <0x481a0000 0x400>;
458 interrupts = <125>; 459 interrupts = <125>;
459 ti,spi-num-cs = <2>; 460 ti,spi-num-cs = <2>;
460 ti,hwmods = "spi1"; 461 ti,hwmods = "spi1";
461 dmas = <&edma 42 462 dmas = <&edma 42
462 &edma 43 463 &edma 43
463 &edma 44 464 &edma 44
464 &edma 45>; 465 &edma 45>;
465 dma-names = "tx0", "rx0", "tx1", "rx1"; 466 dma-names = "tx0", "rx0", "tx1", "rx1";
466 status = "disabled"; 467 status = "disabled";
467 }; 468 };
468 469
469 usb: usb@47400000 { 470 usb: usb@47400000 {
470 compatible = "ti,am33xx-usb"; 471 compatible = "ti,am33xx-usb";
471 reg = <0x47400000 0x1000>; 472 reg = <0x47400000 0x1000>;
472 ranges; 473 ranges;
473 #address-cells = <1>; 474 #address-cells = <1>;
474 #size-cells = <1>; 475 #size-cells = <1>;
475 ti,hwmods = "usb_otg_hs"; 476 ti,hwmods = "usb_otg_hs";
476 status = "disabled"; 477 status = "disabled";
477 478
478 usb_ctrl_mod: control@44e10620 { 479 usb_ctrl_mod: control@44e10620 {
479 compatible = "ti,am335x-usb-ctrl-module"; 480 compatible = "ti,am335x-usb-ctrl-module";
480 reg = <0x44e10620 0x10 481 reg = <0x44e10620 0x10
481 0x44e10648 0x4>; 482 0x44e10648 0x4>;
482 reg-names = "phy_ctrl", "wakeup"; 483 reg-names = "phy_ctrl", "wakeup";
483 status = "disabled"; 484 status = "disabled";
484 }; 485 };
485 486
486 usb0_phy: usb-phy@47401300 { 487 usb0_phy: usb-phy@47401300 {
487 compatible = "ti,am335x-usb-phy"; 488 compatible = "ti,am335x-usb-phy";
488 reg = <0x47401300 0x100>; 489 reg = <0x47401300 0x100>;
489 reg-names = "phy"; 490 reg-names = "phy";
490 status = "disabled"; 491 status = "disabled";
491 ti,ctrl_mod = <&usb_ctrl_mod>; 492 ti,ctrl_mod = <&usb_ctrl_mod>;
492 }; 493 };
493 494
494 usb0: usb@47401000 { 495 usb0: usb@47401000 {
495 compatible = "ti,musb-am33xx"; 496 compatible = "ti,musb-am33xx";
496 status = "disabled"; 497 status = "disabled";
497 reg = <0x47401400 0x400 498 reg = <0x47401400 0x400
498 0x47401000 0x200>; 499 0x47401000 0x200>;
499 reg-names = "mc", "control"; 500 reg-names = "mc", "control";
500 501
501 interrupts = <18>; 502 interrupts = <18>;
502 interrupt-names = "mc"; 503 interrupt-names = "mc";
503 dr_mode = "otg"; 504 dr_mode = "otg";
504 mentor,multipoint = <1>; 505 mentor,multipoint = <1>;
505 mentor,num-eps = <16>; 506 mentor,num-eps = <16>;
506 mentor,ram-bits = <12>; 507 mentor,ram-bits = <12>;
507 mentor,power = <500>; 508 mentor,power = <500>;
508 phys = <&usb0_phy>; 509 phys = <&usb0_phy>;
509 510
510 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 511 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
511 &cppi41dma 2 0 &cppi41dma 3 0 512 &cppi41dma 2 0 &cppi41dma 3 0
512 &cppi41dma 4 0 &cppi41dma 5 0 513 &cppi41dma 4 0 &cppi41dma 5 0
513 &cppi41dma 6 0 &cppi41dma 7 0 514 &cppi41dma 6 0 &cppi41dma 7 0
514 &cppi41dma 8 0 &cppi41dma 9 0 515 &cppi41dma 8 0 &cppi41dma 9 0
515 &cppi41dma 10 0 &cppi41dma 11 0 516 &cppi41dma 10 0 &cppi41dma 11 0
516 &cppi41dma 12 0 &cppi41dma 13 0 517 &cppi41dma 12 0 &cppi41dma 13 0
517 &cppi41dma 14 0 &cppi41dma 0 1 518 &cppi41dma 14 0 &cppi41dma 0 1
518 &cppi41dma 1 1 &cppi41dma 2 1 519 &cppi41dma 1 1 &cppi41dma 2 1
519 &cppi41dma 3 1 &cppi41dma 4 1 520 &cppi41dma 3 1 &cppi41dma 4 1
520 &cppi41dma 5 1 &cppi41dma 6 1 521 &cppi41dma 5 1 &cppi41dma 6 1
521 &cppi41dma 7 1 &cppi41dma 8 1 522 &cppi41dma 7 1 &cppi41dma 8 1
522 &cppi41dma 9 1 &cppi41dma 10 1 523 &cppi41dma 9 1 &cppi41dma 10 1
523 &cppi41dma 11 1 &cppi41dma 12 1 524 &cppi41dma 11 1 &cppi41dma 12 1
524 &cppi41dma 13 1 &cppi41dma 14 1>; 525 &cppi41dma 13 1 &cppi41dma 14 1>;
525 dma-names = 526 dma-names =
526 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 527 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
527 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 528 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
528 "rx14", "rx15", 529 "rx14", "rx15",
529 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 530 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
530 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 531 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
531 "tx14", "tx15"; 532 "tx14", "tx15";
532 }; 533 };
533 534
534 usb1_phy: usb-phy@47401b00 { 535 usb1_phy: usb-phy@47401b00 {
535 compatible = "ti,am335x-usb-phy"; 536 compatible = "ti,am335x-usb-phy";
536 reg = <0x47401b00 0x100>; 537 reg = <0x47401b00 0x100>;
537 reg-names = "phy"; 538 reg-names = "phy";
538 status = "disabled"; 539 status = "disabled";
539 ti,ctrl_mod = <&usb_ctrl_mod>; 540 ti,ctrl_mod = <&usb_ctrl_mod>;
540 }; 541 };
541 542
542 usb1: usb@47401800 { 543 usb1: usb@47401800 {
543 compatible = "ti,musb-am33xx"; 544 compatible = "ti,musb-am33xx";
544 status = "disabled"; 545 status = "disabled";
545 reg = <0x47401c00 0x400 546 reg = <0x47401c00 0x400
546 0x47401800 0x200>; 547 0x47401800 0x200>;
547 reg-names = "mc", "control"; 548 reg-names = "mc", "control";
548 interrupts = <19>; 549 interrupts = <19>;
549 interrupt-names = "mc"; 550 interrupt-names = "mc";
550 dr_mode = "otg"; 551 dr_mode = "otg";
551 mentor,multipoint = <1>; 552 mentor,multipoint = <1>;
552 mentor,num-eps = <16>; 553 mentor,num-eps = <16>;
553 mentor,ram-bits = <12>; 554 mentor,ram-bits = <12>;
554 mentor,power = <500>; 555 mentor,power = <500>;
555 phys = <&usb1_phy>; 556 phys = <&usb1_phy>;
556 557
557 dmas = <&cppi41dma 15 0 &cppi41dma 16 0 558 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
558 &cppi41dma 17 0 &cppi41dma 18 0 559 &cppi41dma 17 0 &cppi41dma 18 0
559 &cppi41dma 19 0 &cppi41dma 20 0 560 &cppi41dma 19 0 &cppi41dma 20 0
560 &cppi41dma 21 0 &cppi41dma 22 0 561 &cppi41dma 21 0 &cppi41dma 22 0
561 &cppi41dma 23 0 &cppi41dma 24 0 562 &cppi41dma 23 0 &cppi41dma 24 0
562 &cppi41dma 25 0 &cppi41dma 26 0 563 &cppi41dma 25 0 &cppi41dma 26 0
563 &cppi41dma 27 0 &cppi41dma 28 0 564 &cppi41dma 27 0 &cppi41dma 28 0
564 &cppi41dma 29 0 &cppi41dma 15 1 565 &cppi41dma 29 0 &cppi41dma 15 1
565 &cppi41dma 16 1 &cppi41dma 17 1 566 &cppi41dma 16 1 &cppi41dma 17 1
566 &cppi41dma 18 1 &cppi41dma 19 1 567 &cppi41dma 18 1 &cppi41dma 19 1
567 &cppi41dma 20 1 &cppi41dma 21 1 568 &cppi41dma 20 1 &cppi41dma 21 1
568 &cppi41dma 22 1 &cppi41dma 23 1 569 &cppi41dma 22 1 &cppi41dma 23 1
569 &cppi41dma 24 1 &cppi41dma 25 1 570 &cppi41dma 24 1 &cppi41dma 25 1
570 &cppi41dma 26 1 &cppi41dma 27 1 571 &cppi41dma 26 1 &cppi41dma 27 1
571 &cppi41dma 28 1 &cppi41dma 29 1>; 572 &cppi41dma 28 1 &cppi41dma 29 1>;
572 dma-names = 573 dma-names =
573 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 574 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
574 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 575 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
575 "rx14", "rx15", 576 "rx14", "rx15",
576 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 577 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
577 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 578 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
578 "tx14", "tx15"; 579 "tx14", "tx15";
579 }; 580 };
580 581
581 cppi41dma: dma-controller@47402000 { 582 cppi41dma: dma-controller@47402000 {
582 compatible = "ti,am3359-cppi41"; 583 compatible = "ti,am3359-cppi41";
583 reg = <0x47400000 0x1000 584 reg = <0x47400000 0x1000
584 0x47402000 0x1000 585 0x47402000 0x1000
585 0x47403000 0x1000 586 0x47403000 0x1000
586 0x47404000 0x4000>; 587 0x47404000 0x4000>;
587 reg-names = "glue", "controller", "scheduler", "queuemgr"; 588 reg-names = "glue", "controller", "scheduler", "queuemgr";
588 interrupts = <17>; 589 interrupts = <17>;
589 interrupt-names = "glue"; 590 interrupt-names = "glue";
590 #dma-cells = <2>; 591 #dma-cells = <2>;
591 #dma-channels = <30>; 592 #dma-channels = <30>;
592 #dma-requests = <256>; 593 #dma-requests = <256>;
593 status = "disabled"; 594 status = "disabled";
594 }; 595 };
595 }; 596 };
596 597
597 epwmss0: epwmss@48300000 { 598 epwmss0: epwmss@48300000 {
598 compatible = "ti,am33xx-pwmss"; 599 compatible = "ti,am33xx-pwmss";
599 reg = <0x48300000 0x10>; 600 reg = <0x48300000 0x10>;
600 ti,hwmods = "epwmss0"; 601 ti,hwmods = "epwmss0";
601 #address-cells = <1>; 602 #address-cells = <1>;
602 #size-cells = <1>; 603 #size-cells = <1>;
603 status = "disabled"; 604 status = "disabled";
604 ranges = <0x48300100 0x48300100 0x80 /* ECAP */ 605 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
605 0x48300180 0x48300180 0x80 /* EQEP */ 606 0x48300180 0x48300180 0x80 /* EQEP */
606 0x48300200 0x48300200 0x80>; /* EHRPWM */ 607 0x48300200 0x48300200 0x80>; /* EHRPWM */
607 608
608 ecap0: ecap@48300100 { 609 ecap0: ecap@48300100 {
609 compatible = "ti,am33xx-ecap"; 610 compatible = "ti,am33xx-ecap";
610 #pwm-cells = <3>; 611 #pwm-cells = <3>;
611 reg = <0x48300100 0x80>; 612 reg = <0x48300100 0x80>;
612 ti,hwmods = "ecap0"; 613 ti,hwmods = "ecap0";
613 status = "disabled"; 614 status = "disabled";
614 }; 615 };
615 616
616 ehrpwm0: ehrpwm@48300200 { 617 ehrpwm0: ehrpwm@48300200 {
617 compatible = "ti,am33xx-ehrpwm"; 618 compatible = "ti,am33xx-ehrpwm";
618 #pwm-cells = <3>; 619 #pwm-cells = <3>;
619 reg = <0x48300200 0x80>; 620 reg = <0x48300200 0x80>;
620 ti,hwmods = "ehrpwm0"; 621 ti,hwmods = "ehrpwm0";
621 status = "disabled"; 622 status = "disabled";
622 }; 623 };
623 }; 624 };
624 625
625 epwmss1: epwmss@48302000 { 626 epwmss1: epwmss@48302000 {
626 compatible = "ti,am33xx-pwmss"; 627 compatible = "ti,am33xx-pwmss";
627 reg = <0x48302000 0x10>; 628 reg = <0x48302000 0x10>;
628 ti,hwmods = "epwmss1"; 629 ti,hwmods = "epwmss1";
629 #address-cells = <1>; 630 #address-cells = <1>;
630 #size-cells = <1>; 631 #size-cells = <1>;
631 status = "disabled"; 632 status = "disabled";
632 ranges = <0x48302100 0x48302100 0x80 /* ECAP */ 633 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
633 0x48302180 0x48302180 0x80 /* EQEP */ 634 0x48302180 0x48302180 0x80 /* EQEP */
634 0x48302200 0x48302200 0x80>; /* EHRPWM */ 635 0x48302200 0x48302200 0x80>; /* EHRPWM */
635 636
636 ecap1: ecap@48302100 { 637 ecap1: ecap@48302100 {
637 compatible = "ti,am33xx-ecap"; 638 compatible = "ti,am33xx-ecap";
638 #pwm-cells = <3>; 639 #pwm-cells = <3>;
639 reg = <0x48302100 0x80>; 640 reg = <0x48302100 0x80>;
640 ti,hwmods = "ecap1"; 641 ti,hwmods = "ecap1";
641 status = "disabled"; 642 status = "disabled";
642 }; 643 };
643 644
644 ehrpwm1: ehrpwm@48302200 { 645 ehrpwm1: ehrpwm@48302200 {
645 compatible = "ti,am33xx-ehrpwm"; 646 compatible = "ti,am33xx-ehrpwm";
646 #pwm-cells = <3>; 647 #pwm-cells = <3>;
647 reg = <0x48302200 0x80>; 648 reg = <0x48302200 0x80>;
648 ti,hwmods = "ehrpwm1"; 649 ti,hwmods = "ehrpwm1";
649 status = "disabled"; 650 status = "disabled";
650 }; 651 };
651 }; 652 };
652 653
653 epwmss2: epwmss@48304000 { 654 epwmss2: epwmss@48304000 {
654 compatible = "ti,am33xx-pwmss"; 655 compatible = "ti,am33xx-pwmss";
655 reg = <0x48304000 0x10>; 656 reg = <0x48304000 0x10>;
656 ti,hwmods = "epwmss2"; 657 ti,hwmods = "epwmss2";
657 #address-cells = <1>; 658 #address-cells = <1>;
658 #size-cells = <1>; 659 #size-cells = <1>;
659 status = "disabled"; 660 status = "disabled";
660 ranges = <0x48304100 0x48304100 0x80 /* ECAP */ 661 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
661 0x48304180 0x48304180 0x80 /* EQEP */ 662 0x48304180 0x48304180 0x80 /* EQEP */
662 0x48304200 0x48304200 0x80>; /* EHRPWM */ 663 0x48304200 0x48304200 0x80>; /* EHRPWM */
663 664
664 ecap2: ecap@48304100 { 665 ecap2: ecap@48304100 {
665 compatible = "ti,am33xx-ecap"; 666 compatible = "ti,am33xx-ecap";
666 #pwm-cells = <3>; 667 #pwm-cells = <3>;
667 reg = <0x48304100 0x80>; 668 reg = <0x48304100 0x80>;
668 ti,hwmods = "ecap2"; 669 ti,hwmods = "ecap2";
669 status = "disabled"; 670 status = "disabled";
670 }; 671 };
671 672
672 ehrpwm2: ehrpwm@48304200 { 673 ehrpwm2: ehrpwm@48304200 {
673 compatible = "ti,am33xx-ehrpwm"; 674 compatible = "ti,am33xx-ehrpwm";
674 #pwm-cells = <3>; 675 #pwm-cells = <3>;
675 reg = <0x48304200 0x80>; 676 reg = <0x48304200 0x80>;
676 ti,hwmods = "ehrpwm2"; 677 ti,hwmods = "ehrpwm2";
677 status = "disabled"; 678 status = "disabled";
678 }; 679 };
679 }; 680 };
680 681
681 mac: ethernet@4a100000 { 682 mac: ethernet@4a100000 {
682 compatible = "ti,cpsw"; 683 compatible = "ti,cpsw";
683 ti,hwmods = "cpgmac0"; 684 ti,hwmods = "cpgmac0";
684 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 685 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
685 clock-names = "fck", "cpts"; 686 clock-names = "fck", "cpts";
686 cpdma_channels = <8>; 687 cpdma_channels = <8>;
687 ale_entries = <1024>; 688 ale_entries = <1024>;
688 bd_ram_size = <0x2000>; 689 bd_ram_size = <0x2000>;
689 no_bd_ram = <0>; 690 no_bd_ram = <0>;
690 rx_descs = <64>; 691 rx_descs = <64>;
691 mac_control = <0x20>; 692 mac_control = <0x20>;
692 slaves = <2>; 693 slaves = <2>;
693 active_slave = <0>; 694 active_slave = <0>;
694 cpts_clock_mult = <0x80000000>; 695 cpts_clock_mult = <0x80000000>;
695 cpts_clock_shift = <29>; 696 cpts_clock_shift = <29>;
696 reg = <0x4a100000 0x800 697 reg = <0x4a100000 0x800
697 0x4a101200 0x100>; 698 0x4a101200 0x100>;
698 #address-cells = <1>; 699 #address-cells = <1>;
699 #size-cells = <1>; 700 #size-cells = <1>;
700 interrupt-parent = <&intc>; 701 interrupt-parent = <&intc>;
701 /* 702 /*
702 * c0_rx_thresh_pend 703 * c0_rx_thresh_pend
703 * c0_rx_pend 704 * c0_rx_pend
704 * c0_tx_pend 705 * c0_tx_pend
705 * c0_misc_pend 706 * c0_misc_pend
706 */ 707 */
707 interrupts = <40 41 42 43>; 708 interrupts = <40 41 42 43>;
708 ranges; 709 ranges;
709 710
710 davinci_mdio: mdio@4a101000 { 711 davinci_mdio: mdio@4a101000 {
711 compatible = "ti,davinci_mdio"; 712 compatible = "ti,davinci_mdio";
712 #address-cells = <1>; 713 #address-cells = <1>;
713 #size-cells = <0>; 714 #size-cells = <0>;
714 ti,hwmods = "davinci_mdio"; 715 ti,hwmods = "davinci_mdio";
715 bus_freq = <1000000>; 716 bus_freq = <1000000>;
716 reg = <0x4a101000 0x100>; 717 reg = <0x4a101000 0x100>;
717 }; 718 };
718 719
719 cpsw_emac0: slave@4a100200 { 720 cpsw_emac0: slave@4a100200 {
720 /* Filled in by U-Boot */ 721 /* Filled in by U-Boot */
721 mac-address = [ 00 00 00 00 00 00 ]; 722 mac-address = [ 00 00 00 00 00 00 ];
722 }; 723 };
723 724
724 cpsw_emac1: slave@4a100300 { 725 cpsw_emac1: slave@4a100300 {
725 /* Filled in by U-Boot */ 726 /* Filled in by U-Boot */
726 mac-address = [ 00 00 00 00 00 00 ]; 727 mac-address = [ 00 00 00 00 00 00 ];
727 }; 728 };
728 729
729 phy_sel: cpsw-phy-sel@44e10650 { 730 phy_sel: cpsw-phy-sel@44e10650 {
730 compatible = "ti,am3352-cpsw-phy-sel"; 731 compatible = "ti,am3352-cpsw-phy-sel";
731 reg= <0x44e10650 0x4>; 732 reg= <0x44e10650 0x4>;
732 reg-names = "gmii-sel"; 733 reg-names = "gmii-sel";
733 }; 734 };
734 }; 735 };
735 736
736 ocmcram: ocmcram@40300000 { 737 ocmcram: ocmcram@40300000 {
737 compatible = "ti,am3352-ocmcram"; 738 compatible = "ti,am3352-ocmcram";
738 reg = <0x40300000 0x10000>; 739 reg = <0x40300000 0x10000>;
739 ti,hwmods = "ocmcram"; 740 ti,hwmods = "ocmcram";
740 }; 741 };
741 742
742 wkup_m3: wkup_m3@44d00000 { 743 wkup_m3: wkup_m3@44d00000 {
743 compatible = "ti,am3353-wkup-m3"; 744 compatible = "ti,am3353-wkup-m3";
744 reg = <0x44d00000 0x4000 745 reg = <0x44d00000 0x4000
745 0x44d80000 0x2000 746 0x44d80000 0x2000
746 0x44e11324 0x0024>; 747 0x44e11324 0x0024>;
747 reg-names = "m3_umem", "m3_dmem", "ipc_regs"; 748 reg-names = "m3_umem", "m3_dmem", "ipc_regs";
748 interrupts = <78>; 749 interrupts = <78>;
749 ti,hwmods = "wkup_m3"; 750 ti,hwmods = "wkup_m3";
750 ti,no-reset-on-init; 751 ti,no-reset-on-init;
751 mboxes = <&mailbox &mbox_wkupm3>; 752 mboxes = <&mailbox &mbox_wkupm3>;
752 }; 753 };
753 754
754 pruss: pruss@4a300000 { 755 pruss: pruss@4a300000 {
755 compatible = "ti,am335x-pruss"; 756 compatible = "ti,am335x-pruss";
756 ti,hwmods = "pruss"; 757 ti,hwmods = "pruss";
757 reg = <0x4a300000 0x2000>, 758 reg = <0x4a300000 0x2000>,
758 <0x4a302000 0x2000>, 759 <0x4a302000 0x2000>,
759 <0x4a310000 0x3000>, 760 <0x4a310000 0x3000>,
760 <0x4a320000 0x2000>, 761 <0x4a320000 0x2000>,
761 <0x4a326000 0x2000>; 762 <0x4a326000 0x2000>;
762 reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg"; 763 reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg";
763 interrupts = <20 21 22 23 24 25 26 27>; 764 interrupts = <20 21 22 23 24 25 26 27>;
764 #address-cells = <1>; 765 #address-cells = <1>;
765 #size-cells = <1>; 766 #size-cells = <1>;
766 ranges; 767 ranges;
767 768
768 pru0: pru@4a334000 { 769 pru0: pru@4a334000 {
769 compatible = "ti,pru-rproc"; 770 compatible = "ti,pru-rproc";
770 reg = <0x4a334000 0x2000>, 771 reg = <0x4a334000 0x2000>,
771 <0x4a322000 0x400>, 772 <0x4a322000 0x400>,
772 <0x4a322400 0x100>; 773 <0x4a322400 0x100>;
773 reg-names = "iram", "control", "debug"; 774 reg-names = "iram", "control", "debug";
774 mboxes = <&mailbox &mbox_pru0>; 775 mboxes = <&mailbox &mbox_pru0>;
775 }; 776 };
776 777
777 pru1: pru@4a338000 { 778 pru1: pru@4a338000 {
778 compatible = "ti,pru-rproc"; 779 compatible = "ti,pru-rproc";
779 reg = <0x4a338000 0x2000>, 780 reg = <0x4a338000 0x2000>,
780 <0x4a324000 0x400>, 781 <0x4a324000 0x400>,
781 <0x4a324400 0x100>; 782 <0x4a324400 0x100>;
782 reg-names = "iram", "control", "debug"; 783 reg-names = "iram", "control", "debug";
783 mboxes = <&mailbox &mbox_pru1>; 784 mboxes = <&mailbox &mbox_pru1>;
784 }; 785 };
785 }; 786 };
786 787
787 elm: elm@48080000 { 788 elm: elm@48080000 {
788 compatible = "ti,am3352-elm"; 789 compatible = "ti,am3352-elm";
789 reg = <0x48080000 0x2000>; 790 reg = <0x48080000 0x2000>;
790 interrupts = <4>; 791 interrupts = <4>;
791 ti,hwmods = "elm"; 792 ti,hwmods = "elm";
792 status = "disabled"; 793 status = "disabled";
793 }; 794 };
794 795
795 lcdc: lcdc@4830e000 { 796 lcdc: lcdc@4830e000 {
796 compatible = "ti,am33xx-tilcdc"; 797 compatible = "ti,am33xx-tilcdc";
797 reg = <0x4830e000 0x1000>; 798 reg = <0x4830e000 0x1000>;
798 interrupt-parent = <&intc>; 799 interrupt-parent = <&intc>;
799 interrupts = <36>; 800 interrupts = <36>;
800 ti,hwmods = "lcdc"; 801 ti,hwmods = "lcdc";
801 status = "disabled"; 802 status = "disabled";
802 }; 803 };
803 804
804 tscadc: tscadc@44e0d000 { 805 tscadc: tscadc@44e0d000 {
805 compatible = "ti,am3359-tscadc"; 806 compatible = "ti,am3359-tscadc";
806 reg = <0x44e0d000 0x1000>; 807 reg = <0x44e0d000 0x1000>;
807 interrupt-parent = <&intc>; 808 interrupt-parent = <&intc>;
808 interrupts = <16>; 809 interrupts = <16>;
809 ti,hwmods = "adc_tsc"; 810 ti,hwmods = "adc_tsc";
810 status = "disabled"; 811 status = "disabled";
811 812
812 tsc { 813 tsc {
813 compatible = "ti,am3359-tsc"; 814 compatible = "ti,am3359-tsc";
814 }; 815 };
815 am335x_adc: adc { 816 am335x_adc: adc {
816 #io-channel-cells = <1>; 817 #io-channel-cells = <1>;
817 compatible = "ti,am3359-adc"; 818 compatible = "ti,am3359-adc";
818 }; 819 };
819 }; 820 };
820 821
821 gpmc: gpmc@50000000 { 822 gpmc: gpmc@50000000 {
822 compatible = "ti,am3352-gpmc"; 823 compatible = "ti,am3352-gpmc";
823 ti,hwmods = "gpmc"; 824 ti,hwmods = "gpmc";
824 ti,no-idle-on-init; 825 ti,no-idle-on-init;
825 reg = <0x50000000 0x2000>; 826 reg = <0x50000000 0x2000>;
826 interrupts = <100>; 827 interrupts = <100>;
827 gpmc,num-cs = <7>; 828 gpmc,num-cs = <7>;
828 gpmc,num-waitpins = <2>; 829 gpmc,num-waitpins = <2>;
829 #address-cells = <2>; 830 #address-cells = <2>;
830 #size-cells = <1>; 831 #size-cells = <1>;
831 status = "disabled"; 832 status = "disabled";
832 }; 833 };
833 834
834 sham: sham@53100000 { 835 sham: sham@53100000 {
835 compatible = "ti,omap4-sham"; 836 compatible = "ti,omap4-sham";
836 ti,hwmods = "sham"; 837 ti,hwmods = "sham";
837 reg = <0x53100000 0x200>; 838 reg = <0x53100000 0x200>;
838 interrupts = <109>; 839 interrupts = <109>;
839 dmas = <&edma 36>; 840 dmas = <&edma 36>;
840 dma-names = "rx"; 841 dma-names = "rx";
841 }; 842 };
842 843
843 aes: aes@53500000 { 844 aes: aes@53500000 {
844 compatible = "ti,omap4-aes"; 845 compatible = "ti,omap4-aes";
845 ti,hwmods = "aes"; 846 ti,hwmods = "aes";
846 reg = <0x53500000 0xa0>; 847 reg = <0x53500000 0xa0>;
847 interrupts = <103>; 848 interrupts = <103>;
848 dmas = <&edma 6>, 849 dmas = <&edma 6>,
849 <&edma 5>; 850 <&edma 5>;
850 dma-names = "tx", "rx"; 851 dma-names = "tx", "rx";
851 }; 852 };
852 853
853 mcasp0: mcasp@48038000 { 854 mcasp0: mcasp@48038000 {
854 compatible = "ti,am33xx-mcasp-audio"; 855 compatible = "ti,am33xx-mcasp-audio";
855 ti,hwmods = "mcasp0"; 856 ti,hwmods = "mcasp0";
856 reg = <0x48038000 0x2000>, 857 reg = <0x48038000 0x2000>,
857 <0x46000000 0x400000>; 858 <0x46000000 0x400000>;
858 reg-names = "mpu", "dat"; 859 reg-names = "mpu", "dat";
859 interrupts = <80>, <81>; 860 interrupts = <80>, <81>;
860 interrupts-names = "tx", "rx"; 861 interrupts-names = "tx", "rx";
861 status = "disabled"; 862 status = "disabled";
862 dmas = <&edma 8>, 863 dmas = <&edma 8>,
863 <&edma 9>; 864 <&edma 9>;
864 dma-names = "tx", "rx"; 865 dma-names = "tx", "rx";
865 }; 866 };
866 867
867 mcasp1: mcasp@4803C000 { 868 mcasp1: mcasp@4803C000 {
868 compatible = "ti,am33xx-mcasp-audio"; 869 compatible = "ti,am33xx-mcasp-audio";
869 ti,hwmods = "mcasp1"; 870 ti,hwmods = "mcasp1";
870 reg = <0x4803C000 0x2000>, 871 reg = <0x4803C000 0x2000>,
871 <0x46400000 0x400000>; 872 <0x46400000 0x400000>;
872 reg-names = "mpu", "dat"; 873 reg-names = "mpu", "dat";
873 interrupts = <82>, <83>; 874 interrupts = <82>, <83>;
874 interrupts-names = "tx", "rx"; 875 interrupts-names = "tx", "rx";
875 status = "disabled"; 876 status = "disabled";
876 dmas = <&edma 10>, 877 dmas = <&edma 10>,
877 <&edma 11>; 878 <&edma 11>;
878 dma-names = "tx", "rx"; 879 dma-names = "tx", "rx";
879 }; 880 };
880 881
881 rng: rng@48310000 { 882 rng: rng@48310000 {
882 compatible = "ti,omap4-rng"; 883 compatible = "ti,omap4-rng";
883 ti,hwmods = "rng"; 884 ti,hwmods = "rng";
884 reg = <0x48310000 0x2000>; 885 reg = <0x48310000 0x2000>;
885 interrupts = <111>; 886 interrupts = <111>;
886 }; 887 };
887 888
888 sgx@0x56000000 { 889 sgx@0x56000000 {
889 compatible = "ti,sgx"; 890 compatible = "ti,sgx";
890 ti,hwmods = "gfx"; 891 ti,hwmods = "gfx";
891 reg = <0x56000000 0x1000000>; 892 reg = <0x56000000 0x1000000>;
892 interrupts = <37>; 893 interrupts = <37>;
893 }; 894 };
894 }; 895 };
895 }; 896 };
896 897
897 /include/ "am33xx-clocks.dtsi" 898 /include/ "am33xx-clocks.dtsi"
898 899
arch/arm/boot/dts/am4372.dtsi
Diff comments   View file @ 14ed5c8
1 /* 1 /*
2 * Device Tree Source for AM4372 SoC 2 * Device Tree Source for AM4372 SoC
3 * 3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public License 6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any 7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 13
14 #include "skeleton.dtsi" 14 #include "skeleton.dtsi"
15 15
16 / { 16 / {
17 compatible = "ti,am4372", "ti,am43"; 17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 19
20 20
21 aliases { 21 aliases {
22 i2c0 = &i2c0; 22 i2c0 = &i2c0;
23 i2c1 = &i2c1; 23 i2c1 = &i2c1;
24 i2c2 = &i2c2; 24 i2c2 = &i2c2;
25 serial0 = &uart0; 25 serial0 = &uart0;
26 ethernet0 = &cpsw_emac0; 26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1; 27 ethernet1 = &cpsw_emac1;
28 d_can0 = &dcan0; 28 d_can0 = &dcan0;
29 d_can1 = &dcan1; 29 d_can1 = &dcan1;
30 }; 30 };
31 31
32 cpus { 32 cpus {
33 #address-cells = <1>; 33 #address-cells = <1>;
34 #size-cells = <0>; 34 #size-cells = <0>;
35 cpu: cpu@0 { 35 cpu: cpu@0 {
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 device_type = "cpu"; 37 device_type = "cpu";
38 reg = <0>; 38 reg = <0>;
39 39
40 clocks = <&dpll_mpu_ck>; 40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu"; 41 clock-names = "cpu";
42 42
43 /* 43 /*
44 * To consider voltage drop between PMIC and SoC, 44 * To consider voltage drop between PMIC and SoC,
45 * tolerance value is reduced to 2% from 4% and 45 * tolerance value is reduced to 2% from 4% and
46 * voltage value is increased as a precaution. 46 * voltage value is increased as a precaution.
47 */ 47 */
48 voltage-tolerance = <2>; 48 voltage-tolerance = <2>;
49 49
50 clock-latency = <300000>; /* From omap-cpufreq driver */ 50 clock-latency = <300000>; /* From omap-cpufreq driver */
51 }; 51 };
52 }; 52 };
53 53
54 gic: interrupt-controller@48241000 { 54 gic: interrupt-controller@48241000 {
55 compatible = "arm,cortex-a9-gic"; 55 compatible = "arm,cortex-a9-gic";
56 interrupt-controller; 56 interrupt-controller;
57 #interrupt-cells = <3>; 57 #interrupt-cells = <3>;
58 reg = <0x48241000 0x1000>, 58 reg = <0x48241000 0x1000>,
59 <0x48240100 0x0100>; 59 <0x48240100 0x0100>;
60 }; 60 };
61 61
62 l2-cache-controller@48242000 { 62 l2-cache-controller@48242000 {
63 compatible = "arm,pl310-cache"; 63 compatible = "arm,pl310-cache";
64 reg = <0x48242000 0x1000>; 64 reg = <0x48242000 0x1000>;
65 cache-unified; 65 cache-unified;
66 cache-level = <2>; 66 cache-level = <2>;
67 }; 67 };
68 68
69 am43xx_control_module: control_module@4a002000 { 69 am43xx_control_module: control_module@4a002000 {
70 compatible = "syscon"; 70 compatible = "syscon";
71 reg = <0x44e10000 0x7f4>; 71 reg = <0x44e10000 0x7f4>;
72 }; 72 };
73 73
74 am43xx_pinmux: pinmux@44e10800 { 74 am43xx_pinmux: pinmux@44e10800 {
75 compatible = "ti,am437-padconf", "pinctrl-single"; 75 compatible = "ti,am437-padconf", "pinctrl-single";
76 reg = <0x44e10800 0x31c>; 76 reg = <0x44e10800 0x31c>;
77 #address-cells = <1>; 77 #address-cells = <1>;
78 #size-cells = <0>; 78 #size-cells = <0>;
79 #interrupt-cells = <1>; 79 #interrupt-cells = <1>;
80 interrupt-controller; 80 interrupt-controller;
81 pinctrl-single,register-width = <32>; 81 pinctrl-single,register-width = <32>;
82 pinctrl-single,function-mask = <0xffffffff>; 82 pinctrl-single,function-mask = <0xffffffff>;
83 }; 83 };
84 84
85 ocp { 85 ocp {
86 compatible = "ti,am4372-l3-noc", "simple-bus"; 86 compatible = "ti,am4372-l3-noc", "simple-bus";
87 #address-cells = <1>; 87 #address-cells = <1>;
88 #size-cells = <1>; 88 #size-cells = <1>;
89 ranges; 89 ranges;
90 ti,hwmods = "l3_main"; 90 ti,hwmods = "l3_main";
91 reg = <0x44000000 0x400000 91 reg = <0x44000000 0x400000
92 0x44800000 0x400000>; 92 0x44800000 0x400000>;
93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
95 95
96 emif: emif@4c000000 { 96 emif: emif@4c000000 {
97 reg = <0x4c000000 0x1000000>; 97 reg = <0x4c000000 0x1000000>;
98 ti,hwmods = "emif"; 98 ti,hwmods = "emif";
99 }; 99 };
100 100
101 prcm: prcm@44df0000 { 101 prcm: prcm@44df0000 {
102 compatible = "ti,am4-prcm"; 102 compatible = "ti,am4-prcm";
103 reg = <0x44df0000 0x11000>; 103 reg = <0x44df0000 0x11000>;
104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
105 105
106 prcm_clocks: clocks { 106 prcm_clocks: clocks {
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <0>; 108 #size-cells = <0>;
109 }; 109 };
110 110
111 prcm_clockdomains: clockdomains { 111 prcm_clockdomains: clockdomains {
112 }; 112 };
113 }; 113 };
114 114
115 scrm: scrm@44e10000 { 115 scrm: scrm@44e10000 {
116 compatible = "ti,am4-scrm"; 116 compatible = "ti,am4-scrm";
117 reg = <0x44e10000 0x2000>; 117 reg = <0x44e10000 0x2000>;
118 118
119 scrm_clocks: clocks { 119 scrm_clocks: clocks {
120 #address-cells = <1>; 120 #address-cells = <1>;
121 #size-cells = <0>; 121 #size-cells = <0>;
122 }; 122 };
123 123
124 scrm_clockdomains: clockdomains { 124 scrm_clockdomains: clockdomains {
125 }; 125 };
126 }; 126 };
127 127
128 edma: edma@49000000 { 128 edma: edma@49000000 {
129 compatible = "ti,edma3"; 129 compatible = "ti,edma3";
130 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; 130 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
131 reg = <0x49000000 0x10000>, 131 reg = <0x49000000 0x10000>,
132 <0x44e10f90 0x10>; 132 <0x44e10f90 0x10>;
133 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 133 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 135 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
136 #dma-cells = <1>; 136 #dma-cells = <1>;
137 }; 137 };
138 138
139 uart0: serial@44e09000 { 139 uart0: serial@44e09000 {
140 compatible = "ti,am4372-uart","ti,omap2-uart"; 140 compatible = "ti,am4372-uart","ti,omap2-uart";
141 reg = <0x44e09000 0x2000>; 141 reg = <0x44e09000 0x2000>;
142 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 142 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
143 ti,hwmods = "uart1"; 143 ti,hwmods = "uart1";
144 }; 144 };
145 145
146 uart1: serial@48022000 { 146 uart1: serial@48022000 {
147 compatible = "ti,am4372-uart","ti,omap2-uart"; 147 compatible = "ti,am4372-uart","ti,omap2-uart";
148 reg = <0x48022000 0x2000>; 148 reg = <0x48022000 0x2000>;
149 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 149 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
150 ti,hwmods = "uart2"; 150 ti,hwmods = "uart2";
151 status = "disabled"; 151 status = "disabled";
152 }; 152 };
153 153
154 uart2: serial@48024000 { 154 uart2: serial@48024000 {
155 compatible = "ti,am4372-uart","ti,omap2-uart"; 155 compatible = "ti,am4372-uart","ti,omap2-uart";
156 reg = <0x48024000 0x2000>; 156 reg = <0x48024000 0x2000>;
157 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 157 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
158 ti,hwmods = "uart3"; 158 ti,hwmods = "uart3";
159 status = "disabled"; 159 status = "disabled";
160 }; 160 };
161 161
162 uart3: serial@481a6000 { 162 uart3: serial@481a6000 {
163 compatible = "ti,am4372-uart","ti,omap2-uart"; 163 compatible = "ti,am4372-uart","ti,omap2-uart";
164 reg = <0x481a6000 0x2000>; 164 reg = <0x481a6000 0x2000>;
165 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 165 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
166 ti,hwmods = "uart4"; 166 ti,hwmods = "uart4";
167 status = "disabled"; 167 status = "disabled";
168 }; 168 };
169 169
170 uart4: serial@481a8000 { 170 uart4: serial@481a8000 {
171 compatible = "ti,am4372-uart","ti,omap2-uart"; 171 compatible = "ti,am4372-uart","ti,omap2-uart";
172 reg = <0x481a8000 0x2000>; 172 reg = <0x481a8000 0x2000>;
173 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
174 ti,hwmods = "uart5"; 174 ti,hwmods = "uart5";
175 status = "disabled"; 175 status = "disabled";
176 }; 176 };
177 177
178 uart5: serial@481aa000 { 178 uart5: serial@481aa000 {
179 compatible = "ti,am4372-uart","ti,omap2-uart"; 179 compatible = "ti,am4372-uart","ti,omap2-uart";
180 reg = <0x481aa000 0x2000>; 180 reg = <0x481aa000 0x2000>;
181 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 181 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "uart6"; 182 ti,hwmods = "uart6";
183 status = "disabled"; 183 status = "disabled";
184 }; 184 };
185 185
186 mailbox: mailbox@480C8000 { 186 mailbox: mailbox@480C8000 {
187 compatible = "ti,omap4-mailbox"; 187 compatible = "ti,omap4-mailbox";
188 reg = <0x480C8000 0x200>; 188 reg = <0x480C8000 0x200>;
189 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 189 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
190 ti,hwmods = "mailbox"; 190 ti,hwmods = "mailbox";
191 #mbox-cells = <1>; 191 #mbox-cells = <1>;
192 ti,mbox-num-users = <4>; 192 ti,mbox-num-users = <4>;
193 ti,mbox-num-fifos = <8>; 193 ti,mbox-num-fifos = <8>;
194 194
195 mbox_wkupm3: wkup_m3 { 195 mbox_wkupm3: wkup_m3 {
196 ti,mbox-send-noirq;
196 ti,mbox-tx = <0 0 0>; 197 ti,mbox-tx = <0 0 0>;
197 ti,mbox-rx = <0 0 3>; 198 ti,mbox-rx = <0 0 3>;
198 }; 199 };
199 mbox_pru0: mbox_pru0 { 200 mbox_pru0: mbox_pru0 {
200 ti,mbox-tx = <2 0 0>; 201 ti,mbox-tx = <2 0 0>;
201 ti,mbox-rx = <3 0 0>; 202 ti,mbox-rx = <3 0 0>;
202 }; 203 };
203 mbox_pru1: mbox_pru1 { 204 mbox_pru1: mbox_pru1 {
204 ti,mbox-tx = <4 0 0>; 205 ti,mbox-tx = <4 0 0>;
205 ti,mbox-rx = <5 0 0>; 206 ti,mbox-rx = <5 0 0>;
206 }; 207 };
207 }; 208 };
208 209
209 timer1: timer@44e31000 { 210 timer1: timer@44e31000 {
210 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; 211 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
211 reg = <0x44e31000 0x400>; 212 reg = <0x44e31000 0x400>;
212 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 213 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
213 ti,timer-alwon; 214 ti,timer-alwon;
214 ti,hwmods = "timer1"; 215 ti,hwmods = "timer1";
215 }; 216 };
216 217
217 timer2: timer@48040000 { 218 timer2: timer@48040000 {
218 compatible = "ti,am4372-timer","ti,am335x-timer"; 219 compatible = "ti,am4372-timer","ti,am335x-timer";
219 reg = <0x48040000 0x400>; 220 reg = <0x48040000 0x400>;
220 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 221 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
221 ti,hwmods = "timer2"; 222 ti,hwmods = "timer2";
222 }; 223 };
223 224
224 timer3: timer@48042000 { 225 timer3: timer@48042000 {
225 compatible = "ti,am4372-timer","ti,am335x-timer"; 226 compatible = "ti,am4372-timer","ti,am335x-timer";
226 reg = <0x48042000 0x400>; 227 reg = <0x48042000 0x400>;
227 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
228 ti,hwmods = "timer3"; 229 ti,hwmods = "timer3";
229 status = "disabled"; 230 status = "disabled";
230 }; 231 };
231 232
232 timer4: timer@48044000 { 233 timer4: timer@48044000 {
233 compatible = "ti,am4372-timer","ti,am335x-timer"; 234 compatible = "ti,am4372-timer","ti,am335x-timer";
234 reg = <0x48044000 0x400>; 235 reg = <0x48044000 0x400>;
235 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 236 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
236 ti,timer-pwm; 237 ti,timer-pwm;
237 ti,hwmods = "timer4"; 238 ti,hwmods = "timer4";
238 status = "disabled"; 239 status = "disabled";
239 }; 240 };
240 241
241 timer5: timer@48046000 { 242 timer5: timer@48046000 {
242 compatible = "ti,am4372-timer","ti,am335x-timer"; 243 compatible = "ti,am4372-timer","ti,am335x-timer";
243 reg = <0x48046000 0x400>; 244 reg = <0x48046000 0x400>;
244 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 245 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
245 ti,timer-pwm; 246 ti,timer-pwm;
246 ti,hwmods = "timer5"; 247 ti,hwmods = "timer5";
247 status = "disabled"; 248 status = "disabled";
248 }; 249 };
249 250
250 timer6: timer@48048000 { 251 timer6: timer@48048000 {
251 compatible = "ti,am4372-timer","ti,am335x-timer"; 252 compatible = "ti,am4372-timer","ti,am335x-timer";
252 reg = <0x48048000 0x400>; 253 reg = <0x48048000 0x400>;
253 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 254 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
254 ti,timer-pwm; 255 ti,timer-pwm;
255 ti,hwmods = "timer6"; 256 ti,hwmods = "timer6";
256 status = "disabled"; 257 status = "disabled";
257 }; 258 };
258 259
259 timer7: timer@4804a000 { 260 timer7: timer@4804a000 {
260 compatible = "ti,am4372-timer","ti,am335x-timer"; 261 compatible = "ti,am4372-timer","ti,am335x-timer";
261 reg = <0x4804a000 0x400>; 262 reg = <0x4804a000 0x400>;
262 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
263 ti,timer-pwm; 264 ti,timer-pwm;
264 ti,hwmods = "timer7"; 265 ti,hwmods = "timer7";
265 status = "disabled"; 266 status = "disabled";
266 }; 267 };
267 268
268 timer8: timer@481c1000 { 269 timer8: timer@481c1000 {
269 compatible = "ti,am4372-timer","ti,am335x-timer"; 270 compatible = "ti,am4372-timer","ti,am335x-timer";
270 reg = <0x481c1000 0x400>; 271 reg = <0x481c1000 0x400>;
271 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 272 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
272 ti,hwmods = "timer8"; 273 ti,hwmods = "timer8";
273 status = "disabled"; 274 status = "disabled";
274 }; 275 };
275 276
276 timer9: timer@4833d000 { 277 timer9: timer@4833d000 {
277 compatible = "ti,am4372-timer","ti,am335x-timer"; 278 compatible = "ti,am4372-timer","ti,am335x-timer";
278 reg = <0x4833d000 0x400>; 279 reg = <0x4833d000 0x400>;
279 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 280 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
280 ti,hwmods = "timer9"; 281 ti,hwmods = "timer9";
281 status = "disabled"; 282 status = "disabled";
282 }; 283 };
283 284
284 timer10: timer@4833f000 { 285 timer10: timer@4833f000 {
285 compatible = "ti,am4372-timer","ti,am335x-timer"; 286 compatible = "ti,am4372-timer","ti,am335x-timer";
286 reg = <0x4833f000 0x400>; 287 reg = <0x4833f000 0x400>;
287 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 288 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
288 ti,hwmods = "timer10"; 289 ti,hwmods = "timer10";
289 status = "disabled"; 290 status = "disabled";
290 }; 291 };
291 292
292 timer11: timer@48341000 { 293 timer11: timer@48341000 {
293 compatible = "ti,am4372-timer","ti,am335x-timer"; 294 compatible = "ti,am4372-timer","ti,am335x-timer";
294 reg = <0x48341000 0x400>; 295 reg = <0x48341000 0x400>;
295 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 296 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
296 ti,hwmods = "timer11"; 297 ti,hwmods = "timer11";
297 status = "disabled"; 298 status = "disabled";
298 }; 299 };
299 300
300 counter32k: counter@44e86000 { 301 counter32k: counter@44e86000 {
301 compatible = "ti,am4372-counter32k","ti,omap-counter32k"; 302 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
302 reg = <0x44e86000 0x40>; 303 reg = <0x44e86000 0x40>;
303 ti,hwmods = "counter_32k"; 304 ti,hwmods = "counter_32k";
304 }; 305 };
305 306
306 rtc: rtc@44e3e000 { 307 rtc: rtc@44e3e000 {
307 compatible = "ti,am3352-rtc", "ti,am4372-rtc"; 308 compatible = "ti,am3352-rtc", "ti,am4372-rtc";
308 reg = <0x44e3e000 0x1000>; 309 reg = <0x44e3e000 0x1000>;
309 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH 310 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 311 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
311 ti,hwmods = "rtc"; 312 ti,hwmods = "rtc";
312 ti,system-power-controller; 313 ti,system-power-controller;
313 status = "disabled"; 314 status = "disabled";
314 }; 315 };
315 316
316 wdt: wdt@44e35000 { 317 wdt: wdt@44e35000 {
317 compatible = "ti,am4372-wdt","ti,omap3-wdt"; 318 compatible = "ti,am4372-wdt","ti,omap3-wdt";
318 reg = <0x44e35000 0x1000>; 319 reg = <0x44e35000 0x1000>;
319 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 320 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "wd_timer2"; 321 ti,hwmods = "wd_timer2";
321 }; 322 };
322 323
323 gpio0: gpio@44e07000 { 324 gpio0: gpio@44e07000 {
324 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 325 compatible = "ti,am4372-gpio","ti,omap4-gpio";
325 reg = <0x44e07000 0x1000>; 326 reg = <0x44e07000 0x1000>;
326 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 327 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
327 gpio-controller; 328 gpio-controller;
328 #gpio-cells = <2>; 329 #gpio-cells = <2>;
329 interrupt-controller; 330 interrupt-controller;
330 #interrupt-cells = <2>; 331 #interrupt-cells = <2>;
331 ti,hwmods = "gpio1"; 332 ti,hwmods = "gpio1";
332 status = "disabled"; 333 status = "disabled";
333 }; 334 };
334 335
335 gpio1: gpio@4804c000 { 336 gpio1: gpio@4804c000 {
336 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 337 compatible = "ti,am4372-gpio","ti,omap4-gpio";
337 reg = <0x4804c000 0x1000>; 338 reg = <0x4804c000 0x1000>;
338 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 339 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
339 gpio-controller; 340 gpio-controller;
340 #gpio-cells = <2>; 341 #gpio-cells = <2>;
341 interrupt-controller; 342 interrupt-controller;
342 #interrupt-cells = <2>; 343 #interrupt-cells = <2>;
343 ti,hwmods = "gpio2"; 344 ti,hwmods = "gpio2";
344 status = "disabled"; 345 status = "disabled";
345 }; 346 };
346 347
347 gpio2: gpio@481ac000 { 348 gpio2: gpio@481ac000 {
348 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 349 compatible = "ti,am4372-gpio","ti,omap4-gpio";
349 reg = <0x481ac000 0x1000>; 350 reg = <0x481ac000 0x1000>;
350 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 351 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
351 gpio-controller; 352 gpio-controller;
352 #gpio-cells = <2>; 353 #gpio-cells = <2>;
353 interrupt-controller; 354 interrupt-controller;
354 #interrupt-cells = <2>; 355 #interrupt-cells = <2>;
355 ti,hwmods = "gpio3"; 356 ti,hwmods = "gpio3";
356 status = "disabled"; 357 status = "disabled";
357 }; 358 };
358 359
359 gpio3: gpio@481ae000 { 360 gpio3: gpio@481ae000 {
360 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 361 compatible = "ti,am4372-gpio","ti,omap4-gpio";
361 reg = <0x481ae000 0x1000>; 362 reg = <0x481ae000 0x1000>;
362 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 363 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
363 gpio-controller; 364 gpio-controller;
364 #gpio-cells = <2>; 365 #gpio-cells = <2>;
365 interrupt-controller; 366 interrupt-controller;
366 #interrupt-cells = <2>; 367 #interrupt-cells = <2>;
367 ti,hwmods = "gpio4"; 368 ti,hwmods = "gpio4";
368 status = "disabled"; 369 status = "disabled";
369 }; 370 };
370 371
371 gpio4: gpio@48320000 { 372 gpio4: gpio@48320000 {
372 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 373 compatible = "ti,am4372-gpio","ti,omap4-gpio";
373 reg = <0x48320000 0x1000>; 374 reg = <0x48320000 0x1000>;
374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 375 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
375 gpio-controller; 376 gpio-controller;
376 #gpio-cells = <2>; 377 #gpio-cells = <2>;
377 interrupt-controller; 378 interrupt-controller;
378 #interrupt-cells = <2>; 379 #interrupt-cells = <2>;
379 ti,hwmods = "gpio5"; 380 ti,hwmods = "gpio5";
380 status = "disabled"; 381 status = "disabled";
381 }; 382 };
382 383
383 gpio5: gpio@48322000 { 384 gpio5: gpio@48322000 {
384 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 385 compatible = "ti,am4372-gpio","ti,omap4-gpio";
385 reg = <0x48322000 0x1000>; 386 reg = <0x48322000 0x1000>;
386 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
387 gpio-controller; 388 gpio-controller;
388 #gpio-cells = <2>; 389 #gpio-cells = <2>;
389 interrupt-controller; 390 interrupt-controller;
390 #interrupt-cells = <2>; 391 #interrupt-cells = <2>;
391 ti,hwmods = "gpio6"; 392 ti,hwmods = "gpio6";
392 status = "disabled"; 393 status = "disabled";
393 }; 394 };
394 395
395 hwspinlock: spinlock@480ca000 { 396 hwspinlock: spinlock@480ca000 {
396 compatible = "ti,omap4-hwspinlock"; 397 compatible = "ti,omap4-hwspinlock";
397 reg = <0x480ca000 0x1000>; 398 reg = <0x480ca000 0x1000>;
398 ti,hwmods = "spinlock"; 399 ti,hwmods = "spinlock";
399 #hwlock-cells = <1>; 400 #hwlock-cells = <1>;
400 }; 401 };
401 402
402 i2c0: i2c@44e0b000 { 403 i2c0: i2c@44e0b000 {
403 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 404 compatible = "ti,am4372-i2c","ti,omap4-i2c";
404 reg = <0x44e0b000 0x1000>; 405 reg = <0x44e0b000 0x1000>;
405 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 406 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "i2c1"; 407 ti,hwmods = "i2c1";
407 #address-cells = <1>; 408 #address-cells = <1>;
408 #size-cells = <0>; 409 #size-cells = <0>;
409 status = "disabled"; 410 status = "disabled";
410 }; 411 };
411 412
412 i2c1: i2c@4802a000 { 413 i2c1: i2c@4802a000 {
413 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 414 compatible = "ti,am4372-i2c","ti,omap4-i2c";
414 reg = <0x4802a000 0x1000>; 415 reg = <0x4802a000 0x1000>;
415 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 416 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "i2c2"; 417 ti,hwmods = "i2c2";
417 #address-cells = <1>; 418 #address-cells = <1>;
418 #size-cells = <0>; 419 #size-cells = <0>;
419 status = "disabled"; 420 status = "disabled";
420 }; 421 };
421 422
422 i2c2: i2c@4819c000 { 423 i2c2: i2c@4819c000 {
423 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 424 compatible = "ti,am4372-i2c","ti,omap4-i2c";
424 reg = <0x4819c000 0x1000>; 425 reg = <0x4819c000 0x1000>;
425 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 426 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
426 ti,hwmods = "i2c3"; 427 ti,hwmods = "i2c3";
427 #address-cells = <1>; 428 #address-cells = <1>;
428 #size-cells = <0>; 429 #size-cells = <0>;
429 status = "disabled"; 430 status = "disabled";
430 }; 431 };
431 432
432 spi0: spi@48030000 { 433 spi0: spi@48030000 {
433 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 434 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
434 reg = <0x48030000 0x400>; 435 reg = <0x48030000 0x400>;
435 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 436 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "spi0"; 437 ti,hwmods = "spi0";
437 #address-cells = <1>; 438 #address-cells = <1>;
438 #size-cells = <0>; 439 #size-cells = <0>;
439 status = "disabled"; 440 status = "disabled";
440 }; 441 };
441 442
442 mmc1: mmc@48060000 { 443 mmc1: mmc@48060000 {
443 compatible = "ti,omap4-hsmmc"; 444 compatible = "ti,omap4-hsmmc";
444 reg = <0x48060000 0x1000>; 445 reg = <0x48060000 0x1000>;
445 ti,hwmods = "mmc1"; 446 ti,hwmods = "mmc1";
446 ti,dual-volt; 447 ti,dual-volt;
447 ti,needs-special-reset; 448 ti,needs-special-reset;
448 dmas = <&edma 24 449 dmas = <&edma 24
449 &edma 25>; 450 &edma 25>;
450 dma-names = "tx", "rx"; 451 dma-names = "tx", "rx";
451 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 452 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
452 status = "disabled"; 453 status = "disabled";
453 }; 454 };
454 455
455 mmc2: mmc@481d8000 { 456 mmc2: mmc@481d8000 {
456 compatible = "ti,omap4-hsmmc"; 457 compatible = "ti,omap4-hsmmc";
457 reg = <0x481d8000 0x1000>; 458 reg = <0x481d8000 0x1000>;
458 ti,hwmods = "mmc2"; 459 ti,hwmods = "mmc2";
459 ti,needs-special-reset; 460 ti,needs-special-reset;
460 dmas = <&edma 2 461 dmas = <&edma 2
461 &edma 3>; 462 &edma 3>;
462 dma-names = "tx", "rx"; 463 dma-names = "tx", "rx";
463 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 464 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
464 status = "disabled"; 465 status = "disabled";
465 }; 466 };
466 467
467 mmc3: mmc@47810000 { 468 mmc3: mmc@47810000 {
468 compatible = "ti,omap4-hsmmc"; 469 compatible = "ti,omap4-hsmmc";
469 reg = <0x47810000 0x1000>; 470 reg = <0x47810000 0x1000>;
470 ti,hwmods = "mmc3"; 471 ti,hwmods = "mmc3";
471 ti,needs-special-reset; 472 ti,needs-special-reset;
472 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 473 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
473 status = "disabled"; 474 status = "disabled";
474 }; 475 };
475 476
476 spi1: spi@481a0000 { 477 spi1: spi@481a0000 {
477 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 478 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
478 reg = <0x481a0000 0x400>; 479 reg = <0x481a0000 0x400>;
479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 480 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "spi1"; 481 ti,hwmods = "spi1";
481 #address-cells = <1>; 482 #address-cells = <1>;
482 #size-cells = <0>; 483 #size-cells = <0>;
483 status = "disabled"; 484 status = "disabled";
484 }; 485 };
485 486
486 spi2: spi@481a2000 { 487 spi2: spi@481a2000 {
487 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 488 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
488 reg = <0x481a2000 0x400>; 489 reg = <0x481a2000 0x400>;
489 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 490 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
490 ti,hwmods = "spi2"; 491 ti,hwmods = "spi2";
491 #address-cells = <1>; 492 #address-cells = <1>;
492 #size-cells = <0>; 493 #size-cells = <0>;
493 status = "disabled"; 494 status = "disabled";
494 }; 495 };
495 496
496 spi3: spi@481a4000 { 497 spi3: spi@481a4000 {
497 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 498 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
498 reg = <0x481a4000 0x400>; 499 reg = <0x481a4000 0x400>;
499 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 500 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
500 ti,hwmods = "spi3"; 501 ti,hwmods = "spi3";
501 #address-cells = <1>; 502 #address-cells = <1>;
502 #size-cells = <0>; 503 #size-cells = <0>;
503 status = "disabled"; 504 status = "disabled";
504 }; 505 };
505 506
506 spi4: spi@48345000 { 507 spi4: spi@48345000 {
507 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 508 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
508 reg = <0x48345000 0x400>; 509 reg = <0x48345000 0x400>;
509 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 510 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
510 ti,hwmods = "spi4"; 511 ti,hwmods = "spi4";
511 #address-cells = <1>; 512 #address-cells = <1>;
512 #size-cells = <0>; 513 #size-cells = <0>;
513 status = "disabled"; 514 status = "disabled";
514 }; 515 };
515 516
516 mac: ethernet@4a100000 { 517 mac: ethernet@4a100000 {
517 compatible = "ti,am4372-cpsw","ti,cpsw"; 518 compatible = "ti,am4372-cpsw","ti,cpsw";
518 reg = <0x4a100000 0x800 519 reg = <0x4a100000 0x800
519 0x4a101200 0x100>; 520 0x4a101200 0x100>;
520 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 521 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
521 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 522 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
522 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 523 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
523 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 524 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
524 #address-cells = <1>; 525 #address-cells = <1>;
525 #size-cells = <1>; 526 #size-cells = <1>;
526 ti,hwmods = "cpgmac0"; 527 ti,hwmods = "cpgmac0";
527 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 528 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
528 clock-names = "fck", "cpts"; 529 clock-names = "fck", "cpts";
529 status = "disabled"; 530 status = "disabled";
530 cpdma_channels = <8>; 531 cpdma_channels = <8>;
531 ale_entries = <1024>; 532 ale_entries = <1024>;
532 bd_ram_size = <0x2000>; 533 bd_ram_size = <0x2000>;
533 no_bd_ram = <0>; 534 no_bd_ram = <0>;
534 rx_descs = <64>; 535 rx_descs = <64>;
535 mac_control = <0x20>; 536 mac_control = <0x20>;
536 slaves = <2>; 537 slaves = <2>;
537 active_slave = <0>; 538 active_slave = <0>;
538 cpts_clock_mult = <0x80000000>; 539 cpts_clock_mult = <0x80000000>;
539 cpts_clock_shift = <29>; 540 cpts_clock_shift = <29>;
540 ranges; 541 ranges;
541 542
542 davinci_mdio: mdio@4a101000 { 543 davinci_mdio: mdio@4a101000 {
543 compatible = "ti,am4372-mdio","ti,davinci_mdio"; 544 compatible = "ti,am4372-mdio","ti,davinci_mdio";
544 reg = <0x4a101000 0x100>; 545 reg = <0x4a101000 0x100>;
545 #address-cells = <1>; 546 #address-cells = <1>;
546 #size-cells = <0>; 547 #size-cells = <0>;
547 ti,hwmods = "davinci_mdio"; 548 ti,hwmods = "davinci_mdio";
548 bus_freq = <1000000>; 549 bus_freq = <1000000>;
549 status = "disabled"; 550 status = "disabled";
550 }; 551 };
551 552
552 cpsw_emac0: slave@4a100200 { 553 cpsw_emac0: slave@4a100200 {
553 /* Filled in by U-Boot */ 554 /* Filled in by U-Boot */
554 mac-address = [ 00 00 00 00 00 00 ]; 555 mac-address = [ 00 00 00 00 00 00 ];
555 }; 556 };
556 557
557 cpsw_emac1: slave@4a100300 { 558 cpsw_emac1: slave@4a100300 {
558 /* Filled in by U-Boot */ 559 /* Filled in by U-Boot */
559 mac-address = [ 00 00 00 00 00 00 ]; 560 mac-address = [ 00 00 00 00 00 00 ];
560 }; 561 };
561 562
562 phy_sel: cpsw-phy-sel@44e10650 { 563 phy_sel: cpsw-phy-sel@44e10650 {
563 compatible = "ti,am43xx-cpsw-phy-sel"; 564 compatible = "ti,am43xx-cpsw-phy-sel";
564 reg= <0x44e10650 0x4>; 565 reg= <0x44e10650 0x4>;
565 reg-names = "gmii-sel"; 566 reg-names = "gmii-sel";
566 }; 567 };
567 }; 568 };
568 569
569 epwmss0: epwmss@48300000 { 570 epwmss0: epwmss@48300000 {
570 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 571 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
571 reg = <0x48300000 0x10>; 572 reg = <0x48300000 0x10>;
572 #address-cells = <1>; 573 #address-cells = <1>;
573 #size-cells = <1>; 574 #size-cells = <1>;
574 ranges; 575 ranges;
575 ti,hwmods = "epwmss0"; 576 ti,hwmods = "epwmss0";
576 status = "disabled"; 577 status = "disabled";
577 578
578 ecap0: ecap@48300100 { 579 ecap0: ecap@48300100 {
579 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 580 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
580 #pwm-cells = <3>; 581 #pwm-cells = <3>;
581 reg = <0x48300100 0x80>; 582 reg = <0x48300100 0x80>;
582 ti,hwmods = "ecap0"; 583 ti,hwmods = "ecap0";
583 status = "disabled"; 584 status = "disabled";
584 }; 585 };
585 586
586 ehrpwm0: ehrpwm@48300200 { 587 ehrpwm0: ehrpwm@48300200 {
587 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 588 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
588 #pwm-cells = <3>; 589 #pwm-cells = <3>;
589 reg = <0x48300200 0x80>; 590 reg = <0x48300200 0x80>;
590 ti,hwmods = "ehrpwm0"; 591 ti,hwmods = "ehrpwm0";
591 status = "disabled"; 592 status = "disabled";
592 }; 593 };
593 }; 594 };
594 595
595 epwmss1: epwmss@48302000 { 596 epwmss1: epwmss@48302000 {
596 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 597 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
597 reg = <0x48302000 0x10>; 598 reg = <0x48302000 0x10>;
598 #address-cells = <1>; 599 #address-cells = <1>;
599 #size-cells = <1>; 600 #size-cells = <1>;
600 ranges; 601 ranges;
601 ti,hwmods = "epwmss1"; 602 ti,hwmods = "epwmss1";
602 status = "disabled"; 603 status = "disabled";
603 604
604 ecap1: ecap@48302100 { 605 ecap1: ecap@48302100 {
605 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 606 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
606 #pwm-cells = <3>; 607 #pwm-cells = <3>;
607 reg = <0x48302100 0x80>; 608 reg = <0x48302100 0x80>;
608 ti,hwmods = "ecap1"; 609 ti,hwmods = "ecap1";
609 status = "disabled"; 610 status = "disabled";
610 }; 611 };
611 612
612 ehrpwm1: ehrpwm@48302200 { 613 ehrpwm1: ehrpwm@48302200 {
613 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 614 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
614 #pwm-cells = <3>; 615 #pwm-cells = <3>;
615 reg = <0x48302200 0x80>; 616 reg = <0x48302200 0x80>;
616 ti,hwmods = "ehrpwm1"; 617 ti,hwmods = "ehrpwm1";
617 status = "disabled"; 618 status = "disabled";
618 }; 619 };
619 }; 620 };
620 621
621 epwmss2: epwmss@48304000 { 622 epwmss2: epwmss@48304000 {
622 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 623 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
623 reg = <0x48304000 0x10>; 624 reg = <0x48304000 0x10>;
624 #address-cells = <1>; 625 #address-cells = <1>;
625 #size-cells = <1>; 626 #size-cells = <1>;
626 ranges; 627 ranges;
627 ti,hwmods = "epwmss2"; 628 ti,hwmods = "epwmss2";
628 status = "disabled"; 629 status = "disabled";
629 630
630 ecap2: ecap@48304100 { 631 ecap2: ecap@48304100 {
631 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 632 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
632 #pwm-cells = <3>; 633 #pwm-cells = <3>;
633 reg = <0x48304100 0x80>; 634 reg = <0x48304100 0x80>;
634 ti,hwmods = "ecap2"; 635 ti,hwmods = "ecap2";
635 status = "disabled"; 636 status = "disabled";
636 }; 637 };
637 638
638 ehrpwm2: ehrpwm@48304200 { 639 ehrpwm2: ehrpwm@48304200 {
639 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 640 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
640 #pwm-cells = <3>; 641 #pwm-cells = <3>;
641 reg = <0x48304200 0x80>; 642 reg = <0x48304200 0x80>;
642 ti,hwmods = "ehrpwm2"; 643 ti,hwmods = "ehrpwm2";
643 status = "disabled"; 644 status = "disabled";
644 }; 645 };
645 }; 646 };
646 647
647 epwmss3: epwmss@48306000 { 648 epwmss3: epwmss@48306000 {
648 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 649 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
649 reg = <0x48306000 0x10>; 650 reg = <0x48306000 0x10>;
650 #address-cells = <1>; 651 #address-cells = <1>;
651 #size-cells = <1>; 652 #size-cells = <1>;
652 ranges; 653 ranges;
653 ti,hwmods = "epwmss3"; 654 ti,hwmods = "epwmss3";
654 status = "disabled"; 655 status = "disabled";
655 656
656 ehrpwm3: ehrpwm@48306200 { 657 ehrpwm3: ehrpwm@48306200 {
657 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 658 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
658 #pwm-cells = <3>; 659 #pwm-cells = <3>;
659 reg = <0x48306200 0x80>; 660 reg = <0x48306200 0x80>;
660 ti,hwmods = "ehrpwm3"; 661 ti,hwmods = "ehrpwm3";
661 status = "disabled"; 662 status = "disabled";
662 }; 663 };
663 }; 664 };
664 665
665 epwmss4: epwmss@48308000 { 666 epwmss4: epwmss@48308000 {
666 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 667 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
667 reg = <0x48308000 0x10>; 668 reg = <0x48308000 0x10>;
668 #address-cells = <1>; 669 #address-cells = <1>;
669 #size-cells = <1>; 670 #size-cells = <1>;
670 ranges; 671 ranges;
671 ti,hwmods = "epwmss4"; 672 ti,hwmods = "epwmss4";
672 status = "disabled"; 673 status = "disabled";
673 674
674 ehrpwm4: ehrpwm@48308200 { 675 ehrpwm4: ehrpwm@48308200 {
675 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 676 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
676 #pwm-cells = <3>; 677 #pwm-cells = <3>;
677 reg = <0x48308200 0x80>; 678 reg = <0x48308200 0x80>;
678 ti,hwmods = "ehrpwm4"; 679 ti,hwmods = "ehrpwm4";
679 status = "disabled"; 680 status = "disabled";
680 }; 681 };
681 }; 682 };
682 683
683 epwmss5: epwmss@4830a000 { 684 epwmss5: epwmss@4830a000 {
684 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 685 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
685 reg = <0x4830a000 0x10>; 686 reg = <0x4830a000 0x10>;
686 #address-cells = <1>; 687 #address-cells = <1>;
687 #size-cells = <1>; 688 #size-cells = <1>;
688 ranges; 689 ranges;
689 ti,hwmods = "epwmss5"; 690 ti,hwmods = "epwmss5";
690 status = "disabled"; 691 status = "disabled";
691 692
692 ehrpwm5: ehrpwm@4830a200 { 693 ehrpwm5: ehrpwm@4830a200 {
693 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 694 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
694 #pwm-cells = <3>; 695 #pwm-cells = <3>;
695 reg = <0x4830a200 0x80>; 696 reg = <0x4830a200 0x80>;
696 ti,hwmods = "ehrpwm5"; 697 ti,hwmods = "ehrpwm5";
697 status = "disabled"; 698 status = "disabled";
698 }; 699 };
699 }; 700 };
700 701
701 pruss: pruss@54400000 { 702 pruss: pruss@54400000 {
702 compatible = "ti,am4372-pruss"; 703 compatible = "ti,am4372-pruss";
703 ti,hwmods = "pruss"; 704 ti,hwmods = "pruss";
704 reg = <0x54400000 0x2000>, 705 reg = <0x54400000 0x2000>,
705 <0x54402000 0x2000>, 706 <0x54402000 0x2000>,
706 <0x54410000 0x8000>, 707 <0x54410000 0x8000>,
707 <0x54420000 0x2000>, 708 <0x54420000 0x2000>,
708 <0x54426000 0x2000>; 709 <0x54426000 0x2000>;
709 reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg"; 710 reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg";
710 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 711 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
711 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 712 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
712 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 713 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
713 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 714 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
714 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 715 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH
715 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 716 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
716 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 717 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
717 #address-cells = <1>; 718 #address-cells = <1>;
718 #size-cells = <1>; 719 #size-cells = <1>;
719 ranges; 720 ranges;
720 721
721 pru0: pru@4a334000 { 722 pru0: pru@4a334000 {
722 compatible = "ti,pru-rproc"; 723 compatible = "ti,pru-rproc";
723 reg = <0x54434000 0x3000>, 724 reg = <0x54434000 0x3000>,
724 <0x54422000 0x400>, 725 <0x54422000 0x400>,
725 <0x54422400 0x100>; 726 <0x54422400 0x100>;
726 reg-names = "iram", "control", "debug"; 727 reg-names = "iram", "control", "debug";
727 mboxes = <&mailbox &mbox_pru0>; 728 mboxes = <&mailbox &mbox_pru0>;
728 }; 729 };
729 730
730 pru1: pru@4a338000 { 731 pru1: pru@4a338000 {
731 compatible = "ti,pru-rproc"; 732 compatible = "ti,pru-rproc";
732 reg = <0x54438000 0x3000>, 733 reg = <0x54438000 0x3000>,
733 <0x54424000 0x400>, 734 <0x54424000 0x400>,
734 <0x54424400 0x100>; 735 <0x54424400 0x100>;
735 reg-names = "iram", "control", "debug"; 736 reg-names = "iram", "control", "debug";
736 mboxes = <&mailbox &mbox_pru1>; 737 mboxes = <&mailbox &mbox_pru1>;
737 }; 738 };
738 }; 739 };
739 740
740 ocmcram: ocmcram@40300000 { 741 ocmcram: ocmcram@40300000 {
741 compatible = "ti,am4372-ocmcram","ti,am3352-ocmcram"; 742 compatible = "ti,am4372-ocmcram","ti,am3352-ocmcram";
742 reg = <0x40300000 0x40000>; 743 reg = <0x40300000 0x40000>;
743 ti,hwmods = "ocmcram"; 744 ti,hwmods = "ocmcram";
744 clocks = <&l3_gclk>; 745 clocks = <&l3_gclk>;
745 clock-names = "fck"; 746 clock-names = "fck";
746 status = "okay"; 747 status = "okay";
747 }; 748 };
748 749
749 wkup_m3: wkup_m3@44d00000 { 750 wkup_m3: wkup_m3@44d00000 {
750 compatible = "ti,am4372-wkup-m3","ti,am3353-wkup-m3"; 751 compatible = "ti,am4372-wkup-m3","ti,am3353-wkup-m3";
751 reg = <0x44d00000 0x4000 /* M3 UMEM */ 752 reg = <0x44d00000 0x4000 /* M3 UMEM */
752 0x44d80000 0x2000 /* M3 DMEM */ 753 0x44d80000 0x2000 /* M3 DMEM */
753 0x44e11324 0x0024>; /* IPC REGS */ 754 0x44e11324 0x0024>; /* IPC REGS */
754 reg-names = "m3_umem", "m3_dmem", "ipc_regs"; 755 reg-names = "m3_umem", "m3_dmem", "ipc_regs";
755 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 756 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
756 ti,hwmods = "wkup_m3"; 757 ti,hwmods = "wkup_m3";
757 clocks = <&sys_clkin_ck>; 758 clocks = <&sys_clkin_ck>;
758 clock-names = "fck"; 759 clock-names = "fck";
759 mboxes = <&mailbox &mbox_wkupm3>; 760 mboxes = <&mailbox &mbox_wkupm3>;
760 status = "okay"; 761 status = "okay";
761 }; 762 };
762 763
763 tscadc: tscadc@44e0d000 { 764 tscadc: tscadc@44e0d000 {
764 compatible = "ti,am4372-tscadc","ti,am3359-tscadc"; 765 compatible = "ti,am4372-tscadc","ti,am3359-tscadc";
765 reg = <0x44e0d000 0x1000>; 766 reg = <0x44e0d000 0x1000>;
766 ti,hwmods = "adc_tsc"; 767 ti,hwmods = "adc_tsc";
767 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 768 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&adc_tsc_fck>; 769 clocks = <&adc_tsc_fck>;
769 clock-names = "fck"; 770 clock-names = "fck";
770 status = "disabled"; 771 status = "disabled";
771 772
772 tsc { 773 tsc {
773 compatible = "ti,am4372-tsc", "ti,am3359-tsc"; 774 compatible = "ti,am4372-tsc", "ti,am3359-tsc";
774 }; 775 };
775 776
776 adc { 777 adc {
777 #io-channel-cells = <1>; 778 #io-channel-cells = <1>;
778 compatible = "ti,am4372-adc", "ti,am3359-adc"; 779 compatible = "ti,am4372-adc", "ti,am3359-adc";
779 }; 780 };
780 781
781 }; 782 };
782 783
783 sham: sham@53100000 { 784 sham: sham@53100000 {
784 compatible = "ti,omap5-sham"; 785 compatible = "ti,omap5-sham";
785 ti,hwmods = "sham"; 786 ti,hwmods = "sham";
786 reg = <0x53100000 0x300>; 787 reg = <0x53100000 0x300>;
787 dmas = <&edma 36>; 788 dmas = <&edma 36>;
788 dma-names = "rx"; 789 dma-names = "rx";
789 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 790 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
790 }; 791 };
791 792
792 aes: aes@53501000 { 793 aes: aes@53501000 {
793 compatible = "ti,omap4-aes"; 794 compatible = "ti,omap4-aes";
794 ti,hwmods = "aes"; 795 ti,hwmods = "aes";
795 reg = <0x53501000 0xa0>; 796 reg = <0x53501000 0xa0>;
796 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 797 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
797 dmas = <&edma 6 798 dmas = <&edma 6
798 &edma 5>; 799 &edma 5>;
799 dma-names = "tx", "rx"; 800 dma-names = "tx", "rx";
800 }; 801 };
801 802
802 des: des@53701000 { 803 des: des@53701000 {
803 compatible = "ti,omap4-des"; 804 compatible = "ti,omap4-des";
804 ti,hwmods = "des"; 805 ti,hwmods = "des";
805 reg = <0x53701000 0xa0>; 806 reg = <0x53701000 0xa0>;
806 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 807 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
807 dmas = <&edma 34 808 dmas = <&edma 34
808 &edma 33>; 809 &edma 33>;
809 dma-names = "tx", "rx"; 810 dma-names = "tx", "rx";
810 }; 811 };
811 812
812 sgx: sgx@0x56000000 { 813 sgx: sgx@0x56000000 {
813 compatible = "ti,sgx"; 814 compatible = "ti,sgx";
814 ti,hwmods = "gfx"; 815 ti,hwmods = "gfx";
815 reg = <0x56000000 0x1000000>; 816 reg = <0x56000000 0x1000000>;
816 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 817 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
817 }; 818 };
818 819
819 rng: rng@48310000 { 820 rng: rng@48310000 {
820 compatible = "ti,omap4-rng"; 821 compatible = "ti,omap4-rng";
821 ti,hwmods = "rng"; 822 ti,hwmods = "rng";
822 reg = <0x48310000 0x2000>; 823 reg = <0x48310000 0x2000>;
823 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 824 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
824 }; 825 };
825 826
826 mcasp0: mcasp@48038000 { 827 mcasp0: mcasp@48038000 {
827 compatible = "ti,am33xx-mcasp-audio"; 828 compatible = "ti,am33xx-mcasp-audio";
828 ti,hwmods = "mcasp0"; 829 ti,hwmods = "mcasp0";
829 reg = <0x48038000 0x2000>, 830 reg = <0x48038000 0x2000>,
830 <0x46000000 0x400000>; 831 <0x46000000 0x400000>;
831 reg-names = "mpu", "dat"; 832 reg-names = "mpu", "dat";
832 interrupts = <80>, <81>; 833 interrupts = <80>, <81>;
833 interrupts-names = "tx", "rx"; 834 interrupts-names = "tx", "rx";
834 status = "disabled"; 835 status = "disabled";
835 dmas = <&edma 8>, 836 dmas = <&edma 8>,
836 <&edma 9>; 837 <&edma 9>;
837 dma-names = "tx", "rx"; 838 dma-names = "tx", "rx";
838 }; 839 };
839 840
840 mcasp1: mcasp@4803C000 { 841 mcasp1: mcasp@4803C000 {
841 compatible = "ti,am33xx-mcasp-audio"; 842 compatible = "ti,am33xx-mcasp-audio";
842 ti,hwmods = "mcasp1"; 843 ti,hwmods = "mcasp1";
843 reg = <0x4803C000 0x2000>, 844 reg = <0x4803C000 0x2000>,
844 <0x46400000 0x400000>; 845 <0x46400000 0x400000>;
845 reg-names = "mpu", "dat"; 846 reg-names = "mpu", "dat";
846 interrupts = <82>, <83>; 847 interrupts = <82>, <83>;
847 interrupts-names = "tx", "rx"; 848 interrupts-names = "tx", "rx";
848 status = "disabled"; 849 status = "disabled";
849 dmas = <&edma 10>, 850 dmas = <&edma 10>,
850 <&edma 11>; 851 <&edma 11>;
851 dma-names = "tx", "rx"; 852 dma-names = "tx", "rx";
852 }; 853 };
853 854
854 elm: elm@48080000 { 855 elm: elm@48080000 {
855 compatible = "ti,am3352-elm"; 856 compatible = "ti,am3352-elm";
856 reg = <0x48080000 0x2000>; 857 reg = <0x48080000 0x2000>;
857 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 858 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
858 ti,hwmods = "elm"; 859 ti,hwmods = "elm";
859 clocks = <&l4ls_gclk>; 860 clocks = <&l4ls_gclk>;
860 clock-names = "fck"; 861 clock-names = "fck";
861 status = "disabled"; 862 status = "disabled";
862 }; 863 };
863 864
864 gpmc: gpmc@50000000 { 865 gpmc: gpmc@50000000 {
865 compatible = "ti,am3352-gpmc"; 866 compatible = "ti,am3352-gpmc";
866 ti,hwmods = "gpmc"; 867 ti,hwmods = "gpmc";
867 ti,no-idle-on-init; 868 ti,no-idle-on-init;
868 clocks = <&l3s_gclk>; 869 clocks = <&l3s_gclk>;
869 clock-names = "fck"; 870 clock-names = "fck";
870 reg = <0x50000000 0x2000>; 871 reg = <0x50000000 0x2000>;
871 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 872 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
872 gpmc,num-cs = <7>; 873 gpmc,num-cs = <7>;
873 gpmc,num-waitpins = <2>; 874 gpmc,num-waitpins = <2>;
874 #address-cells = <2>; 875 #address-cells = <2>;
875 #size-cells = <1>; 876 #size-cells = <1>;
876 status = "disabled"; 877 status = "disabled";
877 }; 878 };
878 879
879 am43xx_control_usb2phy1: control-phy@44e10620 { 880 am43xx_control_usb2phy1: control-phy@44e10620 {
880 compatible = "ti,control-phy-usb2-am437"; 881 compatible = "ti,control-phy-usb2-am437";
881 reg = <0x44e10620 0x4>; 882 reg = <0x44e10620 0x4>;
882 reg-names = "power"; 883 reg-names = "power";
883 }; 884 };
884 885
885 am43xx_control_usb2phy2: control-phy@0x44e10628 { 886 am43xx_control_usb2phy2: control-phy@0x44e10628 {
886 compatible = "ti,control-phy-usb2-am437"; 887 compatible = "ti,control-phy-usb2-am437";
887 reg = <0x44e10628 0x4>; 888 reg = <0x44e10628 0x4>;
888 reg-names = "power"; 889 reg-names = "power";
889 }; 890 };
890 891
891 ocp2scp0: ocp2scp@483a8000 { 892 ocp2scp0: ocp2scp@483a8000 {
892 compatible = "ti,omap-ocp2scp"; 893 compatible = "ti,omap-ocp2scp";
893 #address-cells = <1>; 894 #address-cells = <1>;
894 #size-cells = <1>; 895 #size-cells = <1>;
895 ranges; 896 ranges;
896 ti,hwmods = "ocp2scp0"; 897 ti,hwmods = "ocp2scp0";
897 898
898 usb2_phy1: phy@483a8000 { 899 usb2_phy1: phy@483a8000 {
899 compatible = "ti,am437x-usb2"; 900 compatible = "ti,am437x-usb2";
900 reg = <0x483a8000 0x8000>; 901 reg = <0x483a8000 0x8000>;
901 ctrl-module = <&am43xx_control_usb2phy1>; 902 ctrl-module = <&am43xx_control_usb2phy1>;
902 clocks = <&usb_phy0_always_on_clk32k>, 903 clocks = <&usb_phy0_always_on_clk32k>,
903 <&usb_otg_ss0_refclk960m>; 904 <&usb_otg_ss0_refclk960m>;
904 clock-names = "wkupclk", "refclk"; 905 clock-names = "wkupclk", "refclk";
905 #phy-cells = <0>; 906 #phy-cells = <0>;
906 status = "disabled"; 907 status = "disabled";
907 }; 908 };
908 }; 909 };
909 910
910 ocp2scp1: ocp2scp@483e8000 { 911 ocp2scp1: ocp2scp@483e8000 {
911 compatible = "ti,omap-ocp2scp"; 912 compatible = "ti,omap-ocp2scp";
912 #address-cells = <1>; 913 #address-cells = <1>;
913 #size-cells = <1>; 914 #size-cells = <1>;
914 ranges; 915 ranges;
915 ti,hwmods = "ocp2scp1"; 916 ti,hwmods = "ocp2scp1";
916 917
917 usb2_phy2: phy@483e8000 { 918 usb2_phy2: phy@483e8000 {
918 compatible = "ti,am437x-usb2"; 919 compatible = "ti,am437x-usb2";
919 reg = <0x483e8000 0x8000>; 920 reg = <0x483e8000 0x8000>;
920 ctrl-module = <&am43xx_control_usb2phy2>; 921 ctrl-module = <&am43xx_control_usb2phy2>;
921 clocks = <&usb_phy1_always_on_clk32k>, 922 clocks = <&usb_phy1_always_on_clk32k>,
922 <&usb_otg_ss1_refclk960m>; 923 <&usb_otg_ss1_refclk960m>;
923 clock-names = "wkupclk", "refclk"; 924 clock-names = "wkupclk", "refclk";
924 #phy-cells = <0>; 925 #phy-cells = <0>;
925 status = "disabled"; 926 status = "disabled";
926 }; 927 };
927 }; 928 };
928 929
929 dwc3_1: omap_dwc3@48380000 { 930 dwc3_1: omap_dwc3@48380000 {
930 compatible = "ti,am437x-dwc3"; 931 compatible = "ti,am437x-dwc3";
931 ti,hwmods = "usb_otg_ss0"; 932 ti,hwmods = "usb_otg_ss0";
932 reg = <0x48380000 0x10000>; 933 reg = <0x48380000 0x10000>;
933 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 934 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
934 #address-cells = <1>; 935 #address-cells = <1>;
935 #size-cells = <1>; 936 #size-cells = <1>;
936 utmi-mode = <1>; 937 utmi-mode = <1>;
937 ranges; 938 ranges;
938 939
939 usb1: usb@48390000 { 940 usb1: usb@48390000 {
940 compatible = "synopsys,dwc3"; 941 compatible = "synopsys,dwc3";
941 reg = <0x48390000 0x17000>; 942 reg = <0x48390000 0x17000>;
942 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 943 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 945 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
945 interrupt-names = "peripheral", 946 interrupt-names = "peripheral",
946 "host", 947 "host",
947 "otg"; 948 "otg";
948 phys = <&usb2_phy1>; 949 phys = <&usb2_phy1>;
949 phy-names = "usb2-phy"; 950 phy-names = "usb2-phy";
950 maximum-speed = "high-speed"; 951 maximum-speed = "high-speed";
951 dr_mode = "otg"; 952 dr_mode = "otg";
952 status = "disabled"; 953 status = "disabled";
953 }; 954 };
954 }; 955 };
955 956
956 dwc3_2: omap_dwc3@483c0000 { 957 dwc3_2: omap_dwc3@483c0000 {
957 compatible = "ti,am437x-dwc3"; 958 compatible = "ti,am437x-dwc3";
958 ti,hwmods = "usb_otg_ss1"; 959 ti,hwmods = "usb_otg_ss1";
959 reg = <0x483c0000 0x10000>; 960 reg = <0x483c0000 0x10000>;
960 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 961 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
961 #address-cells = <1>; 962 #address-cells = <1>;
962 #size-cells = <1>; 963 #size-cells = <1>;
963 utmi-mode = <1>; 964 utmi-mode = <1>;
964 ranges; 965 ranges;
965 966
966 usb2: usb@483d0000 { 967 usb2: usb@483d0000 {
967 compatible = "synopsys,dwc3"; 968 compatible = "synopsys,dwc3";
968 reg = <0x483d0000 0x17000>; 969 reg = <0x483d0000 0x17000>;
969 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 970 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 972 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
972 interrupt-names = "peripheral", 973 interrupt-names = "peripheral",
973 "host", 974 "host",
974 "otg"; 975 "otg";
975 phys = <&usb2_phy2>; 976 phys = <&usb2_phy2>;
976 phy-names = "usb2-phy"; 977 phy-names = "usb2-phy";
977 maximum-speed = "high-speed"; 978 maximum-speed = "high-speed";
978 dr_mode = "otg"; 979 dr_mode = "otg";
979 status = "disabled"; 980 status = "disabled";
980 }; 981 };
981 }; 982 };
982 983
983 qspi: qspi@47900000 { 984 qspi: qspi@47900000 {
984 compatible = "ti,am4372-qspi"; 985 compatible = "ti,am4372-qspi";
985 reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>; 986 reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
986 reg-names = "qspi_base", 987 reg-names = "qspi_base",
987 "qspi_mmap"; 988 "qspi_mmap";
988 #address-cells = <1>; 989 #address-cells = <1>;
989 #size-cells = <0>; 990 #size-cells = <0>;
990 ti,hwmods = "qspi"; 991 ti,hwmods = "qspi";
991 clocks = <&dpll_per_m2_div4_ck>; 992 clocks = <&dpll_per_m2_div4_ck>;
992 clock-names = "fck"; 993 clock-names = "fck";
993 interrupts = <0 138 0x4>; 994 interrupts = <0 138 0x4>;
994 num-cs = <4>; 995 num-cs = <4>;
995 status = "disabled"; 996 status = "disabled";
996 }; 997 };
997 998
998 hdq: hdq@48347000 { 999 hdq: hdq@48347000 {
999 compatible = "ti,am43xx-hdq"; 1000 compatible = "ti,am43xx-hdq";
1000 reg = <0x48347000 0x1000>; 1001 reg = <0x48347000 0x1000>;
1001 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1002 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&func_12m_clk>; 1003 clocks = <&func_12m_clk>;
1003 clock-names = "fck"; 1004 clock-names = "fck";
1004 ti,hwmods = "hdq1w"; 1005 ti,hwmods = "hdq1w";
1005 status = "disabled"; 1006 status = "disabled";
1006 }; 1007 };
1007 1008
1008 dss: dss@4832a000 { 1009 dss: dss@4832a000 {
1009 compatible = "ti,omap3-dss"; 1010 compatible = "ti,omap3-dss";
1010 reg = <0x4832a000 0x200>; 1011 reg = <0x4832a000 0x200>;
1011 status = "disabled"; 1012 status = "disabled";
1012 ti,hwmods = "dss_core"; 1013 ti,hwmods = "dss_core";
1013 clocks = <&disp_clk>; 1014 clocks = <&disp_clk>;
1014 clock-names = "fck"; 1015 clock-names = "fck";
1015 #address-cells = <1>; 1016 #address-cells = <1>;
1016 #size-cells = <1>; 1017 #size-cells = <1>;
1017 ranges; 1018 ranges;
1018 1019
1019 dispc: dispc@4832a400 { 1020 dispc: dispc@4832a400 {
1020 compatible = "ti,omap3-dispc"; 1021 compatible = "ti,omap3-dispc";
1021 reg = <0x4832a400 0x400>; 1022 reg = <0x4832a400 0x400>;
1022 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1023 ti,hwmods = "dss_dispc"; 1024 ti,hwmods = "dss_dispc";
1024 clocks = <&disp_clk>; 1025 clocks = <&disp_clk>;
1025 clock-names = "fck"; 1026 clock-names = "fck";
1026 }; 1027 };
1027 1028
1028 rfbi: rfbi@4832a800 { 1029 rfbi: rfbi@4832a800 {
1029 compatible = "ti,omap3-rfbi"; 1030 compatible = "ti,omap3-rfbi";
1030 reg = <0x4832a800 0x100>; 1031 reg = <0x4832a800 0x100>;
1031 ti,hwmods = "dss_rfbi"; 1032 ti,hwmods = "dss_rfbi";
1032 clocks = <&disp_clk>; 1033 clocks = <&disp_clk>;
1033 clock-names = "fck"; 1034 clock-names = "fck";
1034 }; 1035 };
1035 }; 1036 };
1036 1037
1037 dcan0: can@481cc000 { 1038 dcan0: can@481cc000 {
1038 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1039 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1039 ti,hwmods = "d_can0"; 1040 ti,hwmods = "d_can0";
1040 clocks = <&dcan0_fck>; 1041 clocks = <&dcan0_fck>;
1041 clock-names = "fck"; 1042 clock-names = "fck";
1042 reg = <0x481cc000 0x2000>; 1043 reg = <0x481cc000 0x2000>;
1043 syscon-raminit = <&am43xx_control_module 0x644 0>; 1044 syscon-raminit = <&am43xx_control_module 0x644 0>;
1044 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1045 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1045 status = "disabled"; 1046 status = "disabled";
1046 }; 1047 };
1047 1048
1048 dcan1: can@481d0000 { 1049 dcan1: can@481d0000 {
1049 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1050 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1050 ti,hwmods = "d_can1"; 1051 ti,hwmods = "d_can1";
1051 clocks = <&dcan1_fck>; 1052 clocks = <&dcan1_fck>;
1052 clock-names = "fck"; 1053 clock-names = "fck";
1053 reg = <0x481d0000 0x2000>; 1054 reg = <0x481d0000 0x2000>;
1054 syscon-raminit = <&am43xx_control_module 0x644 1>; 1055 syscon-raminit = <&am43xx_control_module 0x644 1>;
1055 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1056 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1056 status = "disabled"; 1057 status = "disabled";
1057 }; 1058 };
1058 1059
1059 vpfe0: vpfe@48326000 { 1060 vpfe0: vpfe@48326000 {
1060 compatible = "ti,am437x-vpfe"; 1061 compatible = "ti,am437x-vpfe";
1061 reg = <0x48326000 0x2000>; 1062 reg = <0x48326000 0x2000>;
1062 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1063 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1063 ti,hwmods = "vpfe0"; 1064 ti,hwmods = "vpfe0";
1064 status = "disabled"; 1065 status = "disabled";
1065 }; 1066 };
1066 1067
1067 vpfe1: vpfe@48328000 { 1068 vpfe1: vpfe@48328000 {
1068 compatible = "ti,am437x-vpfe"; 1069 compatible = "ti,am437x-vpfe";
1069 reg = <0x48328000 0x2000>; 1070 reg = <0x48328000 0x2000>;
1070 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1071 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1071 ti,hwmods = "vpfe1"; 1072 ti,hwmods = "vpfe1";
1072 status = "disabled"; 1073 status = "disabled";
1073 }; 1074 };
1074 1075
1075 }; 1076 };
1076 }; 1077 };
1077 1078
1078 /include/ "am43xx-clocks.dtsi" 1079 /include/ "am43xx-clocks.dtsi"
1079 1080
arch/arm/mach-omap2/pm33xx.c
Diff comments   View file @ 14ed5c8
1 /* 1 /*
2 * AM33XX Power Management Routines 2 * AM33XX Power Management Routines
3 * 3 *
4 * Copyright (C) 2012-2014 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2012-2014 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Bedia, Dave Gerlach 5 * Vaibhav Bedia, Dave Gerlach
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2. 9 * published by the Free Software Foundation version 2.
10 * 10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty 12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17 #include <linux/kernel.h> 17 #include <linux/kernel.h>
18 #include <linux/init.h> 18 #include <linux/init.h>
19 #include <linux/cpu.h> 19 #include <linux/cpu.h>
20 #include <linux/err.h> 20 #include <linux/err.h>
21 #include <linux/firmware.h> 21 #include <linux/firmware.h>
22 #include <linux/io.h> 22 #include <linux/io.h>
23 #include <linux/platform_device.h> 23 #include <linux/platform_device.h>
24 #include <linux/sched.h> 24 #include <linux/sched.h>
25 #include <linux/suspend.h> 25 #include <linux/suspend.h>
26 #include <linux/completion.h> 26 #include <linux/completion.h>
27 #include <linux/module.h> 27 #include <linux/module.h>
28 #include <linux/interrupt.h> 28 #include <linux/interrupt.h>
29 #include <linux/ti_emif.h> 29 #include <linux/ti_emif.h>
30 #include <linux/omap-mailbox.h> 30 #include <linux/omap-mailbox.h>
31 #include <linux/sizes.h> 31 #include <linux/sizes.h>
32 #include <linux/pinctrl/pinctrl.h> 32 #include <linux/pinctrl/pinctrl.h>
33 #include <linux/pinctrl/pinmux.h> 33 #include <linux/pinctrl/pinmux.h>
34 #include <linux/gpio.h> 34 #include <linux/gpio.h>
35 #include <linux/platform_data/gpio-omap.h> 35 #include <linux/platform_data/gpio-omap.h>
36 #include <linux/platform_data/wkup_m3.h> 36 #include <linux/platform_data/wkup_m3.h>
37 #include <linux/rtc.h> 37 #include <linux/rtc.h>
38 38
39 #include <asm/suspend.h> 39 #include <asm/suspend.h>
40 #include <asm/proc-fns.h> 40 #include <asm/proc-fns.h>
41 #include <asm/fncpy.h> 41 #include <asm/fncpy.h>
42 #include <asm/system_misc.h> 42 #include <asm/system_misc.h>
43 #include <asm/smp_scu.h> 43 #include <asm/smp_scu.h>
44 44
45 #include "control.h" 45 #include "control.h"
46 #include "pm.h" 46 #include "pm.h"
47 #include "cm33xx.h" 47 #include "cm33xx.h"
48 #include "pm33xx.h" 48 #include "pm33xx.h"
49 #include "prm33xx.h" 49 #include "prm33xx.h"
50 #include "common.h" 50 #include "common.h"
51 #include "clockdomain.h" 51 #include "clockdomain.h"
52 #include "powerdomain.h" 52 #include "powerdomain.h"
53 #include "soc.h" 53 #include "soc.h"
54 #include "sram.h" 54 #include "sram.h"
55 #include "omap_hwmod.h" 55 #include "omap_hwmod.h"
56 #include "iomap.h" 56 #include "iomap.h"
57 57
58 static struct rtc_device *omap_rtc; 58 static struct rtc_device *omap_rtc;
59 static struct omap_hwmod *rtc_oh; 59 static struct omap_hwmod *rtc_oh;
60 static struct pinctrl_dev *pmx_dev; 60 static struct pinctrl_dev *pmx_dev;
61 static u32 rtc_magic_val; 61 static u32 rtc_magic_val;
62 static int retrigger_irq; 62 static int retrigger_irq;
63 63
64 #define RTC_SCRATCH_RESUME_REG 0 64 #define RTC_SCRATCH_RESUME_REG 0
65 #define RTC_SCRATCH_MAGIC_REG 1 65 #define RTC_SCRATCH_MAGIC_REG 1
66 66
67 #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */ 67 #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
68 #define RTC_REG_DDR_TYPE_DDR2_0 (0x00 << 16) 68 #define RTC_REG_DDR_TYPE_DDR2_0 (0x00 << 16)
69 #define RTC_REG_DDR_TYPE_DDR3_0 (0x01 << 16) 69 #define RTC_REG_DDR_TYPE_DDR3_0 (0x01 << 16)
70 70
71 #define WKUP_M3_SD_FW_MAGIC 0x570C 71 #define WKUP_M3_SD_FW_MAGIC 0x570C
72 72
73 #ifdef CONFIG_SUSPEND 73 #ifdef CONFIG_SUSPEND
74 static void __iomem *scu_base, *gic_dist_base; 74 static void __iomem *scu_base, *gic_dist_base;
75 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; 75 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
76 static struct clockdomain *gfx_l4ls_clkdm; 76 static struct clockdomain *gfx_l4ls_clkdm;
77 #endif /* CONFIG_SUSPEND */ 77 #endif /* CONFIG_SUSPEND */
78 78
79 static struct am33xx_suspend_params susp_params; 79 static struct am33xx_suspend_params susp_params;
80 80
81 #ifdef CONFIG_CPU_PM 81 #ifdef CONFIG_CPU_PM
82 struct wkup_m3_scale_data_header { 82 struct wkup_m3_scale_data_header {
83 u16 magic; 83 u16 magic;
84 u8 sleep_offset; 84 u8 sleep_offset;
85 u8 wake_offset; 85 u8 wake_offset;
86 } __packed; 86 } __packed;
87 87
88 static void __iomem *am33xx_emif_base; 88 static void __iomem *am33xx_emif_base;
89 static struct am33xx_pm_context *am33xx_pm; 89 static struct am33xx_pm_context *am33xx_pm;
90 90
91 static DECLARE_COMPLETION(am33xx_pm_sync); 91 static DECLARE_COMPLETION(am33xx_pm_sync);
92 92
93 static void (*am33xx_do_wfi_sram)(struct am33xx_suspend_params *); 93 static void (*am33xx_do_wfi_sram)(struct am33xx_suspend_params *);
94 94
95 int am33xx_do_sram_cpuidle(u32 wfi_flags, u32 m3_flags) 95 int am33xx_do_sram_cpuidle(u32 wfi_flags, u32 m3_flags)
96 { 96 {
97 struct am33xx_suspend_params params; 97 struct am33xx_suspend_params params;
98 int ret; 98 int ret;
99 99
100 /* Start with the default flags */ 100 /* Start with the default flags */
101 memcpy(&params, &susp_params, sizeof(params)); 101 memcpy(&params, &susp_params, sizeof(params));
102 102
103 /* Clear bits configurable through this call */ 103 /* Clear bits configurable through this call */
104 params.wfi_flags &= ~(WFI_SELF_REFRESH | WFI_WAKE_M3 | WFI_SAVE_EMIF | 104 params.wfi_flags &= ~(WFI_SELF_REFRESH | WFI_WAKE_M3 | WFI_SAVE_EMIF |
105 WFI_DISABLE_EMIF); 105 WFI_DISABLE_EMIF);
106 106
107 /* Don't enter these states if the M3 isn't available */ 107 /* Don't enter these states if the M3 isn't available */
108 if (am33xx_pm->state != M3_STATE_INITED) 108 if (am33xx_pm->state != M3_STATE_INITED)
109 wfi_flags &= ~WFI_WAKE_M3; 109 wfi_flags &= ~WFI_WAKE_M3;
110 110
111 /* Set bits that have been passed */ 111 /* Set bits that have been passed */
112 params.wfi_flags |= wfi_flags; 112 params.wfi_flags |= wfi_flags;
113 113
114 if (wfi_flags & WFI_WAKE_M3) { 114 if (wfi_flags & WFI_WAKE_M3) {
115 am33xx_pm->ipc.reg1 = IPC_CMD_IDLE; 115 am33xx_pm->ipc.reg1 = IPC_CMD_IDLE;
116 am33xx_pm->ipc.reg2 = DS_IPC_DEFAULT; 116 am33xx_pm->ipc.reg2 = DS_IPC_DEFAULT;
117 am33xx_pm->ipc.reg3 = m3_flags; 117 am33xx_pm->ipc.reg3 = m3_flags;
118 am33xx_pm->ipc.reg5 = DS_IPC_DEFAULT;
118 wkup_m3_set_cmd(&am33xx_pm->ipc); 119 wkup_m3_set_cmd(&am33xx_pm->ipc);
119 ret = wkup_m3_ping(); 120 ret = wkup_m3_ping();
120 if (ret < 0) 121 if (ret < 0)
121 return ret; 122 return ret;
122 } 123 }
123 124
124 am33xx_do_wfi_sram(&params); 125 am33xx_do_wfi_sram(&params);
125 return 0; 126 return 0;
126 } 127 }
127 128
128 #ifdef CONFIG_SUSPEND 129 #ifdef CONFIG_SUSPEND
129 static int am33xx_do_sram_idle(unsigned long int arg) 130 static int am33xx_do_sram_idle(unsigned long int arg)
130 { 131 {
131 am33xx_do_wfi_sram((struct am33xx_suspend_params *)arg); 132 am33xx_do_wfi_sram((struct am33xx_suspend_params *)arg);
132 return 0; 133 return 0;
133 } 134 }
134 135
135 static struct wkup_m3_wakeup_src rtc_wakeups[] = { 136 static struct wkup_m3_wakeup_src rtc_wakeups[] = {
136 {.irq_nr = 0, .src = "Unknown"}, 137 {.irq_nr = 0, .src = "Unknown"},
137 {.irq_nr = 0, .src = "Unknown"}, 138 {.irq_nr = 0, .src = "Unknown"},
138 {.irq_nr = 108, .src = "RTC Alarm"}, 139 {.irq_nr = 108, .src = "RTC Alarm"},
139 {.irq_nr = 0, .src = "Ext wakeup"}, 140 {.irq_nr = 0, .src = "Ext wakeup"},
140 }; 141 };
141 142
142 struct wkup_m3_wakeup_src rtc_wake_src(void) 143 struct wkup_m3_wakeup_src rtc_wake_src(void)
143 { 144 {
144 u32 i; 145 u32 i;
145 146
146 i = __raw_readl(susp_params.rtc_base + 0x98) >> 17; 147 i = __raw_readl(susp_params.rtc_base + 0x98) >> 17;
147 retrigger_irq = rtc_wakeups[i].irq_nr; 148 retrigger_irq = rtc_wakeups[i].irq_nr;
148 149
149 return rtc_wakeups[i]; 150 return rtc_wakeups[i];
150 } 151 }
151 152
152 static void common_save_context(void) 153 static void common_save_context(void)
153 { 154 {
154 omap2_gpio_prepare_for_idle(1); 155 omap2_gpio_prepare_for_idle(1);
155 pinmux_save_context(pmx_dev, "am33xx_pmx_per"); 156 pinmux_save_context(pmx_dev, "am33xx_pmx_per");
156 clks_save_context(); 157 clks_save_context();
157 pwrdms_save_context(); 158 pwrdms_save_context();
158 omap_hwmods_save_context(); 159 omap_hwmods_save_context();
159 clkdm_save_context(); 160 clkdm_save_context();
160 } 161 }
161 162
162 static void common_restore_context(void) 163 static void common_restore_context(void)
163 { 164 {
164 clks_restore_context(); 165 clks_restore_context();
165 pwrdms_restore_context(); 166 pwrdms_restore_context();
166 clkdm_restore_context(); 167 clkdm_restore_context();
167 omap_hwmods_restore_context(); 168 omap_hwmods_restore_context();
168 pinmux_restore_context(pmx_dev, "am33xx_pmx_per"); 169 pinmux_restore_context(pmx_dev, "am33xx_pmx_per");
169 wkup_m3_set_rtc_only_mode(); 170 wkup_m3_set_rtc_only_mode();
170 pwrdms_lost_power(); 171 pwrdms_lost_power();
171 omap2_gpio_resume_after_idle(); 172 omap2_gpio_resume_after_idle();
172 omap_sram_reset(); 173 omap_sram_reset();
173 } 174 }
174 175
175 static void am33xx_save_context(void) 176 static void am33xx_save_context(void)
176 { 177 {
177 common_save_context(); 178 common_save_context();
178 omap_intc_save_context(); 179 omap_intc_save_context();
179 am33xx_control_save_context(); 180 am33xx_control_save_context();
180 } 181 }
181 182
182 static void am33xx_restore_context(void) 183 static void am33xx_restore_context(void)
183 { 184 {
184 common_restore_context(); 185 common_restore_context();
185 am33xx_control_restore_context(); 186 am33xx_control_restore_context();
186 omap_intc_restore_context(); 187 omap_intc_restore_context();
187 am33xx_push_sram_idle(); 188 am33xx_push_sram_idle();
188 } 189 }
189 190
190 static void am43xx_save_context(void) 191 static void am43xx_save_context(void)
191 { 192 {
192 common_save_context(); 193 common_save_context();
193 am43xx_control_save_context(); 194 am43xx_control_save_context();
194 am43xx_prm_save_context(); 195 am43xx_prm_save_context();
195 } 196 }
196 197
197 static void am43xx_restore_context(void) 198 static void am43xx_restore_context(void)
198 { 199 {
199 common_restore_context(); 200 common_restore_context();
200 am43xx_control_restore_context(); 201 am43xx_control_restore_context();
201 am43xx_prm_restore_context(); 202 am43xx_prm_restore_context();
202 am43xx_push_sram_idle(); 203 am43xx_push_sram_idle();
203 /* 204 /*
204 * HACK: restore dpll_per_clkdcoldo register contents, to avoid 205 * HACK: restore dpll_per_clkdcoldo register contents, to avoid
205 * breaking suspend-resume 206 * breaking suspend-resume
206 */ 207 */
207 writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14)); 208 writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
208 } 209 }
209 210
210 int am33xx_rtc_only_idle(long unsigned int unused) 211 int am33xx_rtc_only_idle(long unsigned int unused)
211 { 212 {
212 rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, rtc_magic_val); 213 rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, rtc_magic_val);
213 omap_rtc_power_off_program(); 214 omap_rtc_power_off_program();
214 am33xx_do_wfi_sram(&susp_params); 215 am33xx_do_wfi_sram(&susp_params);
215 return 0; 216 return 0;
216 } 217 }
217 218
218 static int am33xx_pm_suspend(unsigned int state) 219 static int am33xx_pm_suspend(unsigned int state)
219 { 220 {
220 int i, ret = 0; 221 int i, ret = 0;
221 int status = 0; 222 int status = 0;
222 int rtc_only_idle = 0; 223 int rtc_only_idle = 0;
223 struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0, 224 struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
224 .src = "Unknown",}; 225 .src = "Unknown",};
225 226
226 omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF); 227 omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
227 228
228 am33xx_pm->ops->pre_suspend(state); 229 am33xx_pm->ops->pre_suspend(state);
229 230
230 if (state == PM_SUSPEND_MEM && enable_off_mode && rtc_magic_val) 231 if (state == PM_SUSPEND_MEM && enable_off_mode && rtc_magic_val)
231 rtc_only_idle = 1; 232 rtc_only_idle = 1;
232 233
233 if (rtc_only_idle) { 234 if (rtc_only_idle) {
234 omap_hwmod_enable(rtc_oh); 235 omap_hwmod_enable(rtc_oh);
235 am33xx_pm->ops->save_context(); 236 am33xx_pm->ops->save_context();
236 susp_params.wfi_flags |= WFI_RTC_ONLY; 237 susp_params.wfi_flags |= WFI_RTC_ONLY;
237 ret = cpu_suspend((long unsigned int) &susp_params, 238 ret = cpu_suspend((long unsigned int) &susp_params,
238 am33xx_rtc_only_idle); 239 am33xx_rtc_only_idle);
239 susp_params.wfi_flags &= ~WFI_RTC_ONLY; 240 susp_params.wfi_flags &= ~WFI_RTC_ONLY;
240 if (!ret) 241 if (!ret)
241 am33xx_pm->ops->restore_context(); 242 am33xx_pm->ops->restore_context();
242 } else 243 } else
243 ret = cpu_suspend((long unsigned int) &susp_params, 244 ret = cpu_suspend((long unsigned int) &susp_params,
244 am33xx_do_sram_idle); 245 am33xx_do_sram_idle);
245 246
246 /* 247 /*
247 * Because gfx_pwrdm is the only one under MPU control, 248 * Because gfx_pwrdm is the only one under MPU control,
248 * comment on transition status 249 * comment on transition status
249 */ 250 */
250 status = pwrdm_read_pwrst(gfx_pwrdm); 251 status = pwrdm_read_pwrst(gfx_pwrdm);
251 if (status != PWRDM_POWER_OFF) 252 if (status != PWRDM_POWER_OFF)
252 pr_err("PM: GFX domain did not transition\n"); 253 pr_err("PM: GFX domain did not transition\n");
253 254
254 am33xx_pm->ops->post_suspend(state); 255 am33xx_pm->ops->post_suspend(state);
255 256
256 if (ret) { 257 if (ret) {
257 pr_err("PM: Kernel suspend failure\n"); 258 pr_err("PM: Kernel suspend failure\n");
258 } else { 259 } else {
259 i = wkup_m3_pm_status(); 260 i = wkup_m3_pm_status();
260 261
261 switch (i) { 262 switch (i) {
262 case 0: 263 case 0:
263 pr_info("PM: Successfully put all powerdomains to target state\n"); 264 pr_info("PM: Successfully put all powerdomains to target state\n");
264 265
265 /* 266 /*
266 * The PRCM registers on AM335x do not contain 267 * The PRCM registers on AM335x do not contain
267 * previous state information like those present on 268 * previous state information like those present on
268 * OMAP4 so we must manually indicate transition so 269 * OMAP4 so we must manually indicate transition so
269 * state counters are properly incremented 270 * state counters are properly incremented
270 */ 271 */
271 pwrdm_post_transition(mpu_pwrdm); 272 pwrdm_post_transition(mpu_pwrdm);
272 pwrdm_post_transition(per_pwrdm); 273 pwrdm_post_transition(per_pwrdm);
273 break; 274 break;
274 case 1: 275 case 1:
275 pr_err("PM: Could not transition all powerdomains to target state\n"); 276 pr_err("PM: Could not transition all powerdomains to target state\n");
276 ret = -1; 277 ret = -1;
277 break; 278 break;
278 default: 279 default:
279 pr_err("PM: CM3 returned unknown result = %d\n", i); 280 pr_err("PM: CM3 returned unknown result = %d\n", i);
280 ret = -1; 281 ret = -1;
281 } 282 }
282 /* print the wakeup reason */ 283 /* print the wakeup reason */
283 if (rtc_only_idle) { 284 if (rtc_only_idle) {
284 wakeup_src = rtc_wake_src(); 285 wakeup_src = rtc_wake_src();
285 omap_hwmod_idle(rtc_oh); 286 omap_hwmod_idle(rtc_oh);
286 } else { 287 } else {
287 wkup_m3_wake_src(&wakeup_src); 288 wkup_m3_wake_src(&wakeup_src);
288 } 289 }
289 290
290 pr_info("PM: Wakeup source %s\n", wakeup_src.src); 291 pr_info("PM: Wakeup source %s\n", wakeup_src.src);
291 } 292 }
292 293
293 return ret; 294 return ret;
294 } 295 }
295 296
296 static int am33xx_pm_enter(suspend_state_t suspend_state) 297 static int am33xx_pm_enter(suspend_state_t suspend_state)
297 { 298 {
298 int ret = 0; 299 int ret = 0;
299 300
300 switch (suspend_state) { 301 switch (suspend_state) {
301 case PM_SUSPEND_STANDBY: 302 case PM_SUSPEND_STANDBY:
302 case PM_SUSPEND_MEM: 303 case PM_SUSPEND_MEM:
303 ret = am33xx_pm_suspend(suspend_state); 304 ret = am33xx_pm_suspend(suspend_state);
304 break; 305 break;
305 default: 306 default:
306 ret = -EINVAL; 307 ret = -EINVAL;
307 } 308 }
308 309
309 return ret; 310 return ret;
310 } 311 }
311 312
312 313
313 static void am33xx_m3_state_machine_reset(void) 314 static void am33xx_m3_state_machine_reset(void)
314 { 315 {
315 int i; 316 int i;
316 317
317 am33xx_pm->ipc.reg1 = IPC_CMD_RESET; 318 am33xx_pm->ipc.reg1 = IPC_CMD_RESET;
318 319
319 wkup_m3_set_cmd(&am33xx_pm->ipc); 320 wkup_m3_set_cmd(&am33xx_pm->ipc);
320 321
321 am33xx_pm->state = M3_STATE_MSG_FOR_RESET; 322 am33xx_pm->state = M3_STATE_MSG_FOR_RESET;
322 323
323 if (!wkup_m3_ping()) { 324 if (!wkup_m3_ping()) {
324 i = wait_for_completion_timeout(&am33xx_pm_sync, 325 i = wait_for_completion_timeout(&am33xx_pm_sync,
325 msecs_to_jiffies(500)); 326 msecs_to_jiffies(500));
326 if (!i) { 327 if (!i) {
327 WARN(1, "PM: MPU<->CM3 sync failure\n"); 328 WARN(1, "PM: MPU<->CM3 sync failure\n");
328 am33xx_pm->state = M3_STATE_UNKNOWN; 329 am33xx_pm->state = M3_STATE_UNKNOWN;
329 } 330 }
330 } else { 331 } else {
331 pr_warn("PM: Unable to ping CM3\n"); 332 pr_warn("PM: Unable to ping CM3\n");
332 } 333 }
333 } 334 }
334 335
335 static int am33xx_pm_begin(suspend_state_t state) 336 static int am33xx_pm_begin(suspend_state_t state)
336 { 337 {
337 int i; 338 int i;
338 339
339 cpu_idle_poll_ctrl(true); 340 cpu_idle_poll_ctrl(true);
340 341
341 switch (state) { 342 switch (state) {
342 case PM_SUSPEND_MEM: 343 case PM_SUSPEND_MEM:
343 am33xx_pm->ipc.reg1 = IPC_CMD_DS0; 344 am33xx_pm->ipc.reg1 = IPC_CMD_DS0;
345 am33xx_pm->ipc.reg5 = am33xx_pm->m3_i2c_sequence_offsets;
344 break; 346 break;
345 case PM_SUSPEND_STANDBY: 347 case PM_SUSPEND_STANDBY:
346 am33xx_pm->ipc.reg1 = IPC_CMD_STANDBY; 348 am33xx_pm->ipc.reg1 = IPC_CMD_STANDBY;
349 am33xx_pm->ipc.reg5 = DS_IPC_DEFAULT;
347 break; 350 break;
348 } 351 }
349 352
350 am33xx_pm->ipc.reg2 = DS_IPC_DEFAULT; 353 am33xx_pm->ipc.reg2 = DS_IPC_DEFAULT;
351 am33xx_pm->ipc.reg3 = DS_IPC_DEFAULT; 354 am33xx_pm->ipc.reg3 = DS_IPC_DEFAULT;
352 355
353 wkup_m3_set_cmd(&am33xx_pm->ipc); 356 wkup_m3_set_cmd(&am33xx_pm->ipc);
354 357
355 am33xx_pm->state = M3_STATE_MSG_FOR_LP; 358 am33xx_pm->state = M3_STATE_MSG_FOR_LP;
356 359
357 if (!wkup_m3_ping()) { 360 if (!wkup_m3_ping()) {
358 i = wait_for_completion_timeout(&am33xx_pm_sync, 361 i = wait_for_completion_timeout(&am33xx_pm_sync,
359 msecs_to_jiffies(500)); 362 msecs_to_jiffies(500));
360 if (!i) { 363 if (!i) {
361 WARN(1, "PM: MPU<->CM3 sync failure\n"); 364 WARN(1, "PM: MPU<->CM3 sync failure\n");
362 return -1; 365 return -1;
363 } 366 }
364 } else { 367 } else {
365 pr_warn("PM: Unable to ping CM3\n"); 368 pr_warn("PM: Unable to ping CM3\n");
366 return -1; 369 return -1;
367 } 370 }
368 371
369 return 0; 372 return 0;
370 } 373 }
371 374
372 static void am33xx_pm_end(void) 375 static void am33xx_pm_end(void)
373 { 376 {
374 am33xx_m3_state_machine_reset(); 377 am33xx_m3_state_machine_reset();
375 378
376 if (retrigger_irq) 379 if (retrigger_irq)
377 writel_relaxed(1 << (retrigger_irq & 31), 380 writel_relaxed(1 << (retrigger_irq & 31),
378 gic_dist_base + 0x200 + retrigger_irq / 32 * 4); 381 gic_dist_base + 0x200 + retrigger_irq / 32 * 4);
379 382
380 cpu_idle_poll_ctrl(false); 383 cpu_idle_poll_ctrl(false);
381 } 384 }
382 385
383 static int am33xx_pm_valid(suspend_state_t state) 386 static int am33xx_pm_valid(suspend_state_t state)
384 { 387 {
385 switch (state) { 388 switch (state) {
386 case PM_SUSPEND_STANDBY: 389 case PM_SUSPEND_STANDBY:
387 case PM_SUSPEND_MEM: 390 case PM_SUSPEND_MEM:
388 return 1; 391 return 1;
389 default: 392 default:
390 return 0; 393 return 0;
391 } 394 }
392 } 395 }
393 396
394 static const struct platform_suspend_ops am33xx_pm_ops = { 397 static const struct platform_suspend_ops am33xx_pm_ops = {
395 .begin = am33xx_pm_begin, 398 .begin = am33xx_pm_begin,
396 .end = am33xx_pm_end, 399 .end = am33xx_pm_end,
397 .enter = am33xx_pm_enter, 400 .enter = am33xx_pm_enter,
398 .valid = am33xx_pm_valid, 401 .valid = am33xx_pm_valid,
399 }; 402 };
400 #endif /* CONFIG_SUSPEND */ 403 #endif /* CONFIG_SUSPEND */
401 404
402 static void am33xx_scale_data_fw_cb(const struct firmware *fw, void *context) 405 static void am33xx_scale_data_fw_cb(const struct firmware *fw, void *context)
403 { 406 {
404 unsigned long val, aux_base; 407 unsigned long val, aux_base;
405 struct wkup_m3_scale_data_header hdr; 408 struct wkup_m3_scale_data_header hdr;
406 409
407 if (!fw) { 410 if (!fw) {
408 pr_info("PM: Voltage scale fw name given but file missing.\n"); 411 pr_info("PM: Voltage scale fw name given but file missing.\n");
409 return; 412 return;
410 } 413 }
411 414
412 memcpy(&hdr, fw->data, sizeof(hdr)); 415 memcpy(&hdr, fw->data, sizeof(hdr));
413 416
414 if (hdr.magic != WKUP_M3_SD_FW_MAGIC) { 417 if (hdr.magic != WKUP_M3_SD_FW_MAGIC) {
415 pr_info("PM: Voltage Scale Data binary does not appear valid.\n"); 418 pr_info("PM: Voltage Scale Data binary does not appear valid.\n");
416 goto release_sd_fw; 419 goto release_sd_fw;
417 } 420 }
418 421
419 aux_base = wkup_m3_copy_aux_data(fw->data + sizeof(hdr), 422 aux_base = wkup_m3_copy_aux_data(fw->data + sizeof(hdr),
420 fw->size - sizeof(hdr)); 423 fw->size - sizeof(hdr));
421 424
422 val = (aux_base + hdr.sleep_offset); 425 val = (aux_base + hdr.sleep_offset);
423 val |= ((aux_base + hdr.wake_offset) << 16); 426 val |= ((aux_base + hdr.wake_offset) << 16);
424 427
425 am33xx_pm->ipc.reg5 = val; 428 am33xx_pm->m3_i2c_sequence_offsets = val;
426 429
427 release_sd_fw: 430 release_sd_fw:
428 release_firmware(fw); 431 release_firmware(fw);
429 }; 432 };
430 433
431 static int __init 434 static int __init
432 am33xx_init_scale_data(struct device *dev, const char *sd_fw_name) 435 am33xx_init_scale_data(struct device *dev, const char *sd_fw_name)
433 { 436 {
434 int ret = 0; 437 int ret = 0;
435 438
436 /* 439 /*
437 * If no name is provided, user has already been warned, pm will 440 * If no name is provided, user has already been warned, pm will
438 * still work so return 0 441 * still work so return 0
439 */ 442 */
440 if (!sd_fw_name) 443 if (!sd_fw_name)
441 return ret; 444 return ret;
442 445
443 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, 446 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
444 sd_fw_name, dev, GFP_KERNEL, NULL, 447 sd_fw_name, dev, GFP_KERNEL, NULL,
445 am33xx_scale_data_fw_cb); 448 am33xx_scale_data_fw_cb);
446 449
447 return ret; 450 return ret;
448 } 451 }
449 452
450 static void am33xx_txev_handler(void) 453 static void am33xx_txev_handler(void)
451 { 454 {
452 switch (am33xx_pm->state) { 455 switch (am33xx_pm->state) {
453 case M3_STATE_RESET: 456 case M3_STATE_RESET:
454 am33xx_pm->state = M3_STATE_INITED; 457 am33xx_pm->state = M3_STATE_INITED;
455 complete(&am33xx_pm_sync); 458 complete(&am33xx_pm_sync);
456 break; 459 break;
457 case M3_STATE_MSG_FOR_RESET: 460 case M3_STATE_MSG_FOR_RESET:
458 am33xx_pm->state = M3_STATE_INITED; 461 am33xx_pm->state = M3_STATE_INITED;
459 complete(&am33xx_pm_sync); 462 complete(&am33xx_pm_sync);
460 break; 463 break;
461 case M3_STATE_MSG_FOR_LP: 464 case M3_STATE_MSG_FOR_LP:
462 complete(&am33xx_pm_sync); 465 complete(&am33xx_pm_sync);
463 break; 466 break;
464 case M3_STATE_UNKNOWN: 467 case M3_STATE_UNKNOWN:
465 pr_warn("PM: Unknown CM3 State\n"); 468 pr_warn("PM: Unknown CM3 State\n");
466 } 469 }
467 } 470 }
468 471
469 static void am33xx_m3_ready_cb(struct device *m3_dev) 472 static void am33xx_m3_ready_cb(struct device *m3_dev)
470 { 473 {
471 int ret; 474 int ret;
472 475
473 am33xx_pm->ver = wkup_m3_fw_version_read(); 476 am33xx_pm->ver = wkup_m3_fw_version_read();
474 477
475 if (am33xx_pm->ver == M3_VERSION_UNKNOWN || 478 if (am33xx_pm->ver == M3_VERSION_UNKNOWN ||
476 am33xx_pm->ver < M3_BASELINE_VERSION) { 479 am33xx_pm->ver < M3_BASELINE_VERSION) {
477 pr_warn("PM: CM3 Firmware Version %x not supported\n", 480 pr_warn("PM: CM3 Firmware Version %x not supported\n",
478 am33xx_pm->ver); 481 am33xx_pm->ver);
479 return; 482 return;
480 } else { 483 } else {
481 pr_info("PM: CM3 Firmware Version = 0x%x\n", 484 pr_info("PM: CM3 Firmware Version = 0x%x\n",
482 am33xx_pm->ver); 485 am33xx_pm->ver);
483 } 486 }
484 487
485 if (soc_is_am33xx()) 488 if (soc_is_am33xx())
486 am33xx_idle_init(susp_params.wfi_flags & WFI_MEM_TYPE_DDR3); 489 am33xx_idle_init(susp_params.wfi_flags & WFI_MEM_TYPE_DDR3);
487 else if (soc_is_am437x()) 490 else if (soc_is_am437x())
488 am437x_idle_init(); 491 am437x_idle_init();
489 492
490 ret = am33xx_init_scale_data(m3_dev, am33xx_pm->sd_fw_name); 493 ret = am33xx_init_scale_data(m3_dev, am33xx_pm->sd_fw_name);
491 if (ret) 494 if (ret)
492 pr_err("PM: Cannot load voltage scaling data blob: %d\n", ret); 495 pr_err("PM: Cannot load voltage scaling data blob: %d\n", ret);
493 496
494 #ifdef CONFIG_SUSPEND 497 #ifdef CONFIG_SUSPEND
495 suspend_set_ops(&am33xx_pm_ops); 498 suspend_set_ops(&am33xx_pm_ops);
496 #endif /* CONFIG_SUSPEND */ 499 #endif /* CONFIG_SUSPEND */
497 } 500 }
498 501
499 static struct wkup_m3_ops am33xx_wkup_m3_ops = { 502 static struct wkup_m3_ops am33xx_wkup_m3_ops = {
500 .txev_handler = am33xx_txev_handler, 503 .txev_handler = am33xx_txev_handler,
501 .rproc_ready = am33xx_m3_ready_cb, 504 .rproc_ready = am33xx_m3_ready_cb,
502 }; 505 };
503 506
504 /* 507 /*
505 * Push the minimal suspend-resume code to SRAM 508 * Push the minimal suspend-resume code to SRAM
506 */ 509 */
507 #ifdef CONFIG_SOC_AM33XX 510 #ifdef CONFIG_SOC_AM33XX
508 void am33xx_push_sram_idle(void) 511 void am33xx_push_sram_idle(void)
509 { 512 {
510 am33xx_do_wfi_sram = (void *)omap_sram_push 513 am33xx_do_wfi_sram = (void *)omap_sram_push
511 (am33xx_do_wfi, am33xx_do_wfi_sz); 514 (am33xx_do_wfi, am33xx_do_wfi_sz);
512 } 515 }
513 #endif 516 #endif
514 517
515 #ifdef CONFIG_SOC_AM43XX 518 #ifdef CONFIG_SOC_AM43XX
516 void am43xx_push_sram_idle(void) 519 void am43xx_push_sram_idle(void)
517 { 520 {
518 am33xx_do_wfi_sram = (void *)omap_sram_push 521 am33xx_do_wfi_sram = (void *)omap_sram_push
519 (am43xx_do_wfi, am43xx_do_wfi_sz); 522 (am43xx_do_wfi, am43xx_do_wfi_sz);
520 } 523 }
521 #endif 524 #endif
522 525
523 static int __init am33xx_map_emif(void) 526 static int __init am33xx_map_emif(void)
524 { 527 {
525 am33xx_emif_base = ioremap(AM33XX_EMIF_BASE, SZ_32K); 528 am33xx_emif_base = ioremap(AM33XX_EMIF_BASE, SZ_32K);
526 529
527 if (!am33xx_emif_base) 530 if (!am33xx_emif_base)
528 return -ENOMEM; 531 return -ENOMEM;
529 532
530 return 0; 533 return 0;
531 } 534 }
532 535
533 #ifdef CONFIG_SUSPEND 536 #ifdef CONFIG_SUSPEND
534 static int __init am43xx_map_scu(void) 537 static int __init am43xx_map_scu(void)
535 { 538 {
536 scu_base = ioremap(scu_a9_get_base(), SZ_256); 539 scu_base = ioremap(scu_a9_get_base(), SZ_256);
537 540
538 if (!scu_base) 541 if (!scu_base)
539 return -ENOMEM; 542 return -ENOMEM;
540 543
541 return 0; 544 return 0;
542 } 545 }
543 546
544 static int __init am43xx_map_gic(void) 547 static int __init am43xx_map_gic(void)
545 { 548 {
546 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K); 549 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
547 550
548 if (!gic_dist_base) 551 if (!gic_dist_base)
549 return -ENOMEM; 552 return -ENOMEM;
550 553
551 return 0; 554 return 0;
552 } 555 }
553 556
554 static int am33xx_suspend_init(void) 557 static int am33xx_suspend_init(void)
555 { 558 {
556 u32 temp; 559 u32 temp;
557 560
558 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); 561 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
559 562
560 if (!gfx_l4ls_clkdm) { 563 if (!gfx_l4ls_clkdm) {
561 pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n"); 564 pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n");
562 return -ENODEV; 565 return -ENODEV;
563 } 566 }
564 567
565 /* Physical resume address to be used by ROM code */ 568 /* Physical resume address to be used by ROM code */
566 am33xx_pm->ipc.reg0 = (AM33XX_OCMC_END - 569 am33xx_pm->ipc.reg0 = (AM33XX_OCMC_END -
567 am33xx_do_wfi_sz + am33xx_resume_offset + 0x4); 570 am33xx_do_wfi_sz + am33xx_resume_offset + 0x4);
568 571
569 /* 572 /*
570 * Save SDRAM config in shadow register. 573 * Save SDRAM config in shadow register.
571 * When the EMIF gets powered back up, its SDRAM_CONFIG register gets 574 * When the EMIF gets powered back up, its SDRAM_CONFIG register gets
572 * loaded from the SECURE_SDRAM_CONFIG register. 575 * loaded from the SECURE_SDRAM_CONFIG register.
573 */ 576 */
574 temp = readl(am33xx_emif_base + EMIF_SDRAM_CONFIG); 577 temp = readl(am33xx_emif_base + EMIF_SDRAM_CONFIG);
575 omap_ctrl_writel(temp, AM33XX_CONTROL_SECURE_SDRAM_CONFIG); 578 omap_ctrl_writel(temp, AM33XX_CONTROL_SECURE_SDRAM_CONFIG);
576 579
577 return 0; 580 return 0;
578 } 581 }
579 582
580 static int am43xx_suspend_init(void) 583 static int am43xx_suspend_init(void)
581 { 584 {
582 int ret = 0; 585 int ret = 0;
583 586
584 ret = am43xx_map_scu(); 587 ret = am43xx_map_scu();
585 if (ret) { 588 if (ret) {
586 pr_err("PM: Could not ioremap SCU\n"); 589 pr_err("PM: Could not ioremap SCU\n");
587 return ret; 590 return ret;
588 } 591 }
589 592
590 ret = am43xx_map_gic(); 593 ret = am43xx_map_gic();
591 if (ret) { 594 if (ret) {
592 pr_err("PM: Could not ioremap GIC\n"); 595 pr_err("PM: Could not ioremap GIC\n");
593 return ret; 596 return ret;
594 } 597 }
595 598
596 susp_params.l2_base_virt = omap4_get_l2cache_base(); 599 susp_params.l2_base_virt = omap4_get_l2cache_base();
597 600
598 if (!susp_params.l2_base_virt) { 601 if (!susp_params.l2_base_virt) {
599 pr_err("PM: Could not get l2 cache base address\n"); 602 pr_err("PM: Could not get l2 cache base address\n");
600 return -ENOMEM; 603 return -ENOMEM;
601 } 604 }
602 605
603 susp_params.cke_override_virt = 606 susp_params.cke_override_virt =
604 ioremap(AM43XX_CTRL_CKE_OVERRIDE, SZ_4); 607 ioremap(AM43XX_CTRL_CKE_OVERRIDE, SZ_4);
605 608
606 if (!susp_params.cke_override_virt) { 609 if (!susp_params.cke_override_virt) {
607 pr_err("PM: Could not ioremap CKE override in Control Module\n"); 610 pr_err("PM: Could not ioremap CKE override in Control Module\n");
608 return -ENOMEM; 611 return -ENOMEM;
609 } 612 }
610 613
611 /* Physical resume address to be used by ROM code */ 614 /* Physical resume address to be used by ROM code */
612 am33xx_pm->ipc.reg0 = (AM33XX_OCMC_END - 615 am33xx_pm->ipc.reg0 = (AM33XX_OCMC_END -
613 am43xx_do_wfi_sz + am43xx_resume_offset + 0x4); 616 am43xx_do_wfi_sz + am43xx_resume_offset + 0x4);
614 617
615 return ret; 618 return ret;
616 } 619 }
617 620
618 static void am33xx_pre_suspend(unsigned int state) 621 static void am33xx_pre_suspend(unsigned int state)
619 { 622 {
620 return; 623 return;
621 } 624 }
622 625
623 static void am43xx_pre_suspend(unsigned int state) 626 static void am43xx_pre_suspend(unsigned int state)
624 { 627 {
625 scu_power_mode(scu_base, SCU_PM_POWEROFF); 628 scu_power_mode(scu_base, SCU_PM_POWEROFF);
626 } 629 }
627 630
628 static void am33xx_post_suspend(unsigned int state) 631 static void am33xx_post_suspend(unsigned int state)
629 { 632 {
630 /* 633 /*
631 * BUG: GFX_L4LS clock domain needs to be woken up to 634 * BUG: GFX_L4LS clock domain needs to be woken up to
632 * ensure thet L4LS clock domain does not get stuck in 635 * ensure thet L4LS clock domain does not get stuck in
633 * transition. If that happens L3 module does not get 636 * transition. If that happens L3 module does not get
634 * disabled, thereby leading to PER power domain 637 * disabled, thereby leading to PER power domain
635 * transition failing 638 * transition failing
636 */ 639 */
637 clkdm_wakeup(gfx_l4ls_clkdm); 640 clkdm_wakeup(gfx_l4ls_clkdm);
638 clkdm_sleep(gfx_l4ls_clkdm); 641 clkdm_sleep(gfx_l4ls_clkdm);
639 } 642 }
640 643
641 static void am43xx_post_suspend(unsigned int state) 644 static void am43xx_post_suspend(unsigned int state)
642 { 645 {
643 scu_power_mode(scu_base, SCU_PM_NORMAL); 646 scu_power_mode(scu_base, SCU_PM_NORMAL);
644 } 647 }
645 648
646 static struct am33xx_pm_ops am33xx_ops = { 649 static struct am33xx_pm_ops am33xx_ops = {
647 .init = am33xx_suspend_init, 650 .init = am33xx_suspend_init,
648 .pre_suspend = am33xx_pre_suspend, 651 .pre_suspend = am33xx_pre_suspend,
649 .post_suspend = am33xx_post_suspend, 652 .post_suspend = am33xx_post_suspend,
650 .save_context = am33xx_save_context, 653 .save_context = am33xx_save_context,
651 .restore_context = am33xx_restore_context, 654 .restore_context = am33xx_restore_context,
652 }; 655 };
653 656
654 static struct am33xx_pm_ops am43xx_ops = { 657 static struct am33xx_pm_ops am43xx_ops = {
655 .init = am43xx_suspend_init, 658 .init = am43xx_suspend_init,
656 .pre_suspend = am43xx_pre_suspend, 659 .pre_suspend = am43xx_pre_suspend,
657 .post_suspend = am43xx_post_suspend, 660 .post_suspend = am43xx_post_suspend,
658 .save_context = am43xx_save_context, 661 .save_context = am43xx_save_context,
659 .restore_context = am43xx_restore_context, 662 .restore_context = am43xx_restore_context,
660 }; 663 };
661 #endif /* CONFIG_SUSPEND */ 664 #endif /* CONFIG_SUSPEND */
662 #endif /* CONFIG_CPU_PM */ 665 #endif /* CONFIG_CPU_PM */
663 666
664 int __init am33xx_pm_init(void) 667 int __init am33xx_pm_init(void)
665 { 668 {
666 #ifdef CONFIG_CPU_PM 669 #ifdef CONFIG_CPU_PM
667 int ret; 670 int ret;
668 u32 temp; 671 u32 temp;
669 struct device_node *np; 672 struct device_node *np;
670 #endif /* CONFIG_CPU_PM */ 673 #endif /* CONFIG_CPU_PM */
671 674
672 if (!soc_is_am33xx() && !soc_is_am43xx()) 675 if (!soc_is_am33xx() && !soc_is_am43xx())
673 return -ENODEV; 676 return -ENODEV;
674 677
675 #ifdef CONFIG_CPU_PM 678 #ifdef CONFIG_CPU_PM
676 am33xx_pm = kzalloc(sizeof(*am33xx_pm), GFP_KERNEL); 679 am33xx_pm = kzalloc(sizeof(*am33xx_pm), GFP_KERNEL);
677 if (!am33xx_pm) { 680 if (!am33xx_pm) {
678 pr_err("Memory allocation failed\n"); 681 pr_err("Memory allocation failed\n");
679 ret = -ENOMEM; 682 ret = -ENOMEM;
680 return ret; 683 return ret;
681 } 684 }
682 685
683 ret = am33xx_map_emif(); 686 ret = am33xx_map_emif();
684 if (ret) { 687 if (ret) {
685 pr_err("PM: Could not ioremap EMIF\n"); 688 pr_err("PM: Could not ioremap EMIF\n");
686 goto err; 689 goto err;
687 } 690 }
688 691
689 #ifdef CONFIG_SUSPEND 692 #ifdef CONFIG_SUSPEND
690 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); 693 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
691 per_pwrdm = pwrdm_lookup("per_pwrdm"); 694 per_pwrdm = pwrdm_lookup("per_pwrdm");
692 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 695 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
693 696
694 if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm)) 697 if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm))
695 return -ENODEV; 698 return -ENODEV;
696 699
697 /* 700 /*
698 * Code paths for each SoC are nearly the same but set ops 701 * Code paths for each SoC are nearly the same but set ops
699 * handle differences during init, pre-suspend, and post-suspend 702 * handle differences during init, pre-suspend, and post-suspend
700 */ 703 */
701 704
702 if (soc_is_am33xx()) 705 if (soc_is_am33xx())
703 am33xx_pm->ops = &am33xx_ops; 706 am33xx_pm->ops = &am33xx_ops;
704 else if (soc_is_am43xx()) 707 else if (soc_is_am43xx())
705 am33xx_pm->ops = &am43xx_ops; 708 am33xx_pm->ops = &am43xx_ops;
706 709
707 ret = am33xx_pm->ops->init(); 710 ret = am33xx_pm->ops->init();
708 711
709 if (ret) 712 if (ret)
710 goto err; 713 goto err;
711 #endif /* CONFIG_SUSPEND */ 714 #endif /* CONFIG_SUSPEND */
712 715
713 /* Determine Memory Type */ 716 /* Determine Memory Type */
714 temp = readl(am33xx_emif_base + EMIF_SDRAM_CONFIG); 717 temp = readl(am33xx_emif_base + EMIF_SDRAM_CONFIG);
715 temp = (temp & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT; 718 temp = (temp & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
716 /* Parameters to pass to assembly code */ 719 /* Parameters to pass to assembly code */
717 susp_params.wfi_flags = 0; 720 susp_params.wfi_flags = 0;
718 susp_params.emif_addr_virt = am33xx_emif_base; 721 susp_params.emif_addr_virt = am33xx_emif_base;
719 susp_params.dram_sync = am33xx_dram_sync; 722 susp_params.dram_sync = am33xx_dram_sync;
720 susp_params.rtc_base = omap_rtc_get_base_addr(); 723 susp_params.rtc_base = omap_rtc_get_base_addr();
721 724
722 switch (temp) { 725 switch (temp) {
723 case MEM_TYPE_DDR2: 726 case MEM_TYPE_DDR2:
724 susp_params.wfi_flags |= WFI_MEM_TYPE_DDR2; 727 susp_params.wfi_flags |= WFI_MEM_TYPE_DDR2;
725 break; 728 break;
726 case MEM_TYPE_DDR3: 729 case MEM_TYPE_DDR3:
727 susp_params.wfi_flags |= WFI_MEM_TYPE_DDR3; 730 susp_params.wfi_flags |= WFI_MEM_TYPE_DDR3;
728 break; 731 break;
729 } 732 }
730 susp_params.wfi_flags |= WFI_SELF_REFRESH; 733 susp_params.wfi_flags |= WFI_SELF_REFRESH;
731 susp_params.wfi_flags |= WFI_SAVE_EMIF; 734 susp_params.wfi_flags |= WFI_SAVE_EMIF;
732 susp_params.wfi_flags |= WFI_DISABLE_EMIF; 735 susp_params.wfi_flags |= WFI_DISABLE_EMIF;
733 susp_params.wfi_flags |= WFI_WAKE_M3; 736 susp_params.wfi_flags |= WFI_WAKE_M3;
734 737
735 am33xx_pm->ipc.reg4 = temp & MEM_TYPE_MASK; 738 am33xx_pm->ipc.reg4 = temp & MEM_TYPE_MASK;
736 739
737 np = of_find_compatible_node(NULL, NULL, "ti,am3353-wkup-m3"); 740 np = of_find_compatible_node(NULL, NULL, "ti,am3353-wkup-m3");
738 if (np) { 741 if (np) {
739 if (of_find_property(np, "ti,needs-vtt-toggle", NULL) && 742 if (of_find_property(np, "ti,needs-vtt-toggle", NULL) &&
740 (!(of_property_read_u32(np, "ti,vtt-gpio-pin", 743 (!(of_property_read_u32(np, "ti,vtt-gpio-pin",
741 &temp)))) { 744 &temp)))) {
742 if (temp >= 0 && temp <= 31) 745 if (temp >= 0 && temp <= 31)
743 am33xx_pm->ipc.reg4 |= 746 am33xx_pm->ipc.reg4 |=
744 ((1 << VTT_STAT_SHIFT) | 747 ((1 << VTT_STAT_SHIFT) |
745 (temp << VTT_GPIO_PIN_SHIFT)); 748 (temp << VTT_GPIO_PIN_SHIFT));
746 else 749 else
747 pr_warn("PM: Invalid VTT GPIO(%d) pin\n", temp); 750 pr_warn("PM: Invalid VTT GPIO(%d) pin\n", temp);
748 } 751 }
749 752
750 if (of_find_property(np, "ti,set-io-isolation", NULL)) 753 if (of_find_property(np, "ti,set-io-isolation", NULL))
751 am33xx_pm->ipc.reg4 |= (1 << IO_ISOLATION_STAT_SHIFT); 754 am33xx_pm->ipc.reg4 |= (1 << IO_ISOLATION_STAT_SHIFT);
752 755
753 ret = of_property_read_string(np, "ti,scale-data-fw", 756 ret = of_property_read_string(np, "ti,scale-data-fw",
754 &am33xx_pm->sd_fw_name); 757 &am33xx_pm->sd_fw_name);
755 if (ret) { 758 if (ret) {
756 pr_warn("PM: Voltage scaling data blob not provided from DT.\n"); 759 pr_warn("PM: Voltage scaling data blob not provided from DT.\n");
757 }; 760 };
758 } 761 }
759 762
760 #endif /* CONFIG_CPU_PM */ 763 #endif /* CONFIG_CPU_PM */
761 764
762 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 765 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
763 766
764 /* CEFUSE domain can be turned off post bootup */ 767 /* CEFUSE domain can be turned off post bootup */
765 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); 768 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
766 if (cefuse_pwrdm) 769 if (cefuse_pwrdm)
767 omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF); 770 omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
768 else 771 else
769 pr_err("PM: Failed to get cefuse_pwrdm\n"); 772 pr_err("PM: Failed to get cefuse_pwrdm\n");
770 773
771 rtc_oh = omap_hwmod_lookup("rtc"); 774 rtc_oh = omap_hwmod_lookup("rtc");
772 if (!rtc_oh) { 775 if (!rtc_oh) {
773 pr_err("PM: could not locate rtc hwmod\n"); 776 pr_err("PM: could not locate rtc hwmod\n");
774 ret = -ENOENT; 777 ret = -ENOENT;
775 goto err; 778 goto err;
776 } 779 }
777 780
778 #ifdef CONFIG_CPU_PM 781 #ifdef CONFIG_CPU_PM
779 am33xx_pm->state = M3_STATE_RESET; 782 am33xx_pm->state = M3_STATE_RESET;
780 783
781 wkup_m3_set_ops(&am33xx_wkup_m3_ops); 784 wkup_m3_set_ops(&am33xx_wkup_m3_ops);
782 785
783 pmx_dev = get_pinctrl_dev_from_devname("44e10800.pinmux"); 786 pmx_dev = get_pinctrl_dev_from_devname("44e10800.pinmux");
784 787
785 np = of_find_node_by_name(NULL, "rtc"); 788 np = of_find_node_by_name(NULL, "rtc");
786 789
787 if (of_device_is_available(np)) { 790 if (of_device_is_available(np)) {
788 omap_rtc = rtc_class_open("rtc0"); 791 omap_rtc = rtc_class_open("rtc0");
789 792
790 rtc_read_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, 793 rtc_read_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG,
791 &rtc_magic_val); 794 &rtc_magic_val);
792 795
793 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC) 796 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
794 pr_warn("PM: bootloader does not support rtc-only!\n"); 797 pr_warn("PM: bootloader does not support rtc-only!\n");
795 798
796 rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, 0); 799 rtc_write_scratch(omap_rtc, RTC_SCRATCH_MAGIC_REG, 0);
797 rtc_write_scratch(omap_rtc, RTC_SCRATCH_RESUME_REG, 800 rtc_write_scratch(omap_rtc, RTC_SCRATCH_RESUME_REG,
798 virt_to_phys(cpu_resume)); 801 virt_to_phys(cpu_resume));
799 } else 802 } else
800 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n"); 803 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
801 804
802 return 0; 805 return 0;
803 806
804 err: 807 err:
805 kfree(am33xx_pm); 808 kfree(am33xx_pm);
806 return ret; 809 return ret;
807 #endif /* CONFIG_CPU_PM */ 810 #endif /* CONFIG_CPU_PM */
808 } 811 }
809 812
arch/arm/mach-omap2/pm33xx.h
Diff comments   View file @ 14ed5c8
1 /* 1 /*
2 * AM33XX Power Management Routines 2 * AM33XX Power Management Routines
3 * 3 *
4 * Copyright (C) 2012-2014 Texas Instruments Inc. 4 * Copyright (C) 2012-2014 Texas Instruments Inc.
5 * Vaibhav Bedia, Dave Gerlach 5 * Vaibhav Bedia, Dave Gerlach
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2. 9 * published by the Free Software Foundation version 2.
10 * 10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty 12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H 16 #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
17 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H 17 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
18 18
19 #ifndef __ASSEMBLER__ 19 #ifndef __ASSEMBLER__
20 20
21 #include <linux/wkup_m3.h> 21 #include <linux/wkup_m3.h>
22 22
23 struct am33xx_pm_ops { 23 struct am33xx_pm_ops {
24 int (*init)(void); 24 int (*init)(void);
25 void (*pre_suspend)(unsigned int state); 25 void (*pre_suspend)(unsigned int state);
26 void (*post_suspend)(unsigned int state); 26 void (*post_suspend)(unsigned int state);
27 void (*save_context)(void); 27 void (*save_context)(void);
28 void (*restore_context)(void); 28 void (*restore_context)(void);
29 }; 29 };
30 30
31 struct am33xx_pm_context { 31 struct am33xx_pm_context {
32 struct wkup_m3_ipc_regs ipc; 32 struct wkup_m3_ipc_regs ipc;
33 struct firmware *firmware; 33 struct firmware *firmware;
34 struct omap_mbox *mbox; 34 struct omap_mbox *mbox;
35 struct am33xx_pm_ops *ops; 35 struct am33xx_pm_ops *ops;
36 u8 state; 36 u8 state;
37 u32 ver; 37 u32 ver;
38 u32 m3_i2c_sequence_offsets;
38 const char *sd_fw_name; 39 const char *sd_fw_name;
39 }; 40 };
40 41
41 /* 42 /*
42 * Params passed to suspend routine 43 * Params passed to suspend routine
43 * 44 *
44 * These are used to load into registers by suspend code, 45 * These are used to load into registers by suspend code,
45 * entries here must always be in sync with the suspend code 46 * entries here must always be in sync with the suspend code
46 * in arm/mach-omap2/sleep33xx.S 47 * in arm/mach-omap2/sleep33xx.S
47 */ 48 */
48 struct am33xx_suspend_params { 49 struct am33xx_suspend_params {
49 void __iomem *emif_addr_virt; 50 void __iomem *emif_addr_virt;
50 u32 wfi_flags; 51 u32 wfi_flags;
51 void __iomem *dram_sync; 52 void __iomem *dram_sync;
52 void __iomem *rtc_base; 53 void __iomem *rtc_base;
53 void __iomem *l2_base_virt; 54 void __iomem *l2_base_virt;
54 void __iomem *cke_override_virt; 55 void __iomem *cke_override_virt;
55 }; 56 };
56 57
57 void wkup_m3_reset_data_pos(void); 58 void wkup_m3_reset_data_pos(void);
58 int wkup_m3_copy_data(const u8 *data, size_t size); 59 int wkup_m3_copy_data(const u8 *data, size_t size);
59 int am33xx_do_sram_cpuidle(u32, u32); 60 int am33xx_do_sram_cpuidle(u32, u32);
60 void omap_rtc_power_off_program(void); 61 void omap_rtc_power_off_program(void);
61 void __iomem *omap_rtc_get_base_addr(void); 62 void __iomem *omap_rtc_get_base_addr(void);
62 63
63 #endif /*__ASSEMBLER__ */ 64 #endif /*__ASSEMBLER__ */
64 65
65 #define IPC_CMD_RTC_ONLY 0x1 66 #define IPC_CMD_RTC_ONLY 0x1
66 #define IPC_CMD_DS0 0x4 67 #define IPC_CMD_DS0 0x4
67 #define IPC_CMD_STANDBY 0xc 68 #define IPC_CMD_STANDBY 0xc
68 #define IPC_CMD_IDLE 0xd 69 #define IPC_CMD_IDLE 0xd
69 #define IPC_CMD_RESET 0xe 70 #define IPC_CMD_RESET 0xe
70 #define DS_IPC_DEFAULT 0xffffffff 71 #define DS_IPC_DEFAULT 0xffffffff
71 #define M3_VERSION_UNKNOWN 0x0000ffff 72 #define M3_VERSION_UNKNOWN 0x0000ffff
72 #define M3_BASELINE_VERSION 0x189 73 #define M3_BASELINE_VERSION 0x190
73 74
74 #define M3_STATE_UNKNOWN 0 75 #define M3_STATE_UNKNOWN 0
75 #define M3_STATE_RESET 1 76 #define M3_STATE_RESET 1
76 #define M3_STATE_INITED 2 77 #define M3_STATE_INITED 2
77 #define M3_STATE_MSG_FOR_LP 3 78 #define M3_STATE_MSG_FOR_LP 3
78 #define M3_STATE_MSG_FOR_RESET 4 79 #define M3_STATE_MSG_FOR_RESET 4
79 80
80 #define AM33XX_OCMC_END 0x40310000 81 #define AM33XX_OCMC_END 0x40310000
81 #define AM33XX_EMIF_BASE 0x4C000000 82 #define AM33XX_EMIF_BASE 0x4C000000
82 83
83 #define AM43XX_CM_BASE 0x44DF0000 84 #define AM43XX_CM_BASE 0x44DF0000
84 85
85 #define AM43XX_CTRL_CKE_OVERRIDE 0x44E1131C 86 #define AM43XX_CTRL_CKE_OVERRIDE 0x44E1131C
86 87
87 #define AM43XX_CM_REGADDR(inst, reg) \ 88 #define AM43XX_CM_REGADDR(inst, reg) \
88 AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg)) 89 AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg))
89 90
90 #define AM43XX_PM_MPU_PWRSTCTRL AM43XX_CM_REGADDR(0x0300, 0x00) 91 #define AM43XX_PM_MPU_PWRSTCTRL AM43XX_CM_REGADDR(0x0300, 0x00)
91 #define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(0x8300, 0x00) 92 #define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(0x8300, 0x00)
92 #define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(0x8300, 0x20) 93 #define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(0x8300, 0x20)
93 #define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(0x8800, 0x0720) 94 #define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(0x8800, 0x0720)
94 95
95 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 96 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720
96 #define AM43XX_PRM_EMIF_CTRL_OFFSET 0x30 97 #define AM43XX_PRM_EMIF_CTRL_OFFSET 0x30
97 98
98 #define MEM_TYPE_DDR2 2 99 #define MEM_TYPE_DDR2 2
99 #define MEM_TYPE_DDR3 3 100 #define MEM_TYPE_DDR3 3
100 101
101 #define WFI_MEM_TYPE_DDR2 (1 << 0) 102 #define WFI_MEM_TYPE_DDR2 (1 << 0)
102 #define WFI_MEM_TYPE_DDR3 (1 << 1) 103 #define WFI_MEM_TYPE_DDR3 (1 << 1)
103 #define WFI_SELF_REFRESH (1 << 2) 104 #define WFI_SELF_REFRESH (1 << 2)
104 #define WFI_SAVE_EMIF (1 << 3) 105 #define WFI_SAVE_EMIF (1 << 3)
105 #define WFI_WAKE_M3 (1 << 4) 106 #define WFI_WAKE_M3 (1 << 4)
106 #define WFI_DISABLE_EMIF (1 << 7) 107 #define WFI_DISABLE_EMIF (1 << 7)
107 #define WFI_RTC_ONLY (1 << 8) 108 #define WFI_RTC_ONLY (1 << 8)
108 109
109 /* 110 /*
110 * 9-4 = VTT GPIO PIN (6 Bits) 111 * 9-4 = VTT GPIO PIN (6 Bits)
111 * 3 = VTT Status (1 Bit) 112 * 3 = VTT Status (1 Bit)
112 * 2-0 = Memory Type (3 Bits) 113 * 2-0 = Memory Type (3 Bits)
113 */ 114 */
114 #define MEM_TYPE_SHIFT (0x0) 115 #define MEM_TYPE_SHIFT (0x0)
115 #define MEM_TYPE_MASK (0x7 << 0) 116 #define MEM_TYPE_MASK (0x7 << 0)
116 #define VTT_STAT_SHIFT (0x3) 117 #define VTT_STAT_SHIFT (0x3)
117 #define VTT_STAT_MASK (0x1 << 3) 118 #define VTT_STAT_MASK (0x1 << 3)
118 #define VTT_GPIO_PIN_SHIFT (0x4) 119 #define VTT_GPIO_PIN_SHIFT (0x4)
119 #define VTT_GPIO_PIN_MASK (0x3f << 4) 120 #define VTT_GPIO_PIN_MASK (0x3f << 4)
120 #define IO_ISOLATION_STAT_SHIFT (10) 121 #define IO_ISOLATION_STAT_SHIFT (10)
121 #define IO_ISOLATION_STAT_MASK (0x1 << 10) 122 #define IO_ISOLATION_STAT_MASK (0x1 << 10)
122 123
123 #define MPU_WAKE 0x800 124 #define MPU_WAKE 0x800
124 125
125 #define MEM_BANK_RET_ST_OFF 0x0 126 #define MEM_BANK_RET_ST_OFF 0x0
126 #define MEM_BANK_RET_ST_RET 0x1 127 #define MEM_BANK_RET_ST_RET 0x1
127 128
128 #define M3_PARAM2_MPU_STATE_SHIFT 0 129 #define M3_PARAM2_MPU_STATE_SHIFT 0
129 #define M3_PARAM2_MPU_RAM_RET_SHIFT 2 130 #define M3_PARAM2_MPU_RAM_RET_SHIFT 2
130 #define M3_PARAM2_MPU_L1_RET_SHIFT 3 131 #define M3_PARAM2_MPU_L1_RET_SHIFT 3
131 #define M3_PARAM2_MPU_L2_RET_SHIFT 4 132 #define M3_PARAM2_MPU_L2_RET_SHIFT 4
132 #define M3_PARAM2_PER_STATE_SHIFT 7 133 #define M3_PARAM2_PER_STATE_SHIFT 7
133 #define M3_PARAM2_WAKE_SOURCES_SHIFT 18 134 #define M3_PARAM2_WAKE_SOURCES_SHIFT 18
134 135
135 #endif /* __ARCH_ARM_MACH_OMAP2_PM33XX_H */ 136 #endif /* __ARCH_ARM_MACH_OMAP2_PM33XX_H */
136 137
drivers/mailbox/omap-mailbox.c
Diff comments   View file @ 14ed5c8
1 /* 1 /*
2 * OMAP mailbox driver 2 * OMAP mailbox driver
3 * 3 *
4 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. 4 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
5 * Copyright (C) 2013-2014 Texas Instruments Inc. 5 * Copyright (C) 2013-2014 Texas Instruments Inc.
6 * 6 *
7 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> 7 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * Suman Anna <s-anna@ti.com> 8 * Suman Anna <s-anna@ti.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License 11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation. 12 * version 2 as published by the Free Software Foundation.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, but 14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details. 17 * General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA 22 * 02110-1301 USA
23 * 23 *
24 */ 24 */
25 25
26 #include <linux/interrupt.h> 26 #include <linux/interrupt.h>
27 #include <linux/spinlock.h> 27 #include <linux/spinlock.h>
28 #include <linux/mutex.h> 28 #include <linux/mutex.h>
29 #include <linux/slab.h> 29 #include <linux/slab.h>
30 #include <linux/kfifo.h> 30 #include <linux/kfifo.h>
31 #include <linux/err.h> 31 #include <linux/err.h>
32 #include <linux/module.h> 32 #include <linux/module.h>
33 #include <linux/of_device.h> 33 #include <linux/of_device.h>
34 #include <linux/platform_device.h> 34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h> 35 #include <linux/pm_runtime.h>
36 #include <linux/platform_data/mailbox-omap.h> 36 #include <linux/platform_data/mailbox-omap.h>
37 #include <linux/omap-mailbox.h> 37 #include <linux/omap-mailbox.h>
38 #include <linux/mailbox_controller.h> 38 #include <linux/mailbox_controller.h>
39 #include <linux/mailbox_client.h> 39 #include <linux/mailbox_client.h>
40 40
41 #define MAILBOX_REVISION 0x000 41 #define MAILBOX_REVISION 0x000
42 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) 42 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
43 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) 43 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
44 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) 44 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
45 45
46 #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) 46 #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
47 #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) 47 #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
48 48
49 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) 49 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
50 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) 50 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
51 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) 51 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
52 52
53 #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ 53 #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
54 OMAP2_MAILBOX_IRQSTATUS(u)) 54 OMAP2_MAILBOX_IRQSTATUS(u))
55 #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ 55 #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
56 OMAP2_MAILBOX_IRQENABLE(u)) 56 OMAP2_MAILBOX_IRQENABLE(u))
57 #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ 57 #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
58 : OMAP2_MAILBOX_IRQENABLE(u)) 58 : OMAP2_MAILBOX_IRQENABLE(u))
59 59
60 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) 60 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
61 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) 61 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
62 62
63 #define MBOX_REG_SIZE 0x120 63 #define MBOX_REG_SIZE 0x120
64 64
65 #define OMAP4_MBOX_REG_SIZE 0x130 65 #define OMAP4_MBOX_REG_SIZE 0x130
66 66
67 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32)) 67 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
68 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32)) 68 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
69 69
70 /*
71 * We need this for special case handling where controller indicates done
72 * state with IRQ but a specific channel needs to use manually ACK (used
73 * by wkup_m3 on AM33xx/AM43xx).
74 */
75 #define MBOX_TXDONE_BY_ACK (1 << 2)
76
70 struct omap_mbox_fifo { 77 struct omap_mbox_fifo {
71 unsigned long msg; 78 unsigned long msg;
72 unsigned long fifo_stat; 79 unsigned long fifo_stat;
73 unsigned long msg_stat; 80 unsigned long msg_stat;
74 unsigned long irqenable; 81 unsigned long irqenable;
75 unsigned long irqstatus; 82 unsigned long irqstatus;
76 unsigned long irqdisable; 83 unsigned long irqdisable;
77 u32 intr_bit; 84 u32 intr_bit;
78 }; 85 };
79 86
80 struct omap_mbox_queue { 87 struct omap_mbox_queue {
81 spinlock_t lock; 88 spinlock_t lock;
82 struct kfifo fifo; 89 struct kfifo fifo;
83 struct work_struct work; 90 struct work_struct work;
84 struct omap_mbox *mbox; 91 struct omap_mbox *mbox;
85 bool full; 92 bool full;
86 }; 93 };
87 94
88 struct omap_mbox_device { 95 struct omap_mbox_device {
89 struct device *dev; 96 struct device *dev;
90 struct mutex cfg_lock; 97 struct mutex cfg_lock;
91 void __iomem *mbox_base; 98 void __iomem *mbox_base;
92 u32 num_users; 99 u32 num_users;
93 u32 num_fifos; 100 u32 num_fifos;
94 struct omap_mbox **mboxes; 101 struct omap_mbox **mboxes;
95 struct mbox_controller controller; 102 struct mbox_controller controller;
96 struct list_head elem; 103 struct list_head elem;
97 }; 104 };
98 105
99 struct omap_mbox_fifo_info { 106 struct omap_mbox_fifo_info {
100 int tx_id; 107 int tx_id;
101 int tx_usr; 108 int tx_usr;
102 int tx_irq; 109 int tx_irq;
103 110
104 int rx_id; 111 int rx_id;
105 int rx_usr; 112 int rx_usr;
106 int rx_irq; 113 int rx_irq;
107 114
108 const char *name; 115 const char *name;
116 bool send_no_irq;
109 }; 117 };
110 118
111 struct omap_mbox { 119 struct omap_mbox {
112 const char *name; 120 const char *name;
113 int irq; 121 int irq;
114 struct omap_mbox_queue *rxq; 122 struct omap_mbox_queue *rxq;
115 struct device *dev; 123 struct device *dev;
116 struct omap_mbox_device *parent; 124 struct omap_mbox_device *parent;
117 struct omap_mbox_fifo tx_fifo; 125 struct omap_mbox_fifo tx_fifo;
118 struct omap_mbox_fifo rx_fifo; 126 struct omap_mbox_fifo rx_fifo;
119 u32 ctx[OMAP4_MBOX_NR_REGS]; 127 u32 ctx[OMAP4_MBOX_NR_REGS];
120 u32 intr_type; 128 u32 intr_type;
121 struct mbox_chan *chan; 129 struct mbox_chan *chan;
130 bool send_no_irq;
122 }; 131 };
123 132
124 /* global variables for the mailbox devices */ 133 /* global variables for the mailbox devices */
125 static DEFINE_MUTEX(omap_mbox_devices_lock); 134 static DEFINE_MUTEX(omap_mbox_devices_lock);
126 static LIST_HEAD(omap_mbox_devices); 135 static LIST_HEAD(omap_mbox_devices);
127 136
128 static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; 137 static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
129 module_param(mbox_kfifo_size, uint, S_IRUGO); 138 module_param(mbox_kfifo_size, uint, S_IRUGO);
130 MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); 139 MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
131 140
132 static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan) 141 static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
133 { 142 {
134 if (!chan || !chan->con_priv) 143 if (!chan || !chan->con_priv)
135 return NULL; 144 return NULL;
136 145
137 return (struct omap_mbox *)chan->con_priv; 146 return (struct omap_mbox *)chan->con_priv;
138 } 147 }
139 148
140 static inline 149 static inline
141 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) 150 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
142 { 151 {
143 return __raw_readl(mdev->mbox_base + ofs); 152 return __raw_readl(mdev->mbox_base + ofs);
144 } 153 }
145 154
146 static inline 155 static inline
147 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) 156 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
148 { 157 {
149 __raw_writel(val, mdev->mbox_base + ofs); 158 __raw_writel(val, mdev->mbox_base + ofs);
150 } 159 }
151 160
152 /* Mailbox FIFO handle functions */ 161 /* Mailbox FIFO handle functions */
153 static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) 162 static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
154 { 163 {
155 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; 164 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
156 return (mbox_msg_t) mbox_read_reg(mbox->parent, fifo->msg); 165 return (mbox_msg_t) mbox_read_reg(mbox->parent, fifo->msg);
157 } 166 }
158 167
159 static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 168 static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
160 { 169 {
161 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; 170 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
162 mbox_write_reg(mbox->parent, msg, fifo->msg); 171 mbox_write_reg(mbox->parent, msg, fifo->msg);
163 } 172 }
164 173
165 static int mbox_fifo_empty(struct omap_mbox *mbox) 174 static int mbox_fifo_empty(struct omap_mbox *mbox)
166 { 175 {
167 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; 176 struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
168 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); 177 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
169 } 178 }
170 179
171 static int mbox_fifo_full(struct omap_mbox *mbox) 180 static int mbox_fifo_full(struct omap_mbox *mbox)
172 { 181 {
173 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; 182 struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
174 return mbox_read_reg(mbox->parent, fifo->fifo_stat); 183 return mbox_read_reg(mbox->parent, fifo->fifo_stat);
175 } 184 }
176 185
177 /* Mailbox IRQ handle functions */ 186 /* Mailbox IRQ handle functions */
178 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 187 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
179 { 188 {
180 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 189 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
181 &mbox->tx_fifo : &mbox->rx_fifo; 190 &mbox->tx_fifo : &mbox->rx_fifo;
182 u32 bit = fifo->intr_bit; 191 u32 bit = fifo->intr_bit;
183 u32 irqstatus = fifo->irqstatus; 192 u32 irqstatus = fifo->irqstatus;
184 193
185 mbox_write_reg(mbox->parent, bit, irqstatus); 194 mbox_write_reg(mbox->parent, bit, irqstatus);
186 195
187 /* Flush posted write for irq status to avoid spurious interrupts */ 196 /* Flush posted write for irq status to avoid spurious interrupts */
188 mbox_read_reg(mbox->parent, irqstatus); 197 mbox_read_reg(mbox->parent, irqstatus);
189 } 198 }
190 199
191 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 200 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
192 { 201 {
193 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 202 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
194 &mbox->tx_fifo : &mbox->rx_fifo; 203 &mbox->tx_fifo : &mbox->rx_fifo;
195 u32 bit = fifo->intr_bit; 204 u32 bit = fifo->intr_bit;
196 u32 irqenable = fifo->irqenable; 205 u32 irqenable = fifo->irqenable;
197 u32 irqstatus = fifo->irqstatus; 206 u32 irqstatus = fifo->irqstatus;
198 207
199 u32 enable = mbox_read_reg(mbox->parent, irqenable); 208 u32 enable = mbox_read_reg(mbox->parent, irqenable);
200 u32 status = mbox_read_reg(mbox->parent, irqstatus); 209 u32 status = mbox_read_reg(mbox->parent, irqstatus);
201 210
202 return (int)(enable & status & bit); 211 return (int)(enable & status & bit);
203 } 212 }
204 213
205 void omap_mbox_save_ctx(struct mbox_chan *chan) 214 void omap_mbox_save_ctx(struct mbox_chan *chan)
206 { 215 {
207 int i; 216 int i;
208 int nr_regs; 217 int nr_regs;
209 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 218 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
210 219
211 if (WARN_ON(!mbox)) 220 if (WARN_ON(!mbox))
212 return; 221 return;
213 222
214 if (mbox->intr_type) 223 if (mbox->intr_type)
215 nr_regs = OMAP4_MBOX_NR_REGS; 224 nr_regs = OMAP4_MBOX_NR_REGS;
216 else 225 else
217 nr_regs = MBOX_NR_REGS; 226 nr_regs = MBOX_NR_REGS;
218 for (i = 0; i < nr_regs; i++) { 227 for (i = 0; i < nr_regs; i++) {
219 mbox->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32)); 228 mbox->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32));
220 229
221 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, 230 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
222 i, mbox->ctx[i]); 231 i, mbox->ctx[i]);
223 } 232 }
224 } 233 }
225 EXPORT_SYMBOL(omap_mbox_save_ctx); 234 EXPORT_SYMBOL(omap_mbox_save_ctx);
226 235
227 void omap_mbox_restore_ctx(struct mbox_chan *chan) 236 void omap_mbox_restore_ctx(struct mbox_chan *chan)
228 { 237 {
229 int i; 238 int i;
230 int nr_regs; 239 int nr_regs;
231 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 240 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
232 241
233 if (WARN_ON(!mbox)) 242 if (WARN_ON(!mbox))
234 return; 243 return;
235 244
236 if (mbox->intr_type) 245 if (mbox->intr_type)
237 nr_regs = OMAP4_MBOX_NR_REGS; 246 nr_regs = OMAP4_MBOX_NR_REGS;
238 else 247 else
239 nr_regs = MBOX_NR_REGS; 248 nr_regs = MBOX_NR_REGS;
240 for (i = 0; i < nr_regs; i++) { 249 for (i = 0; i < nr_regs; i++) {
241 mbox_write_reg(mbox->parent, mbox->ctx[i], i * sizeof(u32)); 250 mbox_write_reg(mbox->parent, mbox->ctx[i], i * sizeof(u32));
242 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, 251 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
243 i, mbox->ctx[i]); 252 i, mbox->ctx[i]);
244 } 253 }
245 } 254 }
246 EXPORT_SYMBOL(omap_mbox_restore_ctx); 255 EXPORT_SYMBOL(omap_mbox_restore_ctx);
247 256
248 static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 257 static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
249 { 258 {
250 u32 l; 259 u32 l;
251 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 260 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
252 &mbox->tx_fifo : &mbox->rx_fifo; 261 &mbox->tx_fifo : &mbox->rx_fifo;
253 u32 bit = fifo->intr_bit; 262 u32 bit = fifo->intr_bit;
254 u32 irqenable = fifo->irqenable; 263 u32 irqenable = fifo->irqenable;
255 264
256 l = mbox_read_reg(mbox->parent, irqenable); 265 l = mbox_read_reg(mbox->parent, irqenable);
257 l |= bit; 266 l |= bit;
258 mbox_write_reg(mbox->parent, l, irqenable); 267 mbox_write_reg(mbox->parent, l, irqenable);
259 } 268 }
260 269
261 static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) 270 static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
262 { 271 {
263 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? 272 struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
264 &mbox->tx_fifo : &mbox->rx_fifo; 273 &mbox->tx_fifo : &mbox->rx_fifo;
265 u32 bit = fifo->intr_bit; 274 u32 bit = fifo->intr_bit;
266 u32 irqdisable = fifo->irqdisable; 275 u32 irqdisable = fifo->irqdisable;
267 276
268 /* 277 /*
269 * Read and update the interrupt configuration register for pre-OMAP4. 278 * Read and update the interrupt configuration register for pre-OMAP4.
270 * OMAP4 and later SoCs have a dedicated interrupt disabling register. 279 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
271 */ 280 */
272 if (!mbox->intr_type) 281 if (!mbox->intr_type)
273 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; 282 bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
274 283
275 mbox_write_reg(mbox->parent, bit, irqdisable); 284 mbox_write_reg(mbox->parent, bit, irqdisable);
276 } 285 }
277 286
278 void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) 287 void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
279 { 288 {
280 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 289 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
281 290
282 if (WARN_ON(!mbox)) 291 if (WARN_ON(!mbox))
283 return; 292 return;
284 293
285 _omap_mbox_enable_irq(mbox, irq); 294 _omap_mbox_enable_irq(mbox, irq);
286 } 295 }
287 EXPORT_SYMBOL(omap_mbox_enable_irq); 296 EXPORT_SYMBOL(omap_mbox_enable_irq);
288 297
289 void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) 298 void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
290 { 299 {
291 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 300 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
292 301
293 if (WARN_ON(!mbox)) 302 if (WARN_ON(!mbox))
294 return; 303 return;
295 304
296 _omap_mbox_disable_irq(mbox, irq); 305 _omap_mbox_disable_irq(mbox, irq);
297 } 306 }
298 EXPORT_SYMBOL(omap_mbox_disable_irq); 307 EXPORT_SYMBOL(omap_mbox_disable_irq);
299 308
300 /* 309 /*
301 * Message receiver(workqueue) 310 * Message receiver(workqueue)
302 */ 311 */
303 static void mbox_rx_work(struct work_struct *work) 312 static void mbox_rx_work(struct work_struct *work)
304 { 313 {
305 struct omap_mbox_queue *mq = 314 struct omap_mbox_queue *mq =
306 container_of(work, struct omap_mbox_queue, work); 315 container_of(work, struct omap_mbox_queue, work);
307 mbox_msg_t msg; 316 mbox_msg_t msg;
308 int len; 317 int len;
309 318
310 while (kfifo_len(&mq->fifo) >= sizeof(msg)) { 319 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
311 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); 320 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
312 WARN_ON(len != sizeof(msg)); 321 WARN_ON(len != sizeof(msg));
313 322
314 mbox_chan_received_data(mq->mbox->chan, (void *)msg); 323 mbox_chan_received_data(mq->mbox->chan, (void *)msg);
315 spin_lock_irq(&mq->lock); 324 spin_lock_irq(&mq->lock);
316 if (mq->full) { 325 if (mq->full) {
317 mq->full = false; 326 mq->full = false;
318 _omap_mbox_enable_irq(mq->mbox, IRQ_RX); 327 _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
319 } 328 }
320 spin_unlock_irq(&mq->lock); 329 spin_unlock_irq(&mq->lock);
321 } 330 }
322 } 331 }
323 332
324 /* 333 /*
325 * Mailbox interrupt handler 334 * Mailbox interrupt handler
326 */ 335 */
327 static void __mbox_tx_interrupt(struct omap_mbox *mbox) 336 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
328 { 337 {
329 _omap_mbox_disable_irq(mbox, IRQ_TX); 338 _omap_mbox_disable_irq(mbox, IRQ_TX);
330 ack_mbox_irq(mbox, IRQ_TX); 339 ack_mbox_irq(mbox, IRQ_TX);
331 mbox_chan_txdone(mbox->chan, 0); 340 mbox_chan_txdone(mbox->chan, 0);
332 } 341 }
333 342
334 static void __mbox_rx_interrupt(struct omap_mbox *mbox) 343 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
335 { 344 {
336 struct omap_mbox_queue *mq = mbox->rxq; 345 struct omap_mbox_queue *mq = mbox->rxq;
337 mbox_msg_t msg; 346 mbox_msg_t msg;
338 int len; 347 int len;
339 348
340 while (!mbox_fifo_empty(mbox)) { 349 while (!mbox_fifo_empty(mbox)) {
341 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { 350 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
342 _omap_mbox_disable_irq(mbox, IRQ_RX); 351 _omap_mbox_disable_irq(mbox, IRQ_RX);
343 mq->full = true; 352 mq->full = true;
344 goto nomem; 353 goto nomem;
345 } 354 }
346 355
347 msg = mbox_fifo_read(mbox); 356 msg = mbox_fifo_read(mbox);
348 357
349 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); 358 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
350 WARN_ON(len != sizeof(msg)); 359 WARN_ON(len != sizeof(msg));
351 } 360 }
352 361
353 /* no more messages in the fifo. clear IRQ source. */ 362 /* no more messages in the fifo. clear IRQ source. */
354 ack_mbox_irq(mbox, IRQ_RX); 363 ack_mbox_irq(mbox, IRQ_RX);
355 nomem: 364 nomem:
356 schedule_work(&mbox->rxq->work); 365 schedule_work(&mbox->rxq->work);
357 } 366 }
358 367
359 static irqreturn_t mbox_interrupt(int irq, void *p) 368 static irqreturn_t mbox_interrupt(int irq, void *p)
360 { 369 {
361 struct omap_mbox *mbox = p; 370 struct omap_mbox *mbox = p;
362 371
363 if (is_mbox_irq(mbox, IRQ_TX)) 372 if (is_mbox_irq(mbox, IRQ_TX))
364 __mbox_tx_interrupt(mbox); 373 __mbox_tx_interrupt(mbox);
365 374
366 if (is_mbox_irq(mbox, IRQ_RX)) 375 if (is_mbox_irq(mbox, IRQ_RX))
367 __mbox_rx_interrupt(mbox); 376 __mbox_rx_interrupt(mbox);
368 377
369 return IRQ_HANDLED; 378 return IRQ_HANDLED;
370 } 379 }
371 380
372 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, 381 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
373 void (*work)(struct work_struct *)) 382 void (*work)(struct work_struct *))
374 { 383 {
375 struct omap_mbox_queue *mq; 384 struct omap_mbox_queue *mq;
376 385
377 if (!work) 386 if (!work)
378 return NULL; 387 return NULL;
379 388
380 mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); 389 mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
381 if (!mq) 390 if (!mq)
382 return NULL; 391 return NULL;
383 392
384 spin_lock_init(&mq->lock); 393 spin_lock_init(&mq->lock);
385 394
386 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) 395 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
387 goto error; 396 goto error;
388 397
389 INIT_WORK(&mq->work, work); 398 INIT_WORK(&mq->work, work);
390 return mq; 399 return mq;
391 400
392 error: 401 error:
393 kfree(mq); 402 kfree(mq);
394 return NULL; 403 return NULL;
395 } 404 }
396 405
397 static void mbox_queue_free(struct omap_mbox_queue *q) 406 static void mbox_queue_free(struct omap_mbox_queue *q)
398 { 407 {
399 kfifo_free(&q->fifo); 408 kfifo_free(&q->fifo);
400 kfree(q); 409 kfree(q);
401 } 410 }
402 411
403 static int omap_mbox_startup(struct omap_mbox *mbox) 412 static int omap_mbox_startup(struct omap_mbox *mbox)
404 { 413 {
405 int ret = 0; 414 int ret = 0;
406 struct omap_mbox_queue *mq; 415 struct omap_mbox_queue *mq;
407 416
408 mq = mbox_queue_alloc(mbox, mbox_rx_work); 417 mq = mbox_queue_alloc(mbox, mbox_rx_work);
409 if (!mq) 418 if (!mq)
410 return -ENOMEM; 419 return -ENOMEM;
411 mbox->rxq = mq; 420 mbox->rxq = mq;
412 mq->mbox = mbox; 421 mq->mbox = mbox;
413 422
414 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, 423 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
415 mbox->name, mbox); 424 mbox->name, mbox);
416 if (unlikely(ret)) { 425 if (unlikely(ret)) {
417 pr_err("failed to register mailbox interrupt:%d\n", ret); 426 pr_err("failed to register mailbox interrupt:%d\n", ret);
418 goto fail_request_irq; 427 goto fail_request_irq;
419 } 428 }
420 429
430 if (mbox->send_no_irq)
431 mbox->chan->txdone_method = MBOX_TXDONE_BY_ACK;
432
421 _omap_mbox_enable_irq(mbox, IRQ_RX); 433 _omap_mbox_enable_irq(mbox, IRQ_RX);
422 434
423 return 0; 435 return 0;
424 436
425 fail_request_irq: 437 fail_request_irq:
426 mbox_queue_free(mbox->rxq); 438 mbox_queue_free(mbox->rxq);
427 return ret; 439 return ret;
428 } 440 }
429 441
430 static void omap_mbox_fini(struct omap_mbox *mbox) 442 static void omap_mbox_fini(struct omap_mbox *mbox)
431 { 443 {
432 _omap_mbox_disable_irq(mbox, IRQ_RX); 444 _omap_mbox_disable_irq(mbox, IRQ_RX);
433 free_irq(mbox->irq, mbox); 445 free_irq(mbox->irq, mbox);
434 flush_work(&mbox->rxq->work); 446 flush_work(&mbox->rxq->work);
435 mbox_queue_free(mbox->rxq); 447 mbox_queue_free(mbox->rxq);
436 } 448 }
437 449
438 static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev, 450 static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
439 const char *mbox_name) 451 const char *mbox_name)
440 { 452 {
441 struct omap_mbox *_mbox, *mbox = NULL; 453 struct omap_mbox *_mbox, *mbox = NULL;
442 struct omap_mbox **mboxes = mdev->mboxes; 454 struct omap_mbox **mboxes = mdev->mboxes;
443 int i; 455 int i;
444 456
445 if (!mboxes) 457 if (!mboxes)
446 return NULL; 458 return NULL;
447 459
448 for (i = 0; (_mbox = mboxes[i]); i++) { 460 for (i = 0; (_mbox = mboxes[i]); i++) {
449 if (!strcmp(_mbox->name, mbox_name)) { 461 if (!strcmp(_mbox->name, mbox_name)) {
450 mbox = _mbox; 462 mbox = _mbox;
451 break; 463 break;
452 } 464 }
453 } 465 }
454 return mbox; 466 return mbox;
455 } 467 }
456 468
457 struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl, 469 struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
458 const char *chan_name) 470 const char *chan_name)
459 { 471 {
460 struct device *dev = cl->dev; 472 struct device *dev = cl->dev;
461 struct omap_mbox *mbox = NULL; 473 struct omap_mbox *mbox = NULL;
462 struct omap_mbox_device *mdev; 474 struct omap_mbox_device *mdev;
463 struct mbox_chan *chan; 475 struct mbox_chan *chan;
464 unsigned long flags; 476 unsigned long flags;
465 int ret; 477 int ret;
466 478
467 if (!dev) 479 if (!dev)
468 return ERR_PTR(-ENODEV); 480 return ERR_PTR(-ENODEV);
469 481
470 if (dev->of_node) { 482 if (dev->of_node) {
471 pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n", 483 pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
472 __func__); 484 __func__);
473 return ERR_PTR(-ENODEV); 485 return ERR_PTR(-ENODEV);
474 } 486 }
475 487
476 mutex_lock(&omap_mbox_devices_lock); 488 mutex_lock(&omap_mbox_devices_lock);
477 list_for_each_entry(mdev, &omap_mbox_devices, elem) { 489 list_for_each_entry(mdev, &omap_mbox_devices, elem) {
478 mbox = omap_mbox_device_find(mdev, chan_name); 490 mbox = omap_mbox_device_find(mdev, chan_name);
479 if (mbox) 491 if (mbox)
480 break; 492 break;
481 } 493 }
482 mutex_unlock(&omap_mbox_devices_lock); 494 mutex_unlock(&omap_mbox_devices_lock);
483 495
484 if (!mbox || !mbox->chan) 496 if (!mbox || !mbox->chan)
485 return ERR_PTR(-ENOENT); 497 return ERR_PTR(-ENOENT);
486 498
487 chan = mbox->chan; 499 chan = mbox->chan;
488 spin_lock_irqsave(&chan->lock, flags); 500 spin_lock_irqsave(&chan->lock, flags);
489 chan->msg_free = 0; 501 chan->msg_free = 0;
490 chan->msg_count = 0; 502 chan->msg_count = 0;
491 chan->active_req = NULL; 503 chan->active_req = NULL;
492 chan->cl = cl; 504 chan->cl = cl;
493 init_completion(&chan->tx_complete); 505 init_completion(&chan->tx_complete);
494 spin_unlock_irqrestore(&chan->lock, flags); 506 spin_unlock_irqrestore(&chan->lock, flags);
495 507
496 ret = chan->mbox->ops->startup(chan); 508 ret = chan->mbox->ops->startup(chan);
497 if (ret) { 509 if (ret) {
498 pr_err("Unable to startup the chan (%d)\n", ret); 510 pr_err("Unable to startup the chan (%d)\n", ret);
499 mbox_free_channel(chan); 511 mbox_free_channel(chan);
500 chan = ERR_PTR(ret); 512 chan = ERR_PTR(ret);
501 } 513 }
502 514
503 return chan; 515 return chan;
504 } 516 }
505 EXPORT_SYMBOL(omap_mbox_request_channel); 517 EXPORT_SYMBOL(omap_mbox_request_channel);
506 518
507 static struct class omap_mbox_class = { .name = "mbox", }; 519 static struct class omap_mbox_class = { .name = "mbox", };
508 520
509 static int omap_mbox_register(struct omap_mbox_device *mdev) 521 static int omap_mbox_register(struct omap_mbox_device *mdev)
510 { 522 {
511 int ret; 523 int ret;
512 int i; 524 int i;
513 struct omap_mbox **mboxes; 525 struct omap_mbox **mboxes;
514 526
515 if (!mdev || !mdev->mboxes) 527 if (!mdev || !mdev->mboxes)
516 return -EINVAL; 528 return -EINVAL;
517 529
518 mboxes = mdev->mboxes; 530 mboxes = mdev->mboxes;
519 for (i = 0; mboxes[i]; i++) { 531 for (i = 0; mboxes[i]; i++) {
520 struct omap_mbox *mbox = mboxes[i]; 532 struct omap_mbox *mbox = mboxes[i];
521 mbox->dev = device_create(&omap_mbox_class, mdev->dev, 533 mbox->dev = device_create(&omap_mbox_class, mdev->dev,
522 0, mbox, "%s", mbox->name); 534 0, mbox, "%s", mbox->name);
523 if (IS_ERR(mbox->dev)) { 535 if (IS_ERR(mbox->dev)) {
524 ret = PTR_ERR(mbox->dev); 536 ret = PTR_ERR(mbox->dev);
525 goto err_out; 537 goto err_out;
526 } 538 }
527 } 539 }
528 540
529 mutex_lock(&omap_mbox_devices_lock); 541 mutex_lock(&omap_mbox_devices_lock);
530 list_add(&mdev->elem, &omap_mbox_devices); 542 list_add(&mdev->elem, &omap_mbox_devices);
531 mutex_unlock(&omap_mbox_devices_lock); 543 mutex_unlock(&omap_mbox_devices_lock);
532 544
533 ret = mbox_controller_register(&mdev->controller); 545 ret = mbox_controller_register(&mdev->controller);
534 546
535 err_out: 547 err_out:
536 if (ret) { 548 if (ret) {
537 while (i--) 549 while (i--)
538 device_unregister(mboxes[i]->dev); 550 device_unregister(mboxes[i]->dev);
539 } 551 }
540 return ret; 552 return ret;
541 } 553 }
542 554
543 static int omap_mbox_unregister(struct omap_mbox_device *mdev) 555 static int omap_mbox_unregister(struct omap_mbox_device *mdev)
544 { 556 {
545 int i; 557 int i;
546 struct omap_mbox **mboxes; 558 struct omap_mbox **mboxes;
547 559
548 if (!mdev || !mdev->mboxes) 560 if (!mdev || !mdev->mboxes)
549 return -EINVAL; 561 return -EINVAL;
550 562
551 mutex_lock(&omap_mbox_devices_lock); 563 mutex_lock(&omap_mbox_devices_lock);
552 list_del(&mdev->elem); 564 list_del(&mdev->elem);
553 mutex_unlock(&omap_mbox_devices_lock); 565 mutex_unlock(&omap_mbox_devices_lock);
554 566
555 mbox_controller_unregister(&mdev->controller); 567 mbox_controller_unregister(&mdev->controller);
556 568
557 mboxes = mdev->mboxes; 569 mboxes = mdev->mboxes;
558 for (i = 0; mboxes[i]; i++) 570 for (i = 0; mboxes[i]; i++)
559 device_unregister(mboxes[i]->dev); 571 device_unregister(mboxes[i]->dev);
560 return 0; 572 return 0;
561 } 573 }
562 574
563 static int omap_mbox_chan_startup(struct mbox_chan *chan) 575 static int omap_mbox_chan_startup(struct mbox_chan *chan)
564 { 576 {
565 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 577 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
566 struct omap_mbox_device *mdev = mbox->parent; 578 struct omap_mbox_device *mdev = mbox->parent;
567 int ret = 0; 579 int ret = 0;
568 580
569 mutex_lock(&mdev->cfg_lock); 581 mutex_lock(&mdev->cfg_lock);
570 pm_runtime_get_sync(mdev->dev); 582 pm_runtime_get_sync(mdev->dev);
571 ret = omap_mbox_startup(mbox); 583 ret = omap_mbox_startup(mbox);
572 if (ret) 584 if (ret)
573 pm_runtime_put_sync(mdev->dev); 585 pm_runtime_put_sync(mdev->dev);
574 mutex_unlock(&mdev->cfg_lock); 586 mutex_unlock(&mdev->cfg_lock);
575 return ret; 587 return ret;
576 } 588 }
577 589
578 static void omap_mbox_chan_shutdown(struct mbox_chan *chan) 590 static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
579 { 591 {
580 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); 592 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
581 struct omap_mbox_device *mdev = mbox->parent; 593 struct omap_mbox_device *mdev = mbox->parent;
582 594
583 mutex_lock(&mdev->cfg_lock); 595 mutex_lock(&mdev->cfg_lock);
584 omap_mbox_fini(mbox); 596 omap_mbox_fini(mbox);
585 pm_runtime_put_sync(mdev->dev); 597 pm_runtime_put_sync(mdev->dev);
586 mutex_unlock(&mdev->cfg_lock); 598 mutex_unlock(&mdev->cfg_lock);
587 } 599 }
588 600
589 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) 601 static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
590 { 602 {
591 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
592 int ret = -EBUSY; 603 int ret = -EBUSY;
593 604
594 if (!mbox) 605 if (!mbox_fifo_full(mbox)) {
595 return -EINVAL; 606 _omap_mbox_enable_irq(mbox, IRQ_RX);
607 mbox_fifo_write(mbox, (mbox_msg_t)data);
608 ret = 0;
609 _omap_mbox_disable_irq(mbox, IRQ_RX);
596 610
611 /* we must read and ack the interrupt directly from here */
612 mbox_fifo_read(mbox);
613 ack_mbox_irq(mbox, IRQ_RX);
614 }
615
616 return ret;
617 }
618
619 static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
620 {
621 int ret = -EBUSY;
622
597 if (!mbox_fifo_full(mbox)) { 623 if (!mbox_fifo_full(mbox)) {
598 mbox_fifo_write(mbox, (mbox_msg_t)data); 624 mbox_fifo_write(mbox, (mbox_msg_t)data);
599 ret = 0; 625 ret = 0;
600 } 626 }
601 627
602 /* always enable the interrupt */ 628 /* always enable the interrupt */
603 _omap_mbox_enable_irq(mbox, IRQ_TX); 629 _omap_mbox_enable_irq(mbox, IRQ_TX);
604 return ret; 630 return ret;
605 } 631 }
606 632
633 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
634 {
635 struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
636 int ret;
637
638 if (!mbox)
639 return -EINVAL;
640
641 if (mbox->send_no_irq)
642 ret = omap_mbox_chan_send_noirq(mbox, data);
643 else
644 ret = omap_mbox_chan_send(mbox, data);
645
646 return ret;
647 }
648
607 static struct mbox_chan_ops omap_mbox_chan_ops = { 649 static struct mbox_chan_ops omap_mbox_chan_ops = {
608 .startup = omap_mbox_chan_startup, 650 .startup = omap_mbox_chan_startup,
609 .send_data = omap_mbox_chan_send_data, 651 .send_data = omap_mbox_chan_send_data,
610 .shutdown = omap_mbox_chan_shutdown, 652 .shutdown = omap_mbox_chan_shutdown,
611 }; 653 };
612 654
613 static const struct of_device_id omap_mailbox_of_match[] = { 655 static const struct of_device_id omap_mailbox_of_match[] = {
614 { 656 {
615 .compatible = "ti,omap2-mailbox", 657 .compatible = "ti,omap2-mailbox",
616 .data = (void *)MBOX_INTR_CFG_TYPE1, 658 .data = (void *)MBOX_INTR_CFG_TYPE1,
617 }, 659 },
618 { 660 {
619 .compatible = "ti,omap3-mailbox", 661 .compatible = "ti,omap3-mailbox",
620 .data = (void *)MBOX_INTR_CFG_TYPE1, 662 .data = (void *)MBOX_INTR_CFG_TYPE1,
621 }, 663 },
622 { 664 {
623 .compatible = "ti,omap4-mailbox", 665 .compatible = "ti,omap4-mailbox",
624 .data = (void *)MBOX_INTR_CFG_TYPE2, 666 .data = (void *)MBOX_INTR_CFG_TYPE2,
625 }, 667 },
626 { 668 {
627 /* end */ 669 /* end */
628 }, 670 },
629 }; 671 };
630 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); 672 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
631 673
632 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, 674 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
633 const struct of_phandle_args *sp) 675 const struct of_phandle_args *sp)
634 { 676 {
635 phandle phandle = sp->args[0]; 677 phandle phandle = sp->args[0];
636 struct device_node *node; 678 struct device_node *node;
637 struct omap_mbox_device *mdev; 679 struct omap_mbox_device *mdev;
638 struct omap_mbox *mbox; 680 struct omap_mbox *mbox;
639 681
640 mdev = container_of(controller, struct omap_mbox_device, controller); 682 mdev = container_of(controller, struct omap_mbox_device, controller);
641 if (WARN_ON(!mdev)) 683 if (WARN_ON(!mdev))
642 return NULL; 684 return NULL;
643 685
644 node = of_find_node_by_phandle(phandle); 686 node = of_find_node_by_phandle(phandle);
645 if (!node) { 687 if (!node) {
646 pr_err("%s: could not find node phandle 0x%x\n", 688 pr_err("%s: could not find node phandle 0x%x\n",
647 __func__, phandle); 689 __func__, phandle);
648 return NULL; 690 return NULL;
649 } 691 }
650 692
651 mbox = omap_mbox_device_find(mdev, node->name); 693 mbox = omap_mbox_device_find(mdev, node->name);
652 of_node_put(node); 694 of_node_put(node);
653 return mbox ? mbox->chan : NULL; 695 return mbox ? mbox->chan : NULL;
654 } 696 }
655 697
656 static int omap_mbox_probe(struct platform_device *pdev) 698 static int omap_mbox_probe(struct platform_device *pdev)
657 { 699 {
658 struct resource *mem; 700 struct resource *mem;
659 int ret; 701 int ret;
660 struct mbox_chan *chnls; 702 struct mbox_chan *chnls;
661 struct omap_mbox **list, *mbox, *mboxblk; 703 struct omap_mbox **list, *mbox, *mboxblk;
662 struct omap_mbox_pdata *pdata = pdev->dev.platform_data; 704 struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
663 struct omap_mbox_dev_info *info = NULL; 705 struct omap_mbox_dev_info *info = NULL;
664 struct omap_mbox_fifo_info *finfo, *finfoblk; 706 struct omap_mbox_fifo_info *finfo, *finfoblk;
665 struct omap_mbox_device *mdev; 707 struct omap_mbox_device *mdev;
666 struct omap_mbox_fifo *fifo; 708 struct omap_mbox_fifo *fifo;
667 struct device_node *node = pdev->dev.of_node; 709 struct device_node *node = pdev->dev.of_node;
668 struct device_node *child; 710 struct device_node *child;
669 const struct of_device_id *match; 711 const struct of_device_id *match;
670 u32 intr_type, info_count; 712 u32 intr_type, info_count;
671 u32 num_users, num_fifos; 713 u32 num_users, num_fifos;
672 u32 tmp[3]; 714 u32 tmp[3];
673 u32 l; 715 u32 l;
674 int i; 716 int i;
675 717
676 if (!node && (!pdata || !pdata->info_cnt || !pdata->info)) { 718 if (!node && (!pdata || !pdata->info_cnt || !pdata->info)) {
677 pr_err("%s: platform not supported\n", __func__); 719 pr_err("%s: platform not supported\n", __func__);
678 return -ENODEV; 720 return -ENODEV;
679 } 721 }
680 722
681 if (node) { 723 if (node) {
682 match = of_match_device(omap_mailbox_of_match, &pdev->dev); 724 match = of_match_device(omap_mailbox_of_match, &pdev->dev);
683 if (!match) 725 if (!match)
684 return -ENODEV; 726 return -ENODEV;
685 intr_type = (u32)match->data; 727 intr_type = (u32)match->data;
686 728
687 if (of_property_read_u32(node, "ti,mbox-num-users", 729 if (of_property_read_u32(node, "ti,mbox-num-users",
688 &num_users)) 730 &num_users))
689 return -ENODEV; 731 return -ENODEV;
690 732
691 if (of_property_read_u32(node, "ti,mbox-num-fifos", 733 if (of_property_read_u32(node, "ti,mbox-num-fifos",
692 &num_fifos)) 734 &num_fifos))
693 return -ENODEV; 735 return -ENODEV;
694 736
695 info_count = of_get_available_child_count(node); 737 info_count = of_get_available_child_count(node);
696 if (!info_count) { 738 if (!info_count) {
697 dev_err(&pdev->dev, "no available mbox devices found\n"); 739 dev_err(&pdev->dev, "no available mbox devices found\n");
698 return -ENODEV; 740 return -ENODEV;
699 } 741 }
700 } else { /* non-DT device creation */ 742 } else { /* non-DT device creation */
701 info_count = pdata->info_cnt; 743 info_count = pdata->info_cnt;
702 info = pdata->info; 744 info = pdata->info;
703 intr_type = pdata->intr_type; 745 intr_type = pdata->intr_type;
704 num_users = pdata->num_users; 746 num_users = pdata->num_users;
705 num_fifos = pdata->num_fifos; 747 num_fifos = pdata->num_fifos;
706 } 748 }
707 749
708 finfoblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*finfoblk), 750 finfoblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*finfoblk),
709 GFP_KERNEL); 751 GFP_KERNEL);
710 if (!finfoblk) 752 if (!finfoblk)
711 return -ENOMEM; 753 return -ENOMEM;
712 754
713 finfo = finfoblk; 755 finfo = finfoblk;
714 child = NULL; 756 child = NULL;
715 for (i = 0; i < info_count; i++, finfo++) { 757 for (i = 0; i < info_count; i++, finfo++) {
716 if (node) { 758 if (node) {
717 child = of_get_next_available_child(node, child); 759 child = of_get_next_available_child(node, child);
718 ret = of_property_read_u32_array(child, "ti,mbox-tx", 760 ret = of_property_read_u32_array(child, "ti,mbox-tx",
719 tmp, ARRAY_SIZE(tmp)); 761 tmp, ARRAY_SIZE(tmp));
720 if (ret) 762 if (ret)
721 return ret; 763 return ret;
722 finfo->tx_id = tmp[0]; 764 finfo->tx_id = tmp[0];
723 finfo->tx_irq = tmp[1]; 765 finfo->tx_irq = tmp[1];
724 finfo->tx_usr = tmp[2]; 766 finfo->tx_usr = tmp[2];
725 767
726 ret = of_property_read_u32_array(child, "ti,mbox-rx", 768 ret = of_property_read_u32_array(child, "ti,mbox-rx",
727 tmp, ARRAY_SIZE(tmp)); 769 tmp, ARRAY_SIZE(tmp));
728 if (ret) 770 if (ret)
729 return ret; 771 return ret;
730 finfo->rx_id = tmp[0]; 772 finfo->rx_id = tmp[0];
731 finfo->rx_irq = tmp[1]; 773 finfo->rx_irq = tmp[1];
732 finfo->rx_usr = tmp[2]; 774 finfo->rx_usr = tmp[2];
733 775
734 finfo->name = child->name; 776 finfo->name = child->name;
777
778 if (of_find_property(child, "ti,mbox-send-noirq", NULL))
779 finfo->send_no_irq = true;
735 } else { 780 } else {
736 finfo->tx_id = info->tx_id; 781 finfo->tx_id = info->tx_id;
737 finfo->rx_id = info->rx_id; 782 finfo->rx_id = info->rx_id;
738 finfo->tx_usr = info->usr_id; 783 finfo->tx_usr = info->usr_id;
739 finfo->tx_irq = info->irq_id; 784 finfo->tx_irq = info->irq_id;
740 finfo->rx_usr = info->usr_id; 785 finfo->rx_usr = info->usr_id;
741 finfo->rx_irq = info->irq_id; 786 finfo->rx_irq = info->irq_id;
742 finfo->name = info->name; 787 finfo->name = info->name;
743 info++; 788 info++;
744 } 789 }
745 if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos || 790 if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
746 finfo->tx_usr >= num_users || finfo->rx_usr >= num_users) 791 finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
747 return -EINVAL; 792 return -EINVAL;
748 } 793 }
749 794
750 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); 795 mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
751 if (!mdev) 796 if (!mdev)
752 return -ENOMEM; 797 return -ENOMEM;
753 798
754 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 799 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem); 800 mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
756 if (IS_ERR(mdev->mbox_base)) 801 if (IS_ERR(mdev->mbox_base))
757 return PTR_ERR(mdev->mbox_base); 802 return PTR_ERR(mdev->mbox_base);
758 803
759 /* allocate one extra for marking end of list */ 804 /* allocate one extra for marking end of list */
760 list = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*list), 805 list = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*list),
761 GFP_KERNEL); 806 GFP_KERNEL);
762 if (!list) 807 if (!list)
763 return -ENOMEM; 808 return -ENOMEM;
764 809
765 chnls = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*chnls), 810 chnls = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*chnls),
766 GFP_KERNEL); 811 GFP_KERNEL);
767 if (!chnls) 812 if (!chnls)
768 return -ENOMEM; 813 return -ENOMEM;
769 814
770 mboxblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*mbox), 815 mboxblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*mbox),
771 GFP_KERNEL); 816 GFP_KERNEL);
772 if (!mboxblk) 817 if (!mboxblk)
773 return -ENOMEM; 818 return -ENOMEM;
774 819
775 mbox = mboxblk; 820 mbox = mboxblk;
776 finfo = finfoblk; 821 finfo = finfoblk;
777 for (i = 0; i < info_count; i++, finfo++) { 822 for (i = 0; i < info_count; i++, finfo++) {
778 fifo = &mbox->tx_fifo; 823 fifo = &mbox->tx_fifo;
779 fifo->msg = MAILBOX_MESSAGE(finfo->tx_id); 824 fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
780 fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id); 825 fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
781 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id); 826 fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
782 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr); 827 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
783 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr); 828 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
784 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr); 829 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
785 830
786 fifo = &mbox->rx_fifo; 831 fifo = &mbox->rx_fifo;
787 fifo->msg = MAILBOX_MESSAGE(finfo->rx_id); 832 fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
788 fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id); 833 fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
789 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id); 834 fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
790 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr); 835 fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
791 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr); 836 fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
792 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr); 837 fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
793 838
839 mbox->send_no_irq = finfo->send_no_irq;
794 mbox->intr_type = intr_type; 840 mbox->intr_type = intr_type;
795 841
796 mbox->parent = mdev; 842 mbox->parent = mdev;
797 mbox->name = finfo->name; 843 mbox->name = finfo->name;
798 mbox->irq = platform_get_irq(pdev, finfo->tx_irq); 844 mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
799 if (mbox->irq < 0) 845 if (mbox->irq < 0)
800 return mbox->irq; 846 return mbox->irq;
801 mbox->chan = &chnls[i]; 847 mbox->chan = &chnls[i];
802 chnls[i].con_priv = mbox; 848 chnls[i].con_priv = mbox;
803 list[i] = mbox++; 849 list[i] = mbox++;
804 } 850 }
805 851
806 mutex_init(&mdev->cfg_lock); 852 mutex_init(&mdev->cfg_lock);
807 mdev->dev = &pdev->dev; 853 mdev->dev = &pdev->dev;
808 mdev->num_users = num_users; 854 mdev->num_users = num_users;
809 mdev->num_fifos = num_fifos; 855 mdev->num_fifos = num_fifos;
810 mdev->mboxes = list; 856 mdev->mboxes = list;
811 857
812 /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */ 858 /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
813 mdev->controller.txdone_irq = true; 859 mdev->controller.txdone_irq = true;
814 mdev->controller.dev = mdev->dev; 860 mdev->controller.dev = mdev->dev;
815 mdev->controller.ops = &omap_mbox_chan_ops; 861 mdev->controller.ops = &omap_mbox_chan_ops;
816 mdev->controller.chans = chnls; 862 mdev->controller.chans = chnls;
817 mdev->controller.num_chans = info_count; 863 mdev->controller.num_chans = info_count;
818 mdev->controller.of_xlate = omap_mbox_of_xlate; 864 mdev->controller.of_xlate = omap_mbox_of_xlate;
819 ret = omap_mbox_register(mdev); 865 ret = omap_mbox_register(mdev);
820 if (ret) 866 if (ret)
821 return ret; 867 return ret;
822 868
823 platform_set_drvdata(pdev, mdev); 869 platform_set_drvdata(pdev, mdev);
824 pm_runtime_enable(mdev->dev); 870 pm_runtime_enable(mdev->dev);
825 871
826 ret = pm_runtime_get_sync(mdev->dev); 872 ret = pm_runtime_get_sync(mdev->dev);
827 if (ret < 0) { 873 if (ret < 0) {
828 pm_runtime_put_noidle(mdev->dev); 874 pm_runtime_put_noidle(mdev->dev);
829 goto unregister; 875 goto unregister;
830 } 876 }
831 877
832 /* 878 /*
833 * just print the raw revision register, the format is not 879 * just print the raw revision register, the format is not
834 * uniform across all SoCs 880 * uniform across all SoCs
835 */ 881 */
836 l = mbox_read_reg(mdev, MAILBOX_REVISION); 882 l = mbox_read_reg(mdev, MAILBOX_REVISION);
837 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); 883 dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
838 884
839 ret = pm_runtime_put_sync(mdev->dev); 885 ret = pm_runtime_put_sync(mdev->dev);
840 if (ret < 0) 886 if (ret < 0)
841 goto unregister; 887 goto unregister;
842 888
843 devm_kfree(&pdev->dev, finfoblk); 889 devm_kfree(&pdev->dev, finfoblk);
844 return 0; 890 return 0;
845 891
846 unregister: 892 unregister:
847 pm_runtime_disable(mdev->dev); 893 pm_runtime_disable(mdev->dev);
848 omap_mbox_unregister(mdev); 894 omap_mbox_unregister(mdev);
849 return ret; 895 return ret;
850 } 896 }
851 897
852 static int omap_mbox_remove(struct platform_device *pdev) 898 static int omap_mbox_remove(struct platform_device *pdev)
853 { 899 {
854 struct omap_mbox_device *mdev = platform_get_drvdata(pdev); 900 struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
855 901
856 pm_runtime_disable(mdev->dev); 902 pm_runtime_disable(mdev->dev);
857 omap_mbox_unregister(mdev); 903 omap_mbox_unregister(mdev);
858 904
859 return 0; 905 return 0;
860 } 906 }
861 907
862 static struct platform_driver omap_mbox_driver = { 908 static struct platform_driver omap_mbox_driver = {
863 .probe = omap_mbox_probe, 909 .probe = omap_mbox_probe,
864 .remove = omap_mbox_remove, 910 .remove = omap_mbox_remove,
865 .driver = { 911 .driver = {
866 .name = "omap-mailbox", 912 .name = "omap-mailbox",
867 .owner = THIS_MODULE, 913 .owner = THIS_MODULE,
868 .of_match_table = of_match_ptr(omap_mailbox_of_match), 914 .of_match_table = of_match_ptr(omap_mailbox_of_match),
869 }, 915 },
870 }; 916 };
871 917
872 static int __init omap_mbox_init(void) 918 static int __init omap_mbox_init(void)
873 { 919 {
874 int err; 920 int err;
875 921
876 err = class_register(&omap_mbox_class); 922 err = class_register(&omap_mbox_class);
877 if (err) 923 if (err)
878 return err; 924 return err;
879 925
880 /* kfifo size sanity check: alignment and minimal size */ 926 /* kfifo size sanity check: alignment and minimal size */
881 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); 927 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
882 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, 928 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
883 sizeof(mbox_msg_t)); 929 sizeof(mbox_msg_t));
884 930
885 return platform_driver_register(&omap_mbox_driver); 931 return platform_driver_register(&omap_mbox_driver);
886 } 932 }
887 subsys_initcall(omap_mbox_init); 933 subsys_initcall(omap_mbox_init);
888 934
889 static void __exit omap_mbox_exit(void) 935 static void __exit omap_mbox_exit(void)
890 { 936 {
891 platform_driver_unregister(&omap_mbox_driver); 937 platform_driver_unregister(&omap_mbox_driver);
892 class_unregister(&omap_mbox_class); 938 class_unregister(&omap_mbox_class);
893 } 939 }
894 module_exit(omap_mbox_exit); 940 module_exit(omap_mbox_exit);
895 941
896 MODULE_LICENSE("GPL v2"); 942 MODULE_LICENSE("GPL v2");
897 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); 943 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
898 MODULE_AUTHOR("Toshihiro Kobayashi"); 944 MODULE_AUTHOR("Toshihiro Kobayashi");
899 MODULE_AUTHOR("Hiroshi DOYU"); 945 MODULE_AUTHOR("Hiroshi DOYU");
drivers/remoteproc/wkup_m3_rproc.c
Diff comments   View file @ 14ed5c8
1 /* 1 /*
2 * AMx3 Wkup M3 Remote Processor driver 2 * AMx3 Wkup M3 Remote Processor driver
3 * 3 *
4 * Copyright (C) 2014 Texas Instruments, Inc. 4 * Copyright (C) 2014 Texas Instruments, Inc.
5 * 5 *
6 * Dave Gerlach <d-gerlach@ti.com> 6 * Dave Gerlach <d-gerlach@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation. 10 * version 2 as published by the Free Software Foundation.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 */ 16 */
17 17
18 #include <linux/kernel.h> 18 #include <linux/kernel.h>
19 #include <linux/module.h> 19 #include <linux/module.h>
20 #include <linux/err.h> 20 #include <linux/err.h>
21 #include <linux/platform_device.h> 21 #include <linux/platform_device.h>
22 #include <linux/irq.h> 22 #include <linux/irq.h>
23 #include <linux/interrupt.h> 23 #include <linux/interrupt.h>
24 #include <linux/pm_runtime.h> 24 #include <linux/pm_runtime.h>
25 #include <linux/firmware.h> 25 #include <linux/firmware.h>
26 #include <linux/remoteproc.h> 26 #include <linux/remoteproc.h>
27 #include <linux/omap-mailbox.h> 27 #include <linux/omap-mailbox.h>
28 #include <linux/mailbox_client.h> 28 #include <linux/mailbox_client.h>
29 #include <linux/wkup_m3.h> 29 #include <linux/wkup_m3.h>
30 #include <linux/kthread.h> 30 #include <linux/kthread.h>
31 31
32 #include <linux/platform_data/wkup_m3.h> 32 #include <linux/platform_data/wkup_m3.h>
33 33
34 #include "remoteproc_internal.h" 34 #include "remoteproc_internal.h"
35 35
36 #define WKUP_M3_WAKE_SRC_MASK 0xFF 36 #define WKUP_M3_WAKE_SRC_MASK 0xFF
37 37
38 #define WKUP_M3_STATUS_RESP_SHIFT 16 38 #define WKUP_M3_STATUS_RESP_SHIFT 16
39 #define WKUP_M3_STATUS_RESP_MASK (0xffff << 16) 39 #define WKUP_M3_STATUS_RESP_MASK (0xffff << 16)
40 40
41 #define WKUP_M3_FW_VERSION_SHIFT 0 41 #define WKUP_M3_FW_VERSION_SHIFT 0
42 #define WKUP_M3_FW_VERSION_MASK 0xffff 42 #define WKUP_M3_FW_VERSION_MASK 0xffff
43 43
44 #define AM33XX_CTRL_IPC_REG_COUNT 0x8 44 #define AM33XX_CTRL_IPC_REG_COUNT 0x8
45 #define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m)) 45 #define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m))
46 46
47 /* AM33XX M3_TXEV_EOI register */ 47 /* AM33XX M3_TXEV_EOI register */
48 #define AM33XX_CONTROL_M3_TXEV_EOI 0x00 48 #define AM33XX_CONTROL_M3_TXEV_EOI 0x00
49 49
50 #define AM33XX_M3_TXEV_ACK (0x1 << 0) 50 #define AM33XX_M3_TXEV_ACK (0x1 << 0)
51 #define AM33XX_M3_TXEV_ENABLE (0x0 << 0) 51 #define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
52 52
53 #define WKUP_M3_DMEM_START 0x80000 53 #define WKUP_M3_DMEM_START 0x80000
54 #define WKUP_M3_AUXDATA_OFFSET 0x1000 54 #define WKUP_M3_AUXDATA_OFFSET 0x1000
55 #define WKUP_M3_AUXDATA_SIZE 0xFF 55 #define WKUP_M3_AUXDATA_SIZE 0xFF
56 56
57 struct wkup_m3_rproc { 57 struct wkup_m3_rproc {
58 struct rproc *rproc; 58 struct rproc *rproc;
59 59
60 void * __iomem dev_table_va; 60 void * __iomem dev_table_va;
61 void * __iomem ipc_mem_base; 61 void * __iomem ipc_mem_base;
62 struct platform_device *pdev; 62 struct platform_device *pdev;
63 63
64 struct mbox_client mbox_client; 64 struct mbox_client mbox_client;
65 struct mbox_chan *mbox; 65 struct mbox_chan *mbox;
66 66
67 bool is_active; 67 bool is_active;
68 bool is_rtc_only; 68 bool is_rtc_only;
69 }; 69 };
70 70
71 static struct wkup_m3_rproc *m3_rproc_static; 71 static struct wkup_m3_rproc *m3_rproc_static;
72 struct wkup_m3_ops *wkup_m3_pm_ops; 72 struct wkup_m3_ops *wkup_m3_pm_ops;
73 73
74 static const struct wkup_m3_wakeup_src wakeups[] = { 74 static const struct wkup_m3_wakeup_src wakeups[] = {
75 {.irq_nr = 16, .src = "PRCM"}, 75 {.irq_nr = 16, .src = "PRCM"},
76 {.irq_nr = 35, .src = "USB0_PHY"}, 76 {.irq_nr = 35, .src = "USB0_PHY"},
77 {.irq_nr = 36, .src = "USB1_PHY"}, 77 {.irq_nr = 36, .src = "USB1_PHY"},
78 {.irq_nr = 40, .src = "I2C0"}, 78 {.irq_nr = 40, .src = "I2C0"},
79 {.irq_nr = 41, .src = "RTC Timer"}, 79 {.irq_nr = 41, .src = "RTC Timer"},
80 {.irq_nr = 42, .src = "RTC Alarm"}, 80 {.irq_nr = 42, .src = "RTC Alarm"},
81 {.irq_nr = 43, .src = "Timer0"}, 81 {.irq_nr = 43, .src = "Timer0"},
82 {.irq_nr = 44, .src = "Timer1"}, 82 {.irq_nr = 44, .src = "Timer1"},
83 {.irq_nr = 45, .src = "UART"}, 83 {.irq_nr = 45, .src = "UART"},
84 {.irq_nr = 46, .src = "GPIO0"}, 84 {.irq_nr = 46, .src = "GPIO0"},
85 {.irq_nr = 48, .src = "MPU_WAKE"}, 85 {.irq_nr = 48, .src = "MPU_WAKE"},
86 {.irq_nr = 49, .src = "WDT0"}, 86 {.irq_nr = 49, .src = "WDT0"},
87 {.irq_nr = 50, .src = "WDT1"}, 87 {.irq_nr = 50, .src = "WDT1"},
88 {.irq_nr = 51, .src = "ADC_TSC"}, 88 {.irq_nr = 51, .src = "ADC_TSC"},
89 {.irq_nr = 0, .src = "Unknown"}, 89 {.irq_nr = 0, .src = "Unknown"},
90 }; 90 };
91 91
92 static void am33xx_txev_eoi(struct wkup_m3_rproc *m3_rproc) 92 static void am33xx_txev_eoi(struct wkup_m3_rproc *m3_rproc)
93 { 93 {
94 writel(AM33XX_M3_TXEV_ACK, 94 writel(AM33XX_M3_TXEV_ACK,
95 m3_rproc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI); 95 m3_rproc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
96 } 96 }
97 97
98 static void am33xx_txev_enable(struct wkup_m3_rproc *m3_rproc) 98 static void am33xx_txev_enable(struct wkup_m3_rproc *m3_rproc)
99 { 99 {
100 writel(AM33XX_M3_TXEV_ENABLE, 100 writel(AM33XX_M3_TXEV_ENABLE,
101 m3_rproc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI); 101 m3_rproc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
102 } 102 }
103 103
104 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_rproc *m3_rproc, 104 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_rproc *m3_rproc,
105 u32 val, int ipc_reg_num) 105 u32 val, int ipc_reg_num)
106 { 106 {
107 if (ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT) 107 if (ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT)
108 return; 108 return;
109 109
110 writel(val, m3_rproc->ipc_mem_base + 110 writel(val, m3_rproc->ipc_mem_base +
111 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num)); 111 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
112 } 112 }
113 113
114 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_rproc *m3_rproc, 114 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_rproc *m3_rproc,
115 int ipc_reg_num) 115 int ipc_reg_num)
116 { 116 {
117 if (ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT) 117 if (ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT)
118 return 0; 118 return 0;
119 119
120 return readl(m3_rproc->ipc_mem_base + 120 return readl(m3_rproc->ipc_mem_base +
121 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num)); 121 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
122 } 122 }
123 123
124 static irqreturn_t wkup_m3_txev_handler(int irq, void *unused) 124 static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
125 { 125 {
126 am33xx_txev_eoi(m3_rproc_static); 126 am33xx_txev_eoi(m3_rproc_static);
127 127
128 if (wkup_m3_pm_ops && wkup_m3_pm_ops->txev_handler) 128 if (wkup_m3_pm_ops && wkup_m3_pm_ops->txev_handler)
129 wkup_m3_pm_ops->txev_handler(); 129 wkup_m3_pm_ops->txev_handler();
130 130
131 am33xx_txev_enable(m3_rproc_static); 131 am33xx_txev_enable(m3_rproc_static);
132 132
133 return IRQ_HANDLED; 133 return IRQ_HANDLED;
134 } 134 }
135 135
136 /** 136 /**
137 * wkup_m3_fw_version_clear - Clear FW version from ipc regs 137 * wkup_m3_fw_version_clear - Clear FW version from ipc regs
138 * 138 *
139 * Invalidate M3 firmware version before hardreset. 139 * Invalidate M3 firmware version before hardreset.
140 * Write invalid version in lower 4 nibbles of parameter 140 * Write invalid version in lower 4 nibbles of parameter
141 * register (ipc_regs + 0x8). 141 * register (ipc_regs + 0x8).
142 */ 142 */
143 143
144 static void wkup_m3_fw_version_clear(void) 144 static void wkup_m3_fw_version_clear(void)
145 { 145 {
146 int val; 146 int val;
147 147
148 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 2); 148 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 2);
149 val &= (~WKUP_M3_FW_VERSION_MASK); 149 val &= (~WKUP_M3_FW_VERSION_MASK);
150 wkup_m3_ctrl_ipc_write(m3_rproc_static, val, 2); 150 wkup_m3_ctrl_ipc_write(m3_rproc_static, val, 2);
151 } 151 }
152 152
153 static void wkup_m3_mbox_callback(struct mbox_client *client, void *data)
154 {
155 omap_mbox_disable_irq(m3_rproc_static->mbox, IRQ_RX);
156 }
157
158 void wkup_m3_set_rtc_only_mode(void) 153 void wkup_m3_set_rtc_only_mode(void)
159 { 154 {
160 m3_rproc_static->is_rtc_only = true; 155 m3_rproc_static->is_rtc_only = true;
161 } 156 }
162 EXPORT_SYMBOL(wkup_m3_set_rtc_only_mode); 157 EXPORT_SYMBOL(wkup_m3_set_rtc_only_mode);
163 158
164 static int wkup_m3_rproc_start(struct rproc *rproc) 159 static int wkup_m3_rproc_start(struct rproc *rproc)
165 { 160 {
166 struct wkup_m3_rproc *m3_rproc = rproc->priv; 161 struct wkup_m3_rproc *m3_rproc = rproc->priv;
167 struct platform_device *pdev = m3_rproc->pdev; 162 struct platform_device *pdev = m3_rproc->pdev;
168 struct device *dev = &pdev->dev; 163 struct device *dev = &pdev->dev;
169 struct wkup_m3_platform_data *pdata = dev->platform_data; 164 struct wkup_m3_platform_data *pdata = dev->platform_data;
170 int ret; 165 int ret;
171 166
172 wkup_m3_fw_version_clear(); 167 wkup_m3_fw_version_clear();
173 168
174 ret = pdata->deassert_reset(pdev, pdata->reset_name); 169 ret = pdata->deassert_reset(pdev, pdata->reset_name);
175 if (ret) { 170 if (ret) {
176 dev_err(dev, "Unable to reset wkup_m3!\n"); 171 dev_err(dev, "Unable to reset wkup_m3!\n");
177 return -ENODEV; 172 return -ENODEV;
178 } 173 }
179 174
180 m3_rproc->mbox_client.dev = dev; 175 m3_rproc->mbox_client.dev = dev;
181 m3_rproc->mbox_client.tx_done = NULL; 176 m3_rproc->mbox_client.tx_done = NULL;
182 m3_rproc->mbox_client.rx_callback = wkup_m3_mbox_callback; 177 m3_rproc->mbox_client.rx_callback = NULL;
183 m3_rproc->mbox_client.tx_block = false; 178 m3_rproc->mbox_client.tx_block = false;
184 m3_rproc->mbox_client.knows_txdone = false; 179 m3_rproc->mbox_client.knows_txdone = false;
185 180
186 m3_rproc->mbox = mbox_request_channel(&m3_rproc->mbox_client, 0); 181 m3_rproc->mbox = mbox_request_channel(&m3_rproc->mbox_client, 0);
187 182
188 if (IS_ERR(m3_rproc->mbox)) { 183 if (IS_ERR(m3_rproc->mbox)) {
189 dev_err(dev, "IPC Request for A8->M3 Channel failed!\n"); 184 dev_err(dev, "IPC Request for A8->M3 Channel failed!\n");
190 ret = PTR_ERR(m3_rproc->mbox); 185 ret = PTR_ERR(m3_rproc->mbox);
191 m3_rproc->mbox = NULL; 186 m3_rproc->mbox = NULL;
192 return ret; 187 return ret;
193 } 188 }
194 189
195 if (wkup_m3_pm_ops && wkup_m3_pm_ops->rproc_ready && 190 if (wkup_m3_pm_ops && wkup_m3_pm_ops->rproc_ready &&
196 !m3_rproc_static->is_rtc_only) 191 !m3_rproc_static->is_rtc_only)
197 wkup_m3_pm_ops->rproc_ready(&m3_rproc_static->pdev->dev); 192 wkup_m3_pm_ops->rproc_ready(&m3_rproc_static->pdev->dev);
198 193
199 m3_rproc_static->is_active = 1; 194 m3_rproc_static->is_active = 1;
200 195
201 return 0; 196 return 0;
202 } 197 }
203 198
204 static int wkup_m3_rproc_stop(struct rproc *rproc) 199 static int wkup_m3_rproc_stop(struct rproc *rproc)
205 { 200 {
206 struct wkup_m3_rproc *m3_rproc = rproc->priv; 201 struct wkup_m3_rproc *m3_rproc = rproc->priv;
207 struct platform_device *pdev = m3_rproc->pdev; 202 struct platform_device *pdev = m3_rproc->pdev;
208 struct device *dev = &pdev->dev; 203 struct device *dev = &pdev->dev;
209 struct wkup_m3_platform_data *pdata = dev->platform_data; 204 struct wkup_m3_platform_data *pdata = dev->platform_data;
210 205
211 mbox_free_channel(m3_rproc_static->mbox); 206 mbox_free_channel(m3_rproc_static->mbox);
212 207
213 pdata->assert_reset(pdev, pdata->reset_name); 208 pdata->assert_reset(pdev, pdata->reset_name);
214 209
215 return 0; 210 return 0;
216 } 211 }
217 212
218 static struct rproc_ops wkup_m3_rproc_ops = { 213 static struct rproc_ops wkup_m3_rproc_ops = {
219 .start = wkup_m3_rproc_start, 214 .start = wkup_m3_rproc_start,
220 .stop = wkup_m3_rproc_stop, 215 .stop = wkup_m3_rproc_stop,
221 }; 216 };
222 217
223 /* Public Functions */ 218 /* Public Functions */
224 219
225 /** 220 /**
226 * wkup_m3_copy_aux_data - Copy auxillary data to special region of m3 dmem 221 * wkup_m3_copy_aux_data - Copy auxillary data to special region of m3 dmem
227 * @data - pointer to data 222 * @data - pointer to data
228 * @sz - size of data to copy (limit 256 bytes) 223 * @sz - size of data to copy (limit 256 bytes)
229 * 224 *
230 * Copies any additional blob of data to the wkup_m3 dmem to be used by the 225 * Copies any additional blob of data to the wkup_m3 dmem to be used by the
231 * firmware 226 * firmware
232 */ 227 */
233 unsigned long wkup_m3_copy_aux_data(const void *data, int sz) 228 unsigned long wkup_m3_copy_aux_data(const void *data, int sz)
234 { 229 {
235 unsigned long aux_data_dev_addr; 230 unsigned long aux_data_dev_addr;
236 void *aux_data_addr; 231 void *aux_data_addr;
237 232
238 aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET; 233 aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET;
239 aux_data_addr = rproc_da_to_va(m3_rproc_static->rproc, 234 aux_data_addr = rproc_da_to_va(m3_rproc_static->rproc,
240 aux_data_dev_addr, 235 aux_data_dev_addr,
241 WKUP_M3_AUXDATA_SIZE, 0); 236 WKUP_M3_AUXDATA_SIZE, 0);
242 memcpy(aux_data_addr, data, sz); 237 memcpy(aux_data_addr, data, sz);
243 238
244 return WKUP_M3_AUXDATA_OFFSET; 239 return WKUP_M3_AUXDATA_OFFSET;
245 } 240 }
246 241
247 /** 242 /**
248 * wkup_m3_set_ops - Set callbacks for user of rproc 243 * wkup_m3_set_ops - Set callbacks for user of rproc
249 * @ops - struct wkup_m3_ops * 244 * @ops - struct wkup_m3_ops *
250 * 245 *
251 * Registers callbacks to wkup_m3 to be invoked after rproc is ready to use 246 * Registers callbacks to wkup_m3 to be invoked after rproc is ready to use
252 * and after an interrupt is handled. 247 * and after an interrupt is handled.
253 */ 248 */
254 void wkup_m3_set_ops(struct wkup_m3_ops *ops) 249 void wkup_m3_set_ops(struct wkup_m3_ops *ops)
255 { 250 {
256 wkup_m3_pm_ops = ops; 251 wkup_m3_pm_ops = ops;
257 252
258 if (m3_rproc_static && m3_rproc_static->is_active && 253 if (m3_rproc_static && m3_rproc_static->is_active &&
259 wkup_m3_pm_ops && wkup_m3_pm_ops->rproc_ready) 254 wkup_m3_pm_ops && wkup_m3_pm_ops->rproc_ready)
260 wkup_m3_pm_ops->rproc_ready(&m3_rproc_static->pdev->dev); 255 wkup_m3_pm_ops->rproc_ready(&m3_rproc_static->pdev->dev);
261 } 256 }
262 257
263 /** 258 /**
264 * wkup_m3_ping - Send a dummy msg to wkup_m3 to tell to to check IPC regs 259 * wkup_m3_ping - Send a dummy msg to wkup_m3 to tell to to check IPC regs
265 * 260 *
266 * Returns the result of sending mbox msg or -EIO if no mbox handle is present 261 * Returns the result of sending mbox msg or -EIO if no mbox handle is present
267 */ 262 */
268 int wkup_m3_ping(void) 263 int wkup_m3_ping(void)
269 { 264 {
270 int ret; 265 int ret;
271 mbox_msg_t dummy_msg = 0; 266 mbox_msg_t dummy_msg = 0;
272 267
273 if (!m3_rproc_static->mbox) { 268 if (!m3_rproc_static->mbox) {
274 dev_err(&m3_rproc_static->pdev->dev, 269 dev_err(&m3_rproc_static->pdev->dev,
275 "No IPC channel to communicate with wkup_m3!\n"); 270 "No IPC channel to communicate with wkup_m3!\n");
276 return -EIO; 271 return -EIO;
277 } 272 }
278 273
279 /* 274 /*
280 * Write a dummy message to the mailbox in order to trigger the RX 275 * Write a dummy message to the mailbox in order to trigger the RX
281 * interrupt to alert the M3 that data is available in the IPC 276 * interrupt to alert the M3 that data is available in the IPC
282 * registers. We must enable the IRQ here and disable it after in 277 * registers. We must enable the IRQ here and disable it after in
283 * the RX callback to avoid multiple interrupts being received 278 * the RX callback to avoid multiple interrupts being received
284 * by the CM3. 279 * by the CM3.
285 */ 280 */
286 omap_mbox_enable_irq(m3_rproc_static->mbox, IRQ_RX);
287 ret = mbox_send_message(m3_rproc_static->mbox, (void *)dummy_msg); 281 ret = mbox_send_message(m3_rproc_static->mbox, (void *)dummy_msg);
288 if (ret < 0) { 282 if (ret < 0) {
289 pr_err("%s: mbox_send_message() failed: %d\n", __func__, ret); 283 pr_err("%s: mbox_send_message() failed: %d\n", __func__, ret);
290 return ret; 284 return ret;
291 } 285 }
292 286
287 mbox_client_txdone(m3_rproc_static->mbox, 0);
293 return 0; 288 return 0;
294 } 289 }
295 290
296 /** 291 /**
297 * wkup_m3_wake_src - Get the wakeup source info passed from wkup_m3 292 * wkup_m3_wake_src - Get the wakeup source info passed from wkup_m3
298 * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the 293 * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
299 * wakeup src value 294 * wakeup src value
300 */ 295 */
301 void wkup_m3_wake_src(struct wkup_m3_wakeup_src *wkup_m3_wakeup) 296 void wkup_m3_wake_src(struct wkup_m3_wakeup_src *wkup_m3_wakeup)
302 { 297 {
303 unsigned int wakeup_src_idx; 298 unsigned int wakeup_src_idx;
304 int j, val; 299 int j, val;
305 300
306 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 6); 301 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 6);
307 302
308 wakeup_src_idx = val & WKUP_M3_WAKE_SRC_MASK; 303 wakeup_src_idx = val & WKUP_M3_WAKE_SRC_MASK;
309 304
310 for (j = 0; j < ARRAY_SIZE(wakeups)-1; j++) { 305 for (j = 0; j < ARRAY_SIZE(wakeups)-1; j++) {
311 if (wakeups[j].irq_nr == wakeup_src_idx) { 306 if (wakeups[j].irq_nr == wakeup_src_idx) {
312 *wkup_m3_wakeup = wakeups[j]; 307 *wkup_m3_wakeup = wakeups[j];
313 return; 308 return;
314 } 309 }
315 } 310 }
316 *wkup_m3_wakeup = wakeups[j]; 311 *wkup_m3_wakeup = wakeups[j];
317 } 312 }
318 313
319 /** 314 /**
320 * wkup_m3_pm_status - Return the status code from wkup_m3 after sleep event 315 * wkup_m3_pm_status - Return the status code from wkup_m3 after sleep event
321 * 316 *
322 * Returns an error code that indicates whether or not the dsired sleep 317 * Returns an error code that indicates whether or not the dsired sleep
323 * action was a success or not. 318 * action was a success or not.
324 */ 319 */
325 int wkup_m3_pm_status(void) 320 int wkup_m3_pm_status(void)
326 { 321 {
327 unsigned int i; 322 unsigned int i;
328 int val; 323 int val;
329 324
330 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 1); 325 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 1);
331 326
332 i = WKUP_M3_STATUS_RESP_MASK & val; 327 i = WKUP_M3_STATUS_RESP_MASK & val;
333 i >>= __ffs(WKUP_M3_STATUS_RESP_MASK); 328 i >>= __ffs(WKUP_M3_STATUS_RESP_MASK);
334 329
335 return i; 330 return i;
336 } 331 }
337 332
338 /** 333 /**
339 * wkup_m3_fw_version_read - Return the fw version given by the wkup_m3 334 * wkup_m3_fw_version_read - Return the fw version given by the wkup_m3
340 * 335 *
341 * After boot the fw version should be read to ensure it is compatible. 336 * After boot the fw version should be read to ensure it is compatible.
342 */ 337 */
343 int wkup_m3_fw_version_read(void) 338 int wkup_m3_fw_version_read(void)
344 { 339 {
345 int val; 340 int val;
346 341
347 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 2); 342 val = wkup_m3_ctrl_ipc_read(m3_rproc_static, 2);
348 343
349 return val & WKUP_M3_FW_VERSION_MASK; 344 return val & WKUP_M3_FW_VERSION_MASK;
350 } 345 }
351 346
352 /** 347 /**
353 * wkup_m3_set_cmd - write contents of struct to ipc regs 348 * wkup_m3_set_cmd - write contents of struct to ipc regs
354 * @ipc_regs: struct wkup_m3_ipc_regs * 349 * @ipc_regs: struct wkup_m3_ipc_regs *
355 */ 350 */
356 void wkup_m3_set_cmd(struct wkup_m3_ipc_regs *ipc_regs) 351 void wkup_m3_set_cmd(struct wkup_m3_ipc_regs *ipc_regs)
357 { 352 {
358 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg0, 0); 353 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg0, 0);
359 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg1, 1); 354 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg1, 1);
360 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg2, 2); 355 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg2, 2);
361 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg3, 3); 356 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg3, 3);
362 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg4, 4); 357 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg4, 4);
363 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg5, 5); 358 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg5, 5);
364 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg6, 6); 359 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg6, 6);
365 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg7, 7); 360 wkup_m3_ctrl_ipc_write(m3_rproc_static, ipc_regs->reg7, 7);
366 } 361 }
367 362
368 static void wkup_m3_rproc_loader_thread(struct rproc *rproc) 363 static void wkup_m3_rproc_loader_thread(struct rproc *rproc)
369 { 364 {
370 struct wkup_m3_rproc *m3_rproc = rproc->priv; 365 struct wkup_m3_rproc *m3_rproc = rproc->priv;
371 struct device *dev = &m3_rproc->pdev->dev; 366 struct device *dev = &m3_rproc->pdev->dev;
372 int ret; 367 int ret;
373 368
374 wait_for_completion(&rproc->firmware_loading_complete); 369 wait_for_completion(&rproc->firmware_loading_complete);
375 370
376 ret = rproc_boot(rproc); 371 ret = rproc_boot(rproc);
377 if (ret) 372 if (ret)
378 dev_err(dev, "rproc_boot failed\n"); 373 dev_err(dev, "rproc_boot failed\n");
379 374
380 do_exit(0); 375 do_exit(0);
381 } 376 }
382 static int wkup_m3_rproc_probe(struct platform_device *pdev) 377 static int wkup_m3_rproc_probe(struct platform_device *pdev)
383 { 378 {
384 struct device *dev = &pdev->dev; 379 struct device *dev = &pdev->dev;
385 struct wkup_m3_platform_data *pdata = dev->platform_data; 380 struct wkup_m3_platform_data *pdata = dev->platform_data;
386 struct wkup_m3_rproc *m3_rproc; 381 struct wkup_m3_rproc *m3_rproc;
387 struct rproc *rproc; 382 struct rproc *rproc;
388 int irq, ret; 383 int irq, ret;
389 struct resource *res; 384 struct resource *res;
390 struct task_struct *task; 385 struct task_struct *task;
386
387 if (!wkup_m3_pm_ops)
388 return -EPROBE_DEFER;
391 389
392 pm_runtime_enable(&pdev->dev); 390 pm_runtime_enable(&pdev->dev);
393 391
394 ret = pm_runtime_get_sync(&pdev->dev); 392 ret = pm_runtime_get_sync(&pdev->dev);
395 if (IS_ERR_VALUE(ret)) { 393 if (IS_ERR_VALUE(ret)) {
396 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); 394 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
397 return ret; 395 return ret;
398 } 396 }
399 397
400 rproc = rproc_alloc(dev, "wkup_m3", &wkup_m3_rproc_ops, 398 rproc = rproc_alloc(dev, "wkup_m3", &wkup_m3_rproc_ops,
401 "am335x-pm-firmware.elf", sizeof(*m3_rproc)); 399 "am335x-pm-firmware.elf", sizeof(*m3_rproc));
402 if (!rproc) 400 if (!rproc)
403 return -ENOMEM; 401 return -ENOMEM;
404 402
405 m3_rproc = rproc->priv; 403 m3_rproc = rproc->priv;
406 m3_rproc->rproc = rproc; 404 m3_rproc->rproc = rproc;
407 m3_rproc->pdev = pdev; 405 m3_rproc->pdev = pdev;
408 406
409 m3_rproc_static = m3_rproc; 407 m3_rproc_static = m3_rproc;
410 408
411 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipc_regs"); 409 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipc_regs");
412 m3_rproc->ipc_mem_base = devm_ioremap_resource(dev, res); 410 m3_rproc->ipc_mem_base = devm_ioremap_resource(dev, res);
413 if (!m3_rproc->ipc_mem_base) { 411 if (!m3_rproc->ipc_mem_base) {
414 dev_err(dev, "could not ioremap ipc_mem\n"); 412 dev_err(dev, "could not ioremap ipc_mem\n");
415 ret = -EADDRNOTAVAIL; 413 ret = -EADDRNOTAVAIL;
416 goto err; 414 goto err;
417 } 415 }
418 416
419 irq = platform_get_irq(pdev, 0); 417 irq = platform_get_irq(pdev, 0);
420 if (!irq) { 418 if (!irq) {
421 dev_err(&pdev->dev, "no irq resource\n"); 419 dev_err(&pdev->dev, "no irq resource\n");
422 ret = -ENXIO; 420 ret = -ENXIO;
423 goto err; 421 goto err;
424 } 422 }
425 423
426 ret = devm_request_irq(dev, irq, wkup_m3_txev_handler, 424 ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
427 IRQF_DISABLED, "wkup_m3_txev", m3_rproc); 425 IRQF_DISABLED, "wkup_m3_txev", m3_rproc);
428 if (ret) { 426 if (ret) {
429 dev_err(dev, "request_irq failed\n"); 427 dev_err(dev, "request_irq failed\n");
430 goto err; 428 goto err;
431 } 429 }
432 430
433 if (!(pdata && pdata->deassert_reset)) { 431 if (!(pdata && pdata->deassert_reset)) {
434 dev_err(dev, "Platform data missing deassert_reset!\n"); 432 dev_err(dev, "Platform data missing deassert_reset!\n");
435 ret = -ENODEV; 433 ret = -ENODEV;
436 } 434 }
437 435
438 /* Register as a remoteproc device */ 436 /* Register as a remoteproc device */
439 ret = rproc_add(rproc); 437 ret = rproc_add(rproc);
440 if (ret) { 438 if (ret) {
441 dev_err(dev, "rproc_add failed\n"); 439 dev_err(dev, "rproc_add failed\n");
442 goto err; 440 goto err;
443 } 441 }
444 442
445 /* 443 /*
446 * Wait for firmware loading completion in a thread so we 444 * Wait for firmware loading completion in a thread so we
447 * can boot the wkup_m3 as soon as it's ready without holding 445 * can boot the wkup_m3 as soon as it's ready without holding
448 * up kernel boot 446 * up kernel boot
449 */ 447 */
450 task = kthread_run((void *)wkup_m3_rproc_loader_thread, rproc, 448 task = kthread_run((void *)wkup_m3_rproc_loader_thread, rproc,
451 "wkup_m3_rproc_loader"); 449 "wkup_m3_rproc_loader");
452 450
453 if (IS_ERR(task)) { 451 if (IS_ERR(task)) {
454 dev_err(dev, "can't create rproc_loader thread\n"); 452 dev_err(dev, "can't create rproc_loader thread\n");
455 goto err; 453 goto err;
456 } 454 }
457 455
458 return 0; 456 return 0;
459 457
460 err: 458 err:
461 rproc_put(rproc); 459 rproc_put(rproc);
462 pm_runtime_put_sync(&pdev->dev); 460 pm_runtime_put_sync(&pdev->dev);
463 return ret; 461 return ret;
464 } 462 }
465 463
466 static int wkup_m3_rproc_remove(struct platform_device *pdev) 464 static int wkup_m3_rproc_remove(struct platform_device *pdev)
467 { 465 {
468 struct rproc *rproc = platform_get_drvdata(pdev); 466 struct rproc *rproc = platform_get_drvdata(pdev);
469 467
470 rproc_del(rproc); 468 rproc_del(rproc);
471 rproc_put(rproc); 469 rproc_put(rproc);
472 pm_runtime_put_sync(&pdev->dev); 470 pm_runtime_put_sync(&pdev->dev);
473 471
474 m3_rproc_static = NULL; 472 m3_rproc_static = NULL;
475 473
476 return 0; 474 return 0;
477 } 475 }
478 476
479 static int wkm3_suspend(struct device *dev) 477 static int wkm3_suspend(struct device *dev)
480 { 478 {
481 return 0; 479 return 0;
482 } 480 }
483 481
484 static int wkm3_resume(struct device *dev) 482 static int wkm3_resume(struct device *dev)
485 { 483 {
486 if (m3_rproc_static->is_rtc_only) { 484 if (m3_rproc_static->is_rtc_only) {
487 rproc_shutdown(m3_rproc_static->rproc); 485 rproc_shutdown(m3_rproc_static->rproc);
488 rproc_boot(m3_rproc_static->rproc); 486 rproc_boot(m3_rproc_static->rproc);
489 } 487 }
490 488
491 m3_rproc_static->is_rtc_only = false; 489 m3_rproc_static->is_rtc_only = false;
492 490
493 return 0; 491 return 0;
494 } 492 }
495 493
496 static int wkup_m3_rpm_suspend(struct device *dev) 494 static int wkup_m3_rpm_suspend(struct device *dev)
497 { 495 {
498 return -EBUSY; 496 return -EBUSY;
499 } 497 }
500 498
501 static int wkup_m3_rpm_resume(struct device *dev) 499 static int wkup_m3_rpm_resume(struct device *dev)
502 { 500 {
503 return 0; 501 return 0;
504 } 502 }
505 503
506 static const struct dev_pm_ops wkup_m3_rproc_pm_ops = { 504 static const struct dev_pm_ops wkup_m3_rproc_pm_ops = {
507 SET_SYSTEM_SLEEP_PM_OPS(wkm3_suspend, wkm3_resume) 505 SET_SYSTEM_SLEEP_PM_OPS(wkm3_suspend, wkm3_resume)
508 SET_RUNTIME_PM_OPS(wkup_m3_rpm_suspend, wkup_m3_rpm_resume, NULL) 506 SET_RUNTIME_PM_OPS(wkup_m3_rpm_suspend, wkup_m3_rpm_resume, NULL)
509 }; 507 };
510 508
511 static const struct of_device_id wkup_m3_rproc_of_match[] = { 509 static const struct of_device_id wkup_m3_rproc_of_match[] = {
512 { .compatible = "ti,am3353-wkup-m3", .data = NULL, }, 510 { .compatible = "ti,am3353-wkup-m3", .data = NULL, },
513 { .compatible = "ti,am4372-wkup-m3", .data = NULL, }, 511 { .compatible = "ti,am4372-wkup-m3", .data = NULL, },
514 {}, 512 {},
515 }; 513 };
516 514
517 static struct platform_driver wkup_m3_rproc_driver = { 515 static struct platform_driver wkup_m3_rproc_driver = {
518 .probe = wkup_m3_rproc_probe, 516 .probe = wkup_m3_rproc_probe,
519 .remove = wkup_m3_rproc_remove, 517 .remove = wkup_m3_rproc_remove,
520 .driver = { 518 .driver = {
521 .name = "wkup_m3", 519 .name = "wkup_m3",
522 .owner = THIS_MODULE, 520 .owner = THIS_MODULE,
523 .of_match_table = wkup_m3_rproc_of_match, 521 .of_match_table = wkup_m3_rproc_of_match,
524 .pm = &wkup_m3_rproc_pm_ops, 522 .pm = &wkup_m3_rproc_pm_ops,
525 }, 523 },
526 }; 524 };
527 525
528 module_platform_driver(wkup_m3_rproc_driver); 526 module_platform_driver(wkup_m3_rproc_driver);