Eric Lee / smarc-ti-linux-kernel

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Commit 2196c6f1ed66eef23df3b478cfe71661ae83726e

Authored by Vasant Hegde
Committed by Benjamin Herrenschmidt
1 parent 654837e8fe
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

powerpc/powernv: Return secondary CPUs to firmware before FW update 

Firmware update on PowerNV platform takes several minutes. During
this time one CPU is stuck in FW and the kernel complains about "soft
lockups".

This patch returns all secondary CPUs to firmware before starting
firmware update process.

[ Reworked a bit and cleaned up -- BenH ]

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Showing 3 changed files with 66 additions and 7 deletions Inline Diff

arch/powerpc/include/asm/opal.h
Diff comments   View file @ 2196c6f
1 /* 1 /*
2 * PowerNV OPAL definitions. 2 * PowerNV OPAL definitions.
3 * 3 *
4 * Copyright 2011 IBM Corp. 4 * Copyright 2011 IBM Corp.
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12 #ifndef __OPAL_H 12 #ifndef __OPAL_H
13 #define __OPAL_H 13 #define __OPAL_H
14 14
15 /****** Takeover interface ********/ 15 /****** Takeover interface ********/
16 16
17 /* PAPR H-Call used to querty the HAL existence and/or instanciate 17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only). 18 * it from within pHyp (tech preview only).
19 * 19 *
20 * This is exclusively used in prom_init.c 20 * This is exclusively used in prom_init.c
21 */ 21 */
22 22
23 #ifndef __ASSEMBLY__ 23 #ifndef __ASSEMBLY__
24 24
25 struct opal_takeover_args { 25 struct opal_takeover_args {
26 u64 k_image; /* r4 */ 26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */ 27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */ 28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */ 29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */ 30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */ 31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */ 32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */ 33 u64 rd_loc; /* r11 */
34 }; 34 };
35 35
36 /* 36 /*
37 * SG entry 37 * SG entry
38 * 38 *
39 * WARNING: The current implementation requires each entry 39 * WARNING: The current implementation requires each entry
40 * to represent a block that is 4k aligned *and* each block 40 * to represent a block that is 4k aligned *and* each block
41 * size except the last one in the list to be as well. 41 * size except the last one in the list to be as well.
42 */ 42 */
43 struct opal_sg_entry { 43 struct opal_sg_entry {
44 __be64 data; 44 __be64 data;
45 __be64 length; 45 __be64 length;
46 }; 46 };
47 47
48 /* SG list */ 48 /* SG list */
49 struct opal_sg_list { 49 struct opal_sg_list {
50 __be64 length; 50 __be64 length;
51 __be64 next; 51 __be64 next;
52 struct opal_sg_entry entry[]; 52 struct opal_sg_entry entry[];
53 }; 53 };
54 54
55 /* We calculate number of sg entries based on PAGE_SIZE */ 55 /* We calculate number of sg entries based on PAGE_SIZE */
56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) 56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
57 57
58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align); 58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
59 59
60 extern long opal_do_takeover(struct opal_takeover_args *args); 60 extern long opal_do_takeover(struct opal_takeover_args *args);
61 61
62 struct rtas_args; 62 struct rtas_args;
63 extern int opal_enter_rtas(struct rtas_args *args, 63 extern int opal_enter_rtas(struct rtas_args *args,
64 unsigned long data, 64 unsigned long data,
65 unsigned long entry); 65 unsigned long entry);
66 66
67 #endif /* __ASSEMBLY__ */ 67 #endif /* __ASSEMBLY__ */
68 68
69 /****** OPAL APIs ******/ 69 /****** OPAL APIs ******/
70 70
71 /* Return codes */ 71 /* Return codes */
72 #define OPAL_SUCCESS 0 72 #define OPAL_SUCCESS 0
73 #define OPAL_PARAMETER -1 73 #define OPAL_PARAMETER -1
74 #define OPAL_BUSY -2 74 #define OPAL_BUSY -2
75 #define OPAL_PARTIAL -3 75 #define OPAL_PARTIAL -3
76 #define OPAL_CONSTRAINED -4 76 #define OPAL_CONSTRAINED -4
77 #define OPAL_CLOSED -5 77 #define OPAL_CLOSED -5
78 #define OPAL_HARDWARE -6 78 #define OPAL_HARDWARE -6
79 #define OPAL_UNSUPPORTED -7 79 #define OPAL_UNSUPPORTED -7
80 #define OPAL_PERMISSION -8 80 #define OPAL_PERMISSION -8
81 #define OPAL_NO_MEM -9 81 #define OPAL_NO_MEM -9
82 #define OPAL_RESOURCE -10 82 #define OPAL_RESOURCE -10
83 #define OPAL_INTERNAL_ERROR -11 83 #define OPAL_INTERNAL_ERROR -11
84 #define OPAL_BUSY_EVENT -12 84 #define OPAL_BUSY_EVENT -12
85 #define OPAL_HARDWARE_FROZEN -13 85 #define OPAL_HARDWARE_FROZEN -13
86 #define OPAL_WRONG_STATE -14 86 #define OPAL_WRONG_STATE -14
87 #define OPAL_ASYNC_COMPLETION -15 87 #define OPAL_ASYNC_COMPLETION -15
88 88
89 /* API Tokens (in r0) */ 89 /* API Tokens (in r0) */
90 #define OPAL_INVALID_CALL -1 90 #define OPAL_INVALID_CALL -1
91 #define OPAL_CONSOLE_WRITE 1 91 #define OPAL_CONSOLE_WRITE 1
92 #define OPAL_CONSOLE_READ 2 92 #define OPAL_CONSOLE_READ 2
93 #define OPAL_RTC_READ 3 93 #define OPAL_RTC_READ 3
94 #define OPAL_RTC_WRITE 4 94 #define OPAL_RTC_WRITE 4
95 #define OPAL_CEC_POWER_DOWN 5 95 #define OPAL_CEC_POWER_DOWN 5
96 #define OPAL_CEC_REBOOT 6 96 #define OPAL_CEC_REBOOT 6
97 #define OPAL_READ_NVRAM 7 97 #define OPAL_READ_NVRAM 7
98 #define OPAL_WRITE_NVRAM 8 98 #define OPAL_WRITE_NVRAM 8
99 #define OPAL_HANDLE_INTERRUPT 9 99 #define OPAL_HANDLE_INTERRUPT 9
100 #define OPAL_POLL_EVENTS 10 100 #define OPAL_POLL_EVENTS 10
101 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 101 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
102 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 102 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
103 #define OPAL_PCI_CONFIG_READ_BYTE 13 103 #define OPAL_PCI_CONFIG_READ_BYTE 13
104 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 104 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
105 #define OPAL_PCI_CONFIG_READ_WORD 15 105 #define OPAL_PCI_CONFIG_READ_WORD 15
106 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 106 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
107 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 107 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
108 #define OPAL_PCI_CONFIG_WRITE_WORD 18 108 #define OPAL_PCI_CONFIG_WRITE_WORD 18
109 #define OPAL_SET_XIVE 19 109 #define OPAL_SET_XIVE 19
110 #define OPAL_GET_XIVE 20 110 #define OPAL_GET_XIVE 20
111 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 111 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
112 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 112 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
113 #define OPAL_PCI_EEH_FREEZE_STATUS 23 113 #define OPAL_PCI_EEH_FREEZE_STATUS 23
114 #define OPAL_PCI_SHPC 24 114 #define OPAL_PCI_SHPC 24
115 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 115 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
116 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 116 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
117 #define OPAL_PCI_PHB_MMIO_ENABLE 27 117 #define OPAL_PCI_PHB_MMIO_ENABLE 27
118 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 118 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
119 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 119 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
120 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 120 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
121 #define OPAL_PCI_SET_PE 31 121 #define OPAL_PCI_SET_PE 31
122 #define OPAL_PCI_SET_PELTV 32 122 #define OPAL_PCI_SET_PELTV 32
123 #define OPAL_PCI_SET_MVE 33 123 #define OPAL_PCI_SET_MVE 33
124 #define OPAL_PCI_SET_MVE_ENABLE 34 124 #define OPAL_PCI_SET_MVE_ENABLE 34
125 #define OPAL_PCI_GET_XIVE_REISSUE 35 125 #define OPAL_PCI_GET_XIVE_REISSUE 35
126 #define OPAL_PCI_SET_XIVE_REISSUE 36 126 #define OPAL_PCI_SET_XIVE_REISSUE 36
127 #define OPAL_PCI_SET_XIVE_PE 37 127 #define OPAL_PCI_SET_XIVE_PE 37
128 #define OPAL_GET_XIVE_SOURCE 38 128 #define OPAL_GET_XIVE_SOURCE 38
129 #define OPAL_GET_MSI_32 39 129 #define OPAL_GET_MSI_32 39
130 #define OPAL_GET_MSI_64 40 130 #define OPAL_GET_MSI_64 40
131 #define OPAL_START_CPU 41 131 #define OPAL_START_CPU 41
132 #define OPAL_QUERY_CPU_STATUS 42 132 #define OPAL_QUERY_CPU_STATUS 42
133 #define OPAL_WRITE_OPPANEL 43 133 #define OPAL_WRITE_OPPANEL 43
134 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 134 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
135 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 135 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
136 #define OPAL_PCI_RESET 49 136 #define OPAL_PCI_RESET 49
137 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 137 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
138 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 138 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
139 #define OPAL_PCI_FENCE_PHB 52 139 #define OPAL_PCI_FENCE_PHB 52
140 #define OPAL_PCI_REINIT 53 140 #define OPAL_PCI_REINIT 53
141 #define OPAL_PCI_MASK_PE_ERROR 54 141 #define OPAL_PCI_MASK_PE_ERROR 54
142 #define OPAL_SET_SLOT_LED_STATUS 55 142 #define OPAL_SET_SLOT_LED_STATUS 55
143 #define OPAL_GET_EPOW_STATUS 56 143 #define OPAL_GET_EPOW_STATUS 56
144 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 144 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
145 #define OPAL_RESERVED1 58 145 #define OPAL_RESERVED1 58
146 #define OPAL_RESERVED2 59 146 #define OPAL_RESERVED2 59
147 #define OPAL_PCI_NEXT_ERROR 60 147 #define OPAL_PCI_NEXT_ERROR 60
148 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 148 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
149 #define OPAL_PCI_POLL 62 149 #define OPAL_PCI_POLL 62
150 #define OPAL_PCI_MSI_EOI 63 150 #define OPAL_PCI_MSI_EOI 63
151 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 151 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
152 #define OPAL_XSCOM_READ 65 152 #define OPAL_XSCOM_READ 65
153 #define OPAL_XSCOM_WRITE 66 153 #define OPAL_XSCOM_WRITE 66
154 #define OPAL_LPC_READ 67 154 #define OPAL_LPC_READ 67
155 #define OPAL_LPC_WRITE 68 155 #define OPAL_LPC_WRITE 68
156 #define OPAL_RETURN_CPU 69 156 #define OPAL_RETURN_CPU 69
157 #define OPAL_ELOG_READ 71 157 #define OPAL_ELOG_READ 71
158 #define OPAL_ELOG_WRITE 72 158 #define OPAL_ELOG_WRITE 72
159 #define OPAL_ELOG_ACK 73 159 #define OPAL_ELOG_ACK 73
160 #define OPAL_ELOG_RESEND 74 160 #define OPAL_ELOG_RESEND 74
161 #define OPAL_ELOG_SIZE 75 161 #define OPAL_ELOG_SIZE 75
162 #define OPAL_FLASH_VALIDATE 76 162 #define OPAL_FLASH_VALIDATE 76
163 #define OPAL_FLASH_MANAGE 77 163 #define OPAL_FLASH_MANAGE 77
164 #define OPAL_FLASH_UPDATE 78 164 #define OPAL_FLASH_UPDATE 78
165 #define OPAL_RESYNC_TIMEBASE 79 165 #define OPAL_RESYNC_TIMEBASE 79
166 #define OPAL_DUMP_INIT 81 166 #define OPAL_DUMP_INIT 81
167 #define OPAL_DUMP_INFO 82 167 #define OPAL_DUMP_INFO 82
168 #define OPAL_DUMP_READ 83 168 #define OPAL_DUMP_READ 83
169 #define OPAL_DUMP_ACK 84 169 #define OPAL_DUMP_ACK 84
170 #define OPAL_GET_MSG 85 170 #define OPAL_GET_MSG 85
171 #define OPAL_CHECK_ASYNC_COMPLETION 86 171 #define OPAL_CHECK_ASYNC_COMPLETION 86
172 #define OPAL_SYNC_HOST_REBOOT 87 172 #define OPAL_SYNC_HOST_REBOOT 87
173 #define OPAL_SENSOR_READ 88 173 #define OPAL_SENSOR_READ 88
174 #define OPAL_GET_PARAM 89 174 #define OPAL_GET_PARAM 89
175 #define OPAL_SET_PARAM 90 175 #define OPAL_SET_PARAM 90
176 #define OPAL_DUMP_RESEND 91 176 #define OPAL_DUMP_RESEND 91
177 #define OPAL_DUMP_INFO2 94 177 #define OPAL_DUMP_INFO2 94
178 178
179 #ifndef __ASSEMBLY__ 179 #ifndef __ASSEMBLY__
180 180
181 #include <linux/notifier.h> 181 #include <linux/notifier.h>
182 182
183 /* Other enums */ 183 /* Other enums */
184 enum OpalVendorApiTokens { 184 enum OpalVendorApiTokens {
185 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 185 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
186 }; 186 };
187 187
188 enum OpalFreezeState { 188 enum OpalFreezeState {
189 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 189 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
190 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 190 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
191 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 191 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
192 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 192 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
193 OPAL_EEH_STOPPED_RESET = 4, 193 OPAL_EEH_STOPPED_RESET = 4,
194 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 194 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
195 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 195 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
196 }; 196 };
197 197
198 enum OpalEehFreezeActionToken { 198 enum OpalEehFreezeActionToken {
199 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 199 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
200 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 200 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
201 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3 201 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
202 }; 202 };
203 203
204 enum OpalPciStatusToken { 204 enum OpalPciStatusToken {
205 OPAL_EEH_NO_ERROR = 0, 205 OPAL_EEH_NO_ERROR = 0,
206 OPAL_EEH_IOC_ERROR = 1, 206 OPAL_EEH_IOC_ERROR = 1,
207 OPAL_EEH_PHB_ERROR = 2, 207 OPAL_EEH_PHB_ERROR = 2,
208 OPAL_EEH_PE_ERROR = 3, 208 OPAL_EEH_PE_ERROR = 3,
209 OPAL_EEH_PE_MMIO_ERROR = 4, 209 OPAL_EEH_PE_MMIO_ERROR = 4,
210 OPAL_EEH_PE_DMA_ERROR = 5 210 OPAL_EEH_PE_DMA_ERROR = 5
211 }; 211 };
212 212
213 enum OpalPciErrorSeverity { 213 enum OpalPciErrorSeverity {
214 OPAL_EEH_SEV_NO_ERROR = 0, 214 OPAL_EEH_SEV_NO_ERROR = 0,
215 OPAL_EEH_SEV_IOC_DEAD = 1, 215 OPAL_EEH_SEV_IOC_DEAD = 1,
216 OPAL_EEH_SEV_PHB_DEAD = 2, 216 OPAL_EEH_SEV_PHB_DEAD = 2,
217 OPAL_EEH_SEV_PHB_FENCED = 3, 217 OPAL_EEH_SEV_PHB_FENCED = 3,
218 OPAL_EEH_SEV_PE_ER = 4, 218 OPAL_EEH_SEV_PE_ER = 4,
219 OPAL_EEH_SEV_INF = 5 219 OPAL_EEH_SEV_INF = 5
220 }; 220 };
221 221
222 enum OpalShpcAction { 222 enum OpalShpcAction {
223 OPAL_SHPC_GET_LINK_STATE = 0, 223 OPAL_SHPC_GET_LINK_STATE = 0,
224 OPAL_SHPC_GET_SLOT_STATE = 1 224 OPAL_SHPC_GET_SLOT_STATE = 1
225 }; 225 };
226 226
227 enum OpalShpcLinkState { 227 enum OpalShpcLinkState {
228 OPAL_SHPC_LINK_DOWN = 0, 228 OPAL_SHPC_LINK_DOWN = 0,
229 OPAL_SHPC_LINK_UP = 1 229 OPAL_SHPC_LINK_UP = 1
230 }; 230 };
231 231
232 enum OpalMmioWindowType { 232 enum OpalMmioWindowType {
233 OPAL_M32_WINDOW_TYPE = 1, 233 OPAL_M32_WINDOW_TYPE = 1,
234 OPAL_M64_WINDOW_TYPE = 2, 234 OPAL_M64_WINDOW_TYPE = 2,
235 OPAL_IO_WINDOW_TYPE = 3 235 OPAL_IO_WINDOW_TYPE = 3
236 }; 236 };
237 237
238 enum OpalShpcSlotState { 238 enum OpalShpcSlotState {
239 OPAL_SHPC_DEV_NOT_PRESENT = 0, 239 OPAL_SHPC_DEV_NOT_PRESENT = 0,
240 OPAL_SHPC_DEV_PRESENT = 1 240 OPAL_SHPC_DEV_PRESENT = 1
241 }; 241 };
242 242
243 enum OpalExceptionHandler { 243 enum OpalExceptionHandler {
244 OPAL_MACHINE_CHECK_HANDLER = 1, 244 OPAL_MACHINE_CHECK_HANDLER = 1,
245 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 245 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
246 OPAL_SOFTPATCH_HANDLER = 3 246 OPAL_SOFTPATCH_HANDLER = 3
247 }; 247 };
248 248
249 enum OpalPendingState { 249 enum OpalPendingState {
250 OPAL_EVENT_OPAL_INTERNAL = 0x1, 250 OPAL_EVENT_OPAL_INTERNAL = 0x1,
251 OPAL_EVENT_NVRAM = 0x2, 251 OPAL_EVENT_NVRAM = 0x2,
252 OPAL_EVENT_RTC = 0x4, 252 OPAL_EVENT_RTC = 0x4,
253 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 253 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
254 OPAL_EVENT_CONSOLE_INPUT = 0x10, 254 OPAL_EVENT_CONSOLE_INPUT = 0x10,
255 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 255 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
256 OPAL_EVENT_ERROR_LOG = 0x40, 256 OPAL_EVENT_ERROR_LOG = 0x40,
257 OPAL_EVENT_EPOW = 0x80, 257 OPAL_EVENT_EPOW = 0x80,
258 OPAL_EVENT_LED_STATUS = 0x100, 258 OPAL_EVENT_LED_STATUS = 0x100,
259 OPAL_EVENT_PCI_ERROR = 0x200, 259 OPAL_EVENT_PCI_ERROR = 0x200,
260 OPAL_EVENT_DUMP_AVAIL = 0x400, 260 OPAL_EVENT_DUMP_AVAIL = 0x400,
261 OPAL_EVENT_MSG_PENDING = 0x800, 261 OPAL_EVENT_MSG_PENDING = 0x800,
262 }; 262 };
263 263
264 enum OpalMessageType { 264 enum OpalMessageType {
265 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 265 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
266 * additional params function-specific 266 * additional params function-specific
267 */ 267 */
268 OPAL_MSG_MEM_ERR, 268 OPAL_MSG_MEM_ERR,
269 OPAL_MSG_EPOW, 269 OPAL_MSG_EPOW,
270 OPAL_MSG_SHUTDOWN, 270 OPAL_MSG_SHUTDOWN,
271 OPAL_MSG_TYPE_MAX, 271 OPAL_MSG_TYPE_MAX,
272 }; 272 };
273 273
274 /* Machine check related definitions */ 274 /* Machine check related definitions */
275 enum OpalMCE_Version { 275 enum OpalMCE_Version {
276 OpalMCE_V1 = 1, 276 OpalMCE_V1 = 1,
277 }; 277 };
278 278
279 enum OpalMCE_Severity { 279 enum OpalMCE_Severity {
280 OpalMCE_SEV_NO_ERROR = 0, 280 OpalMCE_SEV_NO_ERROR = 0,
281 OpalMCE_SEV_WARNING = 1, 281 OpalMCE_SEV_WARNING = 1,
282 OpalMCE_SEV_ERROR_SYNC = 2, 282 OpalMCE_SEV_ERROR_SYNC = 2,
283 OpalMCE_SEV_FATAL = 3, 283 OpalMCE_SEV_FATAL = 3,
284 }; 284 };
285 285
286 enum OpalMCE_Disposition { 286 enum OpalMCE_Disposition {
287 OpalMCE_DISPOSITION_RECOVERED = 0, 287 OpalMCE_DISPOSITION_RECOVERED = 0,
288 OpalMCE_DISPOSITION_NOT_RECOVERED = 1, 288 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
289 }; 289 };
290 290
291 enum OpalMCE_Initiator { 291 enum OpalMCE_Initiator {
292 OpalMCE_INITIATOR_UNKNOWN = 0, 292 OpalMCE_INITIATOR_UNKNOWN = 0,
293 OpalMCE_INITIATOR_CPU = 1, 293 OpalMCE_INITIATOR_CPU = 1,
294 }; 294 };
295 295
296 enum OpalMCE_ErrorType { 296 enum OpalMCE_ErrorType {
297 OpalMCE_ERROR_TYPE_UNKNOWN = 0, 297 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
298 OpalMCE_ERROR_TYPE_UE = 1, 298 OpalMCE_ERROR_TYPE_UE = 1,
299 OpalMCE_ERROR_TYPE_SLB = 2, 299 OpalMCE_ERROR_TYPE_SLB = 2,
300 OpalMCE_ERROR_TYPE_ERAT = 3, 300 OpalMCE_ERROR_TYPE_ERAT = 3,
301 OpalMCE_ERROR_TYPE_TLB = 4, 301 OpalMCE_ERROR_TYPE_TLB = 4,
302 }; 302 };
303 303
304 enum OpalMCE_UeErrorType { 304 enum OpalMCE_UeErrorType {
305 OpalMCE_UE_ERROR_INDETERMINATE = 0, 305 OpalMCE_UE_ERROR_INDETERMINATE = 0,
306 OpalMCE_UE_ERROR_IFETCH = 1, 306 OpalMCE_UE_ERROR_IFETCH = 1,
307 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2, 307 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
308 OpalMCE_UE_ERROR_LOAD_STORE = 3, 308 OpalMCE_UE_ERROR_LOAD_STORE = 3,
309 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4, 309 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
310 }; 310 };
311 311
312 enum OpalMCE_SlbErrorType { 312 enum OpalMCE_SlbErrorType {
313 OpalMCE_SLB_ERROR_INDETERMINATE = 0, 313 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
314 OpalMCE_SLB_ERROR_PARITY = 1, 314 OpalMCE_SLB_ERROR_PARITY = 1,
315 OpalMCE_SLB_ERROR_MULTIHIT = 2, 315 OpalMCE_SLB_ERROR_MULTIHIT = 2,
316 }; 316 };
317 317
318 enum OpalMCE_EratErrorType { 318 enum OpalMCE_EratErrorType {
319 OpalMCE_ERAT_ERROR_INDETERMINATE = 0, 319 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
320 OpalMCE_ERAT_ERROR_PARITY = 1, 320 OpalMCE_ERAT_ERROR_PARITY = 1,
321 OpalMCE_ERAT_ERROR_MULTIHIT = 2, 321 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
322 }; 322 };
323 323
324 enum OpalMCE_TlbErrorType { 324 enum OpalMCE_TlbErrorType {
325 OpalMCE_TLB_ERROR_INDETERMINATE = 0, 325 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
326 OpalMCE_TLB_ERROR_PARITY = 1, 326 OpalMCE_TLB_ERROR_PARITY = 1,
327 OpalMCE_TLB_ERROR_MULTIHIT = 2, 327 OpalMCE_TLB_ERROR_MULTIHIT = 2,
328 }; 328 };
329 329
330 enum OpalThreadStatus { 330 enum OpalThreadStatus {
331 OPAL_THREAD_INACTIVE = 0x0, 331 OPAL_THREAD_INACTIVE = 0x0,
332 OPAL_THREAD_STARTED = 0x1, 332 OPAL_THREAD_STARTED = 0x1,
333 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 333 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
334 }; 334 };
335 335
336 enum OpalPciBusCompare { 336 enum OpalPciBusCompare {
337 OpalPciBusAny = 0, /* Any bus number match */ 337 OpalPciBusAny = 0, /* Any bus number match */
338 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 338 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
339 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 339 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
340 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 340 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
341 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 341 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
342 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 342 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
343 OpalPciBusAll = 7, /* Match bus number exactly */ 343 OpalPciBusAll = 7, /* Match bus number exactly */
344 }; 344 };
345 345
346 enum OpalDeviceCompare { 346 enum OpalDeviceCompare {
347 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 347 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
348 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 348 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
349 }; 349 };
350 350
351 enum OpalFuncCompare { 351 enum OpalFuncCompare {
352 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 352 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
353 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 353 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
354 }; 354 };
355 355
356 enum OpalPeAction { 356 enum OpalPeAction {
357 OPAL_UNMAP_PE = 0, 357 OPAL_UNMAP_PE = 0,
358 OPAL_MAP_PE = 1 358 OPAL_MAP_PE = 1
359 }; 359 };
360 360
361 enum OpalPeltvAction { 361 enum OpalPeltvAction {
362 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 362 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
363 OPAL_ADD_PE_TO_DOMAIN = 1 363 OPAL_ADD_PE_TO_DOMAIN = 1
364 }; 364 };
365 365
366 enum OpalMveEnableAction { 366 enum OpalMveEnableAction {
367 OPAL_DISABLE_MVE = 0, 367 OPAL_DISABLE_MVE = 0,
368 OPAL_ENABLE_MVE = 1 368 OPAL_ENABLE_MVE = 1
369 }; 369 };
370 370
371 enum OpalPciResetScope { 371 enum OpalPciResetScope {
372 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 372 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
373 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 373 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
374 OPAL_PCI_IODA_TABLE_RESET = 6, 374 OPAL_PCI_IODA_TABLE_RESET = 6,
375 }; 375 };
376 376
377 enum OpalPciReinitScope { 377 enum OpalPciReinitScope {
378 OPAL_REINIT_PCI_DEV = 1000 378 OPAL_REINIT_PCI_DEV = 1000
379 }; 379 };
380 380
381 enum OpalPciResetState { 381 enum OpalPciResetState {
382 OPAL_DEASSERT_RESET = 0, 382 OPAL_DEASSERT_RESET = 0,
383 OPAL_ASSERT_RESET = 1 383 OPAL_ASSERT_RESET = 1
384 }; 384 };
385 385
386 enum OpalPciMaskAction { 386 enum OpalPciMaskAction {
387 OPAL_UNMASK_ERROR_TYPE = 0, 387 OPAL_UNMASK_ERROR_TYPE = 0,
388 OPAL_MASK_ERROR_TYPE = 1 388 OPAL_MASK_ERROR_TYPE = 1
389 }; 389 };
390 390
391 enum OpalSlotLedType { 391 enum OpalSlotLedType {
392 OPAL_SLOT_LED_ID_TYPE = 0, 392 OPAL_SLOT_LED_ID_TYPE = 0,
393 OPAL_SLOT_LED_FAULT_TYPE = 1 393 OPAL_SLOT_LED_FAULT_TYPE = 1
394 }; 394 };
395 395
396 enum OpalLedAction { 396 enum OpalLedAction {
397 OPAL_TURN_OFF_LED = 0, 397 OPAL_TURN_OFF_LED = 0,
398 OPAL_TURN_ON_LED = 1, 398 OPAL_TURN_ON_LED = 1,
399 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2 399 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
400 }; 400 };
401 401
402 enum OpalEpowStatus { 402 enum OpalEpowStatus {
403 OPAL_EPOW_NONE = 0, 403 OPAL_EPOW_NONE = 0,
404 OPAL_EPOW_UPS = 1, 404 OPAL_EPOW_UPS = 1,
405 OPAL_EPOW_OVER_AMBIENT_TEMP = 2, 405 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
406 OPAL_EPOW_OVER_INTERNAL_TEMP = 3 406 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
407 }; 407 };
408 408
409 /* 409 /*
410 * Address cycle types for LPC accesses. These also correspond 410 * Address cycle types for LPC accesses. These also correspond
411 * to the content of the first cell of the "reg" property for 411 * to the content of the first cell of the "reg" property for
412 * device nodes on the LPC bus 412 * device nodes on the LPC bus
413 */ 413 */
414 enum OpalLPCAddressType { 414 enum OpalLPCAddressType {
415 OPAL_LPC_MEM = 0, 415 OPAL_LPC_MEM = 0,
416 OPAL_LPC_IO = 1, 416 OPAL_LPC_IO = 1,
417 OPAL_LPC_FW = 2, 417 OPAL_LPC_FW = 2,
418 }; 418 };
419 419
420 /* System parameter permission */ 420 /* System parameter permission */
421 enum OpalSysparamPerm { 421 enum OpalSysparamPerm {
422 OPAL_SYSPARAM_READ = 0x1, 422 OPAL_SYSPARAM_READ = 0x1,
423 OPAL_SYSPARAM_WRITE = 0x2, 423 OPAL_SYSPARAM_WRITE = 0x2,
424 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 424 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
425 }; 425 };
426 426
427 struct opal_msg { 427 struct opal_msg {
428 __be32 msg_type; 428 __be32 msg_type;
429 __be32 reserved; 429 __be32 reserved;
430 __be64 params[8]; 430 __be64 params[8];
431 }; 431 };
432 432
433 struct opal_machine_check_event { 433 struct opal_machine_check_event {
434 enum OpalMCE_Version version:8; /* 0x00 */ 434 enum OpalMCE_Version version:8; /* 0x00 */
435 uint8_t in_use; /* 0x01 */ 435 uint8_t in_use; /* 0x01 */
436 enum OpalMCE_Severity severity:8; /* 0x02 */ 436 enum OpalMCE_Severity severity:8; /* 0x02 */
437 enum OpalMCE_Initiator initiator:8; /* 0x03 */ 437 enum OpalMCE_Initiator initiator:8; /* 0x03 */
438 enum OpalMCE_ErrorType error_type:8; /* 0x04 */ 438 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
439 enum OpalMCE_Disposition disposition:8; /* 0x05 */ 439 enum OpalMCE_Disposition disposition:8; /* 0x05 */
440 uint8_t reserved_1[2]; /* 0x06 */ 440 uint8_t reserved_1[2]; /* 0x06 */
441 uint64_t gpr3; /* 0x08 */ 441 uint64_t gpr3; /* 0x08 */
442 uint64_t srr0; /* 0x10 */ 442 uint64_t srr0; /* 0x10 */
443 uint64_t srr1; /* 0x18 */ 443 uint64_t srr1; /* 0x18 */
444 union { /* 0x20 */ 444 union { /* 0x20 */
445 struct { 445 struct {
446 enum OpalMCE_UeErrorType ue_error_type:8; 446 enum OpalMCE_UeErrorType ue_error_type:8;
447 uint8_t effective_address_provided; 447 uint8_t effective_address_provided;
448 uint8_t physical_address_provided; 448 uint8_t physical_address_provided;
449 uint8_t reserved_1[5]; 449 uint8_t reserved_1[5];
450 uint64_t effective_address; 450 uint64_t effective_address;
451 uint64_t physical_address; 451 uint64_t physical_address;
452 uint8_t reserved_2[8]; 452 uint8_t reserved_2[8];
453 } ue_error; 453 } ue_error;
454 454
455 struct { 455 struct {
456 enum OpalMCE_SlbErrorType slb_error_type:8; 456 enum OpalMCE_SlbErrorType slb_error_type:8;
457 uint8_t effective_address_provided; 457 uint8_t effective_address_provided;
458 uint8_t reserved_1[6]; 458 uint8_t reserved_1[6];
459 uint64_t effective_address; 459 uint64_t effective_address;
460 uint8_t reserved_2[16]; 460 uint8_t reserved_2[16];
461 } slb_error; 461 } slb_error;
462 462
463 struct { 463 struct {
464 enum OpalMCE_EratErrorType erat_error_type:8; 464 enum OpalMCE_EratErrorType erat_error_type:8;
465 uint8_t effective_address_provided; 465 uint8_t effective_address_provided;
466 uint8_t reserved_1[6]; 466 uint8_t reserved_1[6];
467 uint64_t effective_address; 467 uint64_t effective_address;
468 uint8_t reserved_2[16]; 468 uint8_t reserved_2[16];
469 } erat_error; 469 } erat_error;
470 470
471 struct { 471 struct {
472 enum OpalMCE_TlbErrorType tlb_error_type:8; 472 enum OpalMCE_TlbErrorType tlb_error_type:8;
473 uint8_t effective_address_provided; 473 uint8_t effective_address_provided;
474 uint8_t reserved_1[6]; 474 uint8_t reserved_1[6];
475 uint64_t effective_address; 475 uint64_t effective_address;
476 uint8_t reserved_2[16]; 476 uint8_t reserved_2[16];
477 } tlb_error; 477 } tlb_error;
478 } u; 478 } u;
479 }; 479 };
480 480
481 /* FSP memory errors handling */ 481 /* FSP memory errors handling */
482 enum OpalMemErr_Version { 482 enum OpalMemErr_Version {
483 OpalMemErr_V1 = 1, 483 OpalMemErr_V1 = 1,
484 }; 484 };
485 485
486 enum OpalMemErrType { 486 enum OpalMemErrType {
487 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 487 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
488 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 488 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
489 OPAL_MEM_ERR_TYPE_SCRUB, 489 OPAL_MEM_ERR_TYPE_SCRUB,
490 }; 490 };
491 491
492 /* Memory Reilience error type */ 492 /* Memory Reilience error type */
493 enum OpalMemErr_ResilErrType { 493 enum OpalMemErr_ResilErrType {
494 OPAL_MEM_RESILIENCE_CE = 0, 494 OPAL_MEM_RESILIENCE_CE = 0,
495 OPAL_MEM_RESILIENCE_UE, 495 OPAL_MEM_RESILIENCE_UE,
496 OPAL_MEM_RESILIENCE_UE_SCRUB, 496 OPAL_MEM_RESILIENCE_UE_SCRUB,
497 }; 497 };
498 498
499 /* Dynamic Memory Deallocation type */ 499 /* Dynamic Memory Deallocation type */
500 enum OpalMemErr_DynErrType { 500 enum OpalMemErr_DynErrType {
501 OPAL_MEM_DYNAMIC_DEALLOC = 0, 501 OPAL_MEM_DYNAMIC_DEALLOC = 0,
502 }; 502 };
503 503
504 /* OpalMemoryErrorData->flags */ 504 /* OpalMemoryErrorData->flags */
505 #define OPAL_MEM_CORRECTED_ERROR 0x0001 505 #define OPAL_MEM_CORRECTED_ERROR 0x0001
506 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002 506 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
507 #define OPAL_MEM_ACK_REQUIRED 0x8000 507 #define OPAL_MEM_ACK_REQUIRED 0x8000
508 508
509 struct OpalMemoryErrorData { 509 struct OpalMemoryErrorData {
510 enum OpalMemErr_Version version:8; /* 0x00 */ 510 enum OpalMemErr_Version version:8; /* 0x00 */
511 enum OpalMemErrType type:8; /* 0x01 */ 511 enum OpalMemErrType type:8; /* 0x01 */
512 uint16_t flags; /* 0x02 */ 512 uint16_t flags; /* 0x02 */
513 uint8_t reserved_1[4]; /* 0x04 */ 513 uint8_t reserved_1[4]; /* 0x04 */
514 514
515 union { 515 union {
516 /* Memory Resilience corrected/uncorrected error info */ 516 /* Memory Resilience corrected/uncorrected error info */
517 struct { 517 struct {
518 enum OpalMemErr_ResilErrType resil_err_type:8; 518 enum OpalMemErr_ResilErrType resil_err_type:8;
519 uint8_t reserved_1[7]; 519 uint8_t reserved_1[7];
520 uint64_t physical_address_start; 520 uint64_t physical_address_start;
521 uint64_t physical_address_end; 521 uint64_t physical_address_end;
522 } resilience; 522 } resilience;
523 /* Dynamic memory deallocation error info */ 523 /* Dynamic memory deallocation error info */
524 struct { 524 struct {
525 enum OpalMemErr_DynErrType dyn_err_type:8; 525 enum OpalMemErr_DynErrType dyn_err_type:8;
526 uint8_t reserved_1[7]; 526 uint8_t reserved_1[7];
527 uint64_t physical_address_start; 527 uint64_t physical_address_start;
528 uint64_t physical_address_end; 528 uint64_t physical_address_end;
529 } dyn_dealloc; 529 } dyn_dealloc;
530 } u; 530 } u;
531 }; 531 };
532 532
533 enum { 533 enum {
534 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 534 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
535 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 535 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
536 OPAL_P7IOC_DIAG_TYPE_BI = 2, 536 OPAL_P7IOC_DIAG_TYPE_BI = 2,
537 OPAL_P7IOC_DIAG_TYPE_CI = 3, 537 OPAL_P7IOC_DIAG_TYPE_CI = 3,
538 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 538 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
539 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 539 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
540 OPAL_P7IOC_DIAG_TYPE_LAST = 6 540 OPAL_P7IOC_DIAG_TYPE_LAST = 6
541 }; 541 };
542 542
543 struct OpalIoP7IOCErrorData { 543 struct OpalIoP7IOCErrorData {
544 uint16_t type; 544 uint16_t type;
545 545
546 /* GEM */ 546 /* GEM */
547 uint64_t gemXfir; 547 uint64_t gemXfir;
548 uint64_t gemRfir; 548 uint64_t gemRfir;
549 uint64_t gemRirqfir; 549 uint64_t gemRirqfir;
550 uint64_t gemMask; 550 uint64_t gemMask;
551 uint64_t gemRwof; 551 uint64_t gemRwof;
552 552
553 /* LEM */ 553 /* LEM */
554 uint64_t lemFir; 554 uint64_t lemFir;
555 uint64_t lemErrMask; 555 uint64_t lemErrMask;
556 uint64_t lemAction0; 556 uint64_t lemAction0;
557 uint64_t lemAction1; 557 uint64_t lemAction1;
558 uint64_t lemWof; 558 uint64_t lemWof;
559 559
560 union { 560 union {
561 struct OpalIoP7IOCRgcErrorData { 561 struct OpalIoP7IOCRgcErrorData {
562 uint64_t rgcStatus; /* 3E1C10 */ 562 uint64_t rgcStatus; /* 3E1C10 */
563 uint64_t rgcLdcp; /* 3E1C18 */ 563 uint64_t rgcLdcp; /* 3E1C18 */
564 }rgc; 564 }rgc;
565 struct OpalIoP7IOCBiErrorData { 565 struct OpalIoP7IOCBiErrorData {
566 uint64_t biLdcp0; /* 3C0100, 3C0118 */ 566 uint64_t biLdcp0; /* 3C0100, 3C0118 */
567 uint64_t biLdcp1; /* 3C0108, 3C0120 */ 567 uint64_t biLdcp1; /* 3C0108, 3C0120 */
568 uint64_t biLdcp2; /* 3C0110, 3C0128 */ 568 uint64_t biLdcp2; /* 3C0110, 3C0128 */
569 uint64_t biFenceStatus; /* 3C0130, 3C0130 */ 569 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
570 570
571 uint8_t biDownbound; /* BI Downbound or Upbound */ 571 uint8_t biDownbound; /* BI Downbound or Upbound */
572 }bi; 572 }bi;
573 struct OpalIoP7IOCCiErrorData { 573 struct OpalIoP7IOCCiErrorData {
574 uint64_t ciPortStatus; /* 3Dn008 */ 574 uint64_t ciPortStatus; /* 3Dn008 */
575 uint64_t ciPortLdcp; /* 3Dn010 */ 575 uint64_t ciPortLdcp; /* 3Dn010 */
576 576
577 uint8_t ciPort; /* Index of CI port: 0/1 */ 577 uint8_t ciPort; /* Index of CI port: 0/1 */
578 }ci; 578 }ci;
579 }; 579 };
580 }; 580 };
581 581
582 /** 582 /**
583 * This structure defines the overlay which will be used to store PHB error 583 * This structure defines the overlay which will be used to store PHB error
584 * data upon request. 584 * data upon request.
585 */ 585 */
586 enum { 586 enum {
587 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 587 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
588 }; 588 };
589 589
590 enum { 590 enum {
591 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 591 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
592 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 592 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
593 }; 593 };
594 594
595 enum { 595 enum {
596 OPAL_P7IOC_NUM_PEST_REGS = 128, 596 OPAL_P7IOC_NUM_PEST_REGS = 128,
597 OPAL_PHB3_NUM_PEST_REGS = 256 597 OPAL_PHB3_NUM_PEST_REGS = 256
598 }; 598 };
599 599
600 struct OpalIoPhbErrorCommon { 600 struct OpalIoPhbErrorCommon {
601 uint32_t version; 601 uint32_t version;
602 uint32_t ioType; 602 uint32_t ioType;
603 uint32_t len; 603 uint32_t len;
604 }; 604 };
605 605
606 struct OpalIoP7IOCPhbErrorData { 606 struct OpalIoP7IOCPhbErrorData {
607 struct OpalIoPhbErrorCommon common; 607 struct OpalIoPhbErrorCommon common;
608 608
609 uint32_t brdgCtl; 609 uint32_t brdgCtl;
610 610
611 // P7IOC utl regs 611 // P7IOC utl regs
612 uint32_t portStatusReg; 612 uint32_t portStatusReg;
613 uint32_t rootCmplxStatus; 613 uint32_t rootCmplxStatus;
614 uint32_t busAgentStatus; 614 uint32_t busAgentStatus;
615 615
616 // P7IOC cfg regs 616 // P7IOC cfg regs
617 uint32_t deviceStatus; 617 uint32_t deviceStatus;
618 uint32_t slotStatus; 618 uint32_t slotStatus;
619 uint32_t linkStatus; 619 uint32_t linkStatus;
620 uint32_t devCmdStatus; 620 uint32_t devCmdStatus;
621 uint32_t devSecStatus; 621 uint32_t devSecStatus;
622 622
623 // cfg AER regs 623 // cfg AER regs
624 uint32_t rootErrorStatus; 624 uint32_t rootErrorStatus;
625 uint32_t uncorrErrorStatus; 625 uint32_t uncorrErrorStatus;
626 uint32_t corrErrorStatus; 626 uint32_t corrErrorStatus;
627 uint32_t tlpHdr1; 627 uint32_t tlpHdr1;
628 uint32_t tlpHdr2; 628 uint32_t tlpHdr2;
629 uint32_t tlpHdr3; 629 uint32_t tlpHdr3;
630 uint32_t tlpHdr4; 630 uint32_t tlpHdr4;
631 uint32_t sourceId; 631 uint32_t sourceId;
632 632
633 uint32_t rsv3; 633 uint32_t rsv3;
634 634
635 // Record data about the call to allocate a buffer. 635 // Record data about the call to allocate a buffer.
636 uint64_t errorClass; 636 uint64_t errorClass;
637 uint64_t correlator; 637 uint64_t correlator;
638 638
639 //P7IOC MMIO Error Regs 639 //P7IOC MMIO Error Regs
640 uint64_t p7iocPlssr; // n120 640 uint64_t p7iocPlssr; // n120
641 uint64_t p7iocCsr; // n110 641 uint64_t p7iocCsr; // n110
642 uint64_t lemFir; // nC00 642 uint64_t lemFir; // nC00
643 uint64_t lemErrorMask; // nC18 643 uint64_t lemErrorMask; // nC18
644 uint64_t lemWOF; // nC40 644 uint64_t lemWOF; // nC40
645 uint64_t phbErrorStatus; // nC80 645 uint64_t phbErrorStatus; // nC80
646 uint64_t phbFirstErrorStatus; // nC88 646 uint64_t phbFirstErrorStatus; // nC88
647 uint64_t phbErrorLog0; // nCC0 647 uint64_t phbErrorLog0; // nCC0
648 uint64_t phbErrorLog1; // nCC8 648 uint64_t phbErrorLog1; // nCC8
649 uint64_t mmioErrorStatus; // nD00 649 uint64_t mmioErrorStatus; // nD00
650 uint64_t mmioFirstErrorStatus; // nD08 650 uint64_t mmioFirstErrorStatus; // nD08
651 uint64_t mmioErrorLog0; // nD40 651 uint64_t mmioErrorLog0; // nD40
652 uint64_t mmioErrorLog1; // nD48 652 uint64_t mmioErrorLog1; // nD48
653 uint64_t dma0ErrorStatus; // nD80 653 uint64_t dma0ErrorStatus; // nD80
654 uint64_t dma0FirstErrorStatus; // nD88 654 uint64_t dma0FirstErrorStatus; // nD88
655 uint64_t dma0ErrorLog0; // nDC0 655 uint64_t dma0ErrorLog0; // nDC0
656 uint64_t dma0ErrorLog1; // nDC8 656 uint64_t dma0ErrorLog1; // nDC8
657 uint64_t dma1ErrorStatus; // nE00 657 uint64_t dma1ErrorStatus; // nE00
658 uint64_t dma1FirstErrorStatus; // nE08 658 uint64_t dma1FirstErrorStatus; // nE08
659 uint64_t dma1ErrorLog0; // nE40 659 uint64_t dma1ErrorLog0; // nE40
660 uint64_t dma1ErrorLog1; // nE48 660 uint64_t dma1ErrorLog1; // nE48
661 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS]; 661 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
662 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS]; 662 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
663 }; 663 };
664 664
665 struct OpalIoPhb3ErrorData { 665 struct OpalIoPhb3ErrorData {
666 struct OpalIoPhbErrorCommon common; 666 struct OpalIoPhbErrorCommon common;
667 667
668 uint32_t brdgCtl; 668 uint32_t brdgCtl;
669 669
670 /* PHB3 UTL regs */ 670 /* PHB3 UTL regs */
671 uint32_t portStatusReg; 671 uint32_t portStatusReg;
672 uint32_t rootCmplxStatus; 672 uint32_t rootCmplxStatus;
673 uint32_t busAgentStatus; 673 uint32_t busAgentStatus;
674 674
675 /* PHB3 cfg regs */ 675 /* PHB3 cfg regs */
676 uint32_t deviceStatus; 676 uint32_t deviceStatus;
677 uint32_t slotStatus; 677 uint32_t slotStatus;
678 uint32_t linkStatus; 678 uint32_t linkStatus;
679 uint32_t devCmdStatus; 679 uint32_t devCmdStatus;
680 uint32_t devSecStatus; 680 uint32_t devSecStatus;
681 681
682 /* cfg AER regs */ 682 /* cfg AER regs */
683 uint32_t rootErrorStatus; 683 uint32_t rootErrorStatus;
684 uint32_t uncorrErrorStatus; 684 uint32_t uncorrErrorStatus;
685 uint32_t corrErrorStatus; 685 uint32_t corrErrorStatus;
686 uint32_t tlpHdr1; 686 uint32_t tlpHdr1;
687 uint32_t tlpHdr2; 687 uint32_t tlpHdr2;
688 uint32_t tlpHdr3; 688 uint32_t tlpHdr3;
689 uint32_t tlpHdr4; 689 uint32_t tlpHdr4;
690 uint32_t sourceId; 690 uint32_t sourceId;
691 691
692 uint32_t rsv3; 692 uint32_t rsv3;
693 693
694 /* Record data about the call to allocate a buffer */ 694 /* Record data about the call to allocate a buffer */
695 uint64_t errorClass; 695 uint64_t errorClass;
696 uint64_t correlator; 696 uint64_t correlator;
697 697
698 uint64_t nFir; /* 000 */ 698 uint64_t nFir; /* 000 */
699 uint64_t nFirMask; /* 003 */ 699 uint64_t nFirMask; /* 003 */
700 uint64_t nFirWOF; /* 008 */ 700 uint64_t nFirWOF; /* 008 */
701 701
702 /* PHB3 MMIO Error Regs */ 702 /* PHB3 MMIO Error Regs */
703 uint64_t phbPlssr; /* 120 */ 703 uint64_t phbPlssr; /* 120 */
704 uint64_t phbCsr; /* 110 */ 704 uint64_t phbCsr; /* 110 */
705 uint64_t lemFir; /* C00 */ 705 uint64_t lemFir; /* C00 */
706 uint64_t lemErrorMask; /* C18 */ 706 uint64_t lemErrorMask; /* C18 */
707 uint64_t lemWOF; /* C40 */ 707 uint64_t lemWOF; /* C40 */
708 uint64_t phbErrorStatus; /* C80 */ 708 uint64_t phbErrorStatus; /* C80 */
709 uint64_t phbFirstErrorStatus; /* C88 */ 709 uint64_t phbFirstErrorStatus; /* C88 */
710 uint64_t phbErrorLog0; /* CC0 */ 710 uint64_t phbErrorLog0; /* CC0 */
711 uint64_t phbErrorLog1; /* CC8 */ 711 uint64_t phbErrorLog1; /* CC8 */
712 uint64_t mmioErrorStatus; /* D00 */ 712 uint64_t mmioErrorStatus; /* D00 */
713 uint64_t mmioFirstErrorStatus; /* D08 */ 713 uint64_t mmioFirstErrorStatus; /* D08 */
714 uint64_t mmioErrorLog0; /* D40 */ 714 uint64_t mmioErrorLog0; /* D40 */
715 uint64_t mmioErrorLog1; /* D48 */ 715 uint64_t mmioErrorLog1; /* D48 */
716 uint64_t dma0ErrorStatus; /* D80 */ 716 uint64_t dma0ErrorStatus; /* D80 */
717 uint64_t dma0FirstErrorStatus; /* D88 */ 717 uint64_t dma0FirstErrorStatus; /* D88 */
718 uint64_t dma0ErrorLog0; /* DC0 */ 718 uint64_t dma0ErrorLog0; /* DC0 */
719 uint64_t dma0ErrorLog1; /* DC8 */ 719 uint64_t dma0ErrorLog1; /* DC8 */
720 uint64_t dma1ErrorStatus; /* E00 */ 720 uint64_t dma1ErrorStatus; /* E00 */
721 uint64_t dma1FirstErrorStatus; /* E08 */ 721 uint64_t dma1FirstErrorStatus; /* E08 */
722 uint64_t dma1ErrorLog0; /* E40 */ 722 uint64_t dma1ErrorLog0; /* E40 */
723 uint64_t dma1ErrorLog1; /* E48 */ 723 uint64_t dma1ErrorLog1; /* E48 */
724 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS]; 724 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
725 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS]; 725 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
726 }; 726 };
727 727
728 typedef struct oppanel_line { 728 typedef struct oppanel_line {
729 const char * line; 729 const char * line;
730 uint64_t line_len; 730 uint64_t line_len;
731 } oppanel_line_t; 731 } oppanel_line_t;
732 732
733 /* /sys/firmware/opal */ 733 /* /sys/firmware/opal */
734 extern struct kobject *opal_kobj; 734 extern struct kobject *opal_kobj;
735 735
736 /* /ibm,opal */ 736 /* /ibm,opal */
737 extern struct device_node *opal_node; 737 extern struct device_node *opal_node;
738 738
739 /* API functions */ 739 /* API functions */
740 int64_t opal_invalid_call(void); 740 int64_t opal_invalid_call(void);
741 int64_t opal_console_write(int64_t term_number, __be64 *length, 741 int64_t opal_console_write(int64_t term_number, __be64 *length,
742 const uint8_t *buffer); 742 const uint8_t *buffer);
743 int64_t opal_console_read(int64_t term_number, __be64 *length, 743 int64_t opal_console_read(int64_t term_number, __be64 *length,
744 uint8_t *buffer); 744 uint8_t *buffer);
745 int64_t opal_console_write_buffer_space(int64_t term_number, 745 int64_t opal_console_write_buffer_space(int64_t term_number,
746 __be64 *length); 746 __be64 *length);
747 int64_t opal_rtc_read(__be32 *year_month_day, 747 int64_t opal_rtc_read(__be32 *year_month_day,
748 __be64 *hour_minute_second_millisecond); 748 __be64 *hour_minute_second_millisecond);
749 int64_t opal_rtc_write(uint32_t year_month_day, 749 int64_t opal_rtc_write(uint32_t year_month_day,
750 uint64_t hour_minute_second_millisecond); 750 uint64_t hour_minute_second_millisecond);
751 int64_t opal_cec_power_down(uint64_t request); 751 int64_t opal_cec_power_down(uint64_t request);
752 int64_t opal_cec_reboot(void); 752 int64_t opal_cec_reboot(void);
753 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 753 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
754 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 754 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
755 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); 755 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
756 int64_t opal_poll_events(__be64 *outstanding_event_mask); 756 int64_t opal_poll_events(__be64 *outstanding_event_mask);
757 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, 757 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
758 uint64_t tce_mem_size); 758 uint64_t tce_mem_size);
759 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, 759 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
760 uint64_t tce_mem_size); 760 uint64_t tce_mem_size);
761 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, 761 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
762 uint64_t offset, uint8_t *data); 762 uint64_t offset, uint8_t *data);
763 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, 763 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
764 uint64_t offset, __be16 *data); 764 uint64_t offset, __be16 *data);
765 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, 765 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
766 uint64_t offset, __be32 *data); 766 uint64_t offset, __be32 *data);
767 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, 767 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
768 uint64_t offset, uint8_t data); 768 uint64_t offset, uint8_t data);
769 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, 769 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
770 uint64_t offset, uint16_t data); 770 uint64_t offset, uint16_t data);
771 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, 771 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
772 uint64_t offset, uint32_t data); 772 uint64_t offset, uint32_t data);
773 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 773 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
774 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); 774 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
775 int64_t opal_register_exception_handler(uint64_t opal_exception, 775 int64_t opal_register_exception_handler(uint64_t opal_exception,
776 uint64_t handler_address, 776 uint64_t handler_address,
777 uint64_t glue_cache_line); 777 uint64_t glue_cache_line);
778 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, 778 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
779 uint8_t *freeze_state, 779 uint8_t *freeze_state,
780 __be16 *pci_error_type, 780 __be16 *pci_error_type,
781 __be64 *phb_status); 781 __be64 *phb_status);
782 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, 782 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
783 uint64_t eeh_action_token); 783 uint64_t eeh_action_token);
784 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); 784 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
785 785
786 786
787 787
788 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, 788 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
789 uint16_t window_num, uint16_t enable); 789 uint16_t window_num, uint16_t enable);
790 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, 790 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
791 uint16_t window_num, 791 uint16_t window_num,
792 uint64_t starting_real_address, 792 uint64_t starting_real_address,
793 uint64_t starting_pci_address, 793 uint64_t starting_pci_address,
794 uint16_t segment_size); 794 uint16_t segment_size);
795 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, 795 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
796 uint16_t window_type, uint16_t window_num, 796 uint16_t window_type, uint16_t window_num,
797 uint16_t segment_num); 797 uint16_t segment_num);
798 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, 798 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
799 uint64_t ivt_addr, uint64_t ivt_len, 799 uint64_t ivt_addr, uint64_t ivt_len,
800 uint64_t reject_array_addr, 800 uint64_t reject_array_addr,
801 uint64_t peltv_addr); 801 uint64_t peltv_addr);
802 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, 802 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
803 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, 803 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
804 uint8_t pe_action); 804 uint8_t pe_action);
805 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, 805 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
806 uint8_t state); 806 uint8_t state);
807 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); 807 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
808 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, 808 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
809 uint32_t state); 809 uint32_t state);
810 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, 810 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
811 uint8_t *p_bit, uint8_t *q_bit); 811 uint8_t *p_bit, uint8_t *q_bit);
812 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 812 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
813 uint8_t p_bit, uint8_t q_bit); 813 uint8_t p_bit, uint8_t q_bit);
814 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); 814 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
815 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 815 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
816 uint32_t xive_num); 816 uint32_t xive_num);
817 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 817 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
818 __be32 *interrupt_source_number); 818 __be32 *interrupt_source_number);
819 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, 819 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
820 uint8_t msi_range, __be32 *msi_address, 820 uint8_t msi_range, __be32 *msi_address,
821 __be32 *message_data); 821 __be32 *message_data);
822 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, 822 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
823 uint32_t xive_num, uint8_t msi_range, 823 uint32_t xive_num, uint8_t msi_range,
824 __be64 *msi_address, __be32 *message_data); 824 __be64 *msi_address, __be32 *message_data);
825 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); 825 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
826 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); 826 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
827 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); 827 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
828 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, 828 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
829 uint16_t tce_levels, uint64_t tce_table_addr, 829 uint16_t tce_levels, uint64_t tce_table_addr,
830 uint64_t tce_table_size, uint64_t tce_page_size); 830 uint64_t tce_table_size, uint64_t tce_page_size);
831 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, 831 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
832 uint16_t dma_window_number, uint64_t pci_start_addr, 832 uint16_t dma_window_number, uint64_t pci_start_addr,
833 uint64_t pci_mem_size); 833 uint64_t pci_mem_size);
834 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 834 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
835 835
836 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, 836 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
837 uint64_t diag_buffer_len); 837 uint64_t diag_buffer_len);
838 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, 838 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
839 uint64_t diag_buffer_len); 839 uint64_t diag_buffer_len);
840 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 840 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
841 uint64_t diag_buffer_len); 841 uint64_t diag_buffer_len);
842 int64_t opal_pci_fence_phb(uint64_t phb_id); 842 int64_t opal_pci_fence_phb(uint64_t phb_id);
843 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data); 843 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
844 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 844 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
845 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 845 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
846 int64_t opal_get_epow_status(__be64 *status); 846 int64_t opal_get_epow_status(__be64 *status);
847 int64_t opal_set_system_attention_led(uint8_t led_action); 847 int64_t opal_set_system_attention_led(uint8_t led_action);
848 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, 848 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
849 uint16_t *pci_error_type, uint16_t *severity); 849 uint16_t *pci_error_type, uint16_t *severity);
850 int64_t opal_pci_poll(uint64_t phb_id); 850 int64_t opal_pci_poll(uint64_t phb_id);
851 int64_t opal_return_cpu(void); 851 int64_t opal_return_cpu(void);
852 852
853 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); 853 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
854 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); 854 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
855 855
856 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 856 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
857 uint32_t addr, uint32_t data, uint32_t sz); 857 uint32_t addr, uint32_t data, uint32_t sz);
858 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, 858 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
859 uint32_t addr, __be32 *data, uint32_t sz); 859 uint32_t addr, __be32 *data, uint32_t sz);
860 860
861 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id); 861 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
862 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type); 862 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
863 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset); 863 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
864 int64_t opal_send_ack_elog(uint64_t log_id); 864 int64_t opal_send_ack_elog(uint64_t log_id);
865 void opal_resend_pending_logs(void); 865 void opal_resend_pending_logs(void);
866 866
867 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); 867 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
868 int64_t opal_manage_flash(uint8_t op); 868 int64_t opal_manage_flash(uint8_t op);
869 int64_t opal_update_flash(uint64_t blk_list); 869 int64_t opal_update_flash(uint64_t blk_list);
870 int64_t opal_dump_init(uint8_t dump_type); 870 int64_t opal_dump_init(uint8_t dump_type);
871 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size); 871 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
872 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type); 872 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
873 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); 873 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
874 int64_t opal_dump_ack(uint32_t dump_id); 874 int64_t opal_dump_ack(uint32_t dump_id);
875 int64_t opal_dump_resend_notification(void); 875 int64_t opal_dump_resend_notification(void);
876 876
877 int64_t opal_get_msg(uint64_t buffer, uint64_t size); 877 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
878 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token); 878 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
879 int64_t opal_sync_host_reboot(void); 879 int64_t opal_sync_host_reboot(void);
880 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, 880 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
881 uint64_t length); 881 uint64_t length);
882 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, 882 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
883 uint64_t length); 883 uint64_t length);
884 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); 884 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
885 885
886 /* Internal functions */ 886 /* Internal functions */
887 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 887 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
888 int depth, void *data); 888 int depth, void *data);
889 extern int early_init_dt_scan_recoverable_ranges(unsigned long node, 889 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
890 const char *uname, int depth, void *data); 890 const char *uname, int depth, void *data);
891 891
892 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 892 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
893 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 893 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
894 894
895 extern void hvc_opal_init_early(void); 895 extern void hvc_opal_init_early(void);
896 896
897 extern int opal_notifier_register(struct notifier_block *nb); 897 extern int opal_notifier_register(struct notifier_block *nb);
898 extern int opal_notifier_unregister(struct notifier_block *nb); 898 extern int opal_notifier_unregister(struct notifier_block *nb);
899 899
900 extern int opal_message_notifier_register(enum OpalMessageType msg_type, 900 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
901 struct notifier_block *nb); 901 struct notifier_block *nb);
902 extern void opal_notifier_enable(void); 902 extern void opal_notifier_enable(void);
903 extern void opal_notifier_disable(void); 903 extern void opal_notifier_disable(void);
904 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 904 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
905 905
906 extern int __opal_async_get_token(void); 906 extern int __opal_async_get_token(void);
907 extern int opal_async_get_token_interruptible(void); 907 extern int opal_async_get_token_interruptible(void);
908 extern int __opal_async_release_token(int token); 908 extern int __opal_async_release_token(int token);
909 extern int opal_async_release_token(int token); 909 extern int opal_async_release_token(int token);
910 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg); 910 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
911 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data); 911 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
912 912
913 struct rtc_time; 913 struct rtc_time;
914 extern int opal_set_rtc_time(struct rtc_time *tm); 914 extern int opal_set_rtc_time(struct rtc_time *tm);
915 extern void opal_get_rtc_time(struct rtc_time *tm); 915 extern void opal_get_rtc_time(struct rtc_time *tm);
916 extern unsigned long opal_get_boot_time(void); 916 extern unsigned long opal_get_boot_time(void);
917 extern void opal_nvram_init(void); 917 extern void opal_nvram_init(void);
918 extern void opal_flash_init(void); 918 extern void opal_flash_init(void);
919 extern void opal_flash_term_callback(void);
919 extern int opal_elog_init(void); 920 extern int opal_elog_init(void);
920 extern void opal_platform_dump_init(void); 921 extern void opal_platform_dump_init(void);
921 extern void opal_sys_param_init(void); 922 extern void opal_sys_param_init(void);
922 extern void opal_msglog_init(void); 923 extern void opal_msglog_init(void);
923 924
924 extern int opal_machine_check(struct pt_regs *regs); 925 extern int opal_machine_check(struct pt_regs *regs);
925 extern bool opal_mce_check_early_recovery(struct pt_regs *regs); 926 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
926 927
927 extern void opal_shutdown(void); 928 extern void opal_shutdown(void);
928 extern int opal_resync_timebase(void); 929 extern int opal_resync_timebase(void);
929 930
930 extern void opal_lpc_init(void); 931 extern void opal_lpc_init(void);
931 932
932 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, 933 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
933 unsigned long vmalloc_size); 934 unsigned long vmalloc_size);
934 void opal_free_sg_list(struct opal_sg_list *sg); 935 void opal_free_sg_list(struct opal_sg_list *sg);
935 936
936 #endif /* __ASSEMBLY__ */ 937 #endif /* __ASSEMBLY__ */
937 938
938 #endif /* __OPAL_H */ 939 #endif /* __OPAL_H */
939 940
arch/powerpc/platforms/powernv/opal-flash.c
Diff comments   View file @ 2196c6f
1 /* 1 /*
2 * PowerNV OPAL Firmware Update Interface 2 * PowerNV OPAL Firmware Update Interface
3 * 3 *
4 * Copyright 2013 IBM Corp. 4 * Copyright 2013 IBM Corp.
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12 #define DEBUG 12 #define DEBUG
13 13
14 #include <linux/kernel.h> 14 #include <linux/kernel.h>
15 #include <linux/reboot.h> 15 #include <linux/reboot.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/kobject.h> 17 #include <linux/kobject.h>
18 #include <linux/sysfs.h> 18 #include <linux/sysfs.h>
19 #include <linux/slab.h> 19 #include <linux/slab.h>
20 #include <linux/mm.h> 20 #include <linux/mm.h>
21 #include <linux/vmalloc.h> 21 #include <linux/vmalloc.h>
22 #include <linux/pagemap.h> 22 #include <linux/pagemap.h>
23 #include <linux/delay.h>
23 24
24 #include <asm/opal.h> 25 #include <asm/opal.h>
25 26
26 /* FLASH status codes */ 27 /* FLASH status codes */
27 #define FLASH_NO_OP -1099 /* No operation initiated by user */ 28 #define FLASH_NO_OP -1099 /* No operation initiated by user */
28 #define FLASH_NO_AUTH -9002 /* Not a service authority partition */ 29 #define FLASH_NO_AUTH -9002 /* Not a service authority partition */
29 30
30 /* Validate image status values */ 31 /* Validate image status values */
31 #define VALIDATE_IMG_READY -1001 /* Image ready for validation */ 32 #define VALIDATE_IMG_READY -1001 /* Image ready for validation */
32 #define VALIDATE_IMG_INCOMPLETE -1002 /* User copied < VALIDATE_BUF_SIZE */ 33 #define VALIDATE_IMG_INCOMPLETE -1002 /* User copied < VALIDATE_BUF_SIZE */
33 34
34 /* Manage image status values */ 35 /* Manage image status values */
35 #define MANAGE_ACTIVE_ERR -9001 /* Cannot overwrite active img */ 36 #define MANAGE_ACTIVE_ERR -9001 /* Cannot overwrite active img */
36 37
37 /* Flash image status values */ 38 /* Flash image status values */
38 #define FLASH_IMG_READY 0 /* Img ready for flash on reboot */ 39 #define FLASH_IMG_READY 0 /* Img ready for flash on reboot */
39 #define FLASH_INVALID_IMG -1003 /* Flash image shorter than expected */ 40 #define FLASH_INVALID_IMG -1003 /* Flash image shorter than expected */
40 #define FLASH_IMG_NULL_DATA -1004 /* Bad data in sg list entry */ 41 #define FLASH_IMG_NULL_DATA -1004 /* Bad data in sg list entry */
41 #define FLASH_IMG_BAD_LEN -1005 /* Bad length in sg list entry */ 42 #define FLASH_IMG_BAD_LEN -1005 /* Bad length in sg list entry */
42 43
43 /* Manage operation tokens */ 44 /* Manage operation tokens */
44 #define FLASH_REJECT_TMP_SIDE 0 /* Reject temporary fw image */ 45 #define FLASH_REJECT_TMP_SIDE 0 /* Reject temporary fw image */
45 #define FLASH_COMMIT_TMP_SIDE 1 /* Commit temporary fw image */ 46 #define FLASH_COMMIT_TMP_SIDE 1 /* Commit temporary fw image */
46 47
47 /* Update tokens */ 48 /* Update tokens */
48 #define FLASH_UPDATE_CANCEL 0 /* Cancel update request */ 49 #define FLASH_UPDATE_CANCEL 0 /* Cancel update request */
49 #define FLASH_UPDATE_INIT 1 /* Initiate update */ 50 #define FLASH_UPDATE_INIT 1 /* Initiate update */
50 51
51 /* Validate image update result tokens */ 52 /* Validate image update result tokens */
52 #define VALIDATE_TMP_UPDATE 0 /* T side will be updated */ 53 #define VALIDATE_TMP_UPDATE 0 /* T side will be updated */
53 #define VALIDATE_FLASH_AUTH 1 /* Partition does not have authority */ 54 #define VALIDATE_FLASH_AUTH 1 /* Partition does not have authority */
54 #define VALIDATE_INVALID_IMG 2 /* Candidate image is not valid */ 55 #define VALIDATE_INVALID_IMG 2 /* Candidate image is not valid */
55 #define VALIDATE_CUR_UNKNOWN 3 /* Current fixpack level is unknown */ 56 #define VALIDATE_CUR_UNKNOWN 3 /* Current fixpack level is unknown */
56 /* 57 /*
57 * Current T side will be committed to P side before being replace with new 58 * Current T side will be committed to P side before being replace with new
58 * image, and the new image is downlevel from current image 59 * image, and the new image is downlevel from current image
59 */ 60 */
60 #define VALIDATE_TMP_COMMIT_DL 4 61 #define VALIDATE_TMP_COMMIT_DL 4
61 /* 62 /*
62 * Current T side will be committed to P side before being replaced with new 63 * Current T side will be committed to P side before being replaced with new
63 * image 64 * image
64 */ 65 */
65 #define VALIDATE_TMP_COMMIT 5 66 #define VALIDATE_TMP_COMMIT 5
66 /* 67 /*
67 * T side will be updated with a downlevel image 68 * T side will be updated with a downlevel image
68 */ 69 */
69 #define VALIDATE_TMP_UPDATE_DL 6 70 #define VALIDATE_TMP_UPDATE_DL 6
70 /* 71 /*
71 * The candidate image's release date is later than the system's firmware 72 * The candidate image's release date is later than the system's firmware
72 * service entitlement date - service warranty period has expired 73 * service entitlement date - service warranty period has expired
73 */ 74 */
74 #define VALIDATE_OUT_OF_WRNTY 7 75 #define VALIDATE_OUT_OF_WRNTY 7
75 76
76 /* Validate buffer size */ 77 /* Validate buffer size */
77 #define VALIDATE_BUF_SIZE 4096 78 #define VALIDATE_BUF_SIZE 4096
78 79
79 /* XXX: Assume candidate image size is <= 1GB */ 80 /* XXX: Assume candidate image size is <= 1GB */
80 #define MAX_IMAGE_SIZE 0x40000000 81 #define MAX_IMAGE_SIZE 0x40000000
81 82
82 /* Image status */ 83 /* Image status */
83 enum { 84 enum {
84 IMAGE_INVALID, 85 IMAGE_INVALID,
85 IMAGE_LOADING, 86 IMAGE_LOADING,
86 IMAGE_READY, 87 IMAGE_READY,
87 }; 88 };
88 89
89 /* Candidate image data */ 90 /* Candidate image data */
90 struct image_data_t { 91 struct image_data_t {
91 int status; 92 int status;
92 void *data; 93 void *data;
93 uint32_t size; 94 uint32_t size;
94 }; 95 };
95 96
96 /* Candidate image header */ 97 /* Candidate image header */
97 struct image_header_t { 98 struct image_header_t {
98 uint16_t magic; 99 uint16_t magic;
99 uint16_t version; 100 uint16_t version;
100 uint32_t size; 101 uint32_t size;
101 }; 102 };
102 103
103 struct validate_flash_t { 104 struct validate_flash_t {
104 int status; /* Return status */ 105 int status; /* Return status */
105 void *buf; /* Candidate image buffer */ 106 void *buf; /* Candidate image buffer */
106 uint32_t buf_size; /* Image size */ 107 uint32_t buf_size; /* Image size */
107 uint32_t result; /* Update results token */ 108 uint32_t result; /* Update results token */
108 }; 109 };
109 110
110 struct manage_flash_t { 111 struct manage_flash_t {
111 int status; /* Return status */ 112 int status; /* Return status */
112 }; 113 };
113 114
114 struct update_flash_t { 115 struct update_flash_t {
115 int status; /* Return status */ 116 int status; /* Return status */
116 }; 117 };
117 118
118 static struct image_header_t image_header; 119 static struct image_header_t image_header;
119 static struct image_data_t image_data; 120 static struct image_data_t image_data;
120 static struct validate_flash_t validate_flash_data; 121 static struct validate_flash_t validate_flash_data;
121 static struct manage_flash_t manage_flash_data; 122 static struct manage_flash_t manage_flash_data;
122 static struct update_flash_t update_flash_data; 123 static struct update_flash_t update_flash_data;
123 124
124 static DEFINE_MUTEX(image_data_mutex); 125 static DEFINE_MUTEX(image_data_mutex);
125 126
126 /* 127 /*
127 * Validate candidate image 128 * Validate candidate image
128 */ 129 */
129 static inline void opal_flash_validate(void) 130 static inline void opal_flash_validate(void)
130 { 131 {
131 long ret; 132 long ret;
132 void *buf = validate_flash_data.buf; 133 void *buf = validate_flash_data.buf;
133 __be32 size, result; 134 __be32 size, result;
134 135
135 ret = opal_validate_flash(__pa(buf), &size, &result); 136 ret = opal_validate_flash(__pa(buf), &size, &result);
136 137
137 validate_flash_data.status = ret; 138 validate_flash_data.status = ret;
138 validate_flash_data.buf_size = be32_to_cpu(size); 139 validate_flash_data.buf_size = be32_to_cpu(size);
139 validate_flash_data.result = be32_to_cpu(result); 140 validate_flash_data.result = be32_to_cpu(result);
140 } 141 }
141 142
142 /* 143 /*
143 * Validate output format: 144 * Validate output format:
144 * validate result token 145 * validate result token
145 * current image version details 146 * current image version details
146 * new image version details 147 * new image version details
147 */ 148 */
148 static ssize_t validate_show(struct kobject *kobj, 149 static ssize_t validate_show(struct kobject *kobj,
149 struct kobj_attribute *attr, char *buf) 150 struct kobj_attribute *attr, char *buf)
150 { 151 {
151 struct validate_flash_t *args_buf = &validate_flash_data; 152 struct validate_flash_t *args_buf = &validate_flash_data;
152 int len; 153 int len;
153 154
154 /* Candidate image is not validated */ 155 /* Candidate image is not validated */
155 if (args_buf->status < VALIDATE_TMP_UPDATE) { 156 if (args_buf->status < VALIDATE_TMP_UPDATE) {
156 len = sprintf(buf, "%d\n", args_buf->status); 157 len = sprintf(buf, "%d\n", args_buf->status);
157 goto out; 158 goto out;
158 } 159 }
159 160
160 /* Result token */ 161 /* Result token */
161 len = sprintf(buf, "%d\n", args_buf->result); 162 len = sprintf(buf, "%d\n", args_buf->result);
162 163
163 /* Current and candidate image version details */ 164 /* Current and candidate image version details */
164 if ((args_buf->result != VALIDATE_TMP_UPDATE) && 165 if ((args_buf->result != VALIDATE_TMP_UPDATE) &&
165 (args_buf->result < VALIDATE_CUR_UNKNOWN)) 166 (args_buf->result < VALIDATE_CUR_UNKNOWN))
166 goto out; 167 goto out;
167 168
168 if (args_buf->buf_size > (VALIDATE_BUF_SIZE - len)) { 169 if (args_buf->buf_size > (VALIDATE_BUF_SIZE - len)) {
169 memcpy(buf + len, args_buf->buf, VALIDATE_BUF_SIZE - len); 170 memcpy(buf + len, args_buf->buf, VALIDATE_BUF_SIZE - len);
170 len = VALIDATE_BUF_SIZE; 171 len = VALIDATE_BUF_SIZE;
171 } else { 172 } else {
172 memcpy(buf + len, args_buf->buf, args_buf->buf_size); 173 memcpy(buf + len, args_buf->buf, args_buf->buf_size);
173 len += args_buf->buf_size; 174 len += args_buf->buf_size;
174 } 175 }
175 out: 176 out:
176 /* Set status to default */ 177 /* Set status to default */
177 args_buf->status = FLASH_NO_OP; 178 args_buf->status = FLASH_NO_OP;
178 return len; 179 return len;
179 } 180 }
180 181
181 /* 182 /*
182 * Validate candidate firmware image 183 * Validate candidate firmware image
183 * 184 *
184 * Note: 185 * Note:
185 * We are only interested in first 4K bytes of the 186 * We are only interested in first 4K bytes of the
186 * candidate image. 187 * candidate image.
187 */ 188 */
188 static ssize_t validate_store(struct kobject *kobj, 189 static ssize_t validate_store(struct kobject *kobj,
189 struct kobj_attribute *attr, 190 struct kobj_attribute *attr,
190 const char *buf, size_t count) 191 const char *buf, size_t count)
191 { 192 {
192 struct validate_flash_t *args_buf = &validate_flash_data; 193 struct validate_flash_t *args_buf = &validate_flash_data;
193 194
194 if (buf[0] != '1') 195 if (buf[0] != '1')
195 return -EINVAL; 196 return -EINVAL;
196 197
197 mutex_lock(&image_data_mutex); 198 mutex_lock(&image_data_mutex);
198 199
199 if (image_data.status != IMAGE_READY || 200 if (image_data.status != IMAGE_READY ||
200 image_data.size < VALIDATE_BUF_SIZE) { 201 image_data.size < VALIDATE_BUF_SIZE) {
201 args_buf->result = VALIDATE_INVALID_IMG; 202 args_buf->result = VALIDATE_INVALID_IMG;
202 args_buf->status = VALIDATE_IMG_INCOMPLETE; 203 args_buf->status = VALIDATE_IMG_INCOMPLETE;
203 goto out; 204 goto out;
204 } 205 }
205 206
206 /* Copy first 4k bytes of candidate image */ 207 /* Copy first 4k bytes of candidate image */
207 memcpy(args_buf->buf, image_data.data, VALIDATE_BUF_SIZE); 208 memcpy(args_buf->buf, image_data.data, VALIDATE_BUF_SIZE);
208 209
209 args_buf->status = VALIDATE_IMG_READY; 210 args_buf->status = VALIDATE_IMG_READY;
210 args_buf->buf_size = VALIDATE_BUF_SIZE; 211 args_buf->buf_size = VALIDATE_BUF_SIZE;
211 212
212 /* Validate candidate image */ 213 /* Validate candidate image */
213 opal_flash_validate(); 214 opal_flash_validate();
214 215
215 out: 216 out:
216 mutex_unlock(&image_data_mutex); 217 mutex_unlock(&image_data_mutex);
217 return count; 218 return count;
218 } 219 }
219 220
220 /* 221 /*
221 * Manage flash routine 222 * Manage flash routine
222 */ 223 */
223 static inline void opal_flash_manage(uint8_t op) 224 static inline void opal_flash_manage(uint8_t op)
224 { 225 {
225 struct manage_flash_t *const args_buf = &manage_flash_data; 226 struct manage_flash_t *const args_buf = &manage_flash_data;
226 227
227 args_buf->status = opal_manage_flash(op); 228 args_buf->status = opal_manage_flash(op);
228 } 229 }
229 230
230 /* 231 /*
231 * Show manage flash status 232 * Show manage flash status
232 */ 233 */
233 static ssize_t manage_show(struct kobject *kobj, 234 static ssize_t manage_show(struct kobject *kobj,
234 struct kobj_attribute *attr, char *buf) 235 struct kobj_attribute *attr, char *buf)
235 { 236 {
236 struct manage_flash_t *const args_buf = &manage_flash_data; 237 struct manage_flash_t *const args_buf = &manage_flash_data;
237 int rc; 238 int rc;
238 239
239 rc = sprintf(buf, "%d\n", args_buf->status); 240 rc = sprintf(buf, "%d\n", args_buf->status);
240 /* Set status to default*/ 241 /* Set status to default*/
241 args_buf->status = FLASH_NO_OP; 242 args_buf->status = FLASH_NO_OP;
242 return rc; 243 return rc;
243 } 244 }
244 245
245 /* 246 /*
246 * Manage operations: 247 * Manage operations:
247 * 0 - Reject 248 * 0 - Reject
248 * 1 - Commit 249 * 1 - Commit
249 */ 250 */
250 static ssize_t manage_store(struct kobject *kobj, 251 static ssize_t manage_store(struct kobject *kobj,
251 struct kobj_attribute *attr, 252 struct kobj_attribute *attr,
252 const char *buf, size_t count) 253 const char *buf, size_t count)
253 { 254 {
254 uint8_t op; 255 uint8_t op;
255 switch (buf[0]) { 256 switch (buf[0]) {
256 case '0': 257 case '0':
257 op = FLASH_REJECT_TMP_SIDE; 258 op = FLASH_REJECT_TMP_SIDE;
258 break; 259 break;
259 case '1': 260 case '1':
260 op = FLASH_COMMIT_TMP_SIDE; 261 op = FLASH_COMMIT_TMP_SIDE;
261 break; 262 break;
262 default: 263 default:
263 return -EINVAL; 264 return -EINVAL;
264 } 265 }
265 266
266 /* commit/reject temporary image */ 267 /* commit/reject temporary image */
267 opal_flash_manage(op); 268 opal_flash_manage(op);
268 return count; 269 return count;
269 } 270 }
270 271
271 /* 272 /*
272 * OPAL update flash 273 * OPAL update flash
273 */ 274 */
274 static int opal_flash_update(int op) 275 static int opal_flash_update(int op)
275 { 276 {
276 struct opal_sg_list *list; 277 struct opal_sg_list *list;
277 unsigned long addr; 278 unsigned long addr;
278 int64_t rc = OPAL_PARAMETER; 279 int64_t rc = OPAL_PARAMETER;
279 280
280 if (op == FLASH_UPDATE_CANCEL) { 281 if (op == FLASH_UPDATE_CANCEL) {
281 pr_alert("FLASH: Image update cancelled\n"); 282 pr_alert("FLASH: Image update cancelled\n");
282 addr = '\0'; 283 addr = '\0';
283 goto flash; 284 goto flash;
284 } 285 }
285 286
286 list = opal_vmalloc_to_sg_list(image_data.data, image_data.size); 287 list = opal_vmalloc_to_sg_list(image_data.data, image_data.size);
287 if (!list) 288 if (!list)
288 goto invalid_img; 289 goto invalid_img;
289 290
290 /* First entry address */ 291 /* First entry address */
291 addr = __pa(list); 292 addr = __pa(list);
292 293
293 pr_alert("FLASH: Image is %u bytes\n", image_data.size);
294 pr_alert("FLASH: Image update requested\n");
295 pr_alert("FLASH: Image will be updated during system reboot\n");
296 pr_alert("FLASH: This will take several minutes. Do not power off!\n");
297
298 flash: 294 flash:
299 rc = opal_update_flash(addr); 295 rc = opal_update_flash(addr);
300 296
301 invalid_img: 297 invalid_img:
302 return rc; 298 return rc;
299 }
300
301 /* Return CPUs to OPAL before starting FW update */
302 static void flash_return_cpu(void *info)
303 {
304 int cpu = smp_processor_id();
305
306 if (!cpu_online(cpu))
307 return;
308
309 /* Disable IRQ */
310 hard_irq_disable();
311
312 /* Return the CPU to OPAL */
313 opal_return_cpu();
314 }
315
316 /* This gets called just before system reboots */
317 void opal_flash_term_callback(void)
318 {
319 struct cpumask mask;
320
321 if (update_flash_data.status != FLASH_IMG_READY)
322 return;
323
324 pr_alert("FLASH: Flashing new firmware\n");
325 pr_alert("FLASH: Image is %u bytes\n", image_data.size);
326 pr_alert("FLASH: Performing flash and reboot/shutdown\n");
327 pr_alert("FLASH: This will take several minutes. Do not power off!\n");
328
329 /* Small delay to help getting the above message out */
330 msleep(500);
331
332 /* Return secondary CPUs to firmware */
333 cpumask_copy(&mask, cpu_online_mask);
334 cpumask_clear_cpu(smp_processor_id(), &mask);
335 if (!cpumask_empty(&mask))
336 smp_call_function_many(&mask,
337 flash_return_cpu, NULL, false);
338 /* Hard disable interrupts */
339 hard_irq_disable();
303 } 340 }
304 341
305 /* 342 /*
306 * Show candidate image status 343 * Show candidate image status
307 */ 344 */
308 static ssize_t update_show(struct kobject *kobj, 345 static ssize_t update_show(struct kobject *kobj,
309 struct kobj_attribute *attr, char *buf) 346 struct kobj_attribute *attr, char *buf)
310 { 347 {
311 struct update_flash_t *const args_buf = &update_flash_data; 348 struct update_flash_t *const args_buf = &update_flash_data;
312 return sprintf(buf, "%d\n", args_buf->status); 349 return sprintf(buf, "%d\n", args_buf->status);
313 } 350 }
314 351
315 /* 352 /*
316 * Set update image flag 353 * Set update image flag
317 * 1 - Flash new image 354 * 1 - Flash new image
318 * 0 - Cancel flash request 355 * 0 - Cancel flash request
319 */ 356 */
320 static ssize_t update_store(struct kobject *kobj, 357 static ssize_t update_store(struct kobject *kobj,
321 struct kobj_attribute *attr, 358 struct kobj_attribute *attr,
322 const char *buf, size_t count) 359 const char *buf, size_t count)
323 { 360 {
324 struct update_flash_t *const args_buf = &update_flash_data; 361 struct update_flash_t *const args_buf = &update_flash_data;
325 int rc = count; 362 int rc = count;
326 363
327 mutex_lock(&image_data_mutex); 364 mutex_lock(&image_data_mutex);
328 365
329 switch (buf[0]) { 366 switch (buf[0]) {
330 case '0': 367 case '0':
331 if (args_buf->status == FLASH_IMG_READY) 368 if (args_buf->status == FLASH_IMG_READY)
332 opal_flash_update(FLASH_UPDATE_CANCEL); 369 opal_flash_update(FLASH_UPDATE_CANCEL);
333 args_buf->status = FLASH_NO_OP; 370 args_buf->status = FLASH_NO_OP;
334 break; 371 break;
335 case '1': 372 case '1':
336 /* Image is loaded? */ 373 /* Image is loaded? */
337 if (image_data.status == IMAGE_READY) 374 if (image_data.status == IMAGE_READY)
338 args_buf->status = 375 args_buf->status =
339 opal_flash_update(FLASH_UPDATE_INIT); 376 opal_flash_update(FLASH_UPDATE_INIT);
340 else 377 else
341 args_buf->status = FLASH_INVALID_IMG; 378 args_buf->status = FLASH_INVALID_IMG;
342 break; 379 break;
343 default: 380 default:
344 rc = -EINVAL; 381 rc = -EINVAL;
345 } 382 }
346 383
347 mutex_unlock(&image_data_mutex); 384 mutex_unlock(&image_data_mutex);
348 return rc; 385 return rc;
349 } 386 }
350 387
351 /* 388 /*
352 * Free image buffer 389 * Free image buffer
353 */ 390 */
354 static void free_image_buf(void) 391 static void free_image_buf(void)
355 { 392 {
356 void *addr; 393 void *addr;
357 int size; 394 int size;
358 395
359 addr = image_data.data; 396 addr = image_data.data;
360 size = PAGE_ALIGN(image_data.size); 397 size = PAGE_ALIGN(image_data.size);
361 while (size > 0) { 398 while (size > 0) {
362 ClearPageReserved(vmalloc_to_page(addr)); 399 ClearPageReserved(vmalloc_to_page(addr));
363 addr += PAGE_SIZE; 400 addr += PAGE_SIZE;
364 size -= PAGE_SIZE; 401 size -= PAGE_SIZE;
365 } 402 }
366 vfree(image_data.data); 403 vfree(image_data.data);
367 image_data.data = NULL; 404 image_data.data = NULL;
368 image_data.status = IMAGE_INVALID; 405 image_data.status = IMAGE_INVALID;
369 } 406 }
370 407
371 /* 408 /*
372 * Allocate image buffer. 409 * Allocate image buffer.
373 */ 410 */
374 static int alloc_image_buf(char *buffer, size_t count) 411 static int alloc_image_buf(char *buffer, size_t count)
375 { 412 {
376 void *addr; 413 void *addr;
377 int size; 414 int size;
378 415
379 if (count < sizeof(struct image_header_t)) { 416 if (count < sizeof(struct image_header_t)) {
380 pr_warn("FLASH: Invalid candidate image\n"); 417 pr_warn("FLASH: Invalid candidate image\n");
381 return -EINVAL; 418 return -EINVAL;
382 } 419 }
383 420
384 memcpy(&image_header, (void *)buffer, sizeof(struct image_header_t)); 421 memcpy(&image_header, (void *)buffer, sizeof(struct image_header_t));
385 image_data.size = be32_to_cpu(image_header.size); 422 image_data.size = be32_to_cpu(image_header.size);
386 pr_debug("FLASH: Candidate image size = %u\n", image_data.size); 423 pr_debug("FLASH: Candidate image size = %u\n", image_data.size);
387 424
388 if (image_data.size > MAX_IMAGE_SIZE) { 425 if (image_data.size > MAX_IMAGE_SIZE) {
389 pr_warn("FLASH: Too large image\n"); 426 pr_warn("FLASH: Too large image\n");
390 return -EINVAL; 427 return -EINVAL;
391 } 428 }
392 if (image_data.size < VALIDATE_BUF_SIZE) { 429 if (image_data.size < VALIDATE_BUF_SIZE) {
393 pr_warn("FLASH: Image is shorter than expected\n"); 430 pr_warn("FLASH: Image is shorter than expected\n");
394 return -EINVAL; 431 return -EINVAL;
395 } 432 }
396 433
397 image_data.data = vzalloc(PAGE_ALIGN(image_data.size)); 434 image_data.data = vzalloc(PAGE_ALIGN(image_data.size));
398 if (!image_data.data) { 435 if (!image_data.data) {
399 pr_err("%s : Failed to allocate memory\n", __func__); 436 pr_err("%s : Failed to allocate memory\n", __func__);
400 return -ENOMEM; 437 return -ENOMEM;
401 } 438 }
402 439
403 /* Pin memory */ 440 /* Pin memory */
404 addr = image_data.data; 441 addr = image_data.data;
405 size = PAGE_ALIGN(image_data.size); 442 size = PAGE_ALIGN(image_data.size);
406 while (size > 0) { 443 while (size > 0) {
407 SetPageReserved(vmalloc_to_page(addr)); 444 SetPageReserved(vmalloc_to_page(addr));
408 addr += PAGE_SIZE; 445 addr += PAGE_SIZE;
409 size -= PAGE_SIZE; 446 size -= PAGE_SIZE;
410 } 447 }
411 448
412 image_data.status = IMAGE_LOADING; 449 image_data.status = IMAGE_LOADING;
413 return 0; 450 return 0;
414 } 451 }
415 452
416 /* 453 /*
417 * Copy candidate image 454 * Copy candidate image
418 * 455 *
419 * Parse candidate image header to get total image size 456 * Parse candidate image header to get total image size
420 * and pre-allocate required memory. 457 * and pre-allocate required memory.
421 */ 458 */
422 static ssize_t image_data_write(struct file *filp, struct kobject *kobj, 459 static ssize_t image_data_write(struct file *filp, struct kobject *kobj,
423 struct bin_attribute *bin_attr, 460 struct bin_attribute *bin_attr,
424 char *buffer, loff_t pos, size_t count) 461 char *buffer, loff_t pos, size_t count)
425 { 462 {
426 int rc; 463 int rc;
427 464
428 mutex_lock(&image_data_mutex); 465 mutex_lock(&image_data_mutex);
429 466
430 /* New image ? */ 467 /* New image ? */
431 if (pos == 0) { 468 if (pos == 0) {
432 /* Free memory, if already allocated */ 469 /* Free memory, if already allocated */
433 if (image_data.data) 470 if (image_data.data)
434 free_image_buf(); 471 free_image_buf();
435 472
436 /* Cancel outstanding image update request */ 473 /* Cancel outstanding image update request */
437 if (update_flash_data.status == FLASH_IMG_READY) 474 if (update_flash_data.status == FLASH_IMG_READY)
438 opal_flash_update(FLASH_UPDATE_CANCEL); 475 opal_flash_update(FLASH_UPDATE_CANCEL);
439 476
440 /* Allocate memory */ 477 /* Allocate memory */
441 rc = alloc_image_buf(buffer, count); 478 rc = alloc_image_buf(buffer, count);
442 if (rc) 479 if (rc)
443 goto out; 480 goto out;
444 } 481 }
445 482
446 if (image_data.status != IMAGE_LOADING) { 483 if (image_data.status != IMAGE_LOADING) {
447 rc = -ENOMEM; 484 rc = -ENOMEM;
448 goto out; 485 goto out;
449 } 486 }
450 487
451 if ((pos + count) > image_data.size) { 488 if ((pos + count) > image_data.size) {
452 rc = -EINVAL; 489 rc = -EINVAL;
453 goto out; 490 goto out;
454 } 491 }
455 492
456 memcpy(image_data.data + pos, (void *)buffer, count); 493 memcpy(image_data.data + pos, (void *)buffer, count);
457 rc = count; 494 rc = count;
458 495
459 /* Set image status */ 496 /* Set image status */
460 if ((pos + count) == image_data.size) { 497 if ((pos + count) == image_data.size) {
461 pr_debug("FLASH: Candidate image loaded....\n"); 498 pr_debug("FLASH: Candidate image loaded....\n");
462 image_data.status = IMAGE_READY; 499 image_data.status = IMAGE_READY;
463 } 500 }
464 501
465 out: 502 out:
466 mutex_unlock(&image_data_mutex); 503 mutex_unlock(&image_data_mutex);
467 return rc; 504 return rc;
468 } 505 }
469 506
470 /* 507 /*
471 * sysfs interface : 508 * sysfs interface :
472 * OPAL uses below sysfs files for code update. 509 * OPAL uses below sysfs files for code update.
473 * We create these files under /sys/firmware/opal. 510 * We create these files under /sys/firmware/opal.
474 * 511 *
475 * image : Interface to load candidate firmware image 512 * image : Interface to load candidate firmware image
476 * validate_flash : Validate firmware image 513 * validate_flash : Validate firmware image
477 * manage_flash : Commit/Reject firmware image 514 * manage_flash : Commit/Reject firmware image
478 * update_flash : Flash new firmware image 515 * update_flash : Flash new firmware image
479 * 516 *
480 */ 517 */
481 static struct bin_attribute image_data_attr = { 518 static struct bin_attribute image_data_attr = {
482 .attr = {.name = "image", .mode = 0200}, 519 .attr = {.name = "image", .mode = 0200},
483 .size = MAX_IMAGE_SIZE, /* Limit image size */ 520 .size = MAX_IMAGE_SIZE, /* Limit image size */
484 .write = image_data_write, 521 .write = image_data_write,
485 }; 522 };
486 523
487 static struct kobj_attribute validate_attribute = 524 static struct kobj_attribute validate_attribute =
488 __ATTR(validate_flash, 0600, validate_show, validate_store); 525 __ATTR(validate_flash, 0600, validate_show, validate_store);
489 526
490 static struct kobj_attribute manage_attribute = 527 static struct kobj_attribute manage_attribute =
491 __ATTR(manage_flash, 0600, manage_show, manage_store); 528 __ATTR(manage_flash, 0600, manage_show, manage_store);
492 529
493 static struct kobj_attribute update_attribute = 530 static struct kobj_attribute update_attribute =
494 __ATTR(update_flash, 0600, update_show, update_store); 531 __ATTR(update_flash, 0600, update_show, update_store);
495 532
496 static struct attribute *image_op_attrs[] = { 533 static struct attribute *image_op_attrs[] = {
497 &validate_attribute.attr, 534 &validate_attribute.attr,
498 &manage_attribute.attr, 535 &manage_attribute.attr,
499 &update_attribute.attr, 536 &update_attribute.attr,
500 NULL /* need to NULL terminate the list of attributes */ 537 NULL /* need to NULL terminate the list of attributes */
501 }; 538 };
502 539
503 static struct attribute_group image_op_attr_group = { 540 static struct attribute_group image_op_attr_group = {
504 .attrs = image_op_attrs, 541 .attrs = image_op_attrs,
505 }; 542 };
506 543
507 void __init opal_flash_init(void) 544 void __init opal_flash_init(void)
508 { 545 {
509 int ret; 546 int ret;
510 547
511 /* Allocate validate image buffer */ 548 /* Allocate validate image buffer */
512 validate_flash_data.buf = kzalloc(VALIDATE_BUF_SIZE, GFP_KERNEL); 549 validate_flash_data.buf = kzalloc(VALIDATE_BUF_SIZE, GFP_KERNEL);
513 if (!validate_flash_data.buf) { 550 if (!validate_flash_data.buf) {
514 pr_err("%s : Failed to allocate memory\n", __func__); 551 pr_err("%s : Failed to allocate memory\n", __func__);
515 return; 552 return;
516 } 553 }
517 554
518 /* Make sure /sys/firmware/opal directory is created */ 555 /* Make sure /sys/firmware/opal directory is created */
519 if (!opal_kobj) { 556 if (!opal_kobj) {
520 pr_warn("FLASH: opal kobject is not available\n"); 557 pr_warn("FLASH: opal kobject is not available\n");
521 goto nokobj; 558 goto nokobj;
522 } 559 }
523 560
524 /* Create the sysfs files */ 561 /* Create the sysfs files */
525 ret = sysfs_create_group(opal_kobj, &image_op_attr_group); 562 ret = sysfs_create_group(opal_kobj, &image_op_attr_group);
526 if (ret) { 563 if (ret) {
527 pr_warn("FLASH: Failed to create sysfs files\n"); 564 pr_warn("FLASH: Failed to create sysfs files\n");
528 goto nokobj; 565 goto nokobj;
529 } 566 }
530 567
531 ret = sysfs_create_bin_file(opal_kobj, &image_data_attr); 568 ret = sysfs_create_bin_file(opal_kobj, &image_data_attr);
532 if (ret) { 569 if (ret) {
533 pr_warn("FLASH: Failed to create sysfs files\n"); 570 pr_warn("FLASH: Failed to create sysfs files\n");
534 goto nosysfs_file; 571 goto nosysfs_file;
535 } 572 }
536 573
537 /* Set default status */ 574 /* Set default status */
538 validate_flash_data.status = FLASH_NO_OP; 575 validate_flash_data.status = FLASH_NO_OP;
539 manage_flash_data.status = FLASH_NO_OP; 576 manage_flash_data.status = FLASH_NO_OP;
540 update_flash_data.status = FLASH_NO_OP; 577 update_flash_data.status = FLASH_NO_OP;
541 image_data.status = IMAGE_INVALID; 578 image_data.status = IMAGE_INVALID;
542 return; 579 return;
543 580
544 nosysfs_file: 581 nosysfs_file:
545 sysfs_remove_group(opal_kobj, &image_op_attr_group); 582 sysfs_remove_group(opal_kobj, &image_op_attr_group);
546 583
arch/powerpc/platforms/powernv/setup.c
Diff comments   View file @ 2196c6f
1 /* 1 /*
2 * PowerNV setup code. 2 * PowerNV setup code.
3 * 3 *
4 * Copyright 2011 IBM Corp. 4 * Copyright 2011 IBM Corp.
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12 #undef DEBUG 12 #undef DEBUG
13 13
14 #include <linux/cpu.h> 14 #include <linux/cpu.h>
15 #include <linux/errno.h> 15 #include <linux/errno.h>
16 #include <linux/sched.h> 16 #include <linux/sched.h>
17 #include <linux/kernel.h> 17 #include <linux/kernel.h>
18 #include <linux/tty.h> 18 #include <linux/tty.h>
19 #include <linux/reboot.h> 19 #include <linux/reboot.h>
20 #include <linux/init.h> 20 #include <linux/init.h>
21 #include <linux/console.h> 21 #include <linux/console.h>
22 #include <linux/delay.h> 22 #include <linux/delay.h>
23 #include <linux/irq.h> 23 #include <linux/irq.h>
24 #include <linux/seq_file.h> 24 #include <linux/seq_file.h>
25 #include <linux/of.h> 25 #include <linux/of.h>
26 #include <linux/of_fdt.h> 26 #include <linux/of_fdt.h>
27 #include <linux/interrupt.h> 27 #include <linux/interrupt.h>
28 #include <linux/bug.h> 28 #include <linux/bug.h>
29 #include <linux/pci.h> 29 #include <linux/pci.h>
30 30
31 #include <asm/machdep.h> 31 #include <asm/machdep.h>
32 #include <asm/firmware.h> 32 #include <asm/firmware.h>
33 #include <asm/xics.h> 33 #include <asm/xics.h>
34 #include <asm/rtas.h> 34 #include <asm/rtas.h>
35 #include <asm/opal.h> 35 #include <asm/opal.h>
36 #include <asm/kexec.h> 36 #include <asm/kexec.h>
37 37
38 #include "powernv.h" 38 #include "powernv.h"
39 39
40 static void __init pnv_setup_arch(void) 40 static void __init pnv_setup_arch(void)
41 { 41 {
42 /* Initialize SMP */ 42 /* Initialize SMP */
43 pnv_smp_init(); 43 pnv_smp_init();
44 44
45 /* Setup PCI */ 45 /* Setup PCI */
46 pnv_pci_init(); 46 pnv_pci_init();
47 47
48 /* Setup RTC and NVRAM callbacks */ 48 /* Setup RTC and NVRAM callbacks */
49 if (firmware_has_feature(FW_FEATURE_OPAL)) 49 if (firmware_has_feature(FW_FEATURE_OPAL))
50 opal_nvram_init(); 50 opal_nvram_init();
51 51
52 /* Enable NAP mode */ 52 /* Enable NAP mode */
53 powersave_nap = 1; 53 powersave_nap = 1;
54 54
55 /* XXX PMCS */ 55 /* XXX PMCS */
56 } 56 }
57 57
58 static void __init pnv_init_early(void) 58 static void __init pnv_init_early(void)
59 { 59 {
60 /* 60 /*
61 * Initialize the LPC bus now so that legacy serial 61 * Initialize the LPC bus now so that legacy serial
62 * ports can be found on it 62 * ports can be found on it
63 */ 63 */
64 opal_lpc_init(); 64 opal_lpc_init();
65 65
66 #ifdef CONFIG_HVC_OPAL 66 #ifdef CONFIG_HVC_OPAL
67 if (firmware_has_feature(FW_FEATURE_OPAL)) 67 if (firmware_has_feature(FW_FEATURE_OPAL))
68 hvc_opal_init_early(); 68 hvc_opal_init_early();
69 else 69 else
70 #endif 70 #endif
71 add_preferred_console("hvc", 0, NULL); 71 add_preferred_console("hvc", 0, NULL);
72 } 72 }
73 73
74 static void __init pnv_init_IRQ(void) 74 static void __init pnv_init_IRQ(void)
75 { 75 {
76 xics_init(); 76 xics_init();
77 77
78 WARN_ON(!ppc_md.get_irq); 78 WARN_ON(!ppc_md.get_irq);
79 } 79 }
80 80
81 static void pnv_show_cpuinfo(struct seq_file *m) 81 static void pnv_show_cpuinfo(struct seq_file *m)
82 { 82 {
83 struct device_node *root; 83 struct device_node *root;
84 const char *model = ""; 84 const char *model = "";
85 85
86 root = of_find_node_by_path("/"); 86 root = of_find_node_by_path("/");
87 if (root) 87 if (root)
88 model = of_get_property(root, "model", NULL); 88 model = of_get_property(root, "model", NULL);
89 seq_printf(m, "machine\t\t: PowerNV %s\n", model); 89 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
90 if (firmware_has_feature(FW_FEATURE_OPALv3)) 90 if (firmware_has_feature(FW_FEATURE_OPALv3))
91 seq_printf(m, "firmware\t: OPAL v3\n"); 91 seq_printf(m, "firmware\t: OPAL v3\n");
92 else if (firmware_has_feature(FW_FEATURE_OPALv2)) 92 else if (firmware_has_feature(FW_FEATURE_OPALv2))
93 seq_printf(m, "firmware\t: OPAL v2\n"); 93 seq_printf(m, "firmware\t: OPAL v2\n");
94 else if (firmware_has_feature(FW_FEATURE_OPAL)) 94 else if (firmware_has_feature(FW_FEATURE_OPAL))
95 seq_printf(m, "firmware\t: OPAL v1\n"); 95 seq_printf(m, "firmware\t: OPAL v1\n");
96 else 96 else
97 seq_printf(m, "firmware\t: BML\n"); 97 seq_printf(m, "firmware\t: BML\n");
98 of_node_put(root); 98 of_node_put(root);
99 } 99 }
100 100
101 static void pnv_prepare_going_down(void)
102 {
103 /*
104 * Disable all notifiers from OPAL, we can't
105 * service interrupts anymore anyway
106 */
107 opal_notifier_disable();
108
109 /* Soft disable interrupts */
110 local_irq_disable();
111
112 /*
113 * Return secondary CPUs to firwmare if a flash update
114 * is pending otherwise we will get all sort of error
115 * messages about CPU being stuck etc.. This will also
116 * have the side effect of hard disabling interrupts so
117 * past this point, the kernel is effectively dead.
118 */
119 opal_flash_term_callback();
120 }
121
101 static void __noreturn pnv_restart(char *cmd) 122 static void __noreturn pnv_restart(char *cmd)
102 { 123 {
103 long rc = OPAL_BUSY; 124 long rc = OPAL_BUSY;
104 125
105 opal_notifier_disable(); 126 pnv_prepare_going_down();
106 127
107 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 128 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
108 rc = opal_cec_reboot(); 129 rc = opal_cec_reboot();
109 if (rc == OPAL_BUSY_EVENT) 130 if (rc == OPAL_BUSY_EVENT)
110 opal_poll_events(NULL); 131 opal_poll_events(NULL);
111 else 132 else
112 mdelay(10); 133 mdelay(10);
113 } 134 }
114 for (;;) 135 for (;;)
115 opal_poll_events(NULL); 136 opal_poll_events(NULL);
116 } 137 }
117 138
118 static void __noreturn pnv_power_off(void) 139 static void __noreturn pnv_power_off(void)
119 { 140 {
120 long rc = OPAL_BUSY; 141 long rc = OPAL_BUSY;
121 142
122 opal_notifier_disable(); 143 pnv_prepare_going_down();
123 144
124 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 145 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
125 rc = opal_cec_power_down(0); 146 rc = opal_cec_power_down(0);
126 if (rc == OPAL_BUSY_EVENT) 147 if (rc == OPAL_BUSY_EVENT)
127 opal_poll_events(NULL); 148 opal_poll_events(NULL);
128 else 149 else
129 mdelay(10); 150 mdelay(10);
130 } 151 }
131 for (;;) 152 for (;;)
132 opal_poll_events(NULL); 153 opal_poll_events(NULL);
133 } 154 }
134 155
135 static void __noreturn pnv_halt(void) 156 static void __noreturn pnv_halt(void)
136 { 157 {
137 pnv_power_off(); 158 pnv_power_off();
138 } 159 }
139 160
140 static void pnv_progress(char *s, unsigned short hex) 161 static void pnv_progress(char *s, unsigned short hex)
141 { 162 {
142 } 163 }
143 164
144 static int pnv_dma_set_mask(struct device *dev, u64 dma_mask) 165 static int pnv_dma_set_mask(struct device *dev, u64 dma_mask)
145 { 166 {
146 if (dev_is_pci(dev)) 167 if (dev_is_pci(dev))
147 return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask); 168 return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask);
148 return __dma_set_mask(dev, dma_mask); 169 return __dma_set_mask(dev, dma_mask);
149 } 170 }
150 171
151 static void pnv_shutdown(void) 172 static void pnv_shutdown(void)
152 { 173 {
153 /* Let the PCI code clear up IODA tables */ 174 /* Let the PCI code clear up IODA tables */
154 pnv_pci_shutdown(); 175 pnv_pci_shutdown();
155 176
156 /* 177 /*
157 * Stop OPAL activity: Unregister all OPAL interrupts so they 178 * Stop OPAL activity: Unregister all OPAL interrupts so they
158 * don't fire up while we kexec and make sure all potentially 179 * don't fire up while we kexec and make sure all potentially
159 * DMA'ing ops are complete (such as dump retrieval). 180 * DMA'ing ops are complete (such as dump retrieval).
160 */ 181 */
161 opal_shutdown(); 182 opal_shutdown();
162 } 183 }
163 184
164 #ifdef CONFIG_KEXEC 185 #ifdef CONFIG_KEXEC
165 static void pnv_kexec_wait_secondaries_down(void) 186 static void pnv_kexec_wait_secondaries_down(void)
166 { 187 {
167 int my_cpu, i, notified = -1; 188 int my_cpu, i, notified = -1;
168 189
169 my_cpu = get_cpu(); 190 my_cpu = get_cpu();
170 191
171 for_each_online_cpu(i) { 192 for_each_online_cpu(i) {
172 uint8_t status; 193 uint8_t status;
173 int64_t rc; 194 int64_t rc;
174 195
175 if (i == my_cpu) 196 if (i == my_cpu)
176 continue; 197 continue;
177 198
178 for (;;) { 199 for (;;) {
179 rc = opal_query_cpu_status(get_hard_smp_processor_id(i), 200 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
180 &status); 201 &status);
181 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) 202 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
182 break; 203 break;
183 barrier(); 204 barrier();
184 if (i != notified) { 205 if (i != notified) {
185 printk(KERN_INFO "kexec: waiting for cpu %d " 206 printk(KERN_INFO "kexec: waiting for cpu %d "
186 "(physical %d) to enter OPAL\n", 207 "(physical %d) to enter OPAL\n",
187 i, paca[i].hw_cpu_id); 208 i, paca[i].hw_cpu_id);
188 notified = i; 209 notified = i;
189 } 210 }
190 } 211 }
191 } 212 }
192 } 213 }
193 214
194 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) 215 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
195 { 216 {
196 xics_kexec_teardown_cpu(secondary); 217 xics_kexec_teardown_cpu(secondary);
197 218
198 /* On OPAL v3, we return all CPUs to firmware */ 219 /* On OPAL v3, we return all CPUs to firmware */
199 220
200 if (!firmware_has_feature(FW_FEATURE_OPALv3)) 221 if (!firmware_has_feature(FW_FEATURE_OPALv3))
201 return; 222 return;
202 223
203 if (secondary) { 224 if (secondary) {
204 /* Return secondary CPUs to firmware on OPAL v3 */ 225 /* Return secondary CPUs to firmware on OPAL v3 */
205 mb(); 226 mb();
206 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; 227 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
207 mb(); 228 mb();
208 229
209 /* Return the CPU to OPAL */ 230 /* Return the CPU to OPAL */
210 opal_return_cpu(); 231 opal_return_cpu();
211 } else if (crash_shutdown) { 232 } else if (crash_shutdown) {
212 /* 233 /*
213 * On crash, we don't wait for secondaries to go 234 * On crash, we don't wait for secondaries to go
214 * down as they might be unreachable or hung, so 235 * down as they might be unreachable or hung, so
215 * instead we just wait a bit and move on. 236 * instead we just wait a bit and move on.
216 */ 237 */
217 mdelay(1); 238 mdelay(1);
218 } else { 239 } else {
219 /* Primary waits for the secondaries to have reached OPAL */ 240 /* Primary waits for the secondaries to have reached OPAL */
220 pnv_kexec_wait_secondaries_down(); 241 pnv_kexec_wait_secondaries_down();
221 } 242 }
222 } 243 }
223 #endif /* CONFIG_KEXEC */ 244 #endif /* CONFIG_KEXEC */
224 245
225 static void __init pnv_setup_machdep_opal(void) 246 static void __init pnv_setup_machdep_opal(void)
226 { 247 {
227 ppc_md.get_boot_time = opal_get_boot_time; 248 ppc_md.get_boot_time = opal_get_boot_time;
228 ppc_md.get_rtc_time = opal_get_rtc_time; 249 ppc_md.get_rtc_time = opal_get_rtc_time;
229 ppc_md.set_rtc_time = opal_set_rtc_time; 250 ppc_md.set_rtc_time = opal_set_rtc_time;
230 ppc_md.restart = pnv_restart; 251 ppc_md.restart = pnv_restart;
231 ppc_md.power_off = pnv_power_off; 252 ppc_md.power_off = pnv_power_off;
232 ppc_md.halt = pnv_halt; 253 ppc_md.halt = pnv_halt;
233 ppc_md.machine_check_exception = opal_machine_check; 254 ppc_md.machine_check_exception = opal_machine_check;
234 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; 255 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
235 } 256 }
236 257
237 #ifdef CONFIG_PPC_POWERNV_RTAS 258 #ifdef CONFIG_PPC_POWERNV_RTAS
238 static void __init pnv_setup_machdep_rtas(void) 259 static void __init pnv_setup_machdep_rtas(void)
239 { 260 {
240 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { 261 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
241 ppc_md.get_boot_time = rtas_get_boot_time; 262 ppc_md.get_boot_time = rtas_get_boot_time;
242 ppc_md.get_rtc_time = rtas_get_rtc_time; 263 ppc_md.get_rtc_time = rtas_get_rtc_time;
243 ppc_md.set_rtc_time = rtas_set_rtc_time; 264 ppc_md.set_rtc_time = rtas_set_rtc_time;
244 } 265 }
245 ppc_md.restart = rtas_restart; 266 ppc_md.restart = rtas_restart;
246 ppc_md.power_off = rtas_power_off; 267 ppc_md.power_off = rtas_power_off;
247 ppc_md.halt = rtas_halt; 268 ppc_md.halt = rtas_halt;
248 } 269 }
249 #endif /* CONFIG_PPC_POWERNV_RTAS */ 270 #endif /* CONFIG_PPC_POWERNV_RTAS */
250 271
251 static int __init pnv_probe(void) 272 static int __init pnv_probe(void)
252 { 273 {
253 unsigned long root = of_get_flat_dt_root(); 274 unsigned long root = of_get_flat_dt_root();
254 275
255 if (!of_flat_dt_is_compatible(root, "ibm,powernv")) 276 if (!of_flat_dt_is_compatible(root, "ibm,powernv"))
256 return 0; 277 return 0;
257 278
258 hpte_init_native(); 279 hpte_init_native();
259 280
260 if (firmware_has_feature(FW_FEATURE_OPAL)) 281 if (firmware_has_feature(FW_FEATURE_OPAL))
261 pnv_setup_machdep_opal(); 282 pnv_setup_machdep_opal();
262 #ifdef CONFIG_PPC_POWERNV_RTAS 283 #ifdef CONFIG_PPC_POWERNV_RTAS
263 else if (rtas.base) 284 else if (rtas.base)
264 pnv_setup_machdep_rtas(); 285 pnv_setup_machdep_rtas();
265 #endif /* CONFIG_PPC_POWERNV_RTAS */ 286 #endif /* CONFIG_PPC_POWERNV_RTAS */
266 287
267 pr_debug("PowerNV detected !\n"); 288 pr_debug("PowerNV detected !\n");
268 289
269 return 1; 290 return 1;
270 } 291 }
271 292
272 define_machine(powernv) { 293 define_machine(powernv) {
273 .name = "PowerNV", 294 .name = "PowerNV",
274 .probe = pnv_probe, 295 .probe = pnv_probe,
275 .init_early = pnv_init_early, 296 .init_early = pnv_init_early,
276 .setup_arch = pnv_setup_arch, 297 .setup_arch = pnv_setup_arch,
277 .init_IRQ = pnv_init_IRQ, 298 .init_IRQ = pnv_init_IRQ,
278 .show_cpuinfo = pnv_show_cpuinfo, 299 .show_cpuinfo = pnv_show_cpuinfo,
279 .progress = pnv_progress, 300 .progress = pnv_progress,
280 .machine_shutdown = pnv_shutdown, 301 .machine_shutdown = pnv_shutdown,
281 .power_save = power7_idle, 302 .power_save = power7_idle,
282 .calibrate_decr = generic_calibrate_decr, 303 .calibrate_decr = generic_calibrate_decr,
283 .dma_set_mask = pnv_dma_set_mask, 304 .dma_set_mask = pnv_dma_set_mask,
284 #ifdef CONFIG_KEXEC 305 #ifdef CONFIG_KEXEC
285 .kexec_cpu_down = pnv_kexec_cpu_down, 306 .kexec_cpu_down = pnv_kexec_cpu_down,
286 #endif 307 #endif
287 }; 308 };
288 309