Eric Lee / smarc-ti-linux-kernel

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Commit 25217fef355174209eff68c0eb438a8af5d7b01c

Authored by Abhilash Kesavan
Committed by Olof Johansson
1 parent 896ddd600b
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

ARM: dts: disable CCI on exynos5420 based arndale-octa 

The arndale-octa board was giving "imprecise external aborts" during
boot-up with MCPM enabled. CCI enablement of the boot cluster was found
to be the cause of these aborts (possibly because the secure f/w was not
allowing it). Hence, disable CCI for the arndale-octa board.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

Showing 2 changed files with 5 additions and 1 deletions Inline Diff

arch/arm/boot/dts/exynos5420-arndale-octa.dts
Diff comments   View file @ 25217fe
1 /* 1 /*
2 * Samsung's Exynos5420 based Arndale Octa board device tree source 2 * Samsung's Exynos5420 based Arndale Octa board device tree source
3 * 3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 5 * http://www.samsung.com
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12 /dts-v1/; 12 /dts-v1/;
13 #include "exynos5420.dtsi" 13 #include "exynos5420.dtsi"
14 #include <dt-bindings/interrupt-controller/irq.h> 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 16
17 / { 17 / {
18 model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; 18 model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
19 compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; 19 compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
20 20
21 memory { 21 memory {
22 reg = <0x20000000 0x80000000>; 22 reg = <0x20000000 0x80000000>;
23 }; 23 };
24 24
25 chosen { 25 chosen {
26 bootargs = "console=ttySAC3,115200"; 26 bootargs = "console=ttySAC3,115200";
27 }; 27 };
28 28
29 firmware@02073000 { 29 firmware@02073000 {
30 compatible = "samsung,secure-firmware"; 30 compatible = "samsung,secure-firmware";
31 reg = <0x02073000 0x1000>; 31 reg = <0x02073000 0x1000>;
32 }; 32 };
33 33
34 fixed-rate-clocks { 34 fixed-rate-clocks {
35 oscclk { 35 oscclk {
36 compatible = "samsung,exynos5420-oscclk"; 36 compatible = "samsung,exynos5420-oscclk";
37 clock-frequency = <24000000>; 37 clock-frequency = <24000000>;
38 }; 38 };
39 }; 39 };
40 40
41 rtc@101E0000 { 41 rtc@101E0000 {
42 status = "okay"; 42 status = "okay";
43 }; 43 };
44 44
45 codec@11000000 { 45 codec@11000000 {
46 samsung,mfc-r = <0x43000000 0x800000>; 46 samsung,mfc-r = <0x43000000 0x800000>;
47 samsung,mfc-l = <0x51000000 0x800000>; 47 samsung,mfc-l = <0x51000000 0x800000>;
48 }; 48 };
49 49
50 mmc@12200000 { 50 mmc@12200000 {
51 status = "okay"; 51 status = "okay";
52 broken-cd; 52 broken-cd;
53 card-detect-delay = <200>; 53 card-detect-delay = <200>;
54 samsung,dw-mshc-ciu-div = <3>; 54 samsung,dw-mshc-ciu-div = <3>;
55 samsung,dw-mshc-sdr-timing = <0 4>; 55 samsung,dw-mshc-sdr-timing = <0 4>;
56 samsung,dw-mshc-ddr-timing = <0 2>; 56 samsung,dw-mshc-ddr-timing = <0 2>;
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 58 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
59 vmmc-supply = <&ldo10_reg>; 59 vmmc-supply = <&ldo10_reg>;
60 bus-width = <8>; 60 bus-width = <8>;
61 cap-mmc-highspeed; 61 cap-mmc-highspeed;
62 }; 62 };
63 63
64 mmc@12220000 { 64 mmc@12220000 {
65 status = "okay"; 65 status = "okay";
66 card-detect-delay = <200>; 66 card-detect-delay = <200>;
67 samsung,dw-mshc-ciu-div = <3>; 67 samsung,dw-mshc-ciu-div = <3>;
68 samsung,dw-mshc-sdr-timing = <2 3>; 68 samsung,dw-mshc-sdr-timing = <2 3>;
69 samsung,dw-mshc-ddr-timing = <1 2>; 69 samsung,dw-mshc-ddr-timing = <1 2>;
70 pinctrl-names = "default"; 70 pinctrl-names = "default";
71 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 71 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
72 vmmc-supply = <&ldo19_reg>; 72 vmmc-supply = <&ldo19_reg>;
73 vqmmc-supply = <&ldo13_reg>; 73 vqmmc-supply = <&ldo13_reg>;
74 bus-width = <4>; 74 bus-width = <4>;
75 cap-sd-highspeed; 75 cap-sd-highspeed;
76 }; 76 };
77 77
78 hsi2c_4: i2c@12CA0000 { 78 hsi2c_4: i2c@12CA0000 {
79 status = "okay"; 79 status = "okay";
80 80
81 s2mps11_pmic@66 { 81 s2mps11_pmic@66 {
82 compatible = "samsung,s2mps11-pmic"; 82 compatible = "samsung,s2mps11-pmic";
83 reg = <0x66>; 83 reg = <0x66>;
84 s2mps11,buck2-ramp-delay = <12>; 84 s2mps11,buck2-ramp-delay = <12>;
85 s2mps11,buck34-ramp-delay = <12>; 85 s2mps11,buck34-ramp-delay = <12>;
86 s2mps11,buck16-ramp-delay = <12>; 86 s2mps11,buck16-ramp-delay = <12>;
87 s2mps11,buck6-ramp-enable = <1>; 87 s2mps11,buck6-ramp-enable = <1>;
88 s2mps11,buck2-ramp-enable = <1>; 88 s2mps11,buck2-ramp-enable = <1>;
89 s2mps11,buck3-ramp-enable = <1>; 89 s2mps11,buck3-ramp-enable = <1>;
90 s2mps11,buck4-ramp-enable = <1>; 90 s2mps11,buck4-ramp-enable = <1>;
91 91
92 interrupt-parent = <&gpx3>; 92 interrupt-parent = <&gpx3>;
93 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 93 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
94 94
95 s2mps11_osc: clocks { 95 s2mps11_osc: clocks {
96 #clock-cells = <1>; 96 #clock-cells = <1>;
97 clock-output-names = "s2mps11_ap", 97 clock-output-names = "s2mps11_ap",
98 "s2mps11_cp", "s2mps11_bt"; 98 "s2mps11_cp", "s2mps11_bt";
99 }; 99 };
100 100
101 regulators { 101 regulators {
102 ldo1_reg: LDO1 { 102 ldo1_reg: LDO1 {
103 regulator-name = "PVDD_ALIVE_1V0"; 103 regulator-name = "PVDD_ALIVE_1V0";
104 regulator-min-microvolt = <1000000>; 104 regulator-min-microvolt = <1000000>;
105 regulator-max-microvolt = <1000000>; 105 regulator-max-microvolt = <1000000>;
106 regulator-always-on; 106 regulator-always-on;
107 }; 107 };
108 108
109 ldo2_reg: LDO2 { 109 ldo2_reg: LDO2 {
110 regulator-name = "PVDD_APIO_1V8"; 110 regulator-name = "PVDD_APIO_1V8";
111 regulator-min-microvolt = <1800000>; 111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <1800000>; 112 regulator-max-microvolt = <1800000>;
113 }; 113 };
114 114
115 ldo3_reg: LDO3 { 115 ldo3_reg: LDO3 {
116 regulator-name = "PVDD_APIO_MMCON_1V8"; 116 regulator-name = "PVDD_APIO_MMCON_1V8";
117 regulator-min-microvolt = <1800000>; 117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>; 118 regulator-max-microvolt = <1800000>;
119 regulator-always-on; 119 regulator-always-on;
120 }; 120 };
121 121
122 ldo4_reg: LDO4 { 122 ldo4_reg: LDO4 {
123 regulator-name = "PVDD_ADC_1V8"; 123 regulator-name = "PVDD_ADC_1V8";
124 regulator-min-microvolt = <1800000>; 124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>; 125 regulator-max-microvolt = <1800000>;
126 }; 126 };
127 127
128 ldo5_reg: LDO5 { 128 ldo5_reg: LDO5 {
129 regulator-name = "PVDD_PLL_1V8"; 129 regulator-name = "PVDD_PLL_1V8";
130 regulator-min-microvolt = <1800000>; 130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <1800000>; 131 regulator-max-microvolt = <1800000>;
132 regulator-always-on; 132 regulator-always-on;
133 }; 133 };
134 134
135 ldo6_reg: LDO6 { 135 ldo6_reg: LDO6 {
136 regulator-name = "PVDD_ANAIP_1V0"; 136 regulator-name = "PVDD_ANAIP_1V0";
137 regulator-min-microvolt = <1000000>; 137 regulator-min-microvolt = <1000000>;
138 regulator-max-microvolt = <1000000>; 138 regulator-max-microvolt = <1000000>;
139 }; 139 };
140 140
141 ldo7_reg: LDO7 { 141 ldo7_reg: LDO7 {
142 regulator-name = "PVDD_ANAIP_1V8"; 142 regulator-name = "PVDD_ANAIP_1V8";
143 regulator-min-microvolt = <1800000>; 143 regulator-min-microvolt = <1800000>;
144 regulator-max-microvolt = <1800000>; 144 regulator-max-microvolt = <1800000>;
145 }; 145 };
146 146
147 ldo8_reg: LDO8 { 147 ldo8_reg: LDO8 {
148 regulator-name = "PVDD_ABB_1V8"; 148 regulator-name = "PVDD_ABB_1V8";
149 regulator-min-microvolt = <1800000>; 149 regulator-min-microvolt = <1800000>;
150 regulator-max-microvolt = <1800000>; 150 regulator-max-microvolt = <1800000>;
151 }; 151 };
152 152
153 ldo9_reg: LDO9 { 153 ldo9_reg: LDO9 {
154 regulator-name = "PVDD_USB_3V3"; 154 regulator-name = "PVDD_USB_3V3";
155 regulator-min-microvolt = <3000000>; 155 regulator-min-microvolt = <3000000>;
156 regulator-max-microvolt = <3000000>; 156 regulator-max-microvolt = <3000000>;
157 regulator-always-on; 157 regulator-always-on;
158 }; 158 };
159 159
160 ldo10_reg: LDO10 { 160 ldo10_reg: LDO10 {
161 regulator-name = "PVDD_PRE_1V8"; 161 regulator-name = "PVDD_PRE_1V8";
162 regulator-min-microvolt = <1800000>; 162 regulator-min-microvolt = <1800000>;
163 regulator-max-microvolt = <1800000>; 163 regulator-max-microvolt = <1800000>;
164 regulator-always-on; 164 regulator-always-on;
165 }; 165 };
166 166
167 ldo11_reg: LDO11 { 167 ldo11_reg: LDO11 {
168 regulator-name = "PVDD_USB_1V0"; 168 regulator-name = "PVDD_USB_1V0";
169 regulator-min-microvolt = <1000000>; 169 regulator-min-microvolt = <1000000>;
170 regulator-max-microvolt = <1000000>; 170 regulator-max-microvolt = <1000000>;
171 regulator-always-on; 171 regulator-always-on;
172 }; 172 };
173 173
174 ldo12_reg: LDO12 { 174 ldo12_reg: LDO12 {
175 regulator-name = "PVDD_HSIC_1V8"; 175 regulator-name = "PVDD_HSIC_1V8";
176 regulator-min-microvolt = <1800000>; 176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <1800000>; 177 regulator-max-microvolt = <1800000>;
178 }; 178 };
179 179
180 ldo13_reg: LDO13 { 180 ldo13_reg: LDO13 {
181 regulator-name = "PVDD_APIO_MMCOFF_2V8"; 181 regulator-name = "PVDD_APIO_MMCOFF_2V8";
182 regulator-min-microvolt = <2800000>; 182 regulator-min-microvolt = <2800000>;
183 regulator-max-microvolt = <2800000>; 183 regulator-max-microvolt = <2800000>;
184 }; 184 };
185 185
186 ldo15_reg: LDO15 { 186 ldo15_reg: LDO15 {
187 regulator-name = "PVDD_PERI_2V8"; 187 regulator-name = "PVDD_PERI_2V8";
188 regulator-min-microvolt = <3300000>; 188 regulator-min-microvolt = <3300000>;
189 regulator-max-microvolt = <3300000>; 189 regulator-max-microvolt = <3300000>;
190 }; 190 };
191 191
192 ldo16_reg: LDO16 { 192 ldo16_reg: LDO16 {
193 regulator-name = "PVDD_PERI_3V3"; 193 regulator-name = "PVDD_PERI_3V3";
194 regulator-min-microvolt = <2200000>; 194 regulator-min-microvolt = <2200000>;
195 regulator-max-microvolt = <2200000>; 195 regulator-max-microvolt = <2200000>;
196 }; 196 };
197 197
198 ldo18_reg: LDO18 { 198 ldo18_reg: LDO18 {
199 regulator-name = "PVDD_EMMC_1V8"; 199 regulator-name = "PVDD_EMMC_1V8";
200 regulator-min-microvolt = <1800000>; 200 regulator-min-microvolt = <1800000>;
201 regulator-max-microvolt = <1800000>; 201 regulator-max-microvolt = <1800000>;
202 }; 202 };
203 203
204 ldo19_reg: LDO19 { 204 ldo19_reg: LDO19 {
205 regulator-name = "PVDD_TFLASH_2V8"; 205 regulator-name = "PVDD_TFLASH_2V8";
206 regulator-min-microvolt = <2800000>; 206 regulator-min-microvolt = <2800000>;
207 regulator-max-microvolt = <2800000>; 207 regulator-max-microvolt = <2800000>;
208 }; 208 };
209 209
210 ldo20_reg: LDO20 { 210 ldo20_reg: LDO20 {
211 regulator-name = "PVDD_BTWIFI_1V8"; 211 regulator-name = "PVDD_BTWIFI_1V8";
212 regulator-min-microvolt = <1800000>; 212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <1800000>; 213 regulator-max-microvolt = <1800000>;
214 }; 214 };
215 215
216 ldo21_reg: LDO21 { 216 ldo21_reg: LDO21 {
217 regulator-name = "PVDD_CAM1IO_1V8"; 217 regulator-name = "PVDD_CAM1IO_1V8";
218 regulator-min-microvolt = <1800000>; 218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <1800000>; 219 regulator-max-microvolt = <1800000>;
220 }; 220 };
221 221
222 ldo23_reg: LDO23 { 222 ldo23_reg: LDO23 {
223 regulator-name = "PVDD_MIFS_1V1"; 223 regulator-name = "PVDD_MIFS_1V1";
224 regulator-min-microvolt = <1200000>; 224 regulator-min-microvolt = <1200000>;
225 regulator-max-microvolt = <1200000>; 225 regulator-max-microvolt = <1200000>;
226 regulator-always-on; 226 regulator-always-on;
227 }; 227 };
228 228
229 ldo24_reg: LDO24 { 229 ldo24_reg: LDO24 {
230 regulator-name = "PVDD_CAM1_AVDD_2V8"; 230 regulator-name = "PVDD_CAM1_AVDD_2V8";
231 regulator-min-microvolt = <2800000>; 231 regulator-min-microvolt = <2800000>;
232 regulator-max-microvolt = <2800000>; 232 regulator-max-microvolt = <2800000>;
233 }; 233 };
234 234
235 ldo26_reg: LDO26 { 235 ldo26_reg: LDO26 {
236 regulator-name = "PVDD_CAM0_AF_2V8"; 236 regulator-name = "PVDD_CAM0_AF_2V8";
237 regulator-min-microvolt = <3000000>; 237 regulator-min-microvolt = <3000000>;
238 regulator-max-microvolt = <3000000>; 238 regulator-max-microvolt = <3000000>;
239 }; 239 };
240 240
241 ldo27_reg: LDO27 { 241 ldo27_reg: LDO27 {
242 regulator-name = "PVDD_G3DS_1V0"; 242 regulator-name = "PVDD_G3DS_1V0";
243 regulator-min-microvolt = <1200000>; 243 regulator-min-microvolt = <1200000>;
244 regulator-max-microvolt = <1200000>; 244 regulator-max-microvolt = <1200000>;
245 }; 245 };
246 246
247 ldo28_reg: LDO28 { 247 ldo28_reg: LDO28 {
248 regulator-name = "PVDD_TSP_3V3"; 248 regulator-name = "PVDD_TSP_3V3";
249 regulator-min-microvolt = <3300000>; 249 regulator-min-microvolt = <3300000>;
250 regulator-max-microvolt = <3300000>; 250 regulator-max-microvolt = <3300000>;
251 }; 251 };
252 252
253 ldo29_reg: LDO29 { 253 ldo29_reg: LDO29 {
254 regulator-name = "PVDD_AUDIO_1V8"; 254 regulator-name = "PVDD_AUDIO_1V8";
255 regulator-min-microvolt = <1800000>; 255 regulator-min-microvolt = <1800000>;
256 regulator-max-microvolt = <1800000>; 256 regulator-max-microvolt = <1800000>;
257 }; 257 };
258 258
259 ldo31_reg: LDO31 { 259 ldo31_reg: LDO31 {
260 regulator-name = "PVDD_PERI_1V8"; 260 regulator-name = "PVDD_PERI_1V8";
261 regulator-min-microvolt = <1800000>; 261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>; 262 regulator-max-microvolt = <1800000>;
263 }; 263 };
264 264
265 ldo32_reg: LDO32 { 265 ldo32_reg: LDO32 {
266 regulator-name = "PVDD_LCD_1V8"; 266 regulator-name = "PVDD_LCD_1V8";
267 regulator-min-microvolt = <1800000>; 267 regulator-min-microvolt = <1800000>;
268 regulator-max-microvolt = <1800000>; 268 regulator-max-microvolt = <1800000>;
269 }; 269 };
270 270
271 ldo33_reg: LDO33 { 271 ldo33_reg: LDO33 {
272 regulator-name = "PVDD_CAM0IO_1V8"; 272 regulator-name = "PVDD_CAM0IO_1V8";
273 regulator-min-microvolt = <1800000>; 273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <1800000>; 274 regulator-max-microvolt = <1800000>;
275 }; 275 };
276 276
277 ldo35_reg: LDO35 { 277 ldo35_reg: LDO35 {
278 regulator-name = "PVDD_CAM0_DVDD_1V2"; 278 regulator-name = "PVDD_CAM0_DVDD_1V2";
279 regulator-min-microvolt = <1200000>; 279 regulator-min-microvolt = <1200000>;
280 regulator-max-microvolt = <1200000>; 280 regulator-max-microvolt = <1200000>;
281 }; 281 };
282 282
283 ldo38_reg: LDO38 { 283 ldo38_reg: LDO38 {
284 regulator-name = "PVDD_CAM0_AVDD_2V8"; 284 regulator-name = "PVDD_CAM0_AVDD_2V8";
285 regulator-min-microvolt = <2800000>; 285 regulator-min-microvolt = <2800000>;
286 regulator-max-microvolt = <2800000>; 286 regulator-max-microvolt = <2800000>;
287 }; 287 };
288 288
289 buck1_reg: BUCK1 { 289 buck1_reg: BUCK1 {
290 regulator-name = "PVDD_MIF_1V1"; 290 regulator-name = "PVDD_MIF_1V1";
291 regulator-min-microvolt = <800000>; 291 regulator-min-microvolt = <800000>;
292 regulator-max-microvolt = <1100000>; 292 regulator-max-microvolt = <1100000>;
293 regulator-always-on; 293 regulator-always-on;
294 }; 294 };
295 295
296 buck2_reg: BUCK2 { 296 buck2_reg: BUCK2 {
297 regulator-name = "vdd_arm"; 297 regulator-name = "vdd_arm";
298 regulator-min-microvolt = <800000>; 298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1000000>; 299 regulator-max-microvolt = <1000000>;
300 regulator-always-on; 300 regulator-always-on;
301 }; 301 };
302 302
303 buck3_reg: BUCK3 { 303 buck3_reg: BUCK3 {
304 regulator-name = "PVDD_INT_1V0"; 304 regulator-name = "PVDD_INT_1V0";
305 regulator-min-microvolt = <800000>; 305 regulator-min-microvolt = <800000>;
306 regulator-max-microvolt = <1000000>; 306 regulator-max-microvolt = <1000000>;
307 regulator-always-on; 307 regulator-always-on;
308 }; 308 };
309 309
310 buck4_reg: BUCK4 { 310 buck4_reg: BUCK4 {
311 regulator-name = "PVDD_G3D_1V0"; 311 regulator-name = "PVDD_G3D_1V0";
312 regulator-min-microvolt = <800000>; 312 regulator-min-microvolt = <800000>;
313 regulator-max-microvolt = <1000000>; 313 regulator-max-microvolt = <1000000>;
314 }; 314 };
315 315
316 buck5_reg: BUCK5 { 316 buck5_reg: BUCK5 {
317 regulator-name = "PVDD_LPDDR3_1V2"; 317 regulator-name = "PVDD_LPDDR3_1V2";
318 regulator-min-microvolt = <800000>; 318 regulator-min-microvolt = <800000>;
319 regulator-max-microvolt = <1200000>; 319 regulator-max-microvolt = <1200000>;
320 regulator-always-on; 320 regulator-always-on;
321 }; 321 };
322 322
323 buck6_reg: BUCK6 { 323 buck6_reg: BUCK6 {
324 regulator-name = "PVDD_KFC_1V0"; 324 regulator-name = "PVDD_KFC_1V0";
325 regulator-min-microvolt = <800000>; 325 regulator-min-microvolt = <800000>;
326 regulator-max-microvolt = <1000000>; 326 regulator-max-microvolt = <1000000>;
327 regulator-always-on; 327 regulator-always-on;
328 }; 328 };
329 329
330 buck7_reg: BUCK7 { 330 buck7_reg: BUCK7 {
331 regulator-name = "VIN_LLDO_1V4"; 331 regulator-name = "VIN_LLDO_1V4";
332 regulator-min-microvolt = <800000>; 332 regulator-min-microvolt = <800000>;
333 regulator-max-microvolt = <1400000>; 333 regulator-max-microvolt = <1400000>;
334 regulator-always-on; 334 regulator-always-on;
335 }; 335 };
336 336
337 buck8_reg: BUCK8 { 337 buck8_reg: BUCK8 {
338 regulator-name = "VIN_MLDO_2V0"; 338 regulator-name = "VIN_MLDO_2V0";
339 regulator-min-microvolt = <800000>; 339 regulator-min-microvolt = <800000>;
340 regulator-max-microvolt = <2000000>; 340 regulator-max-microvolt = <2000000>;
341 regulator-always-on; 341 regulator-always-on;
342 }; 342 };
343 343
344 buck9_reg: BUCK9 { 344 buck9_reg: BUCK9 {
345 regulator-name = "VIN_HLDO_3V5"; 345 regulator-name = "VIN_HLDO_3V5";
346 regulator-min-microvolt = <3000000>; 346 regulator-min-microvolt = <3000000>;
347 regulator-max-microvolt = <3500000>; 347 regulator-max-microvolt = <3500000>;
348 regulator-always-on; 348 regulator-always-on;
349 }; 349 };
350 350
351 buck10_reg: BUCK10 { 351 buck10_reg: BUCK10 {
352 regulator-name = "PVDD_EMMCF_2V8"; 352 regulator-name = "PVDD_EMMCF_2V8";
353 regulator-min-microvolt = <2800000>; 353 regulator-min-microvolt = <2800000>;
354 regulator-max-microvolt = <2800000>; 354 regulator-max-microvolt = <2800000>;
355 }; 355 };
356 }; 356 };
357 }; 357 };
358 }; 358 };
359 359
360 gpio_keys { 360 gpio_keys {
361 compatible = "gpio-keys"; 361 compatible = "gpio-keys";
362 362
363 wakeup { 363 wakeup {
364 label = "SW-TACT1"; 364 label = "SW-TACT1";
365 gpios = <&gpx2 7 1>; 365 gpios = <&gpx2 7 1>;
366 linux,code = <KEY_WAKEUP>; 366 linux,code = <KEY_WAKEUP>;
367 gpio-key,wakeup; 367 gpio-key,wakeup;
368 }; 368 };
369 }; 369 };
370 }; 370 };
371 371
372 &usbdrd_dwc3_1 { 372 &usbdrd_dwc3_1 {
373 dr_mode = "host"; 373 dr_mode = "host";
374 }; 374 };
375
376 &cci {
377 status = "disabled";
378 };
375 379
arch/arm/boot/dts/exynos5420.dtsi
Diff comments   View file @ 25217fe
1 /* 1 /*
2 * SAMSUNG EXYNOS5420 SoC device tree source 2 * SAMSUNG EXYNOS5420 SoC device tree source
3 * 3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 5 * http://www.samsung.com
6 * 6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. 7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide 8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings. 9 * values for board specfic bindings.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16 #include <dt-bindings/clock/exynos5420.h> 16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi" 17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi" 18 #include "exynos5420-pinctrl.dtsi"
19 19
20 #include <dt-bindings/clock/exynos-audss-clk.h> 20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 21
22 / { 22 / {
23 compatible = "samsung,exynos5420", "samsung,exynos5"; 23 compatible = "samsung,exynos5420", "samsung,exynos5";
24 24
25 aliases { 25 aliases {
26 mshc0 = &mmc_0; 26 mshc0 = &mmc_0;
27 mshc1 = &mmc_1; 27 mshc1 = &mmc_1;
28 mshc2 = &mmc_2; 28 mshc2 = &mmc_2;
29 pinctrl0 = &pinctrl_0; 29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1; 30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3; 32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4; 33 pinctrl4 = &pinctrl_4;
34 i2c0 = &i2c_0; 34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1; 35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2; 36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3; 37 i2c3 = &i2c_3;
38 i2c4 = &hsi2c_4; 38 i2c4 = &hsi2c_4;
39 i2c5 = &hsi2c_5; 39 i2c5 = &hsi2c_5;
40 i2c6 = &hsi2c_6; 40 i2c6 = &hsi2c_6;
41 i2c7 = &hsi2c_7; 41 i2c7 = &hsi2c_7;
42 i2c8 = &hsi2c_8; 42 i2c8 = &hsi2c_8;
43 i2c9 = &hsi2c_9; 43 i2c9 = &hsi2c_9;
44 i2c10 = &hsi2c_10; 44 i2c10 = &hsi2c_10;
45 gsc0 = &gsc_0; 45 gsc0 = &gsc_0;
46 gsc1 = &gsc_1; 46 gsc1 = &gsc_1;
47 spi0 = &spi_0; 47 spi0 = &spi_0;
48 spi1 = &spi_1; 48 spi1 = &spi_1;
49 spi2 = &spi_2; 49 spi2 = &spi_2;
50 usbdrdphy0 = &usbdrd_phy0; 50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1; 51 usbdrdphy1 = &usbdrd_phy1;
52 }; 52 };
53 53
54 cpus { 54 cpus {
55 #address-cells = <1>; 55 #address-cells = <1>;
56 #size-cells = <0>; 56 #size-cells = <0>;
57 57
58 cpu0: cpu@0 { 58 cpu0: cpu@0 {
59 device_type = "cpu"; 59 device_type = "cpu";
60 compatible = "arm,cortex-a15"; 60 compatible = "arm,cortex-a15";
61 reg = <0x0>; 61 reg = <0x0>;
62 clock-frequency = <1800000000>; 62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>; 63 cci-control-port = <&cci_control1>;
64 }; 64 };
65 65
66 cpu1: cpu@1 { 66 cpu1: cpu@1 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cortex-a15"; 68 compatible = "arm,cortex-a15";
69 reg = <0x1>; 69 reg = <0x1>;
70 clock-frequency = <1800000000>; 70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>; 71 cci-control-port = <&cci_control1>;
72 }; 72 };
73 73
74 cpu2: cpu@2 { 74 cpu2: cpu@2 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 compatible = "arm,cortex-a15"; 76 compatible = "arm,cortex-a15";
77 reg = <0x2>; 77 reg = <0x2>;
78 clock-frequency = <1800000000>; 78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>; 79 cci-control-port = <&cci_control1>;
80 }; 80 };
81 81
82 cpu3: cpu@3 { 82 cpu3: cpu@3 {
83 device_type = "cpu"; 83 device_type = "cpu";
84 compatible = "arm,cortex-a15"; 84 compatible = "arm,cortex-a15";
85 reg = <0x3>; 85 reg = <0x3>;
86 clock-frequency = <1800000000>; 86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>; 87 cci-control-port = <&cci_control1>;
88 }; 88 };
89 89
90 cpu4: cpu@100 { 90 cpu4: cpu@100 {
91 device_type = "cpu"; 91 device_type = "cpu";
92 compatible = "arm,cortex-a7"; 92 compatible = "arm,cortex-a7";
93 reg = <0x100>; 93 reg = <0x100>;
94 clock-frequency = <1000000000>; 94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>; 95 cci-control-port = <&cci_control0>;
96 }; 96 };
97 97
98 cpu5: cpu@101 { 98 cpu5: cpu@101 {
99 device_type = "cpu"; 99 device_type = "cpu";
100 compatible = "arm,cortex-a7"; 100 compatible = "arm,cortex-a7";
101 reg = <0x101>; 101 reg = <0x101>;
102 clock-frequency = <1000000000>; 102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>; 103 cci-control-port = <&cci_control0>;
104 }; 104 };
105 105
106 cpu6: cpu@102 { 106 cpu6: cpu@102 {
107 device_type = "cpu"; 107 device_type = "cpu";
108 compatible = "arm,cortex-a7"; 108 compatible = "arm,cortex-a7";
109 reg = <0x102>; 109 reg = <0x102>;
110 clock-frequency = <1000000000>; 110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>; 111 cci-control-port = <&cci_control0>;
112 }; 112 };
113 113
114 cpu7: cpu@103 { 114 cpu7: cpu@103 {
115 device_type = "cpu"; 115 device_type = "cpu";
116 compatible = "arm,cortex-a7"; 116 compatible = "arm,cortex-a7";
117 reg = <0x103>; 117 reg = <0x103>;
118 clock-frequency = <1000000000>; 118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>; 119 cci-control-port = <&cci_control0>;
120 }; 120 };
121 }; 121 };
122 122
123 cci@10d20000 { 123 cci: cci@10d20000 {
124 compatible = "arm,cci-400"; 124 compatible = "arm,cci-400";
125 #address-cells = <1>; 125 #address-cells = <1>;
126 #size-cells = <1>; 126 #size-cells = <1>;
127 reg = <0x10d20000 0x1000>; 127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>; 128 ranges = <0x0 0x10d20000 0x6000>;
129 129
130 cci_control0: slave-if@4000 { 130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if"; 131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace"; 132 interface-type = "ace";
133 reg = <0x4000 0x1000>; 133 reg = <0x4000 0x1000>;
134 }; 134 };
135 cci_control1: slave-if@5000 { 135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if"; 136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace"; 137 interface-type = "ace";
138 reg = <0x5000 0x1000>; 138 reg = <0x5000 0x1000>;
139 }; 139 };
140 }; 140 };
141 141
142 sysram@02020000 { 142 sysram@02020000 {
143 compatible = "mmio-sram"; 143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>; 144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>; 145 #address-cells = <1>;
146 #size-cells = <1>; 146 #size-cells = <1>;
147 ranges = <0 0x02020000 0x54000>; 147 ranges = <0 0x02020000 0x54000>;
148 148
149 smp-sysram@0 { 149 smp-sysram@0 {
150 compatible = "samsung,exynos4210-sysram"; 150 compatible = "samsung,exynos4210-sysram";
151 reg = <0x0 0x1000>; 151 reg = <0x0 0x1000>;
152 }; 152 };
153 153
154 smp-sysram@53000 { 154 smp-sysram@53000 {
155 compatible = "samsung,exynos4210-sysram-ns"; 155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>; 156 reg = <0x53000 0x1000>;
157 }; 157 };
158 }; 158 };
159 159
160 clock: clock-controller@10010000 { 160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock"; 161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>; 162 reg = <0x10010000 0x30000>;
163 #clock-cells = <1>; 163 #clock-cells = <1>;
164 }; 164 };
165 165
166 clock_audss: audss-clock-controller@3810000 { 166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock"; 167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>; 168 reg = <0x03810000 0x0C>;
169 #clock-cells = <1>; 169 #clock-cells = <1>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
173 }; 173 };
174 174
175 mfc: codec@11000000 { 175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7"; 176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>; 177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>; 178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>; 179 clocks = <&clock CLK_MFC>;
180 clock-names = "mfc"; 180 clock-names = "mfc";
181 samsung,power-domain = <&mfc_pd>; 181 samsung,power-domain = <&mfc_pd>;
182 }; 182 };
183 183
184 mmc_0: mmc@12200000 { 184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu"; 185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>; 186 interrupts = <0 75 0>;
187 #address-cells = <1>; 187 #address-cells = <1>;
188 #size-cells = <0>; 188 #size-cells = <0>;
189 reg = <0x12200000 0x2000>; 189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu"; 191 clock-names = "biu", "ciu";
192 fifo-depth = <0x40>; 192 fifo-depth = <0x40>;
193 status = "disabled"; 193 status = "disabled";
194 }; 194 };
195 195
196 mmc_1: mmc@12210000 { 196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu"; 197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>; 198 interrupts = <0 76 0>;
199 #address-cells = <1>; 199 #address-cells = <1>;
200 #size-cells = <0>; 200 #size-cells = <0>;
201 reg = <0x12210000 0x2000>; 201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu"; 203 clock-names = "biu", "ciu";
204 fifo-depth = <0x40>; 204 fifo-depth = <0x40>;
205 status = "disabled"; 205 status = "disabled";
206 }; 206 };
207 207
208 mmc_2: mmc@12220000 { 208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc"; 209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>; 210 interrupts = <0 77 0>;
211 #address-cells = <1>; 211 #address-cells = <1>;
212 #size-cells = <0>; 212 #size-cells = <0>;
213 reg = <0x12220000 0x1000>; 213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu"; 215 clock-names = "biu", "ciu";
216 fifo-depth = <0x40>; 216 fifo-depth = <0x40>;
217 status = "disabled"; 217 status = "disabled";
218 }; 218 };
219 219
220 mct: mct@101C0000 { 220 mct: mct@101C0000 {
221 compatible = "samsung,exynos4210-mct"; 221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>; 222 reg = <0x101C0000 0x800>;
223 interrupt-controller; 223 interrupt-controller;
224 #interrups-cells = <1>; 224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>; 225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, 226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>; 227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct"; 229 clock-names = "fin_pll", "mct";
230 230
231 mct_map: mct-map { 231 mct_map: mct-map {
232 #interrupt-cells = <1>; 232 #interrupt-cells = <1>;
233 #address-cells = <0>; 233 #address-cells = <0>;
234 #size-cells = <0>; 234 #size-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>, 235 interrupt-map = <0 &combiner 23 3>,
236 <1 &combiner 23 4>, 236 <1 &combiner 23 4>,
237 <2 &combiner 25 2>, 237 <2 &combiner 25 2>,
238 <3 &combiner 25 3>, 238 <3 &combiner 25 3>,
239 <4 &gic 0 120 0>, 239 <4 &gic 0 120 0>,
240 <5 &gic 0 121 0>, 240 <5 &gic 0 121 0>,
241 <6 &gic 0 122 0>, 241 <6 &gic 0 122 0>,
242 <7 &gic 0 123 0>, 242 <7 &gic 0 123 0>,
243 <8 &gic 0 128 0>, 243 <8 &gic 0 128 0>,
244 <9 &gic 0 129 0>, 244 <9 &gic 0 129 0>,
245 <10 &gic 0 130 0>, 245 <10 &gic 0 130 0>,
246 <11 &gic 0 131 0>; 246 <11 &gic 0 131 0>;
247 }; 247 };
248 }; 248 };
249 249
250 gsc_pd: power-domain@10044000 { 250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd"; 251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>; 252 reg = <0x10044000 0x20>;
253 }; 253 };
254 254
255 isp_pd: power-domain@10044020 { 255 isp_pd: power-domain@10044020 {
256 compatible = "samsung,exynos4210-pd"; 256 compatible = "samsung,exynos4210-pd";
257 reg = <0x10044020 0x20>; 257 reg = <0x10044020 0x20>;
258 }; 258 };
259 259
260 mfc_pd: power-domain@10044060 { 260 mfc_pd: power-domain@10044060 {
261 compatible = "samsung,exynos4210-pd"; 261 compatible = "samsung,exynos4210-pd";
262 reg = <0x10044060 0x20>; 262 reg = <0x10044060 0x20>;
263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, 263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
264 <&clock CLK_MOUT_USER_ACLK333>; 264 <&clock CLK_MOUT_USER_ACLK333>;
265 clock-names = "oscclk", "pclk0", "clk0"; 265 clock-names = "oscclk", "pclk0", "clk0";
266 }; 266 };
267 267
268 msc_pd: power-domain@10044120 { 268 msc_pd: power-domain@10044120 {
269 compatible = "samsung,exynos4210-pd"; 269 compatible = "samsung,exynos4210-pd";
270 reg = <0x10044120 0x20>; 270 reg = <0x10044120 0x20>;
271 }; 271 };
272 272
273 pinctrl_0: pinctrl@13400000 { 273 pinctrl_0: pinctrl@13400000 {
274 compatible = "samsung,exynos5420-pinctrl"; 274 compatible = "samsung,exynos5420-pinctrl";
275 reg = <0x13400000 0x1000>; 275 reg = <0x13400000 0x1000>;
276 interrupts = <0 45 0>; 276 interrupts = <0 45 0>;
277 277
278 wakeup-interrupt-controller { 278 wakeup-interrupt-controller {
279 compatible = "samsung,exynos4210-wakeup-eint"; 279 compatible = "samsung,exynos4210-wakeup-eint";
280 interrupt-parent = <&gic>; 280 interrupt-parent = <&gic>;
281 interrupts = <0 32 0>; 281 interrupts = <0 32 0>;
282 }; 282 };
283 }; 283 };
284 284
285 pinctrl_1: pinctrl@13410000 { 285 pinctrl_1: pinctrl@13410000 {
286 compatible = "samsung,exynos5420-pinctrl"; 286 compatible = "samsung,exynos5420-pinctrl";
287 reg = <0x13410000 0x1000>; 287 reg = <0x13410000 0x1000>;
288 interrupts = <0 78 0>; 288 interrupts = <0 78 0>;
289 }; 289 };
290 290
291 pinctrl_2: pinctrl@14000000 { 291 pinctrl_2: pinctrl@14000000 {
292 compatible = "samsung,exynos5420-pinctrl"; 292 compatible = "samsung,exynos5420-pinctrl";
293 reg = <0x14000000 0x1000>; 293 reg = <0x14000000 0x1000>;
294 interrupts = <0 46 0>; 294 interrupts = <0 46 0>;
295 }; 295 };
296 296
297 pinctrl_3: pinctrl@14010000 { 297 pinctrl_3: pinctrl@14010000 {
298 compatible = "samsung,exynos5420-pinctrl"; 298 compatible = "samsung,exynos5420-pinctrl";
299 reg = <0x14010000 0x1000>; 299 reg = <0x14010000 0x1000>;
300 interrupts = <0 50 0>; 300 interrupts = <0 50 0>;
301 }; 301 };
302 302
303 pinctrl_4: pinctrl@03860000 { 303 pinctrl_4: pinctrl@03860000 {
304 compatible = "samsung,exynos5420-pinctrl"; 304 compatible = "samsung,exynos5420-pinctrl";
305 reg = <0x03860000 0x1000>; 305 reg = <0x03860000 0x1000>;
306 interrupts = <0 47 0>; 306 interrupts = <0 47 0>;
307 }; 307 };
308 308
309 rtc: rtc@101E0000 { 309 rtc: rtc@101E0000 {
310 clocks = <&clock CLK_RTC>; 310 clocks = <&clock CLK_RTC>;
311 clock-names = "rtc"; 311 clock-names = "rtc";
312 status = "disabled"; 312 status = "disabled";
313 }; 313 };
314 314
315 amba { 315 amba {
316 #address-cells = <1>; 316 #address-cells = <1>;
317 #size-cells = <1>; 317 #size-cells = <1>;
318 compatible = "arm,amba-bus"; 318 compatible = "arm,amba-bus";
319 interrupt-parent = <&gic>; 319 interrupt-parent = <&gic>;
320 ranges; 320 ranges;
321 321
322 adma: adma@03880000 { 322 adma: adma@03880000 {
323 compatible = "arm,pl330", "arm,primecell"; 323 compatible = "arm,pl330", "arm,primecell";
324 reg = <0x03880000 0x1000>; 324 reg = <0x03880000 0x1000>;
325 interrupts = <0 110 0>; 325 interrupts = <0 110 0>;
326 clocks = <&clock_audss EXYNOS_ADMA>; 326 clocks = <&clock_audss EXYNOS_ADMA>;
327 clock-names = "apb_pclk"; 327 clock-names = "apb_pclk";
328 #dma-cells = <1>; 328 #dma-cells = <1>;
329 #dma-channels = <6>; 329 #dma-channels = <6>;
330 #dma-requests = <16>; 330 #dma-requests = <16>;
331 }; 331 };
332 332
333 pdma0: pdma@121A0000 { 333 pdma0: pdma@121A0000 {
334 compatible = "arm,pl330", "arm,primecell"; 334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x121A0000 0x1000>; 335 reg = <0x121A0000 0x1000>;
336 interrupts = <0 34 0>; 336 interrupts = <0 34 0>;
337 clocks = <&clock CLK_PDMA0>; 337 clocks = <&clock CLK_PDMA0>;
338 clock-names = "apb_pclk"; 338 clock-names = "apb_pclk";
339 #dma-cells = <1>; 339 #dma-cells = <1>;
340 #dma-channels = <8>; 340 #dma-channels = <8>;
341 #dma-requests = <32>; 341 #dma-requests = <32>;
342 }; 342 };
343 343
344 pdma1: pdma@121B0000 { 344 pdma1: pdma@121B0000 {
345 compatible = "arm,pl330", "arm,primecell"; 345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0x121B0000 0x1000>; 346 reg = <0x121B0000 0x1000>;
347 interrupts = <0 35 0>; 347 interrupts = <0 35 0>;
348 clocks = <&clock CLK_PDMA1>; 348 clocks = <&clock CLK_PDMA1>;
349 clock-names = "apb_pclk"; 349 clock-names = "apb_pclk";
350 #dma-cells = <1>; 350 #dma-cells = <1>;
351 #dma-channels = <8>; 351 #dma-channels = <8>;
352 #dma-requests = <32>; 352 #dma-requests = <32>;
353 }; 353 };
354 354
355 mdma0: mdma@10800000 { 355 mdma0: mdma@10800000 {
356 compatible = "arm,pl330", "arm,primecell"; 356 compatible = "arm,pl330", "arm,primecell";
357 reg = <0x10800000 0x1000>; 357 reg = <0x10800000 0x1000>;
358 interrupts = <0 33 0>; 358 interrupts = <0 33 0>;
359 clocks = <&clock CLK_MDMA0>; 359 clocks = <&clock CLK_MDMA0>;
360 clock-names = "apb_pclk"; 360 clock-names = "apb_pclk";
361 #dma-cells = <1>; 361 #dma-cells = <1>;
362 #dma-channels = <8>; 362 #dma-channels = <8>;
363 #dma-requests = <1>; 363 #dma-requests = <1>;
364 }; 364 };
365 365
366 mdma1: mdma@11C10000 { 366 mdma1: mdma@11C10000 {
367 compatible = "arm,pl330", "arm,primecell"; 367 compatible = "arm,pl330", "arm,primecell";
368 reg = <0x11C10000 0x1000>; 368 reg = <0x11C10000 0x1000>;
369 interrupts = <0 124 0>; 369 interrupts = <0 124 0>;
370 clocks = <&clock CLK_MDMA1>; 370 clocks = <&clock CLK_MDMA1>;
371 clock-names = "apb_pclk"; 371 clock-names = "apb_pclk";
372 #dma-cells = <1>; 372 #dma-cells = <1>;
373 #dma-channels = <8>; 373 #dma-channels = <8>;
374 #dma-requests = <1>; 374 #dma-requests = <1>;
375 /* 375 /*
376 * MDMA1 can support both secure and non-secure 376 * MDMA1 can support both secure and non-secure
377 * AXI transactions. When this is enabled in the kernel 377 * AXI transactions. When this is enabled in the kernel
378 * for boards that run in secure mode, we are getting 378 * for boards that run in secure mode, we are getting
379 * imprecise external aborts causing the kernel to oops. 379 * imprecise external aborts causing the kernel to oops.
380 */ 380 */
381 status = "disabled"; 381 status = "disabled";
382 }; 382 };
383 }; 383 };
384 384
385 i2s0: i2s@03830000 { 385 i2s0: i2s@03830000 {
386 compatible = "samsung,exynos5420-i2s"; 386 compatible = "samsung,exynos5420-i2s";
387 reg = <0x03830000 0x100>; 387 reg = <0x03830000 0x100>;
388 dmas = <&adma 0 388 dmas = <&adma 0
389 &adma 2 389 &adma 2
390 &adma 1>; 390 &adma 1>;
391 dma-names = "tx", "rx", "tx-sec"; 391 dma-names = "tx", "rx", "tx-sec";
392 clocks = <&clock_audss EXYNOS_I2S_BUS>, 392 clocks = <&clock_audss EXYNOS_I2S_BUS>,
393 <&clock_audss EXYNOS_I2S_BUS>, 393 <&clock_audss EXYNOS_I2S_BUS>,
394 <&clock_audss EXYNOS_SCLK_I2S>; 394 <&clock_audss EXYNOS_SCLK_I2S>;
395 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 395 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
396 samsung,idma-addr = <0x03000000>; 396 samsung,idma-addr = <0x03000000>;
397 pinctrl-names = "default"; 397 pinctrl-names = "default";
398 pinctrl-0 = <&i2s0_bus>; 398 pinctrl-0 = <&i2s0_bus>;
399 status = "disabled"; 399 status = "disabled";
400 }; 400 };
401 401
402 i2s1: i2s@12D60000 { 402 i2s1: i2s@12D60000 {
403 compatible = "samsung,exynos5420-i2s"; 403 compatible = "samsung,exynos5420-i2s";
404 reg = <0x12D60000 0x100>; 404 reg = <0x12D60000 0x100>;
405 dmas = <&pdma1 12 405 dmas = <&pdma1 12
406 &pdma1 11>; 406 &pdma1 11>;
407 dma-names = "tx", "rx"; 407 dma-names = "tx", "rx";
408 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; 408 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
409 clock-names = "iis", "i2s_opclk0"; 409 clock-names = "iis", "i2s_opclk0";
410 pinctrl-names = "default"; 410 pinctrl-names = "default";
411 pinctrl-0 = <&i2s1_bus>; 411 pinctrl-0 = <&i2s1_bus>;
412 status = "disabled"; 412 status = "disabled";
413 }; 413 };
414 414
415 i2s2: i2s@12D70000 { 415 i2s2: i2s@12D70000 {
416 compatible = "samsung,exynos5420-i2s"; 416 compatible = "samsung,exynos5420-i2s";
417 reg = <0x12D70000 0x100>; 417 reg = <0x12D70000 0x100>;
418 dmas = <&pdma0 12 418 dmas = <&pdma0 12
419 &pdma0 11>; 419 &pdma0 11>;
420 dma-names = "tx", "rx"; 420 dma-names = "tx", "rx";
421 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; 421 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
422 clock-names = "iis", "i2s_opclk0"; 422 clock-names = "iis", "i2s_opclk0";
423 pinctrl-names = "default"; 423 pinctrl-names = "default";
424 pinctrl-0 = <&i2s2_bus>; 424 pinctrl-0 = <&i2s2_bus>;
425 status = "disabled"; 425 status = "disabled";
426 }; 426 };
427 427
428 spi_0: spi@12d20000 { 428 spi_0: spi@12d20000 {
429 compatible = "samsung,exynos4210-spi"; 429 compatible = "samsung,exynos4210-spi";
430 reg = <0x12d20000 0x100>; 430 reg = <0x12d20000 0x100>;
431 interrupts = <0 68 0>; 431 interrupts = <0 68 0>;
432 dmas = <&pdma0 5 432 dmas = <&pdma0 5
433 &pdma0 4>; 433 &pdma0 4>;
434 dma-names = "tx", "rx"; 434 dma-names = "tx", "rx";
435 #address-cells = <1>; 435 #address-cells = <1>;
436 #size-cells = <0>; 436 #size-cells = <0>;
437 pinctrl-names = "default"; 437 pinctrl-names = "default";
438 pinctrl-0 = <&spi0_bus>; 438 pinctrl-0 = <&spi0_bus>;
439 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 439 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
440 clock-names = "spi", "spi_busclk0"; 440 clock-names = "spi", "spi_busclk0";
441 status = "disabled"; 441 status = "disabled";
442 }; 442 };
443 443
444 spi_1: spi@12d30000 { 444 spi_1: spi@12d30000 {
445 compatible = "samsung,exynos4210-spi"; 445 compatible = "samsung,exynos4210-spi";
446 reg = <0x12d30000 0x100>; 446 reg = <0x12d30000 0x100>;
447 interrupts = <0 69 0>; 447 interrupts = <0 69 0>;
448 dmas = <&pdma1 5 448 dmas = <&pdma1 5
449 &pdma1 4>; 449 &pdma1 4>;
450 dma-names = "tx", "rx"; 450 dma-names = "tx", "rx";
451 #address-cells = <1>; 451 #address-cells = <1>;
452 #size-cells = <0>; 452 #size-cells = <0>;
453 pinctrl-names = "default"; 453 pinctrl-names = "default";
454 pinctrl-0 = <&spi1_bus>; 454 pinctrl-0 = <&spi1_bus>;
455 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 455 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
456 clock-names = "spi", "spi_busclk0"; 456 clock-names = "spi", "spi_busclk0";
457 status = "disabled"; 457 status = "disabled";
458 }; 458 };
459 459
460 spi_2: spi@12d40000 { 460 spi_2: spi@12d40000 {
461 compatible = "samsung,exynos4210-spi"; 461 compatible = "samsung,exynos4210-spi";
462 reg = <0x12d40000 0x100>; 462 reg = <0x12d40000 0x100>;
463 interrupts = <0 70 0>; 463 interrupts = <0 70 0>;
464 dmas = <&pdma0 7 464 dmas = <&pdma0 7
465 &pdma0 6>; 465 &pdma0 6>;
466 dma-names = "tx", "rx"; 466 dma-names = "tx", "rx";
467 #address-cells = <1>; 467 #address-cells = <1>;
468 #size-cells = <0>; 468 #size-cells = <0>;
469 pinctrl-names = "default"; 469 pinctrl-names = "default";
470 pinctrl-0 = <&spi2_bus>; 470 pinctrl-0 = <&spi2_bus>;
471 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 471 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
472 clock-names = "spi", "spi_busclk0"; 472 clock-names = "spi", "spi_busclk0";
473 status = "disabled"; 473 status = "disabled";
474 }; 474 };
475 475
476 uart_0: serial@12C00000 { 476 uart_0: serial@12C00000 {
477 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 477 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
478 clock-names = "uart", "clk_uart_baud0"; 478 clock-names = "uart", "clk_uart_baud0";
479 }; 479 };
480 480
481 uart_1: serial@12C10000 { 481 uart_1: serial@12C10000 {
482 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 482 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
483 clock-names = "uart", "clk_uart_baud0"; 483 clock-names = "uart", "clk_uart_baud0";
484 }; 484 };
485 485
486 uart_2: serial@12C20000 { 486 uart_2: serial@12C20000 {
487 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 487 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
488 clock-names = "uart", "clk_uart_baud0"; 488 clock-names = "uart", "clk_uart_baud0";
489 }; 489 };
490 490
491 uart_3: serial@12C30000 { 491 uart_3: serial@12C30000 {
492 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 492 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
493 clock-names = "uart", "clk_uart_baud0"; 493 clock-names = "uart", "clk_uart_baud0";
494 }; 494 };
495 495
496 pwm: pwm@12dd0000 { 496 pwm: pwm@12dd0000 {
497 compatible = "samsung,exynos4210-pwm"; 497 compatible = "samsung,exynos4210-pwm";
498 reg = <0x12dd0000 0x100>; 498 reg = <0x12dd0000 0x100>;
499 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 499 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
500 #pwm-cells = <3>; 500 #pwm-cells = <3>;
501 clocks = <&clock CLK_PWM>; 501 clocks = <&clock CLK_PWM>;
502 clock-names = "timers"; 502 clock-names = "timers";
503 }; 503 };
504 504
505 dp_phy: video-phy@10040728 { 505 dp_phy: video-phy@10040728 {
506 compatible = "samsung,exynos5250-dp-video-phy"; 506 compatible = "samsung,exynos5250-dp-video-phy";
507 reg = <0x10040728 4>; 507 reg = <0x10040728 4>;
508 #phy-cells = <0>; 508 #phy-cells = <0>;
509 }; 509 };
510 510
511 dp: dp-controller@145B0000 { 511 dp: dp-controller@145B0000 {
512 clocks = <&clock CLK_DP1>; 512 clocks = <&clock CLK_DP1>;
513 clock-names = "dp"; 513 clock-names = "dp";
514 phys = <&dp_phy>; 514 phys = <&dp_phy>;
515 phy-names = "dp"; 515 phy-names = "dp";
516 }; 516 };
517 517
518 mipi_phy: video-phy@10040714 { 518 mipi_phy: video-phy@10040714 {
519 compatible = "samsung,s5pv210-mipi-video-phy"; 519 compatible = "samsung,s5pv210-mipi-video-phy";
520 reg = <0x10040714 12>; 520 reg = <0x10040714 12>;
521 #phy-cells = <1>; 521 #phy-cells = <1>;
522 }; 522 };
523 523
524 dsi@14500000 { 524 dsi@14500000 {
525 compatible = "samsung,exynos5410-mipi-dsi"; 525 compatible = "samsung,exynos5410-mipi-dsi";
526 reg = <0x14500000 0x10000>; 526 reg = <0x14500000 0x10000>;
527 interrupts = <0 82 0>; 527 interrupts = <0 82 0>;
528 phys = <&mipi_phy 1>; 528 phys = <&mipi_phy 1>;
529 phy-names = "dsim"; 529 phy-names = "dsim";
530 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; 530 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
531 clock-names = "bus_clk", "pll_clk"; 531 clock-names = "bus_clk", "pll_clk";
532 #address-cells = <1>; 532 #address-cells = <1>;
533 #size-cells = <0>; 533 #size-cells = <0>;
534 status = "disabled"; 534 status = "disabled";
535 }; 535 };
536 536
537 fimd: fimd@14400000 { 537 fimd: fimd@14400000 {
538 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 538 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
539 clock-names = "sclk_fimd", "fimd"; 539 clock-names = "sclk_fimd", "fimd";
540 }; 540 };
541 541
542 adc: adc@12D10000 { 542 adc: adc@12D10000 {
543 compatible = "samsung,exynos-adc-v2"; 543 compatible = "samsung,exynos-adc-v2";
544 reg = <0x12D10000 0x100>; 544 reg = <0x12D10000 0x100>;
545 interrupts = <0 106 0>; 545 interrupts = <0 106 0>;
546 clocks = <&clock CLK_TSADC>; 546 clocks = <&clock CLK_TSADC>;
547 clock-names = "adc"; 547 clock-names = "adc";
548 #io-channel-cells = <1>; 548 #io-channel-cells = <1>;
549 io-channel-ranges; 549 io-channel-ranges;
550 samsung,syscon-phandle = <&pmu_system_controller>; 550 samsung,syscon-phandle = <&pmu_system_controller>;
551 status = "disabled"; 551 status = "disabled";
552 }; 552 };
553 553
554 i2c_0: i2c@12C60000 { 554 i2c_0: i2c@12C60000 {
555 compatible = "samsung,s3c2440-i2c"; 555 compatible = "samsung,s3c2440-i2c";
556 reg = <0x12C60000 0x100>; 556 reg = <0x12C60000 0x100>;
557 interrupts = <0 56 0>; 557 interrupts = <0 56 0>;
558 #address-cells = <1>; 558 #address-cells = <1>;
559 #size-cells = <0>; 559 #size-cells = <0>;
560 clocks = <&clock CLK_I2C0>; 560 clocks = <&clock CLK_I2C0>;
561 clock-names = "i2c"; 561 clock-names = "i2c";
562 pinctrl-names = "default"; 562 pinctrl-names = "default";
563 pinctrl-0 = <&i2c0_bus>; 563 pinctrl-0 = <&i2c0_bus>;
564 samsung,sysreg-phandle = <&sysreg_system_controller>; 564 samsung,sysreg-phandle = <&sysreg_system_controller>;
565 status = "disabled"; 565 status = "disabled";
566 }; 566 };
567 567
568 i2c_1: i2c@12C70000 { 568 i2c_1: i2c@12C70000 {
569 compatible = "samsung,s3c2440-i2c"; 569 compatible = "samsung,s3c2440-i2c";
570 reg = <0x12C70000 0x100>; 570 reg = <0x12C70000 0x100>;
571 interrupts = <0 57 0>; 571 interrupts = <0 57 0>;
572 #address-cells = <1>; 572 #address-cells = <1>;
573 #size-cells = <0>; 573 #size-cells = <0>;
574 clocks = <&clock CLK_I2C1>; 574 clocks = <&clock CLK_I2C1>;
575 clock-names = "i2c"; 575 clock-names = "i2c";
576 pinctrl-names = "default"; 576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c1_bus>; 577 pinctrl-0 = <&i2c1_bus>;
578 samsung,sysreg-phandle = <&sysreg_system_controller>; 578 samsung,sysreg-phandle = <&sysreg_system_controller>;
579 status = "disabled"; 579 status = "disabled";
580 }; 580 };
581 581
582 i2c_2: i2c@12C80000 { 582 i2c_2: i2c@12C80000 {
583 compatible = "samsung,s3c2440-i2c"; 583 compatible = "samsung,s3c2440-i2c";
584 reg = <0x12C80000 0x100>; 584 reg = <0x12C80000 0x100>;
585 interrupts = <0 58 0>; 585 interrupts = <0 58 0>;
586 #address-cells = <1>; 586 #address-cells = <1>;
587 #size-cells = <0>; 587 #size-cells = <0>;
588 clocks = <&clock CLK_I2C2>; 588 clocks = <&clock CLK_I2C2>;
589 clock-names = "i2c"; 589 clock-names = "i2c";
590 pinctrl-names = "default"; 590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c2_bus>; 591 pinctrl-0 = <&i2c2_bus>;
592 samsung,sysreg-phandle = <&sysreg_system_controller>; 592 samsung,sysreg-phandle = <&sysreg_system_controller>;
593 status = "disabled"; 593 status = "disabled";
594 }; 594 };
595 595
596 i2c_3: i2c@12C90000 { 596 i2c_3: i2c@12C90000 {
597 compatible = "samsung,s3c2440-i2c"; 597 compatible = "samsung,s3c2440-i2c";
598 reg = <0x12C90000 0x100>; 598 reg = <0x12C90000 0x100>;
599 interrupts = <0 59 0>; 599 interrupts = <0 59 0>;
600 #address-cells = <1>; 600 #address-cells = <1>;
601 #size-cells = <0>; 601 #size-cells = <0>;
602 clocks = <&clock CLK_I2C3>; 602 clocks = <&clock CLK_I2C3>;
603 clock-names = "i2c"; 603 clock-names = "i2c";
604 pinctrl-names = "default"; 604 pinctrl-names = "default";
605 pinctrl-0 = <&i2c3_bus>; 605 pinctrl-0 = <&i2c3_bus>;
606 samsung,sysreg-phandle = <&sysreg_system_controller>; 606 samsung,sysreg-phandle = <&sysreg_system_controller>;
607 status = "disabled"; 607 status = "disabled";
608 }; 608 };
609 609
610 hsi2c_4: i2c@12CA0000 { 610 hsi2c_4: i2c@12CA0000 {
611 compatible = "samsung,exynos5-hsi2c"; 611 compatible = "samsung,exynos5-hsi2c";
612 reg = <0x12CA0000 0x1000>; 612 reg = <0x12CA0000 0x1000>;
613 interrupts = <0 60 0>; 613 interrupts = <0 60 0>;
614 #address-cells = <1>; 614 #address-cells = <1>;
615 #size-cells = <0>; 615 #size-cells = <0>;
616 pinctrl-names = "default"; 616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c4_hs_bus>; 617 pinctrl-0 = <&i2c4_hs_bus>;
618 clocks = <&clock CLK_USI0>; 618 clocks = <&clock CLK_USI0>;
619 clock-names = "hsi2c"; 619 clock-names = "hsi2c";
620 status = "disabled"; 620 status = "disabled";
621 }; 621 };
622 622
623 hsi2c_5: i2c@12CB0000 { 623 hsi2c_5: i2c@12CB0000 {
624 compatible = "samsung,exynos5-hsi2c"; 624 compatible = "samsung,exynos5-hsi2c";
625 reg = <0x12CB0000 0x1000>; 625 reg = <0x12CB0000 0x1000>;
626 interrupts = <0 61 0>; 626 interrupts = <0 61 0>;
627 #address-cells = <1>; 627 #address-cells = <1>;
628 #size-cells = <0>; 628 #size-cells = <0>;
629 pinctrl-names = "default"; 629 pinctrl-names = "default";
630 pinctrl-0 = <&i2c5_hs_bus>; 630 pinctrl-0 = <&i2c5_hs_bus>;
631 clocks = <&clock CLK_USI1>; 631 clocks = <&clock CLK_USI1>;
632 clock-names = "hsi2c"; 632 clock-names = "hsi2c";
633 status = "disabled"; 633 status = "disabled";
634 }; 634 };
635 635
636 hsi2c_6: i2c@12CC0000 { 636 hsi2c_6: i2c@12CC0000 {
637 compatible = "samsung,exynos5-hsi2c"; 637 compatible = "samsung,exynos5-hsi2c";
638 reg = <0x12CC0000 0x1000>; 638 reg = <0x12CC0000 0x1000>;
639 interrupts = <0 62 0>; 639 interrupts = <0 62 0>;
640 #address-cells = <1>; 640 #address-cells = <1>;
641 #size-cells = <0>; 641 #size-cells = <0>;
642 pinctrl-names = "default"; 642 pinctrl-names = "default";
643 pinctrl-0 = <&i2c6_hs_bus>; 643 pinctrl-0 = <&i2c6_hs_bus>;
644 clocks = <&clock CLK_USI2>; 644 clocks = <&clock CLK_USI2>;
645 clock-names = "hsi2c"; 645 clock-names = "hsi2c";
646 status = "disabled"; 646 status = "disabled";
647 }; 647 };
648 648
649 hsi2c_7: i2c@12CD0000 { 649 hsi2c_7: i2c@12CD0000 {
650 compatible = "samsung,exynos5-hsi2c"; 650 compatible = "samsung,exynos5-hsi2c";
651 reg = <0x12CD0000 0x1000>; 651 reg = <0x12CD0000 0x1000>;
652 interrupts = <0 63 0>; 652 interrupts = <0 63 0>;
653 #address-cells = <1>; 653 #address-cells = <1>;
654 #size-cells = <0>; 654 #size-cells = <0>;
655 pinctrl-names = "default"; 655 pinctrl-names = "default";
656 pinctrl-0 = <&i2c7_hs_bus>; 656 pinctrl-0 = <&i2c7_hs_bus>;
657 clocks = <&clock CLK_USI3>; 657 clocks = <&clock CLK_USI3>;
658 clock-names = "hsi2c"; 658 clock-names = "hsi2c";
659 status = "disabled"; 659 status = "disabled";
660 }; 660 };
661 661
662 hsi2c_8: i2c@12E00000 { 662 hsi2c_8: i2c@12E00000 {
663 compatible = "samsung,exynos5-hsi2c"; 663 compatible = "samsung,exynos5-hsi2c";
664 reg = <0x12E00000 0x1000>; 664 reg = <0x12E00000 0x1000>;
665 interrupts = <0 87 0>; 665 interrupts = <0 87 0>;
666 #address-cells = <1>; 666 #address-cells = <1>;
667 #size-cells = <0>; 667 #size-cells = <0>;
668 pinctrl-names = "default"; 668 pinctrl-names = "default";
669 pinctrl-0 = <&i2c8_hs_bus>; 669 pinctrl-0 = <&i2c8_hs_bus>;
670 clocks = <&clock CLK_USI4>; 670 clocks = <&clock CLK_USI4>;
671 clock-names = "hsi2c"; 671 clock-names = "hsi2c";
672 status = "disabled"; 672 status = "disabled";
673 }; 673 };
674 674
675 hsi2c_9: i2c@12E10000 { 675 hsi2c_9: i2c@12E10000 {
676 compatible = "samsung,exynos5-hsi2c"; 676 compatible = "samsung,exynos5-hsi2c";
677 reg = <0x12E10000 0x1000>; 677 reg = <0x12E10000 0x1000>;
678 interrupts = <0 88 0>; 678 interrupts = <0 88 0>;
679 #address-cells = <1>; 679 #address-cells = <1>;
680 #size-cells = <0>; 680 #size-cells = <0>;
681 pinctrl-names = "default"; 681 pinctrl-names = "default";
682 pinctrl-0 = <&i2c9_hs_bus>; 682 pinctrl-0 = <&i2c9_hs_bus>;
683 clocks = <&clock CLK_USI5>; 683 clocks = <&clock CLK_USI5>;
684 clock-names = "hsi2c"; 684 clock-names = "hsi2c";
685 status = "disabled"; 685 status = "disabled";
686 }; 686 };
687 687
688 hsi2c_10: i2c@12E20000 { 688 hsi2c_10: i2c@12E20000 {
689 compatible = "samsung,exynos5-hsi2c"; 689 compatible = "samsung,exynos5-hsi2c";
690 reg = <0x12E20000 0x1000>; 690 reg = <0x12E20000 0x1000>;
691 interrupts = <0 203 0>; 691 interrupts = <0 203 0>;
692 #address-cells = <1>; 692 #address-cells = <1>;
693 #size-cells = <0>; 693 #size-cells = <0>;
694 pinctrl-names = "default"; 694 pinctrl-names = "default";
695 pinctrl-0 = <&i2c10_hs_bus>; 695 pinctrl-0 = <&i2c10_hs_bus>;
696 clocks = <&clock CLK_USI6>; 696 clocks = <&clock CLK_USI6>;
697 clock-names = "hsi2c"; 697 clock-names = "hsi2c";
698 status = "disabled"; 698 status = "disabled";
699 }; 699 };
700 700
701 hdmi: hdmi@14530000 { 701 hdmi: hdmi@14530000 {
702 compatible = "samsung,exynos5420-hdmi"; 702 compatible = "samsung,exynos5420-hdmi";
703 reg = <0x14530000 0x70000>; 703 reg = <0x14530000 0x70000>;
704 interrupts = <0 95 0>; 704 interrupts = <0 95 0>;
705 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 705 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
706 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 706 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
707 <&clock CLK_MOUT_HDMI>; 707 <&clock CLK_MOUT_HDMI>;
708 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 708 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
709 "sclk_hdmiphy", "mout_hdmi"; 709 "sclk_hdmiphy", "mout_hdmi";
710 phy = <&hdmiphy>; 710 phy = <&hdmiphy>;
711 samsung,syscon-phandle = <&pmu_system_controller>; 711 samsung,syscon-phandle = <&pmu_system_controller>;
712 status = "disabled"; 712 status = "disabled";
713 }; 713 };
714 714
715 hdmiphy: hdmiphy@145D0000 { 715 hdmiphy: hdmiphy@145D0000 {
716 reg = <0x145D0000 0x20>; 716 reg = <0x145D0000 0x20>;
717 }; 717 };
718 718
719 mixer: mixer@14450000 { 719 mixer: mixer@14450000 {
720 compatible = "samsung,exynos5420-mixer"; 720 compatible = "samsung,exynos5420-mixer";
721 reg = <0x14450000 0x10000>; 721 reg = <0x14450000 0x10000>;
722 interrupts = <0 94 0>; 722 interrupts = <0 94 0>;
723 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 723 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
724 clock-names = "mixer", "sclk_hdmi"; 724 clock-names = "mixer", "sclk_hdmi";
725 }; 725 };
726 726
727 gsc_0: video-scaler@13e00000 { 727 gsc_0: video-scaler@13e00000 {
728 compatible = "samsung,exynos5-gsc"; 728 compatible = "samsung,exynos5-gsc";
729 reg = <0x13e00000 0x1000>; 729 reg = <0x13e00000 0x1000>;
730 interrupts = <0 85 0>; 730 interrupts = <0 85 0>;
731 clocks = <&clock CLK_GSCL0>; 731 clocks = <&clock CLK_GSCL0>;
732 clock-names = "gscl"; 732 clock-names = "gscl";
733 samsung,power-domain = <&gsc_pd>; 733 samsung,power-domain = <&gsc_pd>;
734 }; 734 };
735 735
736 gsc_1: video-scaler@13e10000 { 736 gsc_1: video-scaler@13e10000 {
737 compatible = "samsung,exynos5-gsc"; 737 compatible = "samsung,exynos5-gsc";
738 reg = <0x13e10000 0x1000>; 738 reg = <0x13e10000 0x1000>;
739 interrupts = <0 86 0>; 739 interrupts = <0 86 0>;
740 clocks = <&clock CLK_GSCL1>; 740 clocks = <&clock CLK_GSCL1>;
741 clock-names = "gscl"; 741 clock-names = "gscl";
742 samsung,power-domain = <&gsc_pd>; 742 samsung,power-domain = <&gsc_pd>;
743 }; 743 };
744 744
745 pmu_system_controller: system-controller@10040000 { 745 pmu_system_controller: system-controller@10040000 {
746 compatible = "samsung,exynos5420-pmu", "syscon"; 746 compatible = "samsung,exynos5420-pmu", "syscon";
747 reg = <0x10040000 0x5000>; 747 reg = <0x10040000 0x5000>;
748 clock-names = "clkout16"; 748 clock-names = "clkout16";
749 clocks = <&clock CLK_FIN_PLL>; 749 clocks = <&clock CLK_FIN_PLL>;
750 #clock-cells = <1>; 750 #clock-cells = <1>;
751 }; 751 };
752 752
753 sysreg_system_controller: syscon@10050000 { 753 sysreg_system_controller: syscon@10050000 {
754 compatible = "samsung,exynos5-sysreg", "syscon"; 754 compatible = "samsung,exynos5-sysreg", "syscon";
755 reg = <0x10050000 0x5000>; 755 reg = <0x10050000 0x5000>;
756 }; 756 };
757 757
758 tmu_cpu0: tmu@10060000 { 758 tmu_cpu0: tmu@10060000 {
759 compatible = "samsung,exynos5420-tmu"; 759 compatible = "samsung,exynos5420-tmu";
760 reg = <0x10060000 0x100>; 760 reg = <0x10060000 0x100>;
761 interrupts = <0 65 0>; 761 interrupts = <0 65 0>;
762 clocks = <&clock CLK_TMU>; 762 clocks = <&clock CLK_TMU>;
763 clock-names = "tmu_apbif"; 763 clock-names = "tmu_apbif";
764 }; 764 };
765 765
766 tmu_cpu1: tmu@10064000 { 766 tmu_cpu1: tmu@10064000 {
767 compatible = "samsung,exynos5420-tmu"; 767 compatible = "samsung,exynos5420-tmu";
768 reg = <0x10064000 0x100>; 768 reg = <0x10064000 0x100>;
769 interrupts = <0 183 0>; 769 interrupts = <0 183 0>;
770 clocks = <&clock CLK_TMU>; 770 clocks = <&clock CLK_TMU>;
771 clock-names = "tmu_apbif"; 771 clock-names = "tmu_apbif";
772 }; 772 };
773 773
774 tmu_cpu2: tmu@10068000 { 774 tmu_cpu2: tmu@10068000 {
775 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 775 compatible = "samsung,exynos5420-tmu-ext-triminfo";
776 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 776 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
777 interrupts = <0 184 0>; 777 interrupts = <0 184 0>;
778 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 778 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
779 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 779 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
780 }; 780 };
781 781
782 tmu_cpu3: tmu@1006c000 { 782 tmu_cpu3: tmu@1006c000 {
783 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 783 compatible = "samsung,exynos5420-tmu-ext-triminfo";
784 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 784 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
785 interrupts = <0 185 0>; 785 interrupts = <0 185 0>;
786 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 786 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
787 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 787 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
788 }; 788 };
789 789
790 tmu_gpu: tmu@100a0000 { 790 tmu_gpu: tmu@100a0000 {
791 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 791 compatible = "samsung,exynos5420-tmu-ext-triminfo";
792 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 792 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
793 interrupts = <0 215 0>; 793 interrupts = <0 215 0>;
794 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 794 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
795 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 795 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
796 }; 796 };
797 797
798 watchdog: watchdog@101D0000 { 798 watchdog: watchdog@101D0000 {
799 compatible = "samsung,exynos5420-wdt"; 799 compatible = "samsung,exynos5420-wdt";
800 reg = <0x101D0000 0x100>; 800 reg = <0x101D0000 0x100>;
801 interrupts = <0 42 0>; 801 interrupts = <0 42 0>;
802 clocks = <&clock CLK_WDT>; 802 clocks = <&clock CLK_WDT>;
803 clock-names = "watchdog"; 803 clock-names = "watchdog";
804 samsung,syscon-phandle = <&pmu_system_controller>; 804 samsung,syscon-phandle = <&pmu_system_controller>;
805 }; 805 };
806 806
807 sss: sss@10830000 { 807 sss: sss@10830000 {
808 compatible = "samsung,exynos4210-secss"; 808 compatible = "samsung,exynos4210-secss";
809 reg = <0x10830000 0x10000>; 809 reg = <0x10830000 0x10000>;
810 interrupts = <0 112 0>; 810 interrupts = <0 112 0>;
811 clocks = <&clock CLK_SSS>; 811 clocks = <&clock CLK_SSS>;
812 clock-names = "secss"; 812 clock-names = "secss";
813 }; 813 };
814 814
815 usbdrd3_0: usb@12000000 { 815 usbdrd3_0: usb@12000000 {
816 compatible = "samsung,exynos5250-dwusb3"; 816 compatible = "samsung,exynos5250-dwusb3";
817 clocks = <&clock CLK_USBD300>; 817 clocks = <&clock CLK_USBD300>;
818 clock-names = "usbdrd30"; 818 clock-names = "usbdrd30";
819 #address-cells = <1>; 819 #address-cells = <1>;
820 #size-cells = <1>; 820 #size-cells = <1>;
821 ranges; 821 ranges;
822 822
823 usbdrd_dwc3_0: dwc3 { 823 usbdrd_dwc3_0: dwc3 {
824 compatible = "snps,dwc3"; 824 compatible = "snps,dwc3";
825 reg = <0x12000000 0x10000>; 825 reg = <0x12000000 0x10000>;
826 interrupts = <0 72 0>; 826 interrupts = <0 72 0>;
827 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; 827 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
828 phy-names = "usb2-phy", "usb3-phy"; 828 phy-names = "usb2-phy", "usb3-phy";
829 }; 829 };
830 }; 830 };
831 831
832 usbdrd_phy0: phy@12100000 { 832 usbdrd_phy0: phy@12100000 {
833 compatible = "samsung,exynos5420-usbdrd-phy"; 833 compatible = "samsung,exynos5420-usbdrd-phy";
834 reg = <0x12100000 0x100>; 834 reg = <0x12100000 0x100>;
835 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 835 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
836 clock-names = "phy", "ref"; 836 clock-names = "phy", "ref";
837 samsung,pmu-syscon = <&pmu_system_controller>; 837 samsung,pmu-syscon = <&pmu_system_controller>;
838 #phy-cells = <1>; 838 #phy-cells = <1>;
839 }; 839 };
840 840
841 usbdrd3_1: usb@12400000 { 841 usbdrd3_1: usb@12400000 {
842 compatible = "samsung,exynos5250-dwusb3"; 842 compatible = "samsung,exynos5250-dwusb3";
843 clocks = <&clock CLK_USBD301>; 843 clocks = <&clock CLK_USBD301>;
844 clock-names = "usbdrd30"; 844 clock-names = "usbdrd30";
845 #address-cells = <1>; 845 #address-cells = <1>;
846 #size-cells = <1>; 846 #size-cells = <1>;
847 ranges; 847 ranges;
848 848
849 usbdrd_dwc3_1: dwc3 { 849 usbdrd_dwc3_1: dwc3 {
850 compatible = "snps,dwc3"; 850 compatible = "snps,dwc3";
851 reg = <0x12400000 0x10000>; 851 reg = <0x12400000 0x10000>;
852 interrupts = <0 73 0>; 852 interrupts = <0 73 0>;
853 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; 853 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
854 phy-names = "usb2-phy", "usb3-phy"; 854 phy-names = "usb2-phy", "usb3-phy";
855 }; 855 };
856 }; 856 };
857 857
858 usbdrd_phy1: phy@12500000 { 858 usbdrd_phy1: phy@12500000 {
859 compatible = "samsung,exynos5420-usbdrd-phy"; 859 compatible = "samsung,exynos5420-usbdrd-phy";
860 reg = <0x12500000 0x100>; 860 reg = <0x12500000 0x100>;
861 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 861 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
862 clock-names = "phy", "ref"; 862 clock-names = "phy", "ref";
863 samsung,pmu-syscon = <&pmu_system_controller>; 863 samsung,pmu-syscon = <&pmu_system_controller>;
864 #phy-cells = <1>; 864 #phy-cells = <1>;
865 }; 865 };
866 866
867 usbhost2: usb@12110000 { 867 usbhost2: usb@12110000 {
868 compatible = "samsung,exynos4210-ehci"; 868 compatible = "samsung,exynos4210-ehci";
869 reg = <0x12110000 0x100>; 869 reg = <0x12110000 0x100>;
870 interrupts = <0 71 0>; 870 interrupts = <0 71 0>;
871 871
872 clocks = <&clock CLK_USBH20>; 872 clocks = <&clock CLK_USBH20>;
873 clock-names = "usbhost"; 873 clock-names = "usbhost";
874 #address-cells = <1>; 874 #address-cells = <1>;
875 #size-cells = <0>; 875 #size-cells = <0>;
876 port@0 { 876 port@0 {
877 reg = <0>; 877 reg = <0>;
878 phys = <&usb2_phy 1>; 878 phys = <&usb2_phy 1>;
879 }; 879 };
880 }; 880 };
881 881
882 usbhost1: usb@12120000 { 882 usbhost1: usb@12120000 {
883 compatible = "samsung,exynos4210-ohci"; 883 compatible = "samsung,exynos4210-ohci";
884 reg = <0x12120000 0x100>; 884 reg = <0x12120000 0x100>;
885 interrupts = <0 71 0>; 885 interrupts = <0 71 0>;
886 886
887 clocks = <&clock CLK_USBH20>; 887 clocks = <&clock CLK_USBH20>;
888 clock-names = "usbhost"; 888 clock-names = "usbhost";
889 #address-cells = <1>; 889 #address-cells = <1>;
890 #size-cells = <0>; 890 #size-cells = <0>;
891 port@0 { 891 port@0 {
892 reg = <0>; 892 reg = <0>;
893 phys = <&usb2_phy 1>; 893 phys = <&usb2_phy 1>;
894 }; 894 };
895 }; 895 };
896 896
897 usb2_phy: phy@12130000 { 897 usb2_phy: phy@12130000 {
898 compatible = "samsung,exynos5250-usb2-phy"; 898 compatible = "samsung,exynos5250-usb2-phy";
899 reg = <0x12130000 0x100>; 899 reg = <0x12130000 0x100>;
900 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 900 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
901 clock-names = "phy", "ref"; 901 clock-names = "phy", "ref";
902 #phy-cells = <1>; 902 #phy-cells = <1>;
903 samsung,sysreg-phandle = <&sysreg_system_controller>; 903 samsung,sysreg-phandle = <&sysreg_system_controller>;
904 samsung,pmureg-phandle = <&pmu_system_controller>; 904 samsung,pmureg-phandle = <&pmu_system_controller>;
905 }; 905 };
906 }; 906 };
907 907