Eric Lee / smarc-ti-linux-kernel

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Commit 29ef7a3e26283606f181000b11e5fd37d73ab98f

Authored by Aneesh Kumar K.V
Committed by Benjamin Herrenschmidt
1 parent 2d6b63bbdd
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

powerpc/mm: Fix tlbie to add AVAL fields for 64K pages 

The if condition check was based on a draft ISA doc. Remove the same.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Showing 1 changed file with 16 additions and 22 deletions Side-by-side Diff

arch/powerpc/mm/hash_native_64.c
Diff comments   View file @ 29ef7a3
... ... @@ -82,17 +82,14 @@
82 82 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
83 83 va |= penc << 12;
84 84 va |= ssize << 8;
85   - /* Add AVAL part */
86   - if (psize != apsize) {
87   - /*
88   - * MPSS, 64K base page size and 16MB parge page size
89   - * We don't need all the bits, but rest of the bits
90   - * must be ignored by the processor.
91   - * vpn cover upto 65 bits of va. (0...65) and we need
92   - * 58..64 bits of va.
93   - */
94   - va |= (vpn & 0xfe);
95   - }
  85 + /*
  86 + * AVAL bits:
  87 + * We don't need all the bits, but rest of the bits
  88 + * must be ignored by the processor.
  89 + * vpn cover upto 65 bits of va. (0...65) and we need
  90 + * 58..64 bits of va.
  91 + */
  92 + va |= (vpn & 0xfe); /* AVAL */
96 93 va |= 1; /* L */
97 94 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
98 95 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
... ... @@ -133,17 +130,14 @@
133 130 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
134 131 va |= penc << 12;
135 132 va |= ssize << 8;
136   - /* Add AVAL part */
137   - if (psize != apsize) {
138   - /*
139   - * MPSS, 64K base page size and 16MB parge page size
140   - * We don't need all the bits, but rest of the bits
141   - * must be ignored by the processor.
142   - * vpn cover upto 65 bits of va. (0...65) and we need
143   - * 58..64 bits of va.
144   - */
145   - va |= (vpn & 0xfe);
146   - }
  133 + /*
  134 + * AVAL bits:
  135 + * We don't need all the bits, but rest of the bits
  136 + * must be ignored by the processor.
  137 + * vpn cover upto 65 bits of va. (0...65) and we need
  138 + * 58..64 bits of va.
  139 + */
  140 + va |= (vpn & 0xfe);
147 141 va |= 1; /* L */
148 142 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
149 143 : : "r"(va) : "memory");