Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 2d4712b7a615e5db3eb9a427f1722eec79681b4b

Authored by Linus Torvalds 2013-10-14 00:13:28 +0800

Merge branch 'parisc-3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc fixes from Helge Deller:
 "This patchset includes a bugfix to prevent a kernel crash when memory
  in page zero is accessed by the kernel itself, e.g.  via
  probe_kernel_read().

  Furthermore we now export flush_cache_page() which is needed
  (indirectly) by the lustre filesystem.  The other patches remove
  unused functions and optimizes the page fault handler to only evaluate
  variables if needed, which again protects against possible kernel
  crashes"

* 'parisc-3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: let probe_kernel_read() capture access to page zero
  parisc: optimize variable initialization in do_page_fault
  parisc: fix interruption handler to respect pagefault_disable()
  parisc: mark parisc_terminate() noreturn and cold.
  parisc: remove unused syscall_ipi() function.
  parisc: kill SMP single function call interrupt
  parisc: Export flush_cache_page() (needed by lustre)

Showing 6 changed files Inline Diff

arch/parisc/include/asm/traps.h
arch/parisc/kernel/cache.c
arch/parisc/kernel/smp.c
arch/parisc/kernel/traps.c
arch/parisc/lib/memcpy.c
arch/parisc/mm/fault.c

arch/parisc/include/asm/traps.h

Diff comments View file @ 2d4712b

1	#ifndef __ASM_TRAPS_H	1	#ifndef __ASM_TRAPS_H
2	#define __ASM_TRAPS_H	2	#define __ASM_TRAPS_H
3		3
4	#ifdef __KERNEL__	4	#ifdef __KERNEL__
5	struct pt_regs;	5	struct pt_regs;
6		6
7	/* traps.c */	7	/* traps.c */
8	void parisc_terminate(char msg, struct pt_regs regs,	8	void parisc_terminate(char msg, struct pt_regs regs,
9	int code, unsigned long offset);	9	int code, unsigned long offset) __noreturn __cold;
10		10
11	/* mm/fault.c */	11	/* mm/fault.c */
12	void do_page_fault(struct pt_regs *regs, unsigned long code,	12	void do_page_fault(struct pt_regs *regs, unsigned long code,
13	unsigned long address);	13	unsigned long address);
14	#endif	14	#endif
15		15
16	#endif	16	#endif
17		17

arch/parisc/kernel/cache.c

Diff comments View file @ 2d4712b

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
  * Copyright (C) 1999 SuSE GmbH Nuernberg
  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
  *
  * Cache and TLB management
  *
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
 #include <linux/pagemap.h>
 #include <linux/sched.h>
 #include <asm/pdc.h>
 #include <asm/cache.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
 #include <asm/sections.h>
 #include <asm/shmparam.h>
 int split_tlb __read_mostly;
 int dcache_stride __read_mostly;
 int icache_stride __read_mostly;
 EXPORT_SYMBOL(dcache_stride);
 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
 EXPORT_SYMBOL(flush_dcache_page_asm);
 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
 /* On some machines (e.g. ones with the Merced bus), there can be
  * only a single PxTLB broadcast at a time; this must be guaranteed
  * by software.  We put a spinlock around all TLB flushes  to
  * ensure this.
  */
 DEFINE_SPINLOCK(pa_tlb_lock);
 struct pdc_cache_info cache_info __read_mostly;
 #ifndef CONFIG_PA20
 static struct pdc_btlb_info btlb_info __read_mostly;
 #endif
 #ifdef CONFIG_SMP
 void
 flush_data_cache(void)
 {
 	on_each_cpu(flush_data_cache_local, NULL, 1);
 }
 void
 flush_instruction_cache(void)
 {
 	on_each_cpu(flush_instruction_cache_local, NULL, 1);
 }
 #endif
 void
 flush_cache_all_local(void)
 {
 	flush_instruction_cache_local(NULL);
 	flush_data_cache_local(NULL);
 }
 EXPORT_SYMBOL(flush_cache_all_local);
 /* Virtual address of pfn.  */
 #define pfn_va(pfn)	__va(PFN_PHYS(pfn))
 void
 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
 	unsigned long pfn = pte_pfn(*ptep);
 	struct page *page;
 	/* We don't have pte special.  As a result, we can be called with
 	   an invalid pfn and we don't need to flush the kernel dcache page.
 	   This occurs with FireGL card in C8000.  */
 	if (!pfn_valid(pfn))
 		return;
 	page = pfn_to_page(pfn);
 	if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
 		flush_kernel_dcache_page_addr(pfn_va(pfn));
 		clear_bit(PG_dcache_dirty, &page->flags);
 	} else if (parisc_requires_coherency())
 		flush_kernel_dcache_page_addr(pfn_va(pfn));
 }
 void
 show_cache_info(struct seq_file *m)
 {
 	char buf[32];
 	seq_printf(m, "I-cache\t\t: %ld KB\n",
 		cache_info.ic_size/1024 );
 	if (cache_info.dc_loop != 1)
 		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
 	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
 		cache_info.dc_size/1024,
 		(cache_info.dc_conf.cc_wt ? "WT":"WB"),
 		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
 		((cache_info.dc_loop == 1) ? "direct mapped" : buf));
 	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 		cache_info.it_size,
 		cache_info.dt_size,
 		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 	);
 #ifndef CONFIG_PA20
 	/* BTLB - Block TLB */
 	if (btlb_info.max_size==0) {
 		seq_printf(m, "BTLB\t\t: not supported\n" );
 	} else {
 		seq_printf(m,
 		"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 		btlb_info.max_size, (int)4096,
 		btlb_info.max_size>>8,
 		btlb_info.fixed_range_info.num_i,
 		btlb_info.fixed_range_info.num_d,
 		btlb_info.fixed_range_info.num_comb,
 		btlb_info.variable_range_info.num_i,
 		btlb_info.variable_range_info.num_d,
 		btlb_info.variable_range_info.num_comb
 		);
 	}
 #endif
 }
 void __init
 parisc_cache_init(void)
 {
 	if (pdc_cache_info(&cache_info) < 0)
 		panic("parisc_cache_init: pdc_cache_info failed");
 #if 0
 	printk("ic_size %lx dc_size %lx it_size %lx\n",
 		cache_info.ic_size,
 		cache_info.dc_size,
 		cache_info.it_size);
 	printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 		cache_info.dc_base,
 		cache_info.dc_stride,
 		cache_info.dc_count,
 		cache_info.dc_loop);
 	printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 		*(unsigned long *) (&cache_info.dc_conf),
 		cache_info.dc_conf.cc_alias,
 		cache_info.dc_conf.cc_block,
 		cache_info.dc_conf.cc_line,
 		cache_info.dc_conf.cc_shift);
 	printk("	wt %d sh %d cst %d hv %d\n",
 		cache_info.dc_conf.cc_wt,
 		cache_info.dc_conf.cc_sh,
 		cache_info.dc_conf.cc_cst,
 		cache_info.dc_conf.cc_hv);
 	printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 		cache_info.ic_base,
 		cache_info.ic_stride,
 		cache_info.ic_count,
 		cache_info.ic_loop);
 	printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 		*(unsigned long *) (&cache_info.ic_conf),
 		cache_info.ic_conf.cc_alias,
 		cache_info.ic_conf.cc_block,
 		cache_info.ic_conf.cc_line,
 		cache_info.ic_conf.cc_shift);
 	printk("	wt %d sh %d cst %d hv %d\n",
 		cache_info.ic_conf.cc_wt,
 		cache_info.ic_conf.cc_sh,
 		cache_info.ic_conf.cc_cst,
 		cache_info.ic_conf.cc_hv);
 	printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
 		cache_info.dt_conf.tc_sh,
 		cache_info.dt_conf.tc_page,
 		cache_info.dt_conf.tc_cst,
 		cache_info.dt_conf.tc_aid,
 		cache_info.dt_conf.tc_pad1);
 	printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
 		cache_info.it_conf.tc_sh,
 		cache_info.it_conf.tc_page,
 		cache_info.it_conf.tc_cst,
 		cache_info.it_conf.tc_aid,
 		cache_info.it_conf.tc_pad1);
 #endif
 	split_tlb = 0;
 	if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 		if (cache_info.dt_conf.tc_sh == 2)
 			printk(KERN_WARNING "Unexpected TLB configuration. "
 			"Will flush I/D separately (could be optimized).\n");
 		split_tlb = 1;
 	}
 	/* "New and Improved" version from Jim Hull
 	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 	 * The following CAFL_STRIDE is an optimized version, see
 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
 	 */
 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 #undef CAFL_STRIDE
 #ifndef CONFIG_PA20
 	if (pdc_btlb_info(&btlb_info) < 0) {
 		memset(&btlb_info, 0, sizeof btlb_info);
 	}
 #endif
 	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 						PDC_MODEL_NVA_UNSUPPORTED) {
 		printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 #if 0
 		panic("SMP kernel required to avoid non-equivalent aliasing");
 #endif
 	}
 }
 void disable_sr_hashing(void)
 {
 	int srhash_type, retval;
 	unsigned long space_bits;
 	switch (boot_cpu_data.cpu_type) {
 	case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 		BUG();
 		return;
 	case pcxs:
 	case pcxt:
 	case pcxt_:
 		srhash_type = SRHASH_PCXST;
 		break;
 	case pcxl:
 		srhash_type = SRHASH_PCXL;
 		break;
 	case pcxl2: /* pcxl2 doesn't support space register hashing */
 		return;
 	default: /* Currently all PA2.0 machines use the same ins. sequence */
 		srhash_type = SRHASH_PA20;
 		break;
 	}
 	disable_sr_hashing_asm(srhash_type);
 	retval = pdc_spaceid_bits(&space_bits);
 	/* If this procedure isn't implemented, don't panic. */
 	if (retval < 0 && retval != PDC_BAD_OPTION)
 		panic("pdc_spaceid_bits call failed.\n");
 	if (space_bits != 0)
 		panic("SpaceID hashing is still on!\n");
 }
 static inline void
 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
 		   unsigned long physaddr)
 {
 	preempt_disable();
 	flush_dcache_page_asm(physaddr, vmaddr);
 	if (vma->vm_flags & VM_EXEC)
 		flush_icache_page_asm(physaddr, vmaddr);
 	preempt_enable();
 }
 void flush_dcache_page(struct page *page)
 {
 	struct address_space *mapping = page_mapping(page);
 	struct vm_area_struct *mpnt;
 	unsigned long offset;
 	unsigned long addr, old_addr = 0;
 	pgoff_t pgoff;
 	if (mapping && !mapping_mapped(mapping)) {
 		set_bit(PG_dcache_dirty, &page->flags);
 		return;
 	}
 	flush_kernel_dcache_page(page);
 	if (!mapping)
 		return;
 	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 	/* We have carefully arranged in arch_get_unmapped_area() that
 	 * *any* mappings of a file are always congruently mapped (whether
 	 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 	 * to flush one address here for them all to become coherent */
 	flush_dcache_mmap_lock(mapping);
 	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
 		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 		addr = mpnt->vm_start + offset;
 		/* The TLB is the engine of coherence on parisc: The
 		 * CPU is entitled to speculate any page with a TLB
 		 * mapping, so here we kill the mapping then flush the
 		 * page along a special flush only alias mapping.
 		 * This guarantees that the page is no-longer in the
 		 * cache for any process and nor may it be
 		 * speculatively read in (until the user or kernel
 		 * specifically accesses it, of course) */
 		flush_tlb_page(mpnt, addr);
 		if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
 			__flush_cache_page(mpnt, addr, page_to_phys(page));
 			if (old_addr)
 				printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
 			old_addr = addr;
 		}
 	}
 	flush_dcache_mmap_unlock(mapping);
 }
 EXPORT_SYMBOL(flush_dcache_page);
 /* Defined in arch/parisc/kernel/pacache.S */
 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
 EXPORT_SYMBOL(flush_data_cache_local);
 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
 int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
 void __init parisc_setup_cache_timing(void)
 {
 	unsigned long rangetime, alltime;
 	unsigned long size;
 	alltime = mfctl(16);
 	flush_data_cache();
 	alltime = mfctl(16) - alltime;
 	size = (unsigned long)(_end - _text);
 	rangetime = mfctl(16);
 	flush_kernel_dcache_range((unsigned long)_text, size);
 	rangetime = mfctl(16) - rangetime;
 	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
 		alltime, size, rangetime);
 	/* Racy, but if we see an intermediate value, it's ok too... */
 	parisc_cache_flush_threshold = size * alltime / rangetime;
 	parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
 	if (!parisc_cache_flush_threshold)
 		parisc_cache_flush_threshold = FLUSH_THRESHOLD;
 	if (parisc_cache_flush_threshold > cache_info.dc_size)
 		parisc_cache_flush_threshold = cache_info.dc_size;
 	printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
 }
 extern void purge_kernel_dcache_page_asm(unsigned long);
 extern void clear_user_page_asm(void *, unsigned long);
 extern void copy_user_page_asm(void *, void *, unsigned long);
 void flush_kernel_dcache_page_addr(void *addr)
 {
 	unsigned long flags;
 	flush_kernel_dcache_page_asm(addr);
 	purge_tlb_start(flags);
 	pdtlb_kernel(addr);
 	purge_tlb_end(flags);
 }
 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 void clear_user_page(void *vto, unsigned long vaddr, struct page *page)
 {
 	clear_page_asm(vto);
 	if (!parisc_requires_coherency())
 		flush_kernel_dcache_page_asm(vto);
 }
 EXPORT_SYMBOL(clear_user_page);
 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 	struct page *pg)
 {
 	/* Copy using kernel mapping.  No coherency is needed
 	   (all in kmap/kunmap) on machines that don't support
 	   non-equivalent aliasing.  However, the `from' page
 	   needs to be flushed before it can be accessed through
 	   the kernel mapping. */
 	preempt_disable();
 	flush_dcache_page_asm(__pa(vfrom), vaddr);
 	preempt_enable();
 	copy_page_asm(vto, vfrom);
 	if (!parisc_requires_coherency())
 		flush_kernel_dcache_page_asm(vto);
 }
 EXPORT_SYMBOL(copy_user_page);
 #ifdef CONFIG_PA8X00
 void kunmap_parisc(void *addr)
 {
 	if (parisc_requires_coherency())
 		flush_kernel_dcache_page_addr(addr);
 }
 EXPORT_SYMBOL(kunmap_parisc);
 #endif
 void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
 {
 	unsigned long flags;
 	/* Note: purge_tlb_entries can be called at startup with
 	   no context.  */
 	purge_tlb_start(flags);
 	mtsp(mm->context, 1);
 	pdtlb(addr);
 	pitlb(addr);
 	purge_tlb_end(flags);
 }
 EXPORT_SYMBOL(purge_tlb_entries);
 void __flush_tlb_range(unsigned long sid, unsigned long start,
 		       unsigned long end)
 {
 	unsigned long npages;
 	npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 	if (npages >= 512)  /* 2MB of space: arbitrary, should be tuned */
 		flush_tlb_all();
 	else {
 		unsigned long flags;
 		purge_tlb_start(flags);
 		mtsp(sid, 1);
 		if (split_tlb) {
 			while (npages--) {
 				pdtlb(start);
 				pitlb(start);
 				start += PAGE_SIZE;
 			}
 		} else {
 			while (npages--) {
 				pdtlb(start);
 				start += PAGE_SIZE;
 			}
 		}
 		purge_tlb_end(flags);
 	}
 }
 static void cacheflush_h_tmp_function(void *dummy)
 {
 	flush_cache_all_local();
 }
 void flush_cache_all(void)
 {
 	on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
 }
 static inline unsigned long mm_total_size(struct mm_struct *mm)
 {
 	struct vm_area_struct *vma;
 	unsigned long usize = 0;
 	for (vma = mm->mmap; vma; vma = vma->vm_next)
 		usize += vma->vm_end - vma->vm_start;
 	return usize;
 }
 static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
 {
 	pte_t *ptep = NULL;
 	if (!pgd_none(*pgd)) {
 		pud_t *pud = pud_offset(pgd, addr);
 		if (!pud_none(*pud)) {
 			pmd_t *pmd = pmd_offset(pud, addr);
 			if (!pmd_none(*pmd))
 				ptep = pte_offset_map(pmd, addr);
 		}
 	}
 	return ptep;
 }
 void flush_cache_mm(struct mm_struct *mm)
 {
 	struct vm_area_struct *vma;
 	pgd_t *pgd;
 	/* Flushing the whole cache on each cpu takes forever on
 	   rp3440, etc.  So, avoid it if the mm isn't too big.  */
 	if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
 		flush_cache_all();
 		return;
 	}
 	if (mm->context == mfsp(3)) {
 		for (vma = mm->mmap; vma; vma = vma->vm_next) {
 			flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
 			if ((vma->vm_flags & VM_EXEC) == 0)
 				continue;
 			flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
 		}
 		return;
 	}
 	pgd = mm->pgd;
 	for (vma = mm->mmap; vma; vma = vma->vm_next) {
 		unsigned long addr;
 		for (addr = vma->vm_start; addr < vma->vm_end;
 		     addr += PAGE_SIZE) {
 			unsigned long pfn;
 			pte_t *ptep = get_ptep(pgd, addr);
 			if (!ptep)
 				continue;
 			pfn = pte_pfn(*ptep);
 			if (!pfn_valid(pfn))
 				continue;
 			__flush_cache_page(vma, addr, PFN_PHYS(pfn));
 		}
 	}
 }
 void
 flush_user_dcache_range(unsigned long start, unsigned long end)
 {
 	if ((end - start) < parisc_cache_flush_threshold)
 		flush_user_dcache_range_asm(start,end);
 	else
 		flush_data_cache();
 }
 void
 flush_user_icache_range(unsigned long start, unsigned long end)
 {
 	if ((end - start) < parisc_cache_flush_threshold)
 		flush_user_icache_range_asm(start,end);
 	else
 		flush_instruction_cache();
 }
 void flush_cache_range(struct vm_area_struct *vma,
 		unsigned long start, unsigned long end)
 {
 	unsigned long addr;
 	pgd_t *pgd;
 	BUG_ON(!vma->vm_mm->context);
 	if ((end - start) >= parisc_cache_flush_threshold) {
 		flush_cache_all();
 		return;
 	}
 	if (vma->vm_mm->context == mfsp(3)) {
 		flush_user_dcache_range_asm(start, end);
 		if (vma->vm_flags & VM_EXEC)
 			flush_user_icache_range_asm(start, end);
 		return;
 	}
 	pgd = vma->vm_mm->pgd;
 	for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
 		unsigned long pfn;
 		pte_t *ptep = get_ptep(pgd, addr);
 		if (!ptep)
 			continue;
 		pfn = pte_pfn(*ptep);
 		if (pfn_valid(pfn))
 			__flush_cache_page(vma, addr, PFN_PHYS(pfn));
 	}
 }
 void
 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
 {
 	BUG_ON(!vma->vm_mm->context);
 	if (pfn_valid(pfn)) {
 		flush_tlb_page(vma, vmaddr);
 		__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
 	}
 }
+EXPORT_SYMBOL_GPL(flush_cache_page);
 #ifdef CONFIG_PARISC_TMPALIAS
 void clear_user_highpage(struct page *page, unsigned long vaddr)
 {
 	void *vto;
 	unsigned long flags;
 	/* Clear using TMPALIAS region.  The page doesn't need to
 	   be flushed but the kernel mapping needs to be purged.  */
 	vto = kmap_atomic(page);
 	/* The PA-RISC 2.0 Architecture book states on page F-6:
 	   "Before a write-capable translation is enabled, *all*
 	   non-equivalently-aliased translations must be removed
 	   from the page table and purged from the TLB.  (Note
 	   that the caches are not required to be flushed at this
 	   time.)  Before any non-equivalent aliased translation
 	   is re-enabled, the virtual address range for the writeable
 	   page (the entire page) must be flushed from the cache,
 	   and the write-capable translation removed from the page
 	   table and purged from the TLB."  */
 	purge_kernel_dcache_page_asm((unsigned long)vto);
 	purge_tlb_start(flags);
 	pdtlb_kernel(vto);
 	purge_tlb_end(flags);
 	preempt_disable();
 	clear_user_page_asm(vto, vaddr);
 	preempt_enable();
 	pagefault_enable();		/* kunmap_atomic(addr, KM_USER0); */
 }
 void copy_user_highpage(struct page *to, struct page *from,
 	unsigned long vaddr, struct vm_area_struct *vma)
 {
 	void *vfrom, *vto;
 	unsigned long flags;
 	/* Copy using TMPALIAS region.  This has the advantage
 	   that the `from' page doesn't need to be flushed.  However,
 	   the `to' page must be flushed in copy_user_page_asm since
 	   it can be used to bring in executable code.  */
 	vfrom = kmap_atomic(from);
 	vto = kmap_atomic(to);
 	purge_kernel_dcache_page_asm((unsigned long)vto);
 	purge_tlb_start(flags);
 	pdtlb_kernel(vto);
 	pdtlb_kernel(vfrom);
 	purge_tlb_end(flags);
 	preempt_disable();
 	copy_user_page_asm(vto, vfrom, vaddr);
 	flush_dcache_page_asm(__pa(vto), vaddr);
 	preempt_enable();
 	pagefault_enable();		/* kunmap_atomic(addr, KM_USER1); */
 	pagefault_enable();		/* kunmap_atomic(addr, KM_USER0); */
 }
 #endif /* CONFIG_PARISC_TMPALIAS */

arch/parisc/kernel/smp.c

Diff comments View file @ 2d4712b

 /*
 ** SMP Support
 **
 ** Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
 ** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
 ** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org>
 **
 ** Lots of stuff stolen from arch/alpha/kernel/smp.c
 ** ...and then parisc stole from arch/ia64/kernel/smp.c. Thanks David! :^)
 **
 ** Thanks to John Curry and Ullas Ponnadi. I learned a lot from their work.
 ** -grant (1/12/2001)
 **
 **	This program is free software; you can redistribute it and/or modify
 **	it under the terms of the GNU General Public License as published by
 **      the Free Software Foundation; either version 2 of the License, or
 **      (at your option) any later version.
 */
 #include <linux/types.h>
 #include <linux/spinlock.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/kernel_stat.h>
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/bitops.h>
 #include <linux/ftrace.h>
 #include <linux/cpu.h>
 #include <linux/atomic.h>
 #include <asm/current.h>
 #include <asm/delay.h>
 #include <asm/tlbflush.h>
 #include <asm/io.h>
 #include <asm/irq.h>		/* for CPU_IRQ_REGION and friends */
 #include <asm/mmu_context.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/unistd.h>
 #include <asm/cacheflush.h>
 #undef DEBUG_SMP
 #ifdef DEBUG_SMP
 static int smp_debug_lvl = 0;
 #define smp_debug(lvl, printargs...)		\
 		if (lvl >= smp_debug_lvl)	\
 			printk(printargs);
 #else
 #define smp_debug(lvl, ...)	do { } while(0)
 #endif /* DEBUG_SMP */
 volatile struct task_struct *smp_init_current_idle_task;
 /* track which CPU is booting */
 static volatile int cpu_now_booting;
 static int parisc_max_cpus = 1;
 static DEFINE_PER_CPU(spinlock_t, ipi_lock);
 enum ipi_message_type {
 	IPI_NOP=0,
 	IPI_RESCHEDULE=1,
 	IPI_CALL_FUNC,
-	IPI_CALL_FUNC_SINGLE,
 	IPI_CPU_START,
 	IPI_CPU_STOP,
 	IPI_CPU_TEST
 };
 /********** SMP inter processor interrupt and communication routines */
 #undef PER_CPU_IRQ_REGION
 #ifdef PER_CPU_IRQ_REGION
 /* XXX REVISIT Ignore for now.
 **    *May* need this "hook" to register IPI handler
 **    once we have perCPU ExtIntr switch tables.
 */
 static void
 ipi_init(int cpuid)
 {
 #error verify IRQ_OFFSET(IPI_IRQ) is ipi_interrupt() in new IRQ region
 	if(cpu_online(cpuid) )
 	{
 		switch_to_idle_task(current);
 	}
 	return;
 }
 #endif
 /*
 ** Yoink this CPU from the runnable list...
 **
 */
 static void
 halt_processor(void)
 {
 	/* REVISIT : redirect I/O Interrupts to another CPU? */
 	/* REVISIT : does PM *know* this CPU isn't available? */
 	set_cpu_online(smp_processor_id(), false);
 	local_irq_disable();
 	for (;;)
 		;
 }
 irqreturn_t __irq_entry
 ipi_interrupt(int irq, void *dev_id)
 {
 	int this_cpu = smp_processor_id();
 	struct cpuinfo_parisc *p = &per_cpu(cpu_data, this_cpu);
 	unsigned long ops;
 	unsigned long flags;
 	/* Count this now; we may make a call that never returns. */
 	inc_irq_stat(irq_call_count);
 	mb();	/* Order interrupt and bit testing. */
 	for (;;) {
 		spinlock_t *lock = &per_cpu(ipi_lock, this_cpu);
 		spin_lock_irqsave(lock, flags);
 		ops = p->pending_ipi;
 		p->pending_ipi = 0;
 		spin_unlock_irqrestore(lock, flags);
 		mb(); /* Order bit clearing and data access. */
 		if (!ops)
 		    break;
 		while (ops) {
 			unsigned long which = ffz(~ops);
 			ops &= ~(1 << which);
 			switch (which) {
 			case IPI_NOP:
 				smp_debug(100, KERN_DEBUG "CPU%d IPI_NOP\n", this_cpu);
 				break;
 			case IPI_RESCHEDULE:
 				smp_debug(100, KERN_DEBUG "CPU%d IPI_RESCHEDULE\n", this_cpu);
 				inc_irq_stat(irq_resched_count);
 				scheduler_ipi();
 				break;
 			case IPI_CALL_FUNC:
 				smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC\n", this_cpu);
 				generic_smp_call_function_interrupt();
 				break;
-			case IPI_CALL_FUNC_SINGLE:
-				smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC_SINGLE\n", this_cpu);
-				generic_smp_call_function_single_interrupt();
-				break;
 			case IPI_CPU_START:
 				smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_START\n", this_cpu);
 				break;
 			case IPI_CPU_STOP:
 				smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_STOP\n", this_cpu);
 				halt_processor();
 				break;
 			case IPI_CPU_TEST:
 				smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu);
 				break;
 			default:
 				printk(KERN_CRIT "Unknown IPI num on CPU%d: %lu\n",
 					this_cpu, which);
 				return IRQ_NONE;
 			} /* Switch */
 		/* let in any pending interrupts */
 		local_irq_enable();
 		local_irq_disable();
 		} /* while (ops) */
 	}
 	return IRQ_HANDLED;
 }
 static inline void
 ipi_send(int cpu, enum ipi_message_type op)
 {
 	struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpu);
 	spinlock_t *lock = &per_cpu(ipi_lock, cpu);
 	unsigned long flags;
 	spin_lock_irqsave(lock, flags);
 	p->pending_ipi |= 1 << op;
 	gsc_writel(IPI_IRQ - CPU_IRQ_BASE, p->hpa);
 	spin_unlock_irqrestore(lock, flags);
 }
 static void
 send_IPI_mask(const struct cpumask *mask, enum ipi_message_type op)
 {
 	int cpu;
 	for_each_cpu(cpu, mask)
 		ipi_send(cpu, op);
 }
 static inline void
 send_IPI_single(int dest_cpu, enum ipi_message_type op)
 {
 	BUG_ON(dest_cpu == NO_PROC_ID);
 	ipi_send(dest_cpu, op);
 }
 static inline void
 send_IPI_allbutself(enum ipi_message_type op)
 {
 	int i;
 	for_each_online_cpu(i) {
 		if (i != smp_processor_id())
 			send_IPI_single(i, op);
 	}
 }
 inline void
 smp_send_stop(void)	{ send_IPI_allbutself(IPI_CPU_STOP); }
 static inline void
 smp_send_start(void)	{ send_IPI_allbutself(IPI_CPU_START); }
 void
 smp_send_reschedule(int cpu) { send_IPI_single(cpu, IPI_RESCHEDULE); }
 void
 smp_send_all_nop(void)
 {
 	send_IPI_allbutself(IPI_NOP);
 }
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
 	send_IPI_mask(mask, IPI_CALL_FUNC);
 }
 void arch_send_call_function_single_ipi(int cpu)
 {
-	send_IPI_single(cpu, IPI_CALL_FUNC_SINGLE);
+	send_IPI_single(cpu, IPI_CALL_FUNC);
 }
 /*
  * Called by secondaries to update state and initialize CPU registers.
  */
 static void __init
 smp_cpu_init(int cpunum)
 {
 	extern int init_per_cpu(int);  /* arch/parisc/kernel/processor.c */
 	extern void init_IRQ(void);    /* arch/parisc/kernel/irq.c */
 	extern void start_cpu_itimer(void); /* arch/parisc/kernel/time.c */
 	/* Set modes and Enable floating point coprocessor */
 	(void) init_per_cpu(cpunum);
 	disable_sr_hashing();
 	mb();
 	/* Well, support 2.4 linux scheme as well. */
 	if (cpu_online(cpunum))	{
 		extern void machine_halt(void); /* arch/parisc.../process.c */
 		printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum);
 		machine_halt();
 	}
 	notify_cpu_starting(cpunum);
 	set_cpu_online(cpunum, true);
 	/* Initialise the idle task for this CPU */
 	atomic_inc(&init_mm.mm_count);
 	current->active_mm = &init_mm;
 	BUG_ON(current->mm);
 	enter_lazy_tlb(&init_mm, current);
 	init_IRQ();   /* make sure no IRQs are enabled or pending */
 	start_cpu_itimer();
 }
 /*
  * Slaves start using C here. Indirectly called from smp_slave_stext.
  * Do what start_kernel() and main() do for boot strap processor (aka monarch)
  */
 void __init smp_callin(void)
 {
 	int slave_id = cpu_now_booting;
 	smp_cpu_init(slave_id);
 	preempt_disable();
 	flush_cache_all_local(); /* start with known state */
 	flush_tlb_all_local(NULL);
 	local_irq_enable();  /* Interrupts have been off until now */
 	cpu_startup_entry(CPUHP_ONLINE);
 	/* NOTREACHED */
 	panic("smp_callin() AAAAaaaaahhhh....\n");
 }
 /*
  * Bring one cpu online.
  */
 int smp_boot_one_cpu(int cpuid, struct task_struct *idle)
 {
 	const struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpuid);
 	long timeout;
 	task_thread_info(idle)->cpu = cpuid;
 	/* Let _start know what logical CPU we're booting
 	** (offset into init_tasks[],cpu_data[])
 	*/
 	cpu_now_booting = cpuid;
 	/*
 	** boot strap code needs to know the task address since
 	** it also contains the process stack.
 	*/
 	smp_init_current_idle_task = idle ;
 	mb();
 	printk(KERN_INFO "Releasing cpu %d now, hpa=%lx\n", cpuid, p->hpa);
 	/*
 	** This gets PDC to release the CPU from a very tight loop.
 	**
 	** From the PA-RISC 2.0 Firmware Architecture Reference Specification:
 	** "The MEM_RENDEZ vector specifies the location of OS_RENDEZ which
 	** is executed after receiving the rendezvous signal (an interrupt to
 	** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the
 	** contents of memory are valid."
 	*/
 	gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, p->hpa);
 	mb();
 	/*
 	 * OK, wait a bit for that CPU to finish staggering about.
 	 * Slave will set a bit when it reaches smp_cpu_init().
 	 * Once the "monarch CPU" sees the bit change, it can move on.
 	 */
 	for (timeout = 0; timeout < 10000; timeout++) {
 		if(cpu_online(cpuid)) {
 			/* Which implies Slave has started up */
 			cpu_now_booting = 0;
 			smp_init_current_idle_task = NULL;
 			goto alive ;
 		}
 		udelay(100);
 		barrier();
 	}
 	printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
 	return -1;
 alive:
 	/* Remember the Slave data */
 	smp_debug(100, KERN_DEBUG "SMP: CPU:%d came alive after %ld _us\n",
 		cpuid, timeout * 100);
 	return 0;
 }
 void __init smp_prepare_boot_cpu(void)
 {
 	int bootstrap_processor = per_cpu(cpu_data, 0).cpuid;
 	/* Setup BSP mappings */
 	printk(KERN_INFO "SMP: bootstrap CPU ID is %d\n", bootstrap_processor);
 	set_cpu_online(bootstrap_processor, true);
 	set_cpu_present(bootstrap_processor, true);
 }
 /*
 ** inventory.c:do_inventory() hasn't yet been run and thus we
 ** don't 'discover' the additional CPUs until later.
 */
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
 	int cpu;
 	for_each_possible_cpu(cpu)
 		spin_lock_init(&per_cpu(ipi_lock, cpu));
 	init_cpu_present(cpumask_of(0));
 	parisc_max_cpus = max_cpus;
 	if (!max_cpus)
 		printk(KERN_INFO "SMP mode deactivated.\n");
 }
 void smp_cpus_done(unsigned int cpu_max)
 {
 	return;
 }
 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
 	if (cpu != 0 && cpu < parisc_max_cpus)
 		smp_boot_one_cpu(cpu, tidle);
 	return cpu_online(cpu) ? 0 : -ENOSYS;
 }
 #ifdef CONFIG_PROC_FS
 int __init
 setup_profiling_timer(unsigned int multiplier)
 {
 	return -EINVAL;
 }
 #endif

arch/parisc/kernel/traps.c

Diff comments View file @ 2d4712b

 /*
  *  linux/arch/parisc/traps.c
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
  *  Copyright (C) 1999, 2000  Philipp Rumpf <prumpf@tux.org>
  */
 /*
  * 'Traps.c' handles hardware traps and faults after we have saved some
  * state in 'asm.s'.
  */
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/errno.h>
 #include <linux/ptrace.h>
 #include <linux/timer.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/console.h>
 #include <linux/bug.h>
 #include <asm/assembly.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/traps.h>
 #include <asm/unaligned.h>
 #include <linux/atomic.h>
 #include <asm/smp.h>
 #include <asm/pdc.h>
 #include <asm/pdc_chassis.h>
 #include <asm/unwind.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
 #include "../math-emu/math-emu.h"	/* for handle_fpe() */
 #define PRINT_USER_FAULTS /* (turn this on if you want user faults to be */
 			  /*  dumped to the console via printk)          */
 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK)
 DEFINE_SPINLOCK(pa_dbit_lock);
 #endif
 static void parisc_show_stack(struct task_struct *task, unsigned long *sp,
 	struct pt_regs *regs);
 static int printbinary(char *buf, unsigned long x, int nbits)
 {
 	unsigned long mask = 1UL << (nbits - 1);
 	while (mask != 0) {
 		*buf++ = (mask & x ? '1' : '0');
 		mask >>= 1;
 	}
 	*buf = '\0';
 	return nbits;
 }
 #ifdef CONFIG_64BIT
 #define RFMT "%016lx"
 #else
 #define RFMT "%08lx"
 #endif
 #define FFMT "%016llx"	/* fpregs are 64-bit always */
 #define PRINTREGS(lvl,r,f,fmt,x)	\
 	printk("%s%s%02d-%02d  " fmt " " fmt " " fmt " " fmt "\n",	\
 		lvl, f, (x), (x+3), (r)[(x)+0], (r)[(x)+1],		\
 		(r)[(x)+2], (r)[(x)+3])
 static void print_gr(char *level, struct pt_regs *regs)
 {
 	int i;
 	char buf[64];
 	printk("%s\n", level);
 	printk("%s     YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI\n", level);
 	printbinary(buf, regs->gr[0], 32);
 	printk("%sPSW: %s %s\n", level, buf, print_tainted());
 	for (i = 0; i < 32; i += 4)
 		PRINTREGS(level, regs->gr, "r", RFMT, i);
 }
 static void print_fr(char *level, struct pt_regs *regs)
 {
 	int i;
 	char buf[64];
 	struct { u32 sw[2]; } s;
 	/* FR are 64bit everywhere. Need to use asm to get the content
 	 * of fpsr/fper1, and we assume that we won't have a FP Identify
 	 * in our way, otherwise we're screwed.
 	 * The fldd is used to restore the T-bit if there was one, as the
 	 * store clears it anyway.
 	 * PA2.0 book says "thou shall not use fstw on FPSR/FPERs" - T-Bone */
 	asm volatile ("fstd %%fr0,0(%1)	\n\t"
 		      "fldd 0(%1),%%fr0	\n\t"
 		      : "=m" (s) : "r" (&s) : "r0");
 	printk("%s\n", level);
 	printk("%s      VZOUICununcqcqcqcqcqcrmunTDVZOUI\n", level);
 	printbinary(buf, s.sw[0], 32);
 	printk("%sFPSR: %s\n", level, buf);
 	printk("%sFPER1: %08x\n", level, s.sw[1]);
 	/* here we'll print fr0 again, tho it'll be meaningless */
 	for (i = 0; i < 32; i += 4)
 		PRINTREGS(level, regs->fr, "fr", FFMT, i);
 }
 void show_regs(struct pt_regs *regs)
 {
 	int i, user;
 	char *level;
 	unsigned long cr30, cr31;
 	user = user_mode(regs);
 	level = user ? KERN_DEBUG : KERN_CRIT;
 	show_regs_print_info(level);
 	print_gr(level, regs);
 	for (i = 0; i < 8; i += 4)
 		PRINTREGS(level, regs->sr, "sr", RFMT, i);
 	if (user)
 		print_fr(level, regs);
 	cr30 = mfctl(30);
 	cr31 = mfctl(31);
 	printk("%s\n", level);
 	printk("%sIASQ: " RFMT " " RFMT " IAOQ: " RFMT " " RFMT "\n",
 	       level, regs->iasq[0], regs->iasq[1], regs->iaoq[0], regs->iaoq[1]);
 	printk("%s IIR: %08lx    ISR: " RFMT "  IOR: " RFMT "\n",
 	       level, regs->iir, regs->isr, regs->ior);
 	printk("%s CPU: %8d   CR30: " RFMT " CR31: " RFMT "\n",
 	       level, current_thread_info()->cpu, cr30, cr31);
 	printk("%s ORIG_R28: " RFMT "\n", level, regs->orig_r28);
 	if (user) {
 		printk("%s IAOQ[0]: " RFMT "\n", level, regs->iaoq[0]);
 		printk("%s IAOQ[1]: " RFMT "\n", level, regs->iaoq[1]);
 		printk("%s RP(r2): " RFMT "\n", level, regs->gr[2]);
 	} else {
 		printk("%s IAOQ[0]: %pS\n", level, (void *) regs->iaoq[0]);
 		printk("%s IAOQ[1]: %pS\n", level, (void *) regs->iaoq[1]);
 		printk("%s RP(r2): %pS\n", level, (void *) regs->gr[2]);
 		parisc_show_stack(current, NULL, regs);
 	}
 }
 static void do_show_stack(struct unwind_frame_info *info)
 {
 	int i = 1;
 	printk(KERN_CRIT "Backtrace:\n");
 	while (i <= 16) {
 		if (unwind_once(info) < 0 || info->ip == 0)
 			break;
 		if (__kernel_text_address(info->ip)) {
 			printk(KERN_CRIT " [<" RFMT ">] %pS\n",
 				info->ip, (void *) info->ip);
 			i++;
 		}
 	}
 	printk(KERN_CRIT "\n");
 }
 static void parisc_show_stack(struct task_struct *task, unsigned long *sp,
 	struct pt_regs *regs)
 {
 	struct unwind_frame_info info;
 	struct task_struct *t;
 	t = task ? task : current;
 	if (regs) {
 		unwind_frame_init(&info, t, regs);
 		goto show_stack;
 	}
 	if (t == current) {
 		unsigned long sp;
 HERE:
 		asm volatile ("copy %%r30, %0" : "=r"(sp));
 		{
 			struct pt_regs r;
 			memset(&r, 0, sizeof(struct pt_regs));
 			r.iaoq[0] = (unsigned long)&&HERE;
 			r.gr[2] = (unsigned long)__builtin_return_address(0);
 			r.gr[30] = sp;
 			unwind_frame_init(&info, current, &r);
 		}
 	} else {
 		unwind_frame_init_from_blocked_task(&info, t);
 	}
 show_stack:
 	do_show_stack(&info);
 }
 void show_stack(struct task_struct *t, unsigned long *sp)
 {
 	return parisc_show_stack(t, sp, NULL);
 }
 int is_valid_bugaddr(unsigned long iaoq)
 {
 	return 1;
 }
 void die_if_kernel(char *str, struct pt_regs *regs, long err)
 {
 	if (user_mode(regs)) {
 		if (err == 0)
 			return; /* STFU */
 		printk(KERN_CRIT "%s (pid %d): %s (code %ld) at " RFMT "\n",
 			current->comm, task_pid_nr(current), str, err, regs->iaoq[0]);
 #ifdef PRINT_USER_FAULTS
 		/* XXX for debugging only */
 		show_regs(regs);
 #endif
 		return;
 	}
 	oops_in_progress = 1;
 	oops_enter();
 	/* Amuse the user in a SPARC fashion */
 	if (err) printk(KERN_CRIT
 			"      _______________________________ \n"
 			"     < Your System ate a SPARC! Gah! >\n"
 			"      ------------------------------- \n"
 			"             \\   ^__^\n"
 			"                 (__)\\       )\\/\\\n"
 			"                  U  ||----w |\n"
 			"                     ||     ||\n");
 	/* unlock the pdc lock if necessary */
 	pdc_emergency_unlock();
 	/* maybe the kernel hasn't booted very far yet and hasn't been able
 	 * to initialize the serial or STI console. In that case we should
 	 * re-enable the pdc console, so that the user will be able to
 	 * identify the problem. */
 	if (!console_drivers)
 		pdc_console_restart();
 	if (err)
 		printk(KERN_CRIT "%s (pid %d): %s (code %ld)\n",
 			current->comm, task_pid_nr(current), str, err);
 	/* Wot's wrong wif bein' racy? */
 	if (current->thread.flags & PARISC_KERNEL_DEATH) {
 		printk(KERN_CRIT "%s() recursion detected.\n", __func__);
 		local_irq_enable();
 		while (1);
 	}
 	current->thread.flags |= PARISC_KERNEL_DEATH;
 	show_regs(regs);
 	dump_stack();
 	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 	if (in_interrupt())
 		panic("Fatal exception in interrupt");
 	if (panic_on_oops) {
 		printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
 		ssleep(5);
 		panic("Fatal exception");
 	}
 	oops_exit();
 	do_exit(SIGSEGV);
 }
-int syscall_ipi(int (*syscall) (struct pt_regs *), struct pt_regs *regs)
-{
-	return syscall(regs);
-}
 /* gdb uses break 4,8 */
 #define GDB_BREAK_INSN 0x10004
 static void handle_gdb_break(struct pt_regs *regs, int wot)
 {
 	struct siginfo si;
 	si.si_signo = SIGTRAP;
 	si.si_errno = 0;
 	si.si_code = wot;
 	si.si_addr = (void __user *) (regs->iaoq[0] & ~3);
 	force_sig_info(SIGTRAP, &si, current);
 }
 static void handle_break(struct pt_regs *regs)
 {
 	unsigned iir = regs->iir;
 	if (unlikely(iir == PARISC_BUG_BREAK_INSN && !user_mode(regs))) {
 		/* check if a BUG() or WARN() trapped here.  */
 		enum bug_trap_type tt;
 		tt = report_bug(regs->iaoq[0] & ~3, regs);
 		if (tt == BUG_TRAP_TYPE_WARN) {
 			regs->iaoq[0] += 4;
 			regs->iaoq[1] += 4;
 			return; /* return to next instruction when WARN_ON().  */
 		}
 		die_if_kernel("Unknown kernel breakpoint", regs,
 			(tt == BUG_TRAP_TYPE_NONE) ? 9 : 0);
 	}
 #ifdef PRINT_USER_FAULTS
 	if (unlikely(iir != GDB_BREAK_INSN)) {
 		printk(KERN_DEBUG "break %d,%d: pid=%d command='%s'\n",
 			iir & 31, (iir>>13) & ((1<<13)-1),
 			task_pid_nr(current), current->comm);
 		show_regs(regs);
 	}
 #endif
 	/* send standard GDB signal */
 	handle_gdb_break(regs, TRAP_BRKPT);
 }
 static void default_trap(int code, struct pt_regs *regs)
 {
 	printk(KERN_ERR "Trap %d on CPU %d\n", code, smp_processor_id());
 	show_regs(regs);
 }
 void (*cpu_lpmc) (int code, struct pt_regs *regs) __read_mostly = default_trap;
 void transfer_pim_to_trap_frame(struct pt_regs *regs)
 {
     register int i;
     extern unsigned int hpmc_pim_data[];
     struct pdc_hpmc_pim_11 *pim_narrow;
     struct pdc_hpmc_pim_20 *pim_wide;
     if (boot_cpu_data.cpu_type >= pcxu) {
 	pim_wide = (struct pdc_hpmc_pim_20 *)hpmc_pim_data;
 	/*
 	 * Note: The following code will probably generate a
 	 * bunch of truncation error warnings from the compiler.
 	 * Could be handled with an ifdef, but perhaps there
 	 * is a better way.
 	 */
 	regs->gr[0] = pim_wide->cr[22];
 	for (i = 1; i < 32; i++)
 	    regs->gr[i] = pim_wide->gr[i];
 	for (i = 0; i < 32; i++)
 	    regs->fr[i] = pim_wide->fr[i];
 	for (i = 0; i < 8; i++)
 	    regs->sr[i] = pim_wide->sr[i];
 	regs->iasq[0] = pim_wide->cr[17];
 	regs->iasq[1] = pim_wide->iasq_back;
 	regs->iaoq[0] = pim_wide->cr[18];
 	regs->iaoq[1] = pim_wide->iaoq_back;
 	regs->sar  = pim_wide->cr[11];
 	regs->iir  = pim_wide->cr[19];
 	regs->isr  = pim_wide->cr[20];
 	regs->ior  = pim_wide->cr[21];
     }
     else {
 	pim_narrow = (struct pdc_hpmc_pim_11 *)hpmc_pim_data;
 	regs->gr[0] = pim_narrow->cr[22];
 	for (i = 1; i < 32; i++)
 	    regs->gr[i] = pim_narrow->gr[i];
 	for (i = 0; i < 32; i++)
 	    regs->fr[i] = pim_narrow->fr[i];
 	for (i = 0; i < 8; i++)
 	    regs->sr[i] = pim_narrow->sr[i];
 	regs->iasq[0] = pim_narrow->cr[17];
 	regs->iasq[1] = pim_narrow->iasq_back;
 	regs->iaoq[0] = pim_narrow->cr[18];
 	regs->iaoq[1] = pim_narrow->iaoq_back;
 	regs->sar  = pim_narrow->cr[11];
 	regs->iir  = pim_narrow->cr[19];
 	regs->isr  = pim_narrow->cr[20];
 	regs->ior  = pim_narrow->cr[21];
     }
     /*
      * The following fields only have meaning if we came through
      * another path. So just zero them here.
      */
     regs->ksp = 0;
     regs->kpc = 0;
     regs->orig_r28 = 0;
 }
 /*
  * This routine is called as a last resort when everything else
  * has gone clearly wrong. We get called for faults in kernel space,
  * and HPMC's.
  */
 void parisc_terminate(char *msg, struct pt_regs *regs, int code, unsigned long offset)
 {
 	static DEFINE_SPINLOCK(terminate_lock);
 	oops_in_progress = 1;
 	set_eiem(0);
 	local_irq_disable();
 	spin_lock(&terminate_lock);
 	/* unlock the pdc lock if necessary */
 	pdc_emergency_unlock();
 	/* restart pdc console if necessary */
 	if (!console_drivers)
 		pdc_console_restart();
 	/* Not all paths will gutter the processor... */
 	switch(code){
 	case 1:
 		transfer_pim_to_trap_frame(regs);
 		break;
 	default:
 		/* Fall through */
 		break;
 	}
 	{
 		/* show_stack(NULL, (unsigned long *)regs->gr[30]); */
 		struct unwind_frame_info info;
 		unwind_frame_init(&info, current, regs);
 		do_show_stack(&info);
 	}
 	printk("\n");
 	printk(KERN_CRIT "%s: Code=%d regs=%p (Addr=" RFMT ")\n",
 			msg, code, regs, offset);
 	show_regs(regs);
 	spin_unlock(&terminate_lock);
 	/* put soft power button back under hardware control;
 	 * if the user had pressed it once at any time, the
 	 * system will shut down immediately right here. */
 	pdc_soft_power_button(0);
 	/* Call kernel panic() so reboot timeouts work properly
 	 * FIXME: This function should be on the list of
 	 * panic notifiers, and we should call panic
 	 * directly from the location that we wish.
 	 * e.g. We should not call panic from
 	 * parisc_terminate, but rather the oter way around.
 	 * This hack works, prints the panic message twice,
 	 * and it enables reboot timers!
 	 */
 	panic(msg);
 }
 void notrace handle_interruption(int code, struct pt_regs *regs)
 {
 	unsigned long fault_address = 0;
 	unsigned long fault_space = 0;
 	struct siginfo si;
 	if (code == 1)
 	    pdc_console_restart();  /* switch back to pdc if HPMC */
 	else
 	    local_irq_enable();
 	/* Security check:
 	 * If the priority level is still user, and the
 	 * faulting space is not equal to the active space
 	 * then the user is attempting something in a space
 	 * that does not belong to them. Kill the process.
 	 *
 	 * This is normally the situation when the user
 	 * attempts to jump into the kernel space at the
 	 * wrong offset, be it at the gateway page or a
 	 * random location.
 	 *
 	 * We cannot normally signal the process because it
 	 * could *be* on the gateway page, and processes
 	 * executing on the gateway page can't have signals
 	 * delivered.
 	 *
 	 * We merely readjust the address into the users
 	 * space, at a destination address of zero, and
 	 * allow processing to continue.
 	 */
 	if (((unsigned long)regs->iaoq[0] & 3) &&
 	    ((unsigned long)regs->iasq[0] != (unsigned long)regs->sr[7])) {
 		/* Kill the user process later */
 		regs->iaoq[0] = 0 | 3;
 		regs->iaoq[1] = regs->iaoq[0] + 4;
 		regs->iasq[0] = regs->iasq[1] = regs->sr[7];
 		regs->gr[0] &= ~PSW_B;
 		return;
 	}
 #if 0
 	printk(KERN_CRIT "Interruption # %d\n", code);
 #endif
 	switch(code) {
 	case  1:
 		/* High-priority machine check (HPMC) */
 		/* set up a new led state on systems shipped with a LED State panel */
 		pdc_chassis_send_status(PDC_CHASSIS_DIRECT_HPMC);
 		parisc_terminate("High Priority Machine Check (HPMC)",
 				regs, code, 0);
 		/* NOT REACHED */
 	case  2:
 		/* Power failure interrupt */
 		printk(KERN_CRIT "Power failure interrupt !\n");
 		return;
 	case  3:
 		/* Recovery counter trap */
 		regs->gr[0] &= ~PSW_R;
 		if (user_space(regs))
 			handle_gdb_break(regs, TRAP_TRACE);
 		/* else this must be the start of a syscall - just let it run */
 		return;
 	case  5:
 		/* Low-priority machine check */
 		pdc_chassis_send_status(PDC_CHASSIS_DIRECT_LPMC);
 		flush_cache_all();
 		flush_tlb_all();
 		cpu_lpmc(5, regs);
 		return;
 	case  6:
 		/* Instruction TLB miss fault/Instruction page fault */
 		fault_address = regs->iaoq[0];
 		fault_space   = regs->iasq[0];
 		break;
 	case  8:
 		/* Illegal instruction trap */
 		die_if_kernel("Illegal instruction", regs, code);
 		si.si_code = ILL_ILLOPC;
 		goto give_sigill;
 	case  9:
 		/* Break instruction trap */
 		handle_break(regs);
 		return;
 	case 10:
 		/* Privileged operation trap */
 		die_if_kernel("Privileged operation", regs, code);
 		si.si_code = ILL_PRVOPC;
 		goto give_sigill;
 	case 11:
 		/* Privileged register trap */
 		if ((regs->iir & 0xffdfffe0) == 0x034008a0) {
 			/* This is a MFCTL cr26/cr27 to gr instruction.
 			 * PCXS traps on this, so we need to emulate it.
 			 */
 			if (regs->iir & 0x00200000)
 				regs->gr[regs->iir & 0x1f] = mfctl(27);
 			else
 				regs->gr[regs->iir & 0x1f] = mfctl(26);
 			regs->iaoq[0] = regs->iaoq[1];
 			regs->iaoq[1] += 4;
 			regs->iasq[0] = regs->iasq[1];
 			return;
 		}
 		die_if_kernel("Privileged register usage", regs, code);
 		si.si_code = ILL_PRVREG;
 	give_sigill:
 		si.si_signo = SIGILL;
 		si.si_errno = 0;
 		si.si_addr = (void __user *) regs->iaoq[0];
 		force_sig_info(SIGILL, &si, current);
 		return;
 	case 12:
 		/* Overflow Trap, let the userland signal handler do the cleanup */
 		si.si_signo = SIGFPE;
 		si.si_code = FPE_INTOVF;
 		si.si_addr = (void __user *) regs->iaoq[0];
 		force_sig_info(SIGFPE, &si, current);
 		return;
 	case 13:
 		/* Conditional Trap
 		   The condition succeeds in an instruction which traps
 		   on condition  */
 		if(user_mode(regs)){
 			si.si_signo = SIGFPE;
 			/* Set to zero, and let the userspace app figure it out from
 			   the insn pointed to by si_addr */
 			si.si_code = 0;
 			si.si_addr = (void __user *) regs->iaoq[0];
 			force_sig_info(SIGFPE, &si, current);
 			return;
 		}
 		/* The kernel doesn't want to handle condition codes */
 		break;
 	case 14:
 		/* Assist Exception Trap, i.e. floating point exception. */
 		die_if_kernel("Floating point exception", regs, 0); /* quiet */
 		__inc_irq_stat(irq_fpassist_count);
 		handle_fpe(regs);
 		return;
 	case 15:
 		/* Data TLB miss fault/Data page fault */
 		/* Fall through */
 	case 16:
 		/* Non-access instruction TLB miss fault */
 		/* The instruction TLB entry needed for the target address of the FIC
 		   is absent, and hardware can't find it, so we get to cleanup */
 		/* Fall through */
 	case 17:
 		/* Non-access data TLB miss fault/Non-access data page fault */
 		/* FIXME:
 			 Still need to add slow path emulation code here!
 			 If the insn used a non-shadow register, then the tlb
 			 handlers could not have their side-effect (e.g. probe
 			 writing to a target register) emulated since rfir would
 			 erase the changes to said register. Instead we have to
 			 setup everything, call this function we are in, and emulate
 			 by hand. Technically we need to emulate:
 			 fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw
 		*/
 		fault_address = regs->ior;
 		fault_space = regs->isr;
 		break;
 	case 18:
 		/* PCXS only -- later cpu's split this into types 26,27 & 28 */
 		/* Check for unaligned access */
 		if (check_unaligned(regs)) {
 			handle_unaligned(regs);
 			return;
 		}
 		/* Fall Through */
 	case 26:
 		/* PCXL: Data memory access rights trap */
 		fault_address = regs->ior;
 		fault_space   = regs->isr;
 		break;
 	case 19:
 		/* Data memory break trap */
 		regs->gr[0] |= PSW_X; /* So we can single-step over the trap */
 		/* fall thru */
 	case 21:
 		/* Page reference trap */
 		handle_gdb_break(regs, TRAP_HWBKPT);
 		return;
 	case 25:
 		/* Taken branch trap */
 		regs->gr[0] &= ~PSW_T;
 		if (user_space(regs))
 			handle_gdb_break(regs, TRAP_BRANCH);
 		/* else this must be the start of a syscall - just let it
 		 * run.
 		 */
 		return;
 	case  7:
 		/* Instruction access rights */
 		/* PCXL: Instruction memory protection trap */
 		/*
 		 * This could be caused by either: 1) a process attempting
 		 * to execute within a vma that does not have execute
 		 * permission, or 2) an access rights violation caused by a
 		 * flush only translation set up by ptep_get_and_clear().
 		 * So we check the vma permissions to differentiate the two.
 		 * If the vma indicates we have execute permission, then
 		 * the cause is the latter one. In this case, we need to
 		 * call do_page_fault() to fix the problem.
 		 */
 		if (user_mode(regs)) {
 			struct vm_area_struct *vma;
 			down_read(&current->mm->mmap_sem);
 			vma = find_vma(current->mm,regs->iaoq[0]);
 			if (vma && (regs->iaoq[0] >= vma->vm_start)
 				&& (vma->vm_flags & VM_EXEC)) {
 				fault_address = regs->iaoq[0];
 				fault_space = regs->iasq[0];
 				up_read(&current->mm->mmap_sem);
 				break; /* call do_page_fault() */
 			}
 			up_read(&current->mm->mmap_sem);
 		}
 		/* Fall Through */
 	case 27:
 		/* Data memory protection ID trap */
 		if (code == 27 && !user_mode(regs) &&
 			fixup_exception(regs))
 			return;
 		die_if_kernel("Protection id trap", regs, code);
 		si.si_code = SEGV_MAPERR;
 		si.si_signo = SIGSEGV;
 		si.si_errno = 0;
 		if (code == 7)
 		    si.si_addr = (void __user *) regs->iaoq[0];
 		else
 		    si.si_addr = (void __user *) regs->ior;
 		force_sig_info(SIGSEGV, &si, current);
 		return;
 	case 28:
 		/* Unaligned data reference trap */
 		handle_unaligned(regs);
 		return;
 	default:
 		if (user_mode(regs)) {
 #ifdef PRINT_USER_FAULTS
 			printk(KERN_DEBUG "\nhandle_interruption() pid=%d command='%s'\n",
 			    task_pid_nr(current), current->comm);
 			show_regs(regs);
 #endif
 			/* SIGBUS, for lack of a better one. */
 			si.si_signo = SIGBUS;
 			si.si_code = BUS_OBJERR;
 			si.si_errno = 0;
 			si.si_addr = (void __user *) regs->ior;
 			force_sig_info(SIGBUS, &si, current);
 			return;
 		}
 		pdc_chassis_send_status(PDC_CHASSIS_DIRECT_PANIC);
 		parisc_terminate("Unexpected interruption", regs, code, 0);
 		/* NOT REACHED */
 	}
 	if (user_mode(regs)) {
 	    if ((fault_space >> SPACEID_SHIFT) != (regs->sr[7] >> SPACEID_SHIFT)) {
 #ifdef PRINT_USER_FAULTS
 		if (fault_space == 0)
 			printk(KERN_DEBUG "User Fault on Kernel Space ");
 		else
 			printk(KERN_DEBUG "User Fault (long pointer) (fault %d) ",
 			       code);
 		printk(KERN_CONT "pid=%d command='%s'\n",
 		       task_pid_nr(current), current->comm);
 		show_regs(regs);
 #endif
 		si.si_signo = SIGSEGV;
 		si.si_errno = 0;
 		si.si_code = SEGV_MAPERR;
 		si.si_addr = (void __user *) regs->ior;
 		force_sig_info(SIGSEGV, &si, current);
 		return;
 	    }
 	}
 	else {
 	    /*
-	     * The kernel should never fault on its own address space.
+	     * The kernel should never fault on its own address space,
+	     * unless pagefault_disable() was called before.
 	     */
-	    if (fault_space == 0)
+	    if (fault_space == 0 && !in_atomic())
 	    {
 		pdc_chassis_send_status(PDC_CHASSIS_DIRECT_PANIC);
 		parisc_terminate("Kernel Fault", regs, code, fault_address);
 	    }
 	}
 	do_page_fault(regs, code, fault_address);
 }
 int __init check_ivt(void *iva)
 {
 	extern u32 os_hpmc_size;
 	extern const u32 os_hpmc[];
 	int i;
 	u32 check = 0;
 	u32 *ivap;
 	u32 *hpmcp;
 	u32 length;
 	if (strcmp((char *)iva, "cows can fly"))
 		return -1;
 	ivap = (u32 *)iva;
 	for (i = 0; i < 8; i++)
 	    *ivap++ = 0;
 	/* Compute Checksum for HPMC handler */
 	length = os_hpmc_size;
 	ivap[7] = length;
 	hpmcp = (u32 *)os_hpmc;
 	for (i=0; i<length/4; i++)
 	    check += *hpmcp++;
 	for (i=0; i<8; i++)
 	    check += ivap[i];
 	ivap[5] = -check;
 	return 0;
 }
 #ifndef CONFIG_64BIT
 extern const void fault_vector_11;
 #endif
 extern const void fault_vector_20;
 void __init trap_init(void)
 {
 	void *iva;
 	if (boot_cpu_data.cpu_type >= pcxu)
 		iva = (void *) &fault_vector_20;
 	else
 #ifdef CONFIG_64BIT
 		panic("Can't boot 64-bit OS on PA1.1 processor!");
 #else
 		iva = (void *) &fault_vector_11;
 #endif
 	if (check_ivt(iva))
 		panic("IVT invalid");
 }

arch/parisc/lib/memcpy.c

Diff comments View file @ 2d4712b

 /*
  *    Optimized memory copy routines.
  *
  *    Copyright (C) 2004 Randolph Chung <tausq@debian.org>
  *    Copyright (C) 2013 Helge Deller <deller@gmx.de>
  *
  *    This program is free software; you can redistribute it and/or modify
  *    it under the terms of the GNU General Public License as published by
  *    the Free Software Foundation; either version 2, or (at your option)
  *    any later version.
  *
  *    This program is distributed in the hope that it will be useful,
  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *    GNU General Public License for more details.
  *
  *    You should have received a copy of the GNU General Public License
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *    Portions derived from the GNU C Library
  *    Copyright (C) 1991, 1997, 2003 Free Software Foundation, Inc.
  *
  * Several strategies are tried to try to get the best performance for various
  * conditions. In the optimal case, we copy 64-bytes in an unrolled loop using
  * fp regs. This is followed by loops that copy 32- or 16-bytes at a time using
  * general registers.  Unaligned copies are handled either by aligning the
  * destination and then using shift-and-write method, or in a few cases by
  * falling back to a byte-at-a-time copy.
  *
  * I chose to implement this in C because it is easier to maintain and debug,
  * and in my experiments it appears that the C code generated by gcc (3.3/3.4
  * at the time of writing) is fairly optimal. Unfortunately some of the
  * semantics of the copy routine (exception handling) is difficult to express
  * in C, so we have to play some tricks to get it to work.
  *
  * All the loads and stores are done via explicit asm() code in order to use
  * the right space registers.
  *
  * Testing with various alignments and buffer sizes shows that this code is
  * often >10x faster than a simple byte-at-a-time copy, even for strangely
  * aligned operands. It is interesting to note that the glibc version
  * of memcpy (written in C) is actually quite fast already. This routine is
  * able to beat it by 30-40% for aligned copies because of the loop unrolling,
  * but in some cases the glibc version is still slightly faster. This lends
  * more credibility that gcc can generate very good code as long as we are
  * careful.
  *
  * TODO:
  * - cache prefetching needs more experimentation to get optimal settings
  * - try not to use the post-increment address modifiers; they create additional
  *   interlocks
  * - replace byte-copy loops with stybs sequences
  */
 #ifdef __KERNEL__
 #include <linux/module.h>
 #include <linux/compiler.h>
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 #define s_space "%%sr1"
 #define d_space "%%sr2"
 #else
 #include "memcpy.h"
 #define s_space "%%sr0"
 #define d_space "%%sr0"
 #define pa_memcpy new2_copy
 #endif
 DECLARE_PER_CPU(struct exception_data, exception_data);
 #define preserve_branch(label)	do {					\
 	volatile int dummy = 0;						\
 	/* The following branch is never taken, it's just here to  */	\
 	/* prevent gcc from optimizing away our exception code. */ 	\
 	if (unlikely(dummy != dummy))					\
 		goto label;						\
 } while (0)
 #define get_user_space() (segment_eq(get_fs(), KERNEL_DS) ? 0 : mfsp(3))
 #define get_kernel_space() (0)
 #define MERGE(w0, sh_1, w1, sh_2)  ({					\
 	unsigned int _r;						\
 	asm volatile (							\
 	"mtsar %3\n"							\
 	"shrpw %1, %2, %%sar, %0\n"					\
 	: "=r"(_r)							\
 	: "r"(w0), "r"(w1), "r"(sh_2)					\
 	);								\
 	_r;								\
 })
 #define THRESHOLD	16
 #ifdef DEBUG_MEMCPY
 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
 #else
 #define DPRINTF(fmt, args...)
 #endif
 #define def_load_ai_insn(_insn,_sz,_tt,_s,_a,_t,_e)	\
 	__asm__ __volatile__ (				\
 	"1:\t" #_insn ",ma " #_sz "(" _s ",%1), %0\n\t"	\
 	ASM_EXCEPTIONTABLE_ENTRY(1b,_e)			\
 	: _tt(_t), "+r"(_a)				\
 	: 						\
 	: "r8")
 #define def_store_ai_insn(_insn,_sz,_tt,_s,_a,_t,_e) 	\
 	__asm__ __volatile__ (				\
 	"1:\t" #_insn ",ma %1, " #_sz "(" _s ",%0)\n\t"	\
 	ASM_EXCEPTIONTABLE_ENTRY(1b,_e)			\
 	: "+r"(_a) 					\
 	: _tt(_t)					\
 	: "r8")
 #define ldbma(_s, _a, _t, _e) def_load_ai_insn(ldbs,1,"=r",_s,_a,_t,_e)
 #define stbma(_s, _t, _a, _e) def_store_ai_insn(stbs,1,"r",_s,_a,_t,_e)
 #define ldwma(_s, _a, _t, _e) def_load_ai_insn(ldw,4,"=r",_s,_a,_t,_e)
 #define stwma(_s, _t, _a, _e) def_store_ai_insn(stw,4,"r",_s,_a,_t,_e)
 #define flddma(_s, _a, _t, _e) def_load_ai_insn(fldd,8,"=f",_s,_a,_t,_e)
 #define fstdma(_s, _t, _a, _e) def_store_ai_insn(fstd,8,"f",_s,_a,_t,_e)
 #define def_load_insn(_insn,_tt,_s,_o,_a,_t,_e) 	\
 	__asm__ __volatile__ (				\
 	"1:\t" #_insn " " #_o "(" _s ",%1), %0\n\t"	\
 	ASM_EXCEPTIONTABLE_ENTRY(1b,_e)			\
 	: _tt(_t) 					\
 	: "r"(_a)					\
 	: "r8")
 #define def_store_insn(_insn,_tt,_s,_t,_o,_a,_e) 	\
 	__asm__ __volatile__ (				\
 	"1:\t" #_insn " %0, " #_o "(" _s ",%1)\n\t" 	\
 	ASM_EXCEPTIONTABLE_ENTRY(1b,_e)			\
 	: 						\
 	: _tt(_t), "r"(_a)				\
 	: "r8")
 #define ldw(_s,_o,_a,_t,_e)	def_load_insn(ldw,"=r",_s,_o,_a,_t,_e)
 #define stw(_s,_t,_o,_a,_e) 	def_store_insn(stw,"r",_s,_t,_o,_a,_e)
 #ifdef  CONFIG_PREFETCH
 static inline void prefetch_src(const void *addr)
 {
 	__asm__("ldw 0(" s_space ",%0), %%r0" : : "r" (addr));
 }
 static inline void prefetch_dst(const void *addr)
 {
 	__asm__("ldd 0(" d_space ",%0), %%r0" : : "r" (addr));
 }
 #else
 #define prefetch_src(addr) do { } while(0)
 #define prefetch_dst(addr) do { } while(0)
 #endif
 #define PA_MEMCPY_OK		0
 #define PA_MEMCPY_LOAD_ERROR	1
 #define PA_MEMCPY_STORE_ERROR	2
 /* Copy from a not-aligned src to an aligned dst, using shifts. Handles 4 words
  * per loop.  This code is derived from glibc.
  */
 static inline unsigned long copy_dstaligned(unsigned long dst,
 					unsigned long src, unsigned long len)
 {
 	/* gcc complains that a2 and a3 may be uninitialized, but actually
 	 * they cannot be.  Initialize a2/a3 to shut gcc up.
 	 */
 	register unsigned int a0, a1, a2 = 0, a3 = 0;
 	int sh_1, sh_2;
 	/* prefetch_src((const void *)src); */
 	/* Calculate how to shift a word read at the memory operation
 	   aligned srcp to make it aligned for copy.  */
 	sh_1 = 8 * (src % sizeof(unsigned int));
 	sh_2 = 8 * sizeof(unsigned int) - sh_1;
 	/* Make src aligned by rounding it down.  */
 	src &= -sizeof(unsigned int);
 	switch (len % 4)
 	{
 		case 2:
 			/* a1 = ((unsigned int *) src)[0];
 			   a2 = ((unsigned int *) src)[1]; */
 			ldw(s_space, 0, src, a1, cda_ldw_exc);
 			ldw(s_space, 4, src, a2, cda_ldw_exc);
 			src -= 1 * sizeof(unsigned int);
 			dst -= 3 * sizeof(unsigned int);
 			len += 2;
 			goto do1;
 		case 3:
 			/* a0 = ((unsigned int *) src)[0];
 			   a1 = ((unsigned int *) src)[1]; */
 			ldw(s_space, 0, src, a0, cda_ldw_exc);
 			ldw(s_space, 4, src, a1, cda_ldw_exc);
 			src -= 0 * sizeof(unsigned int);
 			dst -= 2 * sizeof(unsigned int);
 			len += 1;
 			goto do2;
 		case 0:
 			if (len == 0)
 				return PA_MEMCPY_OK;
 			/* a3 = ((unsigned int *) src)[0];
 			   a0 = ((unsigned int *) src)[1]; */
 			ldw(s_space, 0, src, a3, cda_ldw_exc);
 			ldw(s_space, 4, src, a0, cda_ldw_exc);
 			src -=-1 * sizeof(unsigned int);
 			dst -= 1 * sizeof(unsigned int);
 			len += 0;
 			goto do3;
 		case 1:
 			/* a2 = ((unsigned int *) src)[0];
 			   a3 = ((unsigned int *) src)[1]; */
 			ldw(s_space, 0, src, a2, cda_ldw_exc);
 			ldw(s_space, 4, src, a3, cda_ldw_exc);
 			src -=-2 * sizeof(unsigned int);
 			dst -= 0 * sizeof(unsigned int);
 			len -= 1;
 			if (len == 0)
 				goto do0;
 			goto do4;			/* No-op.  */
 	}
 	do
 	{
 		/* prefetch_src((const void *)(src + 4 * sizeof(unsigned int))); */
 do4:
 		/* a0 = ((unsigned int *) src)[0]; */
 		ldw(s_space, 0, src, a0, cda_ldw_exc);
 		/* ((unsigned int *) dst)[0] = MERGE (a2, sh_1, a3, sh_2); */
 		stw(d_space, MERGE (a2, sh_1, a3, sh_2), 0, dst, cda_stw_exc);
 do3:
 		/* a1 = ((unsigned int *) src)[1]; */
 		ldw(s_space, 4, src, a1, cda_ldw_exc);
 		/* ((unsigned int *) dst)[1] = MERGE (a3, sh_1, a0, sh_2); */
 		stw(d_space, MERGE (a3, sh_1, a0, sh_2), 4, dst, cda_stw_exc);
 do2:
 		/* a2 = ((unsigned int *) src)[2]; */
 		ldw(s_space, 8, src, a2, cda_ldw_exc);
 		/* ((unsigned int *) dst)[2] = MERGE (a0, sh_1, a1, sh_2); */
 		stw(d_space, MERGE (a0, sh_1, a1, sh_2), 8, dst, cda_stw_exc);
 do1:
 		/* a3 = ((unsigned int *) src)[3]; */
 		ldw(s_space, 12, src, a3, cda_ldw_exc);
 		/* ((unsigned int *) dst)[3] = MERGE (a1, sh_1, a2, sh_2); */
 		stw(d_space, MERGE (a1, sh_1, a2, sh_2), 12, dst, cda_stw_exc);
 		src += 4 * sizeof(unsigned int);
 		dst += 4 * sizeof(unsigned int);
 		len -= 4;
 	}
 	while (len != 0);
 do0:
 	/* ((unsigned int *) dst)[0] = MERGE (a2, sh_1, a3, sh_2); */
 	stw(d_space, MERGE (a2, sh_1, a3, sh_2), 0, dst, cda_stw_exc);
 	preserve_branch(handle_load_error);
 	preserve_branch(handle_store_error);
 	return PA_MEMCPY_OK;
 handle_load_error:
 	__asm__ __volatile__ ("cda_ldw_exc:\n");
 	return PA_MEMCPY_LOAD_ERROR;
 handle_store_error:
 	__asm__ __volatile__ ("cda_stw_exc:\n");
 	return PA_MEMCPY_STORE_ERROR;
 }
 /* Returns PA_MEMCPY_OK, PA_MEMCPY_LOAD_ERROR or PA_MEMCPY_STORE_ERROR.
  * In case of an access fault the faulty address can be read from the per_cpu
  * exception data struct. */
 static unsigned long pa_memcpy_internal(void *dstp, const void *srcp,
 					unsigned long len)
 {
 	register unsigned long src, dst, t1, t2, t3;
 	register unsigned char *pcs, *pcd;
 	register unsigned int *pws, *pwd;
 	register double *pds, *pdd;
 	unsigned long ret;
 	src = (unsigned long)srcp;
 	dst = (unsigned long)dstp;
 	pcs = (unsigned char *)srcp;
 	pcd = (unsigned char *)dstp;
 	/* prefetch_src((const void *)srcp); */
 	if (len < THRESHOLD)
 		goto byte_copy;
 	/* Check alignment */
 	t1 = (src ^ dst);
 	if (unlikely(t1 & (sizeof(double)-1)))
 		goto unaligned_copy;
 	/* src and dst have same alignment. */
 	/* Copy bytes till we are double-aligned. */
 	t2 = src & (sizeof(double) - 1);
 	if (unlikely(t2 != 0)) {
 		t2 = sizeof(double) - t2;
 		while (t2 && len) {
 			/* *pcd++ = *pcs++; */
 			ldbma(s_space, pcs, t3, pmc_load_exc);
 			len--;
 			stbma(d_space, t3, pcd, pmc_store_exc);
 			t2--;
 		}
 	}
 	pds = (double *)pcs;
 	pdd = (double *)pcd;
 #if 0
 	/* Copy 8 doubles at a time */
 	while (len >= 8*sizeof(double)) {
 		register double r1, r2, r3, r4, r5, r6, r7, r8;
 		/* prefetch_src((char *)pds + L1_CACHE_BYTES); */
 		flddma(s_space, pds, r1, pmc_load_exc);
 		flddma(s_space, pds, r2, pmc_load_exc);
 		flddma(s_space, pds, r3, pmc_load_exc);
 		flddma(s_space, pds, r4, pmc_load_exc);
 		fstdma(d_space, r1, pdd, pmc_store_exc);
 		fstdma(d_space, r2, pdd, pmc_store_exc);
 		fstdma(d_space, r3, pdd, pmc_store_exc);
 		fstdma(d_space, r4, pdd, pmc_store_exc);
 #if 0
 		if (L1_CACHE_BYTES <= 32)
 			prefetch_src((char *)pds + L1_CACHE_BYTES);
 #endif
 		flddma(s_space, pds, r5, pmc_load_exc);
 		flddma(s_space, pds, r6, pmc_load_exc);
 		flddma(s_space, pds, r7, pmc_load_exc);
 		flddma(s_space, pds, r8, pmc_load_exc);
 		fstdma(d_space, r5, pdd, pmc_store_exc);
 		fstdma(d_space, r6, pdd, pmc_store_exc);
 		fstdma(d_space, r7, pdd, pmc_store_exc);
 		fstdma(d_space, r8, pdd, pmc_store_exc);
 		len -= 8*sizeof(double);
 	}
 #endif
 	pws = (unsigned int *)pds;
 	pwd = (unsigned int *)pdd;
 word_copy:
 	while (len >= 8*sizeof(unsigned int)) {
 		register unsigned int r1,r2,r3,r4,r5,r6,r7,r8;
 		/* prefetch_src((char *)pws + L1_CACHE_BYTES); */
 		ldwma(s_space, pws, r1, pmc_load_exc);
 		ldwma(s_space, pws, r2, pmc_load_exc);
 		ldwma(s_space, pws, r3, pmc_load_exc);
 		ldwma(s_space, pws, r4, pmc_load_exc);
 		stwma(d_space, r1, pwd, pmc_store_exc);
 		stwma(d_space, r2, pwd, pmc_store_exc);
 		stwma(d_space, r3, pwd, pmc_store_exc);
 		stwma(d_space, r4, pwd, pmc_store_exc);
 		ldwma(s_space, pws, r5, pmc_load_exc);
 		ldwma(s_space, pws, r6, pmc_load_exc);
 		ldwma(s_space, pws, r7, pmc_load_exc);
 		ldwma(s_space, pws, r8, pmc_load_exc);
 		stwma(d_space, r5, pwd, pmc_store_exc);
 		stwma(d_space, r6, pwd, pmc_store_exc);
 		stwma(d_space, r7, pwd, pmc_store_exc);
 		stwma(d_space, r8, pwd, pmc_store_exc);
 		len -= 8*sizeof(unsigned int);
 	}
 	while (len >= 4*sizeof(unsigned int)) {
 		register unsigned int r1,r2,r3,r4;
 		ldwma(s_space, pws, r1, pmc_load_exc);
 		ldwma(s_space, pws, r2, pmc_load_exc);
 		ldwma(s_space, pws, r3, pmc_load_exc);
 		ldwma(s_space, pws, r4, pmc_load_exc);
 		stwma(d_space, r1, pwd, pmc_store_exc);
 		stwma(d_space, r2, pwd, pmc_store_exc);
 		stwma(d_space, r3, pwd, pmc_store_exc);
 		stwma(d_space, r4, pwd, pmc_store_exc);
 		len -= 4*sizeof(unsigned int);
 	}
 	pcs = (unsigned char *)pws;
 	pcd = (unsigned char *)pwd;
 byte_copy:
 	while (len) {
 		/* *pcd++ = *pcs++; */
 		ldbma(s_space, pcs, t3, pmc_load_exc);
 		stbma(d_space, t3, pcd, pmc_store_exc);
 		len--;
 	}
 	return PA_MEMCPY_OK;
 unaligned_copy:
 	/* possibly we are aligned on a word, but not on a double... */
 	if (likely((t1 & (sizeof(unsigned int)-1)) == 0)) {
 		t2 = src & (sizeof(unsigned int) - 1);
 		if (unlikely(t2 != 0)) {
 			t2 = sizeof(unsigned int) - t2;
 			while (t2) {
 				/* *pcd++ = *pcs++; */
 				ldbma(s_space, pcs, t3, pmc_load_exc);
 				stbma(d_space, t3, pcd, pmc_store_exc);
 				len--;
 				t2--;
 			}
 		}
 		pws = (unsigned int *)pcs;
 		pwd = (unsigned int *)pcd;
 		goto word_copy;
 	}
 	/* Align the destination.  */
 	if (unlikely((dst & (sizeof(unsigned int) - 1)) != 0)) {
 		t2 = sizeof(unsigned int) - (dst & (sizeof(unsigned int) - 1));
 		while (t2) {
 			/* *pcd++ = *pcs++; */
 			ldbma(s_space, pcs, t3, pmc_load_exc);
 			stbma(d_space, t3, pcd, pmc_store_exc);
 			len--;
 			t2--;
 		}
 		dst = (unsigned long)pcd;
 		src = (unsigned long)pcs;
 	}
 	ret = copy_dstaligned(dst, src, len / sizeof(unsigned int));
 	if (ret)
 		return ret;
 	pcs += (len & -sizeof(unsigned int));
 	pcd += (len & -sizeof(unsigned int));
 	len %= sizeof(unsigned int);
 	preserve_branch(handle_load_error);
 	preserve_branch(handle_store_error);
 	goto byte_copy;
 handle_load_error:
 	__asm__ __volatile__ ("pmc_load_exc:\n");
 	return PA_MEMCPY_LOAD_ERROR;
 handle_store_error:
 	__asm__ __volatile__ ("pmc_store_exc:\n");
 	return PA_MEMCPY_STORE_ERROR;
 }
 /* Returns 0 for success, otherwise, returns number of bytes not transferred. */
 static unsigned long pa_memcpy(void *dstp, const void *srcp, unsigned long len)
 {
 	unsigned long ret, fault_addr, reference;
 	struct exception_data *d;
 	ret = pa_memcpy_internal(dstp, srcp, len);
 	if (likely(ret == PA_MEMCPY_OK))
 		return 0;
 	/* if a load or store fault occured we can get the faulty addr */
 	d = &__get_cpu_var(exception_data);
 	fault_addr = d->fault_addr;
 	/* error in load or store? */
 	if (ret == PA_MEMCPY_LOAD_ERROR)
 		reference = (unsigned long) srcp;
 	else
 		reference = (unsigned long) dstp;
 	DPRINTF("pa_memcpy: fault type = %lu, len=%lu fault_addr=%lu ref=%lu\n",
 		ret, len, fault_addr, reference);
 	if (fault_addr >= reference)
 		return len - (fault_addr - reference);
 	else
 		return len;
 }
 #ifdef __KERNEL__
 unsigned long copy_to_user(void __user *dst, const void *src, unsigned long len)
 {
 	mtsp(get_kernel_space(), 1);
 	mtsp(get_user_space(), 2);
 	return pa_memcpy((void __force *)dst, src, len);
 }
 EXPORT_SYMBOL(__copy_from_user);
 unsigned long __copy_from_user(void *dst, const void __user *src, unsigned long len)
 {
 	mtsp(get_user_space(), 1);
 	mtsp(get_kernel_space(), 2);
 	return pa_memcpy(dst, (void __force *)src, len);
 }
 unsigned long copy_in_user(void __user *dst, const void __user *src, unsigned long len)
 {
 	mtsp(get_user_space(), 1);
 	mtsp(get_user_space(), 2);
 	return pa_memcpy((void __force *)dst, (void __force *)src, len);
 }
 void * memcpy(void * dst,const void *src, size_t count)
 {
 	mtsp(get_kernel_space(), 1);
 	mtsp(get_kernel_space(), 2);
 	pa_memcpy(dst, src, count);
 	return dst;
 }
 EXPORT_SYMBOL(copy_to_user);
 EXPORT_SYMBOL(copy_from_user);
 EXPORT_SYMBOL(copy_in_user);
 EXPORT_SYMBOL(memcpy);
+long probe_kernel_read(void *dst, const void *src, size_t size)
+{
+	unsigned long addr = (unsigned long)src;
+	if (size < 0 || addr < PAGE_SIZE)
+		return -EFAULT;
+	/* check for I/O space F_EXTEND(0xfff00000) access as well? */
+	return __probe_kernel_read(dst, src, size);
+}
 #endif

arch/parisc/mm/fault.c

Diff comments View file @ 2d4712b

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  *
  * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
  * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
  * Copyright 1999 Hewlett Packard Co.
  *
  */
 #include <linux/mm.h>
 #include <linux/ptrace.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <asm/uaccess.h>
 #include <asm/traps.h>
 #define PRINT_USER_FAULTS /* (turn this on if you want user faults to be */
 			 /*  dumped to the console via printk)          */
 /* Various important other fields */
 #define bit22set(x)		(x & 0x00000200)
 #define bits23_25set(x)		(x & 0x000001c0)
 #define isGraphicsFlushRead(x)	((x & 0xfc003fdf) == 0x04001a80)
 				/* extended opcode is 0x6a */
 #define BITSSET		0x1c0	/* for identifying LDCW */
 DEFINE_PER_CPU(struct exception_data, exception_data);
 /*
  * parisc_acctyp(unsigned int inst) --
  *    Given a PA-RISC memory access instruction, determine if the
  *    the instruction would perform a memory read or memory write
  *    operation.
  *
  *    This function assumes that the given instruction is a memory access
  *    instruction (i.e. you should really only call it if you know that
  *    the instruction has generated some sort of a memory access fault).
  *
  * Returns:
  *   VM_READ  if read operation
  *   VM_WRITE if write operation
  *   VM_EXEC  if execute operation
  */
 static unsigned long
 parisc_acctyp(unsigned long code, unsigned int inst)
 {
 	if (code == 6 || code == 16)
 	    return VM_EXEC;
 	switch (inst & 0xf0000000) {
 	case 0x40000000: /* load */
 	case 0x50000000: /* new load */
 		return VM_READ;
 	case 0x60000000: /* store */
 	case 0x70000000: /* new store */
 		return VM_WRITE;
 	case 0x20000000: /* coproc */
 	case 0x30000000: /* coproc2 */
 		if (bit22set(inst))
 			return VM_WRITE;
 	case 0x0: /* indexed/memory management */
 		if (bit22set(inst)) {
 			/*
 			 * Check for the 'Graphics Flush Read' instruction.
 			 * It resembles an FDC instruction, except for bits
 			 * 20 and 21. Any combination other than zero will
 			 * utilize the block mover functionality on some
 			 * older PA-RISC platforms.  The case where a block
 			 * move is performed from VM to graphics IO space
 			 * should be treated as a READ.
 			 *
 			 * The significance of bits 20,21 in the FDC
 			 * instruction is:
 			 *
 			 *   00  Flush data cache (normal instruction behavior)
 			 *   01  Graphics flush write  (IO space -> VM)
 			 *   10  Graphics flush read   (VM -> IO space)
 			 *   11  Graphics flush read/write (VM <-> IO space)
 			 */
 			if (isGraphicsFlushRead(inst))
 				return VM_READ;
 			return VM_WRITE;
 		} else {
 			/*
 			 * Check for LDCWX and LDCWS (semaphore instructions).
 			 * If bits 23 through 25 are all 1's it is one of
 			 * the above two instructions and is a write.
 			 *
 			 * Note: With the limited bits we are looking at,
 			 * this will also catch PROBEW and PROBEWI. However,
 			 * these should never get in here because they don't
 			 * generate exceptions of the type:
 			 *   Data TLB miss fault/data page fault
 			 *   Data memory protection trap
 			 */
 			if (bits23_25set(inst) == BITSSET)
 				return VM_WRITE;
 		}
 		return VM_READ; /* Default */
 	}
 	return VM_READ; /* Default */
 }
 #undef bit22set
 #undef bits23_25set
 #undef isGraphicsFlushRead
 #undef BITSSET
 #if 0
 /* This is the treewalk to find a vma which is the highest that has
  * a start < addr.  We're using find_vma_prev instead right now, but
  * we might want to use this at some point in the future.  Probably
  * not, but I want it committed to CVS so I don't lose it :-)
  */
 			while (tree != vm_avl_empty) {
 				if (tree->vm_start > addr) {
 					tree = tree->vm_avl_left;
 				} else {
 					prev = tree;
 					if (prev->vm_next == NULL)
 						break;
 					if (prev->vm_next->vm_start > addr)
 						break;
 					tree = tree->vm_avl_right;
 				}
 			}
 #endif
 int fixup_exception(struct pt_regs *regs)
 {
 	const struct exception_table_entry *fix;
 	fix = search_exception_tables(regs->iaoq[0]);
 	if (fix) {
 		struct exception_data *d;
 		d = &__get_cpu_var(exception_data);
 		d->fault_ip = regs->iaoq[0];
 		d->fault_space = regs->isr;
 		d->fault_addr = regs->ior;
 		regs->iaoq[0] = ((fix->fixup) & ~3);
 		/*
 		 * NOTE: In some cases the faulting instruction
 		 * may be in the delay slot of a branch. We
 		 * don't want to take the branch, so we don't
 		 * increment iaoq[1], instead we set it to be
 		 * iaoq[0]+4, and clear the B bit in the PSW
 		 */
 		regs->iaoq[1] = regs->iaoq[0] + 4;
 		regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
 		return 1;
 	}
 	return 0;
 }
 void do_page_fault(struct pt_regs *regs, unsigned long code,
 			      unsigned long address)
 {
 	struct vm_area_struct *vma, *prev_vma;
-	struct task_struct *tsk = current;
+	struct task_struct *tsk;
-	struct mm_struct *mm = tsk->mm;
+	struct mm_struct *mm;
 	unsigned long acc_type;
 	int fault;
-	unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+	unsigned int flags;
-	if (in_atomic() || !mm)
+	if (in_atomic())
 		goto no_context;
+	tsk = current;
+	mm = tsk->mm;
+	if (!mm)
+		goto no_context;
+	flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
 	if (user_mode(regs))
 		flags |= FAULT_FLAG_USER;
 	acc_type = parisc_acctyp(code, regs->iir);
 	if (acc_type & VM_WRITE)
 		flags |= FAULT_FLAG_WRITE;
 retry:
 	down_read(&mm->mmap_sem);
 	vma = find_vma_prev(mm, address, &prev_vma);
 	if (!vma || address < vma->vm_start)
 		goto check_expansion;
 /*
  * Ok, we have a good vm_area for this memory access. We still need to
  * check the access permissions.
  */
 good_area:
 	if ((vma->vm_flags & acc_type) != acc_type)
 		goto bad_area;
 	/*
 	 * If for any reason at all we couldn't handle the fault, make
 	 * sure we exit gracefully rather than endlessly redo the
 	 * fault.
 	 */
 	fault = handle_mm_fault(mm, vma, address, flags);
 	if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
 		return;
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		/*
 		 * We hit a shared mapping outside of the file, or some
 		 * other thing happened to us that made us unable to
 		 * handle the page fault gracefully.
 		 */
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto bad_area;
 		BUG();
 	}
 	if (flags & FAULT_FLAG_ALLOW_RETRY) {
 		if (fault & VM_FAULT_MAJOR)
 			current->maj_flt++;
 		else
 			current->min_flt++;
 		if (fault & VM_FAULT_RETRY) {
 			flags &= ~FAULT_FLAG_ALLOW_RETRY;
 			/*
 			 * No need to up_read(&mm->mmap_sem) as we would
 			 * have already released it in __lock_page_or_retry
 			 * in mm/filemap.c.
 			 */
 			goto retry;
 		}
 	}
 	up_read(&mm->mmap_sem);
 	return;
 check_expansion:
 	vma = prev_vma;
 	if (vma && (expand_stack(vma, address) == 0))
 		goto good_area;
 /*
  * Something tried to access memory that isn't in our memory map..
  */
 bad_area:
 	up_read(&mm->mmap_sem);
 	if (user_mode(regs)) {
 		struct siginfo si;
 #ifdef PRINT_USER_FAULTS
 		printk(KERN_DEBUG "\n");
 		printk(KERN_DEBUG "do_page_fault() pid=%d command='%s' type=%lu address=0x%08lx\n",
 		    task_pid_nr(tsk), tsk->comm, code, address);
 		if (vma) {
 			printk(KERN_DEBUG "vm_start = 0x%08lx, vm_end = 0x%08lx\n",
 					vma->vm_start, vma->vm_end);
 		}
 		show_regs(regs);
 #endif
 		/* FIXME: actually we need to get the signo and code correct */
 		si.si_signo = SIGSEGV;
 		si.si_errno = 0;
 		si.si_code = SEGV_MAPERR;
 		si.si_addr = (void __user *) address;
 		force_sig_info(SIGSEGV, &si, current);
 		return;
 	}
 no_context:
 	if (!user_mode(regs) && fixup_exception(regs)) {
 		return;
 	}
 	parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
   out_of_memory:
 	up_read(&mm->mmap_sem);
 	if (!user_mode(regs))
 		goto no_context;
 	pagefault_out_of_memory();
 }