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Commit 31b7b6a86e9b86b8d97b3bc47b22585074ad115b

Authored by Marc Zyngier
Committed by Jason Cooper
1 parent 841f2aa462
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

irqchip: atmel-aic5: Convert to handle_domain_irq 

Use the new handle_domain_irq method to handle interrupts.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Link: https://lkml.kernel.org/r/1409047421-27649-21-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Showing 1 changed file with 1 additions and 3 deletions Inline Diff

drivers/irqchip/irq-atmel-aic5.c
Diff comments   View file @ 31b7b6a
1 /* 1 /*
2 * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver 2 * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver
3 * 3 *
4 * Copyright (C) 2004 SAN People 4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL 5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson 6 * Copyright (C) Rick Bronson
7 * Copyright (C) 2014 Free Electrons 7 * Copyright (C) 2014 Free Electrons
8 * 8 *
9 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 9 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/module.h> 17 #include <linux/module.h>
18 #include <linux/mm.h> 18 #include <linux/mm.h>
19 #include <linux/bitmap.h> 19 #include <linux/bitmap.h>
20 #include <linux/types.h> 20 #include <linux/types.h>
21 #include <linux/irq.h> 21 #include <linux/irq.h>
22 #include <linux/of.h> 22 #include <linux/of.h>
23 #include <linux/of_address.h> 23 #include <linux/of_address.h>
24 #include <linux/of_irq.h> 24 #include <linux/of_irq.h>
25 #include <linux/irqdomain.h> 25 #include <linux/irqdomain.h>
26 #include <linux/err.h> 26 #include <linux/err.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/io.h> 28 #include <linux/io.h>
29 29
30 #include <asm/exception.h> 30 #include <asm/exception.h>
31 #include <asm/mach/irq.h> 31 #include <asm/mach/irq.h>
32 32
33 #include "irq-atmel-aic-common.h" 33 #include "irq-atmel-aic-common.h"
34 #include "irqchip.h" 34 #include "irqchip.h"
35 35
36 /* Number of irq lines managed by AIC */ 36 /* Number of irq lines managed by AIC */
37 #define NR_AIC5_IRQS 128 37 #define NR_AIC5_IRQS 128
38 38
39 #define AT91_AIC5_SSR 0x0 39 #define AT91_AIC5_SSR 0x0
40 #define AT91_AIC5_INTSEL_MSK (0x7f << 0) 40 #define AT91_AIC5_INTSEL_MSK (0x7f << 0)
41 41
42 #define AT91_AIC5_SMR 0x4 42 #define AT91_AIC5_SMR 0x4
43 43
44 #define AT91_AIC5_SVR 0x8 44 #define AT91_AIC5_SVR 0x8
45 #define AT91_AIC5_IVR 0x10 45 #define AT91_AIC5_IVR 0x10
46 #define AT91_AIC5_FVR 0x14 46 #define AT91_AIC5_FVR 0x14
47 #define AT91_AIC5_ISR 0x18 47 #define AT91_AIC5_ISR 0x18
48 48
49 #define AT91_AIC5_IPR0 0x20 49 #define AT91_AIC5_IPR0 0x20
50 #define AT91_AIC5_IPR1 0x24 50 #define AT91_AIC5_IPR1 0x24
51 #define AT91_AIC5_IPR2 0x28 51 #define AT91_AIC5_IPR2 0x28
52 #define AT91_AIC5_IPR3 0x2c 52 #define AT91_AIC5_IPR3 0x2c
53 #define AT91_AIC5_IMR 0x30 53 #define AT91_AIC5_IMR 0x30
54 #define AT91_AIC5_CISR 0x34 54 #define AT91_AIC5_CISR 0x34
55 55
56 #define AT91_AIC5_IECR 0x40 56 #define AT91_AIC5_IECR 0x40
57 #define AT91_AIC5_IDCR 0x44 57 #define AT91_AIC5_IDCR 0x44
58 #define AT91_AIC5_ICCR 0x48 58 #define AT91_AIC5_ICCR 0x48
59 #define AT91_AIC5_ISCR 0x4c 59 #define AT91_AIC5_ISCR 0x4c
60 #define AT91_AIC5_EOICR 0x38 60 #define AT91_AIC5_EOICR 0x38
61 #define AT91_AIC5_SPU 0x3c 61 #define AT91_AIC5_SPU 0x3c
62 #define AT91_AIC5_DCR 0x6c 62 #define AT91_AIC5_DCR 0x6c
63 63
64 #define AT91_AIC5_FFER 0x50 64 #define AT91_AIC5_FFER 0x50
65 #define AT91_AIC5_FFDR 0x54 65 #define AT91_AIC5_FFDR 0x54
66 #define AT91_AIC5_FFSR 0x58 66 #define AT91_AIC5_FFSR 0x58
67 67
68 static struct irq_domain *aic5_domain; 68 static struct irq_domain *aic5_domain;
69 69
70 static asmlinkage void __exception_irq_entry 70 static asmlinkage void __exception_irq_entry
71 aic5_handle(struct pt_regs *regs) 71 aic5_handle(struct pt_regs *regs)
72 { 72 {
73 struct irq_domain_chip_generic *dgc = aic5_domain->gc; 73 struct irq_domain_chip_generic *dgc = aic5_domain->gc;
74 struct irq_chip_generic *gc = dgc->gc[0]; 74 struct irq_chip_generic *gc = dgc->gc[0];
75 u32 irqnr; 75 u32 irqnr;
76 u32 irqstat; 76 u32 irqstat;
77 77
78 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR); 78 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR);
79 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR); 79 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR);
80 80
81 irqnr = irq_find_mapping(aic5_domain, irqnr);
82
83 if (!irqstat) 81 if (!irqstat)
84 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 82 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
85 else 83 else
86 handle_IRQ(irqnr, regs); 84 handle_domain_irq(aic5_domain, irqnr, regs);
87 } 85 }
88 86
89 static void aic5_mask(struct irq_data *d) 87 static void aic5_mask(struct irq_data *d)
90 { 88 {
91 struct irq_domain *domain = d->domain; 89 struct irq_domain *domain = d->domain;
92 struct irq_domain_chip_generic *dgc = domain->gc; 90 struct irq_domain_chip_generic *dgc = domain->gc;
93 struct irq_chip_generic *gc = dgc->gc[0]; 91 struct irq_chip_generic *gc = dgc->gc[0];
94 92
95 /* Disable interrupt on AIC5 */ 93 /* Disable interrupt on AIC5 */
96 irq_gc_lock(gc); 94 irq_gc_lock(gc);
97 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 95 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
98 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 96 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
99 gc->mask_cache &= ~d->mask; 97 gc->mask_cache &= ~d->mask;
100 irq_gc_unlock(gc); 98 irq_gc_unlock(gc);
101 } 99 }
102 100
103 static void aic5_unmask(struct irq_data *d) 101 static void aic5_unmask(struct irq_data *d)
104 { 102 {
105 struct irq_domain *domain = d->domain; 103 struct irq_domain *domain = d->domain;
106 struct irq_domain_chip_generic *dgc = domain->gc; 104 struct irq_domain_chip_generic *dgc = domain->gc;
107 struct irq_chip_generic *gc = dgc->gc[0]; 105 struct irq_chip_generic *gc = dgc->gc[0];
108 106
109 /* Enable interrupt on AIC5 */ 107 /* Enable interrupt on AIC5 */
110 irq_gc_lock(gc); 108 irq_gc_lock(gc);
111 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 109 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
112 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR); 110 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR);
113 gc->mask_cache |= d->mask; 111 gc->mask_cache |= d->mask;
114 irq_gc_unlock(gc); 112 irq_gc_unlock(gc);
115 } 113 }
116 114
117 static int aic5_retrigger(struct irq_data *d) 115 static int aic5_retrigger(struct irq_data *d)
118 { 116 {
119 struct irq_domain *domain = d->domain; 117 struct irq_domain *domain = d->domain;
120 struct irq_domain_chip_generic *dgc = domain->gc; 118 struct irq_domain_chip_generic *dgc = domain->gc;
121 struct irq_chip_generic *gc = dgc->gc[0]; 119 struct irq_chip_generic *gc = dgc->gc[0];
122 120
123 /* Enable interrupt on AIC5 */ 121 /* Enable interrupt on AIC5 */
124 irq_gc_lock(gc); 122 irq_gc_lock(gc);
125 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 123 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
126 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR); 124 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR);
127 irq_gc_unlock(gc); 125 irq_gc_unlock(gc);
128 126
129 return 0; 127 return 0;
130 } 128 }
131 129
132 static int aic5_set_type(struct irq_data *d, unsigned type) 130 static int aic5_set_type(struct irq_data *d, unsigned type)
133 { 131 {
134 struct irq_domain *domain = d->domain; 132 struct irq_domain *domain = d->domain;
135 struct irq_domain_chip_generic *dgc = domain->gc; 133 struct irq_domain_chip_generic *dgc = domain->gc;
136 struct irq_chip_generic *gc = dgc->gc[0]; 134 struct irq_chip_generic *gc = dgc->gc[0];
137 unsigned int smr; 135 unsigned int smr;
138 int ret; 136 int ret;
139 137
140 irq_gc_lock(gc); 138 irq_gc_lock(gc);
141 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 139 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
142 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); 140 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
143 ret = aic_common_set_type(d, type, &smr); 141 ret = aic_common_set_type(d, type, &smr);
144 if (!ret) 142 if (!ret)
145 irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR); 143 irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR);
146 irq_gc_unlock(gc); 144 irq_gc_unlock(gc);
147 145
148 return ret; 146 return ret;
149 } 147 }
150 148
151 #ifdef CONFIG_PM 149 #ifdef CONFIG_PM
152 static void aic5_suspend(struct irq_data *d) 150 static void aic5_suspend(struct irq_data *d)
153 { 151 {
154 struct irq_domain *domain = d->domain; 152 struct irq_domain *domain = d->domain;
155 struct irq_domain_chip_generic *dgc = domain->gc; 153 struct irq_domain_chip_generic *dgc = domain->gc;
156 struct irq_chip_generic *bgc = dgc->gc[0]; 154 struct irq_chip_generic *bgc = dgc->gc[0];
157 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
158 int i; 156 int i;
159 u32 mask; 157 u32 mask;
160 158
161 irq_gc_lock(bgc); 159 irq_gc_lock(bgc);
162 for (i = 0; i < dgc->irqs_per_chip; i++) { 160 for (i = 0; i < dgc->irqs_per_chip; i++) {
163 mask = 1 << i; 161 mask = 1 << i;
164 if ((mask & gc->mask_cache) == (mask & gc->wake_active)) 162 if ((mask & gc->mask_cache) == (mask & gc->wake_active))
165 continue; 163 continue;
166 164
167 irq_reg_writel(i + gc->irq_base, 165 irq_reg_writel(i + gc->irq_base,
168 bgc->reg_base + AT91_AIC5_SSR); 166 bgc->reg_base + AT91_AIC5_SSR);
169 if (mask & gc->wake_active) 167 if (mask & gc->wake_active)
170 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR); 168 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
171 else 169 else
172 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 170 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
173 } 171 }
174 irq_gc_unlock(bgc); 172 irq_gc_unlock(bgc);
175 } 173 }
176 174
177 static void aic5_resume(struct irq_data *d) 175 static void aic5_resume(struct irq_data *d)
178 { 176 {
179 struct irq_domain *domain = d->domain; 177 struct irq_domain *domain = d->domain;
180 struct irq_domain_chip_generic *dgc = domain->gc; 178 struct irq_domain_chip_generic *dgc = domain->gc;
181 struct irq_chip_generic *bgc = dgc->gc[0]; 179 struct irq_chip_generic *bgc = dgc->gc[0];
182 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 180 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
183 int i; 181 int i;
184 u32 mask; 182 u32 mask;
185 183
186 irq_gc_lock(bgc); 184 irq_gc_lock(bgc);
187 for (i = 0; i < dgc->irqs_per_chip; i++) { 185 for (i = 0; i < dgc->irqs_per_chip; i++) {
188 mask = 1 << i; 186 mask = 1 << i;
189 if ((mask & gc->mask_cache) == (mask & gc->wake_active)) 187 if ((mask & gc->mask_cache) == (mask & gc->wake_active))
190 continue; 188 continue;
191 189
192 irq_reg_writel(i + gc->irq_base, 190 irq_reg_writel(i + gc->irq_base,
193 bgc->reg_base + AT91_AIC5_SSR); 191 bgc->reg_base + AT91_AIC5_SSR);
194 if (mask & gc->mask_cache) 192 if (mask & gc->mask_cache)
195 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR); 193 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
196 else 194 else
197 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 195 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
198 } 196 }
199 irq_gc_unlock(bgc); 197 irq_gc_unlock(bgc);
200 } 198 }
201 199
202 static void aic5_pm_shutdown(struct irq_data *d) 200 static void aic5_pm_shutdown(struct irq_data *d)
203 { 201 {
204 struct irq_domain *domain = d->domain; 202 struct irq_domain *domain = d->domain;
205 struct irq_domain_chip_generic *dgc = domain->gc; 203 struct irq_domain_chip_generic *dgc = domain->gc;
206 struct irq_chip_generic *bgc = dgc->gc[0]; 204 struct irq_chip_generic *bgc = dgc->gc[0];
207 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 205 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
208 int i; 206 int i;
209 207
210 irq_gc_lock(bgc); 208 irq_gc_lock(bgc);
211 for (i = 0; i < dgc->irqs_per_chip; i++) { 209 for (i = 0; i < dgc->irqs_per_chip; i++) {
212 irq_reg_writel(i + gc->irq_base, 210 irq_reg_writel(i + gc->irq_base,
213 bgc->reg_base + AT91_AIC5_SSR); 211 bgc->reg_base + AT91_AIC5_SSR);
214 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 212 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
215 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR); 213 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
216 } 214 }
217 irq_gc_unlock(bgc); 215 irq_gc_unlock(bgc);
218 } 216 }
219 #else 217 #else
220 #define aic5_suspend NULL 218 #define aic5_suspend NULL
221 #define aic5_resume NULL 219 #define aic5_resume NULL
222 #define aic5_pm_shutdown NULL 220 #define aic5_pm_shutdown NULL
223 #endif /* CONFIG_PM */ 221 #endif /* CONFIG_PM */
224 222
225 static void __init aic5_hw_init(struct irq_domain *domain) 223 static void __init aic5_hw_init(struct irq_domain *domain)
226 { 224 {
227 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0); 225 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
228 int i; 226 int i;
229 227
230 /* 228 /*
231 * Perform 8 End Of Interrupt Command to make sure AIC 229 * Perform 8 End Of Interrupt Command to make sure AIC
232 * will not Lock out nIRQ 230 * will not Lock out nIRQ
233 */ 231 */
234 for (i = 0; i < 8; i++) 232 for (i = 0; i < 8; i++)
235 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 233 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
236 234
237 /* 235 /*
238 * Spurious Interrupt ID in Spurious Vector Register. 236 * Spurious Interrupt ID in Spurious Vector Register.
239 * When there is no current interrupt, the IRQ Vector Register 237 * When there is no current interrupt, the IRQ Vector Register
240 * reads the value stored in AIC_SPU 238 * reads the value stored in AIC_SPU
241 */ 239 */
242 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU); 240 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU);
243 241
244 /* No debugging in AIC: Debug (Protect) Control Register */ 242 /* No debugging in AIC: Debug (Protect) Control Register */
245 irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR); 243 irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR);
246 244
247 /* Disable and clear all interrupts initially */ 245 /* Disable and clear all interrupts initially */
248 for (i = 0; i < domain->revmap_size; i++) { 246 for (i = 0; i < domain->revmap_size; i++) {
249 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR); 247 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR);
250 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR); 248 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR);
251 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 249 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
252 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR); 250 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR);
253 } 251 }
254 } 252 }
255 253
256 static int aic5_irq_domain_xlate(struct irq_domain *d, 254 static int aic5_irq_domain_xlate(struct irq_domain *d,
257 struct device_node *ctrlr, 255 struct device_node *ctrlr,
258 const u32 *intspec, unsigned int intsize, 256 const u32 *intspec, unsigned int intsize,
259 irq_hw_number_t *out_hwirq, 257 irq_hw_number_t *out_hwirq,
260 unsigned int *out_type) 258 unsigned int *out_type)
261 { 259 {
262 struct irq_domain_chip_generic *dgc = d->gc; 260 struct irq_domain_chip_generic *dgc = d->gc;
263 struct irq_chip_generic *gc; 261 struct irq_chip_generic *gc;
264 unsigned smr; 262 unsigned smr;
265 int ret; 263 int ret;
266 264
267 if (!dgc) 265 if (!dgc)
268 return -EINVAL; 266 return -EINVAL;
269 267
270 ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, 268 ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
271 out_hwirq, out_type); 269 out_hwirq, out_type);
272 if (ret) 270 if (ret)
273 return ret; 271 return ret;
274 272
275 gc = dgc->gc[0]; 273 gc = dgc->gc[0];
276 274
277 irq_gc_lock(gc); 275 irq_gc_lock(gc);
278 irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR); 276 irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR);
279 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); 277 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
280 ret = aic_common_set_priority(intspec[2], &smr); 278 ret = aic_common_set_priority(intspec[2], &smr);
281 if (!ret) 279 if (!ret)
282 irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR); 280 irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);
283 irq_gc_unlock(gc); 281 irq_gc_unlock(gc);
284 282
285 return ret; 283 return ret;
286 } 284 }
287 285
288 static const struct irq_domain_ops aic5_irq_ops = { 286 static const struct irq_domain_ops aic5_irq_ops = {
289 .map = irq_map_generic_chip, 287 .map = irq_map_generic_chip,
290 .xlate = aic5_irq_domain_xlate, 288 .xlate = aic5_irq_domain_xlate,
291 }; 289 };
292 290
293 static void __init sama5d3_aic_irq_fixup(struct device_node *root) 291 static void __init sama5d3_aic_irq_fixup(struct device_node *root)
294 { 292 {
295 aic_common_rtc_irq_fixup(root); 293 aic_common_rtc_irq_fixup(root);
296 } 294 }
297 295
298 static const struct of_device_id __initdata aic5_irq_fixups[] = { 296 static const struct of_device_id __initdata aic5_irq_fixups[] = {
299 { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, 297 { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
300 { /* sentinel */ }, 298 { /* sentinel */ },
301 }; 299 };
302 300
303 static int __init aic5_of_init(struct device_node *node, 301 static int __init aic5_of_init(struct device_node *node,
304 struct device_node *parent, 302 struct device_node *parent,
305 int nirqs) 303 int nirqs)
306 { 304 {
307 struct irq_chip_generic *gc; 305 struct irq_chip_generic *gc;
308 struct irq_domain *domain; 306 struct irq_domain *domain;
309 int nchips; 307 int nchips;
310 int i; 308 int i;
311 309
312 if (nirqs > NR_AIC5_IRQS) 310 if (nirqs > NR_AIC5_IRQS)
313 return -EINVAL; 311 return -EINVAL;
314 312
315 if (aic5_domain) 313 if (aic5_domain)
316 return -EEXIST; 314 return -EEXIST;
317 315
318 domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5", 316 domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
319 nirqs); 317 nirqs);
320 if (IS_ERR(domain)) 318 if (IS_ERR(domain))
321 return PTR_ERR(domain); 319 return PTR_ERR(domain);
322 320
323 aic_common_irq_fixup(aic5_irq_fixups); 321 aic_common_irq_fixup(aic5_irq_fixups);
324 322
325 aic5_domain = domain; 323 aic5_domain = domain;
326 nchips = aic5_domain->revmap_size / 32; 324 nchips = aic5_domain->revmap_size / 32;
327 for (i = 0; i < nchips; i++) { 325 for (i = 0; i < nchips; i++) {
328 gc = irq_get_domain_generic_chip(domain, i * 32); 326 gc = irq_get_domain_generic_chip(domain, i * 32);
329 327
330 gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR; 328 gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
331 gc->chip_types[0].chip.irq_mask = aic5_mask; 329 gc->chip_types[0].chip.irq_mask = aic5_mask;
332 gc->chip_types[0].chip.irq_unmask = aic5_unmask; 330 gc->chip_types[0].chip.irq_unmask = aic5_unmask;
333 gc->chip_types[0].chip.irq_retrigger = aic5_retrigger; 331 gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
334 gc->chip_types[0].chip.irq_set_type = aic5_set_type; 332 gc->chip_types[0].chip.irq_set_type = aic5_set_type;
335 gc->chip_types[0].chip.irq_suspend = aic5_suspend; 333 gc->chip_types[0].chip.irq_suspend = aic5_suspend;
336 gc->chip_types[0].chip.irq_resume = aic5_resume; 334 gc->chip_types[0].chip.irq_resume = aic5_resume;
337 gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown; 335 gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
338 } 336 }
339 337
340 aic5_hw_init(domain); 338 aic5_hw_init(domain);
341 set_handle_irq(aic5_handle); 339 set_handle_irq(aic5_handle);
342 340
343 return 0; 341 return 0;
344 } 342 }
345 343
346 #define NR_SAMA5D3_IRQS 50 344 #define NR_SAMA5D3_IRQS 50
347 345
348 static int __init sama5d3_aic5_of_init(struct device_node *node, 346 static int __init sama5d3_aic5_of_init(struct device_node *node,
349 struct device_node *parent) 347 struct device_node *parent)
350 { 348 {
351 return aic5_of_init(node, parent, NR_SAMA5D3_IRQS); 349 return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
352 } 350 }
353 IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init); 351 IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
354 352