Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 35874f3617b38e0c1f72163407c41d554a8f5939

Authored by Peter De Schrijver 2014-06-12 23:36:36 +0800

Committed by Thierry Reding 2014-07-17 20:32:51 +0800

Exists in ti-lsk-linux-4.1.y and in 10 other branches

ARM: tegra: move fuse exports to soc/tegra/fuse.h

All fuse related functionality will move to a driver in the following
patches. To prepare for this, export all the required functionality in a
global header file and move all users of fuse.h to soc/tegra/fuse.h.

While we're at it, remove tegra_bct_strapping, as its only user was
removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling
driver").

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Showing 6 changed files with 22 additions and 14 deletions Inline Diff

arch/arm/mach-tegra/fuse.h
arch/arm/mach-tegra/tegra.c
arch/arm/mach-tegra/tegra114_speedo.c
arch/arm/mach-tegra/tegra20_speedo.c
arch/arm/mach-tegra/tegra30_speedo.c
include/soc/tegra/fuse.h

arch/arm/mach-tegra/fuse.h

Diff comments View file @ 35874f3

 /*
  * Copyright (C) 2010 Google, Inc.
  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *	Colin Cross <ccross@android.com>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  */
 #ifndef __MACH_TEGRA_FUSE_H
 #define __MACH_TEGRA_FUSE_H
 #define SKU_ID_T20	8
 #define SKU_ID_T25SE	20
 #define SKU_ID_AP25	23
 #define SKU_ID_T25	24
 #define SKU_ID_AP25E	27
 #define SKU_ID_T25E	28
 #ifndef __ASSEMBLY__
-enum tegra_revision {
-	TEGRA_REVISION_UNKNOWN = 0,
-	TEGRA_REVISION_A01,
-	TEGRA_REVISION_A02,
-	TEGRA_REVISION_A03,
-	TEGRA_REVISION_A03p,
-	TEGRA_REVISION_A04,
-	TEGRA_REVISION_MAX,
-};
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
 extern int tegra_cpu_speedo_id;		/* only exist in Tegra30 and later */
 extern int tegra_soc_speedo_id;
-extern enum tegra_revision tegra_revision;
-extern int tegra_bct_strapping;
 unsigned long long tegra_chip_uid(void);
-void tegra_init_fuse(void);
 bool tegra_spare_fuse(int bit);
 u32 tegra_fuse_readl(unsigned long offset);
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 void tegra20_init_speedo_data(void);
 #else
 static inline void tegra20_init_speedo_data(void) {}
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void tegra30_init_speedo_data(void);
 #else
 static inline void tegra30_init_speedo_data(void) {}
 #endif
 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 void tegra114_init_speedo_data(void);
 #else
 static inline void tegra114_init_speedo_data(void) {}
 #endif
 #endif /* __ASSEMBLY__ */
 #endif

arch/arm/mach-tegra/tegra.c

Diff comments View file @ 35874f3

 /*
  * NVIDIA Tegra SoC device tree board support
  *
  * Copyright (C) 2011, 2013, NVIDIA Corporation
  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  * Copyright (C) 2010 Google, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  */
 #include <linux/clk.h>
 #include <linux/clk/tegra.h>
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/pda_power.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
 #include <soc/tegra/fuse.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/trusted_foundations.h>
 #include "apbio.h"
 #include "board.h"
 #include "common.h"
 #include "cpuidle.h"
-#include "fuse.h"
 #include "iomap.h"
 #include "irq.h"
 #include "pmc.h"
 #include "pm.h"
 #include "reset.h"
 #include "sleep.h"
 /*
  * Storage for debug-macro.S's state.
  *
  * This must be in .data not .bss so that it gets initialized each time the
  * kernel is loaded. The data is declared here rather than debug-macro.S so
  * that multiple inclusions of debug-macro.S point at the same data.
  */
 u32 tegra_uart_config[3] = {
 	/* Debug UART initialization required */
 	1,
 	/* Debug UART physical address */
 	0,
 	/* Debug UART virtual address */
 	0,
 };
 static void __init tegra_init_early(void)
 {
 	of_register_trusted_foundations();
 	tegra_apb_io_init();
 	tegra_init_fuse();
 	tegra_cpu_reset_handler_init();
 	tegra_powergate_init();
 	tegra_hotplug_init();
 }
 static void __init tegra_dt_init_irq(void)
 {
 	tegra_pmc_init_irq();
 	tegra_init_irq();
 	irqchip_init();
 	tegra_legacy_irq_syscore_init();
 }
 static void __init tegra_dt_init(void)
 {
 	struct soc_device_attribute *soc_dev_attr;
 	struct soc_device *soc_dev;
 	struct device *parent = NULL;
 	tegra_pmc_init();
 	tegra_clocks_apply_init_table();
 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 	if (!soc_dev_attr)
 		goto out;
 	soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
 	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
 	soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
 	soc_dev = soc_device_register(soc_dev_attr);
 	if (IS_ERR(soc_dev)) {
 		kfree(soc_dev_attr->family);
 		kfree(soc_dev_attr->revision);
 		kfree(soc_dev_attr->soc_id);
 		kfree(soc_dev_attr);
 		goto out;
 	}
 	parent = soc_device_to_device(soc_dev);
 	/*
 	 * Finished with the static registrations now; fill in the missing
 	 * devices
 	 */
 out:
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 }
 static void __init paz00_init(void)
 {
 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
 		tegra_paz00_wifikill_init();
 }
 static struct {
 	char *machine;
 	void (*init)(void);
 } board_init_funcs[] = {
 	{ "compal,paz00", paz00_init },
 };
 static void __init tegra_dt_init_late(void)
 {
 	int i;
 	tegra_init_suspend();
 	tegra_cpuidle_init();
 	tegra_powergate_debugfs_init();
 	for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
 		if (of_machine_is_compatible(board_init_funcs[i].machine)) {
 			board_init_funcs[i].init();
 			break;
 		}
 	}
 }
 static const char * const tegra_dt_board_compat[] = {
 	"nvidia,tegra124",
 	"nvidia,tegra114",
 	"nvidia,tegra30",
 	"nvidia,tegra20",
 	NULL
 };
 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
 	.l2c_aux_val	= 0x3c400001,
 	.l2c_aux_mask	= 0xc20fc3fe,
 	.smp		= smp_ops(tegra_smp_ops),
 	.map_io		= tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq	= tegra_dt_init_irq,
 	.init_machine	= tegra_dt_init,
 	.init_late	= tegra_dt_init_late,
 	.restart	= tegra_pmc_restart,
 	.dt_compat	= tegra_dt_board_compat,
 MACHINE_END

arch/arm/mach-tegra/tegra114_speedo.c

Diff comments View file @ 35874f3

 /*
  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
  *
  * This program is distributed in the hope it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/bug.h>
 #include <linux/kernel.h>
+#include <soc/tegra/fuse.h>
 #include "fuse.h"
 #define CORE_PROCESS_CORNERS_NUM	2
 #define CPU_PROCESS_CORNERS_NUM		2
 enum {
 	THRESHOLD_INDEX_0,
 	THRESHOLD_INDEX_1,
 	THRESHOLD_INDEX_COUNT,
 };
 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
 	{1123,     UINT_MAX},
 	{0,        UINT_MAX},
 };
 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
 	{1695,     UINT_MAX},
 	{0,        UINT_MAX},
 };
 static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
 {
 	u32 tmp;
 	switch (sku) {
 	case 0x00:
 	case 0x10:
 	case 0x05:
 	case 0x06:
 		tegra_cpu_speedo_id = 1;
 		tegra_soc_speedo_id = 0;
 		*threshold = THRESHOLD_INDEX_0;
 		break;
 	case 0x03:
 	case 0x04:
 		tegra_cpu_speedo_id = 2;
 		tegra_soc_speedo_id = 1;
 		*threshold = THRESHOLD_INDEX_1;
 		break;
 	default:
 		pr_err("Tegra114 Unknown SKU %d\n", sku);
 		tegra_cpu_speedo_id = 0;
 		tegra_soc_speedo_id = 0;
 		*threshold = THRESHOLD_INDEX_0;
 		break;
 	}
 	if (rev == TEGRA_REVISION_A01) {
 		tmp = tegra_fuse_readl(0x270) << 1;
 		tmp |= tegra_fuse_readl(0x26c);
 		if (!tmp)
 			tegra_cpu_speedo_id = 0;
 	}
 }
 void tegra114_init_speedo_data(void)
 {
 	u32 cpu_speedo_val;
 	u32 core_speedo_val;
 	int threshold;
 	int i;
 	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
 			THRESHOLD_INDEX_COUNT);
 	BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
 			THRESHOLD_INDEX_COUNT);
 	rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
 	cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
 	core_speedo_val = tegra_fuse_readl(0x134);
 	for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
 		if (cpu_speedo_val < cpu_process_speedos[threshold][i])
 			break;
 	tegra_cpu_process_id = i;
 	for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
 		if (core_speedo_val < core_process_speedos[threshold][i])
 			break;
 	tegra_core_process_id = i;
 }

arch/arm/mach-tegra/tegra20_speedo.c

Diff comments View file @ 35874f3

 /*
  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
  *
  * This program is distributed in the hope it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/bug.h>
 #include <linux/kernel.h>
+#include <soc/tegra/fuse.h>
 #include "fuse.h"
 #define CPU_SPEEDO_LSBIT		20
 #define CPU_SPEEDO_MSBIT		29
 #define CPU_SPEEDO_REDUND_LSBIT		30
 #define CPU_SPEEDO_REDUND_MSBIT		39
 #define CPU_SPEEDO_REDUND_OFFS	(CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
 #define CORE_SPEEDO_LSBIT		40
 #define CORE_SPEEDO_MSBIT		47
 #define CORE_SPEEDO_REDUND_LSBIT	48
 #define CORE_SPEEDO_REDUND_MSBIT	55
 #define CORE_SPEEDO_REDUND_OFFS	(CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
 #define SPEEDO_MULT			4
 #define PROCESS_CORNERS_NUM		4
 #define SPEEDO_ID_SELECT_0(rev)		((rev) <= 2)
 #define SPEEDO_ID_SELECT_1(sku)		\
 	(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
 	 ((sku) != 27) && ((sku) != 28))
 enum {
 	SPEEDO_ID_0,
 	SPEEDO_ID_1,
 	SPEEDO_ID_2,
 	SPEEDO_ID_COUNT,
 };
 static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
 	{315, 366, 420, UINT_MAX},
 	{303, 368, 419, UINT_MAX},
 	{316, 331, 383, UINT_MAX},
 };
 static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
 	{165, 195, 224, UINT_MAX},
 	{165, 195, 224, UINT_MAX},
 	{165, 195, 224, UINT_MAX},
 };
 void tegra20_init_speedo_data(void)
 {
 	u32 reg;
 	u32 val;
 	int i;
 	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
 	BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
 	if (SPEEDO_ID_SELECT_0(tegra_revision))
 		tegra_soc_speedo_id = SPEEDO_ID_0;
 	else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
 		tegra_soc_speedo_id = SPEEDO_ID_1;
 	else
 		tegra_soc_speedo_id = SPEEDO_ID_2;
 	val = 0;
 	for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
 		reg = tegra_spare_fuse(i) |
 			tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
 		val = (val << 1) | (reg & 0x1);
 	}
 	val = val * SPEEDO_MULT;
 	pr_debug("%s CPU speedo value %u\n", __func__, val);
 	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
 		if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
 			break;
 	}
 	tegra_cpu_process_id = i;
 	val = 0;
 	for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
 		reg = tegra_spare_fuse(i) |
 			tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
 		val = (val << 1) | (reg & 0x1);
 	}
 	val = val * SPEEDO_MULT;
 	pr_debug("%s Core speedo value %u\n", __func__, val);
 	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
 		if (val <= core_process_speedos[tegra_soc_speedo_id][i])
 			break;
 	}
 	tegra_core_process_id = i;
 	pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
 }

arch/arm/mach-tegra/tegra30_speedo.c

Diff comments View file @ 35874f3

 /*
  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
  *
  * This program is distributed in the hope it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/bug.h>
 #include <linux/kernel.h>
+#include <soc/tegra/fuse.h>
 #include "fuse.h"
 #define CORE_PROCESS_CORNERS_NUM	1
 #define CPU_PROCESS_CORNERS_NUM		6
 #define FUSE_SPEEDO_CALIB_0	0x114
 #define FUSE_PACKAGE_INFO	0X1FC
 #define FUSE_TEST_PROG_VER	0X128
 #define G_SPEEDO_BIT_MINUS1	58
 #define G_SPEEDO_BIT_MINUS1_R	59
 #define G_SPEEDO_BIT_MINUS2	60
 #define G_SPEEDO_BIT_MINUS2_R	61
 #define LP_SPEEDO_BIT_MINUS1	62
 #define LP_SPEEDO_BIT_MINUS1_R	63
 #define LP_SPEEDO_BIT_MINUS2	64
 #define LP_SPEEDO_BIT_MINUS2_R	65
 enum {
 	THRESHOLD_INDEX_0,
 	THRESHOLD_INDEX_1,
 	THRESHOLD_INDEX_2,
 	THRESHOLD_INDEX_3,
 	THRESHOLD_INDEX_4,
 	THRESHOLD_INDEX_5,
 	THRESHOLD_INDEX_6,
 	THRESHOLD_INDEX_7,
 	THRESHOLD_INDEX_8,
 	THRESHOLD_INDEX_9,
 	THRESHOLD_INDEX_10,
 	THRESHOLD_INDEX_11,
 	THRESHOLD_INDEX_COUNT,
 };
 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
 	{180},
 	{170},
 	{195},
 	{180},
 	{168},
 	{192},
 	{180},
 	{170},
 	{195},
 	{180},
 	{180},
 	{180},
 };
 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
 	{306, 338, 360, 376, UINT_MAX},
 	{295, 336, 358, 375, UINT_MAX},
 	{325, 325, 358, 375, UINT_MAX},
 	{325, 325, 358, 375, UINT_MAX},
 	{292, 324, 348, 364, UINT_MAX},
 	{324, 324, 348, 364, UINT_MAX},
 	{324, 324, 348, 364, UINT_MAX},
 	{295, 336, 358, 375, UINT_MAX},
 	{358, 358, 358, 358, 397, UINT_MAX},
 	{364, 364, 364, 364, 397, UINT_MAX},
 	{295, 336, 358, 375, 391, UINT_MAX},
 	{295, 336, 358, 375, 391, UINT_MAX},
 };
 static int threshold_index;
 static int package_id;
 static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
 {
 	u32 reg;
 	int ate_ver;
 	int bit_minus1;
 	int bit_minus2;
 	reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
 	*speedo_lp = (reg & 0xFFFF) * 4;
 	*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
 	ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
 	pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
 	if (ate_ver >= 26) {
 		bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
 		bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
 		bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
 		bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
 		*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
 		bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
 		bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
 		bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
 		bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
 		*speedo_g |= (bit_minus1 << 1) | bit_minus2;
 	} else {
 		*speedo_lp |= 0x3;
 		*speedo_g |= 0x3;
 	}
 }
 static void rev_sku_to_speedo_ids(int rev, int sku)
 {
 	switch (rev) {
 	case TEGRA_REVISION_A01:
 		tegra_cpu_speedo_id = 0;
 		tegra_soc_speedo_id = 0;
 		threshold_index = THRESHOLD_INDEX_0;
 		break;
 	case TEGRA_REVISION_A02:
 	case TEGRA_REVISION_A03:
 		switch (sku) {
 		case 0x87:
 		case 0x82:
 			tegra_cpu_speedo_id = 1;
 			tegra_soc_speedo_id = 1;
 			threshold_index = THRESHOLD_INDEX_1;
 			break;
 		case 0x81:
 			switch (package_id) {
 			case 1:
 				tegra_cpu_speedo_id = 2;
 				tegra_soc_speedo_id = 2;
 				threshold_index = THRESHOLD_INDEX_2;
 				break;
 			case 2:
 				tegra_cpu_speedo_id = 4;
 				tegra_soc_speedo_id = 1;
 				threshold_index = THRESHOLD_INDEX_7;
 				break;
 			default:
 				pr_err("Tegra30: Unknown pkg %d\n", package_id);
 				BUG();
 				break;
 			}
 			break;
 		case 0x80:
 			switch (package_id) {
 			case 1:
 				tegra_cpu_speedo_id = 5;
 				tegra_soc_speedo_id = 2;
 				threshold_index = THRESHOLD_INDEX_8;
 				break;
 			case 2:
 				tegra_cpu_speedo_id = 6;
 				tegra_soc_speedo_id = 2;
 				threshold_index = THRESHOLD_INDEX_9;
 				break;
 			default:
 				pr_err("Tegra30: Unknown pkg %d\n", package_id);
 				BUG();
 				break;
 			}
 			break;
 		case 0x83:
 			switch (package_id) {
 			case 1:
 				tegra_cpu_speedo_id = 7;
 				tegra_soc_speedo_id = 1;
 				threshold_index = THRESHOLD_INDEX_10;
 				break;
 			case 2:
 				tegra_cpu_speedo_id = 3;
 				tegra_soc_speedo_id = 2;
 				threshold_index = THRESHOLD_INDEX_3;
 				break;
 			default:
 				pr_err("Tegra30: Unknown pkg %d\n", package_id);
 				BUG();
 				break;
 			}
 			break;
 		case 0x8F:
 			tegra_cpu_speedo_id = 8;
 			tegra_soc_speedo_id = 1;
 			threshold_index = THRESHOLD_INDEX_11;
 			break;
 		case 0x08:
 			tegra_cpu_speedo_id = 1;
 			tegra_soc_speedo_id = 1;
 			threshold_index = THRESHOLD_INDEX_4;
 			break;
 		case 0x02:
 			tegra_cpu_speedo_id = 2;
 			tegra_soc_speedo_id = 2;
 			threshold_index = THRESHOLD_INDEX_5;
 			break;
 		case 0x04:
 			tegra_cpu_speedo_id = 3;
 			tegra_soc_speedo_id = 2;
 			threshold_index = THRESHOLD_INDEX_6;
 			break;
 		case 0:
 			switch (package_id) {
 			case 1:
 				tegra_cpu_speedo_id = 2;
 				tegra_soc_speedo_id = 2;
 				threshold_index = THRESHOLD_INDEX_2;
 				break;
 			case 2:
 				tegra_cpu_speedo_id = 3;
 				tegra_soc_speedo_id = 2;
 				threshold_index = THRESHOLD_INDEX_3;
 				break;
 			default:
 				pr_err("Tegra30: Unknown pkg %d\n", package_id);
 				BUG();
 				break;
 			}
 			break;
 		default:
 			pr_warn("Tegra30: Unknown SKU %d\n", sku);
 			tegra_cpu_speedo_id = 0;
 			tegra_soc_speedo_id = 0;
 			threshold_index = THRESHOLD_INDEX_0;
 			break;
 		}
 		break;
 	default:
 		pr_warn("Tegra30: Unknown chip rev %d\n", rev);
 		tegra_cpu_speedo_id = 0;
 		tegra_soc_speedo_id = 0;
 		threshold_index = THRESHOLD_INDEX_0;
 		break;
 	}
 }
 void tegra30_init_speedo_data(void)
 {
 	u32 cpu_speedo_val;
 	u32 core_speedo_val;
 	int i;
 	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
 			THRESHOLD_INDEX_COUNT);
 	BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
 			THRESHOLD_INDEX_COUNT);
 	package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
 	rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
 	fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
 	pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
 	pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
 	for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
 		if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
 			break;
 	}
 	tegra_cpu_process_id = i - 1;
 	if (tegra_cpu_process_id == -1) {
 		pr_warn("Tegra30: CPU speedo value %3d out of range",
 		       cpu_speedo_val);
 		tegra_cpu_process_id = 0;
 		tegra_cpu_speedo_id = 1;
 	}
 	for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
 		if (core_speedo_val < core_process_speedos[threshold_index][i])
 			break;
 	}
 	tegra_core_process_id = i - 1;
 	if (tegra_core_process_id == -1) {
 		pr_warn("Tegra30: CORE speedo value %3d out of range",
 		       core_speedo_val);
 		tegra_core_process_id = 0;
 		tegra_soc_speedo_id = 1;
 	}
 	pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
 		tegra_cpu_speedo_id, tegra_soc_speedo_id);
 }

include/soc/tegra/fuse.h

Diff comments View file @ 35874f3

 /*
  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
  *
  * This program is distributed in the hope it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef __SOC_TEGRA_FUSE_H__
 #define __SOC_TEGRA_FUSE_H__
 #define TEGRA20		0x20
 #define TEGRA30		0x30
 #define TEGRA114	0x35
 #define TEGRA124	0x40
 #ifndef __ASSEMBLY__
 u32 tegra_read_chipid(void);
 u8 tegra_get_chip_id(void);
+enum tegra_revision {
+	TEGRA_REVISION_UNKNOWN = 0,
+	TEGRA_REVISION_A01,
+	TEGRA_REVISION_A02,
+	TEGRA_REVISION_A03,
+	TEGRA_REVISION_A03p,
+	TEGRA_REVISION_A04,
+	TEGRA_REVISION_MAX,
+};
+u32 tegra_read_straps(void);
+u32 tegra_read_chipid(void);
+void tegra_init_fuse(void);
+extern enum tegra_revision tegra_revision;
 #if defined(CONFIG_TEGRA20_APB_DMA)
 int tegra_apb_readl_using_dma(unsigned long offset, u32 *value);
 int tegra_apb_writel_using_dma(u32 value, unsigned long offset);
 #else
 static inline int tegra_apb_readl_using_dma(unsigned long offset, u32 *value)
 {
 	return -EINVAL;
 }
 static inline int tegra_apb_writel_using_dma(u32 value, unsigned long offset)
 {
 	return -EINVAL;
 }
 #endif /* CONFIG_TEGRA20_APB_DMA */
 #endif /* __ASSEMBLY__ */
 #endif /* __SOC_TEGRA_FUSE_H__ */