Eric Lee / smarc-ti-linux-kernel

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Commit 4eb96b5eeb7fa68b8c275ac8cd49ba8694bd8b83

Authored by Sourav Poddar
Committed by Kishon Vijay Abraham I
1 parent 56e3f362b3
Exists in ti-linux-3.12.y and in 3 other branches newt-ti-linux-3.12.y, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y

arm: dts: dra7-evm: Fix qspi partition. 

Change the size to reflect correct kernel size.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/boot/dts/dra7-evm.dts
Diff comments   View file @ 4eb96b5
1 /* 1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "dra7.dtsi" 10 #include "dra7.dtsi"
11 #include <dt-bindings/pinctrl/dra7xx.h> 11 #include <dt-bindings/pinctrl/dra7xx.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h> 12 #include <dt-bindings/clk/ti-dra7-atl.h>
13 13
14 / { 14 / {
15 model = "TI DRA7"; 15 model = "TI DRA7";
16 compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; 16 compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
17 17
18 memory { 18 memory {
19 device_type = "memory"; 19 device_type = "memory";
20 reg = <0x80000000 0x60000000>; /* 1536 MB */ 20 reg = <0x80000000 0x60000000>; /* 1536 MB */
21 }; 21 };
22 22
23 extcon1: gpio_usbvid_extcon1 { 23 extcon1: gpio_usbvid_extcon1 {
24 compatible = "ti,gpio-usb-id"; 24 compatible = "ti,gpio-usb-id";
25 gpios = <&gpio21 1 0>; 25 gpios = <&gpio21 1 0>;
26 }; 26 };
27 27
28 extcon2: gpio_usbvid_extcon2 { 28 extcon2: gpio_usbvid_extcon2 {
29 compatible = "ti,gpio-usb-id"; 29 compatible = "ti,gpio-usb-id";
30 gpios = <&gpio21 2 0>; 30 gpios = <&gpio21 2 0>;
31 }; 31 };
32 32
33 evm_3v3_sd: fixedregulator-sd { 33 evm_3v3_sd: fixedregulator-sd {
34 compatible = "regulator-fixed"; 34 compatible = "regulator-fixed";
35 regulator-name = "evm_3v3_sd"; 35 regulator-name = "evm_3v3_sd";
36 regulator-min-microvolt = <3300000>; 36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>; 37 regulator-max-microvolt = <3300000>;
38 enable-active-high; 38 enable-active-high;
39 gpio = <&gpio21 5 0>; 39 gpio = <&gpio21 5 0>;
40 }; 40 };
41 41
42 evm_3v3_sw: fixedregulator-evm_3v3_sw { 42 evm_3v3_sw: fixedregulator-evm_3v3_sw {
43 compatible = "regulator-fixed"; 43 compatible = "regulator-fixed";
44 regulator-name = "evm_3v3_sw"; 44 regulator-name = "evm_3v3_sw";
45 regulator-min-microvolt = <3300000>; 45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>;
47 }; 47 };
48 48
49 aic_dvdd_1v8: fixedregulator-aic-dvdd-1v8 { 49 aic_dvdd_1v8: fixedregulator-aic-dvdd-1v8 {
50 compatible = "regulator-fixed"; 50 compatible = "regulator-fixed";
51 regulator-name = "aic-dvdd-1v8"; 51 regulator-name = "aic-dvdd-1v8";
52 regulator-min-microvolt = <1800000>; 52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>; 53 regulator-max-microvolt = <1800000>;
54 regulator-boot-on; 54 regulator-boot-on;
55 }; 55 };
56 56
57 sound { 57 sound {
58 compatible = "ti,dra7xx-evm-audio"; 58 compatible = "ti,dra7xx-evm-audio";
59 ti,model = "DRA7xx-EVM"; 59 ti,model = "DRA7xx-EVM";
60 ti,audio-codec = <&tlv320aic3106>; 60 ti,audio-codec = <&tlv320aic3106>;
61 ti,mcasp-controller = <&mcasp3>; 61 ti,mcasp-controller = <&mcasp3>;
62 ti,codec-clock-rate = <5644800>; 62 ti,codec-clock-rate = <5644800>;
63 clocks = <&atl_clkin 2>; 63 clocks = <&atl_clkin 2>;
64 clock-names = "ti,codec-clock"; 64 clock-names = "ti,codec-clock";
65 ti,audio-routing = 65 ti,audio-routing =
66 "Headphone Jack", "HPLOUT", 66 "Headphone Jack", "HPLOUT",
67 "Headphone Jack", "HPROUT", 67 "Headphone Jack", "HPROUT",
68 "LINE1L", "Line In", 68 "LINE1L", "Line In",
69 "LINE1R", "Line In"; 69 "LINE1R", "Line In";
70 }; 70 };
71 }; 71 };
72 72
73 &dra7_pmx_core { 73 &dra7_pmx_core {
74 pinctrl-names = "default"; 74 pinctrl-names = "default";
75 pinctrl-0 = < 75 pinctrl-0 = <
76 &vout1_pins 76 &vout1_pins
77 &irq_pins 77 &irq_pins
78 &atl_pins 78 &atl_pins
79 &hpd_pin 79 &hpd_pin
80 >; 80 >;
81 81
82 atl_pins: pinmux_atl_pins { 82 atl_pins: pinmux_atl_pins {
83 pinctrl-single,pins = < 83 pinctrl-single,pins = <
84 0x298 0x00000005 /* xref_clk1.atl_clk1 OUTPUT | MODE5 */ 84 0x298 0x00000005 /* xref_clk1.atl_clk1 OUTPUT | MODE5 */
85 0x29c 0x00000005 /* xref_clk2.atl_clk2 OUTPUT | MODE5 */ 85 0x29c 0x00000005 /* xref_clk2.atl_clk2 OUTPUT | MODE5 */
86 >; 86 >;
87 }; 87 };
88 88
89 i2c1_pins: pinmux_i2c1_pins { 89 i2c1_pins: pinmux_i2c1_pins {
90 pinctrl-single,pins = < 90 pinctrl-single,pins = <
91 0x400 0x60000 /* i2c1_sda */ 91 0x400 0x60000 /* i2c1_sda */
92 0x404 0x60000 /* i2c1_scl */ 92 0x404 0x60000 /* i2c1_scl */
93 >; 93 >;
94 }; 94 };
95 95
96 i2c2_pins: pinmux_i2c2_pins { 96 i2c2_pins: pinmux_i2c2_pins {
97 pinctrl-single,pins = < 97 pinctrl-single,pins = <
98 0x408 0x60000 /* i2c2_sda */ 98 0x408 0x60000 /* i2c2_sda */
99 0x40c 0x60000 /* i2c2_scl */ 99 0x40c 0x60000 /* i2c2_scl */
100 >; 100 >;
101 }; 101 };
102 102
103 i2c3_pins: pinmux_i2c3_pins { 103 i2c3_pins: pinmux_i2c3_pins {
104 pinctrl-single,pins = < 104 pinctrl-single,pins = <
105 0x410 0x60000 /* i2c3_sda */ 105 0x410 0x60000 /* i2c3_sda */
106 0x414 0x60000 /* i2c3_scl */ 106 0x414 0x60000 /* i2c3_scl */
107 >; 107 >;
108 }; 108 };
109 109
110 irq_pins: pinmux_irq_pins { 110 irq_pins: pinmux_irq_pins {
111 pinctrl-single,pins = < 111 pinctrl-single,pins = <
112 0x420 0x1 /* Wakeup2 INPUT | MODE1 */ 112 0x420 0x1 /* Wakeup2 INPUT | MODE1 */
113 >; 113 >;
114 }; 114 };
115 115
116 mmc1_pins: pinmux_mmc1_pins { 116 mmc1_pins: pinmux_mmc1_pins {
117 pinctrl-single,pins = < 117 pinctrl-single,pins = <
118 0x36c 0x4000e /* mmc1sdcd.gpio INPUT | MODE15 */ 118 0x36c 0x4000e /* mmc1sdcd.gpio INPUT | MODE15 */
119 >; 119 >;
120 }; 120 };
121 121
122 mmc1_muxpu: pinmux_mmc1_muxpu { 122 mmc1_muxpu: pinmux_mmc1_muxpu {
123 pinctrl-single,pins = < 123 pinctrl-single,pins = <
124 0x354 0x60000 /* mmc1_clk.clk INPUT PULLUP | MODE0 */ 124 0x354 0x60000 /* mmc1_clk.clk INPUT PULLUP | MODE0 */
125 0x358 0x60000 /* mmc1_cmd.cmd INPUT PULLUP | MODE0 */ 125 0x358 0x60000 /* mmc1_cmd.cmd INPUT PULLUP | MODE0 */
126 0x35c 0x60000 /* mmc1_dat0.dat0 INPUT PULLUP | MODE0 */ 126 0x35c 0x60000 /* mmc1_dat0.dat0 INPUT PULLUP | MODE0 */
127 0x360 0x60000 /* mmc1_dat1.dat1 INPUT PULLUP | MODE0 */ 127 0x360 0x60000 /* mmc1_dat1.dat1 INPUT PULLUP | MODE0 */
128 0x364 0x60000 /* mmc1_dat2.dat2 INPUT PULLUP | MODE0 */ 128 0x364 0x60000 /* mmc1_dat2.dat2 INPUT PULLUP | MODE0 */
129 0x368 0x60000 /* mmc1_dat3.dat3 INPUT PULLUP | MODE0 */ 129 0x368 0x60000 /* mmc1_dat3.dat3 INPUT PULLUP | MODE0 */
130 >; 130 >;
131 }; 131 };
132 132
133 mmc1_muxpd: pinmux_mmc1_muxpd { 133 mmc1_muxpd: pinmux_mmc1_muxpd {
134 pinctrl-single,pins = < 134 pinctrl-single,pins = <
135 0x354 0x20000 /* mmc1_clk.clk INPUT PULLUP | MODE0 */ 135 0x354 0x20000 /* mmc1_clk.clk INPUT PULLUP | MODE0 */
136 0x358 0x20000 /* mmc1_cmd.cmd INPUT PULLUP | MODE0 */ 136 0x358 0x20000 /* mmc1_cmd.cmd INPUT PULLUP | MODE0 */
137 0x35c 0x20000 /* mmc1_dat0.dat0 INPUT PULLUP | MODE0 */ 137 0x35c 0x20000 /* mmc1_dat0.dat0 INPUT PULLUP | MODE0 */
138 0x360 0x20000 /* mmc1_dat1.dat1 INPUT PULLUP | MODE0 */ 138 0x360 0x20000 /* mmc1_dat1.dat1 INPUT PULLUP | MODE0 */
139 0x364 0x20000 /* mmc1_dat2.dat2 INPUT PULLUP | MODE0 */ 139 0x364 0x20000 /* mmc1_dat2.dat2 INPUT PULLUP | MODE0 */
140 0x368 0x20000 /* mmc1_dat3.dat3 INPUT PULLUP | MODE0 */ 140 0x368 0x20000 /* mmc1_dat3.dat3 INPUT PULLUP | MODE0 */
141 >; 141 >;
142 }; 142 };
143 143
144 mcspi1_pins: pinmux_mcspi1_pins { 144 mcspi1_pins: pinmux_mcspi1_pins {
145 pinctrl-single,pins = < 145 pinctrl-single,pins = <
146 0x3a4 0x40000 /* spi2_clk */ 146 0x3a4 0x40000 /* spi2_clk */
147 0x3a8 0x40000 /* spi2_d1 */ 147 0x3a8 0x40000 /* spi2_d1 */
148 0x3ac 0x40000 /* spi2_d0 */ 148 0x3ac 0x40000 /* spi2_d0 */
149 0x3b0 0xc0000 /* spi2_cs0 */ 149 0x3b0 0xc0000 /* spi2_cs0 */
150 0x3b4 0xc0000 /* spi2_cs1 */ 150 0x3b4 0xc0000 /* spi2_cs1 */
151 0x3bc 0xe0006 /* spi2_cs3 */ 151 0x3bc 0xe0006 /* spi2_cs3 */
152 >; 152 >;
153 }; 153 };
154 154
155 mcspi2_pins: pinmux_mcspi2_pins { 155 mcspi2_pins: pinmux_mcspi2_pins {
156 pinctrl-single,pins = < 156 pinctrl-single,pins = <
157 0x3c0 0x40000 /* spi2_sclk */ 157 0x3c0 0x40000 /* spi2_sclk */
158 0x3c4 0xc0000 /* spi2_d1 */ 158 0x3c4 0xc0000 /* spi2_d1 */
159 0x3c8 0xc0000 /* spi2_d1 */ 159 0x3c8 0xc0000 /* spi2_d1 */
160 0x3cc 0xe0000 /* spi2_cs0 */ 160 0x3cc 0xe0000 /* spi2_cs0 */
161 >; 161 >;
162 }; 162 };
163 163
164 uart1_pins: pinmux_uart1_pins { 164 uart1_pins: pinmux_uart1_pins {
165 pinctrl-single,pins = < 165 pinctrl-single,pins = <
166 0x3e0 0xe0000 /* uart1_rxd */ 166 0x3e0 0xe0000 /* uart1_rxd */
167 0x3e4 0xe0000 /* uart1_txd */ 167 0x3e4 0xe0000 /* uart1_txd */
168 >; 168 >;
169 }; 169 };
170 170
171 uart3_pins: pinmux_uart3_pins { 171 uart3_pins: pinmux_uart3_pins {
172 pinctrl-single,pins = < 172 pinctrl-single,pins = <
173 0x248 0xc0000 /* uart3_rxd */ 173 0x248 0xc0000 /* uart3_rxd */
174 0x24c 0xc0000 /* uart3_txd */ 174 0x24c 0xc0000 /* uart3_txd */
175 >; 175 >;
176 }; 176 };
177 177
178 qspi1_pins: pinmux_qspi1_pins { 178 qspi1_pins: pinmux_qspi1_pins {
179 pinctrl-single,pins = < 179 pinctrl-single,pins = <
180 0x4c 0x40001 /* gpmc_a3.qspi1_cs2 */ 180 0x4c 0x40001 /* gpmc_a3.qspi1_cs2 */
181 0x50 0x40001 /* gpmc_a4.qspi1_cs3 */ 181 0x50 0x40001 /* gpmc_a4.qspi1_cs3 */
182 0x74 0x40001 /* gpmc_a13.qspi1_rtclk */ 182 0x74 0x40001 /* gpmc_a13.qspi1_rtclk */
183 0x78 0x40001 /* gpmc_a14.qspi1_d3 */ 183 0x78 0x40001 /* gpmc_a14.qspi1_d3 */
184 0x7c 0x40001 /* gpmc_a15.qspi1_d2 */ 184 0x7c 0x40001 /* gpmc_a15.qspi1_d2 */
185 0x80 0x40001 /* gpmc_a16.qspi1_d1 */ 185 0x80 0x40001 /* gpmc_a16.qspi1_d1 */
186 0x84 0x40001 /* gpmc_a17.qspi1_d0 */ 186 0x84 0x40001 /* gpmc_a17.qspi1_d0 */
187 0x88 0x40001 /* qpmc_a18.qspi1_sclk */ 187 0x88 0x40001 /* qpmc_a18.qspi1_sclk */
188 0xb8 0x60001 /* gpmc_cs2.qspi1_cs0 */ 188 0xb8 0x60001 /* gpmc_cs2.qspi1_cs0 */
189 0xbc 0x60001 /* gpmc_cs3.qspi1_cs1 */ 189 0xbc 0x60001 /* gpmc_cs3.qspi1_cs1 */
190 >; 190 >;
191 }; 191 };
192 192
193 usb1_pins: pinmux_usb1_pins { 193 usb1_pins: pinmux_usb1_pins {
194 pinctrl-single,pins = < 194 pinctrl-single,pins = <
195 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */ 195 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
196 >; 196 >;
197 }; 197 };
198 198
199 usb2_pins: pinmux_usb2_pins { 199 usb2_pins: pinmux_usb2_pins {
200 pinctrl-single,pins = < 200 pinctrl-single,pins = <
201 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */ 201 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
202 >; 202 >;
203 }; 203 };
204 204
205 vout1_pins: pinmux_vout1_pins { 205 vout1_pins: pinmux_vout1_pins {
206 pinctrl-single,pins = < 206 pinctrl-single,pins = <
207 0x1C8 0x0 /* vout1_clk OUTPUT | MODE0 */ 207 0x1C8 0x0 /* vout1_clk OUTPUT | MODE0 */
208 0x1CC 0x0 /* vout1_de OUTPUT | MODE0 */ 208 0x1CC 0x0 /* vout1_de OUTPUT | MODE0 */
209 0x1D0 0x0 /* vout1_fld OUTPUT | MODE0 */ 209 0x1D0 0x0 /* vout1_fld OUTPUT | MODE0 */
210 0x1D4 0x0 /* vout1_hsync OUTPUT | MODE0 */ 210 0x1D4 0x0 /* vout1_hsync OUTPUT | MODE0 */
211 0x1D8 0x0 /* vout1_vsync OUTPUT | MODE0 */ 211 0x1D8 0x0 /* vout1_vsync OUTPUT | MODE0 */
212 0x1DC 0x0 /* vout1_d0 OUTPUT | MODE0 */ 212 0x1DC 0x0 /* vout1_d0 OUTPUT | MODE0 */
213 0x1E0 0x0 /* vout1_d1 OUTPUT | MODE0 */ 213 0x1E0 0x0 /* vout1_d1 OUTPUT | MODE0 */
214 0x1E4 0x0 /* vout1_d2 OUTPUT | MODE0 */ 214 0x1E4 0x0 /* vout1_d2 OUTPUT | MODE0 */
215 0x1E8 0x0 /* vout1_d3 OUTPUT | MODE0 */ 215 0x1E8 0x0 /* vout1_d3 OUTPUT | MODE0 */
216 0x1EC 0x0 /* vout1_d4 OUTPUT | MODE0 */ 216 0x1EC 0x0 /* vout1_d4 OUTPUT | MODE0 */
217 0x1F0 0x0 /* vout1_d5 OUTPUT | MODE0 */ 217 0x1F0 0x0 /* vout1_d5 OUTPUT | MODE0 */
218 0x1F4 0x0 /* vout1_d6 OUTPUT | MODE0 */ 218 0x1F4 0x0 /* vout1_d6 OUTPUT | MODE0 */
219 0x1F8 0x0 /* vout1_d7 OUTPUT | MODE0 */ 219 0x1F8 0x0 /* vout1_d7 OUTPUT | MODE0 */
220 0x1FC 0x0 /* vout1_d8 OUTPUT | MODE0 */ 220 0x1FC 0x0 /* vout1_d8 OUTPUT | MODE0 */
221 0x200 0x0 /* vout1_d9 OUTPUT | MODE0 */ 221 0x200 0x0 /* vout1_d9 OUTPUT | MODE0 */
222 0x204 0x0 /* vout1_d10 OUTPUT | MODE0 */ 222 0x204 0x0 /* vout1_d10 OUTPUT | MODE0 */
223 0x208 0x0 /* vout1_d11 OUTPUT | MODE0 */ 223 0x208 0x0 /* vout1_d11 OUTPUT | MODE0 */
224 0x20C 0x0 /* vout1_d12 OUTPUT | MODE0 */ 224 0x20C 0x0 /* vout1_d12 OUTPUT | MODE0 */
225 0x210 0x0 /* vout1_d13 OUTPUT | MODE0 */ 225 0x210 0x0 /* vout1_d13 OUTPUT | MODE0 */
226 0x214 0x0 /* vout1_d14 OUTPUT | MODE0 */ 226 0x214 0x0 /* vout1_d14 OUTPUT | MODE0 */
227 0x218 0x0 /* vout1_d15 OUTPUT | MODE0 */ 227 0x218 0x0 /* vout1_d15 OUTPUT | MODE0 */
228 0x21C 0x0 /* vout1_d16 OUTPUT | MODE0 */ 228 0x21C 0x0 /* vout1_d16 OUTPUT | MODE0 */
229 0x220 0x0 /* vout1_d17 OUTPUT | MODE0 */ 229 0x220 0x0 /* vout1_d17 OUTPUT | MODE0 */
230 0x224 0x0 /* vout1_d18 OUTPUT | MODE0 */ 230 0x224 0x0 /* vout1_d18 OUTPUT | MODE0 */
231 0x228 0x0 /* vout1_d19 OUTPUT | MODE0 */ 231 0x228 0x0 /* vout1_d19 OUTPUT | MODE0 */
232 0x22C 0x0 /* vout1_d20 OUTPUT | MODE0 */ 232 0x22C 0x0 /* vout1_d20 OUTPUT | MODE0 */
233 0x230 0x0 /* vout1_d21 OUTPUT | MODE0 */ 233 0x230 0x0 /* vout1_d21 OUTPUT | MODE0 */
234 0x234 0x0 /* vout1_d22 OUTPUT | MODE0 */ 234 0x234 0x0 /* vout1_d22 OUTPUT | MODE0 */
235 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */ 235 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */
236 >; 236 >;
237 }; 237 };
238 238
239 cpsw_default: cpsw_default { 239 cpsw_default: cpsw_default {
240 pinctrl-single,pins = < 240 pinctrl-single,pins = <
241 /* Slave 1 */ 241 /* Slave 1 */
242 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ 242 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
243 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ 243 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
244 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ 244 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
245 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ 245 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
246 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ 246 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
247 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ 247 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
248 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ 248 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
249 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ 249 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
250 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ 250 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
251 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ 251 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
252 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ 252 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
253 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ 253 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
254 254
255 /* Slave 2 */ 255 /* Slave 2 */
256 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ 256 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
257 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ 257 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
258 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ 258 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
259 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ 259 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
260 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ 260 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
261 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ 261 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
262 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ 262 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
263 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ 263 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
264 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ 264 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
265 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ 265 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
266 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ 266 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
267 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ 267 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
268 >; 268 >;
269 269
270 }; 270 };
271 cpsw_sleep: cpsw_sleep { 271 cpsw_sleep: cpsw_sleep {
272 pinctrl-single,pins = < 272 pinctrl-single,pins = <
273 /* Slave 1 */ 273 /* Slave 1 */
274 0x250 (PIN_OFF_NONE) 274 0x250 (PIN_OFF_NONE)
275 0x254 (PIN_OFF_NONE) 275 0x254 (PIN_OFF_NONE)
276 0x258 (PIN_OFF_NONE) 276 0x258 (PIN_OFF_NONE)
277 0x25c (PIN_OFF_NONE) 277 0x25c (PIN_OFF_NONE)
278 0x260 (PIN_OFF_NONE) 278 0x260 (PIN_OFF_NONE)
279 0x264 (PIN_OFF_NONE) 279 0x264 (PIN_OFF_NONE)
280 0x268 (PIN_OFF_NONE) 280 0x268 (PIN_OFF_NONE)
281 0x26c (PIN_OFF_NONE) 281 0x26c (PIN_OFF_NONE)
282 0x270 (PIN_OFF_NONE) 282 0x270 (PIN_OFF_NONE)
283 0x274 (PIN_OFF_NONE) 283 0x274 (PIN_OFF_NONE)
284 0x278 (PIN_OFF_NONE) 284 0x278 (PIN_OFF_NONE)
285 0x27c (PIN_OFF_NONE) 285 0x27c (PIN_OFF_NONE)
286 286
287 /* Slave 1 */ 287 /* Slave 1 */
288 0x198 (PIN_OFF_NONE) 288 0x198 (PIN_OFF_NONE)
289 0x19c (PIN_OFF_NONE) 289 0x19c (PIN_OFF_NONE)
290 0x1a0 (PIN_OFF_NONE) 290 0x1a0 (PIN_OFF_NONE)
291 0x1a4 (PIN_OFF_NONE) 291 0x1a4 (PIN_OFF_NONE)
292 0x1a8 (PIN_OFF_NONE) 292 0x1a8 (PIN_OFF_NONE)
293 0x1ac (PIN_OFF_NONE) 293 0x1ac (PIN_OFF_NONE)
294 0x1b0 (PIN_OFF_NONE) 294 0x1b0 (PIN_OFF_NONE)
295 0x1b4 (PIN_OFF_NONE) 295 0x1b4 (PIN_OFF_NONE)
296 0x1b8 (PIN_OFF_NONE) 296 0x1b8 (PIN_OFF_NONE)
297 0x1bc (PIN_OFF_NONE) 297 0x1bc (PIN_OFF_NONE)
298 0x1c0 (PIN_OFF_NONE) 298 0x1c0 (PIN_OFF_NONE)
299 0x1c4 (PIN_OFF_NONE) 299 0x1c4 (PIN_OFF_NONE)
300 >; 300 >;
301 }; 301 };
302 302
303 davinci_mdio_default: davinci_mdio_default { 303 davinci_mdio_default: davinci_mdio_default {
304 pinctrl-single,pins = < 304 pinctrl-single,pins = <
305 /* MDIO */ 305 /* MDIO */
306 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */ 306 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
307 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */ 307 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
308 >; 308 >;
309 }; 309 };
310 310
311 davinci_mdio_sleep: davinci_mdio_sleep { 311 davinci_mdio_sleep: davinci_mdio_sleep {
312 pinctrl-single,pins = < 312 pinctrl-single,pins = <
313 0x23c (PIN_OFF_NONE) 313 0x23c (PIN_OFF_NONE)
314 0x240 (PIN_OFF_NONE) 314 0x240 (PIN_OFF_NONE)
315 >; 315 >;
316 }; 316 };
317 317
318 nand_flash_x16: nand_flash_x16 { 318 nand_flash_x16: nand_flash_x16 {
319 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch 319 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
320 * So NAND flash requires following switch settings: 320 * So NAND flash requires following switch settings:
321 * SW5.9 (GPMC_WPN) = LOW 321 * SW5.9 (GPMC_WPN) = LOW
322 * SW5.1 (NAND_BOOTn) = HIGH */ 322 * SW5.1 (NAND_BOOTn) = HIGH */
323 pinctrl-single,pins = < 323 pinctrl-single,pins = <
324 0x0 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad0 */ 324 0x0 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad0 */
325 0x4 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad1 */ 325 0x4 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad1 */
326 0x8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad2 */ 326 0x8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad2 */
327 0xc 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad3 */ 327 0xc 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad3 */
328 0x10 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad4 */ 328 0x10 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad4 */
329 0x14 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad5 */ 329 0x14 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad5 */
330 0x18 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad6 */ 330 0x18 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad6 */
331 0x1c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad7 */ 331 0x1c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad7 */
332 0x20 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad8 */ 332 0x20 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad8 */
333 0x24 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad9 */ 333 0x24 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad9 */
334 0x28 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad10 */ 334 0x28 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad10 */
335 0x2c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad11 */ 335 0x2c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad11 */
336 0x30 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad12 */ 336 0x30 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad12 */
337 0x34 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad13 */ 337 0x34 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad13 */
338 0x38 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad14 */ 338 0x38 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad14 */
339 0x3c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad15 */ 339 0x3c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad15 */
340 0xD8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_wait0 */ 340 0xD8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_wait0 */
341 0xCC 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_wen */ 341 0xCC 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_wen */
342 0xB4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_csn0 */ 342 0xB4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_csn0 */
343 0xC4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_advn_ale */ 343 0xC4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_advn_ale */
344 0xC8 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_oen_ren */ 344 0xC8 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_oen_ren */
345 0xD0 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_be0n_cle */ 345 0xD0 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_be0n_cle */
346 >; 346 >;
347 }; 347 };
348 348
349 mcasp3_pins: pinmux_mcasp3_pins { 349 mcasp3_pins: pinmux_mcasp3_pins {
350 pinctrl-single,pins = < 350 pinctrl-single,pins = <
351 0x324 0x10000 /* mcasp3_aclkx.mcasp3_aclkx Mode0.Output.PD */ 351 0x324 0x10000 /* mcasp3_aclkx.mcasp3_aclkx Mode0.Output.PD */
352 0x328 0x10000 /* mcasp3_fsx.mcasp3_fsx Mode0.Output.PD */ 352 0x328 0x10000 /* mcasp3_fsx.mcasp3_fsx Mode0.Output.PD */
353 0x32c 0x10000 /* mcasp3_axr0.mcasp3_axr0 Mode0.Output.PD */ 353 0x32c 0x10000 /* mcasp3_axr0.mcasp3_axr0 Mode0.Output.PD */
354 0x330 0x50000 /* mcasp3_axr1.mcasp3_axr1 Mode0.Input.PD */ 354 0x330 0x50000 /* mcasp3_axr1.mcasp3_axr1 Mode0.Input.PD */
355 >; 355 >;
356 }; 356 };
357 357
358 hpd_pin: pinmux_hpd_pin { 358 hpd_pin: pinmux_hpd_pin {
359 pinctrl-single,pins = < 359 pinctrl-single,pins = <
360 0x3b8 0x5000e /* gpio7_12 INPUT | MODE14 */ 360 0x3b8 0x5000e /* gpio7_12 INPUT | MODE14 */
361 >; 361 >;
362 }; 362 };
363 }; 363 };
364 364
365 &i2c1 { 365 &i2c1 {
366 status = "okay"; 366 status = "okay";
367 pinctrl-names = "default"; 367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c1_pins>; 368 pinctrl-0 = <&i2c1_pins>;
369 clock-frequency = <400000>; 369 clock-frequency = <400000>;
370 370
371 tps659038: tps659038@58 { 371 tps659038: tps659038@58 {
372 compatible = "ti,tps659038"; 372 compatible = "ti,tps659038";
373 reg = <0x58>; 373 reg = <0x58>;
374 374
375 tps659038_pmic { 375 tps659038_pmic {
376 compatible = "ti,tps659038-pmic"; 376 compatible = "ti,tps659038-pmic";
377 377
378 regulators { 378 regulators {
379 smps123_reg: smps123 { 379 smps123_reg: smps123 {
380 /* VDD_MPU */ 380 /* VDD_MPU */
381 regulator-name = "smps123"; 381 regulator-name = "smps123";
382 regulator-min-microvolt = < 850000>; 382 regulator-min-microvolt = < 850000>;
383 regulator-max-microvolt = <1250000>; 383 regulator-max-microvolt = <1250000>;
384 regulator-always-on; 384 regulator-always-on;
385 regulator-boot-on; 385 regulator-boot-on;
386 }; 386 };
387 387
388 smps45_reg: smps45 { 388 smps45_reg: smps45 {
389 /* VDD_DSPEVE */ 389 /* VDD_DSPEVE */
390 regulator-name = "smps45"; 390 regulator-name = "smps45";
391 regulator-min-microvolt = < 850000>; 391 regulator-min-microvolt = < 850000>;
392 regulator-max-microvolt = <1150000>; 392 regulator-max-microvolt = <1150000>;
393 regulator-boot-on; 393 regulator-boot-on;
394 }; 394 };
395 395
396 smps6_reg: smps6 { 396 smps6_reg: smps6 {
397 /* VDD_GPU - over VDD_SMPS6 */ 397 /* VDD_GPU - over VDD_SMPS6 */
398 regulator-name = "smps6"; 398 regulator-name = "smps6";
399 regulator-min-microvolt = <850000>; 399 regulator-min-microvolt = <850000>;
400 regulator-max-microvolt = <12500000>; 400 regulator-max-microvolt = <12500000>;
401 regulator-boot-on; 401 regulator-boot-on;
402 }; 402 };
403 403
404 smps7_reg: smps7 { 404 smps7_reg: smps7 {
405 /* CORE_VDD */ 405 /* CORE_VDD */
406 regulator-name = "smps7"; 406 regulator-name = "smps7";
407 regulator-min-microvolt = <850000>; 407 regulator-min-microvolt = <850000>;
408 regulator-max-microvolt = <1030000>; 408 regulator-max-microvolt = <1030000>;
409 regulator-always-on; 409 regulator-always-on;
410 regulator-boot-on; 410 regulator-boot-on;
411 }; 411 };
412 412
413 smps8_reg: smps8 { 413 smps8_reg: smps8 {
414 /* VDD_IVAHD */ 414 /* VDD_IVAHD */
415 regulator-name = "smps8"; 415 regulator-name = "smps8";
416 regulator-min-microvolt = < 850000>; 416 regulator-min-microvolt = < 850000>;
417 regulator-max-microvolt = <1250000>; 417 regulator-max-microvolt = <1250000>;
418 regulator-boot-on; 418 regulator-boot-on;
419 }; 419 };
420 420
421 smps9_reg: smps9 { 421 smps9_reg: smps9 {
422 /* VDDS1V8 */ 422 /* VDDS1V8 */
423 regulator-name = "smps9"; 423 regulator-name = "smps9";
424 regulator-min-microvolt = <1800000>; 424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <1800000>; 425 regulator-max-microvolt = <1800000>;
426 regulator-always-on; 426 regulator-always-on;
427 regulator-boot-on; 427 regulator-boot-on;
428 }; 428 };
429 429
430 ldo1_reg: ldo1 { 430 ldo1_reg: ldo1 {
431 /* LDO1_OUT --> SDIO */ 431 /* LDO1_OUT --> SDIO */
432 regulator-name = "ldo1"; 432 regulator-name = "ldo1";
433 regulator-min-microvolt = <1800000>; 433 regulator-min-microvolt = <1800000>;
434 regulator-max-microvolt = <3300000>; 434 regulator-max-microvolt = <3300000>;
435 regulator-always-on; 435 regulator-always-on;
436 regulator-boot-on; 436 regulator-boot-on;
437 }; 437 };
438 438
439 ldo2_reg: ldo2 { 439 ldo2_reg: ldo2 {
440 /* VDD_RTCIO */ 440 /* VDD_RTCIO */
441 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 441 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
442 regulator-name = "ldo2"; 442 regulator-name = "ldo2";
443 regulator-min-microvolt = <3300000>; 443 regulator-min-microvolt = <3300000>;
444 regulator-max-microvolt = <3300000>; 444 regulator-max-microvolt = <3300000>;
445 regulator-boot-on; 445 regulator-boot-on;
446 }; 446 };
447 447
448 ldo3_reg: ldo3 { 448 ldo3_reg: ldo3 {
449 /* VDDA_1V8_PHY */ 449 /* VDDA_1V8_PHY */
450 regulator-name = "ldo3"; 450 regulator-name = "ldo3";
451 regulator-min-microvolt = <1800000>; 451 regulator-min-microvolt = <1800000>;
452 regulator-max-microvolt = <1800000>; 452 regulator-max-microvolt = <1800000>;
453 regulator-boot-on; 453 regulator-boot-on;
454 }; 454 };
455 455
456 ldo9_reg: ldo9 { 456 ldo9_reg: ldo9 {
457 /* VDD_RTC */ 457 /* VDD_RTC */
458 regulator-name = "ldo9"; 458 regulator-name = "ldo9";
459 regulator-min-microvolt = <1050000>; 459 regulator-min-microvolt = <1050000>;
460 regulator-max-microvolt = <1050000>; 460 regulator-max-microvolt = <1050000>;
461 regulator-boot-on; 461 regulator-boot-on;
462 }; 462 };
463 463
464 ldoln_reg: ldoln { 464 ldoln_reg: ldoln {
465 /* VDDA_1V8_PLL */ 465 /* VDDA_1V8_PLL */
466 regulator-name = "ldoln"; 466 regulator-name = "ldoln";
467 regulator-min-microvolt = <1800000>; 467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>; 468 regulator-max-microvolt = <1800000>;
469 regulator-always-on; 469 regulator-always-on;
470 regulator-boot-on; 470 regulator-boot-on;
471 }; 471 };
472 472
473 ldousb_reg: ldousb { 473 ldousb_reg: ldousb {
474 /* VDDA_3V_USB: VDDA_USBHS33 */ 474 /* VDDA_3V_USB: VDDA_USBHS33 */
475 regulator-name = "ldousb"; 475 regulator-name = "ldousb";
476 regulator-min-microvolt = <3300000>; 476 regulator-min-microvolt = <3300000>;
477 regulator-max-microvolt = <3300000>; 477 regulator-max-microvolt = <3300000>;
478 regulator-boot-on; 478 regulator-boot-on;
479 }; 479 };
480 480
481 }; 481 };
482 }; 482 };
483 }; 483 };
484 484
485 pcf_gpio_20: gpio@20 { 485 pcf_gpio_20: gpio@20 {
486 compatible = "ti,pcf8575"; 486 compatible = "ti,pcf8575";
487 reg = <0x20>; 487 reg = <0x20>;
488 lines-initial-states = <0x4000>; 488 lines-initial-states = <0x4000>;
489 gpio-controller; 489 gpio-controller;
490 #gpio-cells = <2>; 490 #gpio-cells = <2>;
491 interrupt-parent = <&gpio6>; 491 interrupt-parent = <&gpio6>;
492 interrupts = <11 2>; 492 interrupts = <11 2>;
493 interrupt-controller; 493 interrupt-controller;
494 #interrupt-cells = <2>; 494 #interrupt-cells = <2>;
495 }; 495 };
496 496
497 gpio21: gpio@21 { 497 gpio21: gpio@21 {
498 compatible = "ti,pcf8575"; 498 compatible = "ti,pcf8575";
499 reg = <0x21>; 499 reg = <0x21>;
500 lines-initial-states = <0x1408>; 500 lines-initial-states = <0x1408>;
501 gpio-controller; 501 gpio-controller;
502 #gpio-cells = <2>; 502 #gpio-cells = <2>;
503 interrupt-parent = <&pcf_gpio_20>; 503 interrupt-parent = <&pcf_gpio_20>;
504 interrupts = <14 2>; 504 interrupts = <14 2>;
505 interrupt-controller; 505 interrupt-controller;
506 #interrupt-cells = <2>; 506 #interrupt-cells = <2>;
507 }; 507 };
508 508
509 /* TLC chip for LCD panel power and backlight */ 509 /* TLC chip for LCD panel power and backlight */
510 tlc59108: tlc59108@40 { 510 tlc59108: tlc59108@40 {
511 compatible = "ti,tlc59108"; 511 compatible = "ti,tlc59108";
512 reg = <0x40>; 512 reg = <0x40>;
513 gpios = <&pcf_gpio_20 13 0>; /* P15, CON_LCD_PWR_DN */ 513 gpios = <&pcf_gpio_20 13 0>; /* P15, CON_LCD_PWR_DN */
514 video-source = <&dpi1>; 514 video-source = <&dpi1>;
515 data-lines = <24>; 515 data-lines = <24>;
516 }; 516 };
517 517
518 mxt244: touchscreen@4a { 518 mxt244: touchscreen@4a {
519 compatible = "atmel,mXT244"; 519 compatible = "atmel,mXT244";
520 status = "okay"; 520 status = "okay";
521 reg = <0x4a>; 521 reg = <0x4a>;
522 interrupts = <0 119 0x4>; 522 interrupts = <0 119 0x4>;
523 523
524 atmel,config = < 524 atmel,config = <
525 /* MXT244_GEN_COMMAND(6) */ 525 /* MXT244_GEN_COMMAND(6) */
526 0x00 0x00 0x00 0x00 0x00 0x00 526 0x00 0x00 0x00 0x00 0x00 0x00
527 /* MXT244_GEN_POWER(7) */ 527 /* MXT244_GEN_POWER(7) */
528 0x20 0xff 0x32 528 0x20 0xff 0x32
529 /* MXT244_GEN_ACQUIRE(8) */ 529 /* MXT244_GEN_ACQUIRE(8) */
530 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23 530 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
531 /* MXT244_TOUCH_MULTI(9) */ 531 /* MXT244_TOUCH_MULTI(9) */
532 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00 532 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
533 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00 533 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
534 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 534 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
535 0x00 535 0x00
536 /* MXT244_TOUCH_KEYARRAY(15) */ 536 /* MXT244_TOUCH_KEYARRAY(15) */
537 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 537 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
538 0x00 538 0x00
539 /* MXT244_COMMSCONFIG_T18(2) */ 539 /* MXT244_COMMSCONFIG_T18(2) */
540 0x00 0x00 540 0x00 0x00
541 /* MXT244_SPT_GPIOPWM(19) */ 541 /* MXT244_SPT_GPIOPWM(19) */
542 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 542 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
543 0x00 0x00 0x00 0x00 0x00 0x00 543 0x00 0x00 0x00 0x00 0x00 0x00
544 /* MXT244_PROCI_GRIPFACE(20) */ 544 /* MXT244_PROCI_GRIPFACE(20) */
545 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04 545 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
546 0x0f 0x0a 546 0x0f 0x0a
547 /* MXT244_PROCG_NOISE(22) */ 547 /* MXT244_PROCG_NOISE(22) */
548 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00 548 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
549 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03 549 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
550 /* MXT244_TOUCH_PROXIMITY(23) */ 550 /* MXT244_TOUCH_PROXIMITY(23) */
551 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 551 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
552 0x00 0x00 0x00 0x00 0x00 552 0x00 0x00 0x00 0x00 0x00
553 /* MXT244_PROCI_ONETOUCH(24) */ 553 /* MXT244_PROCI_ONETOUCH(24) */
554 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 554 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
555 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 555 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
556 /* MXT244_SPT_SELFTEST(25) */ 556 /* MXT244_SPT_SELFTEST(25) */
557 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 557 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
558 0x00 0x00 0x00 0x00 558 0x00 0x00 0x00 0x00
559 /* MXT244_PROCI_TWOTOUCH(27) */ 559 /* MXT244_PROCI_TWOTOUCH(27) */
560 0x00 0x00 0x00 0x00 0x00 0x00 0x00 560 0x00 0x00 0x00 0x00 0x00 0x00 0x00
561 /* MXT244_SPT_CTECONFIG(28) */ 561 /* MXT244_SPT_CTECONFIG(28) */
562 0x00 0x00 0x02 0x08 0x10 0x00 562 0x00 0x00 0x02 0x08 0x10 0x00
563 >; 563 >;
564 564
565 atmel,x_line = <18>; 565 atmel,x_line = <18>;
566 atmel,y_line = <12>; 566 atmel,y_line = <12>;
567 atmel,x_size = <800>; 567 atmel,x_size = <800>;
568 atmel,y_size = <480>; 568 atmel,y_size = <480>;
569 atmel,blen = <0x01>; 569 atmel,blen = <0x01>;
570 atmel,threshold = <30>; 570 atmel,threshold = <30>;
571 atmel,voltage = <2800000>; 571 atmel,voltage = <2800000>;
572 atmel,orient = <0x4>; 572 atmel,orient = <0x4>;
573 }; 573 };
574 574
575 tlv320aic3106: tlv320aic3106@18 { 575 tlv320aic3106: tlv320aic3106@18 {
576 compatible = "ti,tlv320aic3106"; 576 compatible = "ti,tlv320aic3106";
577 reg = <0x18>; 577 reg = <0x18>;
578 adc-settle-ms = <40>; 578 adc-settle-ms = <40>;
579 status = "okay"; 579 status = "okay";
580 580
581 /* Regulators */ 581 /* Regulators */
582 AVDD-supply = <&evm_3v3_sw>; 582 AVDD-supply = <&evm_3v3_sw>;
583 IOVDD-supply = <&evm_3v3_sw>; 583 IOVDD-supply = <&evm_3v3_sw>;
584 DRVDD-supply = <&evm_3v3_sw>; 584 DRVDD-supply = <&evm_3v3_sw>;
585 DVDD-supply = <&aic_dvdd_1v8>; 585 DVDD-supply = <&aic_dvdd_1v8>;
586 }; 586 };
587 }; 587 };
588 588
589 &i2c2 { 589 &i2c2 {
590 status = "okay"; 590 status = "okay";
591 pinctrl-names = "default"; 591 pinctrl-names = "default";
592 pinctrl-0 = <&i2c2_pins>; 592 pinctrl-0 = <&i2c2_pins>;
593 clock-frequency = <400000>; 593 clock-frequency = <400000>;
594 594
595 pcf_hdmi: gpio@26 { 595 pcf_hdmi: gpio@26 {
596 compatible = "nxp,pcf8575"; 596 compatible = "nxp,pcf8575";
597 reg = <0x26>; 597 reg = <0x26>;
598 lines-initial-states = <0xffeb>; 598 lines-initial-states = <0xffeb>;
599 gpio-controller; 599 gpio-controller;
600 #gpio-cells = <2>; 600 #gpio-cells = <2>;
601 }; 601 };
602 }; 602 };
603 603
604 &i2c3 { 604 &i2c3 {
605 status = "okay"; 605 status = "okay";
606 pinctrl-names = "default"; 606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c3_pins>; 607 pinctrl-0 = <&i2c3_pins>;
608 clock-frequency = <3400000>; 608 clock-frequency = <3400000>;
609 }; 609 };
610 610
611 &mcspi1 { 611 &mcspi1 {
612 status = "okay"; 612 status = "okay";
613 pinctrl-names = "default"; 613 pinctrl-names = "default";
614 pinctrl-0 = <&mcspi1_pins>; 614 pinctrl-0 = <&mcspi1_pins>;
615 }; 615 };
616 616
617 &mcspi2 { 617 &mcspi2 {
618 status = "okay"; 618 status = "okay";
619 pinctrl-names = "default"; 619 pinctrl-names = "default";
620 pinctrl-0 = <&mcspi2_pins>; 620 pinctrl-0 = <&mcspi2_pins>;
621 }; 621 };
622 622
623 &uart1 { 623 &uart1 {
624 status = "okay"; 624 status = "okay";
625 pinctrl-names = "default"; 625 pinctrl-names = "default";
626 pinctrl-0 = <&uart1_pins>; 626 pinctrl-0 = <&uart1_pins>;
627 }; 627 };
628 628
629 &uart3 { 629 &uart3 {
630 status = "okay"; 630 status = "okay";
631 pinctrl-names = "default"; 631 pinctrl-names = "default";
632 pinctrl-0 = <&uart3_pins>; 632 pinctrl-0 = <&uart3_pins>;
633 }; 633 };
634 634
635 &qspi { 635 &qspi {
636 status = "okay"; 636 status = "okay";
637 pinctrl-names = "default"; 637 pinctrl-names = "default";
638 pinctrl-0 = <&qspi1_pins>; 638 pinctrl-0 = <&qspi1_pins>;
639 639
640 spi-max-frequency = <48000000>; 640 spi-max-frequency = <48000000>;
641 m25p80@0 { 641 m25p80@0 {
642 compatible = "s25fl256s1"; 642 compatible = "s25fl256s1";
643 spi-max-frequency = <48000000>; 643 spi-max-frequency = <48000000>;
644 reg = <0>; 644 reg = <0>;
645 spi-tx-bus-width = <1>; 645 spi-tx-bus-width = <1>;
646 spi-rx-bus-width = <4>; 646 spi-rx-bus-width = <4>;
647 spi-cpol; 647 spi-cpol;
648 spi-cpha; 648 spi-cpha;
649 #address-cells = <1>; 649 #address-cells = <1>;
650 #size-cells = <1>; 650 #size-cells = <1>;
651 651
652 /* MTD partition table. 652 /* MTD partition table.
653 * The ROM checks the first four physical blocks 653 * The ROM checks the first four physical blocks
654 * for a valid file to boot and the flash here is 654 * for a valid file to boot and the flash here is
655 * 64KiB block size. 655 * 64KiB block size.
656 */ 656 */
657 partition@0 { 657 partition@0 {
658 label = "QSPI.SPL"; 658 label = "QSPI.SPL";
659 reg = <0x00000000 0x000010000>; 659 reg = <0x00000000 0x000010000>;
660 }; 660 };
661 partition@1 { 661 partition@1 {
662 label = "QSPI.SPL.backup1"; 662 label = "QSPI.SPL.backup1";
663 reg = <0x00010000 0x00010000>; 663 reg = <0x00010000 0x00010000>;
664 }; 664 };
665 partition@2 { 665 partition@2 {
666 label = "QSPI.SPL.backup2"; 666 label = "QSPI.SPL.backup2";
667 reg = <0x00020000 0x00010000>; 667 reg = <0x00020000 0x00010000>;
668 }; 668 };
669 partition@3 { 669 partition@3 {
670 label = "QSPI.SPL.backup3"; 670 label = "QSPI.SPL.backup3";
671 reg = <0x00030000 0x00010000>; 671 reg = <0x00030000 0x00010000>;
672 }; 672 };
673 partition@4 { 673 partition@4 {
674 label = "QSPI.u-boot"; 674 label = "QSPI.u-boot";
675 reg = <0x00040000 0x00100000>; 675 reg = <0x00040000 0x00100000>;
676 }; 676 };
677 partition@5 { 677 partition@5 {
678 label = "QSPI.u-boot-spl-os"; 678 label = "QSPI.u-boot-spl-os";
679 reg = <0x00140000 0x00010000>; 679 reg = <0x00140000 0x00010000>;
680 }; 680 };
681 partition@6 { 681 partition@6 {
682 label = "QSPI.u-boot-env"; 682 label = "QSPI.u-boot-env";
683 reg = <0x00150000 0x00010000>; 683 reg = <0x00150000 0x00010000>;
684 }; 684 };
685 partition@7 { 685 partition@7 {
686 label = "QSPI.u-boot-env.backup1"; 686 label = "QSPI.u-boot-env.backup1";
687 reg = <0x00160000 0x0010000>; 687 reg = <0x00160000 0x0010000>;
688 }; 688 };
689 partition@8 { 689 partition@8 {
690 label = "QSPI.kernel"; 690 label = "QSPI.kernel";
691 reg = <0x00170000 0x00970000>; 691 reg = <0x00170000 0x0800000>;
692 }; 692 };
693 partition@9 { 693 partition@9 {
694 label = "QSPI.file-system"; 694 label = "QSPI.file-system";
695 reg = <0x00970000 0x01690000>; 695 reg = <0x00970000 0x01690000>;
696 }; 696 };
697 }; 697 };
698 }; 698 };
699 699
700 &usb1 { 700 &usb1 {
701 dr_mode = "peripheral"; 701 dr_mode = "peripheral";
702 pinctrl-names = "default"; 702 pinctrl-names = "default";
703 pinctrl-0 = <&usb1_pins>; 703 pinctrl-0 = <&usb1_pins>;
704 }; 704 };
705 705
706 &usb2 { 706 &usb2 {
707 dr_mode = "host"; 707 dr_mode = "host";
708 pinctrl-names = "default"; 708 pinctrl-names = "default";
709 pinctrl-0 = <&usb2_pins>; 709 pinctrl-0 = <&usb2_pins>;
710 }; 710 };
711 711
712 &dwc3_1 { 712 &dwc3_1 {
713 extcon = <&extcon1>; 713 extcon = <&extcon1>;
714 }; 714 };
715 715
716 &dwc3_2 { 716 &dwc3_2 {
717 extcon = <&extcon2>; 717 extcon = <&extcon2>;
718 }; 718 };
719 719
720 &mmc1 { 720 &mmc1 {
721 status = "okay"; 721 status = "okay";
722 vmmc-supply = <&evm_3v3_sd>; 722 vmmc-supply = <&evm_3v3_sd>;
723 vmmc_aux-supply = <&ldo1_reg>; 723 vmmc_aux-supply = <&ldo1_reg>;
724 pbias-supply = <&pbias_regulator>; 724 pbias-supply = <&pbias_regulator>;
725 bus-width = <4>; 725 bus-width = <4>;
726 pinctrl-names = "default", "muxpu", "muxpd"; 726 pinctrl-names = "default", "muxpu", "muxpd";
727 pinctrl-0 = <&mmc1_pins>; 727 pinctrl-0 = <&mmc1_pins>;
728 pinctrl-1 = <&mmc1_muxpu>; 728 pinctrl-1 = <&mmc1_muxpu>;
729 pinctrl-2 = <&mmc1_muxpd>; 729 pinctrl-2 = <&mmc1_muxpd>;
730 cd-gpios = <&gpio6 27 0>; /* gpio 187 */ 730 cd-gpios = <&gpio6 27 0>; /* gpio 187 */
731 }; 731 };
732 732
733 &mmc2 { 733 &mmc2 {
734 status = "okay"; 734 status = "okay";
735 vmmc-supply = <&evm_3v3_sw>; 735 vmmc-supply = <&evm_3v3_sw>;
736 bus-width = <8>; 736 bus-width = <8>;
737 ti,non-removable; 737 ti,non-removable;
738 cap-mmc-dual-data-rate; 738 cap-mmc-dual-data-rate;
739 }; 739 };
740 740
741 &dss { 741 &dss {
742 vdda_video-supply = <&ldoln_reg>; 742 vdda_video-supply = <&ldoln_reg>;
743 }; 743 };
744 744
745 &hdmi { 745 &hdmi {
746 vdda_hdmi_dac-supply = <&ldo3_reg>; 746 vdda_hdmi_dac-supply = <&ldo3_reg>;
747 }; 747 };
748 748
749 &avs_mpu { 749 &avs_mpu {
750 avs-supply = <&smps123_reg>; 750 avs-supply = <&smps123_reg>;
751 /* Account for Palmas accuracy not < 10mV */ 751 /* Account for Palmas accuracy not < 10mV */
752 voltage-tolerance = <1>; 752 voltage-tolerance = <1>;
753 }; 753 };
754 754
755 &avs_core { 755 &avs_core {
756 avs-supply = <&smps7_reg>; 756 avs-supply = <&smps7_reg>;
757 /* Account for Palmas accuracy not < 10mV */ 757 /* Account for Palmas accuracy not < 10mV */
758 voltage-tolerance = <1>; 758 voltage-tolerance = <1>;
759 }; 759 };
760 760
761 &avs_gpu { 761 &avs_gpu {
762 avs-supply = <&smps6_reg>; 762 avs-supply = <&smps6_reg>;
763 /* Account for Palmas accuracy not < 10mV */ 763 /* Account for Palmas accuracy not < 10mV */
764 voltage-tolerance = <1>; 764 voltage-tolerance = <1>;
765 }; 765 };
766 766
767 &avs_dspeve { 767 &avs_dspeve {
768 avs-supply = <&smps45_reg>; 768 avs-supply = <&smps45_reg>;
769 /* Account for Palmas accuracy not < 10mV */ 769 /* Account for Palmas accuracy not < 10mV */
770 voltage-tolerance = <1>; 770 voltage-tolerance = <1>;
771 }; 771 };
772 772
773 &avs_iva { 773 &avs_iva {
774 avs-supply = <&smps8_reg>; 774 avs-supply = <&smps8_reg>;
775 /* Account for Palmas accuracy not < 10mV */ 775 /* Account for Palmas accuracy not < 10mV */
776 voltage-tolerance = <1>; 776 voltage-tolerance = <1>;
777 }; 777 };
778 778
779 &cpu0 { 779 &cpu0 {
780 cpu0-supply = <&avs_mpu>; 780 cpu0-supply = <&avs_mpu>;
781 }; 781 };
782 782
783 / { 783 / {
784 aliases { 784 aliases {
785 display0 = &tlc59108; 785 display0 = &tlc59108;
786 display1 = &hdmi0; 786 display1 = &hdmi0;
787 }; 787 };
788 788
789 tpd12s015: encoder@0 { 789 tpd12s015: encoder@0 {
790 compatible = "ti,draevm-tpd12s015"; 790 compatible = "ti,draevm-tpd12s015";
791 791
792 video-source = <&hdmi>; 792 video-source = <&hdmi>;
793 793
794 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */ 794 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
795 <&pcf_hdmi 5 0>, /* P5, LS OE */ 795 <&pcf_hdmi 5 0>, /* P5, LS OE */
796 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */ 796 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
797 }; 797 };
798 798
799 hdmi0: connector@0 { 799 hdmi0: connector@0 {
800 compatible = "ti,hdmi_connector"; 800 compatible = "ti,hdmi_connector";
801 801
802 video-source = <&tpd12s015>; 802 video-source = <&tpd12s015>;
803 }; 803 };
804 }; 804 };
805 805
806 &mac { 806 &mac {
807 status = "okay"; 807 status = "okay";
808 pinctrl-names = "default", "sleep"; 808 pinctrl-names = "default", "sleep";
809 pinctrl-0 = <&cpsw_default>; 809 pinctrl-0 = <&cpsw_default>;
810 pinctrl-1 = <&cpsw_sleep>; 810 pinctrl-1 = <&cpsw_sleep>;
811 dual_emac; 811 dual_emac;
812 }; 812 };
813 813
814 &cpsw_emac0 { 814 &cpsw_emac0 {
815 phy_id = <&davinci_mdio>, <2>; 815 phy_id = <&davinci_mdio>, <2>;
816 }; 816 };
817 817
818 &cpsw_emac1 { 818 &cpsw_emac1 {
819 phy_id = <&davinci_mdio>, <3>; 819 phy_id = <&davinci_mdio>, <3>;
820 }; 820 };
821 821
822 &davinci_mdio { 822 &davinci_mdio {
823 pinctrl-names = "default", "sleep"; 823 pinctrl-names = "default", "sleep";
824 pinctrl-0 = <&davinci_mdio_default>; 824 pinctrl-0 = <&davinci_mdio_default>;
825 pinctrl-1 = <&davinci_mdio_sleep>; 825 pinctrl-1 = <&davinci_mdio_sleep>;
826 }; 826 };
827 827
828 &elm { 828 &elm {
829 status = "okay"; 829 status = "okay";
830 }; 830 };
831 831
832 &gpmc { 832 &gpmc {
833 status = "okay"; 833 status = "okay";
834 pinctrl-names = "default"; 834 pinctrl-names = "default";
835 pinctrl-0 = <&nand_flash_x16>; 835 pinctrl-0 = <&nand_flash_x16>;
836 ranges = <0 0 0x08000000 0x10000000>; 836 ranges = <0 0 0x08000000 0x10000000>;
837 nand@0,0 { 837 nand@0,0 {
838 reg = <0 0 0>; 838 reg = <0 0 0>;
839 nand-bus-width = <16>; 839 nand-bus-width = <16>;
840 gpmc,device-width = <2>; 840 gpmc,device-width = <2>;
841 gpmc,sync-clk-ps = <0>; 841 gpmc,sync-clk-ps = <0>;
842 gpmc,cs-on-ns = <0>; 842 gpmc,cs-on-ns = <0>;
843 gpmc,cs-rd-off-ns = <40>; 843 gpmc,cs-rd-off-ns = <40>;
844 gpmc,cs-wr-off-ns = <40>; 844 gpmc,cs-wr-off-ns = <40>;
845 gpmc,adv-on-ns = <0>; 845 gpmc,adv-on-ns = <0>;
846 gpmc,adv-rd-off-ns = <30>; 846 gpmc,adv-rd-off-ns = <30>;
847 gpmc,adv-wr-off-ns = <30>; 847 gpmc,adv-wr-off-ns = <30>;
848 gpmc,we-on-ns = <5>; 848 gpmc,we-on-ns = <5>;
849 gpmc,we-off-ns = <25>; 849 gpmc,we-off-ns = <25>;
850 gpmc,oe-on-ns = <2>; 850 gpmc,oe-on-ns = <2>;
851 gpmc,oe-off-ns = <20>; 851 gpmc,oe-off-ns = <20>;
852 gpmc,access-ns = <20>; 852 gpmc,access-ns = <20>;
853 gpmc,wr-access-ns = <40>; 853 gpmc,wr-access-ns = <40>;
854 gpmc,rd-cycle-ns = <40>; 854 gpmc,rd-cycle-ns = <40>;
855 gpmc,wr-cycle-ns = <40>; 855 gpmc,wr-cycle-ns = <40>;
856 gpmc,wait-on-read = "true"; 856 gpmc,wait-on-read = "true";
857 gpmc,wait-on-write = "true"; 857 gpmc,wait-on-write = "true";
858 gpmc,bus-turnaround-ns = <0>; 858 gpmc,bus-turnaround-ns = <0>;
859 gpmc,cycle2cycle-delay-ns = <0>; 859 gpmc,cycle2cycle-delay-ns = <0>;
860 gpmc,clk-activation-ns = <0>; 860 gpmc,clk-activation-ns = <0>;
861 gpmc,wait-monitoring-ns = <0>; 861 gpmc,wait-monitoring-ns = <0>;
862 gpmc,wr-data-mux-bus-ns = <0>; 862 gpmc,wr-data-mux-bus-ns = <0>;
863 ti,nand-ecc-opt = "bch8"; 863 ti,nand-ecc-opt = "bch8";
864 ti,elm-id = <&elm>; 864 ti,elm-id = <&elm>;
865 /* MTD partition table */ 865 /* MTD partition table */
866 /* All SPL-* partitions are sized to minimal length 866 /* All SPL-* partitions are sized to minimal length
867 * which can be independently programmable. For 867 * which can be independently programmable. For
868 * NAND flash this is equal to size of erase-block */ 868 * NAND flash this is equal to size of erase-block */
869 #address-cells = <1>; 869 #address-cells = <1>;
870 #size-cells = <1>; 870 #size-cells = <1>;
871 partition@0 { 871 partition@0 {
872 label = "NAND.SPL"; 872 label = "NAND.SPL";
873 reg = <0x00000000 0x000020000>; 873 reg = <0x00000000 0x000020000>;
874 }; 874 };
875 partition@1 { 875 partition@1 {
876 label = "NAND.SPL.backup1"; 876 label = "NAND.SPL.backup1";
877 reg = <0x00020000 0x00020000>; 877 reg = <0x00020000 0x00020000>;
878 }; 878 };
879 partition@2 { 879 partition@2 {
880 label = "NAND.SPL.backup2"; 880 label = "NAND.SPL.backup2";
881 reg = <0x00040000 0x00020000>; 881 reg = <0x00040000 0x00020000>;
882 }; 882 };
883 partition@3 { 883 partition@3 {
884 label = "NAND.SPL.backup3"; 884 label = "NAND.SPL.backup3";
885 reg = <0x00060000 0x00020000>; 885 reg = <0x00060000 0x00020000>;
886 }; 886 };
887 partition@4 { 887 partition@4 {
888 label = "NAND.u-boot-spl-os"; 888 label = "NAND.u-boot-spl-os";
889 reg = <0x00080000 0x00040000>; 889 reg = <0x00080000 0x00040000>;
890 }; 890 };
891 partition@5 { 891 partition@5 {
892 label = "NAND.u-boot"; 892 label = "NAND.u-boot";
893 reg = <0x000C0000 0x00100000>; 893 reg = <0x000C0000 0x00100000>;
894 }; 894 };
895 partition@6 { 895 partition@6 {
896 label = "NAND.u-boot-env"; 896 label = "NAND.u-boot-env";
897 reg = <0x001C0000 0x00020000>; 897 reg = <0x001C0000 0x00020000>;
898 }; 898 };
899 partition@7 { 899 partition@7 {
900 label = "NAND.u-boot-env.backup1"; 900 label = "NAND.u-boot-env.backup1";
901 reg = <0x001E0000 0x00020000>; 901 reg = <0x001E0000 0x00020000>;
902 }; 902 };
903 partition@8 { 903 partition@8 {
904 label = "NAND.kernel"; 904 label = "NAND.kernel";
905 reg = <0x00200000 0x00800000>; 905 reg = <0x00200000 0x00800000>;
906 }; 906 };
907 partition@9 { 907 partition@9 {
908 label = "NAND.file-system"; 908 label = "NAND.file-system";
909 reg = <0x00A00000 0x0F600000>; 909 reg = <0x00A00000 0x0F600000>;
910 }; 910 };
911 }; 911 };
912 }; 912 };
913 913
914 &atl_clkin { 914 &atl_clkin {
915 fck_parent = "dpll_abe_m2_ck"; 915 fck_parent = "dpll_abe_m2_ck";
916 status = "okay"; 916 status = "okay";
917 917
918 atl2 { 918 atl2 {
919 bws = <DRA7_ATL_WS_MCASP2_FSX>; 919 bws = <DRA7_ATL_WS_MCASP2_FSX>;
920 aws = <DRA7_ATL_WS_MCASP3_FSX>; 920 aws = <DRA7_ATL_WS_MCASP3_FSX>;
921 }; 921 };
922 }; 922 };
923 923
924 &mcasp3 { 924 &mcasp3 {
925 pinctrl-names = "default"; 925 pinctrl-names = "default";
926 pinctrl-0 = <&mcasp3_pins>; 926 pinctrl-0 = <&mcasp3_pins>;
927 927
928 fck_parent = "atl_clkin2_ck"; 928 fck_parent = "atl_clkin2_ck";
929 929
930 status = "okay"; 930 status = "okay";
931 931
932 op-mode = <0>; /* MCASP_IIS_MODE */ 932 op-mode = <0>; /* MCASP_IIS_MODE */
933 tdm-slots = <2>; 933 tdm-slots = <2>;
934 /* 16 serializer */ 934 /* 16 serializer */
935 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 935 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
936 1 2 0 0 936 1 2 0 0
937 0 0 0 0 937 0 0 0 0
938 0 0 0 0 938 0 0 0 0
939 0 0 0 0 939 0 0 0 0
940 >; 940 >;
941 }; 941 };
942 942