Eric Lee / smarc-ti-linux-kernel

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Commit 55016b9e6084a85d212dfdc17ee708c67c18507d

Authored by Felipe Balbi
Committed by Greg Kroah-Hartman
1 parent d8325cceb3
Exists in ti-linux-3.14.y and in 2 other branches processor-sdk-linux-01.00.00, smarc-ti-linux-3.14.y

usb: dwc3: gadget: fix set_halt() bug with pending transfers 

[ Upstream commit 7a60855972f0d3c014093046cb6f013a1ee5bb19 ]

According to our Gadget Framework API documentation,
->set_halt() *must* return -EAGAIN if we have pending
transfers (on either direction) or FIFO isn't empty (on
TX endpoints).

Fix this bug so that the mass storage gadget can be used
without stall=0 parameter.

This patch should be backported to all kernels since v3.2.

Suggested-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 3 changed files with 15 additions and 7 deletions Inline Diff

drivers/usb/dwc3/ep0.c
Diff comments   View file @ 55016b9
1 /** 1 /**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 * 3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>, 6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 * 8 *
9 * This program is free software: you can redistribute it and/or modify 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of 10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation. 11 * the License as published by the Free Software Foundation.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 */ 17 */
18 18
19 #include <linux/kernel.h> 19 #include <linux/kernel.h>
20 #include <linux/slab.h> 20 #include <linux/slab.h>
21 #include <linux/spinlock.h> 21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h> 22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h> 23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h> 24 #include <linux/interrupt.h>
25 #include <linux/io.h> 25 #include <linux/io.h>
26 #include <linux/list.h> 26 #include <linux/list.h>
27 #include <linux/dma-mapping.h> 27 #include <linux/dma-mapping.h>
28 28
29 #include <linux/usb/ch9.h> 29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h> 30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h> 31 #include <linux/usb/composite.h>
32 32
33 #include "core.h" 33 #include "core.h"
34 #include "gadget.h" 34 #include "gadget.h"
35 #include "io.h" 35 #include "io.h"
36 36
37 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 37 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
38 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 38 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
39 struct dwc3_ep *dep, struct dwc3_request *req); 39 struct dwc3_ep *dep, struct dwc3_request *req);
40 40
41 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 41 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
42 { 42 {
43 switch (state) { 43 switch (state) {
44 case EP0_UNCONNECTED: 44 case EP0_UNCONNECTED:
45 return "Unconnected"; 45 return "Unconnected";
46 case EP0_SETUP_PHASE: 46 case EP0_SETUP_PHASE:
47 return "Setup Phase"; 47 return "Setup Phase";
48 case EP0_DATA_PHASE: 48 case EP0_DATA_PHASE:
49 return "Data Phase"; 49 return "Data Phase";
50 case EP0_STATUS_PHASE: 50 case EP0_STATUS_PHASE:
51 return "Status Phase"; 51 return "Status Phase";
52 default: 52 default:
53 return "UNKNOWN"; 53 return "UNKNOWN";
54 } 54 }
55 } 55 }
56 56
57 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 57 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
58 u32 len, u32 type) 58 u32 len, u32 type)
59 { 59 {
60 struct dwc3_gadget_ep_cmd_params params; 60 struct dwc3_gadget_ep_cmd_params params;
61 struct dwc3_trb *trb; 61 struct dwc3_trb *trb;
62 struct dwc3_ep *dep; 62 struct dwc3_ep *dep;
63 63
64 int ret; 64 int ret;
65 65
66 dep = dwc->eps[epnum]; 66 dep = dwc->eps[epnum];
67 if (dep->flags & DWC3_EP_BUSY) { 67 if (dep->flags & DWC3_EP_BUSY) {
68 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); 68 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
69 return 0; 69 return 0;
70 } 70 }
71 71
72 trb = dwc->ep0_trb; 72 trb = dwc->ep0_trb;
73 73
74 trb->bpl = lower_32_bits(buf_dma); 74 trb->bpl = lower_32_bits(buf_dma);
75 trb->bph = upper_32_bits(buf_dma); 75 trb->bph = upper_32_bits(buf_dma);
76 trb->size = len; 76 trb->size = len;
77 trb->ctrl = type; 77 trb->ctrl = type;
78 78
79 trb->ctrl |= (DWC3_TRB_CTRL_HWO 79 trb->ctrl |= (DWC3_TRB_CTRL_HWO
80 | DWC3_TRB_CTRL_LST 80 | DWC3_TRB_CTRL_LST
81 | DWC3_TRB_CTRL_IOC 81 | DWC3_TRB_CTRL_IOC
82 | DWC3_TRB_CTRL_ISP_IMI); 82 | DWC3_TRB_CTRL_ISP_IMI);
83 83
84 memset(&params, 0, sizeof(params)); 84 memset(&params, 0, sizeof(params));
85 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 85 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
86 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 86 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
87 87
88 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 88 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
89 DWC3_DEPCMD_STARTTRANSFER, &params); 89 DWC3_DEPCMD_STARTTRANSFER, &params);
90 if (ret < 0) { 90 if (ret < 0) {
91 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 91 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
92 return ret; 92 return ret;
93 } 93 }
94 94
95 dep->flags |= DWC3_EP_BUSY; 95 dep->flags |= DWC3_EP_BUSY;
96 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 96 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
97 dep->number); 97 dep->number);
98 98
99 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 99 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
100 100
101 return 0; 101 return 0;
102 } 102 }
103 103
104 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 104 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
105 struct dwc3_request *req) 105 struct dwc3_request *req)
106 { 106 {
107 struct dwc3 *dwc = dep->dwc; 107 struct dwc3 *dwc = dep->dwc;
108 108
109 req->request.actual = 0; 109 req->request.actual = 0;
110 req->request.status = -EINPROGRESS; 110 req->request.status = -EINPROGRESS;
111 req->epnum = dep->number; 111 req->epnum = dep->number;
112 112
113 list_add_tail(&req->list, &dep->request_list); 113 list_add_tail(&req->list, &dep->request_list);
114 114
115 /* 115 /*
116 * Gadget driver might not be quick enough to queue a request 116 * Gadget driver might not be quick enough to queue a request
117 * before we get a Transfer Not Ready event on this endpoint. 117 * before we get a Transfer Not Ready event on this endpoint.
118 * 118 *
119 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 119 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
120 * flag is set, it's telling us that as soon as Gadget queues the 120 * flag is set, it's telling us that as soon as Gadget queues the
121 * required request, we should kick the transfer here because the 121 * required request, we should kick the transfer here because the
122 * IRQ we were waiting for is long gone. 122 * IRQ we were waiting for is long gone.
123 */ 123 */
124 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 124 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
125 unsigned direction; 125 unsigned direction;
126 126
127 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 127 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
128 128
129 if (dwc->ep0state != EP0_DATA_PHASE) { 129 if (dwc->ep0state != EP0_DATA_PHASE) {
130 dev_WARN(dwc->dev, "Unexpected pending request\n"); 130 dev_WARN(dwc->dev, "Unexpected pending request\n");
131 return 0; 131 return 0;
132 } 132 }
133 133
134 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 134 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
135 135
136 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 136 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
137 DWC3_EP0_DIR_IN); 137 DWC3_EP0_DIR_IN);
138 138
139 return 0; 139 return 0;
140 } 140 }
141 141
142 /* 142 /*
143 * In case gadget driver asked us to delay the STATUS phase, 143 * In case gadget driver asked us to delay the STATUS phase,
144 * handle it here. 144 * handle it here.
145 */ 145 */
146 if (dwc->delayed_status) { 146 if (dwc->delayed_status) {
147 unsigned direction; 147 unsigned direction;
148 148
149 direction = !dwc->ep0_expect_in; 149 direction = !dwc->ep0_expect_in;
150 dwc->delayed_status = false; 150 dwc->delayed_status = false;
151 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 151 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
152 152
153 if (dwc->ep0state == EP0_STATUS_PHASE) 153 if (dwc->ep0state == EP0_STATUS_PHASE)
154 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 154 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
155 else 155 else
156 dev_dbg(dwc->dev, "too early for delayed status\n"); 156 dev_dbg(dwc->dev, "too early for delayed status\n");
157 157
158 return 0; 158 return 0;
159 } 159 }
160 160
161 /* 161 /*
162 * Unfortunately we have uncovered a limitation wrt the Data Phase. 162 * Unfortunately we have uncovered a limitation wrt the Data Phase.
163 * 163 *
164 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 164 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
165 * come before issueing Start Transfer command, but if we do, we will 165 * come before issueing Start Transfer command, but if we do, we will
166 * miss situations where the host starts another SETUP phase instead of 166 * miss situations where the host starts another SETUP phase instead of
167 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 167 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
168 * Layer Compliance Suite. 168 * Layer Compliance Suite.
169 * 169 *
170 * The problem surfaces due to the fact that in case of back-to-back 170 * The problem surfaces due to the fact that in case of back-to-back
171 * SETUP packets there will be no XferNotReady(DATA) generated and we 171 * SETUP packets there will be no XferNotReady(DATA) generated and we
172 * will be stuck waiting for XferNotReady(DATA) forever. 172 * will be stuck waiting for XferNotReady(DATA) forever.
173 * 173 *
174 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 174 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
175 * it tells us to start Data Phase right away. It also mentions that if 175 * it tells us to start Data Phase right away. It also mentions that if
176 * we receive a SETUP phase instead of the DATA phase, core will issue 176 * we receive a SETUP phase instead of the DATA phase, core will issue
177 * XferComplete for the DATA phase, before actually initiating it in 177 * XferComplete for the DATA phase, before actually initiating it in
178 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 178 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
179 * can only be used to print some debugging logs, as the core expects 179 * can only be used to print some debugging logs, as the core expects
180 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 180 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
181 * just so it completes right away, without transferring anything and, 181 * just so it completes right away, without transferring anything and,
182 * only then, we can go back to the SETUP phase. 182 * only then, we can go back to the SETUP phase.
183 * 183 *
184 * Because of this scenario, SNPS decided to change the programming 184 * Because of this scenario, SNPS decided to change the programming
185 * model of control transfers and support on-demand transfers only for 185 * model of control transfers and support on-demand transfers only for
186 * the STATUS phase. To fix the issue we have now, we will always wait 186 * the STATUS phase. To fix the issue we have now, we will always wait
187 * for gadget driver to queue the DATA phase's struct usb_request, then 187 * for gadget driver to queue the DATA phase's struct usb_request, then
188 * start it right away. 188 * start it right away.
189 * 189 *
190 * If we're actually in a 2-stage transfer, we will wait for 190 * If we're actually in a 2-stage transfer, we will wait for
191 * XferNotReady(STATUS). 191 * XferNotReady(STATUS).
192 */ 192 */
193 if (dwc->three_stage_setup) { 193 if (dwc->three_stage_setup) {
194 unsigned direction; 194 unsigned direction;
195 195
196 direction = dwc->ep0_expect_in; 196 direction = dwc->ep0_expect_in;
197 dwc->ep0state = EP0_DATA_PHASE; 197 dwc->ep0state = EP0_DATA_PHASE;
198 198
199 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 199 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
200 200
201 dep->flags &= ~DWC3_EP0_DIR_IN; 201 dep->flags &= ~DWC3_EP0_DIR_IN;
202 } 202 }
203 203
204 return 0; 204 return 0;
205 } 205 }
206 206
207 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 207 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
208 gfp_t gfp_flags) 208 gfp_t gfp_flags)
209 { 209 {
210 struct dwc3_request *req = to_dwc3_request(request); 210 struct dwc3_request *req = to_dwc3_request(request);
211 struct dwc3_ep *dep = to_dwc3_ep(ep); 211 struct dwc3_ep *dep = to_dwc3_ep(ep);
212 struct dwc3 *dwc = dep->dwc; 212 struct dwc3 *dwc = dep->dwc;
213 213
214 unsigned long flags; 214 unsigned long flags;
215 215
216 int ret; 216 int ret;
217 217
218 spin_lock_irqsave(&dwc->lock, flags); 218 spin_lock_irqsave(&dwc->lock, flags);
219 if (!dep->endpoint.desc) { 219 if (!dep->endpoint.desc) {
220 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 220 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
221 request, dep->name); 221 request, dep->name);
222 ret = -ESHUTDOWN; 222 ret = -ESHUTDOWN;
223 goto out; 223 goto out;
224 } 224 }
225 225
226 /* we share one TRB for ep0/1 */ 226 /* we share one TRB for ep0/1 */
227 if (!list_empty(&dep->request_list)) { 227 if (!list_empty(&dep->request_list)) {
228 ret = -EBUSY; 228 ret = -EBUSY;
229 goto out; 229 goto out;
230 } 230 }
231 231
232 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", 232 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
233 request, dep->name, request->length, 233 request, dep->name, request->length,
234 dwc3_ep0_state_string(dwc->ep0state)); 234 dwc3_ep0_state_string(dwc->ep0state));
235 235
236 ret = __dwc3_gadget_ep0_queue(dep, req); 236 ret = __dwc3_gadget_ep0_queue(dep, req);
237 237
238 out: 238 out:
239 spin_unlock_irqrestore(&dwc->lock, flags); 239 spin_unlock_irqrestore(&dwc->lock, flags);
240 240
241 return ret; 241 return ret;
242 } 242 }
243 243
244 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 244 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
245 { 245 {
246 struct dwc3_ep *dep; 246 struct dwc3_ep *dep;
247 247
248 /* reinitialize physical ep1 */ 248 /* reinitialize physical ep1 */
249 dep = dwc->eps[1]; 249 dep = dwc->eps[1];
250 dep->flags = DWC3_EP_ENABLED; 250 dep->flags = DWC3_EP_ENABLED;
251 251
252 /* stall is always issued on EP0 */ 252 /* stall is always issued on EP0 */
253 dep = dwc->eps[0]; 253 dep = dwc->eps[0];
254 __dwc3_gadget_ep_set_halt(dep, 1); 254 __dwc3_gadget_ep_set_halt(dep, 1, false);
255 dep->flags = DWC3_EP_ENABLED; 255 dep->flags = DWC3_EP_ENABLED;
256 dwc->delayed_status = false; 256 dwc->delayed_status = false;
257 257
258 if (!list_empty(&dep->request_list)) { 258 if (!list_empty(&dep->request_list)) {
259 struct dwc3_request *req; 259 struct dwc3_request *req;
260 260
261 req = next_request(&dep->request_list); 261 req = next_request(&dep->request_list);
262 dwc3_gadget_giveback(dep, req, -ECONNRESET); 262 dwc3_gadget_giveback(dep, req, -ECONNRESET);
263 } 263 }
264 264
265 dwc->ep0state = EP0_SETUP_PHASE; 265 dwc->ep0state = EP0_SETUP_PHASE;
266 dwc3_ep0_out_start(dwc); 266 dwc3_ep0_out_start(dwc);
267 } 267 }
268 268
269 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 269 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
270 { 270 {
271 struct dwc3_ep *dep = to_dwc3_ep(ep); 271 struct dwc3_ep *dep = to_dwc3_ep(ep);
272 struct dwc3 *dwc = dep->dwc; 272 struct dwc3 *dwc = dep->dwc;
273 273
274 dwc3_ep0_stall_and_restart(dwc); 274 dwc3_ep0_stall_and_restart(dwc);
275 275
276 return 0; 276 return 0;
277 } 277 }
278 278
279 void dwc3_ep0_out_start(struct dwc3 *dwc) 279 void dwc3_ep0_out_start(struct dwc3 *dwc)
280 { 280 {
281 int ret; 281 int ret;
282 282
283 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 283 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
284 DWC3_TRBCTL_CONTROL_SETUP); 284 DWC3_TRBCTL_CONTROL_SETUP);
285 WARN_ON(ret < 0); 285 WARN_ON(ret < 0);
286 } 286 }
287 287
288 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 288 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
289 { 289 {
290 struct dwc3_ep *dep; 290 struct dwc3_ep *dep;
291 u32 windex = le16_to_cpu(wIndex_le); 291 u32 windex = le16_to_cpu(wIndex_le);
292 u32 epnum; 292 u32 epnum;
293 293
294 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 294 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
295 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 295 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
296 epnum |= 1; 296 epnum |= 1;
297 297
298 dep = dwc->eps[epnum]; 298 dep = dwc->eps[epnum];
299 if (dep->flags & DWC3_EP_ENABLED) 299 if (dep->flags & DWC3_EP_ENABLED)
300 return dep; 300 return dep;
301 301
302 return NULL; 302 return NULL;
303 } 303 }
304 304
305 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 305 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
306 { 306 {
307 } 307 }
308 /* 308 /*
309 * ch 9.4.5 309 * ch 9.4.5
310 */ 310 */
311 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 311 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
312 struct usb_ctrlrequest *ctrl) 312 struct usb_ctrlrequest *ctrl)
313 { 313 {
314 struct dwc3_ep *dep; 314 struct dwc3_ep *dep;
315 u32 recip; 315 u32 recip;
316 u32 reg; 316 u32 reg;
317 u16 usb_status = 0; 317 u16 usb_status = 0;
318 __le16 *response_pkt; 318 __le16 *response_pkt;
319 319
320 recip = ctrl->bRequestType & USB_RECIP_MASK; 320 recip = ctrl->bRequestType & USB_RECIP_MASK;
321 switch (recip) { 321 switch (recip) {
322 case USB_RECIP_DEVICE: 322 case USB_RECIP_DEVICE:
323 /* 323 /*
324 * LTM will be set once we know how to set this in HW. 324 * LTM will be set once we know how to set this in HW.
325 */ 325 */
326 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; 326 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
327 327
328 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 328 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
329 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 329 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
330 if (reg & DWC3_DCTL_INITU1ENA) 330 if (reg & DWC3_DCTL_INITU1ENA)
331 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 331 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
332 if (reg & DWC3_DCTL_INITU2ENA) 332 if (reg & DWC3_DCTL_INITU2ENA)
333 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 333 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
334 } 334 }
335 335
336 break; 336 break;
337 337
338 case USB_RECIP_INTERFACE: 338 case USB_RECIP_INTERFACE:
339 /* 339 /*
340 * Function Remote Wake Capable D0 340 * Function Remote Wake Capable D0
341 * Function Remote Wakeup D1 341 * Function Remote Wakeup D1
342 */ 342 */
343 break; 343 break;
344 344
345 case USB_RECIP_ENDPOINT: 345 case USB_RECIP_ENDPOINT:
346 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 346 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
347 if (!dep) 347 if (!dep)
348 return -EINVAL; 348 return -EINVAL;
349 349
350 if (dep->flags & DWC3_EP_STALL) 350 if (dep->flags & DWC3_EP_STALL)
351 usb_status = 1 << USB_ENDPOINT_HALT; 351 usb_status = 1 << USB_ENDPOINT_HALT;
352 break; 352 break;
353 default: 353 default:
354 return -EINVAL; 354 return -EINVAL;
355 } 355 }
356 356
357 response_pkt = (__le16 *) dwc->setup_buf; 357 response_pkt = (__le16 *) dwc->setup_buf;
358 *response_pkt = cpu_to_le16(usb_status); 358 *response_pkt = cpu_to_le16(usb_status);
359 359
360 dep = dwc->eps[0]; 360 dep = dwc->eps[0];
361 dwc->ep0_usb_req.dep = dep; 361 dwc->ep0_usb_req.dep = dep;
362 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 362 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
363 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 363 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
364 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 364 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
365 365
366 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 366 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
367 } 367 }
368 368
369 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 369 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
370 struct usb_ctrlrequest *ctrl, int set) 370 struct usb_ctrlrequest *ctrl, int set)
371 { 371 {
372 struct dwc3_ep *dep; 372 struct dwc3_ep *dep;
373 u32 recip; 373 u32 recip;
374 u32 wValue; 374 u32 wValue;
375 u32 wIndex; 375 u32 wIndex;
376 u32 reg; 376 u32 reg;
377 int ret; 377 int ret;
378 enum usb_device_state state; 378 enum usb_device_state state;
379 379
380 wValue = le16_to_cpu(ctrl->wValue); 380 wValue = le16_to_cpu(ctrl->wValue);
381 wIndex = le16_to_cpu(ctrl->wIndex); 381 wIndex = le16_to_cpu(ctrl->wIndex);
382 recip = ctrl->bRequestType & USB_RECIP_MASK; 382 recip = ctrl->bRequestType & USB_RECIP_MASK;
383 state = dwc->gadget.state; 383 state = dwc->gadget.state;
384 384
385 switch (recip) { 385 switch (recip) {
386 case USB_RECIP_DEVICE: 386 case USB_RECIP_DEVICE:
387 387
388 switch (wValue) { 388 switch (wValue) {
389 case USB_DEVICE_REMOTE_WAKEUP: 389 case USB_DEVICE_REMOTE_WAKEUP:
390 break; 390 break;
391 /* 391 /*
392 * 9.4.1 says only only for SS, in AddressState only for 392 * 9.4.1 says only only for SS, in AddressState only for
393 * default control pipe 393 * default control pipe
394 */ 394 */
395 case USB_DEVICE_U1_ENABLE: 395 case USB_DEVICE_U1_ENABLE:
396 if (state != USB_STATE_CONFIGURED) 396 if (state != USB_STATE_CONFIGURED)
397 return -EINVAL; 397 return -EINVAL;
398 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 398 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
399 return -EINVAL; 399 return -EINVAL;
400 400
401 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 401 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
402 if (set) 402 if (set)
403 reg |= DWC3_DCTL_INITU1ENA; 403 reg |= DWC3_DCTL_INITU1ENA;
404 else 404 else
405 reg &= ~DWC3_DCTL_INITU1ENA; 405 reg &= ~DWC3_DCTL_INITU1ENA;
406 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 406 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
407 break; 407 break;
408 408
409 case USB_DEVICE_U2_ENABLE: 409 case USB_DEVICE_U2_ENABLE:
410 if (state != USB_STATE_CONFIGURED) 410 if (state != USB_STATE_CONFIGURED)
411 return -EINVAL; 411 return -EINVAL;
412 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 412 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
413 return -EINVAL; 413 return -EINVAL;
414 414
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
416 if (set) 416 if (set)
417 reg |= DWC3_DCTL_INITU2ENA; 417 reg |= DWC3_DCTL_INITU2ENA;
418 else 418 else
419 reg &= ~DWC3_DCTL_INITU2ENA; 419 reg &= ~DWC3_DCTL_INITU2ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
421 break; 421 break;
422 422
423 case USB_DEVICE_LTM_ENABLE: 423 case USB_DEVICE_LTM_ENABLE:
424 return -EINVAL; 424 return -EINVAL;
425 break; 425 break;
426 426
427 case USB_DEVICE_TEST_MODE: 427 case USB_DEVICE_TEST_MODE:
428 if ((wIndex & 0xff) != 0) 428 if ((wIndex & 0xff) != 0)
429 return -EINVAL; 429 return -EINVAL;
430 if (!set) 430 if (!set)
431 return -EINVAL; 431 return -EINVAL;
432 432
433 dwc->test_mode_nr = wIndex >> 8; 433 dwc->test_mode_nr = wIndex >> 8;
434 dwc->test_mode = true; 434 dwc->test_mode = true;
435 break; 435 break;
436 default: 436 default:
437 return -EINVAL; 437 return -EINVAL;
438 } 438 }
439 break; 439 break;
440 440
441 case USB_RECIP_INTERFACE: 441 case USB_RECIP_INTERFACE:
442 switch (wValue) { 442 switch (wValue) {
443 case USB_INTRF_FUNC_SUSPEND: 443 case USB_INTRF_FUNC_SUSPEND:
444 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 444 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
445 /* XXX enable Low power suspend */ 445 /* XXX enable Low power suspend */
446 ; 446 ;
447 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 447 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
448 /* XXX enable remote wakeup */ 448 /* XXX enable remote wakeup */
449 ; 449 ;
450 break; 450 break;
451 default: 451 default:
452 return -EINVAL; 452 return -EINVAL;
453 } 453 }
454 break; 454 break;
455 455
456 case USB_RECIP_ENDPOINT: 456 case USB_RECIP_ENDPOINT:
457 switch (wValue) { 457 switch (wValue) {
458 case USB_ENDPOINT_HALT: 458 case USB_ENDPOINT_HALT:
459 dep = dwc3_wIndex_to_dep(dwc, wIndex); 459 dep = dwc3_wIndex_to_dep(dwc, wIndex);
460 if (!dep) 460 if (!dep)
461 return -EINVAL; 461 return -EINVAL;
462 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 462 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
463 break; 463 break;
464 ret = __dwc3_gadget_ep_set_halt(dep, set); 464 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
465 if (ret) 465 if (ret)
466 return -EINVAL; 466 return -EINVAL;
467 break; 467 break;
468 default: 468 default:
469 return -EINVAL; 469 return -EINVAL;
470 } 470 }
471 break; 471 break;
472 472
473 default: 473 default:
474 return -EINVAL; 474 return -EINVAL;
475 } 475 }
476 476
477 return 0; 477 return 0;
478 } 478 }
479 479
480 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 480 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
481 { 481 {
482 enum usb_device_state state = dwc->gadget.state; 482 enum usb_device_state state = dwc->gadget.state;
483 u32 addr; 483 u32 addr;
484 u32 reg; 484 u32 reg;
485 485
486 addr = le16_to_cpu(ctrl->wValue); 486 addr = le16_to_cpu(ctrl->wValue);
487 if (addr > 127) { 487 if (addr > 127) {
488 dev_dbg(dwc->dev, "invalid device address %d\n", addr); 488 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
489 return -EINVAL; 489 return -EINVAL;
490 } 490 }
491 491
492 if (state == USB_STATE_CONFIGURED) { 492 if (state == USB_STATE_CONFIGURED) {
493 dev_dbg(dwc->dev, "trying to set address when configured\n"); 493 dev_dbg(dwc->dev, "trying to set address when configured\n");
494 return -EINVAL; 494 return -EINVAL;
495 } 495 }
496 496
497 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 497 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
498 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 498 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
499 reg |= DWC3_DCFG_DEVADDR(addr); 499 reg |= DWC3_DCFG_DEVADDR(addr);
500 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 500 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
501 501
502 if (addr) 502 if (addr)
503 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 503 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
504 else 504 else
505 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 505 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
506 506
507 return 0; 507 return 0;
508 } 508 }
509 509
510 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 510 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
511 { 511 {
512 int ret; 512 int ret;
513 513
514 spin_unlock(&dwc->lock); 514 spin_unlock(&dwc->lock);
515 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 515 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
516 spin_lock(&dwc->lock); 516 spin_lock(&dwc->lock);
517 return ret; 517 return ret;
518 } 518 }
519 519
520 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 520 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
521 { 521 {
522 enum usb_device_state state = dwc->gadget.state; 522 enum usb_device_state state = dwc->gadget.state;
523 u32 cfg; 523 u32 cfg;
524 int ret; 524 int ret;
525 u32 reg; 525 u32 reg;
526 526
527 dwc->start_config_issued = false; 527 dwc->start_config_issued = false;
528 cfg = le16_to_cpu(ctrl->wValue); 528 cfg = le16_to_cpu(ctrl->wValue);
529 529
530 switch (state) { 530 switch (state) {
531 case USB_STATE_DEFAULT: 531 case USB_STATE_DEFAULT:
532 return -EINVAL; 532 return -EINVAL;
533 break; 533 break;
534 534
535 case USB_STATE_ADDRESS: 535 case USB_STATE_ADDRESS:
536 ret = dwc3_ep0_delegate_req(dwc, ctrl); 536 ret = dwc3_ep0_delegate_req(dwc, ctrl);
537 /* if the cfg matches and the cfg is non zero */ 537 /* if the cfg matches and the cfg is non zero */
538 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 538 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
539 539
540 /* 540 /*
541 * only change state if set_config has already 541 * only change state if set_config has already
542 * been processed. If gadget driver returns 542 * been processed. If gadget driver returns
543 * USB_GADGET_DELAYED_STATUS, we will wait 543 * USB_GADGET_DELAYED_STATUS, we will wait
544 * to change the state on the next usb_ep_queue() 544 * to change the state on the next usb_ep_queue()
545 */ 545 */
546 if (ret == 0) 546 if (ret == 0)
547 usb_gadget_set_state(&dwc->gadget, 547 usb_gadget_set_state(&dwc->gadget,
548 USB_STATE_CONFIGURED); 548 USB_STATE_CONFIGURED);
549 549
550 /* 550 /*
551 * Enable transition to U1/U2 state when 551 * Enable transition to U1/U2 state when
552 * nothing is pending from application. 552 * nothing is pending from application.
553 */ 553 */
554 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 554 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
555 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 555 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
556 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 556 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
557 557
558 dwc->resize_fifos = true; 558 dwc->resize_fifos = true;
559 dev_dbg(dwc->dev, "resize fifos flag SET\n"); 559 dev_dbg(dwc->dev, "resize fifos flag SET\n");
560 } 560 }
561 break; 561 break;
562 562
563 case USB_STATE_CONFIGURED: 563 case USB_STATE_CONFIGURED:
564 ret = dwc3_ep0_delegate_req(dwc, ctrl); 564 ret = dwc3_ep0_delegate_req(dwc, ctrl);
565 if (!cfg && !ret) 565 if (!cfg && !ret)
566 usb_gadget_set_state(&dwc->gadget, 566 usb_gadget_set_state(&dwc->gadget,
567 USB_STATE_ADDRESS); 567 USB_STATE_ADDRESS);
568 break; 568 break;
569 default: 569 default:
570 ret = -EINVAL; 570 ret = -EINVAL;
571 } 571 }
572 return ret; 572 return ret;
573 } 573 }
574 574
575 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 575 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
576 { 576 {
577 struct dwc3_ep *dep = to_dwc3_ep(ep); 577 struct dwc3_ep *dep = to_dwc3_ep(ep);
578 struct dwc3 *dwc = dep->dwc; 578 struct dwc3 *dwc = dep->dwc;
579 579
580 u32 param = 0; 580 u32 param = 0;
581 u32 reg; 581 u32 reg;
582 582
583 struct timing { 583 struct timing {
584 u8 u1sel; 584 u8 u1sel;
585 u8 u1pel; 585 u8 u1pel;
586 u16 u2sel; 586 u16 u2sel;
587 u16 u2pel; 587 u16 u2pel;
588 } __packed timing; 588 } __packed timing;
589 589
590 int ret; 590 int ret;
591 591
592 memcpy(&timing, req->buf, sizeof(timing)); 592 memcpy(&timing, req->buf, sizeof(timing));
593 593
594 dwc->u1sel = timing.u1sel; 594 dwc->u1sel = timing.u1sel;
595 dwc->u1pel = timing.u1pel; 595 dwc->u1pel = timing.u1pel;
596 dwc->u2sel = le16_to_cpu(timing.u2sel); 596 dwc->u2sel = le16_to_cpu(timing.u2sel);
597 dwc->u2pel = le16_to_cpu(timing.u2pel); 597 dwc->u2pel = le16_to_cpu(timing.u2pel);
598 598
599 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 599 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
600 if (reg & DWC3_DCTL_INITU2ENA) 600 if (reg & DWC3_DCTL_INITU2ENA)
601 param = dwc->u2pel; 601 param = dwc->u2pel;
602 if (reg & DWC3_DCTL_INITU1ENA) 602 if (reg & DWC3_DCTL_INITU1ENA)
603 param = dwc->u1pel; 603 param = dwc->u1pel;
604 604
605 /* 605 /*
606 * According to Synopsys Databook, if parameter is 606 * According to Synopsys Databook, if parameter is
607 * greater than 125, a value of zero should be 607 * greater than 125, a value of zero should be
608 * programmed in the register. 608 * programmed in the register.
609 */ 609 */
610 if (param > 125) 610 if (param > 125)
611 param = 0; 611 param = 0;
612 612
613 /* now that we have the time, issue DGCMD Set Sel */ 613 /* now that we have the time, issue DGCMD Set Sel */
614 ret = dwc3_send_gadget_generic_command(dwc, 614 ret = dwc3_send_gadget_generic_command(dwc,
615 DWC3_DGCMD_SET_PERIODIC_PAR, param); 615 DWC3_DGCMD_SET_PERIODIC_PAR, param);
616 WARN_ON(ret < 0); 616 WARN_ON(ret < 0);
617 } 617 }
618 618
619 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 619 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
620 { 620 {
621 struct dwc3_ep *dep; 621 struct dwc3_ep *dep;
622 enum usb_device_state state = dwc->gadget.state; 622 enum usb_device_state state = dwc->gadget.state;
623 u16 wLength; 623 u16 wLength;
624 u16 wValue; 624 u16 wValue;
625 625
626 if (state == USB_STATE_DEFAULT) 626 if (state == USB_STATE_DEFAULT)
627 return -EINVAL; 627 return -EINVAL;
628 628
629 wValue = le16_to_cpu(ctrl->wValue); 629 wValue = le16_to_cpu(ctrl->wValue);
630 wLength = le16_to_cpu(ctrl->wLength); 630 wLength = le16_to_cpu(ctrl->wLength);
631 631
632 if (wLength != 6) { 632 if (wLength != 6) {
633 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 633 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
634 wLength); 634 wLength);
635 return -EINVAL; 635 return -EINVAL;
636 } 636 }
637 637
638 /* 638 /*
639 * To handle Set SEL we need to receive 6 bytes from Host. So let's 639 * To handle Set SEL we need to receive 6 bytes from Host. So let's
640 * queue a usb_request for 6 bytes. 640 * queue a usb_request for 6 bytes.
641 * 641 *
642 * Remember, though, this controller can't handle non-wMaxPacketSize 642 * Remember, though, this controller can't handle non-wMaxPacketSize
643 * aligned transfers on the OUT direction, so we queue a request for 643 * aligned transfers on the OUT direction, so we queue a request for
644 * wMaxPacketSize instead. 644 * wMaxPacketSize instead.
645 */ 645 */
646 dep = dwc->eps[0]; 646 dep = dwc->eps[0];
647 dwc->ep0_usb_req.dep = dep; 647 dwc->ep0_usb_req.dep = dep;
648 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 648 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
649 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 649 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
650 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 650 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
651 651
652 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 652 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
653 } 653 }
654 654
655 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 655 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
656 { 656 {
657 u16 wLength; 657 u16 wLength;
658 u16 wValue; 658 u16 wValue;
659 u16 wIndex; 659 u16 wIndex;
660 660
661 wValue = le16_to_cpu(ctrl->wValue); 661 wValue = le16_to_cpu(ctrl->wValue);
662 wLength = le16_to_cpu(ctrl->wLength); 662 wLength = le16_to_cpu(ctrl->wLength);
663 wIndex = le16_to_cpu(ctrl->wIndex); 663 wIndex = le16_to_cpu(ctrl->wIndex);
664 664
665 if (wIndex || wLength) 665 if (wIndex || wLength)
666 return -EINVAL; 666 return -EINVAL;
667 667
668 /* 668 /*
669 * REVISIT It's unclear from Databook what to do with this 669 * REVISIT It's unclear from Databook what to do with this
670 * value. For now, just cache it. 670 * value. For now, just cache it.
671 */ 671 */
672 dwc->isoch_delay = wValue; 672 dwc->isoch_delay = wValue;
673 673
674 return 0; 674 return 0;
675 } 675 }
676 676
677 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 677 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
678 { 678 {
679 int ret; 679 int ret;
680 680
681 switch (ctrl->bRequest) { 681 switch (ctrl->bRequest) {
682 case USB_REQ_GET_STATUS: 682 case USB_REQ_GET_STATUS:
683 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); 683 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
684 ret = dwc3_ep0_handle_status(dwc, ctrl); 684 ret = dwc3_ep0_handle_status(dwc, ctrl);
685 break; 685 break;
686 case USB_REQ_CLEAR_FEATURE: 686 case USB_REQ_CLEAR_FEATURE:
687 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); 687 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
688 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 688 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
689 break; 689 break;
690 case USB_REQ_SET_FEATURE: 690 case USB_REQ_SET_FEATURE:
691 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); 691 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
692 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 692 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
693 break; 693 break;
694 case USB_REQ_SET_ADDRESS: 694 case USB_REQ_SET_ADDRESS:
695 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); 695 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
696 ret = dwc3_ep0_set_address(dwc, ctrl); 696 ret = dwc3_ep0_set_address(dwc, ctrl);
697 break; 697 break;
698 case USB_REQ_SET_CONFIGURATION: 698 case USB_REQ_SET_CONFIGURATION:
699 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); 699 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
700 ret = dwc3_ep0_set_config(dwc, ctrl); 700 ret = dwc3_ep0_set_config(dwc, ctrl);
701 break; 701 break;
702 case USB_REQ_SET_SEL: 702 case USB_REQ_SET_SEL:
703 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n"); 703 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
704 ret = dwc3_ep0_set_sel(dwc, ctrl); 704 ret = dwc3_ep0_set_sel(dwc, ctrl);
705 break; 705 break;
706 case USB_REQ_SET_ISOCH_DELAY: 706 case USB_REQ_SET_ISOCH_DELAY:
707 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); 707 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
708 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 708 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
709 break; 709 break;
710 default: 710 default:
711 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); 711 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
712 ret = dwc3_ep0_delegate_req(dwc, ctrl); 712 ret = dwc3_ep0_delegate_req(dwc, ctrl);
713 break; 713 break;
714 } 714 }
715 715
716 return ret; 716 return ret;
717 } 717 }
718 718
719 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 719 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
720 const struct dwc3_event_depevt *event) 720 const struct dwc3_event_depevt *event)
721 { 721 {
722 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 722 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
723 int ret = -EINVAL; 723 int ret = -EINVAL;
724 u32 len; 724 u32 len;
725 725
726 if (!dwc->gadget_driver) 726 if (!dwc->gadget_driver)
727 goto out; 727 goto out;
728 728
729 len = le16_to_cpu(ctrl->wLength); 729 len = le16_to_cpu(ctrl->wLength);
730 if (!len) { 730 if (!len) {
731 dwc->three_stage_setup = false; 731 dwc->three_stage_setup = false;
732 dwc->ep0_expect_in = false; 732 dwc->ep0_expect_in = false;
733 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 733 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
734 } else { 734 } else {
735 dwc->three_stage_setup = true; 735 dwc->three_stage_setup = true;
736 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 736 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
737 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 737 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
738 } 738 }
739 739
740 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 740 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
741 ret = dwc3_ep0_std_request(dwc, ctrl); 741 ret = dwc3_ep0_std_request(dwc, ctrl);
742 else 742 else
743 ret = dwc3_ep0_delegate_req(dwc, ctrl); 743 ret = dwc3_ep0_delegate_req(dwc, ctrl);
744 744
745 if (ret == USB_GADGET_DELAYED_STATUS) 745 if (ret == USB_GADGET_DELAYED_STATUS)
746 dwc->delayed_status = true; 746 dwc->delayed_status = true;
747 747
748 out: 748 out:
749 if (ret < 0) 749 if (ret < 0)
750 dwc3_ep0_stall_and_restart(dwc); 750 dwc3_ep0_stall_and_restart(dwc);
751 } 751 }
752 752
753 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 753 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
754 const struct dwc3_event_depevt *event) 754 const struct dwc3_event_depevt *event)
755 { 755 {
756 struct dwc3_request *r = NULL; 756 struct dwc3_request *r = NULL;
757 struct usb_request *ur; 757 struct usb_request *ur;
758 struct dwc3_trb *trb; 758 struct dwc3_trb *trb;
759 struct dwc3_ep *ep0; 759 struct dwc3_ep *ep0;
760 u32 transferred; 760 u32 transferred;
761 u32 status; 761 u32 status;
762 u32 length; 762 u32 length;
763 u8 epnum; 763 u8 epnum;
764 764
765 epnum = event->endpoint_number; 765 epnum = event->endpoint_number;
766 ep0 = dwc->eps[0]; 766 ep0 = dwc->eps[0];
767 767
768 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 768 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
769 769
770 r = next_request(&ep0->request_list); 770 r = next_request(&ep0->request_list);
771 ur = &r->request; 771 ur = &r->request;
772 772
773 trb = dwc->ep0_trb; 773 trb = dwc->ep0_trb;
774 774
775 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 775 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
776 if (status == DWC3_TRBSTS_SETUP_PENDING) { 776 if (status == DWC3_TRBSTS_SETUP_PENDING) {
777 dev_dbg(dwc->dev, "Setup Pending received\n"); 777 dev_dbg(dwc->dev, "Setup Pending received\n");
778 778
779 if (r) 779 if (r)
780 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 780 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
781 781
782 return; 782 return;
783 } 783 }
784 784
785 length = trb->size & DWC3_TRB_SIZE_MASK; 785 length = trb->size & DWC3_TRB_SIZE_MASK;
786 786
787 if (dwc->ep0_bounced) { 787 if (dwc->ep0_bounced) {
788 unsigned transfer_size = ur->length; 788 unsigned transfer_size = ur->length;
789 unsigned maxp = ep0->endpoint.maxpacket; 789 unsigned maxp = ep0->endpoint.maxpacket;
790 790
791 transfer_size += (maxp - (transfer_size % maxp)); 791 transfer_size += (maxp - (transfer_size % maxp));
792 transferred = min_t(u32, ur->length, 792 transferred = min_t(u32, ur->length,
793 transfer_size - length); 793 transfer_size - length);
794 memcpy(ur->buf, dwc->ep0_bounce, transferred); 794 memcpy(ur->buf, dwc->ep0_bounce, transferred);
795 } else { 795 } else {
796 transferred = ur->length - length; 796 transferred = ur->length - length;
797 } 797 }
798 798
799 ur->actual += transferred; 799 ur->actual += transferred;
800 800
801 if ((epnum & 1) && ur->actual < ur->length) { 801 if ((epnum & 1) && ur->actual < ur->length) {
802 /* for some reason we did not get everything out */ 802 /* for some reason we did not get everything out */
803 803
804 dwc3_ep0_stall_and_restart(dwc); 804 dwc3_ep0_stall_and_restart(dwc);
805 } else { 805 } else {
806 /* 806 /*
807 * handle the case where we have to send a zero packet. This 807 * handle the case where we have to send a zero packet. This
808 * seems to be case when req.length > maxpacket. Could it be? 808 * seems to be case when req.length > maxpacket. Could it be?
809 */ 809 */
810 if (r) 810 if (r)
811 dwc3_gadget_giveback(ep0, r, 0); 811 dwc3_gadget_giveback(ep0, r, 0);
812 } 812 }
813 } 813 }
814 814
815 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 815 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
816 const struct dwc3_event_depevt *event) 816 const struct dwc3_event_depevt *event)
817 { 817 {
818 struct dwc3_request *r; 818 struct dwc3_request *r;
819 struct dwc3_ep *dep; 819 struct dwc3_ep *dep;
820 struct dwc3_trb *trb; 820 struct dwc3_trb *trb;
821 u32 status; 821 u32 status;
822 822
823 dep = dwc->eps[0]; 823 dep = dwc->eps[0];
824 trb = dwc->ep0_trb; 824 trb = dwc->ep0_trb;
825 825
826 if (!list_empty(&dep->request_list)) { 826 if (!list_empty(&dep->request_list)) {
827 r = next_request(&dep->request_list); 827 r = next_request(&dep->request_list);
828 828
829 dwc3_gadget_giveback(dep, r, 0); 829 dwc3_gadget_giveback(dep, r, 0);
830 } 830 }
831 831
832 if (dwc->test_mode) { 832 if (dwc->test_mode) {
833 int ret; 833 int ret;
834 834
835 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 835 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
836 if (ret < 0) { 836 if (ret < 0) {
837 dev_dbg(dwc->dev, "Invalid Test #%d\n", 837 dev_dbg(dwc->dev, "Invalid Test #%d\n",
838 dwc->test_mode_nr); 838 dwc->test_mode_nr);
839 dwc3_ep0_stall_and_restart(dwc); 839 dwc3_ep0_stall_and_restart(dwc);
840 return; 840 return;
841 } 841 }
842 } 842 }
843 843
844 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 844 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
845 if (status == DWC3_TRBSTS_SETUP_PENDING) 845 if (status == DWC3_TRBSTS_SETUP_PENDING)
846 dev_dbg(dwc->dev, "Setup Pending received\n"); 846 dev_dbg(dwc->dev, "Setup Pending received\n");
847 847
848 dwc->ep0state = EP0_SETUP_PHASE; 848 dwc->ep0state = EP0_SETUP_PHASE;
849 dwc3_ep0_out_start(dwc); 849 dwc3_ep0_out_start(dwc);
850 } 850 }
851 851
852 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 852 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
853 const struct dwc3_event_depevt *event) 853 const struct dwc3_event_depevt *event)
854 { 854 {
855 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 855 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
856 856
857 dep->flags &= ~DWC3_EP_BUSY; 857 dep->flags &= ~DWC3_EP_BUSY;
858 dep->resource_index = 0; 858 dep->resource_index = 0;
859 dwc->setup_packet_pending = false; 859 dwc->setup_packet_pending = false;
860 860
861 switch (dwc->ep0state) { 861 switch (dwc->ep0state) {
862 case EP0_SETUP_PHASE: 862 case EP0_SETUP_PHASE:
863 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); 863 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
864 dwc3_ep0_inspect_setup(dwc, event); 864 dwc3_ep0_inspect_setup(dwc, event);
865 break; 865 break;
866 866
867 case EP0_DATA_PHASE: 867 case EP0_DATA_PHASE:
868 dev_vdbg(dwc->dev, "Data Phase\n"); 868 dev_vdbg(dwc->dev, "Data Phase\n");
869 dwc3_ep0_complete_data(dwc, event); 869 dwc3_ep0_complete_data(dwc, event);
870 break; 870 break;
871 871
872 case EP0_STATUS_PHASE: 872 case EP0_STATUS_PHASE:
873 dev_vdbg(dwc->dev, "Status Phase\n"); 873 dev_vdbg(dwc->dev, "Status Phase\n");
874 dwc3_ep0_complete_status(dwc, event); 874 dwc3_ep0_complete_status(dwc, event);
875 break; 875 break;
876 default: 876 default:
877 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 877 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
878 } 878 }
879 } 879 }
880 880
881 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 881 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
882 struct dwc3_ep *dep, struct dwc3_request *req) 882 struct dwc3_ep *dep, struct dwc3_request *req)
883 { 883 {
884 int ret; 884 int ret;
885 885
886 req->direction = !!dep->number; 886 req->direction = !!dep->number;
887 887
888 if (req->request.length == 0) { 888 if (req->request.length == 0) {
889 ret = dwc3_ep0_start_trans(dwc, dep->number, 889 ret = dwc3_ep0_start_trans(dwc, dep->number,
890 dwc->ctrl_req_addr, 0, 890 dwc->ctrl_req_addr, 0,
891 DWC3_TRBCTL_CONTROL_DATA); 891 DWC3_TRBCTL_CONTROL_DATA);
892 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 892 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
893 && (dep->number == 0)) { 893 && (dep->number == 0)) {
894 u32 transfer_size; 894 u32 transfer_size;
895 u32 maxpacket; 895 u32 maxpacket;
896 896
897 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 897 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
898 dep->number); 898 dep->number);
899 if (ret) { 899 if (ret) {
900 dev_dbg(dwc->dev, "failed to map request\n"); 900 dev_dbg(dwc->dev, "failed to map request\n");
901 return; 901 return;
902 } 902 }
903 903
904 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); 904 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
905 905
906 maxpacket = dep->endpoint.maxpacket; 906 maxpacket = dep->endpoint.maxpacket;
907 transfer_size = roundup(req->request.length, maxpacket); 907 transfer_size = roundup(req->request.length, maxpacket);
908 908
909 dwc->ep0_bounced = true; 909 dwc->ep0_bounced = true;
910 910
911 /* 911 /*
912 * REVISIT in case request length is bigger than 912 * REVISIT in case request length is bigger than
913 * DWC3_EP0_BOUNCE_SIZE we will need two chained 913 * DWC3_EP0_BOUNCE_SIZE we will need two chained
914 * TRBs to handle the transfer. 914 * TRBs to handle the transfer.
915 */ 915 */
916 ret = dwc3_ep0_start_trans(dwc, dep->number, 916 ret = dwc3_ep0_start_trans(dwc, dep->number,
917 dwc->ep0_bounce_addr, transfer_size, 917 dwc->ep0_bounce_addr, transfer_size,
918 DWC3_TRBCTL_CONTROL_DATA); 918 DWC3_TRBCTL_CONTROL_DATA);
919 } else { 919 } else {
920 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 920 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
921 dep->number); 921 dep->number);
922 if (ret) { 922 if (ret) {
923 dev_dbg(dwc->dev, "failed to map request\n"); 923 dev_dbg(dwc->dev, "failed to map request\n");
924 return; 924 return;
925 } 925 }
926 926
927 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 927 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
928 req->request.length, DWC3_TRBCTL_CONTROL_DATA); 928 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
929 } 929 }
930 930
931 WARN_ON(ret < 0); 931 WARN_ON(ret < 0);
932 } 932 }
933 933
934 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 934 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
935 { 935 {
936 struct dwc3 *dwc = dep->dwc; 936 struct dwc3 *dwc = dep->dwc;
937 u32 type; 937 u32 type;
938 938
939 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 939 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
940 : DWC3_TRBCTL_CONTROL_STATUS2; 940 : DWC3_TRBCTL_CONTROL_STATUS2;
941 941
942 return dwc3_ep0_start_trans(dwc, dep->number, 942 return dwc3_ep0_start_trans(dwc, dep->number,
943 dwc->ctrl_req_addr, 0, type); 943 dwc->ctrl_req_addr, 0, type);
944 } 944 }
945 945
946 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 946 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
947 { 947 {
948 if (dwc->resize_fifos) { 948 if (dwc->resize_fifos) {
949 dev_dbg(dwc->dev, "starting to resize fifos\n"); 949 dev_dbg(dwc->dev, "starting to resize fifos\n");
950 dwc3_gadget_resize_tx_fifos(dwc); 950 dwc3_gadget_resize_tx_fifos(dwc);
951 dwc->resize_fifos = 0; 951 dwc->resize_fifos = 0;
952 } 952 }
953 953
954 WARN_ON(dwc3_ep0_start_control_status(dep)); 954 WARN_ON(dwc3_ep0_start_control_status(dep));
955 } 955 }
956 956
957 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 957 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
958 const struct dwc3_event_depevt *event) 958 const struct dwc3_event_depevt *event)
959 { 959 {
960 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 960 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
961 961
962 __dwc3_ep0_do_control_status(dwc, dep); 962 __dwc3_ep0_do_control_status(dwc, dep);
963 } 963 }
964 964
965 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 965 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
966 { 966 {
967 struct dwc3_gadget_ep_cmd_params params; 967 struct dwc3_gadget_ep_cmd_params params;
968 u32 cmd; 968 u32 cmd;
969 int ret; 969 int ret;
970 970
971 if (!dep->resource_index) 971 if (!dep->resource_index)
972 return; 972 return;
973 973
974 cmd = DWC3_DEPCMD_ENDTRANSFER; 974 cmd = DWC3_DEPCMD_ENDTRANSFER;
975 cmd |= DWC3_DEPCMD_CMDIOC; 975 cmd |= DWC3_DEPCMD_CMDIOC;
976 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 976 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
977 memset(&params, 0, sizeof(params)); 977 memset(&params, 0, sizeof(params));
978 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params); 978 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
979 WARN_ON_ONCE(ret); 979 WARN_ON_ONCE(ret);
980 dep->resource_index = 0; 980 dep->resource_index = 0;
981 } 981 }
982 982
983 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 983 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
984 const struct dwc3_event_depevt *event) 984 const struct dwc3_event_depevt *event)
985 { 985 {
986 dwc->setup_packet_pending = true; 986 dwc->setup_packet_pending = true;
987 987
988 switch (event->status) { 988 switch (event->status) {
989 case DEPEVT_STATUS_CONTROL_DATA: 989 case DEPEVT_STATUS_CONTROL_DATA:
990 dev_vdbg(dwc->dev, "Control Data\n"); 990 dev_vdbg(dwc->dev, "Control Data\n");
991 991
992 /* 992 /*
993 * We already have a DATA transfer in the controller's cache, 993 * We already have a DATA transfer in the controller's cache,
994 * if we receive a XferNotReady(DATA) we will ignore it, unless 994 * if we receive a XferNotReady(DATA) we will ignore it, unless
995 * it's for the wrong direction. 995 * it's for the wrong direction.
996 * 996 *
997 * In that case, we must issue END_TRANSFER command to the Data 997 * In that case, we must issue END_TRANSFER command to the Data
998 * Phase we already have started and issue SetStall on the 998 * Phase we already have started and issue SetStall on the
999 * control endpoint. 999 * control endpoint.
1000 */ 1000 */
1001 if (dwc->ep0_expect_in != event->endpoint_number) { 1001 if (dwc->ep0_expect_in != event->endpoint_number) {
1002 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1002 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1003 1003
1004 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); 1004 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
1005 dwc3_ep0_end_control_data(dwc, dep); 1005 dwc3_ep0_end_control_data(dwc, dep);
1006 dwc3_ep0_stall_and_restart(dwc); 1006 dwc3_ep0_stall_and_restart(dwc);
1007 return; 1007 return;
1008 } 1008 }
1009 1009
1010 break; 1010 break;
1011 1011
1012 case DEPEVT_STATUS_CONTROL_STATUS: 1012 case DEPEVT_STATUS_CONTROL_STATUS:
1013 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1013 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1014 return; 1014 return;
1015 1015
1016 dev_vdbg(dwc->dev, "Control Status\n"); 1016 dev_vdbg(dwc->dev, "Control Status\n");
1017 1017
1018 dwc->ep0state = EP0_STATUS_PHASE; 1018 dwc->ep0state = EP0_STATUS_PHASE;
1019 1019
1020 if (dwc->delayed_status) { 1020 if (dwc->delayed_status) {
1021 WARN_ON_ONCE(event->endpoint_number != 1); 1021 WARN_ON_ONCE(event->endpoint_number != 1);
1022 dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); 1022 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
1023 return; 1023 return;
1024 } 1024 }
1025 1025
1026 dwc3_ep0_do_control_status(dwc, event); 1026 dwc3_ep0_do_control_status(dwc, event);
1027 } 1027 }
1028 } 1028 }
1029 1029
1030 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1030 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1031 const struct dwc3_event_depevt *event) 1031 const struct dwc3_event_depevt *event)
1032 { 1032 {
1033 u8 epnum = event->endpoint_number; 1033 u8 epnum = event->endpoint_number;
1034 1034
1035 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", 1035 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1036 dwc3_ep_event_string(event->endpoint_event), 1036 dwc3_ep_event_string(event->endpoint_event),
1037 epnum >> 1, (epnum & 1) ? "in" : "out", 1037 epnum >> 1, (epnum & 1) ? "in" : "out",
1038 dwc3_ep0_state_string(dwc->ep0state)); 1038 dwc3_ep0_state_string(dwc->ep0state));
1039 1039
1040 switch (event->endpoint_event) { 1040 switch (event->endpoint_event) {
1041 case DWC3_DEPEVT_XFERCOMPLETE: 1041 case DWC3_DEPEVT_XFERCOMPLETE:
1042 dwc3_ep0_xfer_complete(dwc, event); 1042 dwc3_ep0_xfer_complete(dwc, event);
1043 break; 1043 break;
1044 1044
1045 case DWC3_DEPEVT_XFERNOTREADY: 1045 case DWC3_DEPEVT_XFERNOTREADY:
1046 dwc3_ep0_xfernotready(dwc, event); 1046 dwc3_ep0_xfernotready(dwc, event);
1047 break; 1047 break;
1048 1048
1049 case DWC3_DEPEVT_XFERINPROGRESS: 1049 case DWC3_DEPEVT_XFERINPROGRESS:
1050 case DWC3_DEPEVT_RXTXFIFOEVT: 1050 case DWC3_DEPEVT_RXTXFIFOEVT:
1051 case DWC3_DEPEVT_STREAMEVT: 1051 case DWC3_DEPEVT_STREAMEVT:
1052 case DWC3_DEPEVT_EPCMDCMPLT: 1052 case DWC3_DEPEVT_EPCMDCMPLT:
1053 break; 1053 break;
1054 } 1054 }
1055 } 1055 }
1056 1056
drivers/usb/dwc3/gadget.c
Diff comments   View file @ 55016b9
1 /** 1 /**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 * 3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>, 6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 * 8 *
9 * This program is free software: you can redistribute it and/or modify 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of 10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation. 11 * the License as published by the Free Software Foundation.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 */ 17 */
18 18
19 #include <linux/kernel.h> 19 #include <linux/kernel.h>
20 #include <linux/delay.h> 20 #include <linux/delay.h>
21 #include <linux/slab.h> 21 #include <linux/slab.h>
22 #include <linux/spinlock.h> 22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h> 23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h> 24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h> 25 #include <linux/interrupt.h>
26 #include <linux/io.h> 26 #include <linux/io.h>
27 #include <linux/list.h> 27 #include <linux/list.h>
28 #include <linux/dma-mapping.h> 28 #include <linux/dma-mapping.h>
29 29
30 #include <linux/usb/ch9.h> 30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h> 31 #include <linux/usb/gadget.h>
32 32
33 #include "core.h" 33 #include "core.h"
34 #include "gadget.h" 34 #include "gadget.h"
35 #include "io.h" 35 #include "io.h"
36 36
37 /** 37 /**
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure 39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
41 * 41 *
42 * Caller should take care of locking. This function will 42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector 43 * return 0 on success or -EINVAL if wrong Test Selector
44 * is passed 44 * is passed
45 */ 45 */
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47 { 47 {
48 u32 reg; 48 u32 reg;
49 49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52 52
53 switch (mode) { 53 switch (mode) {
54 case TEST_J: 54 case TEST_J:
55 case TEST_K: 55 case TEST_K:
56 case TEST_SE0_NAK: 56 case TEST_SE0_NAK:
57 case TEST_PACKET: 57 case TEST_PACKET:
58 case TEST_FORCE_EN: 58 case TEST_FORCE_EN:
59 reg |= mode << 1; 59 reg |= mode << 1;
60 break; 60 break;
61 default: 61 default:
62 return -EINVAL; 62 return -EINVAL;
63 } 63 }
64 64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 66
67 return 0; 67 return 0;
68 } 68 }
69 69
70 /** 70 /**
71 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 71 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
72 * @dwc: pointer to our context structure 72 * @dwc: pointer to our context structure
73 * @state: the state to put link into 73 * @state: the state to put link into
74 * 74 *
75 * Caller should take care of locking. This function will 75 * Caller should take care of locking. This function will
76 * return 0 on success or -ETIMEDOUT. 76 * return 0 on success or -ETIMEDOUT.
77 */ 77 */
78 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 78 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
79 { 79 {
80 int retries = 10000; 80 int retries = 10000;
81 u32 reg; 81 u32 reg;
82 82
83 /* 83 /*
84 * Wait until device controller is ready. Only applies to 1.94a and 84 * Wait until device controller is ready. Only applies to 1.94a and
85 * later RTL. 85 * later RTL.
86 */ 86 */
87 if (dwc->revision >= DWC3_REVISION_194A) { 87 if (dwc->revision >= DWC3_REVISION_194A) {
88 while (--retries) { 88 while (--retries) {
89 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 89 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
90 if (reg & DWC3_DSTS_DCNRD) 90 if (reg & DWC3_DSTS_DCNRD)
91 udelay(5); 91 udelay(5);
92 else 92 else
93 break; 93 break;
94 } 94 }
95 95
96 if (retries <= 0) 96 if (retries <= 0)
97 return -ETIMEDOUT; 97 return -ETIMEDOUT;
98 } 98 }
99 99
100 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 100 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
101 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 101 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
102 102
103 /* set requested state */ 103 /* set requested state */
104 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 104 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
105 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 105 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
106 106
107 /* 107 /*
108 * The following code is racy when called from dwc3_gadget_wakeup, 108 * The following code is racy when called from dwc3_gadget_wakeup,
109 * and is not needed, at least on newer versions 109 * and is not needed, at least on newer versions
110 */ 110 */
111 if (dwc->revision >= DWC3_REVISION_194A) 111 if (dwc->revision >= DWC3_REVISION_194A)
112 return 0; 112 return 0;
113 113
114 /* wait for a change in DSTS */ 114 /* wait for a change in DSTS */
115 retries = 10000; 115 retries = 10000;
116 while (--retries) { 116 while (--retries) {
117 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 117 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
118 118
119 if (DWC3_DSTS_USBLNKST(reg) == state) 119 if (DWC3_DSTS_USBLNKST(reg) == state)
120 return 0; 120 return 0;
121 121
122 udelay(5); 122 udelay(5);
123 } 123 }
124 124
125 dev_vdbg(dwc->dev, "link state change request timed out\n"); 125 dev_vdbg(dwc->dev, "link state change request timed out\n");
126 126
127 return -ETIMEDOUT; 127 return -ETIMEDOUT;
128 } 128 }
129 129
130 /** 130 /**
131 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 131 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
132 * @dwc: pointer to our context structure 132 * @dwc: pointer to our context structure
133 * 133 *
134 * This function will a best effort FIFO allocation in order 134 * This function will a best effort FIFO allocation in order
135 * to improve FIFO usage and throughput, while still allowing 135 * to improve FIFO usage and throughput, while still allowing
136 * us to enable as many endpoints as possible. 136 * us to enable as many endpoints as possible.
137 * 137 *
138 * Keep in mind that this operation will be highly dependent 138 * Keep in mind that this operation will be highly dependent
139 * on the configured size for RAM1 - which contains TxFifo -, 139 * on the configured size for RAM1 - which contains TxFifo -,
140 * the amount of endpoints enabled on coreConsultant tool, and 140 * the amount of endpoints enabled on coreConsultant tool, and
141 * the width of the Master Bus. 141 * the width of the Master Bus.
142 * 142 *
143 * In the ideal world, we would always be able to satisfy the 143 * In the ideal world, we would always be able to satisfy the
144 * following equation: 144 * following equation:
145 * 145 *
146 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 146 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
147 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 147 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
148 * 148 *
149 * Unfortunately, due to many variables that's not always the case. 149 * Unfortunately, due to many variables that's not always the case.
150 */ 150 */
151 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 151 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
152 { 152 {
153 int last_fifo_depth = 0; 153 int last_fifo_depth = 0;
154 int ram1_depth; 154 int ram1_depth;
155 int fifo_size; 155 int fifo_size;
156 int mdwidth; 156 int mdwidth;
157 int num; 157 int num;
158 158
159 if (!dwc->needs_fifo_resize) 159 if (!dwc->needs_fifo_resize)
160 return 0; 160 return 0;
161 161
162 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 162 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
163 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 163 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
164 164
165 /* MDWIDTH is represented in bits, we need it in bytes */ 165 /* MDWIDTH is represented in bits, we need it in bytes */
166 mdwidth >>= 3; 166 mdwidth >>= 3;
167 167
168 /* 168 /*
169 * FIXME For now we will only allocate 1 wMaxPacketSize space 169 * FIXME For now we will only allocate 1 wMaxPacketSize space
170 * for each enabled endpoint, later patches will come to 170 * for each enabled endpoint, later patches will come to
171 * improve this algorithm so that we better use the internal 171 * improve this algorithm so that we better use the internal
172 * FIFO space 172 * FIFO space
173 */ 173 */
174 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 174 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
175 struct dwc3_ep *dep = dwc->eps[num]; 175 struct dwc3_ep *dep = dwc->eps[num];
176 int fifo_number = dep->number >> 1; 176 int fifo_number = dep->number >> 1;
177 int mult = 1; 177 int mult = 1;
178 int tmp; 178 int tmp;
179 179
180 if (!(dep->number & 1)) 180 if (!(dep->number & 1))
181 continue; 181 continue;
182 182
183 if (!(dep->flags & DWC3_EP_ENABLED)) 183 if (!(dep->flags & DWC3_EP_ENABLED))
184 continue; 184 continue;
185 185
186 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 186 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
187 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 187 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
188 mult = 3; 188 mult = 3;
189 189
190 /* 190 /*
191 * REVISIT: the following assumes we will always have enough 191 * REVISIT: the following assumes we will always have enough
192 * space available on the FIFO RAM for all possible use cases. 192 * space available on the FIFO RAM for all possible use cases.
193 * Make sure that's true somehow and change FIFO allocation 193 * Make sure that's true somehow and change FIFO allocation
194 * accordingly. 194 * accordingly.
195 * 195 *
196 * If we have Bulk or Isochronous endpoints, we want 196 * If we have Bulk or Isochronous endpoints, we want
197 * them to be able to be very, very fast. So we're giving 197 * them to be able to be very, very fast. So we're giving
198 * those endpoints a fifo_size which is enough for 3 full 198 * those endpoints a fifo_size which is enough for 3 full
199 * packets 199 * packets
200 */ 200 */
201 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 201 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
202 tmp += mdwidth; 202 tmp += mdwidth;
203 203
204 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 204 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
205 205
206 fifo_size |= (last_fifo_depth << 16); 206 fifo_size |= (last_fifo_depth << 16);
207 207
208 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 208 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
209 dep->name, last_fifo_depth, fifo_size & 0xffff); 209 dep->name, last_fifo_depth, fifo_size & 0xffff);
210 210
211 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 211 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
212 fifo_size); 212 fifo_size);
213 213
214 last_fifo_depth += (fifo_size & 0xffff); 214 last_fifo_depth += (fifo_size & 0xffff);
215 } 215 }
216 216
217 return 0; 217 return 0;
218 } 218 }
219 219
220 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 220 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
221 int status) 221 int status)
222 { 222 {
223 struct dwc3 *dwc = dep->dwc; 223 struct dwc3 *dwc = dep->dwc;
224 int i; 224 int i;
225 225
226 if (req->queued) { 226 if (req->queued) {
227 i = 0; 227 i = 0;
228 do { 228 do {
229 dep->busy_slot++; 229 dep->busy_slot++;
230 /* 230 /*
231 * Skip LINK TRB. We can't use req->trb and check for 231 * Skip LINK TRB. We can't use req->trb and check for
232 * DWC3_TRBCTL_LINK_TRB because it points the TRB we 232 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
233 * just completed (not the LINK TRB). 233 * just completed (not the LINK TRB).
234 */ 234 */
235 if (((dep->busy_slot & DWC3_TRB_MASK) == 235 if (((dep->busy_slot & DWC3_TRB_MASK) ==
236 DWC3_TRB_NUM- 1) && 236 DWC3_TRB_NUM- 1) &&
237 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 237 usb_endpoint_xfer_isoc(dep->endpoint.desc))
238 dep->busy_slot++; 238 dep->busy_slot++;
239 } while(++i < req->request.num_mapped_sgs); 239 } while(++i < req->request.num_mapped_sgs);
240 req->queued = false; 240 req->queued = false;
241 } 241 }
242 list_del(&req->list); 242 list_del(&req->list);
243 req->trb = NULL; 243 req->trb = NULL;
244 244
245 if (req->request.status == -EINPROGRESS) 245 if (req->request.status == -EINPROGRESS)
246 req->request.status = status; 246 req->request.status = status;
247 247
248 if (dwc->ep0_bounced && dep->number == 0) 248 if (dwc->ep0_bounced && dep->number == 0)
249 dwc->ep0_bounced = false; 249 dwc->ep0_bounced = false;
250 else 250 else
251 usb_gadget_unmap_request(&dwc->gadget, &req->request, 251 usb_gadget_unmap_request(&dwc->gadget, &req->request,
252 req->direction); 252 req->direction);
253 253
254 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 254 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
255 req, dep->name, req->request.actual, 255 req, dep->name, req->request.actual,
256 req->request.length, status); 256 req->request.length, status);
257 257
258 spin_unlock(&dwc->lock); 258 spin_unlock(&dwc->lock);
259 req->request.complete(&dep->endpoint, &req->request); 259 req->request.complete(&dep->endpoint, &req->request);
260 spin_lock(&dwc->lock); 260 spin_lock(&dwc->lock);
261 } 261 }
262 262
263 static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 263 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
264 { 264 {
265 switch (cmd) { 265 switch (cmd) {
266 case DWC3_DEPCMD_DEPSTARTCFG: 266 case DWC3_DEPCMD_DEPSTARTCFG:
267 return "Start New Configuration"; 267 return "Start New Configuration";
268 case DWC3_DEPCMD_ENDTRANSFER: 268 case DWC3_DEPCMD_ENDTRANSFER:
269 return "End Transfer"; 269 return "End Transfer";
270 case DWC3_DEPCMD_UPDATETRANSFER: 270 case DWC3_DEPCMD_UPDATETRANSFER:
271 return "Update Transfer"; 271 return "Update Transfer";
272 case DWC3_DEPCMD_STARTTRANSFER: 272 case DWC3_DEPCMD_STARTTRANSFER:
273 return "Start Transfer"; 273 return "Start Transfer";
274 case DWC3_DEPCMD_CLEARSTALL: 274 case DWC3_DEPCMD_CLEARSTALL:
275 return "Clear Stall"; 275 return "Clear Stall";
276 case DWC3_DEPCMD_SETSTALL: 276 case DWC3_DEPCMD_SETSTALL:
277 return "Set Stall"; 277 return "Set Stall";
278 case DWC3_DEPCMD_GETEPSTATE: 278 case DWC3_DEPCMD_GETEPSTATE:
279 return "Get Endpoint State"; 279 return "Get Endpoint State";
280 case DWC3_DEPCMD_SETTRANSFRESOURCE: 280 case DWC3_DEPCMD_SETTRANSFRESOURCE:
281 return "Set Endpoint Transfer Resource"; 281 return "Set Endpoint Transfer Resource";
282 case DWC3_DEPCMD_SETEPCONFIG: 282 case DWC3_DEPCMD_SETEPCONFIG:
283 return "Set Endpoint Configuration"; 283 return "Set Endpoint Configuration";
284 default: 284 default:
285 return "UNKNOWN command"; 285 return "UNKNOWN command";
286 } 286 }
287 } 287 }
288 288
289 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 289 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
290 { 290 {
291 u32 timeout = 500; 291 u32 timeout = 500;
292 u32 reg; 292 u32 reg;
293 293
294 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 294 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
295 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 295 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
296 296
297 do { 297 do {
298 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 298 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
299 if (!(reg & DWC3_DGCMD_CMDACT)) { 299 if (!(reg & DWC3_DGCMD_CMDACT)) {
300 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 300 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
301 DWC3_DGCMD_STATUS(reg)); 301 DWC3_DGCMD_STATUS(reg));
302 return 0; 302 return 0;
303 } 303 }
304 304
305 /* 305 /*
306 * We can't sleep here, because it's also called from 306 * We can't sleep here, because it's also called from
307 * interrupt context. 307 * interrupt context.
308 */ 308 */
309 timeout--; 309 timeout--;
310 if (!timeout) 310 if (!timeout)
311 return -ETIMEDOUT; 311 return -ETIMEDOUT;
312 udelay(1); 312 udelay(1);
313 } while (1); 313 } while (1);
314 } 314 }
315 315
316 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 316 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
317 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 317 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
318 { 318 {
319 struct dwc3_ep *dep = dwc->eps[ep]; 319 struct dwc3_ep *dep = dwc->eps[ep];
320 u32 timeout = 500; 320 u32 timeout = 500;
321 u32 reg; 321 u32 reg;
322 322
323 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 323 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
324 dep->name, 324 dep->name,
325 dwc3_gadget_ep_cmd_string(cmd), params->param0, 325 dwc3_gadget_ep_cmd_string(cmd), params->param0,
326 params->param1, params->param2); 326 params->param1, params->param2);
327 327
328 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 328 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
329 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 329 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
330 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 330 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
331 331
332 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 332 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
333 do { 333 do {
334 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 334 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
335 if (!(reg & DWC3_DEPCMD_CMDACT)) { 335 if (!(reg & DWC3_DEPCMD_CMDACT)) {
336 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 336 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
337 DWC3_DEPCMD_STATUS(reg)); 337 DWC3_DEPCMD_STATUS(reg));
338 return 0; 338 return 0;
339 } 339 }
340 340
341 /* 341 /*
342 * We can't sleep here, because it is also called from 342 * We can't sleep here, because it is also called from
343 * interrupt context. 343 * interrupt context.
344 */ 344 */
345 timeout--; 345 timeout--;
346 if (!timeout) 346 if (!timeout)
347 return -ETIMEDOUT; 347 return -ETIMEDOUT;
348 348
349 udelay(1); 349 udelay(1);
350 } while (1); 350 } while (1);
351 } 351 }
352 352
353 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 353 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
354 struct dwc3_trb *trb) 354 struct dwc3_trb *trb)
355 { 355 {
356 u32 offset = (char *) trb - (char *) dep->trb_pool; 356 u32 offset = (char *) trb - (char *) dep->trb_pool;
357 357
358 return dep->trb_pool_dma + offset; 358 return dep->trb_pool_dma + offset;
359 } 359 }
360 360
361 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 361 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
362 { 362 {
363 struct dwc3 *dwc = dep->dwc; 363 struct dwc3 *dwc = dep->dwc;
364 364
365 if (dep->trb_pool) 365 if (dep->trb_pool)
366 return 0; 366 return 0;
367 367
368 if (dep->number == 0 || dep->number == 1) 368 if (dep->number == 0 || dep->number == 1)
369 return 0; 369 return 0;
370 370
371 dep->trb_pool = dma_alloc_coherent(dwc->dev, 371 dep->trb_pool = dma_alloc_coherent(dwc->dev,
372 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 372 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
373 &dep->trb_pool_dma, GFP_KERNEL); 373 &dep->trb_pool_dma, GFP_KERNEL);
374 if (!dep->trb_pool) { 374 if (!dep->trb_pool) {
375 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 375 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
376 dep->name); 376 dep->name);
377 return -ENOMEM; 377 return -ENOMEM;
378 } 378 }
379 379
380 return 0; 380 return 0;
381 } 381 }
382 382
383 static void dwc3_free_trb_pool(struct dwc3_ep *dep) 383 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
384 { 384 {
385 struct dwc3 *dwc = dep->dwc; 385 struct dwc3 *dwc = dep->dwc;
386 386
387 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 387 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
388 dep->trb_pool, dep->trb_pool_dma); 388 dep->trb_pool, dep->trb_pool_dma);
389 389
390 dep->trb_pool = NULL; 390 dep->trb_pool = NULL;
391 dep->trb_pool_dma = 0; 391 dep->trb_pool_dma = 0;
392 } 392 }
393 393
394 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 394 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
395 { 395 {
396 struct dwc3_gadget_ep_cmd_params params; 396 struct dwc3_gadget_ep_cmd_params params;
397 u32 cmd; 397 u32 cmd;
398 398
399 memset(&params, 0x00, sizeof(params)); 399 memset(&params, 0x00, sizeof(params));
400 400
401 if (dep->number != 1) { 401 if (dep->number != 1) {
402 cmd = DWC3_DEPCMD_DEPSTARTCFG; 402 cmd = DWC3_DEPCMD_DEPSTARTCFG;
403 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 403 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
404 if (dep->number > 1) { 404 if (dep->number > 1) {
405 if (dwc->start_config_issued) 405 if (dwc->start_config_issued)
406 return 0; 406 return 0;
407 dwc->start_config_issued = true; 407 dwc->start_config_issued = true;
408 cmd |= DWC3_DEPCMD_PARAM(2); 408 cmd |= DWC3_DEPCMD_PARAM(2);
409 } 409 }
410 410
411 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params); 411 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
412 } 412 }
413 413
414 return 0; 414 return 0;
415 } 415 }
416 416
417 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 417 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
418 const struct usb_endpoint_descriptor *desc, 418 const struct usb_endpoint_descriptor *desc,
419 const struct usb_ss_ep_comp_descriptor *comp_desc, 419 const struct usb_ss_ep_comp_descriptor *comp_desc,
420 bool ignore) 420 bool ignore)
421 { 421 {
422 struct dwc3_gadget_ep_cmd_params params; 422 struct dwc3_gadget_ep_cmd_params params;
423 423
424 memset(&params, 0x00, sizeof(params)); 424 memset(&params, 0x00, sizeof(params));
425 425
426 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 426 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
427 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); 427 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
428 428
429 /* Burst size is only needed in SuperSpeed mode */ 429 /* Burst size is only needed in SuperSpeed mode */
430 if (dwc->gadget.speed == USB_SPEED_SUPER) { 430 if (dwc->gadget.speed == USB_SPEED_SUPER) {
431 u32 burst = dep->endpoint.maxburst - 1; 431 u32 burst = dep->endpoint.maxburst - 1;
432 432
433 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); 433 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
434 } 434 }
435 435
436 if (ignore) 436 if (ignore)
437 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 437 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
438 438
439 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 439 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
440 | DWC3_DEPCFG_XFER_NOT_READY_EN; 440 | DWC3_DEPCFG_XFER_NOT_READY_EN;
441 441
442 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 442 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
443 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 443 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
444 | DWC3_DEPCFG_STREAM_EVENT_EN; 444 | DWC3_DEPCFG_STREAM_EVENT_EN;
445 dep->stream_capable = true; 445 dep->stream_capable = true;
446 } 446 }
447 447
448 if (usb_endpoint_xfer_isoc(desc)) 448 if (usb_endpoint_xfer_isoc(desc))
449 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 449 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
450 450
451 /* 451 /*
452 * We are doing 1:1 mapping for endpoints, meaning 452 * We are doing 1:1 mapping for endpoints, meaning
453 * Physical Endpoints 2 maps to Logical Endpoint 2 and 453 * Physical Endpoints 2 maps to Logical Endpoint 2 and
454 * so on. We consider the direction bit as part of the physical 454 * so on. We consider the direction bit as part of the physical
455 * endpoint number. So USB endpoint 0x81 is 0x03. 455 * endpoint number. So USB endpoint 0x81 is 0x03.
456 */ 456 */
457 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 457 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
458 458
459 /* 459 /*
460 * We must use the lower 16 TX FIFOs even though 460 * We must use the lower 16 TX FIFOs even though
461 * HW might have more 461 * HW might have more
462 */ 462 */
463 if (dep->direction) 463 if (dep->direction)
464 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 464 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
465 465
466 if (desc->bInterval) { 466 if (desc->bInterval) {
467 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 467 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
468 dep->interval = 1 << (desc->bInterval - 1); 468 dep->interval = 1 << (desc->bInterval - 1);
469 } 469 }
470 470
471 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 471 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
472 DWC3_DEPCMD_SETEPCONFIG, &params); 472 DWC3_DEPCMD_SETEPCONFIG, &params);
473 } 473 }
474 474
475 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 475 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
476 { 476 {
477 struct dwc3_gadget_ep_cmd_params params; 477 struct dwc3_gadget_ep_cmd_params params;
478 478
479 memset(&params, 0x00, sizeof(params)); 479 memset(&params, 0x00, sizeof(params));
480 480
481 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 481 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
482 482
483 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 483 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
484 DWC3_DEPCMD_SETTRANSFRESOURCE, &params); 484 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
485 } 485 }
486 486
487 /** 487 /**
488 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 488 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
489 * @dep: endpoint to be initialized 489 * @dep: endpoint to be initialized
490 * @desc: USB Endpoint Descriptor 490 * @desc: USB Endpoint Descriptor
491 * 491 *
492 * Caller should take care of locking 492 * Caller should take care of locking
493 */ 493 */
494 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 494 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
495 const struct usb_endpoint_descriptor *desc, 495 const struct usb_endpoint_descriptor *desc,
496 const struct usb_ss_ep_comp_descriptor *comp_desc, 496 const struct usb_ss_ep_comp_descriptor *comp_desc,
497 bool ignore) 497 bool ignore)
498 { 498 {
499 struct dwc3 *dwc = dep->dwc; 499 struct dwc3 *dwc = dep->dwc;
500 u32 reg; 500 u32 reg;
501 int ret = -ENOMEM; 501 int ret = -ENOMEM;
502 502
503 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 503 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
504 504
505 if (!(dep->flags & DWC3_EP_ENABLED)) { 505 if (!(dep->flags & DWC3_EP_ENABLED)) {
506 ret = dwc3_gadget_start_config(dwc, dep); 506 ret = dwc3_gadget_start_config(dwc, dep);
507 if (ret) 507 if (ret)
508 return ret; 508 return ret;
509 } 509 }
510 510
511 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore); 511 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
512 if (ret) 512 if (ret)
513 return ret; 513 return ret;
514 514
515 if (!(dep->flags & DWC3_EP_ENABLED)) { 515 if (!(dep->flags & DWC3_EP_ENABLED)) {
516 struct dwc3_trb *trb_st_hw; 516 struct dwc3_trb *trb_st_hw;
517 struct dwc3_trb *trb_link; 517 struct dwc3_trb *trb_link;
518 518
519 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 519 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
520 if (ret) 520 if (ret)
521 return ret; 521 return ret;
522 522
523 dep->endpoint.desc = desc; 523 dep->endpoint.desc = desc;
524 dep->comp_desc = comp_desc; 524 dep->comp_desc = comp_desc;
525 dep->type = usb_endpoint_type(desc); 525 dep->type = usb_endpoint_type(desc);
526 dep->flags |= DWC3_EP_ENABLED; 526 dep->flags |= DWC3_EP_ENABLED;
527 527
528 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 528 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
529 reg |= DWC3_DALEPENA_EP(dep->number); 529 reg |= DWC3_DALEPENA_EP(dep->number);
530 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 530 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
531 531
532 if (!usb_endpoint_xfer_isoc(desc)) 532 if (!usb_endpoint_xfer_isoc(desc))
533 return 0; 533 return 0;
534 534
535 /* Link TRB for ISOC. The HWO bit is never reset */ 535 /* Link TRB for ISOC. The HWO bit is never reset */
536 trb_st_hw = &dep->trb_pool[0]; 536 trb_st_hw = &dep->trb_pool[0];
537 537
538 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 538 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
539 memset(trb_link, 0, sizeof(*trb_link)); 539 memset(trb_link, 0, sizeof(*trb_link));
540 540
541 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 541 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
542 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 542 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
543 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 543 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
544 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 544 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
545 } 545 }
546 546
547 return 0; 547 return 0;
548 } 548 }
549 549
550 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 550 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
551 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 551 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
552 { 552 {
553 struct dwc3_request *req; 553 struct dwc3_request *req;
554 554
555 if (!list_empty(&dep->req_queued)) { 555 if (!list_empty(&dep->req_queued)) {
556 dwc3_stop_active_transfer(dwc, dep->number); 556 dwc3_stop_active_transfer(dwc, dep->number);
557 557
558 /* - giveback all requests to gadget driver */ 558 /* - giveback all requests to gadget driver */
559 while (!list_empty(&dep->req_queued)) { 559 while (!list_empty(&dep->req_queued)) {
560 req = next_request(&dep->req_queued); 560 req = next_request(&dep->req_queued);
561 561
562 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 562 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
563 } 563 }
564 } 564 }
565 565
566 while (!list_empty(&dep->request_list)) { 566 while (!list_empty(&dep->request_list)) {
567 req = next_request(&dep->request_list); 567 req = next_request(&dep->request_list);
568 568
569 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 569 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
570 } 570 }
571 } 571 }
572 572
573 /** 573 /**
574 * __dwc3_gadget_ep_disable - Disables a HW endpoint 574 * __dwc3_gadget_ep_disable - Disables a HW endpoint
575 * @dep: the endpoint to disable 575 * @dep: the endpoint to disable
576 * 576 *
577 * This function also removes requests which are currently processed ny the 577 * This function also removes requests which are currently processed ny the
578 * hardware and those which are not yet scheduled. 578 * hardware and those which are not yet scheduled.
579 * Caller should take care of locking. 579 * Caller should take care of locking.
580 */ 580 */
581 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 581 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
582 { 582 {
583 struct dwc3 *dwc = dep->dwc; 583 struct dwc3 *dwc = dep->dwc;
584 u32 reg; 584 u32 reg;
585 585
586 dwc3_remove_requests(dwc, dep); 586 dwc3_remove_requests(dwc, dep);
587 587
588 /* make sure HW endpoint isn't stalled */ 588 /* make sure HW endpoint isn't stalled */
589 if (dep->flags & DWC3_EP_STALL) 589 if (dep->flags & DWC3_EP_STALL)
590 __dwc3_gadget_ep_set_halt(dep, 0); 590 __dwc3_gadget_ep_set_halt(dep, 0, false);
591 591
592 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 592 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
593 reg &= ~DWC3_DALEPENA_EP(dep->number); 593 reg &= ~DWC3_DALEPENA_EP(dep->number);
594 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 594 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
595 595
596 dep->stream_capable = false; 596 dep->stream_capable = false;
597 dep->endpoint.desc = NULL; 597 dep->endpoint.desc = NULL;
598 dep->comp_desc = NULL; 598 dep->comp_desc = NULL;
599 dep->type = 0; 599 dep->type = 0;
600 dep->flags = 0; 600 dep->flags = 0;
601 601
602 return 0; 602 return 0;
603 } 603 }
604 604
605 /* -------------------------------------------------------------------------- */ 605 /* -------------------------------------------------------------------------- */
606 606
607 static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 607 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
608 const struct usb_endpoint_descriptor *desc) 608 const struct usb_endpoint_descriptor *desc)
609 { 609 {
610 return -EINVAL; 610 return -EINVAL;
611 } 611 }
612 612
613 static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 613 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
614 { 614 {
615 return -EINVAL; 615 return -EINVAL;
616 } 616 }
617 617
618 /* -------------------------------------------------------------------------- */ 618 /* -------------------------------------------------------------------------- */
619 619
620 static int dwc3_gadget_ep_enable(struct usb_ep *ep, 620 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
621 const struct usb_endpoint_descriptor *desc) 621 const struct usb_endpoint_descriptor *desc)
622 { 622 {
623 struct dwc3_ep *dep; 623 struct dwc3_ep *dep;
624 struct dwc3 *dwc; 624 struct dwc3 *dwc;
625 unsigned long flags; 625 unsigned long flags;
626 int ret; 626 int ret;
627 627
628 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 628 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
629 pr_debug("dwc3: invalid parameters\n"); 629 pr_debug("dwc3: invalid parameters\n");
630 return -EINVAL; 630 return -EINVAL;
631 } 631 }
632 632
633 if (!desc->wMaxPacketSize) { 633 if (!desc->wMaxPacketSize) {
634 pr_debug("dwc3: missing wMaxPacketSize\n"); 634 pr_debug("dwc3: missing wMaxPacketSize\n");
635 return -EINVAL; 635 return -EINVAL;
636 } 636 }
637 637
638 dep = to_dwc3_ep(ep); 638 dep = to_dwc3_ep(ep);
639 dwc = dep->dwc; 639 dwc = dep->dwc;
640 640
641 if (dep->flags & DWC3_EP_ENABLED) { 641 if (dep->flags & DWC3_EP_ENABLED) {
642 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 642 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
643 dep->name); 643 dep->name);
644 return 0; 644 return 0;
645 } 645 }
646 646
647 switch (usb_endpoint_type(desc)) { 647 switch (usb_endpoint_type(desc)) {
648 case USB_ENDPOINT_XFER_CONTROL: 648 case USB_ENDPOINT_XFER_CONTROL:
649 strlcat(dep->name, "-control", sizeof(dep->name)); 649 strlcat(dep->name, "-control", sizeof(dep->name));
650 break; 650 break;
651 case USB_ENDPOINT_XFER_ISOC: 651 case USB_ENDPOINT_XFER_ISOC:
652 strlcat(dep->name, "-isoc", sizeof(dep->name)); 652 strlcat(dep->name, "-isoc", sizeof(dep->name));
653 break; 653 break;
654 case USB_ENDPOINT_XFER_BULK: 654 case USB_ENDPOINT_XFER_BULK:
655 strlcat(dep->name, "-bulk", sizeof(dep->name)); 655 strlcat(dep->name, "-bulk", sizeof(dep->name));
656 break; 656 break;
657 case USB_ENDPOINT_XFER_INT: 657 case USB_ENDPOINT_XFER_INT:
658 strlcat(dep->name, "-int", sizeof(dep->name)); 658 strlcat(dep->name, "-int", sizeof(dep->name));
659 break; 659 break;
660 default: 660 default:
661 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 661 dev_err(dwc->dev, "invalid endpoint transfer type\n");
662 } 662 }
663 663
664 spin_lock_irqsave(&dwc->lock, flags); 664 spin_lock_irqsave(&dwc->lock, flags);
665 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false); 665 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
666 spin_unlock_irqrestore(&dwc->lock, flags); 666 spin_unlock_irqrestore(&dwc->lock, flags);
667 667
668 return ret; 668 return ret;
669 } 669 }
670 670
671 static int dwc3_gadget_ep_disable(struct usb_ep *ep) 671 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
672 { 672 {
673 struct dwc3_ep *dep; 673 struct dwc3_ep *dep;
674 struct dwc3 *dwc; 674 struct dwc3 *dwc;
675 unsigned long flags; 675 unsigned long flags;
676 int ret; 676 int ret;
677 677
678 if (!ep) { 678 if (!ep) {
679 pr_debug("dwc3: invalid parameters\n"); 679 pr_debug("dwc3: invalid parameters\n");
680 return -EINVAL; 680 return -EINVAL;
681 } 681 }
682 682
683 dep = to_dwc3_ep(ep); 683 dep = to_dwc3_ep(ep);
684 dwc = dep->dwc; 684 dwc = dep->dwc;
685 685
686 if (!(dep->flags & DWC3_EP_ENABLED)) { 686 if (!(dep->flags & DWC3_EP_ENABLED)) {
687 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 687 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
688 dep->name); 688 dep->name);
689 return 0; 689 return 0;
690 } 690 }
691 691
692 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 692 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
693 dep->number >> 1, 693 dep->number >> 1,
694 (dep->number & 1) ? "in" : "out"); 694 (dep->number & 1) ? "in" : "out");
695 695
696 spin_lock_irqsave(&dwc->lock, flags); 696 spin_lock_irqsave(&dwc->lock, flags);
697 ret = __dwc3_gadget_ep_disable(dep); 697 ret = __dwc3_gadget_ep_disable(dep);
698 spin_unlock_irqrestore(&dwc->lock, flags); 698 spin_unlock_irqrestore(&dwc->lock, flags);
699 699
700 return ret; 700 return ret;
701 } 701 }
702 702
703 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 703 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
704 gfp_t gfp_flags) 704 gfp_t gfp_flags)
705 { 705 {
706 struct dwc3_request *req; 706 struct dwc3_request *req;
707 struct dwc3_ep *dep = to_dwc3_ep(ep); 707 struct dwc3_ep *dep = to_dwc3_ep(ep);
708 struct dwc3 *dwc = dep->dwc; 708 struct dwc3 *dwc = dep->dwc;
709 709
710 req = kzalloc(sizeof(*req), gfp_flags); 710 req = kzalloc(sizeof(*req), gfp_flags);
711 if (!req) { 711 if (!req) {
712 dev_err(dwc->dev, "not enough memory\n"); 712 dev_err(dwc->dev, "not enough memory\n");
713 return NULL; 713 return NULL;
714 } 714 }
715 715
716 req->epnum = dep->number; 716 req->epnum = dep->number;
717 req->dep = dep; 717 req->dep = dep;
718 718
719 return &req->request; 719 return &req->request;
720 } 720 }
721 721
722 static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 722 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
723 struct usb_request *request) 723 struct usb_request *request)
724 { 724 {
725 struct dwc3_request *req = to_dwc3_request(request); 725 struct dwc3_request *req = to_dwc3_request(request);
726 726
727 kfree(req); 727 kfree(req);
728 } 728 }
729 729
730 /** 730 /**
731 * dwc3_prepare_one_trb - setup one TRB from one request 731 * dwc3_prepare_one_trb - setup one TRB from one request
732 * @dep: endpoint for which this request is prepared 732 * @dep: endpoint for which this request is prepared
733 * @req: dwc3_request pointer 733 * @req: dwc3_request pointer
734 */ 734 */
735 static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 735 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
736 struct dwc3_request *req, dma_addr_t dma, 736 struct dwc3_request *req, dma_addr_t dma,
737 unsigned length, unsigned last, unsigned chain, unsigned node) 737 unsigned length, unsigned last, unsigned chain, unsigned node)
738 { 738 {
739 struct dwc3 *dwc = dep->dwc; 739 struct dwc3 *dwc = dep->dwc;
740 struct dwc3_trb *trb; 740 struct dwc3_trb *trb;
741 741
742 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 742 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
743 dep->name, req, (unsigned long long) dma, 743 dep->name, req, (unsigned long long) dma,
744 length, last ? " last" : "", 744 length, last ? " last" : "",
745 chain ? " chain" : ""); 745 chain ? " chain" : "");
746 746
747 /* Skip the LINK-TRB on ISOC */ 747 /* Skip the LINK-TRB on ISOC */
748 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 748 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
749 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 749 usb_endpoint_xfer_isoc(dep->endpoint.desc))
750 dep->free_slot++; 750 dep->free_slot++;
751 751
752 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 752 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
753 753
754 if (!req->trb) { 754 if (!req->trb) {
755 dwc3_gadget_move_request_queued(req); 755 dwc3_gadget_move_request_queued(req);
756 req->trb = trb; 756 req->trb = trb;
757 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 757 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
758 req->start_slot = dep->free_slot & DWC3_TRB_MASK; 758 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
759 } 759 }
760 760
761 dep->free_slot++; 761 dep->free_slot++;
762 762
763 trb->size = DWC3_TRB_SIZE_LENGTH(length); 763 trb->size = DWC3_TRB_SIZE_LENGTH(length);
764 trb->bpl = lower_32_bits(dma); 764 trb->bpl = lower_32_bits(dma);
765 trb->bph = upper_32_bits(dma); 765 trb->bph = upper_32_bits(dma);
766 766
767 switch (usb_endpoint_type(dep->endpoint.desc)) { 767 switch (usb_endpoint_type(dep->endpoint.desc)) {
768 case USB_ENDPOINT_XFER_CONTROL: 768 case USB_ENDPOINT_XFER_CONTROL:
769 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 769 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
770 break; 770 break;
771 771
772 case USB_ENDPOINT_XFER_ISOC: 772 case USB_ENDPOINT_XFER_ISOC:
773 if (!node) 773 if (!node)
774 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 774 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
775 else 775 else
776 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; 776 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
777 777
778 if (!req->request.no_interrupt && !chain) 778 if (!req->request.no_interrupt && !chain)
779 trb->ctrl |= DWC3_TRB_CTRL_IOC; 779 trb->ctrl |= DWC3_TRB_CTRL_IOC;
780 break; 780 break;
781 781
782 case USB_ENDPOINT_XFER_BULK: 782 case USB_ENDPOINT_XFER_BULK:
783 case USB_ENDPOINT_XFER_INT: 783 case USB_ENDPOINT_XFER_INT:
784 trb->ctrl = DWC3_TRBCTL_NORMAL; 784 trb->ctrl = DWC3_TRBCTL_NORMAL;
785 break; 785 break;
786 default: 786 default:
787 /* 787 /*
788 * This is only possible with faulty memory because we 788 * This is only possible with faulty memory because we
789 * checked it already :) 789 * checked it already :)
790 */ 790 */
791 BUG(); 791 BUG();
792 } 792 }
793 793
794 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 794 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
795 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 795 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
796 trb->ctrl |= DWC3_TRB_CTRL_CSP; 796 trb->ctrl |= DWC3_TRB_CTRL_CSP;
797 } else if (last) { 797 } else if (last) {
798 trb->ctrl |= DWC3_TRB_CTRL_LST; 798 trb->ctrl |= DWC3_TRB_CTRL_LST;
799 } 799 }
800 800
801 if (chain) 801 if (chain)
802 trb->ctrl |= DWC3_TRB_CTRL_CHN; 802 trb->ctrl |= DWC3_TRB_CTRL_CHN;
803 803
804 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 804 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
805 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 805 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
806 806
807 trb->ctrl |= DWC3_TRB_CTRL_HWO; 807 trb->ctrl |= DWC3_TRB_CTRL_HWO;
808 } 808 }
809 809
810 /* 810 /*
811 * dwc3_prepare_trbs - setup TRBs from requests 811 * dwc3_prepare_trbs - setup TRBs from requests
812 * @dep: endpoint for which requests are being prepared 812 * @dep: endpoint for which requests are being prepared
813 * @starting: true if the endpoint is idle and no requests are queued. 813 * @starting: true if the endpoint is idle and no requests are queued.
814 * 814 *
815 * The function goes through the requests list and sets up TRBs for the 815 * The function goes through the requests list and sets up TRBs for the
816 * transfers. The function returns once there are no more TRBs available or 816 * transfers. The function returns once there are no more TRBs available or
817 * it runs out of requests. 817 * it runs out of requests.
818 */ 818 */
819 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 819 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
820 { 820 {
821 struct dwc3_request *req, *n; 821 struct dwc3_request *req, *n;
822 u32 trbs_left; 822 u32 trbs_left;
823 u32 max; 823 u32 max;
824 unsigned int last_one = 0; 824 unsigned int last_one = 0;
825 825
826 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 826 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
827 827
828 /* the first request must not be queued */ 828 /* the first request must not be queued */
829 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 829 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
830 830
831 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 831 /* Can't wrap around on a non-isoc EP since there's no link TRB */
832 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 832 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
833 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 833 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
834 if (trbs_left > max) 834 if (trbs_left > max)
835 trbs_left = max; 835 trbs_left = max;
836 } 836 }
837 837
838 /* 838 /*
839 * If busy & slot are equal than it is either full or empty. If we are 839 * If busy & slot are equal than it is either full or empty. If we are
840 * starting to process requests then we are empty. Otherwise we are 840 * starting to process requests then we are empty. Otherwise we are
841 * full and don't do anything 841 * full and don't do anything
842 */ 842 */
843 if (!trbs_left) { 843 if (!trbs_left) {
844 if (!starting) 844 if (!starting)
845 return; 845 return;
846 trbs_left = DWC3_TRB_NUM; 846 trbs_left = DWC3_TRB_NUM;
847 /* 847 /*
848 * In case we start from scratch, we queue the ISOC requests 848 * In case we start from scratch, we queue the ISOC requests
849 * starting from slot 1. This is done because we use ring 849 * starting from slot 1. This is done because we use ring
850 * buffer and have no LST bit to stop us. Instead, we place 850 * buffer and have no LST bit to stop us. Instead, we place
851 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 851 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
852 * after the first request so we start at slot 1 and have 852 * after the first request so we start at slot 1 and have
853 * 7 requests proceed before we hit the first IOC. 853 * 7 requests proceed before we hit the first IOC.
854 * Other transfer types don't use the ring buffer and are 854 * Other transfer types don't use the ring buffer and are
855 * processed from the first TRB until the last one. Since we 855 * processed from the first TRB until the last one. Since we
856 * don't wrap around we have to start at the beginning. 856 * don't wrap around we have to start at the beginning.
857 */ 857 */
858 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 858 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
859 dep->busy_slot = 1; 859 dep->busy_slot = 1;
860 dep->free_slot = 1; 860 dep->free_slot = 1;
861 } else { 861 } else {
862 dep->busy_slot = 0; 862 dep->busy_slot = 0;
863 dep->free_slot = 0; 863 dep->free_slot = 0;
864 } 864 }
865 } 865 }
866 866
867 /* The last TRB is a link TRB, not used for xfer */ 867 /* The last TRB is a link TRB, not used for xfer */
868 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 868 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
869 return; 869 return;
870 870
871 list_for_each_entry_safe(req, n, &dep->request_list, list) { 871 list_for_each_entry_safe(req, n, &dep->request_list, list) {
872 unsigned length; 872 unsigned length;
873 dma_addr_t dma; 873 dma_addr_t dma;
874 last_one = false; 874 last_one = false;
875 875
876 if (req->request.num_mapped_sgs > 0) { 876 if (req->request.num_mapped_sgs > 0) {
877 struct usb_request *request = &req->request; 877 struct usb_request *request = &req->request;
878 struct scatterlist *sg = request->sg; 878 struct scatterlist *sg = request->sg;
879 struct scatterlist *s; 879 struct scatterlist *s;
880 int i; 880 int i;
881 881
882 for_each_sg(sg, s, request->num_mapped_sgs, i) { 882 for_each_sg(sg, s, request->num_mapped_sgs, i) {
883 unsigned chain = true; 883 unsigned chain = true;
884 884
885 length = sg_dma_len(s); 885 length = sg_dma_len(s);
886 dma = sg_dma_address(s); 886 dma = sg_dma_address(s);
887 887
888 if (i == (request->num_mapped_sgs - 1) || 888 if (i == (request->num_mapped_sgs - 1) ||
889 sg_is_last(s)) { 889 sg_is_last(s)) {
890 if (list_is_last(&req->list, 890 if (list_is_last(&req->list,
891 &dep->request_list)) 891 &dep->request_list))
892 last_one = true; 892 last_one = true;
893 chain = false; 893 chain = false;
894 } 894 }
895 895
896 trbs_left--; 896 trbs_left--;
897 if (!trbs_left) 897 if (!trbs_left)
898 last_one = true; 898 last_one = true;
899 899
900 if (last_one) 900 if (last_one)
901 chain = false; 901 chain = false;
902 902
903 dwc3_prepare_one_trb(dep, req, dma, length, 903 dwc3_prepare_one_trb(dep, req, dma, length,
904 last_one, chain, i); 904 last_one, chain, i);
905 905
906 if (last_one) 906 if (last_one)
907 break; 907 break;
908 } 908 }
909 } else { 909 } else {
910 dma = req->request.dma; 910 dma = req->request.dma;
911 length = req->request.length; 911 length = req->request.length;
912 trbs_left--; 912 trbs_left--;
913 913
914 if (!trbs_left) 914 if (!trbs_left)
915 last_one = 1; 915 last_one = 1;
916 916
917 /* Is this the last request? */ 917 /* Is this the last request? */
918 if (list_is_last(&req->list, &dep->request_list)) 918 if (list_is_last(&req->list, &dep->request_list))
919 last_one = 1; 919 last_one = 1;
920 920
921 dwc3_prepare_one_trb(dep, req, dma, length, 921 dwc3_prepare_one_trb(dep, req, dma, length,
922 last_one, false, 0); 922 last_one, false, 0);
923 923
924 if (last_one) 924 if (last_one)
925 break; 925 break;
926 } 926 }
927 } 927 }
928 } 928 }
929 929
930 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 930 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
931 int start_new) 931 int start_new)
932 { 932 {
933 struct dwc3_gadget_ep_cmd_params params; 933 struct dwc3_gadget_ep_cmd_params params;
934 struct dwc3_request *req; 934 struct dwc3_request *req;
935 struct dwc3 *dwc = dep->dwc; 935 struct dwc3 *dwc = dep->dwc;
936 int ret; 936 int ret;
937 u32 cmd; 937 u32 cmd;
938 938
939 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 939 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
940 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 940 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
941 return -EBUSY; 941 return -EBUSY;
942 } 942 }
943 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 943 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
944 944
945 /* 945 /*
946 * If we are getting here after a short-out-packet we don't enqueue any 946 * If we are getting here after a short-out-packet we don't enqueue any
947 * new requests as we try to set the IOC bit only on the last request. 947 * new requests as we try to set the IOC bit only on the last request.
948 */ 948 */
949 if (start_new) { 949 if (start_new) {
950 if (list_empty(&dep->req_queued)) 950 if (list_empty(&dep->req_queued))
951 dwc3_prepare_trbs(dep, start_new); 951 dwc3_prepare_trbs(dep, start_new);
952 952
953 /* req points to the first request which will be sent */ 953 /* req points to the first request which will be sent */
954 req = next_request(&dep->req_queued); 954 req = next_request(&dep->req_queued);
955 } else { 955 } else {
956 dwc3_prepare_trbs(dep, start_new); 956 dwc3_prepare_trbs(dep, start_new);
957 957
958 /* 958 /*
959 * req points to the first request where HWO changed from 0 to 1 959 * req points to the first request where HWO changed from 0 to 1
960 */ 960 */
961 req = next_request(&dep->req_queued); 961 req = next_request(&dep->req_queued);
962 } 962 }
963 if (!req) { 963 if (!req) {
964 dep->flags |= DWC3_EP_PENDING_REQUEST; 964 dep->flags |= DWC3_EP_PENDING_REQUEST;
965 return 0; 965 return 0;
966 } 966 }
967 967
968 memset(&params, 0, sizeof(params)); 968 memset(&params, 0, sizeof(params));
969 969
970 if (start_new) { 970 if (start_new) {
971 params.param0 = upper_32_bits(req->trb_dma); 971 params.param0 = upper_32_bits(req->trb_dma);
972 params.param1 = lower_32_bits(req->trb_dma); 972 params.param1 = lower_32_bits(req->trb_dma);
973 cmd = DWC3_DEPCMD_STARTTRANSFER; 973 cmd = DWC3_DEPCMD_STARTTRANSFER;
974 } else { 974 } else {
975 cmd = DWC3_DEPCMD_UPDATETRANSFER; 975 cmd = DWC3_DEPCMD_UPDATETRANSFER;
976 } 976 }
977 977
978 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 978 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
979 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params); 979 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
980 if (ret < 0) { 980 if (ret < 0) {
981 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 981 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
982 982
983 /* 983 /*
984 * FIXME we need to iterate over the list of requests 984 * FIXME we need to iterate over the list of requests
985 * here and stop, unmap, free and del each of the linked 985 * here and stop, unmap, free and del each of the linked
986 * requests instead of what we do now. 986 * requests instead of what we do now.
987 */ 987 */
988 usb_gadget_unmap_request(&dwc->gadget, &req->request, 988 usb_gadget_unmap_request(&dwc->gadget, &req->request,
989 req->direction); 989 req->direction);
990 list_del(&req->list); 990 list_del(&req->list);
991 return ret; 991 return ret;
992 } 992 }
993 993
994 dep->flags |= DWC3_EP_BUSY; 994 dep->flags |= DWC3_EP_BUSY;
995 995
996 if (start_new) { 996 if (start_new) {
997 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 997 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
998 dep->number); 998 dep->number);
999 WARN_ON_ONCE(!dep->resource_index); 999 WARN_ON_ONCE(!dep->resource_index);
1000 } 1000 }
1001 1001
1002 return 0; 1002 return 0;
1003 } 1003 }
1004 1004
1005 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1005 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1006 struct dwc3_ep *dep, u32 cur_uf) 1006 struct dwc3_ep *dep, u32 cur_uf)
1007 { 1007 {
1008 u32 uf; 1008 u32 uf;
1009 1009
1010 if (list_empty(&dep->request_list)) { 1010 if (list_empty(&dep->request_list)) {
1011 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1011 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1012 dep->name); 1012 dep->name);
1013 dep->flags |= DWC3_EP_PENDING_REQUEST; 1013 dep->flags |= DWC3_EP_PENDING_REQUEST;
1014 return; 1014 return;
1015 } 1015 }
1016 1016
1017 /* 4 micro frames in the future */ 1017 /* 4 micro frames in the future */
1018 uf = cur_uf + dep->interval * 4; 1018 uf = cur_uf + dep->interval * 4;
1019 1019
1020 __dwc3_gadget_kick_transfer(dep, uf, 1); 1020 __dwc3_gadget_kick_transfer(dep, uf, 1);
1021 } 1021 }
1022 1022
1023 static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1023 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1024 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1024 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1025 { 1025 {
1026 u32 cur_uf, mask; 1026 u32 cur_uf, mask;
1027 1027
1028 mask = ~(dep->interval - 1); 1028 mask = ~(dep->interval - 1);
1029 cur_uf = event->parameters & mask; 1029 cur_uf = event->parameters & mask;
1030 1030
1031 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1031 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1032 } 1032 }
1033 1033
1034 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1034 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1035 { 1035 {
1036 struct dwc3 *dwc = dep->dwc; 1036 struct dwc3 *dwc = dep->dwc;
1037 int ret; 1037 int ret;
1038 1038
1039 req->request.actual = 0; 1039 req->request.actual = 0;
1040 req->request.status = -EINPROGRESS; 1040 req->request.status = -EINPROGRESS;
1041 req->direction = dep->direction; 1041 req->direction = dep->direction;
1042 req->epnum = dep->number; 1042 req->epnum = dep->number;
1043 1043
1044 /* 1044 /*
1045 * We only add to our list of requests now and 1045 * We only add to our list of requests now and
1046 * start consuming the list once we get XferNotReady 1046 * start consuming the list once we get XferNotReady
1047 * IRQ. 1047 * IRQ.
1048 * 1048 *
1049 * That way, we avoid doing anything that we don't need 1049 * That way, we avoid doing anything that we don't need
1050 * to do now and defer it until the point we receive a 1050 * to do now and defer it until the point we receive a
1051 * particular token from the Host side. 1051 * particular token from the Host side.
1052 * 1052 *
1053 * This will also avoid Host cancelling URBs due to too 1053 * This will also avoid Host cancelling URBs due to too
1054 * many NAKs. 1054 * many NAKs.
1055 */ 1055 */
1056 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1056 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1057 dep->direction); 1057 dep->direction);
1058 if (ret) 1058 if (ret)
1059 return ret; 1059 return ret;
1060 1060
1061 list_add_tail(&req->list, &dep->request_list); 1061 list_add_tail(&req->list, &dep->request_list);
1062 1062
1063 /* 1063 /*
1064 * There are a few special cases: 1064 * There are a few special cases:
1065 * 1065 *
1066 * 1. XferNotReady with empty list of requests. We need to kick the 1066 * 1. XferNotReady with empty list of requests. We need to kick the
1067 * transfer here in that situation, otherwise we will be NAKing 1067 * transfer here in that situation, otherwise we will be NAKing
1068 * forever. If we get XferNotReady before gadget driver has a 1068 * forever. If we get XferNotReady before gadget driver has a
1069 * chance to queue a request, we will ACK the IRQ but won't be 1069 * chance to queue a request, we will ACK the IRQ but won't be
1070 * able to receive the data until the next request is queued. 1070 * able to receive the data until the next request is queued.
1071 * The following code is handling exactly that. 1071 * The following code is handling exactly that.
1072 * 1072 *
1073 */ 1073 */
1074 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1074 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1075 /* 1075 /*
1076 * If xfernotready is already elapsed and it is a case 1076 * If xfernotready is already elapsed and it is a case
1077 * of isoc transfer, then issue END TRANSFER, so that 1077 * of isoc transfer, then issue END TRANSFER, so that
1078 * you can receive xfernotready again and can have 1078 * you can receive xfernotready again and can have
1079 * notion of current microframe. 1079 * notion of current microframe.
1080 */ 1080 */
1081 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1081 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1082 if (list_empty(&dep->req_queued)) { 1082 if (list_empty(&dep->req_queued)) {
1083 dwc3_stop_active_transfer(dwc, dep->number); 1083 dwc3_stop_active_transfer(dwc, dep->number);
1084 dep->flags = DWC3_EP_ENABLED; 1084 dep->flags = DWC3_EP_ENABLED;
1085 } 1085 }
1086 return 0; 1086 return 0;
1087 } 1087 }
1088 1088
1089 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1089 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1090 if (ret && ret != -EBUSY) 1090 if (ret && ret != -EBUSY)
1091 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1091 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1092 dep->name); 1092 dep->name);
1093 return ret; 1093 return ret;
1094 } 1094 }
1095 1095
1096 /* 1096 /*
1097 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1097 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1098 * kick the transfer here after queuing a request, otherwise the 1098 * kick the transfer here after queuing a request, otherwise the
1099 * core may not see the modified TRB(s). 1099 * core may not see the modified TRB(s).
1100 */ 1100 */
1101 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1101 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1102 (dep->flags & DWC3_EP_BUSY) && 1102 (dep->flags & DWC3_EP_BUSY) &&
1103 !(dep->flags & DWC3_EP_MISSED_ISOC)) { 1103 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1104 WARN_ON_ONCE(!dep->resource_index); 1104 WARN_ON_ONCE(!dep->resource_index);
1105 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1105 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1106 false); 1106 false);
1107 if (ret && ret != -EBUSY) 1107 if (ret && ret != -EBUSY)
1108 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1108 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1109 dep->name); 1109 dep->name);
1110 return ret; 1110 return ret;
1111 } 1111 }
1112 1112
1113 return 0; 1113 return 0;
1114 } 1114 }
1115 1115
1116 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1116 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1117 gfp_t gfp_flags) 1117 gfp_t gfp_flags)
1118 { 1118 {
1119 struct dwc3_request *req = to_dwc3_request(request); 1119 struct dwc3_request *req = to_dwc3_request(request);
1120 struct dwc3_ep *dep = to_dwc3_ep(ep); 1120 struct dwc3_ep *dep = to_dwc3_ep(ep);
1121 struct dwc3 *dwc = dep->dwc; 1121 struct dwc3 *dwc = dep->dwc;
1122 1122
1123 unsigned long flags; 1123 unsigned long flags;
1124 1124
1125 int ret; 1125 int ret;
1126 1126
1127 if (!dep->endpoint.desc) { 1127 if (!dep->endpoint.desc) {
1128 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1128 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1129 request, ep->name); 1129 request, ep->name);
1130 return -ESHUTDOWN; 1130 return -ESHUTDOWN;
1131 } 1131 }
1132 1132
1133 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1133 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1134 request, ep->name, request->length); 1134 request, ep->name, request->length);
1135 1135
1136 spin_lock_irqsave(&dwc->lock, flags); 1136 spin_lock_irqsave(&dwc->lock, flags);
1137 ret = __dwc3_gadget_ep_queue(dep, req); 1137 ret = __dwc3_gadget_ep_queue(dep, req);
1138 spin_unlock_irqrestore(&dwc->lock, flags); 1138 spin_unlock_irqrestore(&dwc->lock, flags);
1139 1139
1140 return ret; 1140 return ret;
1141 } 1141 }
1142 1142
1143 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1143 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1144 struct usb_request *request) 1144 struct usb_request *request)
1145 { 1145 {
1146 struct dwc3_request *req = to_dwc3_request(request); 1146 struct dwc3_request *req = to_dwc3_request(request);
1147 struct dwc3_request *r = NULL; 1147 struct dwc3_request *r = NULL;
1148 1148
1149 struct dwc3_ep *dep = to_dwc3_ep(ep); 1149 struct dwc3_ep *dep = to_dwc3_ep(ep);
1150 struct dwc3 *dwc = dep->dwc; 1150 struct dwc3 *dwc = dep->dwc;
1151 1151
1152 unsigned long flags; 1152 unsigned long flags;
1153 int ret = 0; 1153 int ret = 0;
1154 1154
1155 spin_lock_irqsave(&dwc->lock, flags); 1155 spin_lock_irqsave(&dwc->lock, flags);
1156 1156
1157 list_for_each_entry(r, &dep->request_list, list) { 1157 list_for_each_entry(r, &dep->request_list, list) {
1158 if (r == req) 1158 if (r == req)
1159 break; 1159 break;
1160 } 1160 }
1161 1161
1162 if (r != req) { 1162 if (r != req) {
1163 list_for_each_entry(r, &dep->req_queued, list) { 1163 list_for_each_entry(r, &dep->req_queued, list) {
1164 if (r == req) 1164 if (r == req)
1165 break; 1165 break;
1166 } 1166 }
1167 if (r == req) { 1167 if (r == req) {
1168 /* wait until it is processed */ 1168 /* wait until it is processed */
1169 dwc3_stop_active_transfer(dwc, dep->number); 1169 dwc3_stop_active_transfer(dwc, dep->number);
1170 goto out1; 1170 goto out1;
1171 } 1171 }
1172 dev_err(dwc->dev, "request %p was not queued to %s\n", 1172 dev_err(dwc->dev, "request %p was not queued to %s\n",
1173 request, ep->name); 1173 request, ep->name);
1174 ret = -EINVAL; 1174 ret = -EINVAL;
1175 goto out0; 1175 goto out0;
1176 } 1176 }
1177 1177
1178 out1: 1178 out1:
1179 /* giveback the request */ 1179 /* giveback the request */
1180 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1180 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1181 1181
1182 out0: 1182 out0:
1183 spin_unlock_irqrestore(&dwc->lock, flags); 1183 spin_unlock_irqrestore(&dwc->lock, flags);
1184 1184
1185 return ret; 1185 return ret;
1186 } 1186 }
1187 1187
1188 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1188 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1189 { 1189 {
1190 struct dwc3_gadget_ep_cmd_params params; 1190 struct dwc3_gadget_ep_cmd_params params;
1191 struct dwc3 *dwc = dep->dwc; 1191 struct dwc3 *dwc = dep->dwc;
1192 int ret; 1192 int ret;
1193 1193
1194 memset(&params, 0x00, sizeof(params)); 1194 memset(&params, 0x00, sizeof(params));
1195 1195
1196 if (value) { 1196 if (value) {
1197 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1198 (!list_empty(&dep->req_queued) ||
1199 !list_empty(&dep->request_list)))) {
1200 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1201 dep->name);
1202 return -EAGAIN;
1203 }
1204
1197 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1205 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1198 DWC3_DEPCMD_SETSTALL, &params); 1206 DWC3_DEPCMD_SETSTALL, &params);
1199 if (ret) 1207 if (ret)
1200 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1208 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1201 value ? "set" : "clear", 1209 value ? "set" : "clear",
1202 dep->name); 1210 dep->name);
1203 else 1211 else
1204 dep->flags |= DWC3_EP_STALL; 1212 dep->flags |= DWC3_EP_STALL;
1205 } else { 1213 } else {
1206 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1214 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1207 DWC3_DEPCMD_CLEARSTALL, &params); 1215 DWC3_DEPCMD_CLEARSTALL, &params);
1208 if (ret) 1216 if (ret)
1209 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1217 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1210 value ? "set" : "clear", 1218 value ? "set" : "clear",
1211 dep->name); 1219 dep->name);
1212 else 1220 else
1213 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); 1221 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1214 } 1222 }
1215 1223
1216 return ret; 1224 return ret;
1217 } 1225 }
1218 1226
1219 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1227 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1220 { 1228 {
1221 struct dwc3_ep *dep = to_dwc3_ep(ep); 1229 struct dwc3_ep *dep = to_dwc3_ep(ep);
1222 struct dwc3 *dwc = dep->dwc; 1230 struct dwc3 *dwc = dep->dwc;
1223 1231
1224 unsigned long flags; 1232 unsigned long flags;
1225 1233
1226 int ret; 1234 int ret;
1227 1235
1228 spin_lock_irqsave(&dwc->lock, flags); 1236 spin_lock_irqsave(&dwc->lock, flags);
1229 1237
1230 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1238 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1231 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1239 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1232 ret = -EINVAL; 1240 ret = -EINVAL;
1233 goto out; 1241 goto out;
1234 } 1242 }
1235 1243
1236 ret = __dwc3_gadget_ep_set_halt(dep, value); 1244 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1237 out: 1245 out:
1238 spin_unlock_irqrestore(&dwc->lock, flags); 1246 spin_unlock_irqrestore(&dwc->lock, flags);
1239 1247
1240 return ret; 1248 return ret;
1241 } 1249 }
1242 1250
1243 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1251 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1244 { 1252 {
1245 struct dwc3_ep *dep = to_dwc3_ep(ep); 1253 struct dwc3_ep *dep = to_dwc3_ep(ep);
1246 struct dwc3 *dwc = dep->dwc; 1254 struct dwc3 *dwc = dep->dwc;
1247 unsigned long flags; 1255 unsigned long flags;
1248 1256
1249 spin_lock_irqsave(&dwc->lock, flags); 1257 spin_lock_irqsave(&dwc->lock, flags);
1250 dep->flags |= DWC3_EP_WEDGE; 1258 dep->flags |= DWC3_EP_WEDGE;
1251 spin_unlock_irqrestore(&dwc->lock, flags); 1259 spin_unlock_irqrestore(&dwc->lock, flags);
1252 1260
1253 if (dep->number == 0 || dep->number == 1) 1261 if (dep->number == 0 || dep->number == 1)
1254 return dwc3_gadget_ep0_set_halt(ep, 1); 1262 return dwc3_gadget_ep0_set_halt(ep, 1);
1255 else 1263 else
1256 return dwc3_gadget_ep_set_halt(ep, 1); 1264 return __dwc3_gadget_ep_set_halt(dep, 1, false);
1257 } 1265 }
1258 1266
1259 /* -------------------------------------------------------------------------- */ 1267 /* -------------------------------------------------------------------------- */
1260 1268
1261 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1269 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1262 .bLength = USB_DT_ENDPOINT_SIZE, 1270 .bLength = USB_DT_ENDPOINT_SIZE,
1263 .bDescriptorType = USB_DT_ENDPOINT, 1271 .bDescriptorType = USB_DT_ENDPOINT,
1264 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1272 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1265 }; 1273 };
1266 1274
1267 static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1275 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1268 .enable = dwc3_gadget_ep0_enable, 1276 .enable = dwc3_gadget_ep0_enable,
1269 .disable = dwc3_gadget_ep0_disable, 1277 .disable = dwc3_gadget_ep0_disable,
1270 .alloc_request = dwc3_gadget_ep_alloc_request, 1278 .alloc_request = dwc3_gadget_ep_alloc_request,
1271 .free_request = dwc3_gadget_ep_free_request, 1279 .free_request = dwc3_gadget_ep_free_request,
1272 .queue = dwc3_gadget_ep0_queue, 1280 .queue = dwc3_gadget_ep0_queue,
1273 .dequeue = dwc3_gadget_ep_dequeue, 1281 .dequeue = dwc3_gadget_ep_dequeue,
1274 .set_halt = dwc3_gadget_ep0_set_halt, 1282 .set_halt = dwc3_gadget_ep0_set_halt,
1275 .set_wedge = dwc3_gadget_ep_set_wedge, 1283 .set_wedge = dwc3_gadget_ep_set_wedge,
1276 }; 1284 };
1277 1285
1278 static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1286 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1279 .enable = dwc3_gadget_ep_enable, 1287 .enable = dwc3_gadget_ep_enable,
1280 .disable = dwc3_gadget_ep_disable, 1288 .disable = dwc3_gadget_ep_disable,
1281 .alloc_request = dwc3_gadget_ep_alloc_request, 1289 .alloc_request = dwc3_gadget_ep_alloc_request,
1282 .free_request = dwc3_gadget_ep_free_request, 1290 .free_request = dwc3_gadget_ep_free_request,
1283 .queue = dwc3_gadget_ep_queue, 1291 .queue = dwc3_gadget_ep_queue,
1284 .dequeue = dwc3_gadget_ep_dequeue, 1292 .dequeue = dwc3_gadget_ep_dequeue,
1285 .set_halt = dwc3_gadget_ep_set_halt, 1293 .set_halt = dwc3_gadget_ep_set_halt,
1286 .set_wedge = dwc3_gadget_ep_set_wedge, 1294 .set_wedge = dwc3_gadget_ep_set_wedge,
1287 }; 1295 };
1288 1296
1289 /* -------------------------------------------------------------------------- */ 1297 /* -------------------------------------------------------------------------- */
1290 1298
1291 static int dwc3_gadget_get_frame(struct usb_gadget *g) 1299 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1292 { 1300 {
1293 struct dwc3 *dwc = gadget_to_dwc(g); 1301 struct dwc3 *dwc = gadget_to_dwc(g);
1294 u32 reg; 1302 u32 reg;
1295 1303
1296 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1304 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1297 return DWC3_DSTS_SOFFN(reg); 1305 return DWC3_DSTS_SOFFN(reg);
1298 } 1306 }
1299 1307
1300 static int dwc3_gadget_wakeup(struct usb_gadget *g) 1308 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1301 { 1309 {
1302 struct dwc3 *dwc = gadget_to_dwc(g); 1310 struct dwc3 *dwc = gadget_to_dwc(g);
1303 1311
1304 unsigned long timeout; 1312 unsigned long timeout;
1305 unsigned long flags; 1313 unsigned long flags;
1306 1314
1307 u32 reg; 1315 u32 reg;
1308 1316
1309 int ret = 0; 1317 int ret = 0;
1310 1318
1311 u8 link_state; 1319 u8 link_state;
1312 u8 speed; 1320 u8 speed;
1313 1321
1314 spin_lock_irqsave(&dwc->lock, flags); 1322 spin_lock_irqsave(&dwc->lock, flags);
1315 1323
1316 /* 1324 /*
1317 * According to the Databook Remote wakeup request should 1325 * According to the Databook Remote wakeup request should
1318 * be issued only when the device is in early suspend state. 1326 * be issued only when the device is in early suspend state.
1319 * 1327 *
1320 * We can check that via USB Link State bits in DSTS register. 1328 * We can check that via USB Link State bits in DSTS register.
1321 */ 1329 */
1322 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1330 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1323 1331
1324 speed = reg & DWC3_DSTS_CONNECTSPD; 1332 speed = reg & DWC3_DSTS_CONNECTSPD;
1325 if (speed == DWC3_DSTS_SUPERSPEED) { 1333 if (speed == DWC3_DSTS_SUPERSPEED) {
1326 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1334 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1327 ret = -EINVAL; 1335 ret = -EINVAL;
1328 goto out; 1336 goto out;
1329 } 1337 }
1330 1338
1331 link_state = DWC3_DSTS_USBLNKST(reg); 1339 link_state = DWC3_DSTS_USBLNKST(reg);
1332 1340
1333 switch (link_state) { 1341 switch (link_state) {
1334 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1342 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1335 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1343 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1336 break; 1344 break;
1337 default: 1345 default:
1338 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1346 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1339 link_state); 1347 link_state);
1340 ret = -EINVAL; 1348 ret = -EINVAL;
1341 goto out; 1349 goto out;
1342 } 1350 }
1343 1351
1344 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1352 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1345 if (ret < 0) { 1353 if (ret < 0) {
1346 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1354 dev_err(dwc->dev, "failed to put link in Recovery\n");
1347 goto out; 1355 goto out;
1348 } 1356 }
1349 1357
1350 /* Recent versions do this automatically */ 1358 /* Recent versions do this automatically */
1351 if (dwc->revision < DWC3_REVISION_194A) { 1359 if (dwc->revision < DWC3_REVISION_194A) {
1352 /* write zeroes to Link Change Request */ 1360 /* write zeroes to Link Change Request */
1353 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1361 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1354 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1362 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1355 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1363 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1356 } 1364 }
1357 1365
1358 /* poll until Link State changes to ON */ 1366 /* poll until Link State changes to ON */
1359 timeout = jiffies + msecs_to_jiffies(100); 1367 timeout = jiffies + msecs_to_jiffies(100);
1360 1368
1361 while (!time_after(jiffies, timeout)) { 1369 while (!time_after(jiffies, timeout)) {
1362 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1370 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1363 1371
1364 /* in HS, means ON */ 1372 /* in HS, means ON */
1365 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1373 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1366 break; 1374 break;
1367 } 1375 }
1368 1376
1369 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1377 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1370 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1378 dev_err(dwc->dev, "failed to send remote wakeup\n");
1371 ret = -EINVAL; 1379 ret = -EINVAL;
1372 } 1380 }
1373 1381
1374 out: 1382 out:
1375 spin_unlock_irqrestore(&dwc->lock, flags); 1383 spin_unlock_irqrestore(&dwc->lock, flags);
1376 1384
1377 return ret; 1385 return ret;
1378 } 1386 }
1379 1387
1380 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1388 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1381 int is_selfpowered) 1389 int is_selfpowered)
1382 { 1390 {
1383 struct dwc3 *dwc = gadget_to_dwc(g); 1391 struct dwc3 *dwc = gadget_to_dwc(g);
1384 unsigned long flags; 1392 unsigned long flags;
1385 1393
1386 spin_lock_irqsave(&dwc->lock, flags); 1394 spin_lock_irqsave(&dwc->lock, flags);
1387 dwc->is_selfpowered = !!is_selfpowered; 1395 dwc->is_selfpowered = !!is_selfpowered;
1388 spin_unlock_irqrestore(&dwc->lock, flags); 1396 spin_unlock_irqrestore(&dwc->lock, flags);
1389 1397
1390 return 0; 1398 return 0;
1391 } 1399 }
1392 1400
1393 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1401 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1394 { 1402 {
1395 u32 reg; 1403 u32 reg;
1396 u32 timeout = 500; 1404 u32 timeout = 500;
1397 1405
1398 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1406 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1399 if (is_on) { 1407 if (is_on) {
1400 if (dwc->revision <= DWC3_REVISION_187A) { 1408 if (dwc->revision <= DWC3_REVISION_187A) {
1401 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1409 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1402 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1410 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1403 } 1411 }
1404 1412
1405 if (dwc->revision >= DWC3_REVISION_194A) 1413 if (dwc->revision >= DWC3_REVISION_194A)
1406 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1414 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1407 reg |= DWC3_DCTL_RUN_STOP; 1415 reg |= DWC3_DCTL_RUN_STOP;
1408 dwc->pullups_connected = true; 1416 dwc->pullups_connected = true;
1409 } else { 1417 } else {
1410 reg &= ~DWC3_DCTL_RUN_STOP; 1418 reg &= ~DWC3_DCTL_RUN_STOP;
1411 dwc->pullups_connected = false; 1419 dwc->pullups_connected = false;
1412 } 1420 }
1413 1421
1414 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1422 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1415 1423
1416 do { 1424 do {
1417 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1425 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1418 if (is_on) { 1426 if (is_on) {
1419 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1427 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1420 break; 1428 break;
1421 } else { 1429 } else {
1422 if (reg & DWC3_DSTS_DEVCTRLHLT) 1430 if (reg & DWC3_DSTS_DEVCTRLHLT)
1423 break; 1431 break;
1424 } 1432 }
1425 timeout--; 1433 timeout--;
1426 if (!timeout) 1434 if (!timeout)
1427 return -ETIMEDOUT; 1435 return -ETIMEDOUT;
1428 udelay(1); 1436 udelay(1);
1429 } while (1); 1437 } while (1);
1430 1438
1431 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1439 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1432 dwc->gadget_driver 1440 dwc->gadget_driver
1433 ? dwc->gadget_driver->function : "no-function", 1441 ? dwc->gadget_driver->function : "no-function",
1434 is_on ? "connect" : "disconnect"); 1442 is_on ? "connect" : "disconnect");
1435 1443
1436 return 0; 1444 return 0;
1437 } 1445 }
1438 1446
1439 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1447 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1440 { 1448 {
1441 struct dwc3 *dwc = gadget_to_dwc(g); 1449 struct dwc3 *dwc = gadget_to_dwc(g);
1442 unsigned long flags; 1450 unsigned long flags;
1443 int ret; 1451 int ret;
1444 1452
1445 is_on = !!is_on; 1453 is_on = !!is_on;
1446 1454
1447 spin_lock_irqsave(&dwc->lock, flags); 1455 spin_lock_irqsave(&dwc->lock, flags);
1448 ret = dwc3_gadget_run_stop(dwc, is_on); 1456 ret = dwc3_gadget_run_stop(dwc, is_on);
1449 spin_unlock_irqrestore(&dwc->lock, flags); 1457 spin_unlock_irqrestore(&dwc->lock, flags);
1450 1458
1451 return ret; 1459 return ret;
1452 } 1460 }
1453 1461
1454 static void dwc3_gadget_enable_irq(struct dwc3 *dwc) 1462 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1455 { 1463 {
1456 u32 reg; 1464 u32 reg;
1457 1465
1458 /* Enable all but Start and End of Frame IRQs */ 1466 /* Enable all but Start and End of Frame IRQs */
1459 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1467 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1460 DWC3_DEVTEN_EVNTOVERFLOWEN | 1468 DWC3_DEVTEN_EVNTOVERFLOWEN |
1461 DWC3_DEVTEN_CMDCMPLTEN | 1469 DWC3_DEVTEN_CMDCMPLTEN |
1462 DWC3_DEVTEN_ERRTICERREN | 1470 DWC3_DEVTEN_ERRTICERREN |
1463 DWC3_DEVTEN_WKUPEVTEN | 1471 DWC3_DEVTEN_WKUPEVTEN |
1464 DWC3_DEVTEN_ULSTCNGEN | 1472 DWC3_DEVTEN_ULSTCNGEN |
1465 DWC3_DEVTEN_CONNECTDONEEN | 1473 DWC3_DEVTEN_CONNECTDONEEN |
1466 DWC3_DEVTEN_USBRSTEN | 1474 DWC3_DEVTEN_USBRSTEN |
1467 DWC3_DEVTEN_DISCONNEVTEN); 1475 DWC3_DEVTEN_DISCONNEVTEN);
1468 1476
1469 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 1477 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1470 } 1478 }
1471 1479
1472 static void dwc3_gadget_disable_irq(struct dwc3 *dwc) 1480 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1473 { 1481 {
1474 /* mask all interrupts */ 1482 /* mask all interrupts */
1475 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 1483 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1476 } 1484 }
1477 1485
1478 static irqreturn_t dwc3_interrupt(int irq, void *_dwc); 1486 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1479 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); 1487 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1480 1488
1481 static int dwc3_gadget_start(struct usb_gadget *g, 1489 static int dwc3_gadget_start(struct usb_gadget *g,
1482 struct usb_gadget_driver *driver) 1490 struct usb_gadget_driver *driver)
1483 { 1491 {
1484 struct dwc3 *dwc = gadget_to_dwc(g); 1492 struct dwc3 *dwc = gadget_to_dwc(g);
1485 struct dwc3_ep *dep; 1493 struct dwc3_ep *dep;
1486 unsigned long flags; 1494 unsigned long flags;
1487 int ret = 0; 1495 int ret = 0;
1488 int irq; 1496 int irq;
1489 u32 reg; 1497 u32 reg;
1490 1498
1491 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1499 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1492 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, 1500 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1493 IRQF_SHARED, "dwc3", dwc); 1501 IRQF_SHARED, "dwc3", dwc);
1494 if (ret) { 1502 if (ret) {
1495 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 1503 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1496 irq, ret); 1504 irq, ret);
1497 goto err0; 1505 goto err0;
1498 } 1506 }
1499 1507
1500 spin_lock_irqsave(&dwc->lock, flags); 1508 spin_lock_irqsave(&dwc->lock, flags);
1501 1509
1502 if (dwc->gadget_driver) { 1510 if (dwc->gadget_driver) {
1503 dev_err(dwc->dev, "%s is already bound to %s\n", 1511 dev_err(dwc->dev, "%s is already bound to %s\n",
1504 dwc->gadget.name, 1512 dwc->gadget.name,
1505 dwc->gadget_driver->driver.name); 1513 dwc->gadget_driver->driver.name);
1506 ret = -EBUSY; 1514 ret = -EBUSY;
1507 goto err1; 1515 goto err1;
1508 } 1516 }
1509 1517
1510 dwc->gadget_driver = driver; 1518 dwc->gadget_driver = driver;
1511 1519
1512 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1520 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1513 reg &= ~(DWC3_DCFG_SPEED_MASK); 1521 reg &= ~(DWC3_DCFG_SPEED_MASK);
1514 1522
1515 /** 1523 /**
1516 * WORKAROUND: DWC3 revision < 2.20a have an issue 1524 * WORKAROUND: DWC3 revision < 2.20a have an issue
1517 * which would cause metastability state on Run/Stop 1525 * which would cause metastability state on Run/Stop
1518 * bit if we try to force the IP to USB2-only mode. 1526 * bit if we try to force the IP to USB2-only mode.
1519 * 1527 *
1520 * Because of that, we cannot configure the IP to any 1528 * Because of that, we cannot configure the IP to any
1521 * speed other than the SuperSpeed 1529 * speed other than the SuperSpeed
1522 * 1530 *
1523 * Refers to: 1531 * Refers to:
1524 * 1532 *
1525 * STAR#9000525659: Clock Domain Crossing on DCTL in 1533 * STAR#9000525659: Clock Domain Crossing on DCTL in
1526 * USB 2.0 Mode 1534 * USB 2.0 Mode
1527 */ 1535 */
1528 if (dwc->revision < DWC3_REVISION_220A) { 1536 if (dwc->revision < DWC3_REVISION_220A) {
1529 reg |= DWC3_DCFG_SUPERSPEED; 1537 reg |= DWC3_DCFG_SUPERSPEED;
1530 } else { 1538 } else {
1531 switch (dwc->maximum_speed) { 1539 switch (dwc->maximum_speed) {
1532 case USB_SPEED_LOW: 1540 case USB_SPEED_LOW:
1533 reg |= DWC3_DSTS_LOWSPEED; 1541 reg |= DWC3_DSTS_LOWSPEED;
1534 break; 1542 break;
1535 case USB_SPEED_FULL: 1543 case USB_SPEED_FULL:
1536 reg |= DWC3_DSTS_FULLSPEED1; 1544 reg |= DWC3_DSTS_FULLSPEED1;
1537 break; 1545 break;
1538 case USB_SPEED_HIGH: 1546 case USB_SPEED_HIGH:
1539 reg |= DWC3_DSTS_HIGHSPEED; 1547 reg |= DWC3_DSTS_HIGHSPEED;
1540 break; 1548 break;
1541 case USB_SPEED_SUPER: /* FALLTHROUGH */ 1549 case USB_SPEED_SUPER: /* FALLTHROUGH */
1542 case USB_SPEED_UNKNOWN: /* FALTHROUGH */ 1550 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1543 default: 1551 default:
1544 reg |= DWC3_DSTS_SUPERSPEED; 1552 reg |= DWC3_DSTS_SUPERSPEED;
1545 } 1553 }
1546 } 1554 }
1547 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1555 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1548 1556
1549 dwc->start_config_issued = false; 1557 dwc->start_config_issued = false;
1550 1558
1551 /* Start with SuperSpeed Default */ 1559 /* Start with SuperSpeed Default */
1552 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1560 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1553 1561
1554 dep = dwc->eps[0]; 1562 dep = dwc->eps[0];
1555 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 1563 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1556 if (ret) { 1564 if (ret) {
1557 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1565 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1558 goto err2; 1566 goto err2;
1559 } 1567 }
1560 1568
1561 dep = dwc->eps[1]; 1569 dep = dwc->eps[1];
1562 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 1570 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1563 if (ret) { 1571 if (ret) {
1564 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1572 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1565 goto err3; 1573 goto err3;
1566 } 1574 }
1567 1575
1568 /* begin to receive SETUP packets */ 1576 /* begin to receive SETUP packets */
1569 dwc->ep0state = EP0_SETUP_PHASE; 1577 dwc->ep0state = EP0_SETUP_PHASE;
1570 dwc3_ep0_out_start(dwc); 1578 dwc3_ep0_out_start(dwc);
1571 1579
1572 dwc3_gadget_enable_irq(dwc); 1580 dwc3_gadget_enable_irq(dwc);
1573 1581
1574 spin_unlock_irqrestore(&dwc->lock, flags); 1582 spin_unlock_irqrestore(&dwc->lock, flags);
1575 1583
1576 return 0; 1584 return 0;
1577 1585
1578 err3: 1586 err3:
1579 __dwc3_gadget_ep_disable(dwc->eps[0]); 1587 __dwc3_gadget_ep_disable(dwc->eps[0]);
1580 1588
1581 err2: 1589 err2:
1582 dwc->gadget_driver = NULL; 1590 dwc->gadget_driver = NULL;
1583 1591
1584 err1: 1592 err1:
1585 spin_unlock_irqrestore(&dwc->lock, flags); 1593 spin_unlock_irqrestore(&dwc->lock, flags);
1586 1594
1587 free_irq(irq, dwc); 1595 free_irq(irq, dwc);
1588 1596
1589 err0: 1597 err0:
1590 return ret; 1598 return ret;
1591 } 1599 }
1592 1600
1593 static int dwc3_gadget_stop(struct usb_gadget *g, 1601 static int dwc3_gadget_stop(struct usb_gadget *g,
1594 struct usb_gadget_driver *driver) 1602 struct usb_gadget_driver *driver)
1595 { 1603 {
1596 struct dwc3 *dwc = gadget_to_dwc(g); 1604 struct dwc3 *dwc = gadget_to_dwc(g);
1597 unsigned long flags; 1605 unsigned long flags;
1598 int irq; 1606 int irq;
1599 1607
1600 spin_lock_irqsave(&dwc->lock, flags); 1608 spin_lock_irqsave(&dwc->lock, flags);
1601 1609
1602 dwc3_gadget_disable_irq(dwc); 1610 dwc3_gadget_disable_irq(dwc);
1603 __dwc3_gadget_ep_disable(dwc->eps[0]); 1611 __dwc3_gadget_ep_disable(dwc->eps[0]);
1604 __dwc3_gadget_ep_disable(dwc->eps[1]); 1612 __dwc3_gadget_ep_disable(dwc->eps[1]);
1605 1613
1606 dwc->gadget_driver = NULL; 1614 dwc->gadget_driver = NULL;
1607 1615
1608 spin_unlock_irqrestore(&dwc->lock, flags); 1616 spin_unlock_irqrestore(&dwc->lock, flags);
1609 1617
1610 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1618 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1611 free_irq(irq, dwc); 1619 free_irq(irq, dwc);
1612 1620
1613 return 0; 1621 return 0;
1614 } 1622 }
1615 1623
1616 static const struct usb_gadget_ops dwc3_gadget_ops = { 1624 static const struct usb_gadget_ops dwc3_gadget_ops = {
1617 .get_frame = dwc3_gadget_get_frame, 1625 .get_frame = dwc3_gadget_get_frame,
1618 .wakeup = dwc3_gadget_wakeup, 1626 .wakeup = dwc3_gadget_wakeup,
1619 .set_selfpowered = dwc3_gadget_set_selfpowered, 1627 .set_selfpowered = dwc3_gadget_set_selfpowered,
1620 .pullup = dwc3_gadget_pullup, 1628 .pullup = dwc3_gadget_pullup,
1621 .udc_start = dwc3_gadget_start, 1629 .udc_start = dwc3_gadget_start,
1622 .udc_stop = dwc3_gadget_stop, 1630 .udc_stop = dwc3_gadget_stop,
1623 }; 1631 };
1624 1632
1625 /* -------------------------------------------------------------------------- */ 1633 /* -------------------------------------------------------------------------- */
1626 1634
1627 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, 1635 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1628 u8 num, u32 direction) 1636 u8 num, u32 direction)
1629 { 1637 {
1630 struct dwc3_ep *dep; 1638 struct dwc3_ep *dep;
1631 u8 i; 1639 u8 i;
1632 1640
1633 for (i = 0; i < num; i++) { 1641 for (i = 0; i < num; i++) {
1634 u8 epnum = (i << 1) | (!!direction); 1642 u8 epnum = (i << 1) | (!!direction);
1635 1643
1636 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1644 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1637 if (!dep) { 1645 if (!dep) {
1638 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1646 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1639 epnum); 1647 epnum);
1640 return -ENOMEM; 1648 return -ENOMEM;
1641 } 1649 }
1642 1650
1643 dep->dwc = dwc; 1651 dep->dwc = dwc;
1644 dep->number = epnum; 1652 dep->number = epnum;
1645 dep->direction = !!direction; 1653 dep->direction = !!direction;
1646 dwc->eps[epnum] = dep; 1654 dwc->eps[epnum] = dep;
1647 1655
1648 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1656 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1649 (epnum & 1) ? "in" : "out"); 1657 (epnum & 1) ? "in" : "out");
1650 1658
1651 dep->endpoint.name = dep->name; 1659 dep->endpoint.name = dep->name;
1652 1660
1653 dev_vdbg(dwc->dev, "initializing %s\n", dep->name); 1661 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1654 1662
1655 if (epnum == 0 || epnum == 1) { 1663 if (epnum == 0 || epnum == 1) {
1656 usb_ep_set_maxpacket_limit(&dep->endpoint, 512); 1664 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1657 dep->endpoint.maxburst = 1; 1665 dep->endpoint.maxburst = 1;
1658 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1666 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1659 if (!epnum) 1667 if (!epnum)
1660 dwc->gadget.ep0 = &dep->endpoint; 1668 dwc->gadget.ep0 = &dep->endpoint;
1661 } else { 1669 } else {
1662 int ret; 1670 int ret;
1663 1671
1664 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); 1672 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1665 dep->endpoint.max_streams = 15; 1673 dep->endpoint.max_streams = 15;
1666 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1674 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1667 list_add_tail(&dep->endpoint.ep_list, 1675 list_add_tail(&dep->endpoint.ep_list,
1668 &dwc->gadget.ep_list); 1676 &dwc->gadget.ep_list);
1669 1677
1670 ret = dwc3_alloc_trb_pool(dep); 1678 ret = dwc3_alloc_trb_pool(dep);
1671 if (ret) 1679 if (ret)
1672 return ret; 1680 return ret;
1673 } 1681 }
1674 1682
1675 INIT_LIST_HEAD(&dep->request_list); 1683 INIT_LIST_HEAD(&dep->request_list);
1676 INIT_LIST_HEAD(&dep->req_queued); 1684 INIT_LIST_HEAD(&dep->req_queued);
1677 } 1685 }
1678 1686
1679 return 0; 1687 return 0;
1680 } 1688 }
1681 1689
1682 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1690 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1683 { 1691 {
1684 int ret; 1692 int ret;
1685 1693
1686 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1694 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1687 1695
1688 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); 1696 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1689 if (ret < 0) { 1697 if (ret < 0) {
1690 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); 1698 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1691 return ret; 1699 return ret;
1692 } 1700 }
1693 1701
1694 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); 1702 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1695 if (ret < 0) { 1703 if (ret < 0) {
1696 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); 1704 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1697 return ret; 1705 return ret;
1698 } 1706 }
1699 1707
1700 return 0; 1708 return 0;
1701 } 1709 }
1702 1710
1703 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1711 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1704 { 1712 {
1705 struct dwc3_ep *dep; 1713 struct dwc3_ep *dep;
1706 u8 epnum; 1714 u8 epnum;
1707 1715
1708 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1716 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1709 dep = dwc->eps[epnum]; 1717 dep = dwc->eps[epnum];
1710 if (!dep) 1718 if (!dep)
1711 continue; 1719 continue;
1712 /* 1720 /*
1713 * Physical endpoints 0 and 1 are special; they form the 1721 * Physical endpoints 0 and 1 are special; they form the
1714 * bi-directional USB endpoint 0. 1722 * bi-directional USB endpoint 0.
1715 * 1723 *
1716 * For those two physical endpoints, we don't allocate a TRB 1724 * For those two physical endpoints, we don't allocate a TRB
1717 * pool nor do we add them the endpoints list. Due to that, we 1725 * pool nor do we add them the endpoints list. Due to that, we
1718 * shouldn't do these two operations otherwise we would end up 1726 * shouldn't do these two operations otherwise we would end up
1719 * with all sorts of bugs when removing dwc3.ko. 1727 * with all sorts of bugs when removing dwc3.ko.
1720 */ 1728 */
1721 if (epnum != 0 && epnum != 1) { 1729 if (epnum != 0 && epnum != 1) {
1722 dwc3_free_trb_pool(dep); 1730 dwc3_free_trb_pool(dep);
1723 list_del(&dep->endpoint.ep_list); 1731 list_del(&dep->endpoint.ep_list);
1724 } 1732 }
1725 1733
1726 kfree(dep); 1734 kfree(dep);
1727 } 1735 }
1728 } 1736 }
1729 1737
1730 /* -------------------------------------------------------------------------- */ 1738 /* -------------------------------------------------------------------------- */
1731 1739
1732 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, 1740 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1733 struct dwc3_request *req, struct dwc3_trb *trb, 1741 struct dwc3_request *req, struct dwc3_trb *trb,
1734 const struct dwc3_event_depevt *event, int status) 1742 const struct dwc3_event_depevt *event, int status)
1735 { 1743 {
1736 unsigned int count; 1744 unsigned int count;
1737 unsigned int s_pkt = 0; 1745 unsigned int s_pkt = 0;
1738 unsigned int trb_status; 1746 unsigned int trb_status;
1739 1747
1740 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1748 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1741 /* 1749 /*
1742 * We continue despite the error. There is not much we 1750 * We continue despite the error. There is not much we
1743 * can do. If we don't clean it up we loop forever. If 1751 * can do. If we don't clean it up we loop forever. If
1744 * we skip the TRB then it gets overwritten after a 1752 * we skip the TRB then it gets overwritten after a
1745 * while since we use them in a ring buffer. A BUG() 1753 * while since we use them in a ring buffer. A BUG()
1746 * would help. Lets hope that if this occurs, someone 1754 * would help. Lets hope that if this occurs, someone
1747 * fixes the root cause instead of looking away :) 1755 * fixes the root cause instead of looking away :)
1748 */ 1756 */
1749 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1757 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1750 dep->name, trb); 1758 dep->name, trb);
1751 count = trb->size & DWC3_TRB_SIZE_MASK; 1759 count = trb->size & DWC3_TRB_SIZE_MASK;
1752 1760
1753 if (dep->direction) { 1761 if (dep->direction) {
1754 if (count) { 1762 if (count) {
1755 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1763 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1756 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1764 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1757 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1765 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1758 dep->name); 1766 dep->name);
1759 /* 1767 /*
1760 * If missed isoc occurred and there is 1768 * If missed isoc occurred and there is
1761 * no request queued then issue END 1769 * no request queued then issue END
1762 * TRANSFER, so that core generates 1770 * TRANSFER, so that core generates
1763 * next xfernotready and we will issue 1771 * next xfernotready and we will issue
1764 * a fresh START TRANSFER. 1772 * a fresh START TRANSFER.
1765 * If there are still queued request 1773 * If there are still queued request
1766 * then wait, do not issue either END 1774 * then wait, do not issue either END
1767 * or UPDATE TRANSFER, just attach next 1775 * or UPDATE TRANSFER, just attach next
1768 * request in request_list during 1776 * request in request_list during
1769 * giveback.If any future queued request 1777 * giveback.If any future queued request
1770 * is successfully transferred then we 1778 * is successfully transferred then we
1771 * will issue UPDATE TRANSFER for all 1779 * will issue UPDATE TRANSFER for all
1772 * request in the request_list. 1780 * request in the request_list.
1773 */ 1781 */
1774 dep->flags |= DWC3_EP_MISSED_ISOC; 1782 dep->flags |= DWC3_EP_MISSED_ISOC;
1775 } else { 1783 } else {
1776 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1784 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1777 dep->name); 1785 dep->name);
1778 status = -ECONNRESET; 1786 status = -ECONNRESET;
1779 } 1787 }
1780 } else { 1788 } else {
1781 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1789 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1782 } 1790 }
1783 } else { 1791 } else {
1784 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1792 if (count && (event->status & DEPEVT_STATUS_SHORT))
1785 s_pkt = 1; 1793 s_pkt = 1;
1786 } 1794 }
1787 1795
1788 /* 1796 /*
1789 * We assume here we will always receive the entire data block 1797 * We assume here we will always receive the entire data block
1790 * which we should receive. Meaning, if we program RX to 1798 * which we should receive. Meaning, if we program RX to
1791 * receive 4K but we receive only 2K, we assume that's all we 1799 * receive 4K but we receive only 2K, we assume that's all we
1792 * should receive and we simply bounce the request back to the 1800 * should receive and we simply bounce the request back to the
1793 * gadget driver for further processing. 1801 * gadget driver for further processing.
1794 */ 1802 */
1795 req->request.actual += req->request.length - count; 1803 req->request.actual += req->request.length - count;
1796 if (s_pkt) 1804 if (s_pkt)
1797 return 1; 1805 return 1;
1798 if ((event->status & DEPEVT_STATUS_LST) && 1806 if ((event->status & DEPEVT_STATUS_LST) &&
1799 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1807 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1800 DWC3_TRB_CTRL_HWO))) 1808 DWC3_TRB_CTRL_HWO)))
1801 return 1; 1809 return 1;
1802 if ((event->status & DEPEVT_STATUS_IOC) && 1810 if ((event->status & DEPEVT_STATUS_IOC) &&
1803 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1811 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1804 return 1; 1812 return 1;
1805 return 0; 1813 return 0;
1806 } 1814 }
1807 1815
1808 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1816 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1809 const struct dwc3_event_depevt *event, int status) 1817 const struct dwc3_event_depevt *event, int status)
1810 { 1818 {
1811 struct dwc3_request *req; 1819 struct dwc3_request *req;
1812 struct dwc3_trb *trb; 1820 struct dwc3_trb *trb;
1813 unsigned int slot; 1821 unsigned int slot;
1814 unsigned int i; 1822 unsigned int i;
1815 int ret; 1823 int ret;
1816 1824
1817 do { 1825 do {
1818 req = next_request(&dep->req_queued); 1826 req = next_request(&dep->req_queued);
1819 if (!req) { 1827 if (!req) {
1820 WARN_ON_ONCE(1); 1828 WARN_ON_ONCE(1);
1821 return 1; 1829 return 1;
1822 } 1830 }
1823 i = 0; 1831 i = 0;
1824 do { 1832 do {
1825 slot = req->start_slot + i; 1833 slot = req->start_slot + i;
1826 if ((slot == DWC3_TRB_NUM - 1) && 1834 if ((slot == DWC3_TRB_NUM - 1) &&
1827 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 1835 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1828 slot++; 1836 slot++;
1829 slot %= DWC3_TRB_NUM; 1837 slot %= DWC3_TRB_NUM;
1830 trb = &dep->trb_pool[slot]; 1838 trb = &dep->trb_pool[slot];
1831 1839
1832 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, 1840 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1833 event, status); 1841 event, status);
1834 if (ret) 1842 if (ret)
1835 break; 1843 break;
1836 }while (++i < req->request.num_mapped_sgs); 1844 }while (++i < req->request.num_mapped_sgs);
1837 1845
1838 dwc3_gadget_giveback(dep, req, status); 1846 dwc3_gadget_giveback(dep, req, status);
1839 1847
1840 if (ret) 1848 if (ret)
1841 break; 1849 break;
1842 } while (1); 1850 } while (1);
1843 1851
1844 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1852 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1845 list_empty(&dep->req_queued)) { 1853 list_empty(&dep->req_queued)) {
1846 if (list_empty(&dep->request_list)) { 1854 if (list_empty(&dep->request_list)) {
1847 /* 1855 /*
1848 * If there is no entry in request list then do 1856 * If there is no entry in request list then do
1849 * not issue END TRANSFER now. Just set PENDING 1857 * not issue END TRANSFER now. Just set PENDING
1850 * flag, so that END TRANSFER is issued when an 1858 * flag, so that END TRANSFER is issued when an
1851 * entry is added into request list. 1859 * entry is added into request list.
1852 */ 1860 */
1853 dep->flags = DWC3_EP_PENDING_REQUEST; 1861 dep->flags = DWC3_EP_PENDING_REQUEST;
1854 } else { 1862 } else {
1855 dwc3_stop_active_transfer(dwc, dep->number); 1863 dwc3_stop_active_transfer(dwc, dep->number);
1856 dep->flags = DWC3_EP_ENABLED; 1864 dep->flags = DWC3_EP_ENABLED;
1857 } 1865 }
1858 return 1; 1866 return 1;
1859 } 1867 }
1860 1868
1861 if ((event->status & DEPEVT_STATUS_IOC) && 1869 if ((event->status & DEPEVT_STATUS_IOC) &&
1862 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1870 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1863 return 0; 1871 return 0;
1864 return 1; 1872 return 1;
1865 } 1873 }
1866 1874
1867 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1875 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1868 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1876 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1869 int start_new) 1877 int start_new)
1870 { 1878 {
1871 unsigned status = 0; 1879 unsigned status = 0;
1872 int clean_busy; 1880 int clean_busy;
1873 1881
1874 if (event->status & DEPEVT_STATUS_BUSERR) 1882 if (event->status & DEPEVT_STATUS_BUSERR)
1875 status = -ECONNRESET; 1883 status = -ECONNRESET;
1876 1884
1877 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1885 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1878 if (clean_busy) 1886 if (clean_busy)
1879 dep->flags &= ~DWC3_EP_BUSY; 1887 dep->flags &= ~DWC3_EP_BUSY;
1880 1888
1881 /* 1889 /*
1882 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1890 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1883 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1891 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1884 */ 1892 */
1885 if (dwc->revision < DWC3_REVISION_183A) { 1893 if (dwc->revision < DWC3_REVISION_183A) {
1886 u32 reg; 1894 u32 reg;
1887 int i; 1895 int i;
1888 1896
1889 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1897 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1890 dep = dwc->eps[i]; 1898 dep = dwc->eps[i];
1891 1899
1892 if (!(dep->flags & DWC3_EP_ENABLED)) 1900 if (!(dep->flags & DWC3_EP_ENABLED))
1893 continue; 1901 continue;
1894 1902
1895 if (!list_empty(&dep->req_queued)) 1903 if (!list_empty(&dep->req_queued))
1896 return; 1904 return;
1897 } 1905 }
1898 1906
1899 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1907 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1900 reg |= dwc->u1u2; 1908 reg |= dwc->u1u2;
1901 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1909 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1902 1910
1903 dwc->u1u2 = 0; 1911 dwc->u1u2 = 0;
1904 } 1912 }
1905 } 1913 }
1906 1914
1907 static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1915 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1908 const struct dwc3_event_depevt *event) 1916 const struct dwc3_event_depevt *event)
1909 { 1917 {
1910 struct dwc3_ep *dep; 1918 struct dwc3_ep *dep;
1911 u8 epnum = event->endpoint_number; 1919 u8 epnum = event->endpoint_number;
1912 1920
1913 dep = dwc->eps[epnum]; 1921 dep = dwc->eps[epnum];
1914 1922
1915 if (!(dep->flags & DWC3_EP_ENABLED)) 1923 if (!(dep->flags & DWC3_EP_ENABLED))
1916 return; 1924 return;
1917 1925
1918 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1926 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1919 dwc3_ep_event_string(event->endpoint_event)); 1927 dwc3_ep_event_string(event->endpoint_event));
1920 1928
1921 if (epnum == 0 || epnum == 1) { 1929 if (epnum == 0 || epnum == 1) {
1922 dwc3_ep0_interrupt(dwc, event); 1930 dwc3_ep0_interrupt(dwc, event);
1923 return; 1931 return;
1924 } 1932 }
1925 1933
1926 switch (event->endpoint_event) { 1934 switch (event->endpoint_event) {
1927 case DWC3_DEPEVT_XFERCOMPLETE: 1935 case DWC3_DEPEVT_XFERCOMPLETE:
1928 dep->resource_index = 0; 1936 dep->resource_index = 0;
1929 1937
1930 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1938 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1931 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1939 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1932 dep->name); 1940 dep->name);
1933 return; 1941 return;
1934 } 1942 }
1935 1943
1936 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1944 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1937 break; 1945 break;
1938 case DWC3_DEPEVT_XFERINPROGRESS: 1946 case DWC3_DEPEVT_XFERINPROGRESS:
1939 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1947 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1940 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1948 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1941 dep->name); 1949 dep->name);
1942 return; 1950 return;
1943 } 1951 }
1944 1952
1945 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1953 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1946 break; 1954 break;
1947 case DWC3_DEPEVT_XFERNOTREADY: 1955 case DWC3_DEPEVT_XFERNOTREADY:
1948 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1956 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1949 dwc3_gadget_start_isoc(dwc, dep, event); 1957 dwc3_gadget_start_isoc(dwc, dep, event);
1950 } else { 1958 } else {
1951 int ret; 1959 int ret;
1952 1960
1953 dev_vdbg(dwc->dev, "%s: reason %s\n", 1961 dev_vdbg(dwc->dev, "%s: reason %s\n",
1954 dep->name, event->status & 1962 dep->name, event->status &
1955 DEPEVT_STATUS_TRANSFER_ACTIVE 1963 DEPEVT_STATUS_TRANSFER_ACTIVE
1956 ? "Transfer Active" 1964 ? "Transfer Active"
1957 : "Transfer Not Active"); 1965 : "Transfer Not Active");
1958 1966
1959 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1967 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1960 if (!ret || ret == -EBUSY) 1968 if (!ret || ret == -EBUSY)
1961 return; 1969 return;
1962 1970
1963 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1971 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1964 dep->name); 1972 dep->name);
1965 } 1973 }
1966 1974
1967 break; 1975 break;
1968 case DWC3_DEPEVT_STREAMEVT: 1976 case DWC3_DEPEVT_STREAMEVT:
1969 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1977 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1970 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1978 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1971 dep->name); 1979 dep->name);
1972 return; 1980 return;
1973 } 1981 }
1974 1982
1975 switch (event->status) { 1983 switch (event->status) {
1976 case DEPEVT_STREAMEVT_FOUND: 1984 case DEPEVT_STREAMEVT_FOUND:
1977 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1985 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1978 event->parameters); 1986 event->parameters);
1979 1987
1980 break; 1988 break;
1981 case DEPEVT_STREAMEVT_NOTFOUND: 1989 case DEPEVT_STREAMEVT_NOTFOUND:
1982 /* FALLTHROUGH */ 1990 /* FALLTHROUGH */
1983 default: 1991 default:
1984 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1992 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1985 } 1993 }
1986 break; 1994 break;
1987 case DWC3_DEPEVT_RXTXFIFOEVT: 1995 case DWC3_DEPEVT_RXTXFIFOEVT:
1988 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1996 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1989 break; 1997 break;
1990 case DWC3_DEPEVT_EPCMDCMPLT: 1998 case DWC3_DEPEVT_EPCMDCMPLT:
1991 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 1999 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1992 break; 2000 break;
1993 } 2001 }
1994 } 2002 }
1995 2003
1996 static void dwc3_disconnect_gadget(struct dwc3 *dwc) 2004 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1997 { 2005 {
1998 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2006 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1999 spin_unlock(&dwc->lock); 2007 spin_unlock(&dwc->lock);
2000 dwc->gadget_driver->disconnect(&dwc->gadget); 2008 dwc->gadget_driver->disconnect(&dwc->gadget);
2001 spin_lock(&dwc->lock); 2009 spin_lock(&dwc->lock);
2002 } 2010 }
2003 } 2011 }
2004 2012
2005 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 2013 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
2006 { 2014 {
2007 struct dwc3_ep *dep; 2015 struct dwc3_ep *dep;
2008 struct dwc3_gadget_ep_cmd_params params; 2016 struct dwc3_gadget_ep_cmd_params params;
2009 u32 cmd; 2017 u32 cmd;
2010 int ret; 2018 int ret;
2011 2019
2012 dep = dwc->eps[epnum]; 2020 dep = dwc->eps[epnum];
2013 2021
2014 if (!dep->resource_index) 2022 if (!dep->resource_index)
2015 return; 2023 return;
2016 2024
2017 /* 2025 /*
2018 * NOTICE: We are violating what the Databook says about the 2026 * NOTICE: We are violating what the Databook says about the
2019 * EndTransfer command. Ideally we would _always_ wait for the 2027 * EndTransfer command. Ideally we would _always_ wait for the
2020 * EndTransfer Command Completion IRQ, but that's causing too 2028 * EndTransfer Command Completion IRQ, but that's causing too
2021 * much trouble synchronizing between us and gadget driver. 2029 * much trouble synchronizing between us and gadget driver.
2022 * 2030 *
2023 * We have discussed this with the IP Provider and it was 2031 * We have discussed this with the IP Provider and it was
2024 * suggested to giveback all requests here, but give HW some 2032 * suggested to giveback all requests here, but give HW some
2025 * extra time to synchronize with the interconnect. We're using 2033 * extra time to synchronize with the interconnect. We're using
2026 * an arbitraty 100us delay for that. 2034 * an arbitraty 100us delay for that.
2027 * 2035 *
2028 * Note also that a similar handling was tested by Synopsys 2036 * Note also that a similar handling was tested by Synopsys
2029 * (thanks a lot Paul) and nothing bad has come out of it. 2037 * (thanks a lot Paul) and nothing bad has come out of it.
2030 * In short, what we're doing is: 2038 * In short, what we're doing is:
2031 * 2039 *
2032 * - Issue EndTransfer WITH CMDIOC bit set 2040 * - Issue EndTransfer WITH CMDIOC bit set
2033 * - Wait 100us 2041 * - Wait 100us
2034 */ 2042 */
2035 2043
2036 cmd = DWC3_DEPCMD_ENDTRANSFER; 2044 cmd = DWC3_DEPCMD_ENDTRANSFER;
2037 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 2045 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
2038 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 2046 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2039 memset(&params, 0, sizeof(params)); 2047 memset(&params, 0, sizeof(params));
2040 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params); 2048 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2041 WARN_ON_ONCE(ret); 2049 WARN_ON_ONCE(ret);
2042 dep->resource_index = 0; 2050 dep->resource_index = 0;
2043 dep->flags &= ~DWC3_EP_BUSY; 2051 dep->flags &= ~DWC3_EP_BUSY;
2044 udelay(100); 2052 udelay(100);
2045 } 2053 }
2046 2054
2047 static void dwc3_stop_active_transfers(struct dwc3 *dwc) 2055 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2048 { 2056 {
2049 u32 epnum; 2057 u32 epnum;
2050 2058
2051 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2059 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2052 struct dwc3_ep *dep; 2060 struct dwc3_ep *dep;
2053 2061
2054 dep = dwc->eps[epnum]; 2062 dep = dwc->eps[epnum];
2055 if (!dep) 2063 if (!dep)
2056 continue; 2064 continue;
2057 2065
2058 if (!(dep->flags & DWC3_EP_ENABLED)) 2066 if (!(dep->flags & DWC3_EP_ENABLED))
2059 continue; 2067 continue;
2060 2068
2061 dwc3_remove_requests(dwc, dep); 2069 dwc3_remove_requests(dwc, dep);
2062 } 2070 }
2063 } 2071 }
2064 2072
2065 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 2073 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2066 { 2074 {
2067 u32 epnum; 2075 u32 epnum;
2068 2076
2069 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2077 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2070 struct dwc3_ep *dep; 2078 struct dwc3_ep *dep;
2071 struct dwc3_gadget_ep_cmd_params params; 2079 struct dwc3_gadget_ep_cmd_params params;
2072 int ret; 2080 int ret;
2073 2081
2074 dep = dwc->eps[epnum]; 2082 dep = dwc->eps[epnum];
2075 if (!dep) 2083 if (!dep)
2076 continue; 2084 continue;
2077 2085
2078 if (!(dep->flags & DWC3_EP_STALL)) 2086 if (!(dep->flags & DWC3_EP_STALL))
2079 continue; 2087 continue;
2080 2088
2081 dep->flags &= ~DWC3_EP_STALL; 2089 dep->flags &= ~DWC3_EP_STALL;
2082 2090
2083 memset(&params, 0, sizeof(params)); 2091 memset(&params, 0, sizeof(params));
2084 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 2092 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2085 DWC3_DEPCMD_CLEARSTALL, &params); 2093 DWC3_DEPCMD_CLEARSTALL, &params);
2086 WARN_ON_ONCE(ret); 2094 WARN_ON_ONCE(ret);
2087 } 2095 }
2088 } 2096 }
2089 2097
2090 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 2098 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2091 { 2099 {
2092 int reg; 2100 int reg;
2093 2101
2094 dev_vdbg(dwc->dev, "%s\n", __func__); 2102 dev_vdbg(dwc->dev, "%s\n", __func__);
2095 2103
2096 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2104 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2097 reg &= ~DWC3_DCTL_INITU1ENA; 2105 reg &= ~DWC3_DCTL_INITU1ENA;
2098 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2106 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2099 2107
2100 reg &= ~DWC3_DCTL_INITU2ENA; 2108 reg &= ~DWC3_DCTL_INITU2ENA;
2101 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2109 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2102 2110
2103 dwc3_disconnect_gadget(dwc); 2111 dwc3_disconnect_gadget(dwc);
2104 dwc->start_config_issued = false; 2112 dwc->start_config_issued = false;
2105 2113
2106 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2114 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2107 dwc->setup_packet_pending = false; 2115 dwc->setup_packet_pending = false;
2108 } 2116 }
2109 2117
2110 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 2118 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2111 { 2119 {
2112 u32 reg; 2120 u32 reg;
2113 2121
2114 dev_vdbg(dwc->dev, "%s\n", __func__); 2122 dev_vdbg(dwc->dev, "%s\n", __func__);
2115 2123
2116 /* 2124 /*
2117 * WORKAROUND: DWC3 revisions <1.88a have an issue which 2125 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2118 * would cause a missing Disconnect Event if there's a 2126 * would cause a missing Disconnect Event if there's a
2119 * pending Setup Packet in the FIFO. 2127 * pending Setup Packet in the FIFO.
2120 * 2128 *
2121 * There's no suggested workaround on the official Bug 2129 * There's no suggested workaround on the official Bug
2122 * report, which states that "unless the driver/application 2130 * report, which states that "unless the driver/application
2123 * is doing any special handling of a disconnect event, 2131 * is doing any special handling of a disconnect event,
2124 * there is no functional issue". 2132 * there is no functional issue".
2125 * 2133 *
2126 * Unfortunately, it turns out that we _do_ some special 2134 * Unfortunately, it turns out that we _do_ some special
2127 * handling of a disconnect event, namely complete all 2135 * handling of a disconnect event, namely complete all
2128 * pending transfers, notify gadget driver of the 2136 * pending transfers, notify gadget driver of the
2129 * disconnection, and so on. 2137 * disconnection, and so on.
2130 * 2138 *
2131 * Our suggested workaround is to follow the Disconnect 2139 * Our suggested workaround is to follow the Disconnect
2132 * Event steps here, instead, based on a setup_packet_pending 2140 * Event steps here, instead, based on a setup_packet_pending
2133 * flag. Such flag gets set whenever we have a XferNotReady 2141 * flag. Such flag gets set whenever we have a XferNotReady
2134 * event on EP0 and gets cleared on XferComplete for the 2142 * event on EP0 and gets cleared on XferComplete for the
2135 * same endpoint. 2143 * same endpoint.
2136 * 2144 *
2137 * Refers to: 2145 * Refers to:
2138 * 2146 *
2139 * STAR#9000466709: RTL: Device : Disconnect event not 2147 * STAR#9000466709: RTL: Device : Disconnect event not
2140 * generated if setup packet pending in FIFO 2148 * generated if setup packet pending in FIFO
2141 */ 2149 */
2142 if (dwc->revision < DWC3_REVISION_188A) { 2150 if (dwc->revision < DWC3_REVISION_188A) {
2143 if (dwc->setup_packet_pending) 2151 if (dwc->setup_packet_pending)
2144 dwc3_gadget_disconnect_interrupt(dwc); 2152 dwc3_gadget_disconnect_interrupt(dwc);
2145 } 2153 }
2146 2154
2147 /* after reset -> Default State */ 2155 /* after reset -> Default State */
2148 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 2156 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2149 2157
2150 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2158 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2151 dwc3_disconnect_gadget(dwc); 2159 dwc3_disconnect_gadget(dwc);
2152 2160
2153 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2161 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2154 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2162 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2155 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2163 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2156 dwc->test_mode = false; 2164 dwc->test_mode = false;
2157 2165
2158 dwc3_stop_active_transfers(dwc); 2166 dwc3_stop_active_transfers(dwc);
2159 dwc3_clear_stall_all_ep(dwc); 2167 dwc3_clear_stall_all_ep(dwc);
2160 dwc->start_config_issued = false; 2168 dwc->start_config_issued = false;
2161 2169
2162 /* Reset device address to zero */ 2170 /* Reset device address to zero */
2163 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2171 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2164 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2172 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2165 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2173 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2166 } 2174 }
2167 2175
2168 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2176 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2169 { 2177 {
2170 u32 reg; 2178 u32 reg;
2171 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2179 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2172 2180
2173 /* 2181 /*
2174 * We change the clock only at SS but I dunno why I would want to do 2182 * We change the clock only at SS but I dunno why I would want to do
2175 * this. Maybe it becomes part of the power saving plan. 2183 * this. Maybe it becomes part of the power saving plan.
2176 */ 2184 */
2177 2185
2178 if (speed != DWC3_DSTS_SUPERSPEED) 2186 if (speed != DWC3_DSTS_SUPERSPEED)
2179 return; 2187 return;
2180 2188
2181 /* 2189 /*
2182 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2190 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2183 * each time on Connect Done. 2191 * each time on Connect Done.
2184 */ 2192 */
2185 if (!usb30_clock) 2193 if (!usb30_clock)
2186 return; 2194 return;
2187 2195
2188 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2196 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2189 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2197 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2190 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2198 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2191 } 2199 }
2192 2200
2193 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2201 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2194 { 2202 {
2195 struct dwc3_ep *dep; 2203 struct dwc3_ep *dep;
2196 int ret; 2204 int ret;
2197 u32 reg; 2205 u32 reg;
2198 u8 speed; 2206 u8 speed;
2199 2207
2200 dev_vdbg(dwc->dev, "%s\n", __func__); 2208 dev_vdbg(dwc->dev, "%s\n", __func__);
2201 2209
2202 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2210 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2203 speed = reg & DWC3_DSTS_CONNECTSPD; 2211 speed = reg & DWC3_DSTS_CONNECTSPD;
2204 dwc->speed = speed; 2212 dwc->speed = speed;
2205 2213
2206 dwc3_update_ram_clk_sel(dwc, speed); 2214 dwc3_update_ram_clk_sel(dwc, speed);
2207 2215
2208 switch (speed) { 2216 switch (speed) {
2209 case DWC3_DCFG_SUPERSPEED: 2217 case DWC3_DCFG_SUPERSPEED:
2210 /* 2218 /*
2211 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2219 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2212 * would cause a missing USB3 Reset event. 2220 * would cause a missing USB3 Reset event.
2213 * 2221 *
2214 * In such situations, we should force a USB3 Reset 2222 * In such situations, we should force a USB3 Reset
2215 * event by calling our dwc3_gadget_reset_interrupt() 2223 * event by calling our dwc3_gadget_reset_interrupt()
2216 * routine. 2224 * routine.
2217 * 2225 *
2218 * Refers to: 2226 * Refers to:
2219 * 2227 *
2220 * STAR#9000483510: RTL: SS : USB3 reset event may 2228 * STAR#9000483510: RTL: SS : USB3 reset event may
2221 * not be generated always when the link enters poll 2229 * not be generated always when the link enters poll
2222 */ 2230 */
2223 if (dwc->revision < DWC3_REVISION_190A) 2231 if (dwc->revision < DWC3_REVISION_190A)
2224 dwc3_gadget_reset_interrupt(dwc); 2232 dwc3_gadget_reset_interrupt(dwc);
2225 2233
2226 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2234 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2227 dwc->gadget.ep0->maxpacket = 512; 2235 dwc->gadget.ep0->maxpacket = 512;
2228 dwc->gadget.speed = USB_SPEED_SUPER; 2236 dwc->gadget.speed = USB_SPEED_SUPER;
2229 break; 2237 break;
2230 case DWC3_DCFG_HIGHSPEED: 2238 case DWC3_DCFG_HIGHSPEED:
2231 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2239 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2232 dwc->gadget.ep0->maxpacket = 64; 2240 dwc->gadget.ep0->maxpacket = 64;
2233 dwc->gadget.speed = USB_SPEED_HIGH; 2241 dwc->gadget.speed = USB_SPEED_HIGH;
2234 break; 2242 break;
2235 case DWC3_DCFG_FULLSPEED2: 2243 case DWC3_DCFG_FULLSPEED2:
2236 case DWC3_DCFG_FULLSPEED1: 2244 case DWC3_DCFG_FULLSPEED1:
2237 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2245 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2238 dwc->gadget.ep0->maxpacket = 64; 2246 dwc->gadget.ep0->maxpacket = 64;
2239 dwc->gadget.speed = USB_SPEED_FULL; 2247 dwc->gadget.speed = USB_SPEED_FULL;
2240 break; 2248 break;
2241 case DWC3_DCFG_LOWSPEED: 2249 case DWC3_DCFG_LOWSPEED:
2242 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2250 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2243 dwc->gadget.ep0->maxpacket = 8; 2251 dwc->gadget.ep0->maxpacket = 8;
2244 dwc->gadget.speed = USB_SPEED_LOW; 2252 dwc->gadget.speed = USB_SPEED_LOW;
2245 break; 2253 break;
2246 } 2254 }
2247 2255
2248 /* Enable USB2 LPM Capability */ 2256 /* Enable USB2 LPM Capability */
2249 2257
2250 if ((dwc->revision > DWC3_REVISION_194A) 2258 if ((dwc->revision > DWC3_REVISION_194A)
2251 && (speed != DWC3_DCFG_SUPERSPEED)) { 2259 && (speed != DWC3_DCFG_SUPERSPEED)) {
2252 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2260 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2253 reg |= DWC3_DCFG_LPM_CAP; 2261 reg |= DWC3_DCFG_LPM_CAP;
2254 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2262 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2255 2263
2256 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2264 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2257 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2265 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2258 2266
2259 /* 2267 /*
2260 * TODO: This should be configurable. For now using 2268 * TODO: This should be configurable. For now using
2261 * maximum allowed HIRD threshold value of 0b1100 2269 * maximum allowed HIRD threshold value of 0b1100
2262 */ 2270 */
2263 reg |= DWC3_DCTL_HIRD_THRES(12); 2271 reg |= DWC3_DCTL_HIRD_THRES(12);
2264 2272
2265 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2273 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2266 } 2274 }
2267 2275
2268 dep = dwc->eps[0]; 2276 dep = dwc->eps[0];
2269 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); 2277 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2270 if (ret) { 2278 if (ret) {
2271 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2279 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2272 return; 2280 return;
2273 } 2281 }
2274 2282
2275 dep = dwc->eps[1]; 2283 dep = dwc->eps[1];
2276 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); 2284 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2277 if (ret) { 2285 if (ret) {
2278 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2286 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2279 return; 2287 return;
2280 } 2288 }
2281 2289
2282 /* 2290 /*
2283 * Configure PHY via GUSB3PIPECTLn if required. 2291 * Configure PHY via GUSB3PIPECTLn if required.
2284 * 2292 *
2285 * Update GTXFIFOSIZn 2293 * Update GTXFIFOSIZn
2286 * 2294 *
2287 * In both cases reset values should be sufficient. 2295 * In both cases reset values should be sufficient.
2288 */ 2296 */
2289 } 2297 }
2290 2298
2291 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2299 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2292 { 2300 {
2293 dev_vdbg(dwc->dev, "%s\n", __func__); 2301 dev_vdbg(dwc->dev, "%s\n", __func__);
2294 2302
2295 /* 2303 /*
2296 * TODO take core out of low power mode when that's 2304 * TODO take core out of low power mode when that's
2297 * implemented. 2305 * implemented.
2298 */ 2306 */
2299 2307
2300 dwc->gadget_driver->resume(&dwc->gadget); 2308 dwc->gadget_driver->resume(&dwc->gadget);
2301 } 2309 }
2302 2310
2303 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2311 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2304 unsigned int evtinfo) 2312 unsigned int evtinfo)
2305 { 2313 {
2306 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2314 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2307 unsigned int pwropt; 2315 unsigned int pwropt;
2308 2316
2309 /* 2317 /*
2310 * WORKAROUND: DWC3 < 2.50a have an issue when configured without 2318 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2311 * Hibernation mode enabled which would show up when device detects 2319 * Hibernation mode enabled which would show up when device detects
2312 * host-initiated U3 exit. 2320 * host-initiated U3 exit.
2313 * 2321 *
2314 * In that case, device will generate a Link State Change Interrupt 2322 * In that case, device will generate a Link State Change Interrupt
2315 * from U3 to RESUME which is only necessary if Hibernation is 2323 * from U3 to RESUME which is only necessary if Hibernation is
2316 * configured in. 2324 * configured in.
2317 * 2325 *
2318 * There are no functional changes due to such spurious event and we 2326 * There are no functional changes due to such spurious event and we
2319 * just need to ignore it. 2327 * just need to ignore it.
2320 * 2328 *
2321 * Refers to: 2329 * Refers to:
2322 * 2330 *
2323 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation 2331 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2324 * operational mode 2332 * operational mode
2325 */ 2333 */
2326 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 2334 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2327 if ((dwc->revision < DWC3_REVISION_250A) && 2335 if ((dwc->revision < DWC3_REVISION_250A) &&
2328 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { 2336 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2329 if ((dwc->link_state == DWC3_LINK_STATE_U3) && 2337 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2330 (next == DWC3_LINK_STATE_RESUME)) { 2338 (next == DWC3_LINK_STATE_RESUME)) {
2331 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); 2339 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2332 return; 2340 return;
2333 } 2341 }
2334 } 2342 }
2335 2343
2336 /* 2344 /*
2337 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2345 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2338 * on the link partner, the USB session might do multiple entry/exit 2346 * on the link partner, the USB session might do multiple entry/exit
2339 * of low power states before a transfer takes place. 2347 * of low power states before a transfer takes place.
2340 * 2348 *
2341 * Due to this problem, we might experience lower throughput. The 2349 * Due to this problem, we might experience lower throughput. The
2342 * suggested workaround is to disable DCTL[12:9] bits if we're 2350 * suggested workaround is to disable DCTL[12:9] bits if we're
2343 * transitioning from U1/U2 to U0 and enable those bits again 2351 * transitioning from U1/U2 to U0 and enable those bits again
2344 * after a transfer completes and there are no pending transfers 2352 * after a transfer completes and there are no pending transfers
2345 * on any of the enabled endpoints. 2353 * on any of the enabled endpoints.
2346 * 2354 *
2347 * This is the first half of that workaround. 2355 * This is the first half of that workaround.
2348 * 2356 *
2349 * Refers to: 2357 * Refers to:
2350 * 2358 *
2351 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2359 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2352 * core send LGO_Ux entering U0 2360 * core send LGO_Ux entering U0
2353 */ 2361 */
2354 if (dwc->revision < DWC3_REVISION_183A) { 2362 if (dwc->revision < DWC3_REVISION_183A) {
2355 if (next == DWC3_LINK_STATE_U0) { 2363 if (next == DWC3_LINK_STATE_U0) {
2356 u32 u1u2; 2364 u32 u1u2;
2357 u32 reg; 2365 u32 reg;
2358 2366
2359 switch (dwc->link_state) { 2367 switch (dwc->link_state) {
2360 case DWC3_LINK_STATE_U1: 2368 case DWC3_LINK_STATE_U1:
2361 case DWC3_LINK_STATE_U2: 2369 case DWC3_LINK_STATE_U2:
2362 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2370 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2363 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2371 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2364 | DWC3_DCTL_ACCEPTU2ENA 2372 | DWC3_DCTL_ACCEPTU2ENA
2365 | DWC3_DCTL_INITU1ENA 2373 | DWC3_DCTL_INITU1ENA
2366 | DWC3_DCTL_ACCEPTU1ENA); 2374 | DWC3_DCTL_ACCEPTU1ENA);
2367 2375
2368 if (!dwc->u1u2) 2376 if (!dwc->u1u2)
2369 dwc->u1u2 = reg & u1u2; 2377 dwc->u1u2 = reg & u1u2;
2370 2378
2371 reg &= ~u1u2; 2379 reg &= ~u1u2;
2372 2380
2373 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2381 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2374 break; 2382 break;
2375 default: 2383 default:
2376 /* do nothing */ 2384 /* do nothing */
2377 break; 2385 break;
2378 } 2386 }
2379 } 2387 }
2380 } 2388 }
2381 2389
2382 dwc->link_state = next; 2390 dwc->link_state = next;
2383 2391
2384 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2392 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2385 } 2393 }
2386 2394
2387 static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2395 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2388 const struct dwc3_event_devt *event) 2396 const struct dwc3_event_devt *event)
2389 { 2397 {
2390 switch (event->type) { 2398 switch (event->type) {
2391 case DWC3_DEVICE_EVENT_DISCONNECT: 2399 case DWC3_DEVICE_EVENT_DISCONNECT:
2392 dwc3_gadget_disconnect_interrupt(dwc); 2400 dwc3_gadget_disconnect_interrupt(dwc);
2393 break; 2401 break;
2394 case DWC3_DEVICE_EVENT_RESET: 2402 case DWC3_DEVICE_EVENT_RESET:
2395 dwc3_gadget_reset_interrupt(dwc); 2403 dwc3_gadget_reset_interrupt(dwc);
2396 break; 2404 break;
2397 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2405 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2398 dwc3_gadget_conndone_interrupt(dwc); 2406 dwc3_gadget_conndone_interrupt(dwc);
2399 break; 2407 break;
2400 case DWC3_DEVICE_EVENT_WAKEUP: 2408 case DWC3_DEVICE_EVENT_WAKEUP:
2401 dwc3_gadget_wakeup_interrupt(dwc); 2409 dwc3_gadget_wakeup_interrupt(dwc);
2402 break; 2410 break;
2403 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2411 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2404 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2412 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2405 break; 2413 break;
2406 case DWC3_DEVICE_EVENT_EOPF: 2414 case DWC3_DEVICE_EVENT_EOPF:
2407 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2415 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2408 break; 2416 break;
2409 case DWC3_DEVICE_EVENT_SOF: 2417 case DWC3_DEVICE_EVENT_SOF:
2410 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2418 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2411 break; 2419 break;
2412 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2420 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2413 dev_vdbg(dwc->dev, "Erratic Error\n"); 2421 dev_vdbg(dwc->dev, "Erratic Error\n");
2414 break; 2422 break;
2415 case DWC3_DEVICE_EVENT_CMD_CMPL: 2423 case DWC3_DEVICE_EVENT_CMD_CMPL:
2416 dev_vdbg(dwc->dev, "Command Complete\n"); 2424 dev_vdbg(dwc->dev, "Command Complete\n");
2417 break; 2425 break;
2418 case DWC3_DEVICE_EVENT_OVERFLOW: 2426 case DWC3_DEVICE_EVENT_OVERFLOW:
2419 dev_vdbg(dwc->dev, "Overflow\n"); 2427 dev_vdbg(dwc->dev, "Overflow\n");
2420 break; 2428 break;
2421 default: 2429 default:
2422 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2430 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2423 } 2431 }
2424 } 2432 }
2425 2433
2426 static void dwc3_process_event_entry(struct dwc3 *dwc, 2434 static void dwc3_process_event_entry(struct dwc3 *dwc,
2427 const union dwc3_event *event) 2435 const union dwc3_event *event)
2428 { 2436 {
2429 /* Endpoint IRQ, handle it and return early */ 2437 /* Endpoint IRQ, handle it and return early */
2430 if (event->type.is_devspec == 0) { 2438 if (event->type.is_devspec == 0) {
2431 /* depevt */ 2439 /* depevt */
2432 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2440 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2433 } 2441 }
2434 2442
2435 switch (event->type.type) { 2443 switch (event->type.type) {
2436 case DWC3_EVENT_TYPE_DEV: 2444 case DWC3_EVENT_TYPE_DEV:
2437 dwc3_gadget_interrupt(dwc, &event->devt); 2445 dwc3_gadget_interrupt(dwc, &event->devt);
2438 break; 2446 break;
2439 /* REVISIT what to do with Carkit and I2C events ? */ 2447 /* REVISIT what to do with Carkit and I2C events ? */
2440 default: 2448 default:
2441 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2449 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2442 } 2450 }
2443 } 2451 }
2444 2452
2445 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2453 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2446 { 2454 {
2447 struct dwc3_event_buffer *evt; 2455 struct dwc3_event_buffer *evt;
2448 irqreturn_t ret = IRQ_NONE; 2456 irqreturn_t ret = IRQ_NONE;
2449 int left; 2457 int left;
2450 u32 reg; 2458 u32 reg;
2451 2459
2452 evt = dwc->ev_buffs[buf]; 2460 evt = dwc->ev_buffs[buf];
2453 left = evt->count; 2461 left = evt->count;
2454 2462
2455 if (!(evt->flags & DWC3_EVENT_PENDING)) 2463 if (!(evt->flags & DWC3_EVENT_PENDING))
2456 return IRQ_NONE; 2464 return IRQ_NONE;
2457 2465
2458 while (left > 0) { 2466 while (left > 0) {
2459 union dwc3_event event; 2467 union dwc3_event event;
2460 2468
2461 event.raw = *(u32 *) (evt->buf + evt->lpos); 2469 event.raw = *(u32 *) (evt->buf + evt->lpos);
2462 2470
2463 dwc3_process_event_entry(dwc, &event); 2471 dwc3_process_event_entry(dwc, &event);
2464 2472
2465 /* 2473 /*
2466 * FIXME we wrap around correctly to the next entry as 2474 * FIXME we wrap around correctly to the next entry as
2467 * almost all entries are 4 bytes in size. There is one 2475 * almost all entries are 4 bytes in size. There is one
2468 * entry which has 12 bytes which is a regular entry 2476 * entry which has 12 bytes which is a regular entry
2469 * followed by 8 bytes data. ATM I don't know how 2477 * followed by 8 bytes data. ATM I don't know how
2470 * things are organized if we get next to the a 2478 * things are organized if we get next to the a
2471 * boundary so I worry about that once we try to handle 2479 * boundary so I worry about that once we try to handle
2472 * that. 2480 * that.
2473 */ 2481 */
2474 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2482 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2475 left -= 4; 2483 left -= 4;
2476 2484
2477 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2485 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2478 } 2486 }
2479 2487
2480 evt->count = 0; 2488 evt->count = 0;
2481 evt->flags &= ~DWC3_EVENT_PENDING; 2489 evt->flags &= ~DWC3_EVENT_PENDING;
2482 ret = IRQ_HANDLED; 2490 ret = IRQ_HANDLED;
2483 2491
2484 /* Unmask interrupt */ 2492 /* Unmask interrupt */
2485 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2493 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2486 reg &= ~DWC3_GEVNTSIZ_INTMASK; 2494 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2487 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2495 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2488 2496
2489 return ret; 2497 return ret;
2490 } 2498 }
2491 2499
2492 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) 2500 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2493 { 2501 {
2494 struct dwc3 *dwc = _dwc; 2502 struct dwc3 *dwc = _dwc;
2495 unsigned long flags; 2503 unsigned long flags;
2496 irqreturn_t ret = IRQ_NONE; 2504 irqreturn_t ret = IRQ_NONE;
2497 int i; 2505 int i;
2498 2506
2499 spin_lock_irqsave(&dwc->lock, flags); 2507 spin_lock_irqsave(&dwc->lock, flags);
2500 2508
2501 for (i = 0; i < dwc->num_event_buffers; i++) 2509 for (i = 0; i < dwc->num_event_buffers; i++)
2502 ret |= dwc3_process_event_buf(dwc, i); 2510 ret |= dwc3_process_event_buf(dwc, i);
2503 2511
2504 spin_unlock_irqrestore(&dwc->lock, flags); 2512 spin_unlock_irqrestore(&dwc->lock, flags);
2505 2513
2506 return ret; 2514 return ret;
2507 } 2515 }
2508 2516
2509 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) 2517 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2510 { 2518 {
2511 struct dwc3_event_buffer *evt; 2519 struct dwc3_event_buffer *evt;
2512 u32 count; 2520 u32 count;
2513 u32 reg; 2521 u32 reg;
2514 2522
2515 evt = dwc->ev_buffs[buf]; 2523 evt = dwc->ev_buffs[buf];
2516 2524
2517 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2525 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2518 count &= DWC3_GEVNTCOUNT_MASK; 2526 count &= DWC3_GEVNTCOUNT_MASK;
2519 if (!count) 2527 if (!count)
2520 return IRQ_NONE; 2528 return IRQ_NONE;
2521 2529
2522 evt->count = count; 2530 evt->count = count;
2523 evt->flags |= DWC3_EVENT_PENDING; 2531 evt->flags |= DWC3_EVENT_PENDING;
2524 2532
2525 /* Mask interrupt */ 2533 /* Mask interrupt */
2526 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2534 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2527 reg |= DWC3_GEVNTSIZ_INTMASK; 2535 reg |= DWC3_GEVNTSIZ_INTMASK;
2528 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2536 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2529 2537
2530 return IRQ_WAKE_THREAD; 2538 return IRQ_WAKE_THREAD;
2531 } 2539 }
2532 2540
2533 static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2541 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2534 { 2542 {
2535 struct dwc3 *dwc = _dwc; 2543 struct dwc3 *dwc = _dwc;
2536 int i; 2544 int i;
2537 irqreturn_t ret = IRQ_NONE; 2545 irqreturn_t ret = IRQ_NONE;
2538 2546
2539 spin_lock(&dwc->lock); 2547 spin_lock(&dwc->lock);
2540 2548
2541 for (i = 0; i < dwc->num_event_buffers; i++) { 2549 for (i = 0; i < dwc->num_event_buffers; i++) {
2542 irqreturn_t status; 2550 irqreturn_t status;
2543 2551
2544 status = dwc3_check_event_buf(dwc, i); 2552 status = dwc3_check_event_buf(dwc, i);
2545 if (status == IRQ_WAKE_THREAD) 2553 if (status == IRQ_WAKE_THREAD)
2546 ret = status; 2554 ret = status;
2547 } 2555 }
2548 2556
2549 spin_unlock(&dwc->lock); 2557 spin_unlock(&dwc->lock);
2550 2558
2551 return ret; 2559 return ret;
2552 } 2560 }
2553 2561
2554 /** 2562 /**
2555 * dwc3_gadget_init - Initializes gadget related registers 2563 * dwc3_gadget_init - Initializes gadget related registers
2556 * @dwc: pointer to our controller context structure 2564 * @dwc: pointer to our controller context structure
2557 * 2565 *
2558 * Returns 0 on success otherwise negative errno. 2566 * Returns 0 on success otherwise negative errno.
2559 */ 2567 */
2560 int dwc3_gadget_init(struct dwc3 *dwc) 2568 int dwc3_gadget_init(struct dwc3 *dwc)
2561 { 2569 {
2562 int ret; 2570 int ret;
2563 2571
2564 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2572 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2565 &dwc->ctrl_req_addr, GFP_KERNEL); 2573 &dwc->ctrl_req_addr, GFP_KERNEL);
2566 if (!dwc->ctrl_req) { 2574 if (!dwc->ctrl_req) {
2567 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2575 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2568 ret = -ENOMEM; 2576 ret = -ENOMEM;
2569 goto err0; 2577 goto err0;
2570 } 2578 }
2571 2579
2572 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2580 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2573 &dwc->ep0_trb_addr, GFP_KERNEL); 2581 &dwc->ep0_trb_addr, GFP_KERNEL);
2574 if (!dwc->ep0_trb) { 2582 if (!dwc->ep0_trb) {
2575 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2583 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2576 ret = -ENOMEM; 2584 ret = -ENOMEM;
2577 goto err1; 2585 goto err1;
2578 } 2586 }
2579 2587
2580 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2588 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2581 if (!dwc->setup_buf) { 2589 if (!dwc->setup_buf) {
2582 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2590 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2583 ret = -ENOMEM; 2591 ret = -ENOMEM;
2584 goto err2; 2592 goto err2;
2585 } 2593 }
2586 2594
2587 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2595 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2588 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2596 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2589 GFP_KERNEL); 2597 GFP_KERNEL);
2590 if (!dwc->ep0_bounce) { 2598 if (!dwc->ep0_bounce) {
2591 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2599 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2592 ret = -ENOMEM; 2600 ret = -ENOMEM;
2593 goto err3; 2601 goto err3;
2594 } 2602 }
2595 2603
2596 dwc->gadget.ops = &dwc3_gadget_ops; 2604 dwc->gadget.ops = &dwc3_gadget_ops;
2597 dwc->gadget.max_speed = USB_SPEED_SUPER; 2605 dwc->gadget.max_speed = USB_SPEED_SUPER;
2598 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2606 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2599 dwc->gadget.sg_supported = true; 2607 dwc->gadget.sg_supported = true;
2600 dwc->gadget.name = "dwc3-gadget"; 2608 dwc->gadget.name = "dwc3-gadget";
2601 2609
2602 /* 2610 /*
2603 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize 2611 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2604 * on ep out. 2612 * on ep out.
2605 */ 2613 */
2606 dwc->gadget.quirk_ep_out_aligned_size = true; 2614 dwc->gadget.quirk_ep_out_aligned_size = true;
2607 2615
2608 /* 2616 /*
2609 * REVISIT: Here we should clear all pending IRQs to be 2617 * REVISIT: Here we should clear all pending IRQs to be
2610 * sure we're starting from a well known location. 2618 * sure we're starting from a well known location.
2611 */ 2619 */
2612 2620
2613 ret = dwc3_gadget_init_endpoints(dwc); 2621 ret = dwc3_gadget_init_endpoints(dwc);
2614 if (ret) 2622 if (ret)
2615 goto err4; 2623 goto err4;
2616 2624
2617 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2625 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2618 if (ret) { 2626 if (ret) {
2619 dev_err(dwc->dev, "failed to register udc\n"); 2627 dev_err(dwc->dev, "failed to register udc\n");
2620 goto err4; 2628 goto err4;
2621 } 2629 }
2622 2630
2623 return 0; 2631 return 0;
2624 2632
2625 err4: 2633 err4:
2626 dwc3_gadget_free_endpoints(dwc); 2634 dwc3_gadget_free_endpoints(dwc);
2627 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2635 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2628 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2636 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2629 2637
2630 err3: 2638 err3:
2631 kfree(dwc->setup_buf); 2639 kfree(dwc->setup_buf);
2632 2640
2633 err2: 2641 err2:
2634 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2642 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2635 dwc->ep0_trb, dwc->ep0_trb_addr); 2643 dwc->ep0_trb, dwc->ep0_trb_addr);
2636 2644
2637 err1: 2645 err1:
2638 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2646 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2639 dwc->ctrl_req, dwc->ctrl_req_addr); 2647 dwc->ctrl_req, dwc->ctrl_req_addr);
2640 2648
2641 err0: 2649 err0:
2642 return ret; 2650 return ret;
2643 } 2651 }
2644 2652
2645 /* -------------------------------------------------------------------------- */ 2653 /* -------------------------------------------------------------------------- */
2646 2654
2647 void dwc3_gadget_exit(struct dwc3 *dwc) 2655 void dwc3_gadget_exit(struct dwc3 *dwc)
2648 { 2656 {
2649 usb_del_gadget_udc(&dwc->gadget); 2657 usb_del_gadget_udc(&dwc->gadget);
2650 2658
2651 dwc3_gadget_free_endpoints(dwc); 2659 dwc3_gadget_free_endpoints(dwc);
2652 2660
2653 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2661 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2654 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2662 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2655 2663
2656 kfree(dwc->setup_buf); 2664 kfree(dwc->setup_buf);
2657 2665
2658 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2666 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2659 dwc->ep0_trb, dwc->ep0_trb_addr); 2667 dwc->ep0_trb, dwc->ep0_trb_addr);
2660 2668
2661 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2669 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2662 dwc->ctrl_req, dwc->ctrl_req_addr); 2670 dwc->ctrl_req, dwc->ctrl_req_addr);
2663 } 2671 }
2664 2672
2665 int dwc3_gadget_prepare(struct dwc3 *dwc) 2673 int dwc3_gadget_prepare(struct dwc3 *dwc)
2666 { 2674 {
2667 if (dwc->pullups_connected) 2675 if (dwc->pullups_connected)
2668 dwc3_gadget_disable_irq(dwc); 2676 dwc3_gadget_disable_irq(dwc);
2669 2677
2670 return 0; 2678 return 0;
2671 } 2679 }
2672 2680
2673 void dwc3_gadget_complete(struct dwc3 *dwc) 2681 void dwc3_gadget_complete(struct dwc3 *dwc)
2674 { 2682 {
2675 if (dwc->pullups_connected) { 2683 if (dwc->pullups_connected) {
2676 dwc3_gadget_enable_irq(dwc); 2684 dwc3_gadget_enable_irq(dwc);
2677 dwc3_gadget_run_stop(dwc, true); 2685 dwc3_gadget_run_stop(dwc, true);
2678 } 2686 }
2679 } 2687 }
2680 2688
2681 int dwc3_gadget_suspend(struct dwc3 *dwc) 2689 int dwc3_gadget_suspend(struct dwc3 *dwc)
2682 { 2690 {
2683 __dwc3_gadget_ep_disable(dwc->eps[0]); 2691 __dwc3_gadget_ep_disable(dwc->eps[0]);
2684 __dwc3_gadget_ep_disable(dwc->eps[1]); 2692 __dwc3_gadget_ep_disable(dwc->eps[1]);
2685 2693
2686 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); 2694 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2687 2695
2688 return 0; 2696 return 0;
2689 } 2697 }
2690 2698
2691 int dwc3_gadget_resume(struct dwc3 *dwc) 2699 int dwc3_gadget_resume(struct dwc3 *dwc)
2692 { 2700 {
2693 struct dwc3_ep *dep; 2701 struct dwc3_ep *dep;
2694 int ret; 2702 int ret;
2695 2703
2696 /* Start with SuperSpeed Default */ 2704 /* Start with SuperSpeed Default */
2697 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2705 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2698 2706
2699 dep = dwc->eps[0]; 2707 dep = dwc->eps[0];
2700 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 2708 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2701 if (ret) 2709 if (ret)
2702 goto err0; 2710 goto err0;
2703 2711
2704 dep = dwc->eps[1]; 2712 dep = dwc->eps[1];
2705 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 2713 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2706 if (ret) 2714 if (ret)
2707 goto err1; 2715 goto err1;
2708 2716
2709 /* begin to receive SETUP packets */ 2717 /* begin to receive SETUP packets */
2710 dwc->ep0state = EP0_SETUP_PHASE; 2718 dwc->ep0state = EP0_SETUP_PHASE;
2711 dwc3_ep0_out_start(dwc); 2719 dwc3_ep0_out_start(dwc);
2712 2720
2713 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); 2721 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2714 2722
2715 return 0; 2723 return 0;
2716 2724
2717 err1: 2725 err1:
2718 __dwc3_gadget_ep_disable(dwc->eps[0]); 2726 __dwc3_gadget_ep_disable(dwc->eps[0]);
2719 2727
2720 err0: 2728 err0:
2721 return ret; 2729 return ret;
2722 } 2730 }
2723 2731
drivers/usb/dwc3/gadget.h
Diff comments   View file @ 55016b9
1 /** 1 /**
2 * gadget.h - DesignWare USB3 DRD Gadget Header 2 * gadget.h - DesignWare USB3 DRD Gadget Header
3 * 3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>, 6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 * 8 *
9 * This program is free software: you can redistribute it and/or modify 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of 10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation. 11 * the License as published by the Free Software Foundation.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 */ 17 */
18 18
19 #ifndef __DRIVERS_USB_DWC3_GADGET_H 19 #ifndef __DRIVERS_USB_DWC3_GADGET_H
20 #define __DRIVERS_USB_DWC3_GADGET_H 20 #define __DRIVERS_USB_DWC3_GADGET_H
21 21
22 #include <linux/list.h> 22 #include <linux/list.h>
23 #include <linux/usb/gadget.h> 23 #include <linux/usb/gadget.h>
24 #include "io.h" 24 #include "io.h"
25 25
26 struct dwc3; 26 struct dwc3;
27 #define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint)) 27 #define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
28 #define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget)) 28 #define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
29 29
30 /* DEPCFG parameter 1 */ 30 /* DEPCFG parameter 1 */
31 #define DWC3_DEPCFG_INT_NUM(n) ((n) << 0) 31 #define DWC3_DEPCFG_INT_NUM(n) ((n) << 0)
32 #define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8) 32 #define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8)
33 #define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9) 33 #define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
34 #define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10) 34 #define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10)
35 #define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11) 35 #define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11)
36 #define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13) 36 #define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13)
37 #define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16) 37 #define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
38 #define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24) 38 #define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24)
39 #define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25) 39 #define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25)
40 #define DWC3_DEPCFG_BULK_BASED (1 << 30) 40 #define DWC3_DEPCFG_BULK_BASED (1 << 30)
41 #define DWC3_DEPCFG_FIFO_BASED (1 << 31) 41 #define DWC3_DEPCFG_FIFO_BASED (1 << 31)
42 42
43 /* DEPCFG parameter 0 */ 43 /* DEPCFG parameter 0 */
44 #define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1) 44 #define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1)
45 #define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3) 45 #define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
46 #define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17) 46 #define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
47 #define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22) 47 #define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22)
48 #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) 48 #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
49 /* This applies for core versions earlier than 1.94a */ 49 /* This applies for core versions earlier than 1.94a */
50 #define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31) 50 #define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
51 /* These apply for core versions 1.94a and later */ 51 /* These apply for core versions 1.94a and later */
52 #define DWC3_DEPCFG_ACTION_INIT (0 << 30) 52 #define DWC3_DEPCFG_ACTION_INIT (0 << 30)
53 #define DWC3_DEPCFG_ACTION_RESTORE (1 << 30) 53 #define DWC3_DEPCFG_ACTION_RESTORE (1 << 30)
54 #define DWC3_DEPCFG_ACTION_MODIFY (2 << 30) 54 #define DWC3_DEPCFG_ACTION_MODIFY (2 << 30)
55 55
56 /* DEPXFERCFG parameter 0 */ 56 /* DEPXFERCFG parameter 0 */
57 #define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) 57 #define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
58 58
59 /* -------------------------------------------------------------------------- */ 59 /* -------------------------------------------------------------------------- */
60 60
61 #define to_dwc3_request(r) (container_of(r, struct dwc3_request, request)) 61 #define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
62 62
63 static inline struct dwc3_request *next_request(struct list_head *list) 63 static inline struct dwc3_request *next_request(struct list_head *list)
64 { 64 {
65 if (list_empty(list)) 65 if (list_empty(list))
66 return NULL; 66 return NULL;
67 67
68 return list_first_entry(list, struct dwc3_request, list); 68 return list_first_entry(list, struct dwc3_request, list);
69 } 69 }
70 70
71 static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req) 71 static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
72 { 72 {
73 struct dwc3_ep *dep = req->dep; 73 struct dwc3_ep *dep = req->dep;
74 74
75 req->queued = true; 75 req->queued = true;
76 list_move_tail(&req->list, &dep->req_queued); 76 list_move_tail(&req->list, &dep->req_queued);
77 } 77 }
78 78
79 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 79 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
80 int status); 80 int status);
81 81
82 void dwc3_ep0_interrupt(struct dwc3 *dwc, 82 void dwc3_ep0_interrupt(struct dwc3 *dwc,
83 const struct dwc3_event_depevt *event); 83 const struct dwc3_event_depevt *event);
84 void dwc3_ep0_out_start(struct dwc3 *dwc); 84 void dwc3_ep0_out_start(struct dwc3 *dwc);
85 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value); 85 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
86 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 86 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
87 gfp_t gfp_flags); 87 gfp_t gfp_flags);
88 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value); 88 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol);
89 89
90 /** 90 /**
91 * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW 91 * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
92 * @dwc: DesignWare USB3 Pointer 92 * @dwc: DesignWare USB3 Pointer
93 * @number: DWC endpoint number 93 * @number: DWC endpoint number
94 * 94 *
95 * Caller should take care of locking 95 * Caller should take care of locking
96 */ 96 */
97 static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number) 97 static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
98 { 98 {
99 u32 res_id; 99 u32 res_id;
100 100
101 res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number)); 101 res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
102 102
103 return DWC3_DEPCMD_GET_RSC_IDX(res_id); 103 return DWC3_DEPCMD_GET_RSC_IDX(res_id);
104 } 104 }
105 105
106 /** 106 /**
107 * dwc3_gadget_event_string - returns event name 107 * dwc3_gadget_event_string - returns event name
108 * @event: the event code 108 * @event: the event code
109 */ 109 */
110 static inline const char *dwc3_gadget_event_string(u8 event) 110 static inline const char *dwc3_gadget_event_string(u8 event)
111 { 111 {
112 switch (event) { 112 switch (event) {
113 case DWC3_DEVICE_EVENT_DISCONNECT: 113 case DWC3_DEVICE_EVENT_DISCONNECT:
114 return "Disconnect"; 114 return "Disconnect";
115 case DWC3_DEVICE_EVENT_RESET: 115 case DWC3_DEVICE_EVENT_RESET:
116 return "Reset"; 116 return "Reset";
117 case DWC3_DEVICE_EVENT_CONNECT_DONE: 117 case DWC3_DEVICE_EVENT_CONNECT_DONE:
118 return "Connection Done"; 118 return "Connection Done";
119 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 119 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
120 return "Link Status Change"; 120 return "Link Status Change";
121 case DWC3_DEVICE_EVENT_WAKEUP: 121 case DWC3_DEVICE_EVENT_WAKEUP:
122 return "WakeUp"; 122 return "WakeUp";
123 case DWC3_DEVICE_EVENT_EOPF: 123 case DWC3_DEVICE_EVENT_EOPF:
124 return "End-Of-Frame"; 124 return "End-Of-Frame";
125 case DWC3_DEVICE_EVENT_SOF: 125 case DWC3_DEVICE_EVENT_SOF:
126 return "Start-Of-Frame"; 126 return "Start-Of-Frame";
127 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 127 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
128 return "Erratic Error"; 128 return "Erratic Error";
129 case DWC3_DEVICE_EVENT_CMD_CMPL: 129 case DWC3_DEVICE_EVENT_CMD_CMPL:
130 return "Command Complete"; 130 return "Command Complete";
131 case DWC3_DEVICE_EVENT_OVERFLOW: 131 case DWC3_DEVICE_EVENT_OVERFLOW:
132 return "Overflow"; 132 return "Overflow";
133 } 133 }
134 134
135 return "UNKNOWN"; 135 return "UNKNOWN";
136 } 136 }
137 137
138 /** 138 /**
139 * dwc3_ep_event_string - returns event name 139 * dwc3_ep_event_string - returns event name
140 * @event: then event code 140 * @event: then event code
141 */ 141 */
142 static inline const char *dwc3_ep_event_string(u8 event) 142 static inline const char *dwc3_ep_event_string(u8 event)
143 { 143 {
144 switch (event) { 144 switch (event) {
145 case DWC3_DEPEVT_XFERCOMPLETE: 145 case DWC3_DEPEVT_XFERCOMPLETE:
146 return "Transfer Complete"; 146 return "Transfer Complete";
147 case DWC3_DEPEVT_XFERINPROGRESS: 147 case DWC3_DEPEVT_XFERINPROGRESS:
148 return "Transfer In-Progress"; 148 return "Transfer In-Progress";
149 case DWC3_DEPEVT_XFERNOTREADY: 149 case DWC3_DEPEVT_XFERNOTREADY:
150 return "Transfer Not Ready"; 150 return "Transfer Not Ready";
151 case DWC3_DEPEVT_RXTXFIFOEVT: 151 case DWC3_DEPEVT_RXTXFIFOEVT:
152 return "FIFO"; 152 return "FIFO";
153 case DWC3_DEPEVT_STREAMEVT: 153 case DWC3_DEPEVT_STREAMEVT:
154 return "Stream"; 154 return "Stream";
155 case DWC3_DEPEVT_EPCMDCMPLT: 155 case DWC3_DEPEVT_EPCMDCMPLT:
156 return "Endpoint Command Complete"; 156 return "Endpoint Command Complete";
157 } 157 }
158 158
159 return "UNKNOWN"; 159 return "UNKNOWN";
160 } 160 }
161 161
162 #endif /* __DRIVERS_USB_DWC3_GADGET_H */ 162 #endif /* __DRIVERS_USB_DWC3_GADGET_H */
163 163