Commit 5d6a54688632f640abda71164fea5d171ff07db8
Exists in
ti-lsk-linux-4.1.y
and in
10 other branches
Merge tag 'pm-config-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull CONFIG_PM_RUNTIME elimination from Rafael Wysocki: "This removes the last few uses of CONFIG_PM_RUNTIME introduced recently and makes that config option finally go away. CONFIG_PM will be available directly from the menu now and also it will be selected automatically if CONFIG_SUSPEND or CONFIG_HIBERNATION is set" * tag 'pm-config-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: PM: Eliminate CONFIG_PM_RUNTIME tty: 8250_omap: Replace CONFIG_PM_RUNTIME with CONFIG_PM sound: sst-haswell-pcm: Replace CONFIG_PM_RUNTIME with CONFIG_PM spi: Replace CONFIG_PM_RUNTIME with CONFIG_PM
Showing 41 changed files Inline Diff
- arch/arm/configs/ape6evm_defconfig
- arch/arm/configs/armadillo800eva_defconfig
- arch/arm/configs/bcm_defconfig
- arch/arm/configs/bockw_defconfig
- arch/arm/configs/davinci_all_defconfig
- arch/arm/configs/exynos_defconfig
- arch/arm/configs/ezx_defconfig
- arch/arm/configs/hisi_defconfig
- arch/arm/configs/imote2_defconfig
- arch/arm/configs/imx_v6_v7_defconfig
- arch/arm/configs/keystone_defconfig
- arch/arm/configs/kzm9g_defconfig
- arch/arm/configs/lager_defconfig
- arch/arm/configs/mackerel_defconfig
- arch/arm/configs/marzen_defconfig
- arch/arm/configs/omap1_defconfig
- arch/arm/configs/prima2_defconfig
- arch/arm/configs/sama5_defconfig
- arch/arm/configs/shmobile_defconfig
- arch/arm/configs/sunxi_defconfig
- arch/arm/configs/tegra_defconfig
- arch/arm/configs/u8500_defconfig
- arch/arm/configs/vt8500_v6_v7_defconfig
- arch/arm/mach-omap2/Kconfig
- arch/mips/configs/db1xxx_defconfig
- arch/mips/configs/lemote2f_defconfig
- arch/mips/configs/loongson3_defconfig
- arch/mips/configs/nlm_xlp_defconfig
- arch/mips/configs/nlm_xlr_defconfig
- arch/powerpc/configs/ps3_defconfig
- arch/sh/Kconfig
- arch/sh/configs/apsh4ad0a_defconfig
- arch/sh/configs/sdk7786_defconfig
- drivers/spi/spi-img-spfi.c
- drivers/spi/spi-meson-spifc.c
- drivers/tty/serial/8250/8250_omap.c
- drivers/usb/host/isp1760-hcd.c
- drivers/usb/host/oxu210hp-hcd.c
- include/linux/devfreq.h
- kernel/power/Kconfig
- sound/soc/intel/sst-haswell-pcm.c
arch/arm/configs/ape6evm_defconfig
| 1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 2 | CONFIG_POSIX_MQUEUE=y | 2 | CONFIG_POSIX_MQUEUE=y |
| 3 | CONFIG_NO_HZ=y | 3 | CONFIG_NO_HZ=y |
| 4 | CONFIG_HIGH_RES_TIMERS=y | 4 | CONFIG_HIGH_RES_TIMERS=y |
| 5 | CONFIG_BSD_PROCESS_ACCT=y | 5 | CONFIG_BSD_PROCESS_ACCT=y |
| 6 | CONFIG_IKCONFIG=y | 6 | CONFIG_IKCONFIG=y |
| 7 | CONFIG_IKCONFIG_PROC=y | 7 | CONFIG_IKCONFIG_PROC=y |
| 8 | CONFIG_LOG_BUF_SHIFT=16 | 8 | CONFIG_LOG_BUF_SHIFT=16 |
| 9 | CONFIG_CGROUPS=y | 9 | CONFIG_CGROUPS=y |
| 10 | CONFIG_CGROUP_SCHED=y | 10 | CONFIG_CGROUP_SCHED=y |
| 11 | CONFIG_KALLSYMS_ALL=y | 11 | CONFIG_KALLSYMS_ALL=y |
| 12 | CONFIG_EMBEDDED=y | 12 | CONFIG_EMBEDDED=y |
| 13 | CONFIG_PERF_EVENTS=y | 13 | CONFIG_PERF_EVENTS=y |
| 14 | CONFIG_SLAB=y | 14 | CONFIG_SLAB=y |
| 15 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 15 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 16 | CONFIG_ARCH_R8A73A4=y | 16 | CONFIG_ARCH_R8A73A4=y |
| 17 | CONFIG_MACH_APE6EVM=y | 17 | CONFIG_MACH_APE6EVM=y |
| 18 | # CONFIG_ARM_THUMB is not set | 18 | # CONFIG_ARM_THUMB is not set |
| 19 | CONFIG_CPU_BPREDICT_DISABLE=y | 19 | CONFIG_CPU_BPREDICT_DISABLE=y |
| 20 | CONFIG_PL310_ERRATA_588369=y | 20 | CONFIG_PL310_ERRATA_588369=y |
| 21 | CONFIG_ARM_ERRATA_754322=y | 21 | CONFIG_ARM_ERRATA_754322=y |
| 22 | CONFIG_SMP=y | 22 | CONFIG_SMP=y |
| 23 | CONFIG_SCHED_MC=y | 23 | CONFIG_SCHED_MC=y |
| 24 | CONFIG_HAVE_ARM_ARCH_TIMER=y | 24 | CONFIG_HAVE_ARM_ARCH_TIMER=y |
| 25 | CONFIG_NR_CPUS=8 | 25 | CONFIG_NR_CPUS=8 |
| 26 | CONFIG_AEABI=y | 26 | CONFIG_AEABI=y |
| 27 | CONFIG_HIGHMEM=y | 27 | CONFIG_HIGHMEM=y |
| 28 | CONFIG_HIGHPTE=y | 28 | CONFIG_HIGHPTE=y |
| 29 | # CONFIG_HW_PERF_EVENTS is not set | 29 | # CONFIG_HW_PERF_EVENTS is not set |
| 30 | # CONFIG_COMPACTION is not set | 30 | # CONFIG_COMPACTION is not set |
| 31 | # CONFIG_CROSS_MEMORY_ATTACH is not set | 31 | # CONFIG_CROSS_MEMORY_ATTACH is not set |
| 32 | CONFIG_ARM_APPENDED_DTB=y | 32 | CONFIG_ARM_APPENDED_DTB=y |
| 33 | CONFIG_VFP=y | 33 | CONFIG_VFP=y |
| 34 | CONFIG_NEON=y | 34 | CONFIG_NEON=y |
| 35 | CONFIG_BINFMT_MISC=y | 35 | CONFIG_BINFMT_MISC=y |
| 36 | CONFIG_PM_RUNTIME=y | 36 | CONFIG_PM=y |
| 37 | CONFIG_NET=y | 37 | CONFIG_NET=y |
| 38 | CONFIG_PACKET=y | 38 | CONFIG_PACKET=y |
| 39 | CONFIG_UNIX=y | 39 | CONFIG_UNIX=y |
| 40 | CONFIG_XFRM_USER=y | 40 | CONFIG_XFRM_USER=y |
| 41 | CONFIG_NET_KEY=y | 41 | CONFIG_NET_KEY=y |
| 42 | CONFIG_NET_KEY_MIGRATE=y | 42 | CONFIG_NET_KEY_MIGRATE=y |
| 43 | CONFIG_INET=y | 43 | CONFIG_INET=y |
| 44 | CONFIG_IP_MULTICAST=y | 44 | CONFIG_IP_MULTICAST=y |
| 45 | CONFIG_IP_PNP=y | 45 | CONFIG_IP_PNP=y |
| 46 | CONFIG_IP_PNP_DHCP=y | 46 | CONFIG_IP_PNP_DHCP=y |
| 47 | # CONFIG_INET_LRO is not set | 47 | # CONFIG_INET_LRO is not set |
| 48 | # CONFIG_IPV6_SIT is not set | 48 | # CONFIG_IPV6_SIT is not set |
| 49 | CONFIG_NETFILTER=y | 49 | CONFIG_NETFILTER=y |
| 50 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 50 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 51 | CONFIG_DEVTMPFS=y | 51 | CONFIG_DEVTMPFS=y |
| 52 | CONFIG_DEVTMPFS_MOUNT=y | 52 | CONFIG_DEVTMPFS_MOUNT=y |
| 53 | # CONFIG_FW_LOADER_USER_HELPER is not set | 53 | # CONFIG_FW_LOADER_USER_HELPER is not set |
| 54 | CONFIG_NETDEVICES=y | 54 | CONFIG_NETDEVICES=y |
| 55 | # CONFIG_NET_CADENCE is not set | 55 | # CONFIG_NET_CADENCE is not set |
| 56 | CONFIG_SMC91X=y | 56 | CONFIG_SMC91X=y |
| 57 | CONFIG_SMSC911X=y | 57 | CONFIG_SMSC911X=y |
| 58 | # CONFIG_INPUT_MOUSEDEV is not set | 58 | # CONFIG_INPUT_MOUSEDEV is not set |
| 59 | CONFIG_INPUT_EVDEV=y | 59 | CONFIG_INPUT_EVDEV=y |
| 60 | CONFIG_KEYBOARD_GPIO=y | 60 | CONFIG_KEYBOARD_GPIO=y |
| 61 | # CONFIG_INPUT_MOUSE is not set | 61 | # CONFIG_INPUT_MOUSE is not set |
| 62 | # CONFIG_SERIO is not set | 62 | # CONFIG_SERIO is not set |
| 63 | CONFIG_SERIAL_NONSTANDARD=y | 63 | CONFIG_SERIAL_NONSTANDARD=y |
| 64 | CONFIG_SERIAL_SH_SCI=y | 64 | CONFIG_SERIAL_SH_SCI=y |
| 65 | CONFIG_SERIAL_SH_SCI_NR_UARTS=12 | 65 | CONFIG_SERIAL_SH_SCI_NR_UARTS=12 |
| 66 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 66 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 67 | CONFIG_I2C=y | 67 | CONFIG_I2C=y |
| 68 | CONFIG_I2C_SH_MOBILE=y | 68 | CONFIG_I2C_SH_MOBILE=y |
| 69 | CONFIG_GPIO_SH_PFC=y | 69 | CONFIG_GPIO_SH_PFC=y |
| 70 | CONFIG_GPIOLIB=y | 70 | CONFIG_GPIOLIB=y |
| 71 | # CONFIG_HWMON is not set | 71 | # CONFIG_HWMON is not set |
| 72 | CONFIG_THERMAL=y | 72 | CONFIG_THERMAL=y |
| 73 | CONFIG_RCAR_THERMAL=y | 73 | CONFIG_RCAR_THERMAL=y |
| 74 | CONFIG_REGULATOR=y | 74 | CONFIG_REGULATOR=y |
| 75 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 75 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 76 | CONFIG_REGULATOR_GPIO=y | 76 | CONFIG_REGULATOR_GPIO=y |
| 77 | CONFIG_REGULATOR_MAX8973=y | 77 | CONFIG_REGULATOR_MAX8973=y |
| 78 | # CONFIG_HID is not set | 78 | # CONFIG_HID is not set |
| 79 | # CONFIG_USB_SUPPORT is not set | 79 | # CONFIG_USB_SUPPORT is not set |
| 80 | CONFIG_MMC=y | 80 | CONFIG_MMC=y |
| 81 | CONFIG_MMC_SDHI=y | 81 | CONFIG_MMC_SDHI=y |
| 82 | CONFIG_MMC_SH_MMCIF=y | 82 | CONFIG_MMC_SH_MMCIF=y |
| 83 | CONFIG_NEW_LEDS=y | 83 | CONFIG_NEW_LEDS=y |
| 84 | CONFIG_LEDS_CLASS=y | 84 | CONFIG_LEDS_CLASS=y |
| 85 | CONFIG_LEDS_GPIO=y | 85 | CONFIG_LEDS_GPIO=y |
| 86 | CONFIG_DMADEVICES=y | 86 | CONFIG_DMADEVICES=y |
| 87 | CONFIG_SH_DMAE=y | 87 | CONFIG_SH_DMAE=y |
| 88 | # CONFIG_IOMMU_SUPPORT is not set | 88 | # CONFIG_IOMMU_SUPPORT is not set |
| 89 | # CONFIG_DNOTIFY is not set | 89 | # CONFIG_DNOTIFY is not set |
| 90 | CONFIG_TMPFS=y | 90 | CONFIG_TMPFS=y |
| 91 | # CONFIG_MISC_FILESYSTEMS is not set | 91 | # CONFIG_MISC_FILESYSTEMS is not set |
| 92 | CONFIG_NFS_FS=y | 92 | CONFIG_NFS_FS=y |
| 93 | CONFIG_NFS_V3_ACL=y | 93 | CONFIG_NFS_V3_ACL=y |
| 94 | CONFIG_NFS_V4=y | 94 | CONFIG_NFS_V4=y |
| 95 | CONFIG_NFS_V4_1=y | 95 | CONFIG_NFS_V4_1=y |
| 96 | CONFIG_ROOT_NFS=y | 96 | CONFIG_ROOT_NFS=y |
| 97 | CONFIG_MAGIC_SYSRQ=y | 97 | CONFIG_MAGIC_SYSRQ=y |
| 98 | CONFIG_ENABLE_DEFAULT_TRACERS=y | 98 | CONFIG_ENABLE_DEFAULT_TRACERS=y |
| 99 | CONFIG_CRYPTO_CBC=y | 99 | CONFIG_CRYPTO_CBC=y |
| 100 | CONFIG_CRYPTO_ECB=y | 100 | CONFIG_CRYPTO_ECB=y |
| 101 | CONFIG_CRYPTO_MD5=y | 101 | CONFIG_CRYPTO_MD5=y |
| 102 | CONFIG_CRYPTO_MICHAEL_MIC=y | 102 | CONFIG_CRYPTO_MICHAEL_MIC=y |
| 103 | CONFIG_CRYPTO_TWOFISH=y | 103 | CONFIG_CRYPTO_TWOFISH=y |
| 104 | CONFIG_CRC_CCITT=y | 104 | CONFIG_CRC_CCITT=y |
| 105 | CONFIG_CRC16=y | 105 | CONFIG_CRC16=y |
| 106 | CONFIG_CRC_T10DIF=y | 106 | CONFIG_CRC_T10DIF=y |
| 107 | CONFIG_CRC_ITU_T=y | 107 | CONFIG_CRC_ITU_T=y |
| 108 | CONFIG_CRC7=y | 108 | CONFIG_CRC7=y |
| 109 | CONFIG_LIBCRC32C=y | 109 | CONFIG_LIBCRC32C=y |
| 110 | 110 |
arch/arm/configs/armadillo800eva_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
| 4 | CONFIG_IKCONFIG_PROC=y | 4 | CONFIG_IKCONFIG_PROC=y |
| 5 | CONFIG_LOG_BUF_SHIFT=16 | 5 | CONFIG_LOG_BUF_SHIFT=16 |
| 6 | # CONFIG_UTS_NS is not set | 6 | # CONFIG_UTS_NS is not set |
| 7 | # CONFIG_IPC_NS is not set | 7 | # CONFIG_IPC_NS is not set |
| 8 | # CONFIG_PID_NS is not set | 8 | # CONFIG_PID_NS is not set |
| 9 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 9 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 10 | CONFIG_PERF_EVENTS=y | 10 | CONFIG_PERF_EVENTS=y |
| 11 | CONFIG_SLAB=y | 11 | CONFIG_SLAB=y |
| 12 | CONFIG_MODULES=y | 12 | CONFIG_MODULES=y |
| 13 | CONFIG_MODULE_UNLOAD=y | 13 | CONFIG_MODULE_UNLOAD=y |
| 14 | CONFIG_MODULE_FORCE_UNLOAD=y | 14 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 15 | # CONFIG_BLK_DEV_BSG is not set | 15 | # CONFIG_BLK_DEV_BSG is not set |
| 16 | # CONFIG_IOSCHED_DEADLINE is not set | 16 | # CONFIG_IOSCHED_DEADLINE is not set |
| 17 | # CONFIG_IOSCHED_CFQ is not set | 17 | # CONFIG_IOSCHED_CFQ is not set |
| 18 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 18 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 19 | CONFIG_ARCH_R8A7740=y | 19 | CONFIG_ARCH_R8A7740=y |
| 20 | CONFIG_MACH_ARMADILLO800EVA=y | 20 | CONFIG_MACH_ARMADILLO800EVA=y |
| 21 | # CONFIG_SH_TIMER_TMU is not set | 21 | # CONFIG_SH_TIMER_TMU is not set |
| 22 | CONFIG_ARM_THUMB=y | 22 | CONFIG_ARM_THUMB=y |
| 23 | CONFIG_CACHE_L2X0=y | 23 | CONFIG_CACHE_L2X0=y |
| 24 | CONFIG_ARM_ERRATA_430973=y | 24 | CONFIG_ARM_ERRATA_430973=y |
| 25 | CONFIG_ARM_ERRATA_458693=y | 25 | CONFIG_ARM_ERRATA_458693=y |
| 26 | CONFIG_ARM_ERRATA_460075=y | 26 | CONFIG_ARM_ERRATA_460075=y |
| 27 | CONFIG_PL310_ERRATA_588369=y | 27 | CONFIG_PL310_ERRATA_588369=y |
| 28 | CONFIG_ARM_ERRATA_720789=y | 28 | CONFIG_ARM_ERRATA_720789=y |
| 29 | CONFIG_PL310_ERRATA_727915=y | 29 | CONFIG_PL310_ERRATA_727915=y |
| 30 | CONFIG_ARM_ERRATA_743622=y | 30 | CONFIG_ARM_ERRATA_743622=y |
| 31 | CONFIG_ARM_ERRATA_751472=y | 31 | CONFIG_ARM_ERRATA_751472=y |
| 32 | CONFIG_PL310_ERRATA_753970=y | 32 | CONFIG_PL310_ERRATA_753970=y |
| 33 | CONFIG_ARM_ERRATA_754322=y | 33 | CONFIG_ARM_ERRATA_754322=y |
| 34 | CONFIG_PL310_ERRATA_769419=y | 34 | CONFIG_PL310_ERRATA_769419=y |
| 35 | CONFIG_ARM_ERRATA_775420=y | 35 | CONFIG_ARM_ERRATA_775420=y |
| 36 | CONFIG_AEABI=y | 36 | CONFIG_AEABI=y |
| 37 | # CONFIG_OABI_COMPAT is not set | 37 | # CONFIG_OABI_COMPAT is not set |
| 38 | CONFIG_FORCE_MAX_ZONEORDER=13 | 38 | CONFIG_FORCE_MAX_ZONEORDER=13 |
| 39 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 39 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 40 | CONFIG_ZBOOT_ROM_BSS=0x0 | 40 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 41 | CONFIG_ARM_APPENDED_DTB=y | 41 | CONFIG_ARM_APPENDED_DTB=y |
| 42 | CONFIG_KEXEC=y | 42 | CONFIG_KEXEC=y |
| 43 | CONFIG_VFP=y | 43 | CONFIG_VFP=y |
| 44 | CONFIG_NEON=y | 44 | CONFIG_NEON=y |
| 45 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 45 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 46 | CONFIG_PM_RUNTIME=y | 46 | CONFIG_PM=y |
| 47 | CONFIG_NET=y | 47 | CONFIG_NET=y |
| 48 | CONFIG_PACKET=y | 48 | CONFIG_PACKET=y |
| 49 | CONFIG_UNIX=y | 49 | CONFIG_UNIX=y |
| 50 | CONFIG_INET=y | 50 | CONFIG_INET=y |
| 51 | CONFIG_IP_PNP=y | 51 | CONFIG_IP_PNP=y |
| 52 | CONFIG_IP_PNP_DHCP=y | 52 | CONFIG_IP_PNP_DHCP=y |
| 53 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 53 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 54 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 54 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 55 | # CONFIG_INET_XFRM_MODE_BEET is not set | 55 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 56 | # CONFIG_INET_LRO is not set | 56 | # CONFIG_INET_LRO is not set |
| 57 | # CONFIG_INET_DIAG is not set | 57 | # CONFIG_INET_DIAG is not set |
| 58 | # CONFIG_IPV6 is not set | 58 | # CONFIG_IPV6 is not set |
| 59 | # CONFIG_WIRELESS is not set | 59 | # CONFIG_WIRELESS is not set |
| 60 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 60 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 61 | CONFIG_DEVTMPFS=y | 61 | CONFIG_DEVTMPFS=y |
| 62 | CONFIG_DEVTMPFS_MOUNT=y | 62 | CONFIG_DEVTMPFS_MOUNT=y |
| 63 | CONFIG_SCSI=y | 63 | CONFIG_SCSI=y |
| 64 | CONFIG_BLK_DEV_SD=y | 64 | CONFIG_BLK_DEV_SD=y |
| 65 | CONFIG_MD=y | 65 | CONFIG_MD=y |
| 66 | CONFIG_BLK_DEV_DM=y | 66 | CONFIG_BLK_DEV_DM=y |
| 67 | CONFIG_NETDEVICES=y | 67 | CONFIG_NETDEVICES=y |
| 68 | # CONFIG_NET_VENDOR_BROADCOM is not set | 68 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 69 | # CONFIG_NET_VENDOR_CHELSIO is not set | 69 | # CONFIG_NET_VENDOR_CHELSIO is not set |
| 70 | # CONFIG_NET_VENDOR_CIRRUS is not set | 70 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 71 | # CONFIG_NET_VENDOR_FARADAY is not set | 71 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 72 | # CONFIG_NET_VENDOR_INTEL is not set | 72 | # CONFIG_NET_VENDOR_INTEL is not set |
| 73 | # CONFIG_NET_VENDOR_MARVELL is not set | 73 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 74 | # CONFIG_NET_VENDOR_MICREL is not set | 74 | # CONFIG_NET_VENDOR_MICREL is not set |
| 75 | # CONFIG_NET_VENDOR_NATSEMI is not set | 75 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 76 | CONFIG_SH_ETH=y | 76 | CONFIG_SH_ETH=y |
| 77 | # CONFIG_NET_VENDOR_SEEQ is not set | 77 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 78 | # CONFIG_NET_VENDOR_SMSC is not set | 78 | # CONFIG_NET_VENDOR_SMSC is not set |
| 79 | # CONFIG_NET_VENDOR_STMICRO is not set | 79 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 80 | # CONFIG_WLAN is not set | 80 | # CONFIG_WLAN is not set |
| 81 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 81 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 82 | CONFIG_INPUT_EVDEV=y | 82 | CONFIG_INPUT_EVDEV=y |
| 83 | # CONFIG_KEYBOARD_ATKBD is not set | 83 | # CONFIG_KEYBOARD_ATKBD is not set |
| 84 | CONFIG_KEYBOARD_GPIO=y | 84 | CONFIG_KEYBOARD_GPIO=y |
| 85 | # CONFIG_INPUT_MOUSE is not set | 85 | # CONFIG_INPUT_MOUSE is not set |
| 86 | CONFIG_INPUT_TOUCHSCREEN=y | 86 | CONFIG_INPUT_TOUCHSCREEN=y |
| 87 | CONFIG_TOUCHSCREEN_ST1232=y | 87 | CONFIG_TOUCHSCREEN_ST1232=y |
| 88 | # CONFIG_SERIO is not set | 88 | # CONFIG_SERIO is not set |
| 89 | # CONFIG_LEGACY_PTYS is not set | 89 | # CONFIG_LEGACY_PTYS is not set |
| 90 | CONFIG_SERIAL_SH_SCI=y | 90 | CONFIG_SERIAL_SH_SCI=y |
| 91 | CONFIG_SERIAL_SH_SCI_NR_UARTS=9 | 91 | CONFIG_SERIAL_SH_SCI_NR_UARTS=9 |
| 92 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 92 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 93 | # CONFIG_HW_RANDOM is not set | 93 | # CONFIG_HW_RANDOM is not set |
| 94 | CONFIG_I2C=y | 94 | CONFIG_I2C=y |
| 95 | CONFIG_I2C_GPIO=y | 95 | CONFIG_I2C_GPIO=y |
| 96 | CONFIG_I2C_SH_MOBILE=y | 96 | CONFIG_I2C_SH_MOBILE=y |
| 97 | # CONFIG_HWMON is not set | 97 | # CONFIG_HWMON is not set |
| 98 | CONFIG_REGULATOR=y | 98 | CONFIG_REGULATOR=y |
| 99 | CONFIG_REGULATOR_GPIO=y | 99 | CONFIG_REGULATOR_GPIO=y |
| 100 | CONFIG_MEDIA_SUPPORT=y | 100 | CONFIG_MEDIA_SUPPORT=y |
| 101 | CONFIG_VIDEO_DEV=y | 101 | CONFIG_VIDEO_DEV=y |
| 102 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 102 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 103 | CONFIG_V4L_PLATFORM_DRIVERS=y | 103 | CONFIG_V4L_PLATFORM_DRIVERS=y |
| 104 | CONFIG_SOC_CAMERA=y | 104 | CONFIG_SOC_CAMERA=y |
| 105 | CONFIG_SOC_CAMERA_MT9T112=y | 105 | CONFIG_SOC_CAMERA_MT9T112=y |
| 106 | CONFIG_VIDEO_SH_MOBILE_CEU=y | 106 | CONFIG_VIDEO_SH_MOBILE_CEU=y |
| 107 | CONFIG_FB=y | 107 | CONFIG_FB=y |
| 108 | CONFIG_FB_SH_MOBILE_LCDC=y | 108 | CONFIG_FB_SH_MOBILE_LCDC=y |
| 109 | CONFIG_FB_SH_MOBILE_HDMI=y | 109 | CONFIG_FB_SH_MOBILE_HDMI=y |
| 110 | CONFIG_LCD_CLASS_DEVICE=y | 110 | CONFIG_LCD_CLASS_DEVICE=y |
| 111 | CONFIG_BACKLIGHT_PWM=y | 111 | CONFIG_BACKLIGHT_PWM=y |
| 112 | CONFIG_FRAMEBUFFER_CONSOLE=y | 112 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 113 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | 113 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y |
| 114 | CONFIG_LOGO=y | 114 | CONFIG_LOGO=y |
| 115 | # CONFIG_LOGO_LINUX_MONO is not set | 115 | # CONFIG_LOGO_LINUX_MONO is not set |
| 116 | # CONFIG_LOGO_LINUX_VGA16 is not set | 116 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 117 | # CONFIG_SND_SUPPORT_OLD_API is not set | 117 | # CONFIG_SND_SUPPORT_OLD_API is not set |
| 118 | # CONFIG_SND_VERBOSE_PROCFS is not set | 118 | # CONFIG_SND_VERBOSE_PROCFS is not set |
| 119 | # CONFIG_SND_DRIVERS is not set | 119 | # CONFIG_SND_DRIVERS is not set |
| 120 | # CONFIG_SND_ARM is not set | 120 | # CONFIG_SND_ARM is not set |
| 121 | CONFIG_SND_SOC_SH4_FSI=y | 121 | CONFIG_SND_SOC_SH4_FSI=y |
| 122 | # CONFIG_HID_SUPPORT is not set | 122 | # CONFIG_HID_SUPPORT is not set |
| 123 | CONFIG_USB=y | 123 | CONFIG_USB=y |
| 124 | CONFIG_USB_RENESAS_USBHS=y | 124 | CONFIG_USB_RENESAS_USBHS=y |
| 125 | CONFIG_USB_GADGET=y | 125 | CONFIG_USB_GADGET=y |
| 126 | CONFIG_USB_RENESAS_USBHS_UDC=y | 126 | CONFIG_USB_RENESAS_USBHS_UDC=y |
| 127 | CONFIG_USB_ETH=m | 127 | CONFIG_USB_ETH=m |
| 128 | CONFIG_MMC=y | 128 | CONFIG_MMC=y |
| 129 | CONFIG_MMC_SDHI=y | 129 | CONFIG_MMC_SDHI=y |
| 130 | CONFIG_MMC_SH_MMCIF=y | 130 | CONFIG_MMC_SH_MMCIF=y |
| 131 | CONFIG_NEW_LEDS=y | 131 | CONFIG_NEW_LEDS=y |
| 132 | CONFIG_LEDS_CLASS=y | 132 | CONFIG_LEDS_CLASS=y |
| 133 | CONFIG_LEDS_GPIO=y | 133 | CONFIG_LEDS_GPIO=y |
| 134 | CONFIG_RTC_CLASS=y | 134 | CONFIG_RTC_CLASS=y |
| 135 | CONFIG_RTC_DRV_S35390A=y | 135 | CONFIG_RTC_DRV_S35390A=y |
| 136 | CONFIG_DMADEVICES=y | 136 | CONFIG_DMADEVICES=y |
| 137 | CONFIG_SH_DMAE=y | 137 | CONFIG_SH_DMAE=y |
| 138 | CONFIG_UIO=y | 138 | CONFIG_UIO=y |
| 139 | CONFIG_UIO_PDRV_GENIRQ=y | 139 | CONFIG_UIO_PDRV_GENIRQ=y |
| 140 | CONFIG_PWM=y | 140 | CONFIG_PWM=y |
| 141 | CONFIG_PWM_RENESAS_TPU=y | 141 | CONFIG_PWM_RENESAS_TPU=y |
| 142 | # CONFIG_DNOTIFY is not set | 142 | # CONFIG_DNOTIFY is not set |
| 143 | CONFIG_MSDOS_FS=y | 143 | CONFIG_MSDOS_FS=y |
| 144 | CONFIG_VFAT_FS=y | 144 | CONFIG_VFAT_FS=y |
| 145 | CONFIG_TMPFS=y | 145 | CONFIG_TMPFS=y |
| 146 | # CONFIG_MISC_FILESYSTEMS is not set | 146 | # CONFIG_MISC_FILESYSTEMS is not set |
| 147 | CONFIG_NFS_FS=y | 147 | CONFIG_NFS_FS=y |
| 148 | CONFIG_NFS_V3_ACL=y | 148 | CONFIG_NFS_V3_ACL=y |
| 149 | CONFIG_NFS_V4=y | 149 | CONFIG_NFS_V4=y |
| 150 | CONFIG_NFS_V4_1=y | 150 | CONFIG_NFS_V4_1=y |
| 151 | CONFIG_ROOT_NFS=y | 151 | CONFIG_ROOT_NFS=y |
| 152 | CONFIG_NLS_CODEPAGE_437=y | 152 | CONFIG_NLS_CODEPAGE_437=y |
| 153 | CONFIG_NLS_ISO8859_1=y | 153 | CONFIG_NLS_ISO8859_1=y |
| 154 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 154 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 155 | # CONFIG_ENABLE_MUST_CHECK is not set | 155 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 156 | # CONFIG_ARM_UNWIND is not set | 156 | # CONFIG_ARM_UNWIND is not set |
| 157 | CONFIG_CRYPTO=y | 157 | CONFIG_CRYPTO=y |
| 158 | CONFIG_CRYPTO_CBC=y | 158 | CONFIG_CRYPTO_CBC=y |
| 159 | CONFIG_CRYPTO_MD5=y | 159 | CONFIG_CRYPTO_MD5=y |
| 160 | CONFIG_CRYPTO_DES=y | 160 | CONFIG_CRYPTO_DES=y |
| 161 | CONFIG_CRYPTO_ANSI_CPRNG=y | 161 | CONFIG_CRYPTO_ANSI_CPRNG=y |
| 162 | CONFIG_XZ_DEC=y | 162 | CONFIG_XZ_DEC=y |
| 163 | 163 |
arch/arm/configs/bcm_defconfig
| 1 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 2 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_NO_HZ=y | 4 | CONFIG_NO_HZ=y |
| 5 | CONFIG_HIGH_RES_TIMERS=y | 5 | CONFIG_HIGH_RES_TIMERS=y |
| 6 | CONFIG_BSD_PROCESS_ACCT=y | 6 | CONFIG_BSD_PROCESS_ACCT=y |
| 7 | CONFIG_BSD_PROCESS_ACCT_V3=y | 7 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 8 | CONFIG_IKCONFIG=y | 8 | CONFIG_IKCONFIG=y |
| 9 | CONFIG_IKCONFIG_PROC=y | 9 | CONFIG_IKCONFIG_PROC=y |
| 10 | CONFIG_LOG_BUF_SHIFT=19 | 10 | CONFIG_LOG_BUF_SHIFT=19 |
| 11 | CONFIG_CGROUPS=y | 11 | CONFIG_CGROUPS=y |
| 12 | CONFIG_CGROUP_FREEZER=y | 12 | CONFIG_CGROUP_FREEZER=y |
| 13 | CONFIG_CGROUP_DEVICE=y | 13 | CONFIG_CGROUP_DEVICE=y |
| 14 | CONFIG_CGROUP_CPUACCT=y | 14 | CONFIG_CGROUP_CPUACCT=y |
| 15 | CONFIG_RESOURCE_COUNTERS=y | 15 | CONFIG_RESOURCE_COUNTERS=y |
| 16 | CONFIG_CGROUP_SCHED=y | 16 | CONFIG_CGROUP_SCHED=y |
| 17 | CONFIG_BLK_CGROUP=y | 17 | CONFIG_BLK_CGROUP=y |
| 18 | CONFIG_NAMESPACES=y | 18 | CONFIG_NAMESPACES=y |
| 19 | CONFIG_BLK_DEV_INITRD=y | 19 | CONFIG_BLK_DEV_INITRD=y |
| 20 | CONFIG_SYSCTL_SYSCALL=y | 20 | CONFIG_SYSCTL_SYSCALL=y |
| 21 | CONFIG_EMBEDDED=y | 21 | CONFIG_EMBEDDED=y |
| 22 | # CONFIG_COMPAT_BRK is not set | 22 | # CONFIG_COMPAT_BRK is not set |
| 23 | CONFIG_MODULES=y | 23 | CONFIG_MODULES=y |
| 24 | CONFIG_MODULE_UNLOAD=y | 24 | CONFIG_MODULE_UNLOAD=y |
| 25 | # CONFIG_BLK_DEV_BSG is not set | 25 | # CONFIG_BLK_DEV_BSG is not set |
| 26 | CONFIG_PARTITION_ADVANCED=y | 26 | CONFIG_PARTITION_ADVANCED=y |
| 27 | CONFIG_ARCH_BCM=y | 27 | CONFIG_ARCH_BCM=y |
| 28 | CONFIG_ARCH_BCM_21664=y | 28 | CONFIG_ARCH_BCM_21664=y |
| 29 | CONFIG_ARCH_BCM_281XX=y | 29 | CONFIG_ARCH_BCM_281XX=y |
| 30 | CONFIG_ARM_THUMBEE=y | 30 | CONFIG_ARM_THUMBEE=y |
| 31 | CONFIG_SMP=y | 31 | CONFIG_SMP=y |
| 32 | CONFIG_PREEMPT=y | 32 | CONFIG_PREEMPT=y |
| 33 | CONFIG_AEABI=y | 33 | CONFIG_AEABI=y |
| 34 | # CONFIG_COMPACTION is not set | 34 | # CONFIG_COMPACTION is not set |
| 35 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 35 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 36 | CONFIG_ZBOOT_ROM_BSS=0x0 | 36 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 37 | CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M" | 37 | CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M" |
| 38 | CONFIG_CPU_IDLE=y | 38 | CONFIG_CPU_IDLE=y |
| 39 | CONFIG_VFP=y | 39 | CONFIG_VFP=y |
| 40 | CONFIG_NEON=y | 40 | CONFIG_NEON=y |
| 41 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 41 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 42 | CONFIG_PM_RUNTIME=y | 42 | CONFIG_PM=y |
| 43 | CONFIG_NET=y | 43 | CONFIG_NET=y |
| 44 | CONFIG_PACKET=y | 44 | CONFIG_PACKET=y |
| 45 | CONFIG_PACKET_DIAG=y | 45 | CONFIG_PACKET_DIAG=y |
| 46 | CONFIG_UNIX=y | 46 | CONFIG_UNIX=y |
| 47 | CONFIG_UNIX_DIAG=y | 47 | CONFIG_UNIX_DIAG=y |
| 48 | CONFIG_NET_KEY=y | 48 | CONFIG_NET_KEY=y |
| 49 | CONFIG_INET=y | 49 | CONFIG_INET=y |
| 50 | CONFIG_IP_MULTICAST=y | 50 | CONFIG_IP_MULTICAST=y |
| 51 | CONFIG_SYN_COOKIES=y | 51 | CONFIG_SYN_COOKIES=y |
| 52 | CONFIG_TCP_MD5SIG=y | 52 | CONFIG_TCP_MD5SIG=y |
| 53 | CONFIG_IPV6=y | 53 | CONFIG_IPV6=y |
| 54 | CONFIG_DEVTMPFS=y | 54 | CONFIG_DEVTMPFS=y |
| 55 | CONFIG_DEVTMPFS_MOUNT=y | 55 | CONFIG_DEVTMPFS_MOUNT=y |
| 56 | CONFIG_PROC_DEVICETREE=y | 56 | CONFIG_PROC_DEVICETREE=y |
| 57 | # CONFIG_BLK_DEV is not set | 57 | # CONFIG_BLK_DEV is not set |
| 58 | CONFIG_SCSI=y | 58 | CONFIG_SCSI=y |
| 59 | CONFIG_BLK_DEV_SD=y | 59 | CONFIG_BLK_DEV_SD=y |
| 60 | CONFIG_CHR_DEV_SG=y | 60 | CONFIG_CHR_DEV_SG=y |
| 61 | CONFIG_SCSI_MULTI_LUN=y | 61 | CONFIG_SCSI_MULTI_LUN=y |
| 62 | CONFIG_SCSI_SCAN_ASYNC=y | 62 | CONFIG_SCSI_SCAN_ASYNC=y |
| 63 | CONFIG_INPUT_FF_MEMLESS=y | 63 | CONFIG_INPUT_FF_MEMLESS=y |
| 64 | CONFIG_INPUT_JOYDEV=y | 64 | CONFIG_INPUT_JOYDEV=y |
| 65 | CONFIG_INPUT_EVDEV=y | 65 | CONFIG_INPUT_EVDEV=y |
| 66 | # CONFIG_KEYBOARD_ATKBD is not set | 66 | # CONFIG_KEYBOARD_ATKBD is not set |
| 67 | # CONFIG_INPUT_MOUSE is not set | 67 | # CONFIG_INPUT_MOUSE is not set |
| 68 | CONFIG_INPUT_TOUCHSCREEN=y | 68 | CONFIG_INPUT_TOUCHSCREEN=y |
| 69 | CONFIG_INPUT_MISC=y | 69 | CONFIG_INPUT_MISC=y |
| 70 | CONFIG_INPUT_UINPUT=y | 70 | CONFIG_INPUT_UINPUT=y |
| 71 | # CONFIG_SERIO is not set | 71 | # CONFIG_SERIO is not set |
| 72 | # CONFIG_LEGACY_PTYS is not set | 72 | # CONFIG_LEGACY_PTYS is not set |
| 73 | CONFIG_SERIAL_8250=y | 73 | CONFIG_SERIAL_8250=y |
| 74 | CONFIG_SERIAL_8250_CONSOLE=y | 74 | CONFIG_SERIAL_8250_CONSOLE=y |
| 75 | CONFIG_SERIAL_8250_EXTENDED=y | 75 | CONFIG_SERIAL_8250_EXTENDED=y |
| 76 | CONFIG_SERIAL_8250_MANY_PORTS=y | 76 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 77 | CONFIG_SERIAL_8250_SHARE_IRQ=y | 77 | CONFIG_SERIAL_8250_SHARE_IRQ=y |
| 78 | CONFIG_SERIAL_8250_RSA=y | 78 | CONFIG_SERIAL_8250_RSA=y |
| 79 | CONFIG_SERIAL_8250_DW=y | 79 | CONFIG_SERIAL_8250_DW=y |
| 80 | CONFIG_HW_RANDOM=y | 80 | CONFIG_HW_RANDOM=y |
| 81 | CONFIG_I2C=y | 81 | CONFIG_I2C=y |
| 82 | CONFIG_I2C_CHARDEV=y | 82 | CONFIG_I2C_CHARDEV=y |
| 83 | # CONFIG_HWMON is not set | 83 | # CONFIG_HWMON is not set |
| 84 | CONFIG_MFD_BCM590XX=y | 84 | CONFIG_MFD_BCM590XX=y |
| 85 | CONFIG_REGULATOR=y | 85 | CONFIG_REGULATOR=y |
| 86 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 86 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 87 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y | 87 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y |
| 88 | CONFIG_REGULATOR_BCM590XX=y | 88 | CONFIG_REGULATOR_BCM590XX=y |
| 89 | 89 | ||
| 90 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 90 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 91 | CONFIG_FB=y | 91 | CONFIG_FB=y |
| 92 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 92 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 93 | CONFIG_LCD_CLASS_DEVICE=y | 93 | CONFIG_LCD_CLASS_DEVICE=y |
| 94 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 94 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 95 | CONFIG_BACKLIGHT_PWM=y | 95 | CONFIG_BACKLIGHT_PWM=y |
| 96 | # CONFIG_USB_SUPPORT is not set | 96 | # CONFIG_USB_SUPPORT is not set |
| 97 | CONFIG_MMC=y | 97 | CONFIG_MMC=y |
| 98 | CONFIG_MMC_BLOCK_MINORS=32 | 98 | CONFIG_MMC_BLOCK_MINORS=32 |
| 99 | CONFIG_MMC_TEST=y | 99 | CONFIG_MMC_TEST=y |
| 100 | CONFIG_MMC_SDHCI=y | 100 | CONFIG_MMC_SDHCI=y |
| 101 | CONFIG_MMC_SDHCI_PLTFM=y | 101 | CONFIG_MMC_SDHCI_PLTFM=y |
| 102 | CONFIG_MMC_SDHCI_BCM_KONA=y | 102 | CONFIG_MMC_SDHCI_BCM_KONA=y |
| 103 | CONFIG_NEW_LEDS=y | 103 | CONFIG_NEW_LEDS=y |
| 104 | CONFIG_LEDS_CLASS=y | 104 | CONFIG_LEDS_CLASS=y |
| 105 | CONFIG_LEDS_TRIGGERS=y | 105 | CONFIG_LEDS_TRIGGERS=y |
| 106 | CONFIG_LEDS_TRIGGER_TIMER=y | 106 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 107 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 107 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 108 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 108 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 109 | CONFIG_PWM=y | 109 | CONFIG_PWM=y |
| 110 | CONFIG_PWM_BCM_KONA=y | 110 | CONFIG_PWM_BCM_KONA=y |
| 111 | CONFIG_EXT4_FS=y | 111 | CONFIG_EXT4_FS=y |
| 112 | CONFIG_EXT4_FS_POSIX_ACL=y | 112 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 113 | CONFIG_EXT4_FS_SECURITY=y | 113 | CONFIG_EXT4_FS_SECURITY=y |
| 114 | CONFIG_AUTOFS4_FS=y | 114 | CONFIG_AUTOFS4_FS=y |
| 115 | CONFIG_FUSE_FS=y | 115 | CONFIG_FUSE_FS=y |
| 116 | CONFIG_MSDOS_FS=y | 116 | CONFIG_MSDOS_FS=y |
| 117 | CONFIG_VFAT_FS=y | 117 | CONFIG_VFAT_FS=y |
| 118 | CONFIG_TMPFS=y | 118 | CONFIG_TMPFS=y |
| 119 | CONFIG_TMPFS_POSIX_ACL=y | 119 | CONFIG_TMPFS_POSIX_ACL=y |
| 120 | CONFIG_CONFIGFS_FS=y | 120 | CONFIG_CONFIGFS_FS=y |
| 121 | # CONFIG_MISC_FILESYSTEMS is not set | 121 | # CONFIG_MISC_FILESYSTEMS is not set |
| 122 | CONFIG_NLS_CODEPAGE_437=y | 122 | CONFIG_NLS_CODEPAGE_437=y |
| 123 | CONFIG_NLS_ISO8859_1=y | 123 | CONFIG_NLS_ISO8859_1=y |
| 124 | CONFIG_PRINTK_TIME=y | 124 | CONFIG_PRINTK_TIME=y |
| 125 | CONFIG_DEBUG_INFO=y | 125 | CONFIG_DEBUG_INFO=y |
| 126 | CONFIG_DEBUG_FS=y | 126 | CONFIG_DEBUG_FS=y |
| 127 | CONFIG_MAGIC_SYSRQ=y | 127 | CONFIG_MAGIC_SYSRQ=y |
| 128 | CONFIG_DETECT_HUNG_TASK=y | 128 | CONFIG_DETECT_HUNG_TASK=y |
| 129 | CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 | 129 | CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 |
| 130 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y | 130 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y |
| 131 | # CONFIG_FTRACE is not set | 131 | # CONFIG_FTRACE is not set |
| 132 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 132 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 133 | CONFIG_CRC_CCITT=y | 133 | CONFIG_CRC_CCITT=y |
| 134 | CONFIG_CRC_T10DIF=y | 134 | CONFIG_CRC_T10DIF=y |
| 135 | CONFIG_CRC_ITU_T=y | 135 | CONFIG_CRC_ITU_T=y |
| 136 | CONFIG_CRC7=y | 136 | CONFIG_CRC7=y |
| 137 | CONFIG_XZ_DEC=y | 137 | CONFIG_XZ_DEC=y |
| 138 | CONFIG_AVERAGE=y | 138 | CONFIG_AVERAGE=y |
| 139 | CONFIG_PINCTRL_BCM281XX=y | 139 | CONFIG_PINCTRL_BCM281XX=y |
| 140 | CONFIG_WATCHDOG=y | 140 | CONFIG_WATCHDOG=y |
| 141 | CONFIG_BCM_KONA_WDT=y | 141 | CONFIG_BCM_KONA_WDT=y |
| 142 | CONFIG_BCM_KONA_WDT_DEBUG=y | 142 | CONFIG_BCM_KONA_WDT_DEBUG=y |
| 143 | 143 |
arch/arm/configs/bockw_defconfig
| 1 | # CONFIG_ARM_PATCH_PHYS_VIRT is not set | 1 | # CONFIG_ARM_PATCH_PHYS_VIRT is not set |
| 2 | CONFIG_KERNEL_LZMA=y | 2 | CONFIG_KERNEL_LZMA=y |
| 3 | CONFIG_NO_HZ=y | 3 | CONFIG_NO_HZ=y |
| 4 | CONFIG_IKCONFIG=y | 4 | CONFIG_IKCONFIG=y |
| 5 | CONFIG_IKCONFIG_PROC=y | 5 | CONFIG_IKCONFIG_PROC=y |
| 6 | CONFIG_LOG_BUF_SHIFT=16 | 6 | CONFIG_LOG_BUF_SHIFT=16 |
| 7 | CONFIG_SYSCTL_SYSCALL=y | 7 | CONFIG_SYSCTL_SYSCALL=y |
| 8 | CONFIG_EMBEDDED=y | 8 | CONFIG_EMBEDDED=y |
| 9 | CONFIG_SLAB=y | 9 | CONFIG_SLAB=y |
| 10 | # CONFIG_IOSCHED_CFQ is not set | 10 | # CONFIG_IOSCHED_CFQ is not set |
| 11 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 11 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 12 | CONFIG_ARCH_R8A7778=y | 12 | CONFIG_ARCH_R8A7778=y |
| 13 | CONFIG_MACH_BOCKW=y | 13 | CONFIG_MACH_BOCKW=y |
| 14 | CONFIG_MEMORY_START=0x60000000 | 14 | CONFIG_MEMORY_START=0x60000000 |
| 15 | CONFIG_MEMORY_SIZE=0x10000000 | 15 | CONFIG_MEMORY_SIZE=0x10000000 |
| 16 | CONFIG_SHMOBILE_TIMER_HZ=1024 | 16 | CONFIG_SHMOBILE_TIMER_HZ=1024 |
| 17 | # CONFIG_SH_TIMER_CMT is not set | 17 | # CONFIG_SH_TIMER_CMT is not set |
| 18 | # CONFIG_EM_TIMER_STI is not set | 18 | # CONFIG_EM_TIMER_STI is not set |
| 19 | CONFIG_ARM_ERRATA_430973=y | 19 | CONFIG_ARM_ERRATA_430973=y |
| 20 | CONFIG_ARM_ERRATA_458693=y | 20 | CONFIG_ARM_ERRATA_458693=y |
| 21 | CONFIG_ARM_ERRATA_460075=y | 21 | CONFIG_ARM_ERRATA_460075=y |
| 22 | CONFIG_ARM_ERRATA_743622=y | 22 | CONFIG_ARM_ERRATA_743622=y |
| 23 | CONFIG_ARM_ERRATA_754322=y | 23 | CONFIG_ARM_ERRATA_754322=y |
| 24 | CONFIG_AEABI=y | 24 | CONFIG_AEABI=y |
| 25 | # CONFIG_OABI_COMPAT is not set | 25 | # CONFIG_OABI_COMPAT is not set |
| 26 | CONFIG_HIGHMEM=y | 26 | CONFIG_HIGHMEM=y |
| 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 28 | CONFIG_ZBOOT_ROM_BSS=0x0 | 28 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 29 | CONFIG_ARM_APPENDED_DTB=y | 29 | CONFIG_ARM_APPENDED_DTB=y |
| 30 | CONFIG_VFP=y | 30 | CONFIG_VFP=y |
| 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 32 | CONFIG_PM_RUNTIME=y | 32 | CONFIG_PM=y |
| 33 | CONFIG_NET=y | 33 | CONFIG_NET=y |
| 34 | CONFIG_PACKET=y | 34 | CONFIG_PACKET=y |
| 35 | CONFIG_UNIX=y | 35 | CONFIG_UNIX=y |
| 36 | CONFIG_INET=y | 36 | CONFIG_INET=y |
| 37 | CONFIG_IP_PNP=y | 37 | CONFIG_IP_PNP=y |
| 38 | CONFIG_IP_PNP_DHCP=y | 38 | CONFIG_IP_PNP_DHCP=y |
| 39 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 39 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 40 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 40 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 41 | # CONFIG_INET_XFRM_MODE_BEET is not set | 41 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 42 | # CONFIG_INET_LRO is not set | 42 | # CONFIG_INET_LRO is not set |
| 43 | # CONFIG_INET_DIAG is not set | 43 | # CONFIG_INET_DIAG is not set |
| 44 | # CONFIG_IPV6 is not set | 44 | # CONFIG_IPV6 is not set |
| 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 46 | CONFIG_DEVTMPFS=y | 46 | CONFIG_DEVTMPFS=y |
| 47 | CONFIG_DEVTMPFS_MOUNT=y | 47 | CONFIG_DEVTMPFS_MOUNT=y |
| 48 | # CONFIG_STANDALONE is not set | 48 | # CONFIG_STANDALONE is not set |
| 49 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 49 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 50 | # CONFIG_FW_LOADER is not set | 50 | # CONFIG_FW_LOADER is not set |
| 51 | CONFIG_MTD=y | 51 | CONFIG_MTD=y |
| 52 | CONFIG_MTD_CHAR=y | 52 | CONFIG_MTD_CHAR=y |
| 53 | CONFIG_MTD_BLOCK=y | 53 | CONFIG_MTD_BLOCK=y |
| 54 | CONFIG_MTD_CFI=y | 54 | CONFIG_MTD_CFI=y |
| 55 | CONFIG_MTD_CFI_AMDSTD=y | 55 | CONFIG_MTD_CFI_AMDSTD=y |
| 56 | CONFIG_MTD_M25P80=y | 56 | CONFIG_MTD_M25P80=y |
| 57 | CONFIG_MTD_SPI_NOR=y | 57 | CONFIG_MTD_SPI_NOR=y |
| 58 | CONFIG_SCSI=y | 58 | CONFIG_SCSI=y |
| 59 | CONFIG_BLK_DEV_SD=y | 59 | CONFIG_BLK_DEV_SD=y |
| 60 | CONFIG_NETDEVICES=y | 60 | CONFIG_NETDEVICES=y |
| 61 | # CONFIG_NET_CADENCE is not set | 61 | # CONFIG_NET_CADENCE is not set |
| 62 | # CONFIG_NET_VENDOR_BROADCOM is not set | 62 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 63 | # CONFIG_NET_VENDOR_CIRRUS is not set | 63 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 64 | # CONFIG_NET_VENDOR_FARADAY is not set | 64 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 65 | # CONFIG_NET_VENDOR_INTEL is not set | 65 | # CONFIG_NET_VENDOR_INTEL is not set |
| 66 | # CONFIG_NET_VENDOR_MARVELL is not set | 66 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 67 | # CONFIG_NET_VENDOR_MICREL is not set | 67 | # CONFIG_NET_VENDOR_MICREL is not set |
| 68 | # CONFIG_NET_VENDOR_NATSEMI is not set | 68 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 69 | # CONFIG_NET_VENDOR_SEEQ is not set | 69 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 70 | CONFIG_SMSC911X=y | 70 | CONFIG_SMSC911X=y |
| 71 | # CONFIG_NET_VENDOR_STMICRO is not set | 71 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 72 | # CONFIG_NET_VENDOR_WIZNET is not set | 72 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 73 | # CONFIG_INPUT is not set | 73 | # CONFIG_INPUT is not set |
| 74 | # CONFIG_SERIO is not set | 74 | # CONFIG_SERIO is not set |
| 75 | # CONFIG_VT is not set | 75 | # CONFIG_VT is not set |
| 76 | # CONFIG_LEGACY_PTYS is not set | 76 | # CONFIG_LEGACY_PTYS is not set |
| 77 | # CONFIG_DEVKMEM is not set | 77 | # CONFIG_DEVKMEM is not set |
| 78 | CONFIG_SERIAL_SH_SCI=y | 78 | CONFIG_SERIAL_SH_SCI=y |
| 79 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 | 79 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 |
| 80 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 80 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 81 | # CONFIG_HW_RANDOM is not set | 81 | # CONFIG_HW_RANDOM is not set |
| 82 | # CONFIG_HWMON is not set | 82 | # CONFIG_HWMON is not set |
| 83 | CONFIG_I2C=y | 83 | CONFIG_I2C=y |
| 84 | CONFIG_I2C_RCAR=y | 84 | CONFIG_I2C_RCAR=y |
| 85 | CONFIG_GPIO_RCAR=y | 85 | CONFIG_GPIO_RCAR=y |
| 86 | CONFIG_REGULATOR=y | 86 | CONFIG_REGULATOR=y |
| 87 | CONFIG_MEDIA_SUPPORT=y | 87 | CONFIG_MEDIA_SUPPORT=y |
| 88 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 88 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 89 | CONFIG_V4L_PLATFORM_DRIVERS=y | 89 | CONFIG_V4L_PLATFORM_DRIVERS=y |
| 90 | CONFIG_SOC_CAMERA=y | 90 | CONFIG_SOC_CAMERA=y |
| 91 | CONFIG_VIDEO_RCAR_VIN=y | 91 | CONFIG_VIDEO_RCAR_VIN=y |
| 92 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set | 92 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set |
| 93 | CONFIG_VIDEO_ML86V7667=y | 93 | CONFIG_VIDEO_ML86V7667=y |
| 94 | CONFIG_SPI=y | 94 | CONFIG_SPI=y |
| 95 | CONFIG_SPI_SH_HSPI=y | 95 | CONFIG_SPI_SH_HSPI=y |
| 96 | CONFIG_SOUND=y | 96 | CONFIG_SOUND=y |
| 97 | CONFIG_SND=y | 97 | CONFIG_SND=y |
| 98 | CONFIG_SND_SOC=y | 98 | CONFIG_SND_SOC=y |
| 99 | CONFIG_SND_SOC_RCAR=y | 99 | CONFIG_SND_SOC_RCAR=y |
| 100 | CONFIG_USB=y | 100 | CONFIG_USB=y |
| 101 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 101 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 102 | CONFIG_USB_EHCI_HCD=y | 102 | CONFIG_USB_EHCI_HCD=y |
| 103 | CONFIG_USB_OHCI_HCD=y | 103 | CONFIG_USB_OHCI_HCD=y |
| 104 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 104 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 105 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 105 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 106 | CONFIG_USB_STORAGE=y | 106 | CONFIG_USB_STORAGE=y |
| 107 | CONFIG_USB_RCAR_PHY=y | 107 | CONFIG_USB_RCAR_PHY=y |
| 108 | CONFIG_MMC=y | 108 | CONFIG_MMC=y |
| 109 | CONFIG_MMC_SDHI=y | 109 | CONFIG_MMC_SDHI=y |
| 110 | CONFIG_MMC_SH_MMCIF=y | 110 | CONFIG_MMC_SH_MMCIF=y |
| 111 | CONFIG_RTC_CLASS=y | 111 | CONFIG_RTC_CLASS=y |
| 112 | CONFIG_RTC_DRV_RX8581=y | 112 | CONFIG_RTC_DRV_RX8581=y |
| 113 | CONFIG_DMADEVICES=y | 113 | CONFIG_DMADEVICES=y |
| 114 | CONFIG_RCAR_HPB_DMAE=y | 114 | CONFIG_RCAR_HPB_DMAE=y |
| 115 | CONFIG_UIO=y | 115 | CONFIG_UIO=y |
| 116 | CONFIG_UIO_PDRV_GENIRQ=y | 116 | CONFIG_UIO_PDRV_GENIRQ=y |
| 117 | # CONFIG_IOMMU_SUPPORT is not set | 117 | # CONFIG_IOMMU_SUPPORT is not set |
| 118 | # CONFIG_DNOTIFY is not set | 118 | # CONFIG_DNOTIFY is not set |
| 119 | CONFIG_TMPFS=y | 119 | CONFIG_TMPFS=y |
| 120 | # CONFIG_MISC_FILESYSTEMS is not set | 120 | # CONFIG_MISC_FILESYSTEMS is not set |
| 121 | CONFIG_NFS_FS=y | 121 | CONFIG_NFS_FS=y |
| 122 | CONFIG_NFS_V3_ACL=y | 122 | CONFIG_NFS_V3_ACL=y |
| 123 | CONFIG_NFS_V4=y | 123 | CONFIG_NFS_V4=y |
| 124 | CONFIG_NFS_SWAP=y | 124 | CONFIG_NFS_SWAP=y |
| 125 | CONFIG_NFS_V4_1=y | 125 | CONFIG_NFS_V4_1=y |
| 126 | CONFIG_ROOT_NFS=y | 126 | CONFIG_ROOT_NFS=y |
| 127 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 127 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 128 | # CONFIG_ENABLE_MUST_CHECK is not set | 128 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 129 | # CONFIG_SCHED_DEBUG is not set | 129 | # CONFIG_SCHED_DEBUG is not set |
| 130 | # CONFIG_DEBUG_BUGVERBOSE is not set | 130 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 131 | # CONFIG_FTRACE is not set | 131 | # CONFIG_FTRACE is not set |
| 132 | # CONFIG_ARM_UNWIND is not set | 132 | # CONFIG_ARM_UNWIND is not set |
| 133 | CONFIG_AVERAGE=y | 133 | CONFIG_AVERAGE=y |
| 134 | 134 |
arch/arm/configs/davinci_all_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_POSIX_MQUEUE=y | 4 | CONFIG_POSIX_MQUEUE=y |
| 5 | CONFIG_IKCONFIG=y | 5 | CONFIG_IKCONFIG=y |
| 6 | CONFIG_IKCONFIG_PROC=y | 6 | CONFIG_IKCONFIG_PROC=y |
| 7 | CONFIG_LOG_BUF_SHIFT=14 | 7 | CONFIG_LOG_BUF_SHIFT=14 |
| 8 | CONFIG_CGROUPS=y | 8 | CONFIG_CGROUPS=y |
| 9 | CONFIG_BLK_DEV_INITRD=y | 9 | CONFIG_BLK_DEV_INITRD=y |
| 10 | CONFIG_EXPERT=y | 10 | CONFIG_EXPERT=y |
| 11 | CONFIG_MODULES=y | 11 | CONFIG_MODULES=y |
| 12 | CONFIG_MODULE_UNLOAD=y | 12 | CONFIG_MODULE_UNLOAD=y |
| 13 | CONFIG_MODULE_FORCE_UNLOAD=y | 13 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 14 | CONFIG_MODVERSIONS=y | 14 | CONFIG_MODVERSIONS=y |
| 15 | # CONFIG_BLK_DEV_BSG is not set | 15 | # CONFIG_BLK_DEV_BSG is not set |
| 16 | # CONFIG_IOSCHED_DEADLINE is not set | 16 | # CONFIG_IOSCHED_DEADLINE is not set |
| 17 | # CONFIG_IOSCHED_CFQ is not set | 17 | # CONFIG_IOSCHED_CFQ is not set |
| 18 | CONFIG_ARCH_DAVINCI=y | 18 | CONFIG_ARCH_DAVINCI=y |
| 19 | CONFIG_ARCH_DAVINCI_DM644x=y | 19 | CONFIG_ARCH_DAVINCI_DM644x=y |
| 20 | CONFIG_ARCH_DAVINCI_DM355=y | 20 | CONFIG_ARCH_DAVINCI_DM355=y |
| 21 | CONFIG_ARCH_DAVINCI_DM646x=y | 21 | CONFIG_ARCH_DAVINCI_DM646x=y |
| 22 | CONFIG_ARCH_DAVINCI_DM365=y | 22 | CONFIG_ARCH_DAVINCI_DM365=y |
| 23 | CONFIG_ARCH_DAVINCI_DA830=y | 23 | CONFIG_ARCH_DAVINCI_DA830=y |
| 24 | CONFIG_ARCH_DAVINCI_DA850=y | 24 | CONFIG_ARCH_DAVINCI_DA850=y |
| 25 | CONFIG_MACH_DA8XX_DT=y | 25 | CONFIG_MACH_DA8XX_DT=y |
| 26 | CONFIG_MACH_SFFSDR=y | 26 | CONFIG_MACH_SFFSDR=y |
| 27 | CONFIG_MACH_NEUROS_OSD2=y | 27 | CONFIG_MACH_NEUROS_OSD2=y |
| 28 | CONFIG_MACH_DM355_LEOPARD=y | 28 | CONFIG_MACH_DM355_LEOPARD=y |
| 29 | CONFIG_MACH_MITYOMAPL138=y | 29 | CONFIG_MACH_MITYOMAPL138=y |
| 30 | CONFIG_MACH_OMAPL138_HAWKBOARD=y | 30 | CONFIG_MACH_OMAPL138_HAWKBOARD=y |
| 31 | CONFIG_DAVINCI_MUX_DEBUG=y | 31 | CONFIG_DAVINCI_MUX_DEBUG=y |
| 32 | CONFIG_DAVINCI_MUX_WARNINGS=y | 32 | CONFIG_DAVINCI_MUX_WARNINGS=y |
| 33 | CONFIG_DAVINCI_RESET_CLOCKS=y | 33 | CONFIG_DAVINCI_RESET_CLOCKS=y |
| 34 | CONFIG_NO_HZ=y | 34 | CONFIG_NO_HZ=y |
| 35 | CONFIG_HIGH_RES_TIMERS=y | 35 | CONFIG_HIGH_RES_TIMERS=y |
| 36 | CONFIG_PREEMPT=y | 36 | CONFIG_PREEMPT=y |
| 37 | CONFIG_AEABI=y | 37 | CONFIG_AEABI=y |
| 38 | # CONFIG_OABI_COMPAT is not set | 38 | # CONFIG_OABI_COMPAT is not set |
| 39 | CONFIG_LEDS=y | 39 | CONFIG_LEDS=y |
| 40 | CONFIG_USE_OF=y | 40 | CONFIG_USE_OF=y |
| 41 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 41 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 42 | CONFIG_ZBOOT_ROM_BSS=0x0 | 42 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 43 | CONFIG_ARM_APPENDED_DTB=y | 43 | CONFIG_ARM_APPENDED_DTB=y |
| 44 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 44 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 45 | CONFIG_AUTO_ZRELADDR=y | 45 | CONFIG_AUTO_ZRELADDR=y |
| 46 | CONFIG_CPU_FREQ=y | 46 | CONFIG_CPU_FREQ=y |
| 47 | CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y | 47 | CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y |
| 48 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=m | 48 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=m |
| 49 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | 49 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m |
| 50 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m | 50 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m |
| 51 | CONFIG_CPU_IDLE=y | 51 | CONFIG_CPU_IDLE=y |
| 52 | CONFIG_PM_RUNTIME=y | 52 | CONFIG_PM=y |
| 53 | CONFIG_NET=y | 53 | CONFIG_NET=y |
| 54 | CONFIG_PACKET=y | 54 | CONFIG_PACKET=y |
| 55 | CONFIG_UNIX=y | 55 | CONFIG_UNIX=y |
| 56 | CONFIG_INET=y | 56 | CONFIG_INET=y |
| 57 | CONFIG_IP_PNP=y | 57 | CONFIG_IP_PNP=y |
| 58 | CONFIG_IP_PNP_DHCP=y | 58 | CONFIG_IP_PNP_DHCP=y |
| 59 | # CONFIG_INET_LRO is not set | 59 | # CONFIG_INET_LRO is not set |
| 60 | CONFIG_NETFILTER=y | 60 | CONFIG_NETFILTER=y |
| 61 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 61 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 62 | CONFIG_DEVTMPFS=y | 62 | CONFIG_DEVTMPFS=y |
| 63 | CONFIG_DEVTMPFS_MOUNT=y | 63 | CONFIG_DEVTMPFS_MOUNT=y |
| 64 | # CONFIG_FW_LOADER is not set | 64 | # CONFIG_FW_LOADER is not set |
| 65 | CONFIG_MTD=m | 65 | CONFIG_MTD=m |
| 66 | CONFIG_MTD_PARTITIONS=y | 66 | CONFIG_MTD_PARTITIONS=y |
| 67 | CONFIG_MTD_CHAR=m | 67 | CONFIG_MTD_CHAR=m |
| 68 | CONFIG_MTD_BLOCK=m | 68 | CONFIG_MTD_BLOCK=m |
| 69 | CONFIG_MTD_CFI=m | 69 | CONFIG_MTD_CFI=m |
| 70 | CONFIG_MTD_CFI_INTELEXT=m | 70 | CONFIG_MTD_CFI_INTELEXT=m |
| 71 | CONFIG_MTD_CFI_AMDSTD=m | 71 | CONFIG_MTD_CFI_AMDSTD=m |
| 72 | CONFIG_MTD_PHYSMAP=m | 72 | CONFIG_MTD_PHYSMAP=m |
| 73 | CONFIG_MTD_NAND=m | 73 | CONFIG_MTD_NAND=m |
| 74 | CONFIG_MTD_NAND_DAVINCI=m | 74 | CONFIG_MTD_NAND_DAVINCI=m |
| 75 | CONFIG_PROC_DEVICETREE=y | 75 | CONFIG_PROC_DEVICETREE=y |
| 76 | CONFIG_BLK_DEV_LOOP=m | 76 | CONFIG_BLK_DEV_LOOP=m |
| 77 | CONFIG_BLK_DEV_RAM=y | 77 | CONFIG_BLK_DEV_RAM=y |
| 78 | CONFIG_BLK_DEV_RAM_COUNT=1 | 78 | CONFIG_BLK_DEV_RAM_COUNT=1 |
| 79 | CONFIG_BLK_DEV_RAM_SIZE=32768 | 79 | CONFIG_BLK_DEV_RAM_SIZE=32768 |
| 80 | CONFIG_EEPROM_AT24=y | 80 | CONFIG_EEPROM_AT24=y |
| 81 | CONFIG_IDE=m | 81 | CONFIG_IDE=m |
| 82 | CONFIG_BLK_DEV_PALMCHIP_BK3710=m | 82 | CONFIG_BLK_DEV_PALMCHIP_BK3710=m |
| 83 | CONFIG_SCSI=m | 83 | CONFIG_SCSI=m |
| 84 | CONFIG_BLK_DEV_SD=m | 84 | CONFIG_BLK_DEV_SD=m |
| 85 | CONFIG_NETDEVICES=y | 85 | CONFIG_NETDEVICES=y |
| 86 | CONFIG_TUN=m | 86 | CONFIG_TUN=m |
| 87 | CONFIG_LXT_PHY=y | 87 | CONFIG_LXT_PHY=y |
| 88 | CONFIG_LSI_ET1011C_PHY=y | 88 | CONFIG_LSI_ET1011C_PHY=y |
| 89 | CONFIG_NET_ETHERNET=y | 89 | CONFIG_NET_ETHERNET=y |
| 90 | CONFIG_MII=y | 90 | CONFIG_MII=y |
| 91 | CONFIG_TI_DAVINCI_EMAC=y | 91 | CONFIG_TI_DAVINCI_EMAC=y |
| 92 | CONFIG_DM9000=y | 92 | CONFIG_DM9000=y |
| 93 | # CONFIG_NETDEV_1000 is not set | 93 | # CONFIG_NETDEV_1000 is not set |
| 94 | # CONFIG_NETDEV_10000 is not set | 94 | # CONFIG_NETDEV_10000 is not set |
| 95 | CONFIG_PPP=m | 95 | CONFIG_PPP=m |
| 96 | CONFIG_PPP_ASYNC=m | 96 | CONFIG_PPP_ASYNC=m |
| 97 | CONFIG_PPP_SYNC_TTY=m | 97 | CONFIG_PPP_SYNC_TTY=m |
| 98 | CONFIG_PPP_DEFLATE=m | 98 | CONFIG_PPP_DEFLATE=m |
| 99 | CONFIG_NETCONSOLE=y | 99 | CONFIG_NETCONSOLE=y |
| 100 | # CONFIG_INPUT_MOUSEDEV is not set | 100 | # CONFIG_INPUT_MOUSEDEV is not set |
| 101 | CONFIG_INPUT_EVDEV=m | 101 | CONFIG_INPUT_EVDEV=m |
| 102 | CONFIG_INPUT_EVBUG=m | 102 | CONFIG_INPUT_EVBUG=m |
| 103 | CONFIG_KEYBOARD_ATKBD=m | 103 | CONFIG_KEYBOARD_ATKBD=m |
| 104 | CONFIG_KEYBOARD_GPIO=y | 104 | CONFIG_KEYBOARD_GPIO=y |
| 105 | CONFIG_KEYBOARD_XTKBD=m | 105 | CONFIG_KEYBOARD_XTKBD=m |
| 106 | # CONFIG_INPUT_MOUSE is not set | 106 | # CONFIG_INPUT_MOUSE is not set |
| 107 | CONFIG_INPUT_TOUCHSCREEN=y | 107 | CONFIG_INPUT_TOUCHSCREEN=y |
| 108 | CONFIG_INPUT_MISC=y | 108 | CONFIG_INPUT_MISC=y |
| 109 | CONFIG_INPUT_DM355EVM=m | 109 | CONFIG_INPUT_DM355EVM=m |
| 110 | CONFIG_SERIO_LIBPS2=y | 110 | CONFIG_SERIO_LIBPS2=y |
| 111 | # CONFIG_VT_CONSOLE is not set | 111 | # CONFIG_VT_CONSOLE is not set |
| 112 | CONFIG_SERIAL_8250=y | 112 | CONFIG_SERIAL_8250=y |
| 113 | CONFIG_SERIAL_8250_CONSOLE=y | 113 | CONFIG_SERIAL_8250_CONSOLE=y |
| 114 | CONFIG_SERIAL_8250_NR_UARTS=3 | 114 | CONFIG_SERIAL_8250_NR_UARTS=3 |
| 115 | # CONFIG_HW_RANDOM is not set | 115 | # CONFIG_HW_RANDOM is not set |
| 116 | CONFIG_SERIAL_OF_PLATFORM=y | 116 | CONFIG_SERIAL_OF_PLATFORM=y |
| 117 | CONFIG_I2C=y | 117 | CONFIG_I2C=y |
| 118 | CONFIG_I2C_CHARDEV=y | 118 | CONFIG_I2C_CHARDEV=y |
| 119 | CONFIG_I2C_DAVINCI=y | 119 | CONFIG_I2C_DAVINCI=y |
| 120 | CONFIG_PINCTRL_SINGLE=y | 120 | CONFIG_PINCTRL_SINGLE=y |
| 121 | CONFIG_GPIO_PCF857X=y | 121 | CONFIG_GPIO_PCF857X=y |
| 122 | CONFIG_WATCHDOG=y | 122 | CONFIG_WATCHDOG=y |
| 123 | CONFIG_DAVINCI_WATCHDOG=m | 123 | CONFIG_DAVINCI_WATCHDOG=m |
| 124 | CONFIG_MFD_DM355EVM_MSP=y | 124 | CONFIG_MFD_DM355EVM_MSP=y |
| 125 | CONFIG_TPS6507X=y | 125 | CONFIG_TPS6507X=y |
| 126 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 126 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 127 | CONFIG_REGULATOR=y | 127 | CONFIG_REGULATOR=y |
| 128 | CONFIG_REGULATOR_TPS6507X=y | 128 | CONFIG_REGULATOR_TPS6507X=y |
| 129 | CONFIG_FB=y | 129 | CONFIG_FB=y |
| 130 | CONFIG_FB_DA8XX=y | 130 | CONFIG_FB_DA8XX=y |
| 131 | CONFIG_FIRMWARE_EDID=y | 131 | CONFIG_FIRMWARE_EDID=y |
| 132 | # CONFIG_VGA_CONSOLE is not set | 132 | # CONFIG_VGA_CONSOLE is not set |
| 133 | CONFIG_FRAMEBUFFER_CONSOLE=y | 133 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 134 | CONFIG_LOGO=y | 134 | CONFIG_LOGO=y |
| 135 | CONFIG_SOUND=m | 135 | CONFIG_SOUND=m |
| 136 | CONFIG_SND=m | 136 | CONFIG_SND=m |
| 137 | CONFIG_SND_SOC=m | 137 | CONFIG_SND_SOC=m |
| 138 | CONFIG_SND_DAVINCI_SOC=m | 138 | CONFIG_SND_DAVINCI_SOC=m |
| 139 | CONFIG_SND_DAVINCI_SOC_EVM=m | 139 | CONFIG_SND_DAVINCI_SOC_EVM=m |
| 140 | CONFIG_SND_DM6467_SOC_EVM=m | 140 | CONFIG_SND_DM6467_SOC_EVM=m |
| 141 | CONFIG_HID=m | 141 | CONFIG_HID=m |
| 142 | CONFIG_HID_A4TECH=m | 142 | CONFIG_HID_A4TECH=m |
| 143 | CONFIG_HID_APPLE=m | 143 | CONFIG_HID_APPLE=m |
| 144 | CONFIG_HID_BELKIN=m | 144 | CONFIG_HID_BELKIN=m |
| 145 | CONFIG_HID_CHERRY=m | 145 | CONFIG_HID_CHERRY=m |
| 146 | CONFIG_HID_CHICONY=m | 146 | CONFIG_HID_CHICONY=m |
| 147 | CONFIG_HID_CYPRESS=m | 147 | CONFIG_HID_CYPRESS=m |
| 148 | CONFIG_HID_EZKEY=m | 148 | CONFIG_HID_EZKEY=m |
| 149 | CONFIG_HID_GYRATION=m | 149 | CONFIG_HID_GYRATION=m |
| 150 | CONFIG_HID_LOGITECH=m | 150 | CONFIG_HID_LOGITECH=m |
| 151 | CONFIG_HID_MICROSOFT=m | 151 | CONFIG_HID_MICROSOFT=m |
| 152 | CONFIG_HID_MONTEREY=m | 152 | CONFIG_HID_MONTEREY=m |
| 153 | CONFIG_HID_PANTHERLORD=m | 153 | CONFIG_HID_PANTHERLORD=m |
| 154 | CONFIG_HID_PETALYNX=m | 154 | CONFIG_HID_PETALYNX=m |
| 155 | CONFIG_HID_SAMSUNG=m | 155 | CONFIG_HID_SAMSUNG=m |
| 156 | CONFIG_HID_SONY=m | 156 | CONFIG_HID_SONY=m |
| 157 | CONFIG_HID_SUNPLUS=m | 157 | CONFIG_HID_SUNPLUS=m |
| 158 | CONFIG_USB=m | 158 | CONFIG_USB=m |
| 159 | CONFIG_USB_MON=m | 159 | CONFIG_USB_MON=m |
| 160 | CONFIG_USB_MUSB_HDRC=m | 160 | CONFIG_USB_MUSB_HDRC=m |
| 161 | CONFIG_USB_GADGET_MUSB_HDRC=y | 161 | CONFIG_USB_GADGET_MUSB_HDRC=y |
| 162 | CONFIG_MUSB_PIO_ONLY=y | 162 | CONFIG_MUSB_PIO_ONLY=y |
| 163 | CONFIG_USB_STORAGE=m | 163 | CONFIG_USB_STORAGE=m |
| 164 | CONFIG_USB_TEST=m | 164 | CONFIG_USB_TEST=m |
| 165 | CONFIG_USB_GADGET=m | 165 | CONFIG_USB_GADGET=m |
| 166 | CONFIG_USB_GADGET_DEBUG_FILES=y | 166 | CONFIG_USB_GADGET_DEBUG_FILES=y |
| 167 | CONFIG_USB_GADGET_DEBUG_FS=y | 167 | CONFIG_USB_GADGET_DEBUG_FS=y |
| 168 | CONFIG_USB_ZERO=m | 168 | CONFIG_USB_ZERO=m |
| 169 | CONFIG_USB_ETH=m | 169 | CONFIG_USB_ETH=m |
| 170 | CONFIG_USB_GADGETFS=m | 170 | CONFIG_USB_GADGETFS=m |
| 171 | CONFIG_USB_MASS_STORAGE=m | 171 | CONFIG_USB_MASS_STORAGE=m |
| 172 | CONFIG_USB_G_SERIAL=m | 172 | CONFIG_USB_G_SERIAL=m |
| 173 | CONFIG_USB_G_PRINTER=m | 173 | CONFIG_USB_G_PRINTER=m |
| 174 | CONFIG_USB_CDC_COMPOSITE=m | 174 | CONFIG_USB_CDC_COMPOSITE=m |
| 175 | CONFIG_MMC=m | 175 | CONFIG_MMC=m |
| 176 | # CONFIG_MMC_BLOCK_BOUNCE is not set | 176 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 177 | CONFIG_MMC_DAVINCI=m | 177 | CONFIG_MMC_DAVINCI=m |
| 178 | CONFIG_NEW_LEDS=y | 178 | CONFIG_NEW_LEDS=y |
| 179 | CONFIG_LEDS_CLASS=m | 179 | CONFIG_LEDS_CLASS=m |
| 180 | CONFIG_LEDS_GPIO=m | 180 | CONFIG_LEDS_GPIO=m |
| 181 | CONFIG_LEDS_TRIGGERS=y | 181 | CONFIG_LEDS_TRIGGERS=y |
| 182 | CONFIG_LEDS_TRIGGER_TIMER=m | 182 | CONFIG_LEDS_TRIGGER_TIMER=m |
| 183 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m | 183 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m |
| 184 | CONFIG_RTC_CLASS=y | 184 | CONFIG_RTC_CLASS=y |
| 185 | CONFIG_DMADEVICES=y | 185 | CONFIG_DMADEVICES=y |
| 186 | CONFIG_TI_EDMA=y | 186 | CONFIG_TI_EDMA=y |
| 187 | CONFIG_EXT2_FS=y | 187 | CONFIG_EXT2_FS=y |
| 188 | CONFIG_EXT3_FS=y | 188 | CONFIG_EXT3_FS=y |
| 189 | CONFIG_XFS_FS=m | 189 | CONFIG_XFS_FS=m |
| 190 | CONFIG_INOTIFY=y | 190 | CONFIG_INOTIFY=y |
| 191 | CONFIG_AUTOFS4_FS=m | 191 | CONFIG_AUTOFS4_FS=m |
| 192 | CONFIG_MSDOS_FS=y | 192 | CONFIG_MSDOS_FS=y |
| 193 | CONFIG_VFAT_FS=y | 193 | CONFIG_VFAT_FS=y |
| 194 | CONFIG_TMPFS=y | 194 | CONFIG_TMPFS=y |
| 195 | CONFIG_JFFS2_FS=m | 195 | CONFIG_JFFS2_FS=m |
| 196 | CONFIG_CRAMFS=y | 196 | CONFIG_CRAMFS=y |
| 197 | CONFIG_MINIX_FS=m | 197 | CONFIG_MINIX_FS=m |
| 198 | CONFIG_NFS_FS=y | 198 | CONFIG_NFS_FS=y |
| 199 | CONFIG_NFS_V3=y | 199 | CONFIG_NFS_V3=y |
| 200 | CONFIG_ROOT_NFS=y | 200 | CONFIG_ROOT_NFS=y |
| 201 | CONFIG_NFSD=m | 201 | CONFIG_NFSD=m |
| 202 | CONFIG_NFSD_V3=y | 202 | CONFIG_NFSD_V3=y |
| 203 | CONFIG_SMB_FS=m | 203 | CONFIG_SMB_FS=m |
| 204 | CONFIG_PARTITION_ADVANCED=y | 204 | CONFIG_PARTITION_ADVANCED=y |
| 205 | CONFIG_NLS_CODEPAGE_437=y | 205 | CONFIG_NLS_CODEPAGE_437=y |
| 206 | CONFIG_NLS_ASCII=m | 206 | CONFIG_NLS_ASCII=m |
| 207 | CONFIG_NLS_ISO8859_1=y | 207 | CONFIG_NLS_ISO8859_1=y |
| 208 | CONFIG_NLS_UTF8=m | 208 | CONFIG_NLS_UTF8=m |
| 209 | CONFIG_DEBUG_FS=y | 209 | CONFIG_DEBUG_FS=y |
| 210 | CONFIG_DEBUG_KERNEL=y | 210 | CONFIG_DEBUG_KERNEL=y |
| 211 | CONFIG_TIMER_STATS=y | 211 | CONFIG_TIMER_STATS=y |
| 212 | CONFIG_DEBUG_RT_MUTEXES=y | 212 | CONFIG_DEBUG_RT_MUTEXES=y |
| 213 | CONFIG_DEBUG_MUTEXES=y | 213 | CONFIG_DEBUG_MUTEXES=y |
| 214 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 214 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 215 | # CONFIG_ARM_UNWIND is not set | 215 | # CONFIG_ARM_UNWIND is not set |
| 216 | CONFIG_DEBUG_USER=y | 216 | CONFIG_DEBUG_USER=y |
| 217 | CONFIG_DEBUG_ERRORS=y | 217 | CONFIG_DEBUG_ERRORS=y |
| 218 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 218 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 219 | # CONFIG_CRYPTO_HW is not set | 219 | # CONFIG_CRYPTO_HW is not set |
| 220 | CONFIG_CRC_T10DIF=m | 220 | CONFIG_CRC_T10DIF=m |
| 221 | CONFIG_GPIO_PCA953X=y | 221 | CONFIG_GPIO_PCA953X=y |
| 222 | CONFIG_KEYBOARD_GPIO_POLLED=y | 222 | CONFIG_KEYBOARD_GPIO_POLLED=y |
| 223 | 223 |
arch/arm/configs/exynos_defconfig
| 1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 2 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_CGROUPS=y | 4 | CONFIG_CGROUPS=y |
| 5 | CONFIG_BLK_DEV_INITRD=y | 5 | CONFIG_BLK_DEV_INITRD=y |
| 6 | CONFIG_KALLSYMS_ALL=y | 6 | CONFIG_KALLSYMS_ALL=y |
| 7 | CONFIG_MODULES=y | 7 | CONFIG_MODULES=y |
| 8 | CONFIG_MODULE_UNLOAD=y | 8 | CONFIG_MODULE_UNLOAD=y |
| 9 | # CONFIG_BLK_DEV_BSG is not set | 9 | # CONFIG_BLK_DEV_BSG is not set |
| 10 | CONFIG_PARTITION_ADVANCED=y | 10 | CONFIG_PARTITION_ADVANCED=y |
| 11 | CONFIG_ARCH_EXYNOS=y | 11 | CONFIG_ARCH_EXYNOS=y |
| 12 | CONFIG_ARCH_EXYNOS3=y | 12 | CONFIG_ARCH_EXYNOS3=y |
| 13 | CONFIG_EXYNOS5420_MCPM=y | 13 | CONFIG_EXYNOS5420_MCPM=y |
| 14 | CONFIG_SMP=y | 14 | CONFIG_SMP=y |
| 15 | CONFIG_BIG_LITTLE=y | 15 | CONFIG_BIG_LITTLE=y |
| 16 | CONFIG_BL_SWITCHER=y | 16 | CONFIG_BL_SWITCHER=y |
| 17 | CONFIG_BL_SWITCHER_DUMMY_IF=y | 17 | CONFIG_BL_SWITCHER_DUMMY_IF=y |
| 18 | CONFIG_NR_CPUS=8 | 18 | CONFIG_NR_CPUS=8 |
| 19 | CONFIG_PREEMPT=y | 19 | CONFIG_PREEMPT=y |
| 20 | CONFIG_AEABI=y | 20 | CONFIG_AEABI=y |
| 21 | CONFIG_HIGHMEM=y | 21 | CONFIG_HIGHMEM=y |
| 22 | CONFIG_CMA=y | 22 | CONFIG_CMA=y |
| 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 24 | CONFIG_ZBOOT_ROM_BSS=0x0 | 24 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 25 | CONFIG_ARM_APPENDED_DTB=y | 25 | CONFIG_ARM_APPENDED_DTB=y |
| 26 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 26 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 27 | CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" | 27 | CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" |
| 28 | CONFIG_VFP=y | 28 | CONFIG_VFP=y |
| 29 | CONFIG_NEON=y | 29 | CONFIG_NEON=y |
| 30 | CONFIG_PM_RUNTIME=y | 30 | CONFIG_PM=y |
| 31 | CONFIG_NET=y | 31 | CONFIG_NET=y |
| 32 | CONFIG_PACKET=y | 32 | CONFIG_PACKET=y |
| 33 | CONFIG_UNIX=y | 33 | CONFIG_UNIX=y |
| 34 | CONFIG_NET_KEY=y | 34 | CONFIG_NET_KEY=y |
| 35 | CONFIG_INET=y | 35 | CONFIG_INET=y |
| 36 | CONFIG_RFKILL_REGULATOR=y | 36 | CONFIG_RFKILL_REGULATOR=y |
| 37 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 37 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 38 | CONFIG_DEVTMPFS=y | 38 | CONFIG_DEVTMPFS=y |
| 39 | CONFIG_DEVTMPFS_MOUNT=y | 39 | CONFIG_DEVTMPFS_MOUNT=y |
| 40 | CONFIG_PROC_DEVICETREE=y | 40 | CONFIG_PROC_DEVICETREE=y |
| 41 | CONFIG_DMA_CMA=y | 41 | CONFIG_DMA_CMA=y |
| 42 | CONFIG_CMA_SIZE_MBYTES=64 | 42 | CONFIG_CMA_SIZE_MBYTES=64 |
| 43 | CONFIG_BLK_DEV_LOOP=y | 43 | CONFIG_BLK_DEV_LOOP=y |
| 44 | CONFIG_BLK_DEV_CRYPTOLOOP=y | 44 | CONFIG_BLK_DEV_CRYPTOLOOP=y |
| 45 | CONFIG_BLK_DEV_RAM=y | 45 | CONFIG_BLK_DEV_RAM=y |
| 46 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 46 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 47 | CONFIG_SCSI=y | 47 | CONFIG_SCSI=y |
| 48 | CONFIG_BLK_DEV_SD=y | 48 | CONFIG_BLK_DEV_SD=y |
| 49 | CONFIG_CHR_DEV_SG=y | 49 | CONFIG_CHR_DEV_SG=y |
| 50 | CONFIG_MD=y | 50 | CONFIG_MD=y |
| 51 | CONFIG_BLK_DEV_DM=y | 51 | CONFIG_BLK_DEV_DM=y |
| 52 | CONFIG_DM_CRYPT=m | 52 | CONFIG_DM_CRYPT=m |
| 53 | CONFIG_NETDEVICES=y | 53 | CONFIG_NETDEVICES=y |
| 54 | CONFIG_SMSC911X=y | 54 | CONFIG_SMSC911X=y |
| 55 | CONFIG_USB_USBNET=y | 55 | CONFIG_USB_USBNET=y |
| 56 | CONFIG_USB_NET_SMSC75XX=y | 56 | CONFIG_USB_NET_SMSC75XX=y |
| 57 | CONFIG_USB_NET_SMSC95XX=y | 57 | CONFIG_USB_NET_SMSC95XX=y |
| 58 | CONFIG_USB_GADGET=y | 58 | CONFIG_USB_GADGET=y |
| 59 | CONFIG_INPUT_EVDEV=y | 59 | CONFIG_INPUT_EVDEV=y |
| 60 | CONFIG_KEYBOARD_GPIO=y | 60 | CONFIG_KEYBOARD_GPIO=y |
| 61 | CONFIG_KEYBOARD_CROS_EC=y | 61 | CONFIG_KEYBOARD_CROS_EC=y |
| 62 | # CONFIG_MOUSE_PS2 is not set | 62 | # CONFIG_MOUSE_PS2 is not set |
| 63 | CONFIG_MOUSE_CYAPA=y | 63 | CONFIG_MOUSE_CYAPA=y |
| 64 | CONFIG_INPUT_TOUCHSCREEN=y | 64 | CONFIG_INPUT_TOUCHSCREEN=y |
| 65 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y | 65 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y |
| 66 | CONFIG_SERIAL_8250=y | 66 | CONFIG_SERIAL_8250=y |
| 67 | CONFIG_SERIAL_SAMSUNG=y | 67 | CONFIG_SERIAL_SAMSUNG=y |
| 68 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | 68 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y |
| 69 | CONFIG_SERIAL_OF_PLATFORM=y | 69 | CONFIG_SERIAL_OF_PLATFORM=y |
| 70 | CONFIG_HW_RANDOM=y | 70 | CONFIG_HW_RANDOM=y |
| 71 | CONFIG_TCG_TPM=y | 71 | CONFIG_TCG_TPM=y |
| 72 | CONFIG_TCG_TIS_I2C_INFINEON=y | 72 | CONFIG_TCG_TIS_I2C_INFINEON=y |
| 73 | CONFIG_I2C=y | 73 | CONFIG_I2C=y |
| 74 | CONFIG_I2C_CHARDEV=y | 74 | CONFIG_I2C_CHARDEV=y |
| 75 | CONFIG_I2C_MUX=y | 75 | CONFIG_I2C_MUX=y |
| 76 | CONFIG_I2C_ARB_GPIO_CHALLENGE=y | 76 | CONFIG_I2C_ARB_GPIO_CHALLENGE=y |
| 77 | CONFIG_I2C_EXYNOS5=y | 77 | CONFIG_I2C_EXYNOS5=y |
| 78 | CONFIG_I2C_GPIO=y | 78 | CONFIG_I2C_GPIO=y |
| 79 | CONFIG_I2C_CROS_EC_TUNNEL=y | 79 | CONFIG_I2C_CROS_EC_TUNNEL=y |
| 80 | CONFIG_SPI=y | 80 | CONFIG_SPI=y |
| 81 | CONFIG_SPI_S3C64XX=y | 81 | CONFIG_SPI_S3C64XX=y |
| 82 | CONFIG_I2C_S3C2410=y | 82 | CONFIG_I2C_S3C2410=y |
| 83 | CONFIG_DEBUG_GPIO=y | 83 | CONFIG_DEBUG_GPIO=y |
| 84 | CONFIG_POWER_SUPPLY=y | 84 | CONFIG_POWER_SUPPLY=y |
| 85 | CONFIG_BATTERY_SBS=y | 85 | CONFIG_BATTERY_SBS=y |
| 86 | CONFIG_CHARGER_TPS65090=y | 86 | CONFIG_CHARGER_TPS65090=y |
| 87 | # CONFIG_HWMON is not set | 87 | # CONFIG_HWMON is not set |
| 88 | CONFIG_THERMAL=y | 88 | CONFIG_THERMAL=y |
| 89 | CONFIG_EXYNOS_THERMAL=y | 89 | CONFIG_EXYNOS_THERMAL=y |
| 90 | CONFIG_EXYNOS_THERMAL_CORE=y | 90 | CONFIG_EXYNOS_THERMAL_CORE=y |
| 91 | CONFIG_WATCHDOG=y | 91 | CONFIG_WATCHDOG=y |
| 92 | CONFIG_S3C2410_WATCHDOG=y | 92 | CONFIG_S3C2410_WATCHDOG=y |
| 93 | CONFIG_MFD_CROS_EC=y | 93 | CONFIG_MFD_CROS_EC=y |
| 94 | CONFIG_MFD_CROS_EC_I2C=y | 94 | CONFIG_MFD_CROS_EC_I2C=y |
| 95 | CONFIG_MFD_CROS_EC_SPI=y | 95 | CONFIG_MFD_CROS_EC_SPI=y |
| 96 | CONFIG_MFD_MAX77686=y | 96 | CONFIG_MFD_MAX77686=y |
| 97 | CONFIG_MFD_MAX77693=y | 97 | CONFIG_MFD_MAX77693=y |
| 98 | CONFIG_MFD_MAX8997=y | 98 | CONFIG_MFD_MAX8997=y |
| 99 | CONFIG_MFD_SEC_CORE=y | 99 | CONFIG_MFD_SEC_CORE=y |
| 100 | CONFIG_MFD_TPS65090=y | 100 | CONFIG_MFD_TPS65090=y |
| 101 | CONFIG_REGULATOR=y | 101 | CONFIG_REGULATOR=y |
| 102 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 102 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 103 | CONFIG_REGULATOR_GPIO=y | 103 | CONFIG_REGULATOR_GPIO=y |
| 104 | CONFIG_REGULATOR_MAX8997=y | 104 | CONFIG_REGULATOR_MAX8997=y |
| 105 | CONFIG_REGULATOR_MAX77686=y | 105 | CONFIG_REGULATOR_MAX77686=y |
| 106 | CONFIG_REGULATOR_MAX77802=y | 106 | CONFIG_REGULATOR_MAX77802=y |
| 107 | CONFIG_REGULATOR_MAX77693=y | 107 | CONFIG_REGULATOR_MAX77693=y |
| 108 | CONFIG_REGULATOR_S2MPA01=y | 108 | CONFIG_REGULATOR_S2MPA01=y |
| 109 | CONFIG_REGULATOR_S2MPS11=y | 109 | CONFIG_REGULATOR_S2MPS11=y |
| 110 | CONFIG_REGULATOR_S5M8767=y | 110 | CONFIG_REGULATOR_S5M8767=y |
| 111 | CONFIG_REGULATOR_TPS65090=y | 111 | CONFIG_REGULATOR_TPS65090=y |
| 112 | CONFIG_FB=y | 112 | CONFIG_FB=y |
| 113 | CONFIG_FB_MODE_HELPERS=y | 113 | CONFIG_FB_MODE_HELPERS=y |
| 114 | CONFIG_FB_SIMPLE=y | 114 | CONFIG_FB_SIMPLE=y |
| 115 | CONFIG_EXYNOS_VIDEO=y | 115 | CONFIG_EXYNOS_VIDEO=y |
| 116 | CONFIG_EXYNOS_MIPI_DSI=y | 116 | CONFIG_EXYNOS_MIPI_DSI=y |
| 117 | CONFIG_FRAMEBUFFER_CONSOLE=y | 117 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 118 | CONFIG_FONTS=y | 118 | CONFIG_FONTS=y |
| 119 | CONFIG_FONT_7x14=y | 119 | CONFIG_FONT_7x14=y |
| 120 | CONFIG_LOGO=y | 120 | CONFIG_LOGO=y |
| 121 | CONFIG_SOUND=y | 121 | CONFIG_SOUND=y |
| 122 | CONFIG_SND=y | 122 | CONFIG_SND=y |
| 123 | CONFIG_SND_SOC=y | 123 | CONFIG_SND_SOC=y |
| 124 | CONFIG_SND_SOC_SAMSUNG=y | 124 | CONFIG_SND_SOC_SAMSUNG=y |
| 125 | CONFIG_SND_SOC_SNOW=y | 125 | CONFIG_SND_SOC_SNOW=y |
| 126 | CONFIG_USB=y | 126 | CONFIG_USB=y |
| 127 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 127 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 128 | CONFIG_USB_XHCI_HCD=y | 128 | CONFIG_USB_XHCI_HCD=y |
| 129 | CONFIG_USB_EHCI_HCD=y | 129 | CONFIG_USB_EHCI_HCD=y |
| 130 | CONFIG_USB_EHCI_EXYNOS=y | 130 | CONFIG_USB_EHCI_EXYNOS=y |
| 131 | CONFIG_USB_OHCI_HCD=y | 131 | CONFIG_USB_OHCI_HCD=y |
| 132 | CONFIG_USB_OHCI_EXYNOS=y | 132 | CONFIG_USB_OHCI_EXYNOS=y |
| 133 | CONFIG_USB_STORAGE=y | 133 | CONFIG_USB_STORAGE=y |
| 134 | CONFIG_USB_DWC3=y | 134 | CONFIG_USB_DWC3=y |
| 135 | CONFIG_USB_HSIC_USB3503=y | 135 | CONFIG_USB_HSIC_USB3503=y |
| 136 | CONFIG_MMC=y | 136 | CONFIG_MMC=y |
| 137 | CONFIG_MMC_BLOCK_MINORS=16 | 137 | CONFIG_MMC_BLOCK_MINORS=16 |
| 138 | CONFIG_MMC_SDHCI=y | 138 | CONFIG_MMC_SDHCI=y |
| 139 | CONFIG_MMC_SDHCI_S3C=y | 139 | CONFIG_MMC_SDHCI_S3C=y |
| 140 | CONFIG_MMC_SDHCI_S3C_DMA=y | 140 | CONFIG_MMC_SDHCI_S3C_DMA=y |
| 141 | CONFIG_MMC_DW=y | 141 | CONFIG_MMC_DW=y |
| 142 | CONFIG_MMC_DW_IDMAC=y | 142 | CONFIG_MMC_DW_IDMAC=y |
| 143 | CONFIG_MMC_DW_EXYNOS=y | 143 | CONFIG_MMC_DW_EXYNOS=y |
| 144 | CONFIG_RTC_CLASS=y | 144 | CONFIG_RTC_CLASS=y |
| 145 | CONFIG_RTC_DRV_MAX77686=y | 145 | CONFIG_RTC_DRV_MAX77686=y |
| 146 | CONFIG_RTC_DRV_MAX77802=y | 146 | CONFIG_RTC_DRV_MAX77802=y |
| 147 | CONFIG_RTC_DRV_S5M=y | 147 | CONFIG_RTC_DRV_S5M=y |
| 148 | CONFIG_RTC_DRV_S3C=y | 148 | CONFIG_RTC_DRV_S3C=y |
| 149 | CONFIG_DMADEVICES=y | 149 | CONFIG_DMADEVICES=y |
| 150 | CONFIG_PL330_DMA=y | 150 | CONFIG_PL330_DMA=y |
| 151 | CONFIG_COMMON_CLK_MAX77686=y | 151 | CONFIG_COMMON_CLK_MAX77686=y |
| 152 | CONFIG_COMMON_CLK_MAX77802=y | 152 | CONFIG_COMMON_CLK_MAX77802=y |
| 153 | CONFIG_COMMON_CLK_S2MPS11=y | 153 | CONFIG_COMMON_CLK_S2MPS11=y |
| 154 | CONFIG_EXYNOS_IOMMU=y | 154 | CONFIG_EXYNOS_IOMMU=y |
| 155 | CONFIG_IIO=y | 155 | CONFIG_IIO=y |
| 156 | CONFIG_EXYNOS_ADC=y | 156 | CONFIG_EXYNOS_ADC=y |
| 157 | CONFIG_PWM=y | 157 | CONFIG_PWM=y |
| 158 | CONFIG_PWM_SAMSUNG=y | 158 | CONFIG_PWM_SAMSUNG=y |
| 159 | CONFIG_PHY_EXYNOS5250_SATA=y | 159 | CONFIG_PHY_EXYNOS5250_SATA=y |
| 160 | CONFIG_PHY_SAMSUNG_USB2=y | 160 | CONFIG_PHY_SAMSUNG_USB2=y |
| 161 | CONFIG_PHY_EXYNOS4210_USB2=y | 161 | CONFIG_PHY_EXYNOS4210_USB2=y |
| 162 | CONFIG_PHY_EXYNOS4X12_USB2=y | 162 | CONFIG_PHY_EXYNOS4X12_USB2=y |
| 163 | CONFIG_PHY_EXYNOS5250_USB2=y | 163 | CONFIG_PHY_EXYNOS5250_USB2=y |
| 164 | CONFIG_PHY_EXYNOS5_USBDRD=y | 164 | CONFIG_PHY_EXYNOS5_USBDRD=y |
| 165 | CONFIG_EXT2_FS=y | 165 | CONFIG_EXT2_FS=y |
| 166 | CONFIG_EXT3_FS=y | 166 | CONFIG_EXT3_FS=y |
| 167 | CONFIG_EXT4_FS=y | 167 | CONFIG_EXT4_FS=y |
| 168 | CONFIG_MSDOS_FS=y | 168 | CONFIG_MSDOS_FS=y |
| 169 | CONFIG_VFAT_FS=y | 169 | CONFIG_VFAT_FS=y |
| 170 | CONFIG_TMPFS=y | 170 | CONFIG_TMPFS=y |
| 171 | CONFIG_TMPFS_POSIX_ACL=y | 171 | CONFIG_TMPFS_POSIX_ACL=y |
| 172 | CONFIG_CRAMFS=y | 172 | CONFIG_CRAMFS=y |
| 173 | CONFIG_ROMFS_FS=y | 173 | CONFIG_ROMFS_FS=y |
| 174 | CONFIG_NLS_CODEPAGE_437=y | 174 | CONFIG_NLS_CODEPAGE_437=y |
| 175 | CONFIG_NLS_ASCII=y | 175 | CONFIG_NLS_ASCII=y |
| 176 | CONFIG_NLS_ISO8859_1=y | 176 | CONFIG_NLS_ISO8859_1=y |
| 177 | CONFIG_PRINTK_TIME=y | 177 | CONFIG_PRINTK_TIME=y |
| 178 | CONFIG_DEBUG_FS=y | 178 | CONFIG_DEBUG_FS=y |
| 179 | CONFIG_MAGIC_SYSRQ=y | 179 | CONFIG_MAGIC_SYSRQ=y |
| 180 | CONFIG_DEBUG_KERNEL=y | 180 | CONFIG_DEBUG_KERNEL=y |
| 181 | CONFIG_DETECT_HUNG_TASK=y | 181 | CONFIG_DETECT_HUNG_TASK=y |
| 182 | CONFIG_DEBUG_RT_MUTEXES=y | 182 | CONFIG_DEBUG_RT_MUTEXES=y |
| 183 | CONFIG_DEBUG_SPINLOCK=y | 183 | CONFIG_DEBUG_SPINLOCK=y |
| 184 | CONFIG_DEBUG_MUTEXES=y | 184 | CONFIG_DEBUG_MUTEXES=y |
| 185 | CONFIG_DEBUG_INFO=y | 185 | CONFIG_DEBUG_INFO=y |
| 186 | CONFIG_DEBUG_USER=y | 186 | CONFIG_DEBUG_USER=y |
| 187 | CONFIG_CRYPTO_SHA256=y | 187 | CONFIG_CRYPTO_SHA256=y |
| 188 | CONFIG_CRC_CCITT=y | 188 | CONFIG_CRC_CCITT=y |
| 189 | 189 |
arch/arm/configs/ezx_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_LOCALVERSION="-ezx200910312315" | 2 | CONFIG_LOCALVERSION="-ezx200910312315" |
| 3 | # CONFIG_LOCALVERSION_AUTO is not set | 3 | # CONFIG_LOCALVERSION_AUTO is not set |
| 4 | CONFIG_SYSVIPC=y | 4 | CONFIG_SYSVIPC=y |
| 5 | CONFIG_LOG_BUF_SHIFT=14 | 5 | CONFIG_LOG_BUF_SHIFT=14 |
| 6 | CONFIG_SYSFS_DEPRECATED_V2=y | 6 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 7 | CONFIG_BLK_DEV_INITRD=y | 7 | CONFIG_BLK_DEV_INITRD=y |
| 8 | CONFIG_RD_BZIP2=y | 8 | CONFIG_RD_BZIP2=y |
| 9 | CONFIG_RD_LZMA=y | 9 | CONFIG_RD_LZMA=y |
| 10 | CONFIG_EXPERT=y | 10 | CONFIG_EXPERT=y |
| 11 | # CONFIG_COMPAT_BRK is not set | 11 | # CONFIG_COMPAT_BRK is not set |
| 12 | CONFIG_SLAB=y | 12 | CONFIG_SLAB=y |
| 13 | CONFIG_MODULES=y | 13 | CONFIG_MODULES=y |
| 14 | CONFIG_MODULE_UNLOAD=y | 14 | CONFIG_MODULE_UNLOAD=y |
| 15 | CONFIG_MODULE_FORCE_UNLOAD=y | 15 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 16 | CONFIG_MODVERSIONS=y | 16 | CONFIG_MODVERSIONS=y |
| 17 | # CONFIG_LBDAF is not set | 17 | # CONFIG_LBDAF is not set |
| 18 | # CONFIG_BLK_DEV_BSG is not set | 18 | # CONFIG_BLK_DEV_BSG is not set |
| 19 | # CONFIG_IOSCHED_CFQ is not set | 19 | # CONFIG_IOSCHED_CFQ is not set |
| 20 | CONFIG_ARCH_PXA=y | 20 | CONFIG_ARCH_PXA=y |
| 21 | CONFIG_PXA_EZX=y | 21 | CONFIG_PXA_EZX=y |
| 22 | CONFIG_NO_HZ=y | 22 | CONFIG_NO_HZ=y |
| 23 | CONFIG_HIGH_RES_TIMERS=y | 23 | CONFIG_HIGH_RES_TIMERS=y |
| 24 | CONFIG_PREEMPT=y | 24 | CONFIG_PREEMPT=y |
| 25 | CONFIG_AEABI=y | 25 | CONFIG_AEABI=y |
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | 27 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 28 | CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" | 28 | CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" |
| 29 | CONFIG_KEXEC=y | 29 | CONFIG_KEXEC=y |
| 30 | CONFIG_CPU_FREQ=y | 30 | CONFIG_CPU_FREQ=y |
| 31 | CONFIG_CPU_FREQ_DEBUG=y | 31 | CONFIG_CPU_FREQ_DEBUG=y |
| 32 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | 32 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m |
| 33 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | 33 | CONFIG_CPU_FREQ_GOV_USERSPACE=m |
| 34 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m | 34 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m |
| 35 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m | 35 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m |
| 36 | CONFIG_CPU_IDLE=y | 36 | CONFIG_CPU_IDLE=y |
| 37 | CONFIG_FPE_NWFPE=y | 37 | CONFIG_FPE_NWFPE=y |
| 38 | CONFIG_BINFMT_AOUT=m | 38 | CONFIG_BINFMT_AOUT=m |
| 39 | CONFIG_BINFMT_MISC=m | 39 | CONFIG_BINFMT_MISC=m |
| 40 | CONFIG_PM=y | 40 | CONFIG_PM=y |
| 41 | CONFIG_APM_EMULATION=y | 41 | CONFIG_APM_EMULATION=y |
| 42 | CONFIG_PM_RUNTIME=y | ||
| 43 | CONFIG_NET=y | 42 | CONFIG_NET=y |
| 44 | CONFIG_PACKET=y | 43 | CONFIG_PACKET=y |
| 45 | CONFIG_UNIX=y | 44 | CONFIG_UNIX=y |
| 46 | CONFIG_INET=y | 45 | CONFIG_INET=y |
| 47 | CONFIG_IP_PNP=y | 46 | CONFIG_IP_PNP=y |
| 48 | CONFIG_IP_PNP_DHCP=y | 47 | CONFIG_IP_PNP_DHCP=y |
| 49 | CONFIG_IP_PNP_BOOTP=y | 48 | CONFIG_IP_PNP_BOOTP=y |
| 50 | CONFIG_IP_PNP_RARP=y | 49 | CONFIG_IP_PNP_RARP=y |
| 51 | CONFIG_SYN_COOKIES=y | 50 | CONFIG_SYN_COOKIES=y |
| 52 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 51 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 53 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 52 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 54 | # CONFIG_INET_XFRM_MODE_BEET is not set | 53 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 55 | # CONFIG_INET_LRO is not set | 54 | # CONFIG_INET_LRO is not set |
| 56 | # CONFIG_INET_DIAG is not set | 55 | # CONFIG_INET_DIAG is not set |
| 57 | CONFIG_INET6_AH=m | 56 | CONFIG_INET6_AH=m |
| 58 | CONFIG_INET6_ESP=m | 57 | CONFIG_INET6_ESP=m |
| 59 | CONFIG_INET6_IPCOMP=m | 58 | CONFIG_INET6_IPCOMP=m |
| 60 | CONFIG_IPV6_MIP6=m | 59 | CONFIG_IPV6_MIP6=m |
| 61 | CONFIG_IPV6_TUNNEL=m | 60 | CONFIG_IPV6_TUNNEL=m |
| 62 | CONFIG_IPV6_MULTIPLE_TABLES=y | 61 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 63 | CONFIG_IPV6_SUBTREES=y | 62 | CONFIG_IPV6_SUBTREES=y |
| 64 | CONFIG_NETFILTER=y | 63 | CONFIG_NETFILTER=y |
| 65 | CONFIG_NETFILTER_NETLINK_QUEUE=m | 64 | CONFIG_NETFILTER_NETLINK_QUEUE=m |
| 66 | CONFIG_NF_CONNTRACK=m | 65 | CONFIG_NF_CONNTRACK=m |
| 67 | CONFIG_NF_CONNTRACK_EVENTS=y | 66 | CONFIG_NF_CONNTRACK_EVENTS=y |
| 68 | CONFIG_NF_CT_PROTO_SCTP=m | 67 | CONFIG_NF_CT_PROTO_SCTP=m |
| 69 | CONFIG_NF_CT_PROTO_UDPLITE=m | 68 | CONFIG_NF_CT_PROTO_UDPLITE=m |
| 70 | CONFIG_NF_CONNTRACK_AMANDA=m | 69 | CONFIG_NF_CONNTRACK_AMANDA=m |
| 71 | CONFIG_NF_CONNTRACK_FTP=m | 70 | CONFIG_NF_CONNTRACK_FTP=m |
| 72 | CONFIG_NF_CONNTRACK_H323=m | 71 | CONFIG_NF_CONNTRACK_H323=m |
| 73 | CONFIG_NF_CONNTRACK_IRC=m | 72 | CONFIG_NF_CONNTRACK_IRC=m |
| 74 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m | 73 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m |
| 75 | CONFIG_NF_CONNTRACK_PPTP=m | 74 | CONFIG_NF_CONNTRACK_PPTP=m |
| 76 | CONFIG_NF_CONNTRACK_SANE=m | 75 | CONFIG_NF_CONNTRACK_SANE=m |
| 77 | CONFIG_NF_CONNTRACK_SIP=m | 76 | CONFIG_NF_CONNTRACK_SIP=m |
| 78 | CONFIG_NF_CONNTRACK_TFTP=m | 77 | CONFIG_NF_CONNTRACK_TFTP=m |
| 79 | CONFIG_NF_CT_NETLINK=m | 78 | CONFIG_NF_CT_NETLINK=m |
| 80 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 79 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 81 | CONFIG_NETFILTER_XT_TARGET_LED=m | 80 | CONFIG_NETFILTER_XT_TARGET_LED=m |
| 82 | CONFIG_NETFILTER_XT_TARGET_MARK=m | 81 | CONFIG_NETFILTER_XT_TARGET_MARK=m |
| 83 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | 82 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m |
| 84 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | 83 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m |
| 85 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | 84 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m |
| 86 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | 85 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m |
| 87 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | 86 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m |
| 88 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | 87 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m |
| 89 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m | 88 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m |
| 90 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | 89 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m |
| 91 | CONFIG_NETFILTER_XT_MATCH_DCCP=m | 90 | CONFIG_NETFILTER_XT_MATCH_DCCP=m |
| 92 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | 91 | CONFIG_NETFILTER_XT_MATCH_DSCP=m |
| 93 | CONFIG_NETFILTER_XT_MATCH_ESP=m | 92 | CONFIG_NETFILTER_XT_MATCH_ESP=m |
| 94 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | 93 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m |
| 95 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | 94 | CONFIG_NETFILTER_XT_MATCH_HELPER=m |
| 96 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | 95 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m |
| 97 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | 96 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m |
| 98 | CONFIG_NETFILTER_XT_MATCH_MAC=m | 97 | CONFIG_NETFILTER_XT_MATCH_MAC=m |
| 99 | CONFIG_NETFILTER_XT_MATCH_MARK=m | 98 | CONFIG_NETFILTER_XT_MATCH_MARK=m |
| 100 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | 99 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m |
| 101 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | 100 | CONFIG_NETFILTER_XT_MATCH_POLICY=m |
| 102 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | 101 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m |
| 103 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | 102 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m |
| 104 | CONFIG_NETFILTER_XT_MATCH_REALM=m | 103 | CONFIG_NETFILTER_XT_MATCH_REALM=m |
| 105 | CONFIG_NETFILTER_XT_MATCH_SCTP=m | 104 | CONFIG_NETFILTER_XT_MATCH_SCTP=m |
| 106 | CONFIG_NETFILTER_XT_MATCH_STATE=m | 105 | CONFIG_NETFILTER_XT_MATCH_STATE=m |
| 107 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | 106 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m |
| 108 | CONFIG_NETFILTER_XT_MATCH_STRING=m | 107 | CONFIG_NETFILTER_XT_MATCH_STRING=m |
| 109 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 108 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 110 | CONFIG_NETFILTER_XT_MATCH_TIME=m | 109 | CONFIG_NETFILTER_XT_MATCH_TIME=m |
| 111 | CONFIG_NETFILTER_XT_MATCH_U32=m | 110 | CONFIG_NETFILTER_XT_MATCH_U32=m |
| 112 | CONFIG_NF_CONNTRACK_IPV4=m | 111 | CONFIG_NF_CONNTRACK_IPV4=m |
| 113 | CONFIG_IP_NF_QUEUE=m | 112 | CONFIG_IP_NF_QUEUE=m |
| 114 | CONFIG_IP_NF_IPTABLES=m | 113 | CONFIG_IP_NF_IPTABLES=m |
| 115 | CONFIG_IP_NF_MATCH_ADDRTYPE=m | 114 | CONFIG_IP_NF_MATCH_ADDRTYPE=m |
| 116 | CONFIG_IP_NF_MATCH_AH=m | 115 | CONFIG_IP_NF_MATCH_AH=m |
| 117 | CONFIG_IP_NF_MATCH_ECN=m | 116 | CONFIG_IP_NF_MATCH_ECN=m |
| 118 | CONFIG_IP_NF_MATCH_TTL=m | 117 | CONFIG_IP_NF_MATCH_TTL=m |
| 119 | CONFIG_IP_NF_FILTER=m | 118 | CONFIG_IP_NF_FILTER=m |
| 120 | CONFIG_IP_NF_TARGET_REJECT=m | 119 | CONFIG_IP_NF_TARGET_REJECT=m |
| 121 | CONFIG_IP_NF_TARGET_LOG=m | 120 | CONFIG_IP_NF_TARGET_LOG=m |
| 122 | CONFIG_IP_NF_TARGET_ULOG=m | 121 | CONFIG_IP_NF_TARGET_ULOG=m |
| 123 | CONFIG_NF_NAT=m | 122 | CONFIG_NF_NAT=m |
| 124 | CONFIG_IP_NF_TARGET_MASQUERADE=m | 123 | CONFIG_IP_NF_TARGET_MASQUERADE=m |
| 125 | CONFIG_IP_NF_TARGET_NETMAP=m | 124 | CONFIG_IP_NF_TARGET_NETMAP=m |
| 126 | CONFIG_IP_NF_TARGET_REDIRECT=m | 125 | CONFIG_IP_NF_TARGET_REDIRECT=m |
| 127 | CONFIG_NF_NAT_SNMP_BASIC=m | 126 | CONFIG_NF_NAT_SNMP_BASIC=m |
| 128 | CONFIG_IP_NF_MANGLE=m | 127 | CONFIG_IP_NF_MANGLE=m |
| 129 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | 128 | CONFIG_IP_NF_TARGET_CLUSTERIP=m |
| 130 | CONFIG_IP_NF_TARGET_ECN=m | 129 | CONFIG_IP_NF_TARGET_ECN=m |
| 131 | CONFIG_IP_NF_TARGET_TTL=m | 130 | CONFIG_IP_NF_TARGET_TTL=m |
| 132 | CONFIG_IP_NF_RAW=m | 131 | CONFIG_IP_NF_RAW=m |
| 133 | CONFIG_IP_NF_ARPTABLES=m | 132 | CONFIG_IP_NF_ARPTABLES=m |
| 134 | CONFIG_IP_NF_ARPFILTER=m | 133 | CONFIG_IP_NF_ARPFILTER=m |
| 135 | CONFIG_IP_NF_ARP_MANGLE=m | 134 | CONFIG_IP_NF_ARP_MANGLE=m |
| 136 | CONFIG_NF_CONNTRACK_IPV6=m | 135 | CONFIG_NF_CONNTRACK_IPV6=m |
| 137 | CONFIG_IP6_NF_QUEUE=m | 136 | CONFIG_IP6_NF_QUEUE=m |
| 138 | CONFIG_IP6_NF_IPTABLES=m | 137 | CONFIG_IP6_NF_IPTABLES=m |
| 139 | CONFIG_IP6_NF_MATCH_AH=m | 138 | CONFIG_IP6_NF_MATCH_AH=m |
| 140 | CONFIG_IP6_NF_MATCH_EUI64=m | 139 | CONFIG_IP6_NF_MATCH_EUI64=m |
| 141 | CONFIG_IP6_NF_MATCH_FRAG=m | 140 | CONFIG_IP6_NF_MATCH_FRAG=m |
| 142 | CONFIG_IP6_NF_MATCH_OPTS=m | 141 | CONFIG_IP6_NF_MATCH_OPTS=m |
| 143 | CONFIG_IP6_NF_MATCH_HL=m | 142 | CONFIG_IP6_NF_MATCH_HL=m |
| 144 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | 143 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m |
| 145 | CONFIG_IP6_NF_MATCH_MH=m | 144 | CONFIG_IP6_NF_MATCH_MH=m |
| 146 | CONFIG_IP6_NF_MATCH_RT=m | 145 | CONFIG_IP6_NF_MATCH_RT=m |
| 147 | CONFIG_IP6_NF_TARGET_HL=m | 146 | CONFIG_IP6_NF_TARGET_HL=m |
| 148 | CONFIG_IP6_NF_TARGET_LOG=m | 147 | CONFIG_IP6_NF_TARGET_LOG=m |
| 149 | CONFIG_IP6_NF_FILTER=m | 148 | CONFIG_IP6_NF_FILTER=m |
| 150 | CONFIG_IP6_NF_TARGET_REJECT=m | 149 | CONFIG_IP6_NF_TARGET_REJECT=m |
| 151 | CONFIG_IP6_NF_MANGLE=m | 150 | CONFIG_IP6_NF_MANGLE=m |
| 152 | CONFIG_IP6_NF_RAW=m | 151 | CONFIG_IP6_NF_RAW=m |
| 153 | CONFIG_BRIDGE=m | 152 | CONFIG_BRIDGE=m |
| 154 | CONFIG_BT=y | 153 | CONFIG_BT=y |
| 155 | CONFIG_BT_L2CAP=y | 154 | CONFIG_BT_L2CAP=y |
| 156 | CONFIG_BT_SCO=y | 155 | CONFIG_BT_SCO=y |
| 157 | CONFIG_BT_RFCOMM=y | 156 | CONFIG_BT_RFCOMM=y |
| 158 | CONFIG_BT_RFCOMM_TTY=y | 157 | CONFIG_BT_RFCOMM_TTY=y |
| 159 | CONFIG_BT_BNEP=y | 158 | CONFIG_BT_BNEP=y |
| 160 | CONFIG_BT_BNEP_MC_FILTER=y | 159 | CONFIG_BT_BNEP_MC_FILTER=y |
| 161 | CONFIG_BT_BNEP_PROTO_FILTER=y | 160 | CONFIG_BT_BNEP_PROTO_FILTER=y |
| 162 | CONFIG_BT_HIDP=y | 161 | CONFIG_BT_HIDP=y |
| 163 | CONFIG_BT_HCIBTUSB=m | 162 | CONFIG_BT_HCIBTUSB=m |
| 164 | CONFIG_BT_HCIBTSDIO=m | 163 | CONFIG_BT_HCIBTSDIO=m |
| 165 | CONFIG_BT_HCIUART=y | 164 | CONFIG_BT_HCIUART=y |
| 166 | CONFIG_BT_HCIUART_H4=y | 165 | CONFIG_BT_HCIUART_H4=y |
| 167 | CONFIG_BT_HCIBCM203X=m | 166 | CONFIG_BT_HCIBCM203X=m |
| 168 | CONFIG_BT_HCIBPA10X=m | 167 | CONFIG_BT_HCIBPA10X=m |
| 169 | CONFIG_BT_HCIBFUSB=m | 168 | CONFIG_BT_HCIBFUSB=m |
| 170 | CONFIG_BT_HCIVHCI=m | 169 | CONFIG_BT_HCIVHCI=m |
| 171 | CONFIG_BT_MRVL=m | 170 | CONFIG_BT_MRVL=m |
| 172 | CONFIG_BT_MRVL_SDIO=m | 171 | CONFIG_BT_MRVL_SDIO=m |
| 173 | # CONFIG_WIRELESS is not set | 172 | # CONFIG_WIRELESS is not set |
| 174 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 173 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 175 | CONFIG_FW_LOADER=m | 174 | CONFIG_FW_LOADER=m |
| 176 | CONFIG_CONNECTOR=m | 175 | CONFIG_CONNECTOR=m |
| 177 | CONFIG_MTD=y | 176 | CONFIG_MTD=y |
| 178 | CONFIG_MTD_CHAR=y | 177 | CONFIG_MTD_CHAR=y |
| 179 | CONFIG_MTD_BLOCK=y | 178 | CONFIG_MTD_BLOCK=y |
| 180 | CONFIG_MTD_CFI=y | 179 | CONFIG_MTD_CFI=y |
| 181 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 180 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| 182 | CONFIG_MTD_CFI_GEOMETRY=y | 181 | CONFIG_MTD_CFI_GEOMETRY=y |
| 183 | # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set | 182 | # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set |
| 184 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | 183 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set |
| 185 | # CONFIG_MTD_CFI_I2 is not set | 184 | # CONFIG_MTD_CFI_I2 is not set |
| 186 | CONFIG_MTD_OTP=y | 185 | CONFIG_MTD_OTP=y |
| 187 | CONFIG_MTD_CFI_INTELEXT=y | 186 | CONFIG_MTD_CFI_INTELEXT=y |
| 188 | CONFIG_MTD_PXA2XX=y | 187 | CONFIG_MTD_PXA2XX=y |
| 189 | CONFIG_BLK_DEV_LOOP=m | 188 | CONFIG_BLK_DEV_LOOP=m |
| 190 | CONFIG_BLK_DEV_CRYPTOLOOP=m | 189 | CONFIG_BLK_DEV_CRYPTOLOOP=m |
| 191 | CONFIG_BLK_DEV_NBD=m | 190 | CONFIG_BLK_DEV_NBD=m |
| 192 | CONFIG_BLK_DEV_RAM=y | 191 | CONFIG_BLK_DEV_RAM=y |
| 193 | # CONFIG_MISC_DEVICES is not set | 192 | # CONFIG_MISC_DEVICES is not set |
| 194 | CONFIG_NETDEVICES=y | 193 | CONFIG_NETDEVICES=y |
| 195 | CONFIG_DUMMY=y | 194 | CONFIG_DUMMY=y |
| 196 | # CONFIG_NETDEV_1000 is not set | 195 | # CONFIG_NETDEV_1000 is not set |
| 197 | # CONFIG_NETDEV_10000 is not set | 196 | # CONFIG_NETDEV_10000 is not set |
| 198 | # CONFIG_WLAN is not set | 197 | # CONFIG_WLAN is not set |
| 199 | CONFIG_PPP=m | 198 | CONFIG_PPP=m |
| 200 | CONFIG_PPP_MULTILINK=y | 199 | CONFIG_PPP_MULTILINK=y |
| 201 | CONFIG_PPP_FILTER=y | 200 | CONFIG_PPP_FILTER=y |
| 202 | CONFIG_PPP_ASYNC=m | 201 | CONFIG_PPP_ASYNC=m |
| 203 | CONFIG_PPP_SYNC_TTY=m | 202 | CONFIG_PPP_SYNC_TTY=m |
| 204 | CONFIG_PPP_DEFLATE=m | 203 | CONFIG_PPP_DEFLATE=m |
| 205 | CONFIG_PPP_BSDCOMP=m | 204 | CONFIG_PPP_BSDCOMP=m |
| 206 | # CONFIG_INPUT_MOUSEDEV is not set | 205 | # CONFIG_INPUT_MOUSEDEV is not set |
| 207 | CONFIG_INPUT_EVDEV=y | 206 | CONFIG_INPUT_EVDEV=y |
| 208 | # CONFIG_KEYBOARD_ATKBD is not set | 207 | # CONFIG_KEYBOARD_ATKBD is not set |
| 209 | CONFIG_KEYBOARD_GPIO=y | 208 | CONFIG_KEYBOARD_GPIO=y |
| 210 | CONFIG_KEYBOARD_PXA27x=y | 209 | CONFIG_KEYBOARD_PXA27x=y |
| 211 | # CONFIG_INPUT_MOUSE is not set | 210 | # CONFIG_INPUT_MOUSE is not set |
| 212 | CONFIG_INPUT_TOUCHSCREEN=y | 211 | CONFIG_INPUT_TOUCHSCREEN=y |
| 213 | CONFIG_TOUCHSCREEN_PCAP=y | 212 | CONFIG_TOUCHSCREEN_PCAP=y |
| 214 | CONFIG_INPUT_MISC=y | 213 | CONFIG_INPUT_MISC=y |
| 215 | CONFIG_INPUT_UINPUT=y | 214 | CONFIG_INPUT_UINPUT=y |
| 216 | CONFIG_INPUT_PCAP=y | 215 | CONFIG_INPUT_PCAP=y |
| 217 | # CONFIG_SERIO is not set | 216 | # CONFIG_SERIO is not set |
| 218 | CONFIG_SERIAL_PXA=y | 217 | CONFIG_SERIAL_PXA=y |
| 219 | CONFIG_SERIAL_PXA_CONSOLE=y | 218 | CONFIG_SERIAL_PXA_CONSOLE=y |
| 220 | CONFIG_LEGACY_PTY_COUNT=8 | 219 | CONFIG_LEGACY_PTY_COUNT=8 |
| 221 | # CONFIG_HW_RANDOM is not set | 220 | # CONFIG_HW_RANDOM is not set |
| 222 | CONFIG_I2C=y | 221 | CONFIG_I2C=y |
| 223 | CONFIG_I2C_CHARDEV=y | 222 | CONFIG_I2C_CHARDEV=y |
| 224 | CONFIG_I2C_PXA=y | 223 | CONFIG_I2C_PXA=y |
| 225 | CONFIG_SPI=y | 224 | CONFIG_SPI=y |
| 226 | CONFIG_SPI_PXA2XX=y | 225 | CONFIG_SPI_PXA2XX=y |
| 227 | CONFIG_GPIO_SYSFS=y | 226 | CONFIG_GPIO_SYSFS=y |
| 228 | CONFIG_POWER_SUPPLY=y | 227 | CONFIG_POWER_SUPPLY=y |
| 229 | # CONFIG_HWMON is not set | 228 | # CONFIG_HWMON is not set |
| 230 | CONFIG_EZX_PCAP=y | 229 | CONFIG_EZX_PCAP=y |
| 231 | CONFIG_REGULATOR=y | 230 | CONFIG_REGULATOR=y |
| 232 | CONFIG_REGULATOR_DEBUG=y | 231 | CONFIG_REGULATOR_DEBUG=y |
| 233 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y | 232 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y |
| 234 | CONFIG_REGULATOR_PCAP=y | 233 | CONFIG_REGULATOR_PCAP=y |
| 235 | CONFIG_MEDIA_SUPPORT=y | 234 | CONFIG_MEDIA_SUPPORT=y |
| 236 | CONFIG_VIDEO_DEV=y | 235 | CONFIG_VIDEO_DEV=y |
| 237 | CONFIG_MEDIA_TUNER_CUSTOMISE=y | 236 | CONFIG_MEDIA_TUNER_CUSTOMISE=y |
| 238 | # CONFIG_MEDIA_TUNER_SIMPLE is not set | 237 | # CONFIG_MEDIA_TUNER_SIMPLE is not set |
| 239 | # CONFIG_MEDIA_TUNER_TDA8290 is not set | 238 | # CONFIG_MEDIA_TUNER_TDA8290 is not set |
| 240 | # CONFIG_MEDIA_TUNER_TDA827X is not set | 239 | # CONFIG_MEDIA_TUNER_TDA827X is not set |
| 241 | # CONFIG_MEDIA_TUNER_TDA18271 is not set | 240 | # CONFIG_MEDIA_TUNER_TDA18271 is not set |
| 242 | # CONFIG_MEDIA_TUNER_TDA9887 is not set | 241 | # CONFIG_MEDIA_TUNER_TDA9887 is not set |
| 243 | # CONFIG_MEDIA_TUNER_TEA5761 is not set | 242 | # CONFIG_MEDIA_TUNER_TEA5761 is not set |
| 244 | # CONFIG_MEDIA_TUNER_TEA5767 is not set | 243 | # CONFIG_MEDIA_TUNER_TEA5767 is not set |
| 245 | # CONFIG_MEDIA_TUNER_MT20XX is not set | 244 | # CONFIG_MEDIA_TUNER_MT20XX is not set |
| 246 | # CONFIG_MEDIA_TUNER_MT2060 is not set | 245 | # CONFIG_MEDIA_TUNER_MT2060 is not set |
| 247 | # CONFIG_MEDIA_TUNER_MT2266 is not set | 246 | # CONFIG_MEDIA_TUNER_MT2266 is not set |
| 248 | # CONFIG_MEDIA_TUNER_MT2131 is not set | 247 | # CONFIG_MEDIA_TUNER_MT2131 is not set |
| 249 | # CONFIG_MEDIA_TUNER_QT1010 is not set | 248 | # CONFIG_MEDIA_TUNER_QT1010 is not set |
| 250 | # CONFIG_MEDIA_TUNER_XC2028 is not set | 249 | # CONFIG_MEDIA_TUNER_XC2028 is not set |
| 251 | # CONFIG_MEDIA_TUNER_XC5000 is not set | 250 | # CONFIG_MEDIA_TUNER_XC5000 is not set |
| 252 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | 251 | # CONFIG_MEDIA_TUNER_MXL5005S is not set |
| 253 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | 252 | # CONFIG_MEDIA_TUNER_MXL5007T is not set |
| 254 | # CONFIG_MEDIA_TUNER_MC44S803 is not set | 253 | # CONFIG_MEDIA_TUNER_MC44S803 is not set |
| 255 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | 254 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set |
| 256 | CONFIG_SOC_CAMERA=y | 255 | CONFIG_SOC_CAMERA=y |
| 257 | CONFIG_SOC_CAMERA_MT9M111=y | 256 | CONFIG_SOC_CAMERA_MT9M111=y |
| 258 | CONFIG_VIDEO_PXA27x=y | 257 | CONFIG_VIDEO_PXA27x=y |
| 259 | # CONFIG_V4L_USB_DRIVERS is not set | 258 | # CONFIG_V4L_USB_DRIVERS is not set |
| 260 | CONFIG_RADIO_TEA5764=y | 259 | CONFIG_RADIO_TEA5764=y |
| 261 | CONFIG_FB=y | 260 | CONFIG_FB=y |
| 262 | CONFIG_FB_PXA=y | 261 | CONFIG_FB_PXA=y |
| 263 | CONFIG_FB_PXA_OVERLAY=y | 262 | CONFIG_FB_PXA_OVERLAY=y |
| 264 | CONFIG_FB_PXA_PARAMETERS=y | 263 | CONFIG_FB_PXA_PARAMETERS=y |
| 265 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 264 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 266 | # CONFIG_LCD_CLASS_DEVICE is not set | 265 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 267 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 266 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 268 | CONFIG_BACKLIGHT_PWM=y | 267 | CONFIG_BACKLIGHT_PWM=y |
| 269 | # CONFIG_VGA_CONSOLE is not set | 268 | # CONFIG_VGA_CONSOLE is not set |
| 270 | CONFIG_FRAMEBUFFER_CONSOLE=y | 269 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 271 | CONFIG_FONTS=y | 270 | CONFIG_FONTS=y |
| 272 | CONFIG_FONT_MINI_4x6=y | 271 | CONFIG_FONT_MINI_4x6=y |
| 273 | CONFIG_SOUND=y | 272 | CONFIG_SOUND=y |
| 274 | CONFIG_SND=y | 273 | CONFIG_SND=y |
| 275 | CONFIG_SND_MIXER_OSS=y | 274 | CONFIG_SND_MIXER_OSS=y |
| 276 | CONFIG_SND_PCM_OSS=y | 275 | CONFIG_SND_PCM_OSS=y |
| 277 | # CONFIG_SND_DRIVERS is not set | 276 | # CONFIG_SND_DRIVERS is not set |
| 278 | # CONFIG_SND_ARM is not set | 277 | # CONFIG_SND_ARM is not set |
| 279 | # CONFIG_SND_SPI is not set | 278 | # CONFIG_SND_SPI is not set |
| 280 | # CONFIG_SND_USB is not set | 279 | # CONFIG_SND_USB is not set |
| 281 | CONFIG_SND_SOC=y | 280 | CONFIG_SND_SOC=y |
| 282 | CONFIG_SND_PXA2XX_SOC=y | 281 | CONFIG_SND_PXA2XX_SOC=y |
| 283 | # CONFIG_USB_HID is not set | 282 | # CONFIG_USB_HID is not set |
| 284 | CONFIG_HID_APPLE=m | 283 | CONFIG_HID_APPLE=m |
| 285 | CONFIG_USB=y | 284 | CONFIG_USB=y |
| 286 | # CONFIG_USB_DEVICE_CLASS is not set | 285 | # CONFIG_USB_DEVICE_CLASS is not set |
| 287 | CONFIG_USB_OHCI_HCD=y | 286 | CONFIG_USB_OHCI_HCD=y |
| 288 | CONFIG_USB_GADGET=y | 287 | CONFIG_USB_GADGET=y |
| 289 | CONFIG_USB_PXA27X=y | 288 | CONFIG_USB_PXA27X=y |
| 290 | CONFIG_USB_ETH=m | 289 | CONFIG_USB_ETH=m |
| 291 | # CONFIG_USB_ETH_RNDIS is not set | 290 | # CONFIG_USB_ETH_RNDIS is not set |
| 292 | CONFIG_MMC=y | 291 | CONFIG_MMC=y |
| 293 | CONFIG_MMC_UNSAFE_RESUME=y | 292 | CONFIG_MMC_UNSAFE_RESUME=y |
| 294 | CONFIG_SDIO_UART=m | 293 | CONFIG_SDIO_UART=m |
| 295 | CONFIG_MMC_PXA=y | 294 | CONFIG_MMC_PXA=y |
| 296 | CONFIG_MMC_SPI=y | 295 | CONFIG_MMC_SPI=y |
| 297 | CONFIG_NEW_LEDS=y | 296 | CONFIG_NEW_LEDS=y |
| 298 | CONFIG_LEDS_CLASS=y | 297 | CONFIG_LEDS_CLASS=y |
| 299 | CONFIG_LEDS_LP3944=y | 298 | CONFIG_LEDS_LP3944=y |
| 300 | CONFIG_LEDS_TRIGGERS=y | 299 | CONFIG_LEDS_TRIGGERS=y |
| 301 | CONFIG_LEDS_TRIGGER_TIMER=y | 300 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 302 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 301 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 303 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | 302 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y |
| 304 | CONFIG_LEDS_TRIGGER_GPIO=y | 303 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 305 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 304 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 306 | CONFIG_RTC_CLASS=y | 305 | CONFIG_RTC_CLASS=y |
| 307 | CONFIG_RTC_DRV_PCAP=y | 306 | CONFIG_RTC_DRV_PCAP=y |
| 308 | CONFIG_EXT2_FS=y | 307 | CONFIG_EXT2_FS=y |
| 309 | CONFIG_EXT3_FS=m | 308 | CONFIG_EXT3_FS=m |
| 310 | CONFIG_REISERFS_FS=m | 309 | CONFIG_REISERFS_FS=m |
| 311 | CONFIG_REISERFS_FS_XATTR=y | 310 | CONFIG_REISERFS_FS_XATTR=y |
| 312 | CONFIG_REISERFS_FS_POSIX_ACL=y | 311 | CONFIG_REISERFS_FS_POSIX_ACL=y |
| 313 | CONFIG_REISERFS_FS_SECURITY=y | 312 | CONFIG_REISERFS_FS_SECURITY=y |
| 314 | CONFIG_XFS_FS=m | 313 | CONFIG_XFS_FS=m |
| 315 | CONFIG_INOTIFY=y | 314 | CONFIG_INOTIFY=y |
| 316 | CONFIG_AUTOFS_FS=y | 315 | CONFIG_AUTOFS_FS=y |
| 317 | CONFIG_AUTOFS4_FS=y | 316 | CONFIG_AUTOFS4_FS=y |
| 318 | CONFIG_FUSE_FS=m | 317 | CONFIG_FUSE_FS=m |
| 319 | CONFIG_CUSE=m | 318 | CONFIG_CUSE=m |
| 320 | CONFIG_ISO9660_FS=m | 319 | CONFIG_ISO9660_FS=m |
| 321 | CONFIG_JOLIET=y | 320 | CONFIG_JOLIET=y |
| 322 | CONFIG_ZISOFS=y | 321 | CONFIG_ZISOFS=y |
| 323 | CONFIG_MSDOS_FS=m | 322 | CONFIG_MSDOS_FS=m |
| 324 | CONFIG_VFAT_FS=m | 323 | CONFIG_VFAT_FS=m |
| 325 | CONFIG_TMPFS=y | 324 | CONFIG_TMPFS=y |
| 326 | CONFIG_JFFS2_FS=m | 325 | CONFIG_JFFS2_FS=m |
| 327 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | 326 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y |
| 328 | CONFIG_JFFS2_LZO=y | 327 | CONFIG_JFFS2_LZO=y |
| 329 | CONFIG_JFFS2_RUBIN=y | 328 | CONFIG_JFFS2_RUBIN=y |
| 330 | CONFIG_CRAMFS=m | 329 | CONFIG_CRAMFS=m |
| 331 | CONFIG_SQUASHFS=m | 330 | CONFIG_SQUASHFS=m |
| 332 | CONFIG_ROMFS_FS=m | 331 | CONFIG_ROMFS_FS=m |
| 333 | CONFIG_NFS_FS=y | 332 | CONFIG_NFS_FS=y |
| 334 | CONFIG_NFS_V3=y | 333 | CONFIG_NFS_V3=y |
| 335 | CONFIG_NFS_V3_ACL=y | 334 | CONFIG_NFS_V3_ACL=y |
| 336 | CONFIG_NFSD=m | 335 | CONFIG_NFSD=m |
| 337 | CONFIG_NFSD_V3=y | 336 | CONFIG_NFSD_V3=y |
| 338 | CONFIG_NFSD_V3_ACL=y | 337 | CONFIG_NFSD_V3_ACL=y |
| 339 | CONFIG_SMB_FS=m | 338 | CONFIG_SMB_FS=m |
| 340 | CONFIG_CIFS=m | 339 | CONFIG_CIFS=m |
| 341 | CONFIG_CIFS_STATS=y | 340 | CONFIG_CIFS_STATS=y |
| 342 | CONFIG_CIFS_WEAK_PW_HASH=y | 341 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 343 | CONFIG_CIFS_XATTR=y | 342 | CONFIG_CIFS_XATTR=y |
| 344 | CONFIG_CIFS_POSIX=y | 343 | CONFIG_CIFS_POSIX=y |
| 345 | CONFIG_NLS_CODEPAGE_437=m | 344 | CONFIG_NLS_CODEPAGE_437=m |
| 346 | CONFIG_NLS_CODEPAGE_737=m | 345 | CONFIG_NLS_CODEPAGE_737=m |
| 347 | CONFIG_NLS_CODEPAGE_775=m | 346 | CONFIG_NLS_CODEPAGE_775=m |
| 348 | CONFIG_NLS_CODEPAGE_850=m | 347 | CONFIG_NLS_CODEPAGE_850=m |
| 349 | CONFIG_NLS_CODEPAGE_852=m | 348 | CONFIG_NLS_CODEPAGE_852=m |
| 350 | CONFIG_NLS_CODEPAGE_855=m | 349 | CONFIG_NLS_CODEPAGE_855=m |
| 351 | CONFIG_NLS_CODEPAGE_857=m | 350 | CONFIG_NLS_CODEPAGE_857=m |
| 352 | CONFIG_NLS_CODEPAGE_860=m | 351 | CONFIG_NLS_CODEPAGE_860=m |
| 353 | CONFIG_NLS_CODEPAGE_861=m | 352 | CONFIG_NLS_CODEPAGE_861=m |
| 354 | CONFIG_NLS_CODEPAGE_862=m | 353 | CONFIG_NLS_CODEPAGE_862=m |
| 355 | CONFIG_NLS_CODEPAGE_863=m | 354 | CONFIG_NLS_CODEPAGE_863=m |
| 356 | CONFIG_NLS_CODEPAGE_864=m | 355 | CONFIG_NLS_CODEPAGE_864=m |
| 357 | CONFIG_NLS_CODEPAGE_865=m | 356 | CONFIG_NLS_CODEPAGE_865=m |
| 358 | CONFIG_NLS_CODEPAGE_866=m | 357 | CONFIG_NLS_CODEPAGE_866=m |
| 359 | CONFIG_NLS_CODEPAGE_869=m | 358 | CONFIG_NLS_CODEPAGE_869=m |
| 360 | CONFIG_NLS_CODEPAGE_936=m | 359 | CONFIG_NLS_CODEPAGE_936=m |
| 361 | CONFIG_NLS_CODEPAGE_950=m | 360 | CONFIG_NLS_CODEPAGE_950=m |
| 362 | CONFIG_NLS_CODEPAGE_932=m | 361 | CONFIG_NLS_CODEPAGE_932=m |
| 363 | CONFIG_NLS_CODEPAGE_949=m | 362 | CONFIG_NLS_CODEPAGE_949=m |
| 364 | CONFIG_NLS_CODEPAGE_874=m | 363 | CONFIG_NLS_CODEPAGE_874=m |
| 365 | CONFIG_NLS_ISO8859_8=m | 364 | CONFIG_NLS_ISO8859_8=m |
| 366 | CONFIG_NLS_CODEPAGE_1250=m | 365 | CONFIG_NLS_CODEPAGE_1250=m |
| 367 | CONFIG_NLS_CODEPAGE_1251=m | 366 | CONFIG_NLS_CODEPAGE_1251=m |
| 368 | CONFIG_NLS_ASCII=m | 367 | CONFIG_NLS_ASCII=m |
| 369 | CONFIG_NLS_ISO8859_1=m | 368 | CONFIG_NLS_ISO8859_1=m |
| 370 | CONFIG_NLS_ISO8859_2=m | 369 | CONFIG_NLS_ISO8859_2=m |
| 371 | CONFIG_NLS_ISO8859_3=m | 370 | CONFIG_NLS_ISO8859_3=m |
| 372 | CONFIG_NLS_ISO8859_4=m | 371 | CONFIG_NLS_ISO8859_4=m |
| 373 | CONFIG_NLS_ISO8859_5=m | 372 | CONFIG_NLS_ISO8859_5=m |
| 374 | CONFIG_NLS_ISO8859_6=m | 373 | CONFIG_NLS_ISO8859_6=m |
| 375 | CONFIG_NLS_ISO8859_7=m | 374 | CONFIG_NLS_ISO8859_7=m |
| 376 | CONFIG_NLS_ISO8859_9=m | 375 | CONFIG_NLS_ISO8859_9=m |
| 377 | CONFIG_NLS_ISO8859_13=m | 376 | CONFIG_NLS_ISO8859_13=m |
| 378 | CONFIG_NLS_ISO8859_14=m | 377 | CONFIG_NLS_ISO8859_14=m |
| 379 | CONFIG_NLS_ISO8859_15=m | 378 | CONFIG_NLS_ISO8859_15=m |
| 380 | CONFIG_NLS_KOI8_R=m | 379 | CONFIG_NLS_KOI8_R=m |
| 381 | CONFIG_NLS_KOI8_U=m | 380 | CONFIG_NLS_KOI8_U=m |
| 382 | CONFIG_NLS_UTF8=m | 381 | CONFIG_NLS_UTF8=m |
| 383 | CONFIG_PRINTK_TIME=y | 382 | CONFIG_PRINTK_TIME=y |
| 384 | CONFIG_DEBUG_FS=y | 383 | CONFIG_DEBUG_FS=y |
| 385 | CONFIG_DEBUG_KERNEL=y | 384 | CONFIG_DEBUG_KERNEL=y |
| 386 | # CONFIG_SCHED_DEBUG is not set | 385 | # CONFIG_SCHED_DEBUG is not set |
| 387 | CONFIG_DEBUG_RT_MUTEXES=y | 386 | CONFIG_DEBUG_RT_MUTEXES=y |
| 388 | CONFIG_PROVE_LOCKING=y | 387 | CONFIG_PROVE_LOCKING=y |
| 389 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 388 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 390 | # CONFIG_FTRACE is not set | 389 | # CONFIG_FTRACE is not set |
| 391 | CONFIG_DEBUG_USER=y | 390 | CONFIG_DEBUG_USER=y |
| 392 | CONFIG_DEBUG_ERRORS=y | 391 | CONFIG_DEBUG_ERRORS=y |
| 393 | CONFIG_CRYPTO_NULL=m | 392 | CONFIG_CRYPTO_NULL=m |
| 394 | CONFIG_CRYPTO_CRYPTD=m | 393 | CONFIG_CRYPTO_CRYPTD=m |
| 395 | CONFIG_CRYPTO_TEST=m | 394 | CONFIG_CRYPTO_TEST=m |
| 396 | CONFIG_CRYPTO_ECB=m | 395 | CONFIG_CRYPTO_ECB=m |
| 397 | CONFIG_CRYPTO_LRW=m | 396 | CONFIG_CRYPTO_LRW=m |
| 398 | CONFIG_CRYPTO_PCBC=m | 397 | CONFIG_CRYPTO_PCBC=m |
| 399 | CONFIG_CRYPTO_XTS=m | 398 | CONFIG_CRYPTO_XTS=m |
| 400 | CONFIG_CRYPTO_XCBC=m | 399 | CONFIG_CRYPTO_XCBC=m |
| 401 | CONFIG_CRYPTO_VMAC=m | 400 | CONFIG_CRYPTO_VMAC=m |
| 402 | CONFIG_CRYPTO_GHASH=m | 401 | CONFIG_CRYPTO_GHASH=m |
| 403 | CONFIG_CRYPTO_MD4=m | 402 | CONFIG_CRYPTO_MD4=m |
| 404 | CONFIG_CRYPTO_MICHAEL_MIC=m | 403 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 405 | CONFIG_CRYPTO_SHA256=m | 404 | CONFIG_CRYPTO_SHA256=m |
| 406 | CONFIG_CRYPTO_SHA512=m | 405 | CONFIG_CRYPTO_SHA512=m |
| 407 | CONFIG_CRYPTO_TGR192=m | 406 | CONFIG_CRYPTO_TGR192=m |
| 408 | CONFIG_CRYPTO_AES=m | 407 | CONFIG_CRYPTO_AES=m |
| 409 | CONFIG_CRYPTO_ARC4=m | 408 | CONFIG_CRYPTO_ARC4=m |
| 410 | CONFIG_CRYPTO_BLOWFISH=m | 409 | CONFIG_CRYPTO_BLOWFISH=m |
| 411 | CONFIG_CRYPTO_CAST5=m | 410 | CONFIG_CRYPTO_CAST5=m |
| 412 | CONFIG_CRYPTO_CAST6=m | 411 | CONFIG_CRYPTO_CAST6=m |
| 413 | CONFIG_CRYPTO_FCRYPT=m | 412 | CONFIG_CRYPTO_FCRYPT=m |
| 414 | CONFIG_CRYPTO_KHAZAD=m | 413 | CONFIG_CRYPTO_KHAZAD=m |
| 415 | CONFIG_CRYPTO_SEED=m | 414 | CONFIG_CRYPTO_SEED=m |
| 416 | CONFIG_CRYPTO_SERPENT=m | 415 | CONFIG_CRYPTO_SERPENT=m |
| 417 | CONFIG_CRYPTO_TEA=m | 416 | CONFIG_CRYPTO_TEA=m |
| 418 | CONFIG_CRYPTO_TWOFISH=m | 417 | CONFIG_CRYPTO_TWOFISH=m |
| 419 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 418 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 420 | 419 |
arch/arm/configs/hisi_defconfig
| 1 | CONFIG_IRQ_DOMAIN_DEBUG=y | 1 | CONFIG_IRQ_DOMAIN_DEBUG=y |
| 2 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_BLK_DEV_INITRD=y | 4 | CONFIG_BLK_DEV_INITRD=y |
| 5 | CONFIG_RD_LZMA=y | 5 | CONFIG_RD_LZMA=y |
| 6 | CONFIG_ARCH_HISI=y | 6 | CONFIG_ARCH_HISI=y |
| 7 | CONFIG_ARCH_HI3xxx=y | 7 | CONFIG_ARCH_HI3xxx=y |
| 8 | CONFIG_PARTITION_ADVANCED=y | 8 | CONFIG_PARTITION_ADVANCED=y |
| 9 | CONFIG_CMDLINE_PARTITION=y | 9 | CONFIG_CMDLINE_PARTITION=y |
| 10 | CONFIG_ARCH_HIX5HD2=y | 10 | CONFIG_ARCH_HIX5HD2=y |
| 11 | CONFIG_ARCH_HIP04=y | 11 | CONFIG_ARCH_HIP04=y |
| 12 | CONFIG_SMP=y | 12 | CONFIG_SMP=y |
| 13 | CONFIG_NR_CPUS=16 | 13 | CONFIG_NR_CPUS=16 |
| 14 | CONFIG_PREEMPT=y | 14 | CONFIG_PREEMPT=y |
| 15 | CONFIG_AEABI=y | 15 | CONFIG_AEABI=y |
| 16 | CONFIG_HIGHMEM=y | 16 | CONFIG_HIGHMEM=y |
| 17 | CONFIG_ARM_APPENDED_DTB=y | 17 | CONFIG_ARM_APPENDED_DTB=y |
| 18 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 18 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 19 | CONFIG_NEON=y | 19 | CONFIG_NEON=y |
| 20 | CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y | 20 | CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y |
| 21 | CONFIG_PM_RUNTIME=y | 21 | CONFIG_PM=y |
| 22 | CONFIG_NET=y | 22 | CONFIG_NET=y |
| 23 | CONFIG_PACKET=y | 23 | CONFIG_PACKET=y |
| 24 | CONFIG_UNIX=y | 24 | CONFIG_UNIX=y |
| 25 | CONFIG_INET=y | 25 | CONFIG_INET=y |
| 26 | CONFIG_IP_PNP=y | 26 | CONFIG_IP_PNP=y |
| 27 | CONFIG_IP_PNP_DHCP=y | 27 | CONFIG_IP_PNP_DHCP=y |
| 28 | CONFIG_DEVTMPFS=y | 28 | CONFIG_DEVTMPFS=y |
| 29 | CONFIG_DEVTMPFS_MOUNT=y | 29 | CONFIG_DEVTMPFS_MOUNT=y |
| 30 | CONFIG_BLK_DEV_SD=y | 30 | CONFIG_BLK_DEV_SD=y |
| 31 | CONFIG_ATA=y | 31 | CONFIG_ATA=y |
| 32 | CONFIG_SATA_AHCI_PLATFORM=y | 32 | CONFIG_SATA_AHCI_PLATFORM=y |
| 33 | CONFIG_NETDEVICES=y | 33 | CONFIG_NETDEVICES=y |
| 34 | CONFIG_HIX5HD2_GMAC=y | 34 | CONFIG_HIX5HD2_GMAC=y |
| 35 | CONFIG_SERIAL_8250=y | 35 | CONFIG_SERIAL_8250=y |
| 36 | CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y | 36 | CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y |
| 37 | CONFIG_SERIAL_8250_CONSOLE=y | 37 | CONFIG_SERIAL_8250_CONSOLE=y |
| 38 | CONFIG_SERIAL_8250_NR_UARTS=2 | 38 | CONFIG_SERIAL_8250_NR_UARTS=2 |
| 39 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | 39 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 |
| 40 | CONFIG_SERIAL_8250_DW=y | 40 | CONFIG_SERIAL_8250_DW=y |
| 41 | CONFIG_SERIAL_AMBA_PL011=y | 41 | CONFIG_SERIAL_AMBA_PL011=y |
| 42 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 42 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
| 43 | CONFIG_SERIAL_OF_PLATFORM=y | 43 | CONFIG_SERIAL_OF_PLATFORM=y |
| 44 | CONFIG_I2C_DESIGNWARE_PLATFORM=y | 44 | CONFIG_I2C_DESIGNWARE_PLATFORM=y |
| 45 | CONFIG_SPI=y | 45 | CONFIG_SPI=y |
| 46 | CONFIG_SPI_PL022=y | 46 | CONFIG_SPI_PL022=y |
| 47 | CONFIG_PINCTRL_SINGLE=y | 47 | CONFIG_PINCTRL_SINGLE=y |
| 48 | CONFIG_DEBUG_GPIO=y | 48 | CONFIG_DEBUG_GPIO=y |
| 49 | CONFIG_GPIO_SYSFS=y | 49 | CONFIG_GPIO_SYSFS=y |
| 50 | CONFIG_GPIOLIB=y | 50 | CONFIG_GPIOLIB=y |
| 51 | CONFIG_GPIO_GENERIC_PLATFORM=y | 51 | CONFIG_GPIO_GENERIC_PLATFORM=y |
| 52 | CONFIG_REGULATOR_GPIO=y | 52 | CONFIG_REGULATOR_GPIO=y |
| 53 | CONFIG_MFD_SYSCON=y | 53 | CONFIG_MFD_SYSCON=y |
| 54 | CONFIG_POWER_RESET_SYSCON=y | 54 | CONFIG_POWER_RESET_SYSCON=y |
| 55 | CONFIG_DRM=y | 55 | CONFIG_DRM=y |
| 56 | CONFIG_FB_SIMPLE=y | 56 | CONFIG_FB_SIMPLE=y |
| 57 | CONFIG_USB=y | 57 | CONFIG_USB=y |
| 58 | CONFIG_USB_XHCI_HCD=y | 58 | CONFIG_USB_XHCI_HCD=y |
| 59 | CONFIG_USB_EHCI_HCD=y | 59 | CONFIG_USB_EHCI_HCD=y |
| 60 | CONFIG_USB_EHCI_MXC=y | 60 | CONFIG_USB_EHCI_MXC=y |
| 61 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 61 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 62 | CONFIG_USB_OHCI_HCD=y | 62 | CONFIG_USB_OHCI_HCD=y |
| 63 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 63 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 64 | CONFIG_USB_STORAGE=y | 64 | CONFIG_USB_STORAGE=y |
| 65 | CONFIG_NOP_USB_XCEIV=y | 65 | CONFIG_NOP_USB_XCEIV=y |
| 66 | CONFIG_MMC=y | 66 | CONFIG_MMC=y |
| 67 | CONFIG_RTC_CLASS=y | 67 | CONFIG_RTC_CLASS=y |
| 68 | CONFIG_MMC_DW=y | 68 | CONFIG_MMC_DW=y |
| 69 | CONFIG_MMC_DW_IDMAC=y | 69 | CONFIG_MMC_DW_IDMAC=y |
| 70 | CONFIG_MMC_DW_PLTFM=y | 70 | CONFIG_MMC_DW_PLTFM=y |
| 71 | CONFIG_RTC_DRV_PL031=y | 71 | CONFIG_RTC_DRV_PL031=y |
| 72 | CONFIG_DMADEVICES=y | 72 | CONFIG_DMADEVICES=y |
| 73 | CONFIG_DW_DMAC=y | 73 | CONFIG_DW_DMAC=y |
| 74 | CONFIG_PL330_DMA=y | 74 | CONFIG_PL330_DMA=y |
| 75 | CONFIG_PWM=y | 75 | CONFIG_PWM=y |
| 76 | CONFIG_PHY_HIX5HD2_SATA=y | 76 | CONFIG_PHY_HIX5HD2_SATA=y |
| 77 | CONFIG_EXT4_FS=y | 77 | CONFIG_EXT4_FS=y |
| 78 | CONFIG_TMPFS=y | 78 | CONFIG_TMPFS=y |
| 79 | CONFIG_NFS_FS=y | 79 | CONFIG_NFS_FS=y |
| 80 | CONFIG_NFS_V3_ACL=y | 80 | CONFIG_NFS_V3_ACL=y |
| 81 | CONFIG_NFS_V4=y | 81 | CONFIG_NFS_V4=y |
| 82 | CONFIG_ROOT_NFS=y | 82 | CONFIG_ROOT_NFS=y |
| 83 | CONFIG_PRINTK_TIME=y | 83 | CONFIG_PRINTK_TIME=y |
| 84 | CONFIG_DEBUG_FS=y | 84 | CONFIG_DEBUG_FS=y |
| 85 | CONFIG_NLS_CODEPAGE_437=y | 85 | CONFIG_NLS_CODEPAGE_437=y |
| 86 | CONFIG_NLS_ISO8859_1=y | 86 | CONFIG_NLS_ISO8859_1=y |
| 87 | CONFIG_DEBUG_KERNEL=y | 87 | CONFIG_DEBUG_KERNEL=y |
| 88 | CONFIG_LOCKUP_DETECTOR=y | 88 | CONFIG_LOCKUP_DETECTOR=y |
| 89 | CONFIG_VFP=y | 89 | CONFIG_VFP=y |
| 90 | CONFIG_VFPv3=y | 90 | CONFIG_VFPv3=y |
| 91 | 91 |
arch/arm/configs/imote2_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 2 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_LOG_BUF_SHIFT=14 | 4 | CONFIG_LOG_BUF_SHIFT=14 |
| 5 | CONFIG_SYSFS_DEPRECATED_V2=y | 5 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 6 | CONFIG_BLK_DEV_INITRD=y | 6 | CONFIG_BLK_DEV_INITRD=y |
| 7 | CONFIG_RD_BZIP2=y | 7 | CONFIG_RD_BZIP2=y |
| 8 | CONFIG_RD_LZMA=y | 8 | CONFIG_RD_LZMA=y |
| 9 | CONFIG_EXPERT=y | 9 | CONFIG_EXPERT=y |
| 10 | # CONFIG_COMPAT_BRK is not set | 10 | # CONFIG_COMPAT_BRK is not set |
| 11 | CONFIG_SLAB=y | 11 | CONFIG_SLAB=y |
| 12 | CONFIG_MODULES=y | 12 | CONFIG_MODULES=y |
| 13 | CONFIG_MODULE_UNLOAD=y | 13 | CONFIG_MODULE_UNLOAD=y |
| 14 | CONFIG_MODULE_FORCE_UNLOAD=y | 14 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 15 | CONFIG_MODVERSIONS=y | 15 | CONFIG_MODVERSIONS=y |
| 16 | # CONFIG_LBDAF is not set | 16 | # CONFIG_LBDAF is not set |
| 17 | # CONFIG_BLK_DEV_BSG is not set | 17 | # CONFIG_BLK_DEV_BSG is not set |
| 18 | # CONFIG_IOSCHED_CFQ is not set | 18 | # CONFIG_IOSCHED_CFQ is not set |
| 19 | CONFIG_ARCH_PXA=y | 19 | CONFIG_ARCH_PXA=y |
| 20 | CONFIG_MACH_INTELMOTE2=y | 20 | CONFIG_MACH_INTELMOTE2=y |
| 21 | CONFIG_NO_HZ=y | 21 | CONFIG_NO_HZ=y |
| 22 | CONFIG_HIGH_RES_TIMERS=y | 22 | CONFIG_HIGH_RES_TIMERS=y |
| 23 | CONFIG_PREEMPT=y | 23 | CONFIG_PREEMPT=y |
| 24 | CONFIG_AEABI=y | 24 | CONFIG_AEABI=y |
| 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 26 | CONFIG_ZBOOT_ROM_BSS=0x0 | 26 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 27 | CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M" | 27 | CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M" |
| 28 | CONFIG_KEXEC=y | 28 | CONFIG_KEXEC=y |
| 29 | CONFIG_FPE_NWFPE=y | 29 | CONFIG_FPE_NWFPE=y |
| 30 | CONFIG_BINFMT_AOUT=m | 30 | CONFIG_BINFMT_AOUT=m |
| 31 | CONFIG_BINFMT_MISC=m | 31 | CONFIG_BINFMT_MISC=m |
| 32 | CONFIG_PM=y | 32 | CONFIG_PM=y |
| 33 | CONFIG_APM_EMULATION=y | 33 | CONFIG_APM_EMULATION=y |
| 34 | CONFIG_PM_RUNTIME=y | ||
| 35 | CONFIG_NET=y | 34 | CONFIG_NET=y |
| 36 | CONFIG_PACKET=y | 35 | CONFIG_PACKET=y |
| 37 | CONFIG_UNIX=y | 36 | CONFIG_UNIX=y |
| 38 | CONFIG_INET=y | 37 | CONFIG_INET=y |
| 39 | CONFIG_IP_PNP=y | 38 | CONFIG_IP_PNP=y |
| 40 | CONFIG_IP_PNP_DHCP=y | 39 | CONFIG_IP_PNP_DHCP=y |
| 41 | CONFIG_IP_PNP_BOOTP=y | 40 | CONFIG_IP_PNP_BOOTP=y |
| 42 | CONFIG_IP_PNP_RARP=y | 41 | CONFIG_IP_PNP_RARP=y |
| 43 | CONFIG_SYN_COOKIES=y | 42 | CONFIG_SYN_COOKIES=y |
| 44 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 43 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 45 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 44 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 46 | # CONFIG_INET_XFRM_MODE_BEET is not set | 45 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 47 | # CONFIG_INET_LRO is not set | 46 | # CONFIG_INET_LRO is not set |
| 48 | # CONFIG_INET_DIAG is not set | 47 | # CONFIG_INET_DIAG is not set |
| 49 | CONFIG_INET6_AH=m | 48 | CONFIG_INET6_AH=m |
| 50 | CONFIG_INET6_ESP=m | 49 | CONFIG_INET6_ESP=m |
| 51 | CONFIG_INET6_IPCOMP=m | 50 | CONFIG_INET6_IPCOMP=m |
| 52 | CONFIG_IPV6_MIP6=m | 51 | CONFIG_IPV6_MIP6=m |
| 53 | CONFIG_IPV6_TUNNEL=m | 52 | CONFIG_IPV6_TUNNEL=m |
| 54 | CONFIG_IPV6_MULTIPLE_TABLES=y | 53 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 55 | CONFIG_IPV6_SUBTREES=y | 54 | CONFIG_IPV6_SUBTREES=y |
| 56 | CONFIG_NETFILTER=y | 55 | CONFIG_NETFILTER=y |
| 57 | CONFIG_NETFILTER_NETLINK_QUEUE=m | 56 | CONFIG_NETFILTER_NETLINK_QUEUE=m |
| 58 | CONFIG_NF_CONNTRACK=m | 57 | CONFIG_NF_CONNTRACK=m |
| 59 | CONFIG_NF_CONNTRACK_EVENTS=y | 58 | CONFIG_NF_CONNTRACK_EVENTS=y |
| 60 | CONFIG_NF_CT_PROTO_SCTP=m | 59 | CONFIG_NF_CT_PROTO_SCTP=m |
| 61 | CONFIG_NF_CT_PROTO_UDPLITE=m | 60 | CONFIG_NF_CT_PROTO_UDPLITE=m |
| 62 | CONFIG_NF_CONNTRACK_AMANDA=m | 61 | CONFIG_NF_CONNTRACK_AMANDA=m |
| 63 | CONFIG_NF_CONNTRACK_FTP=m | 62 | CONFIG_NF_CONNTRACK_FTP=m |
| 64 | CONFIG_NF_CONNTRACK_H323=m | 63 | CONFIG_NF_CONNTRACK_H323=m |
| 65 | CONFIG_NF_CONNTRACK_IRC=m | 64 | CONFIG_NF_CONNTRACK_IRC=m |
| 66 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m | 65 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m |
| 67 | CONFIG_NF_CONNTRACK_PPTP=m | 66 | CONFIG_NF_CONNTRACK_PPTP=m |
| 68 | CONFIG_NF_CONNTRACK_SANE=m | 67 | CONFIG_NF_CONNTRACK_SANE=m |
| 69 | CONFIG_NF_CONNTRACK_SIP=m | 68 | CONFIG_NF_CONNTRACK_SIP=m |
| 70 | CONFIG_NF_CONNTRACK_TFTP=m | 69 | CONFIG_NF_CONNTRACK_TFTP=m |
| 71 | CONFIG_NF_CT_NETLINK=m | 70 | CONFIG_NF_CT_NETLINK=m |
| 72 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 71 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 73 | CONFIG_NETFILTER_XT_TARGET_LED=m | 72 | CONFIG_NETFILTER_XT_TARGET_LED=m |
| 74 | CONFIG_NETFILTER_XT_TARGET_MARK=m | 73 | CONFIG_NETFILTER_XT_TARGET_MARK=m |
| 75 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | 74 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m |
| 76 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | 75 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m |
| 77 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | 76 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m |
| 78 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | 77 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m |
| 79 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | 78 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m |
| 80 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | 79 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m |
| 81 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m | 80 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m |
| 82 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | 81 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m |
| 83 | CONFIG_NETFILTER_XT_MATCH_DCCP=m | 82 | CONFIG_NETFILTER_XT_MATCH_DCCP=m |
| 84 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | 83 | CONFIG_NETFILTER_XT_MATCH_DSCP=m |
| 85 | CONFIG_NETFILTER_XT_MATCH_ESP=m | 84 | CONFIG_NETFILTER_XT_MATCH_ESP=m |
| 86 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | 85 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m |
| 87 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | 86 | CONFIG_NETFILTER_XT_MATCH_HELPER=m |
| 88 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | 87 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m |
| 89 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | 88 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m |
| 90 | CONFIG_NETFILTER_XT_MATCH_MAC=m | 89 | CONFIG_NETFILTER_XT_MATCH_MAC=m |
| 91 | CONFIG_NETFILTER_XT_MATCH_MARK=m | 90 | CONFIG_NETFILTER_XT_MATCH_MARK=m |
| 92 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | 91 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m |
| 93 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | 92 | CONFIG_NETFILTER_XT_MATCH_POLICY=m |
| 94 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | 93 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m |
| 95 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | 94 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m |
| 96 | CONFIG_NETFILTER_XT_MATCH_REALM=m | 95 | CONFIG_NETFILTER_XT_MATCH_REALM=m |
| 97 | CONFIG_NETFILTER_XT_MATCH_SCTP=m | 96 | CONFIG_NETFILTER_XT_MATCH_SCTP=m |
| 98 | CONFIG_NETFILTER_XT_MATCH_STATE=m | 97 | CONFIG_NETFILTER_XT_MATCH_STATE=m |
| 99 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | 98 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m |
| 100 | CONFIG_NETFILTER_XT_MATCH_STRING=m | 99 | CONFIG_NETFILTER_XT_MATCH_STRING=m |
| 101 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 100 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 102 | CONFIG_NETFILTER_XT_MATCH_TIME=m | 101 | CONFIG_NETFILTER_XT_MATCH_TIME=m |
| 103 | CONFIG_NETFILTER_XT_MATCH_U32=m | 102 | CONFIG_NETFILTER_XT_MATCH_U32=m |
| 104 | CONFIG_NF_CONNTRACK_IPV4=m | 103 | CONFIG_NF_CONNTRACK_IPV4=m |
| 105 | CONFIG_IP_NF_QUEUE=m | 104 | CONFIG_IP_NF_QUEUE=m |
| 106 | CONFIG_IP_NF_IPTABLES=m | 105 | CONFIG_IP_NF_IPTABLES=m |
| 107 | CONFIG_IP_NF_MATCH_ADDRTYPE=m | 106 | CONFIG_IP_NF_MATCH_ADDRTYPE=m |
| 108 | CONFIG_IP_NF_MATCH_AH=m | 107 | CONFIG_IP_NF_MATCH_AH=m |
| 109 | CONFIG_IP_NF_MATCH_ECN=m | 108 | CONFIG_IP_NF_MATCH_ECN=m |
| 110 | CONFIG_IP_NF_MATCH_TTL=m | 109 | CONFIG_IP_NF_MATCH_TTL=m |
| 111 | CONFIG_IP_NF_FILTER=m | 110 | CONFIG_IP_NF_FILTER=m |
| 112 | CONFIG_IP_NF_TARGET_REJECT=m | 111 | CONFIG_IP_NF_TARGET_REJECT=m |
| 113 | CONFIG_IP_NF_TARGET_LOG=m | 112 | CONFIG_IP_NF_TARGET_LOG=m |
| 114 | CONFIG_IP_NF_TARGET_ULOG=m | 113 | CONFIG_IP_NF_TARGET_ULOG=m |
| 115 | CONFIG_NF_NAT=m | 114 | CONFIG_NF_NAT=m |
| 116 | CONFIG_IP_NF_TARGET_MASQUERADE=m | 115 | CONFIG_IP_NF_TARGET_MASQUERADE=m |
| 117 | CONFIG_IP_NF_TARGET_NETMAP=m | 116 | CONFIG_IP_NF_TARGET_NETMAP=m |
| 118 | CONFIG_IP_NF_TARGET_REDIRECT=m | 117 | CONFIG_IP_NF_TARGET_REDIRECT=m |
| 119 | CONFIG_NF_NAT_SNMP_BASIC=m | 118 | CONFIG_NF_NAT_SNMP_BASIC=m |
| 120 | CONFIG_IP_NF_MANGLE=m | 119 | CONFIG_IP_NF_MANGLE=m |
| 121 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | 120 | CONFIG_IP_NF_TARGET_CLUSTERIP=m |
| 122 | CONFIG_IP_NF_TARGET_ECN=m | 121 | CONFIG_IP_NF_TARGET_ECN=m |
| 123 | CONFIG_IP_NF_TARGET_TTL=m | 122 | CONFIG_IP_NF_TARGET_TTL=m |
| 124 | CONFIG_IP_NF_RAW=m | 123 | CONFIG_IP_NF_RAW=m |
| 125 | CONFIG_IP_NF_ARPTABLES=m | 124 | CONFIG_IP_NF_ARPTABLES=m |
| 126 | CONFIG_IP_NF_ARPFILTER=m | 125 | CONFIG_IP_NF_ARPFILTER=m |
| 127 | CONFIG_IP_NF_ARP_MANGLE=m | 126 | CONFIG_IP_NF_ARP_MANGLE=m |
| 128 | CONFIG_NF_CONNTRACK_IPV6=m | 127 | CONFIG_NF_CONNTRACK_IPV6=m |
| 129 | CONFIG_IP6_NF_QUEUE=m | 128 | CONFIG_IP6_NF_QUEUE=m |
| 130 | CONFIG_IP6_NF_IPTABLES=m | 129 | CONFIG_IP6_NF_IPTABLES=m |
| 131 | CONFIG_IP6_NF_MATCH_AH=m | 130 | CONFIG_IP6_NF_MATCH_AH=m |
| 132 | CONFIG_IP6_NF_MATCH_EUI64=m | 131 | CONFIG_IP6_NF_MATCH_EUI64=m |
| 133 | CONFIG_IP6_NF_MATCH_FRAG=m | 132 | CONFIG_IP6_NF_MATCH_FRAG=m |
| 134 | CONFIG_IP6_NF_MATCH_OPTS=m | 133 | CONFIG_IP6_NF_MATCH_OPTS=m |
| 135 | CONFIG_IP6_NF_MATCH_HL=m | 134 | CONFIG_IP6_NF_MATCH_HL=m |
| 136 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | 135 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m |
| 137 | CONFIG_IP6_NF_MATCH_MH=m | 136 | CONFIG_IP6_NF_MATCH_MH=m |
| 138 | CONFIG_IP6_NF_MATCH_RT=m | 137 | CONFIG_IP6_NF_MATCH_RT=m |
| 139 | CONFIG_IP6_NF_TARGET_HL=m | 138 | CONFIG_IP6_NF_TARGET_HL=m |
| 140 | CONFIG_IP6_NF_TARGET_LOG=m | 139 | CONFIG_IP6_NF_TARGET_LOG=m |
| 141 | CONFIG_IP6_NF_FILTER=m | 140 | CONFIG_IP6_NF_FILTER=m |
| 142 | CONFIG_IP6_NF_TARGET_REJECT=m | 141 | CONFIG_IP6_NF_TARGET_REJECT=m |
| 143 | CONFIG_IP6_NF_MANGLE=m | 142 | CONFIG_IP6_NF_MANGLE=m |
| 144 | CONFIG_IP6_NF_RAW=m | 143 | CONFIG_IP6_NF_RAW=m |
| 145 | CONFIG_BRIDGE=m | 144 | CONFIG_BRIDGE=m |
| 146 | # CONFIG_BRIDGE_IGMP_SNOOPING is not set | 145 | # CONFIG_BRIDGE_IGMP_SNOOPING is not set |
| 147 | CONFIG_IEEE802154=y | 146 | CONFIG_IEEE802154=y |
| 148 | # CONFIG_WIRELESS is not set | 147 | # CONFIG_WIRELESS is not set |
| 149 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 148 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 150 | CONFIG_DEVTMPFS=y | 149 | CONFIG_DEVTMPFS=y |
| 151 | CONFIG_DEVTMPFS_MOUNT=y | 150 | CONFIG_DEVTMPFS_MOUNT=y |
| 152 | CONFIG_FW_LOADER=m | 151 | CONFIG_FW_LOADER=m |
| 153 | CONFIG_CONNECTOR=m | 152 | CONFIG_CONNECTOR=m |
| 154 | CONFIG_MTD=y | 153 | CONFIG_MTD=y |
| 155 | CONFIG_MTD_CMDLINE_PARTS=y | 154 | CONFIG_MTD_CMDLINE_PARTS=y |
| 156 | CONFIG_MTD_AFS_PARTS=y | 155 | CONFIG_MTD_AFS_PARTS=y |
| 157 | CONFIG_MTD_AR7_PARTS=y | 156 | CONFIG_MTD_AR7_PARTS=y |
| 158 | CONFIG_MTD_CHAR=y | 157 | CONFIG_MTD_CHAR=y |
| 159 | CONFIG_MTD_BLOCK=y | 158 | CONFIG_MTD_BLOCK=y |
| 160 | CONFIG_MTD_CFI=y | 159 | CONFIG_MTD_CFI=y |
| 161 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 160 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| 162 | CONFIG_MTD_CFI_GEOMETRY=y | 161 | CONFIG_MTD_CFI_GEOMETRY=y |
| 163 | # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set | 162 | # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set |
| 164 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | 163 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set |
| 165 | # CONFIG_MTD_CFI_I2 is not set | 164 | # CONFIG_MTD_CFI_I2 is not set |
| 166 | CONFIG_MTD_OTP=y | 165 | CONFIG_MTD_OTP=y |
| 167 | CONFIG_MTD_CFI_INTELEXT=y | 166 | CONFIG_MTD_CFI_INTELEXT=y |
| 168 | CONFIG_MTD_PXA2XX=y | 167 | CONFIG_MTD_PXA2XX=y |
| 169 | CONFIG_BLK_DEV_LOOP=m | 168 | CONFIG_BLK_DEV_LOOP=m |
| 170 | CONFIG_BLK_DEV_CRYPTOLOOP=m | 169 | CONFIG_BLK_DEV_CRYPTOLOOP=m |
| 171 | CONFIG_BLK_DEV_NBD=m | 170 | CONFIG_BLK_DEV_NBD=m |
| 172 | CONFIG_BLK_DEV_RAM=y | 171 | CONFIG_BLK_DEV_RAM=y |
| 173 | # CONFIG_MISC_DEVICES is not set | 172 | # CONFIG_MISC_DEVICES is not set |
| 174 | CONFIG_NETDEVICES=y | 173 | CONFIG_NETDEVICES=y |
| 175 | CONFIG_DUMMY=y | 174 | CONFIG_DUMMY=y |
| 176 | # CONFIG_NETDEV_1000 is not set | 175 | # CONFIG_NETDEV_1000 is not set |
| 177 | # CONFIG_NETDEV_10000 is not set | 176 | # CONFIG_NETDEV_10000 is not set |
| 178 | # CONFIG_WLAN is not set | 177 | # CONFIG_WLAN is not set |
| 179 | CONFIG_PPP=m | 178 | CONFIG_PPP=m |
| 180 | CONFIG_PPP_MULTILINK=y | 179 | CONFIG_PPP_MULTILINK=y |
| 181 | CONFIG_PPP_FILTER=y | 180 | CONFIG_PPP_FILTER=y |
| 182 | CONFIG_PPP_ASYNC=m | 181 | CONFIG_PPP_ASYNC=m |
| 183 | CONFIG_PPP_SYNC_TTY=m | 182 | CONFIG_PPP_SYNC_TTY=m |
| 184 | CONFIG_PPP_DEFLATE=m | 183 | CONFIG_PPP_DEFLATE=m |
| 185 | CONFIG_PPP_BSDCOMP=m | 184 | CONFIG_PPP_BSDCOMP=m |
| 186 | # CONFIG_INPUT_MOUSEDEV is not set | 185 | # CONFIG_INPUT_MOUSEDEV is not set |
| 187 | CONFIG_INPUT_EVDEV=y | 186 | CONFIG_INPUT_EVDEV=y |
| 188 | # CONFIG_KEYBOARD_ATKBD is not set | 187 | # CONFIG_KEYBOARD_ATKBD is not set |
| 189 | CONFIG_KEYBOARD_GPIO=y | 188 | CONFIG_KEYBOARD_GPIO=y |
| 190 | CONFIG_KEYBOARD_PXA27x=y | 189 | CONFIG_KEYBOARD_PXA27x=y |
| 191 | # CONFIG_INPUT_MOUSE is not set | 190 | # CONFIG_INPUT_MOUSE is not set |
| 192 | CONFIG_INPUT_TOUCHSCREEN=y | 191 | CONFIG_INPUT_TOUCHSCREEN=y |
| 193 | CONFIG_INPUT_MISC=y | 192 | CONFIG_INPUT_MISC=y |
| 194 | CONFIG_INPUT_UINPUT=y | 193 | CONFIG_INPUT_UINPUT=y |
| 195 | # CONFIG_SERIO is not set | 194 | # CONFIG_SERIO is not set |
| 196 | CONFIG_SERIAL_PXA=y | 195 | CONFIG_SERIAL_PXA=y |
| 197 | CONFIG_SERIAL_PXA_CONSOLE=y | 196 | CONFIG_SERIAL_PXA_CONSOLE=y |
| 198 | CONFIG_LEGACY_PTY_COUNT=8 | 197 | CONFIG_LEGACY_PTY_COUNT=8 |
| 199 | # CONFIG_HW_RANDOM is not set | 198 | # CONFIG_HW_RANDOM is not set |
| 200 | CONFIG_I2C=y | 199 | CONFIG_I2C=y |
| 201 | CONFIG_I2C_CHARDEV=y | 200 | CONFIG_I2C_CHARDEV=y |
| 202 | CONFIG_I2C_PXA=y | 201 | CONFIG_I2C_PXA=y |
| 203 | CONFIG_SPI=y | 202 | CONFIG_SPI=y |
| 204 | CONFIG_SPI_PXA2XX=y | 203 | CONFIG_SPI_PXA2XX=y |
| 205 | CONFIG_GPIO_SYSFS=y | 204 | CONFIG_GPIO_SYSFS=y |
| 206 | CONFIG_POWER_SUPPLY=y | 205 | CONFIG_POWER_SUPPLY=y |
| 207 | # CONFIG_HWMON is not set | 206 | # CONFIG_HWMON is not set |
| 208 | CONFIG_PMIC_DA903X=y | 207 | CONFIG_PMIC_DA903X=y |
| 209 | CONFIG_REGULATOR=y | 208 | CONFIG_REGULATOR=y |
| 210 | CONFIG_REGULATOR_DEBUG=y | 209 | CONFIG_REGULATOR_DEBUG=y |
| 211 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y | 210 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y |
| 212 | CONFIG_REGULATOR_DA903X=y | 211 | CONFIG_REGULATOR_DA903X=y |
| 213 | CONFIG_MEDIA_SUPPORT=y | 212 | CONFIG_MEDIA_SUPPORT=y |
| 214 | CONFIG_VIDEO_DEV=y | 213 | CONFIG_VIDEO_DEV=y |
| 215 | CONFIG_MEDIA_TUNER_CUSTOMISE=y | 214 | CONFIG_MEDIA_TUNER_CUSTOMISE=y |
| 216 | # CONFIG_MEDIA_TUNER_SIMPLE is not set | 215 | # CONFIG_MEDIA_TUNER_SIMPLE is not set |
| 217 | # CONFIG_MEDIA_TUNER_TDA8290 is not set | 216 | # CONFIG_MEDIA_TUNER_TDA8290 is not set |
| 218 | # CONFIG_MEDIA_TUNER_TDA827X is not set | 217 | # CONFIG_MEDIA_TUNER_TDA827X is not set |
| 219 | # CONFIG_MEDIA_TUNER_TDA18271 is not set | 218 | # CONFIG_MEDIA_TUNER_TDA18271 is not set |
| 220 | # CONFIG_MEDIA_TUNER_TDA9887 is not set | 219 | # CONFIG_MEDIA_TUNER_TDA9887 is not set |
| 221 | # CONFIG_MEDIA_TUNER_TEA5761 is not set | 220 | # CONFIG_MEDIA_TUNER_TEA5761 is not set |
| 222 | # CONFIG_MEDIA_TUNER_TEA5767 is not set | 221 | # CONFIG_MEDIA_TUNER_TEA5767 is not set |
| 223 | # CONFIG_MEDIA_TUNER_MT20XX is not set | 222 | # CONFIG_MEDIA_TUNER_MT20XX is not set |
| 224 | # CONFIG_MEDIA_TUNER_MT2060 is not set | 223 | # CONFIG_MEDIA_TUNER_MT2060 is not set |
| 225 | # CONFIG_MEDIA_TUNER_MT2266 is not set | 224 | # CONFIG_MEDIA_TUNER_MT2266 is not set |
| 226 | # CONFIG_MEDIA_TUNER_MT2131 is not set | 225 | # CONFIG_MEDIA_TUNER_MT2131 is not set |
| 227 | # CONFIG_MEDIA_TUNER_QT1010 is not set | 226 | # CONFIG_MEDIA_TUNER_QT1010 is not set |
| 228 | # CONFIG_MEDIA_TUNER_XC2028 is not set | 227 | # CONFIG_MEDIA_TUNER_XC2028 is not set |
| 229 | # CONFIG_MEDIA_TUNER_XC5000 is not set | 228 | # CONFIG_MEDIA_TUNER_XC5000 is not set |
| 230 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | 229 | # CONFIG_MEDIA_TUNER_MXL5005S is not set |
| 231 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | 230 | # CONFIG_MEDIA_TUNER_MXL5007T is not set |
| 232 | # CONFIG_MEDIA_TUNER_MC44S803 is not set | 231 | # CONFIG_MEDIA_TUNER_MC44S803 is not set |
| 233 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | 232 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set |
| 234 | CONFIG_SOC_CAMERA=y | 233 | CONFIG_SOC_CAMERA=y |
| 235 | CONFIG_SOC_CAMERA_MT9M111=y | 234 | CONFIG_SOC_CAMERA_MT9M111=y |
| 236 | CONFIG_VIDEO_PXA27x=y | 235 | CONFIG_VIDEO_PXA27x=y |
| 237 | # CONFIG_V4L_USB_DRIVERS is not set | 236 | # CONFIG_V4L_USB_DRIVERS is not set |
| 238 | # CONFIG_RADIO_ADAPTERS is not set | 237 | # CONFIG_RADIO_ADAPTERS is not set |
| 239 | CONFIG_FB=y | 238 | CONFIG_FB=y |
| 240 | CONFIG_FB_PXA=y | 239 | CONFIG_FB_PXA=y |
| 241 | CONFIG_FB_PXA_OVERLAY=y | 240 | CONFIG_FB_PXA_OVERLAY=y |
| 242 | CONFIG_FB_PXA_PARAMETERS=y | 241 | CONFIG_FB_PXA_PARAMETERS=y |
| 243 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 242 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 244 | # CONFIG_LCD_CLASS_DEVICE is not set | 243 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 245 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 244 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 246 | # CONFIG_VGA_CONSOLE is not set | 245 | # CONFIG_VGA_CONSOLE is not set |
| 247 | CONFIG_FRAMEBUFFER_CONSOLE=y | 246 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 248 | CONFIG_FONTS=y | 247 | CONFIG_FONTS=y |
| 249 | CONFIG_FONT_MINI_4x6=y | 248 | CONFIG_FONT_MINI_4x6=y |
| 250 | CONFIG_SOUND=y | 249 | CONFIG_SOUND=y |
| 251 | CONFIG_SND=y | 250 | CONFIG_SND=y |
| 252 | CONFIG_SND_MIXER_OSS=y | 251 | CONFIG_SND_MIXER_OSS=y |
| 253 | CONFIG_SND_PCM_OSS=y | 252 | CONFIG_SND_PCM_OSS=y |
| 254 | # CONFIG_SND_DRIVERS is not set | 253 | # CONFIG_SND_DRIVERS is not set |
| 255 | # CONFIG_SND_ARM is not set | 254 | # CONFIG_SND_ARM is not set |
| 256 | # CONFIG_SND_SPI is not set | 255 | # CONFIG_SND_SPI is not set |
| 257 | # CONFIG_SND_USB is not set | 256 | # CONFIG_SND_USB is not set |
| 258 | CONFIG_SND_SOC=y | 257 | CONFIG_SND_SOC=y |
| 259 | CONFIG_SND_PXA2XX_SOC=y | 258 | CONFIG_SND_PXA2XX_SOC=y |
| 260 | # CONFIG_USB_HID is not set | 259 | # CONFIG_USB_HID is not set |
| 261 | CONFIG_USB=y | 260 | CONFIG_USB=y |
| 262 | # CONFIG_USB_DEVICE_CLASS is not set | 261 | # CONFIG_USB_DEVICE_CLASS is not set |
| 263 | CONFIG_USB_OHCI_HCD=y | 262 | CONFIG_USB_OHCI_HCD=y |
| 264 | CONFIG_USB_GADGET=y | 263 | CONFIG_USB_GADGET=y |
| 265 | CONFIG_USB_PXA27X=y | 264 | CONFIG_USB_PXA27X=y |
| 266 | CONFIG_USB_ETH=m | 265 | CONFIG_USB_ETH=m |
| 267 | # CONFIG_USB_ETH_RNDIS is not set | 266 | # CONFIG_USB_ETH_RNDIS is not set |
| 268 | CONFIG_MMC=y | 267 | CONFIG_MMC=y |
| 269 | CONFIG_MMC_UNSAFE_RESUME=y | 268 | CONFIG_MMC_UNSAFE_RESUME=y |
| 270 | CONFIG_SDIO_UART=m | 269 | CONFIG_SDIO_UART=m |
| 271 | CONFIG_MMC_PXA=y | 270 | CONFIG_MMC_PXA=y |
| 272 | CONFIG_MMC_SPI=y | 271 | CONFIG_MMC_SPI=y |
| 273 | CONFIG_NEW_LEDS=y | 272 | CONFIG_NEW_LEDS=y |
| 274 | CONFIG_LEDS_CLASS=y | 273 | CONFIG_LEDS_CLASS=y |
| 275 | CONFIG_LEDS_LP3944=y | 274 | CONFIG_LEDS_LP3944=y |
| 276 | CONFIG_LEDS_TRIGGERS=y | 275 | CONFIG_LEDS_TRIGGERS=y |
| 277 | CONFIG_LEDS_TRIGGER_TIMER=y | 276 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 278 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 277 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 279 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | 278 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y |
| 280 | CONFIG_LEDS_TRIGGER_GPIO=y | 279 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 281 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 280 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 282 | CONFIG_RTC_CLASS=y | 281 | CONFIG_RTC_CLASS=y |
| 283 | CONFIG_RTC_DRV_PXA=y | 282 | CONFIG_RTC_DRV_PXA=y |
| 284 | CONFIG_EXT2_FS=y | 283 | CONFIG_EXT2_FS=y |
| 285 | CONFIG_EXT3_FS=m | 284 | CONFIG_EXT3_FS=m |
| 286 | CONFIG_INOTIFY=y | 285 | CONFIG_INOTIFY=y |
| 287 | CONFIG_AUTOFS_FS=y | 286 | CONFIG_AUTOFS_FS=y |
| 288 | CONFIG_AUTOFS4_FS=y | 287 | CONFIG_AUTOFS4_FS=y |
| 289 | CONFIG_FUSE_FS=m | 288 | CONFIG_FUSE_FS=m |
| 290 | CONFIG_CUSE=m | 289 | CONFIG_CUSE=m |
| 291 | CONFIG_MSDOS_FS=m | 290 | CONFIG_MSDOS_FS=m |
| 292 | CONFIG_VFAT_FS=m | 291 | CONFIG_VFAT_FS=m |
| 293 | CONFIG_TMPFS=y | 292 | CONFIG_TMPFS=y |
| 294 | CONFIG_JFFS2_FS=y | 293 | CONFIG_JFFS2_FS=y |
| 295 | CONFIG_JFFS2_FS_WBUF_VERIFY=y | 294 | CONFIG_JFFS2_FS_WBUF_VERIFY=y |
| 296 | CONFIG_JFFS2_SUMMARY=y | 295 | CONFIG_JFFS2_SUMMARY=y |
| 297 | CONFIG_JFFS2_FS_XATTR=y | 296 | CONFIG_JFFS2_FS_XATTR=y |
| 298 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | 297 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y |
| 299 | CONFIG_JFFS2_LZO=y | 298 | CONFIG_JFFS2_LZO=y |
| 300 | CONFIG_JFFS2_RUBIN=y | 299 | CONFIG_JFFS2_RUBIN=y |
| 301 | CONFIG_CRAMFS=m | 300 | CONFIG_CRAMFS=m |
| 302 | CONFIG_SQUASHFS=m | 301 | CONFIG_SQUASHFS=m |
| 303 | CONFIG_ROMFS_FS=m | 302 | CONFIG_ROMFS_FS=m |
| 304 | CONFIG_NFS_FS=y | 303 | CONFIG_NFS_FS=y |
| 305 | CONFIG_NFS_V3=y | 304 | CONFIG_NFS_V3=y |
| 306 | CONFIG_NFS_V3_ACL=y | 305 | CONFIG_NFS_V3_ACL=y |
| 307 | CONFIG_NFSD=m | 306 | CONFIG_NFSD=m |
| 308 | CONFIG_NFSD_V3=y | 307 | CONFIG_NFSD_V3=y |
| 309 | CONFIG_NFSD_V3_ACL=y | 308 | CONFIG_NFSD_V3_ACL=y |
| 310 | CONFIG_SMB_FS=m | 309 | CONFIG_SMB_FS=m |
| 311 | CONFIG_CIFS=m | 310 | CONFIG_CIFS=m |
| 312 | CONFIG_CIFS_STATS=y | 311 | CONFIG_CIFS_STATS=y |
| 313 | CONFIG_CIFS_WEAK_PW_HASH=y | 312 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 314 | CONFIG_CIFS_XATTR=y | 313 | CONFIG_CIFS_XATTR=y |
| 315 | CONFIG_CIFS_POSIX=y | 314 | CONFIG_CIFS_POSIX=y |
| 316 | CONFIG_NLS_CODEPAGE_437=m | 315 | CONFIG_NLS_CODEPAGE_437=m |
| 317 | CONFIG_NLS_CODEPAGE_737=m | 316 | CONFIG_NLS_CODEPAGE_737=m |
| 318 | CONFIG_NLS_CODEPAGE_775=m | 317 | CONFIG_NLS_CODEPAGE_775=m |
| 319 | CONFIG_NLS_CODEPAGE_850=m | 318 | CONFIG_NLS_CODEPAGE_850=m |
| 320 | CONFIG_NLS_CODEPAGE_852=m | 319 | CONFIG_NLS_CODEPAGE_852=m |
| 321 | CONFIG_NLS_CODEPAGE_855=m | 320 | CONFIG_NLS_CODEPAGE_855=m |
| 322 | CONFIG_NLS_CODEPAGE_857=m | 321 | CONFIG_NLS_CODEPAGE_857=m |
| 323 | CONFIG_NLS_CODEPAGE_860=m | 322 | CONFIG_NLS_CODEPAGE_860=m |
| 324 | CONFIG_NLS_CODEPAGE_861=m | 323 | CONFIG_NLS_CODEPAGE_861=m |
| 325 | CONFIG_NLS_CODEPAGE_862=m | 324 | CONFIG_NLS_CODEPAGE_862=m |
| 326 | CONFIG_NLS_CODEPAGE_863=m | 325 | CONFIG_NLS_CODEPAGE_863=m |
| 327 | CONFIG_NLS_CODEPAGE_864=m | 326 | CONFIG_NLS_CODEPAGE_864=m |
| 328 | CONFIG_NLS_CODEPAGE_865=m | 327 | CONFIG_NLS_CODEPAGE_865=m |
| 329 | CONFIG_NLS_CODEPAGE_866=m | 328 | CONFIG_NLS_CODEPAGE_866=m |
| 330 | CONFIG_NLS_CODEPAGE_869=m | 329 | CONFIG_NLS_CODEPAGE_869=m |
| 331 | CONFIG_NLS_CODEPAGE_936=m | 330 | CONFIG_NLS_CODEPAGE_936=m |
| 332 | CONFIG_NLS_CODEPAGE_950=m | 331 | CONFIG_NLS_CODEPAGE_950=m |
| 333 | CONFIG_NLS_CODEPAGE_932=m | 332 | CONFIG_NLS_CODEPAGE_932=m |
| 334 | CONFIG_NLS_CODEPAGE_949=m | 333 | CONFIG_NLS_CODEPAGE_949=m |
| 335 | CONFIG_NLS_CODEPAGE_874=m | 334 | CONFIG_NLS_CODEPAGE_874=m |
| 336 | CONFIG_NLS_ISO8859_8=m | 335 | CONFIG_NLS_ISO8859_8=m |
| 337 | CONFIG_NLS_CODEPAGE_1250=m | 336 | CONFIG_NLS_CODEPAGE_1250=m |
| 338 | CONFIG_NLS_CODEPAGE_1251=m | 337 | CONFIG_NLS_CODEPAGE_1251=m |
| 339 | CONFIG_NLS_ASCII=m | 338 | CONFIG_NLS_ASCII=m |
| 340 | CONFIG_NLS_ISO8859_1=m | 339 | CONFIG_NLS_ISO8859_1=m |
| 341 | CONFIG_NLS_ISO8859_2=m | 340 | CONFIG_NLS_ISO8859_2=m |
| 342 | CONFIG_NLS_ISO8859_3=m | 341 | CONFIG_NLS_ISO8859_3=m |
| 343 | CONFIG_NLS_ISO8859_4=m | 342 | CONFIG_NLS_ISO8859_4=m |
| 344 | CONFIG_NLS_ISO8859_5=m | 343 | CONFIG_NLS_ISO8859_5=m |
| 345 | CONFIG_NLS_ISO8859_6=m | 344 | CONFIG_NLS_ISO8859_6=m |
| 346 | CONFIG_NLS_ISO8859_7=m | 345 | CONFIG_NLS_ISO8859_7=m |
| 347 | CONFIG_NLS_ISO8859_9=m | 346 | CONFIG_NLS_ISO8859_9=m |
| 348 | CONFIG_NLS_ISO8859_13=m | 347 | CONFIG_NLS_ISO8859_13=m |
| 349 | CONFIG_NLS_ISO8859_14=m | 348 | CONFIG_NLS_ISO8859_14=m |
| 350 | CONFIG_NLS_ISO8859_15=m | 349 | CONFIG_NLS_ISO8859_15=m |
| 351 | CONFIG_NLS_KOI8_R=m | 350 | CONFIG_NLS_KOI8_R=m |
| 352 | CONFIG_NLS_KOI8_U=m | 351 | CONFIG_NLS_KOI8_U=m |
| 353 | CONFIG_NLS_UTF8=m | 352 | CONFIG_NLS_UTF8=m |
| 354 | CONFIG_PRINTK_TIME=y | 353 | CONFIG_PRINTK_TIME=y |
| 355 | CONFIG_DEBUG_FS=y | 354 | CONFIG_DEBUG_FS=y |
| 356 | CONFIG_DEBUG_KERNEL=y | 355 | CONFIG_DEBUG_KERNEL=y |
| 357 | # CONFIG_SCHED_DEBUG is not set | 356 | # CONFIG_SCHED_DEBUG is not set |
| 358 | CONFIG_DEBUG_RT_MUTEXES=y | 357 | CONFIG_DEBUG_RT_MUTEXES=y |
| 359 | CONFIG_PROVE_LOCKING=y | 358 | CONFIG_PROVE_LOCKING=y |
| 360 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 359 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 361 | # CONFIG_FTRACE is not set | 360 | # CONFIG_FTRACE is not set |
| 362 | CONFIG_DEBUG_USER=y | 361 | CONFIG_DEBUG_USER=y |
| 363 | CONFIG_DEBUG_ERRORS=y | 362 | CONFIG_DEBUG_ERRORS=y |
| 364 | CONFIG_CRYPTO_NULL=m | 363 | CONFIG_CRYPTO_NULL=m |
| 365 | CONFIG_CRYPTO_CRYPTD=m | 364 | CONFIG_CRYPTO_CRYPTD=m |
| 366 | CONFIG_CRYPTO_TEST=m | 365 | CONFIG_CRYPTO_TEST=m |
| 367 | CONFIG_CRYPTO_ECB=m | 366 | CONFIG_CRYPTO_ECB=m |
| 368 | CONFIG_CRYPTO_LRW=m | 367 | CONFIG_CRYPTO_LRW=m |
| 369 | CONFIG_CRYPTO_PCBC=m | 368 | CONFIG_CRYPTO_PCBC=m |
| 370 | CONFIG_CRYPTO_XTS=m | 369 | CONFIG_CRYPTO_XTS=m |
| 371 | CONFIG_CRYPTO_XCBC=m | 370 | CONFIG_CRYPTO_XCBC=m |
| 372 | CONFIG_CRYPTO_VMAC=m | 371 | CONFIG_CRYPTO_VMAC=m |
| 373 | CONFIG_CRYPTO_GHASH=m | 372 | CONFIG_CRYPTO_GHASH=m |
| 374 | CONFIG_CRYPTO_MD4=m | 373 | CONFIG_CRYPTO_MD4=m |
| 375 | CONFIG_CRYPTO_MICHAEL_MIC=m | 374 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 376 | CONFIG_CRYPTO_SHA256=m | 375 | CONFIG_CRYPTO_SHA256=m |
| 377 | CONFIG_CRYPTO_SHA512=m | 376 | CONFIG_CRYPTO_SHA512=m |
| 378 | CONFIG_CRYPTO_TGR192=m | 377 | CONFIG_CRYPTO_TGR192=m |
| 379 | CONFIG_CRYPTO_AES=m | 378 | CONFIG_CRYPTO_AES=m |
| 380 | CONFIG_CRYPTO_ARC4=m | 379 | CONFIG_CRYPTO_ARC4=m |
| 381 | CONFIG_CRYPTO_BLOWFISH=m | 380 | CONFIG_CRYPTO_BLOWFISH=m |
| 382 | CONFIG_CRYPTO_CAST5=m | 381 | CONFIG_CRYPTO_CAST5=m |
| 383 | CONFIG_CRYPTO_CAST6=m | 382 | CONFIG_CRYPTO_CAST6=m |
| 384 | CONFIG_CRYPTO_FCRYPT=m | 383 | CONFIG_CRYPTO_FCRYPT=m |
| 385 | CONFIG_CRYPTO_KHAZAD=m | 384 | CONFIG_CRYPTO_KHAZAD=m |
| 386 | CONFIG_CRYPTO_SEED=m | 385 | CONFIG_CRYPTO_SEED=m |
| 387 | CONFIG_CRYPTO_SERPENT=m | 386 | CONFIG_CRYPTO_SERPENT=m |
| 388 | CONFIG_CRYPTO_TEA=m | 387 | CONFIG_CRYPTO_TEA=m |
| 389 | CONFIG_CRYPTO_TWOFISH=m | 388 | CONFIG_CRYPTO_TWOFISH=m |
| 390 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 389 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 391 | CONFIG_CRC16=y | 390 | CONFIG_CRC16=y |
| 392 | 391 |
arch/arm/configs/imx_v6_v7_defconfig
| 1 | CONFIG_KERNEL_LZO=y | 1 | CONFIG_KERNEL_LZO=y |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_FHANDLE=y | 3 | CONFIG_FHANDLE=y |
| 4 | CONFIG_NO_HZ=y | 4 | CONFIG_NO_HZ=y |
| 5 | CONFIG_HIGH_RES_TIMERS=y | 5 | CONFIG_HIGH_RES_TIMERS=y |
| 6 | CONFIG_LOG_BUF_SHIFT=18 | 6 | CONFIG_LOG_BUF_SHIFT=18 |
| 7 | CONFIG_CGROUPS=y | 7 | CONFIG_CGROUPS=y |
| 8 | CONFIG_RELAY=y | 8 | CONFIG_RELAY=y |
| 9 | CONFIG_BLK_DEV_INITRD=y | 9 | CONFIG_BLK_DEV_INITRD=y |
| 10 | CONFIG_EXPERT=y | 10 | CONFIG_EXPERT=y |
| 11 | CONFIG_PERF_EVENTS=y | 11 | CONFIG_PERF_EVENTS=y |
| 12 | # CONFIG_SLUB_DEBUG is not set | 12 | # CONFIG_SLUB_DEBUG is not set |
| 13 | # CONFIG_COMPAT_BRK is not set | 13 | # CONFIG_COMPAT_BRK is not set |
| 14 | CONFIG_MODULES=y | 14 | CONFIG_MODULES=y |
| 15 | CONFIG_MODULE_UNLOAD=y | 15 | CONFIG_MODULE_UNLOAD=y |
| 16 | CONFIG_MODVERSIONS=y | 16 | CONFIG_MODVERSIONS=y |
| 17 | CONFIG_MODULE_SRCVERSION_ALL=y | 17 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 18 | # CONFIG_BLK_DEV_BSG is not set | 18 | # CONFIG_BLK_DEV_BSG is not set |
| 19 | CONFIG_ARCH_MULTI_V6=y | 19 | CONFIG_ARCH_MULTI_V6=y |
| 20 | CONFIG_ARCH_MXC=y | 20 | CONFIG_ARCH_MXC=y |
| 21 | CONFIG_MACH_MX31LILLY=y | 21 | CONFIG_MACH_MX31LILLY=y |
| 22 | CONFIG_MACH_MX31LITE=y | 22 | CONFIG_MACH_MX31LITE=y |
| 23 | CONFIG_MACH_PCM037=y | 23 | CONFIG_MACH_PCM037=y |
| 24 | CONFIG_MACH_PCM037_EET=y | 24 | CONFIG_MACH_PCM037_EET=y |
| 25 | CONFIG_MACH_MX31_3DS=y | 25 | CONFIG_MACH_MX31_3DS=y |
| 26 | CONFIG_MACH_MX31MOBOARD=y | 26 | CONFIG_MACH_MX31MOBOARD=y |
| 27 | CONFIG_MACH_QONG=y | 27 | CONFIG_MACH_QONG=y |
| 28 | CONFIG_MACH_ARMADILLO5X0=y | 28 | CONFIG_MACH_ARMADILLO5X0=y |
| 29 | CONFIG_MACH_KZM_ARM11_01=y | 29 | CONFIG_MACH_KZM_ARM11_01=y |
| 30 | CONFIG_MACH_IMX31_DT=y | 30 | CONFIG_MACH_IMX31_DT=y |
| 31 | CONFIG_MACH_IMX35_DT=y | 31 | CONFIG_MACH_IMX35_DT=y |
| 32 | CONFIG_MACH_PCM043=y | 32 | CONFIG_MACH_PCM043=y |
| 33 | CONFIG_MACH_MX35_3DS=y | 33 | CONFIG_MACH_MX35_3DS=y |
| 34 | CONFIG_MACH_VPR200=y | 34 | CONFIG_MACH_VPR200=y |
| 35 | CONFIG_SOC_IMX50=y | 35 | CONFIG_SOC_IMX50=y |
| 36 | CONFIG_SOC_IMX51=y | 36 | CONFIG_SOC_IMX51=y |
| 37 | CONFIG_SOC_IMX53=y | 37 | CONFIG_SOC_IMX53=y |
| 38 | CONFIG_SOC_IMX6Q=y | 38 | CONFIG_SOC_IMX6Q=y |
| 39 | CONFIG_SOC_IMX6SL=y | 39 | CONFIG_SOC_IMX6SL=y |
| 40 | CONFIG_SOC_IMX6SX=y | 40 | CONFIG_SOC_IMX6SX=y |
| 41 | CONFIG_SOC_VF610=y | 41 | CONFIG_SOC_VF610=y |
| 42 | CONFIG_PCI=y | 42 | CONFIG_PCI=y |
| 43 | CONFIG_PCI_IMX6=y | 43 | CONFIG_PCI_IMX6=y |
| 44 | CONFIG_SMP=y | 44 | CONFIG_SMP=y |
| 45 | CONFIG_VMSPLIT_2G=y | 45 | CONFIG_VMSPLIT_2G=y |
| 46 | CONFIG_PREEMPT_VOLUNTARY=y | 46 | CONFIG_PREEMPT_VOLUNTARY=y |
| 47 | CONFIG_AEABI=y | 47 | CONFIG_AEABI=y |
| 48 | CONFIG_HIGHMEM=y | 48 | CONFIG_HIGHMEM=y |
| 49 | CONFIG_CMA=y | 49 | CONFIG_CMA=y |
| 50 | CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" | 50 | CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" |
| 51 | CONFIG_CPU_FREQ=y | 51 | CONFIG_CPU_FREQ=y |
| 52 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | 52 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y |
| 53 | CONFIG_ARM_IMX6Q_CPUFREQ=y | 53 | CONFIG_ARM_IMX6Q_CPUFREQ=y |
| 54 | CONFIG_VFP=y | 54 | CONFIG_VFP=y |
| 55 | CONFIG_NEON=y | 55 | CONFIG_NEON=y |
| 56 | CONFIG_BINFMT_MISC=m | 56 | CONFIG_BINFMT_MISC=m |
| 57 | CONFIG_PM_RUNTIME=y | 57 | CONFIG_PM=y |
| 58 | CONFIG_PM_DEBUG=y | 58 | CONFIG_PM_DEBUG=y |
| 59 | CONFIG_PM_TEST_SUSPEND=y | 59 | CONFIG_PM_TEST_SUSPEND=y |
| 60 | CONFIG_NET=y | 60 | CONFIG_NET=y |
| 61 | CONFIG_PACKET=y | 61 | CONFIG_PACKET=y |
| 62 | CONFIG_UNIX=y | 62 | CONFIG_UNIX=y |
| 63 | CONFIG_INET=y | 63 | CONFIG_INET=y |
| 64 | CONFIG_IP_PNP=y | 64 | CONFIG_IP_PNP=y |
| 65 | CONFIG_IP_PNP_DHCP=y | 65 | CONFIG_IP_PNP_DHCP=y |
| 66 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 66 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 67 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 67 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 68 | # CONFIG_INET_XFRM_MODE_BEET is not set | 68 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 69 | # CONFIG_INET_LRO is not set | 69 | # CONFIG_INET_LRO is not set |
| 70 | CONFIG_IPV6=y | 70 | CONFIG_IPV6=y |
| 71 | CONFIG_NETFILTER=y | 71 | CONFIG_NETFILTER=y |
| 72 | CONFIG_CAN=y | 72 | CONFIG_CAN=y |
| 73 | CONFIG_CAN_FLEXCAN=y | 73 | CONFIG_CAN_FLEXCAN=y |
| 74 | CONFIG_CFG80211=y | 74 | CONFIG_CFG80211=y |
| 75 | CONFIG_MAC80211=y | 75 | CONFIG_MAC80211=y |
| 76 | CONFIG_RFKILL=y | 76 | CONFIG_RFKILL=y |
| 77 | CONFIG_RFKILL_INPUT=y | 77 | CONFIG_RFKILL_INPUT=y |
| 78 | CONFIG_DEVTMPFS=y | 78 | CONFIG_DEVTMPFS=y |
| 79 | CONFIG_DEVTMPFS_MOUNT=y | 79 | CONFIG_DEVTMPFS_MOUNT=y |
| 80 | # CONFIG_STANDALONE is not set | 80 | # CONFIG_STANDALONE is not set |
| 81 | CONFIG_DMA_CMA=y | 81 | CONFIG_DMA_CMA=y |
| 82 | CONFIG_IMX_WEIM=y | 82 | CONFIG_IMX_WEIM=y |
| 83 | CONFIG_CONNECTOR=y | 83 | CONFIG_CONNECTOR=y |
| 84 | CONFIG_MTD=y | 84 | CONFIG_MTD=y |
| 85 | CONFIG_MTD_CMDLINE_PARTS=y | 85 | CONFIG_MTD_CMDLINE_PARTS=y |
| 86 | CONFIG_MTD_BLOCK=y | 86 | CONFIG_MTD_BLOCK=y |
| 87 | CONFIG_MTD_CFI=y | 87 | CONFIG_MTD_CFI=y |
| 88 | CONFIG_MTD_JEDECPROBE=y | 88 | CONFIG_MTD_JEDECPROBE=y |
| 89 | CONFIG_MTD_CFI_INTELEXT=y | 89 | CONFIG_MTD_CFI_INTELEXT=y |
| 90 | CONFIG_MTD_CFI_AMDSTD=y | 90 | CONFIG_MTD_CFI_AMDSTD=y |
| 91 | CONFIG_MTD_CFI_STAA=y | 91 | CONFIG_MTD_CFI_STAA=y |
| 92 | CONFIG_MTD_PHYSMAP_OF=y | 92 | CONFIG_MTD_PHYSMAP_OF=y |
| 93 | CONFIG_MTD_DATAFLASH=y | 93 | CONFIG_MTD_DATAFLASH=y |
| 94 | CONFIG_MTD_M25P80=y | 94 | CONFIG_MTD_M25P80=y |
| 95 | CONFIG_MTD_SST25L=y | 95 | CONFIG_MTD_SST25L=y |
| 96 | CONFIG_MTD_NAND=y | 96 | CONFIG_MTD_NAND=y |
| 97 | CONFIG_MTD_NAND_GPMI_NAND=y | 97 | CONFIG_MTD_NAND_GPMI_NAND=y |
| 98 | CONFIG_MTD_NAND_MXC=y | 98 | CONFIG_MTD_NAND_MXC=y |
| 99 | CONFIG_MTD_SPI_NOR=y | 99 | CONFIG_MTD_SPI_NOR=y |
| 100 | CONFIG_MTD_UBI=y | 100 | CONFIG_MTD_UBI=y |
| 101 | CONFIG_BLK_DEV_LOOP=y | 101 | CONFIG_BLK_DEV_LOOP=y |
| 102 | CONFIG_BLK_DEV_RAM=y | 102 | CONFIG_BLK_DEV_RAM=y |
| 103 | CONFIG_BLK_DEV_RAM_SIZE=65536 | 103 | CONFIG_BLK_DEV_RAM_SIZE=65536 |
| 104 | CONFIG_EEPROM_AT24=y | 104 | CONFIG_EEPROM_AT24=y |
| 105 | CONFIG_EEPROM_AT25=y | 105 | CONFIG_EEPROM_AT25=y |
| 106 | # CONFIG_SCSI_PROC_FS is not set | 106 | # CONFIG_SCSI_PROC_FS is not set |
| 107 | CONFIG_BLK_DEV_SD=y | 107 | CONFIG_BLK_DEV_SD=y |
| 108 | CONFIG_SCSI_CONSTANTS=y | 108 | CONFIG_SCSI_CONSTANTS=y |
| 109 | CONFIG_SCSI_LOGGING=y | 109 | CONFIG_SCSI_LOGGING=y |
| 110 | CONFIG_SCSI_SCAN_ASYNC=y | 110 | CONFIG_SCSI_SCAN_ASYNC=y |
| 111 | # CONFIG_SCSI_LOWLEVEL is not set | 111 | # CONFIG_SCSI_LOWLEVEL is not set |
| 112 | CONFIG_ATA=y | 112 | CONFIG_ATA=y |
| 113 | CONFIG_SATA_AHCI_PLATFORM=y | 113 | CONFIG_SATA_AHCI_PLATFORM=y |
| 114 | CONFIG_AHCI_IMX=y | 114 | CONFIG_AHCI_IMX=y |
| 115 | CONFIG_PATA_IMX=y | 115 | CONFIG_PATA_IMX=y |
| 116 | CONFIG_NETDEVICES=y | 116 | CONFIG_NETDEVICES=y |
| 117 | # CONFIG_NET_VENDOR_BROADCOM is not set | 117 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 118 | CONFIG_CS89x0=y | 118 | CONFIG_CS89x0=y |
| 119 | CONFIG_CS89x0_PLATFORM=y | 119 | CONFIG_CS89x0_PLATFORM=y |
| 120 | # CONFIG_NET_VENDOR_FARADAY is not set | 120 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 121 | # CONFIG_NET_VENDOR_INTEL is not set | 121 | # CONFIG_NET_VENDOR_INTEL is not set |
| 122 | # CONFIG_NET_VENDOR_MARVELL is not set | 122 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 123 | # CONFIG_NET_VENDOR_MICREL is not set | 123 | # CONFIG_NET_VENDOR_MICREL is not set |
| 124 | # CONFIG_NET_VENDOR_MICROCHIP is not set | 124 | # CONFIG_NET_VENDOR_MICROCHIP is not set |
| 125 | # CONFIG_NET_VENDOR_NATSEMI is not set | 125 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 126 | # CONFIG_NET_VENDOR_SEEQ is not set | 126 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 127 | CONFIG_SMC91X=y | 127 | CONFIG_SMC91X=y |
| 128 | CONFIG_SMC911X=y | 128 | CONFIG_SMC911X=y |
| 129 | CONFIG_SMSC911X=y | 129 | CONFIG_SMSC911X=y |
| 130 | # CONFIG_NET_VENDOR_STMICRO is not set | 130 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 131 | CONFIG_AT803X_PHY=y | 131 | CONFIG_AT803X_PHY=y |
| 132 | CONFIG_BRCMFMAC=m | 132 | CONFIG_BRCMFMAC=m |
| 133 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 133 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 134 | CONFIG_INPUT_EVDEV=y | 134 | CONFIG_INPUT_EVDEV=y |
| 135 | CONFIG_INPUT_EVBUG=m | 135 | CONFIG_INPUT_EVBUG=m |
| 136 | CONFIG_KEYBOARD_GPIO=y | 136 | CONFIG_KEYBOARD_GPIO=y |
| 137 | CONFIG_KEYBOARD_IMX=y | 137 | CONFIG_KEYBOARD_IMX=y |
| 138 | CONFIG_MOUSE_PS2=m | 138 | CONFIG_MOUSE_PS2=m |
| 139 | CONFIG_MOUSE_PS2_ELANTECH=y | 139 | CONFIG_MOUSE_PS2_ELANTECH=y |
| 140 | CONFIG_INPUT_TOUCHSCREEN=y | 140 | CONFIG_INPUT_TOUCHSCREEN=y |
| 141 | CONFIG_TOUCHSCREEN_EGALAX=y | 141 | CONFIG_TOUCHSCREEN_EGALAX=y |
| 142 | CONFIG_TOUCHSCREEN_MC13783=y | 142 | CONFIG_TOUCHSCREEN_MC13783=y |
| 143 | CONFIG_TOUCHSCREEN_TSC2007=y | 143 | CONFIG_TOUCHSCREEN_TSC2007=y |
| 144 | CONFIG_TOUCHSCREEN_STMPE=y | 144 | CONFIG_TOUCHSCREEN_STMPE=y |
| 145 | CONFIG_INPUT_MISC=y | 145 | CONFIG_INPUT_MISC=y |
| 146 | CONFIG_INPUT_MMA8450=y | 146 | CONFIG_INPUT_MMA8450=y |
| 147 | CONFIG_SERIO_SERPORT=m | 147 | CONFIG_SERIO_SERPORT=m |
| 148 | # CONFIG_LEGACY_PTYS is not set | 148 | # CONFIG_LEGACY_PTYS is not set |
| 149 | # CONFIG_DEVKMEM is not set | 149 | # CONFIG_DEVKMEM is not set |
| 150 | CONFIG_SERIAL_IMX=y | 150 | CONFIG_SERIAL_IMX=y |
| 151 | CONFIG_SERIAL_IMX_CONSOLE=y | 151 | CONFIG_SERIAL_IMX_CONSOLE=y |
| 152 | CONFIG_SERIAL_FSL_LPUART=y | 152 | CONFIG_SERIAL_FSL_LPUART=y |
| 153 | CONFIG_SERIAL_FSL_LPUART_CONSOLE=y | 153 | CONFIG_SERIAL_FSL_LPUART_CONSOLE=y |
| 154 | CONFIG_HW_RANDOM=y | 154 | CONFIG_HW_RANDOM=y |
| 155 | # CONFIG_I2C_COMPAT is not set | 155 | # CONFIG_I2C_COMPAT is not set |
| 156 | CONFIG_I2C_CHARDEV=y | 156 | CONFIG_I2C_CHARDEV=y |
| 157 | # CONFIG_I2C_HELPER_AUTO is not set | 157 | # CONFIG_I2C_HELPER_AUTO is not set |
| 158 | CONFIG_I2C_ALGOPCF=m | 158 | CONFIG_I2C_ALGOPCF=m |
| 159 | CONFIG_I2C_ALGOPCA=m | 159 | CONFIG_I2C_ALGOPCA=m |
| 160 | CONFIG_I2C_IMX=y | 160 | CONFIG_I2C_IMX=y |
| 161 | CONFIG_SPI=y | 161 | CONFIG_SPI=y |
| 162 | CONFIG_SPI_IMX=y | 162 | CONFIG_SPI_IMX=y |
| 163 | CONFIG_GPIO_SYSFS=y | 163 | CONFIG_GPIO_SYSFS=y |
| 164 | CONFIG_GPIO_MC9S08DZ60=y | 164 | CONFIG_GPIO_MC9S08DZ60=y |
| 165 | CONFIG_GPIO_STMPE=y | 165 | CONFIG_GPIO_STMPE=y |
| 166 | CONFIG_SENSORS_GPIO_FAN=y | 166 | CONFIG_SENSORS_GPIO_FAN=y |
| 167 | CONFIG_THERMAL=y | 167 | CONFIG_THERMAL=y |
| 168 | CONFIG_CPU_THERMAL=y | 168 | CONFIG_CPU_THERMAL=y |
| 169 | CONFIG_IMX_THERMAL=y | 169 | CONFIG_IMX_THERMAL=y |
| 170 | CONFIG_POWER_SUPPLY=y | 170 | CONFIG_POWER_SUPPLY=y |
| 171 | CONFIG_POWER_RESET=y | 171 | CONFIG_POWER_RESET=y |
| 172 | CONFIG_POWER_RESET_IMX=y | 172 | CONFIG_POWER_RESET_IMX=y |
| 173 | CONFIG_WATCHDOG=y | 173 | CONFIG_WATCHDOG=y |
| 174 | CONFIG_IMX2_WDT=y | 174 | CONFIG_IMX2_WDT=y |
| 175 | CONFIG_MFD_DA9052_I2C=y | 175 | CONFIG_MFD_DA9052_I2C=y |
| 176 | CONFIG_MFD_MC13XXX_SPI=y | 176 | CONFIG_MFD_MC13XXX_SPI=y |
| 177 | CONFIG_MFD_MC13XXX_I2C=y | 177 | CONFIG_MFD_MC13XXX_I2C=y |
| 178 | CONFIG_MFD_STMPE=y | 178 | CONFIG_MFD_STMPE=y |
| 179 | CONFIG_REGULATOR=y | 179 | CONFIG_REGULATOR=y |
| 180 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 180 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 181 | CONFIG_REGULATOR_ANATOP=y | 181 | CONFIG_REGULATOR_ANATOP=y |
| 182 | CONFIG_REGULATOR_DA9052=y | 182 | CONFIG_REGULATOR_DA9052=y |
| 183 | CONFIG_REGULATOR_GPIO=y | 183 | CONFIG_REGULATOR_GPIO=y |
| 184 | CONFIG_REGULATOR_MC13783=y | 184 | CONFIG_REGULATOR_MC13783=y |
| 185 | CONFIG_REGULATOR_MC13892=y | 185 | CONFIG_REGULATOR_MC13892=y |
| 186 | CONFIG_REGULATOR_PFUZE100=y | 186 | CONFIG_REGULATOR_PFUZE100=y |
| 187 | CONFIG_MEDIA_SUPPORT=y | 187 | CONFIG_MEDIA_SUPPORT=y |
| 188 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 188 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 189 | CONFIG_MEDIA_RC_SUPPORT=y | 189 | CONFIG_MEDIA_RC_SUPPORT=y |
| 190 | CONFIG_RC_DEVICES=y | 190 | CONFIG_RC_DEVICES=y |
| 191 | CONFIG_IR_GPIO_CIR=y | 191 | CONFIG_IR_GPIO_CIR=y |
| 192 | CONFIG_V4L_PLATFORM_DRIVERS=y | 192 | CONFIG_V4L_PLATFORM_DRIVERS=y |
| 193 | CONFIG_SOC_CAMERA=y | 193 | CONFIG_SOC_CAMERA=y |
| 194 | CONFIG_VIDEO_MX3=y | 194 | CONFIG_VIDEO_MX3=y |
| 195 | CONFIG_V4L_MEM2MEM_DRIVERS=y | 195 | CONFIG_V4L_MEM2MEM_DRIVERS=y |
| 196 | CONFIG_VIDEO_CODA=y | 196 | CONFIG_VIDEO_CODA=y |
| 197 | CONFIG_SOC_CAMERA_OV2640=y | 197 | CONFIG_SOC_CAMERA_OV2640=y |
| 198 | CONFIG_IMX_IPUV3_CORE=y | 198 | CONFIG_IMX_IPUV3_CORE=y |
| 199 | CONFIG_DRM=y | 199 | CONFIG_DRM=y |
| 200 | CONFIG_DRM_PANEL_SIMPLE=y | 200 | CONFIG_DRM_PANEL_SIMPLE=y |
| 201 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 201 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 202 | CONFIG_LCD_CLASS_DEVICE=y | 202 | CONFIG_LCD_CLASS_DEVICE=y |
| 203 | CONFIG_LCD_L4F00242T03=y | 203 | CONFIG_LCD_L4F00242T03=y |
| 204 | CONFIG_LCD_PLATFORM=y | 204 | CONFIG_LCD_PLATFORM=y |
| 205 | CONFIG_BACKLIGHT_PWM=y | 205 | CONFIG_BACKLIGHT_PWM=y |
| 206 | CONFIG_BACKLIGHT_GPIO=y | 206 | CONFIG_BACKLIGHT_GPIO=y |
| 207 | CONFIG_FRAMEBUFFER_CONSOLE=y | 207 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 208 | CONFIG_LOGO=y | 208 | CONFIG_LOGO=y |
| 209 | CONFIG_SOUND=y | 209 | CONFIG_SOUND=y |
| 210 | CONFIG_SND=y | 210 | CONFIG_SND=y |
| 211 | CONFIG_SND_SOC=y | 211 | CONFIG_SND_SOC=y |
| 212 | CONFIG_SND_SOC_FSL_SAI=y | 212 | CONFIG_SND_SOC_FSL_SAI=y |
| 213 | CONFIG_SND_IMX_SOC=y | 213 | CONFIG_SND_IMX_SOC=y |
| 214 | CONFIG_SND_SOC_PHYCORE_AC97=y | 214 | CONFIG_SND_SOC_PHYCORE_AC97=y |
| 215 | CONFIG_SND_SOC_EUKREA_TLV320=y | 215 | CONFIG_SND_SOC_EUKREA_TLV320=y |
| 216 | CONFIG_SND_SOC_IMX_WM8962=y | 216 | CONFIG_SND_SOC_IMX_WM8962=y |
| 217 | CONFIG_SND_SOC_IMX_SGTL5000=y | 217 | CONFIG_SND_SOC_IMX_SGTL5000=y |
| 218 | CONFIG_SND_SOC_IMX_SPDIF=y | 218 | CONFIG_SND_SOC_IMX_SPDIF=y |
| 219 | CONFIG_SND_SOC_IMX_MC13783=y | 219 | CONFIG_SND_SOC_IMX_MC13783=y |
| 220 | CONFIG_SND_SOC_TLV320AIC3X=y | 220 | CONFIG_SND_SOC_TLV320AIC3X=y |
| 221 | CONFIG_SND_SIMPLE_CARD=y | 221 | CONFIG_SND_SIMPLE_CARD=y |
| 222 | CONFIG_USB=y | 222 | CONFIG_USB=y |
| 223 | CONFIG_USB_EHCI_HCD=y | 223 | CONFIG_USB_EHCI_HCD=y |
| 224 | CONFIG_USB_EHCI_MXC=y | 224 | CONFIG_USB_EHCI_MXC=y |
| 225 | CONFIG_USB_STORAGE=y | 225 | CONFIG_USB_STORAGE=y |
| 226 | CONFIG_USB_CHIPIDEA=y | 226 | CONFIG_USB_CHIPIDEA=y |
| 227 | CONFIG_USB_CHIPIDEA_UDC=y | 227 | CONFIG_USB_CHIPIDEA_UDC=y |
| 228 | CONFIG_USB_CHIPIDEA_HOST=y | 228 | CONFIG_USB_CHIPIDEA_HOST=y |
| 229 | CONFIG_NOP_USB_XCEIV=y | 229 | CONFIG_NOP_USB_XCEIV=y |
| 230 | CONFIG_USB_MXS_PHY=y | 230 | CONFIG_USB_MXS_PHY=y |
| 231 | CONFIG_USB_GADGET=y | 231 | CONFIG_USB_GADGET=y |
| 232 | CONFIG_USB_ETH=m | 232 | CONFIG_USB_ETH=m |
| 233 | CONFIG_USB_MASS_STORAGE=m | 233 | CONFIG_USB_MASS_STORAGE=m |
| 234 | CONFIG_MMC=y | 234 | CONFIG_MMC=y |
| 235 | CONFIG_MMC_SDHCI=y | 235 | CONFIG_MMC_SDHCI=y |
| 236 | CONFIG_MMC_SDHCI_PLTFM=y | 236 | CONFIG_MMC_SDHCI_PLTFM=y |
| 237 | CONFIG_MMC_SDHCI_ESDHC_IMX=y | 237 | CONFIG_MMC_SDHCI_ESDHC_IMX=y |
| 238 | CONFIG_NEW_LEDS=y | 238 | CONFIG_NEW_LEDS=y |
| 239 | CONFIG_LEDS_CLASS=y | 239 | CONFIG_LEDS_CLASS=y |
| 240 | CONFIG_LEDS_GPIO=y | 240 | CONFIG_LEDS_GPIO=y |
| 241 | CONFIG_LEDS_TRIGGERS=y | 241 | CONFIG_LEDS_TRIGGERS=y |
| 242 | CONFIG_LEDS_TRIGGER_TIMER=y | 242 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 243 | CONFIG_LEDS_TRIGGER_ONESHOT=y | 243 | CONFIG_LEDS_TRIGGER_ONESHOT=y |
| 244 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 244 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 245 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | 245 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y |
| 246 | CONFIG_LEDS_TRIGGER_GPIO=y | 246 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 247 | CONFIG_RTC_CLASS=y | 247 | CONFIG_RTC_CLASS=y |
| 248 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | 248 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y |
| 249 | CONFIG_RTC_DRV_DS1307=y | 249 | CONFIG_RTC_DRV_DS1307=y |
| 250 | CONFIG_RTC_DRV_ISL1208=y | 250 | CONFIG_RTC_DRV_ISL1208=y |
| 251 | CONFIG_RTC_DRV_PCF8563=y | 251 | CONFIG_RTC_DRV_PCF8563=y |
| 252 | CONFIG_RTC_DRV_MC13XXX=y | 252 | CONFIG_RTC_DRV_MC13XXX=y |
| 253 | CONFIG_RTC_DRV_MXC=y | 253 | CONFIG_RTC_DRV_MXC=y |
| 254 | CONFIG_RTC_DRV_SNVS=y | 254 | CONFIG_RTC_DRV_SNVS=y |
| 255 | CONFIG_DMADEVICES=y | 255 | CONFIG_DMADEVICES=y |
| 256 | CONFIG_IMX_SDMA=y | 256 | CONFIG_IMX_SDMA=y |
| 257 | CONFIG_MXS_DMA=y | 257 | CONFIG_MXS_DMA=y |
| 258 | CONFIG_FSL_EDMA=y | 258 | CONFIG_FSL_EDMA=y |
| 259 | CONFIG_STAGING=y | 259 | CONFIG_STAGING=y |
| 260 | CONFIG_DRM_IMX=y | 260 | CONFIG_DRM_IMX=y |
| 261 | CONFIG_DRM_IMX_FB_HELPER=y | 261 | CONFIG_DRM_IMX_FB_HELPER=y |
| 262 | CONFIG_DRM_IMX_PARALLEL_DISPLAY=y | 262 | CONFIG_DRM_IMX_PARALLEL_DISPLAY=y |
| 263 | CONFIG_DRM_IMX_TVE=y | 263 | CONFIG_DRM_IMX_TVE=y |
| 264 | CONFIG_DRM_IMX_LDB=y | 264 | CONFIG_DRM_IMX_LDB=y |
| 265 | CONFIG_DRM_IMX_IPUV3=y | 265 | CONFIG_DRM_IMX_IPUV3=y |
| 266 | CONFIG_DRM_IMX_HDMI=y | 266 | CONFIG_DRM_IMX_HDMI=y |
| 267 | # CONFIG_IOMMU_SUPPORT is not set | 267 | # CONFIG_IOMMU_SUPPORT is not set |
| 268 | CONFIG_PWM=y | 268 | CONFIG_PWM=y |
| 269 | CONFIG_PWM_IMX=y | 269 | CONFIG_PWM_IMX=y |
| 270 | CONFIG_EXT2_FS=y | 270 | CONFIG_EXT2_FS=y |
| 271 | CONFIG_EXT2_FS_XATTR=y | 271 | CONFIG_EXT2_FS_XATTR=y |
| 272 | CONFIG_EXT2_FS_POSIX_ACL=y | 272 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 273 | CONFIG_EXT2_FS_SECURITY=y | 273 | CONFIG_EXT2_FS_SECURITY=y |
| 274 | CONFIG_EXT3_FS=y | 274 | CONFIG_EXT3_FS=y |
| 275 | CONFIG_EXT3_FS_POSIX_ACL=y | 275 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 276 | CONFIG_EXT3_FS_SECURITY=y | 276 | CONFIG_EXT3_FS_SECURITY=y |
| 277 | CONFIG_EXT4_FS=y | 277 | CONFIG_EXT4_FS=y |
| 278 | CONFIG_EXT4_FS_POSIX_ACL=y | 278 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 279 | CONFIG_EXT4_FS_SECURITY=y | 279 | CONFIG_EXT4_FS_SECURITY=y |
| 280 | CONFIG_QUOTA=y | 280 | CONFIG_QUOTA=y |
| 281 | CONFIG_QUOTA_NETLINK_INTERFACE=y | 281 | CONFIG_QUOTA_NETLINK_INTERFACE=y |
| 282 | # CONFIG_PRINT_QUOTA_WARNING is not set | 282 | # CONFIG_PRINT_QUOTA_WARNING is not set |
| 283 | CONFIG_AUTOFS4_FS=y | 283 | CONFIG_AUTOFS4_FS=y |
| 284 | CONFIG_FUSE_FS=y | 284 | CONFIG_FUSE_FS=y |
| 285 | CONFIG_ISO9660_FS=m | 285 | CONFIG_ISO9660_FS=m |
| 286 | CONFIG_JOLIET=y | 286 | CONFIG_JOLIET=y |
| 287 | CONFIG_ZISOFS=y | 287 | CONFIG_ZISOFS=y |
| 288 | CONFIG_UDF_FS=m | 288 | CONFIG_UDF_FS=m |
| 289 | CONFIG_MSDOS_FS=m | 289 | CONFIG_MSDOS_FS=m |
| 290 | CONFIG_VFAT_FS=y | 290 | CONFIG_VFAT_FS=y |
| 291 | CONFIG_TMPFS=y | 291 | CONFIG_TMPFS=y |
| 292 | CONFIG_JFFS2_FS=y | 292 | CONFIG_JFFS2_FS=y |
| 293 | CONFIG_UBIFS_FS=y | 293 | CONFIG_UBIFS_FS=y |
| 294 | CONFIG_NFS_FS=y | 294 | CONFIG_NFS_FS=y |
| 295 | CONFIG_NFS_V3_ACL=y | 295 | CONFIG_NFS_V3_ACL=y |
| 296 | CONFIG_NFS_V4=y | 296 | CONFIG_NFS_V4=y |
| 297 | CONFIG_ROOT_NFS=y | 297 | CONFIG_ROOT_NFS=y |
| 298 | CONFIG_NLS_DEFAULT="cp437" | 298 | CONFIG_NLS_DEFAULT="cp437" |
| 299 | CONFIG_NLS_CODEPAGE_437=y | 299 | CONFIG_NLS_CODEPAGE_437=y |
| 300 | CONFIG_NLS_ASCII=y | 300 | CONFIG_NLS_ASCII=y |
| 301 | CONFIG_NLS_ISO8859_1=y | 301 | CONFIG_NLS_ISO8859_1=y |
| 302 | CONFIG_NLS_ISO8859_15=m | 302 | CONFIG_NLS_ISO8859_15=m |
| 303 | CONFIG_NLS_UTF8=y | 303 | CONFIG_NLS_UTF8=y |
| 304 | CONFIG_PRINTK_TIME=y | 304 | CONFIG_PRINTK_TIME=y |
| 305 | CONFIG_DEBUG_FS=y | 305 | CONFIG_DEBUG_FS=y |
| 306 | CONFIG_MAGIC_SYSRQ=y | 306 | CONFIG_MAGIC_SYSRQ=y |
| 307 | # CONFIG_SCHED_DEBUG is not set | 307 | # CONFIG_SCHED_DEBUG is not set |
| 308 | CONFIG_PROVE_LOCKING=y | 308 | CONFIG_PROVE_LOCKING=y |
| 309 | # CONFIG_DEBUG_BUGVERBOSE is not set | 309 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 310 | # CONFIG_FTRACE is not set | 310 | # CONFIG_FTRACE is not set |
| 311 | # CONFIG_ARM_UNWIND is not set | 311 | # CONFIG_ARM_UNWIND is not set |
| 312 | CONFIG_SECURITYFS=y | 312 | CONFIG_SECURITYFS=y |
| 313 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 313 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 314 | # CONFIG_CRYPTO_HW is not set | 314 | # CONFIG_CRYPTO_HW is not set |
| 315 | CONFIG_CRC_CCITT=m | 315 | CONFIG_CRC_CCITT=m |
| 316 | CONFIG_CRC_T10DIF=y | 316 | CONFIG_CRC_T10DIF=y |
| 317 | CONFIG_CRC7=m | 317 | CONFIG_CRC7=m |
| 318 | CONFIG_LIBCRC32C=m | 318 | CONFIG_LIBCRC32C=m |
| 319 | CONFIG_FONTS=y | 319 | CONFIG_FONTS=y |
| 320 | CONFIG_FONT_8x8=y | 320 | CONFIG_FONT_8x8=y |
| 321 | CONFIG_FONT_8x16=y | 321 | CONFIG_FONT_8x16=y |
| 322 | 322 |
arch/arm/configs/keystone_defconfig
| 1 | # CONFIG_SWAP is not set | 1 | # CONFIG_SWAP is not set |
| 2 | CONFIG_POSIX_MQUEUE=y | 2 | CONFIG_POSIX_MQUEUE=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_IKCONFIG=y | 4 | CONFIG_IKCONFIG=y |
| 5 | CONFIG_IKCONFIG_PROC=y | 5 | CONFIG_IKCONFIG_PROC=y |
| 6 | CONFIG_LOG_BUF_SHIFT=14 | 6 | CONFIG_LOG_BUF_SHIFT=14 |
| 7 | CONFIG_BLK_DEV_INITRD=y | 7 | CONFIG_BLK_DEV_INITRD=y |
| 8 | CONFIG_SYSCTL_SYSCALL=y | 8 | CONFIG_SYSCTL_SYSCALL=y |
| 9 | CONFIG_KALLSYMS_ALL=y | 9 | CONFIG_KALLSYMS_ALL=y |
| 10 | # CONFIG_ELF_CORE is not set | 10 | # CONFIG_ELF_CORE is not set |
| 11 | # CONFIG_BASE_FULL is not set | 11 | # CONFIG_BASE_FULL is not set |
| 12 | CONFIG_EMBEDDED=y | 12 | CONFIG_EMBEDDED=y |
| 13 | CONFIG_PROFILING=y | 13 | CONFIG_PROFILING=y |
| 14 | CONFIG_OPROFILE=y | 14 | CONFIG_OPROFILE=y |
| 15 | CONFIG_KPROBES=y | 15 | CONFIG_KPROBES=y |
| 16 | CONFIG_MODULES=y | 16 | CONFIG_MODULES=y |
| 17 | CONFIG_MODULE_FORCE_LOAD=y | 17 | CONFIG_MODULE_FORCE_LOAD=y |
| 18 | CONFIG_MODULE_UNLOAD=y | 18 | CONFIG_MODULE_UNLOAD=y |
| 19 | CONFIG_MODULE_FORCE_UNLOAD=y | 19 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 20 | CONFIG_MODVERSIONS=y | 20 | CONFIG_MODVERSIONS=y |
| 21 | CONFIG_ARCH_KEYSTONE=y | 21 | CONFIG_ARCH_KEYSTONE=y |
| 22 | CONFIG_ARM_LPAE=y | 22 | CONFIG_ARM_LPAE=y |
| 23 | CONFIG_PCI=y | 23 | CONFIG_PCI=y |
| 24 | CONFIG_PCI_MSI=y | 24 | CONFIG_PCI_MSI=y |
| 25 | CONFIG_PCI_KEYSTONE=y | 25 | CONFIG_PCI_KEYSTONE=y |
| 26 | CONFIG_SMP=y | 26 | CONFIG_SMP=y |
| 27 | CONFIG_PREEMPT=y | 27 | CONFIG_PREEMPT=y |
| 28 | CONFIG_AEABI=y | 28 | CONFIG_AEABI=y |
| 29 | CONFIG_HIGHMEM=y | 29 | CONFIG_HIGHMEM=y |
| 30 | CONFIG_VFP=y | 30 | CONFIG_VFP=y |
| 31 | CONFIG_NEON=y | 31 | CONFIG_NEON=y |
| 32 | # CONFIG_SUSPEND is not set | 32 | # CONFIG_SUSPEND is not set |
| 33 | CONFIG_PM_RUNTIME=y | 33 | CONFIG_PM=y |
| 34 | CONFIG_NET=y | 34 | CONFIG_NET=y |
| 35 | CONFIG_PACKET=y | 35 | CONFIG_PACKET=y |
| 36 | CONFIG_UNIX=y | 36 | CONFIG_UNIX=y |
| 37 | CONFIG_UNIX_DIAG=y | 37 | CONFIG_UNIX_DIAG=y |
| 38 | CONFIG_XFRM_USER=y | 38 | CONFIG_XFRM_USER=y |
| 39 | CONFIG_XFRM_SUB_POLICY=y | 39 | CONFIG_XFRM_SUB_POLICY=y |
| 40 | CONFIG_XFRM_STATISTICS=y | 40 | CONFIG_XFRM_STATISTICS=y |
| 41 | CONFIG_NET_KEY=y | 41 | CONFIG_NET_KEY=y |
| 42 | CONFIG_NET_KEY_MIGRATE=y | 42 | CONFIG_NET_KEY_MIGRATE=y |
| 43 | CONFIG_INET=y | 43 | CONFIG_INET=y |
| 44 | CONFIG_IP_MULTICAST=y | 44 | CONFIG_IP_MULTICAST=y |
| 45 | CONFIG_IP_ADVANCED_ROUTER=y | 45 | CONFIG_IP_ADVANCED_ROUTER=y |
| 46 | CONFIG_IP_MULTIPLE_TABLES=y | 46 | CONFIG_IP_MULTIPLE_TABLES=y |
| 47 | CONFIG_IP_ROUTE_MULTIPATH=y | 47 | CONFIG_IP_ROUTE_MULTIPATH=y |
| 48 | CONFIG_IP_ROUTE_VERBOSE=y | 48 | CONFIG_IP_ROUTE_VERBOSE=y |
| 49 | CONFIG_IP_PNP=y | 49 | CONFIG_IP_PNP=y |
| 50 | CONFIG_IP_PNP_DHCP=y | 50 | CONFIG_IP_PNP_DHCP=y |
| 51 | CONFIG_IP_PNP_BOOTP=y | 51 | CONFIG_IP_PNP_BOOTP=y |
| 52 | CONFIG_NET_IPIP=y | 52 | CONFIG_NET_IPIP=y |
| 53 | CONFIG_NET_IPGRE_DEMUX=y | 53 | CONFIG_NET_IPGRE_DEMUX=y |
| 54 | CONFIG_NET_IPGRE=y | 54 | CONFIG_NET_IPGRE=y |
| 55 | CONFIG_IP_MROUTE=y | 55 | CONFIG_IP_MROUTE=y |
| 56 | CONFIG_IP_MROUTE_MULTIPLE_TABLES=y | 56 | CONFIG_IP_MROUTE_MULTIPLE_TABLES=y |
| 57 | CONFIG_IP_PIMSM_V2=y | 57 | CONFIG_IP_PIMSM_V2=y |
| 58 | CONFIG_INET_AH=y | 58 | CONFIG_INET_AH=y |
| 59 | CONFIG_INET_IPCOMP=y | 59 | CONFIG_INET_IPCOMP=y |
| 60 | CONFIG_IPV6=y | 60 | CONFIG_IPV6=y |
| 61 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | 61 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m |
| 62 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | 62 | CONFIG_INET6_XFRM_MODE_TUNNEL=m |
| 63 | CONFIG_INET6_XFRM_MODE_BEET=m | 63 | CONFIG_INET6_XFRM_MODE_BEET=m |
| 64 | CONFIG_IPV6_SIT=m | 64 | CONFIG_IPV6_SIT=m |
| 65 | CONFIG_IPV6_MULTIPLE_TABLES=y | 65 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 66 | CONFIG_IPV6_SUBTREES=y | 66 | CONFIG_IPV6_SUBTREES=y |
| 67 | CONFIG_IPV6_MROUTE=y | 67 | CONFIG_IPV6_MROUTE=y |
| 68 | CONFIG_IPV6_PIMSM_V2=y | 68 | CONFIG_IPV6_PIMSM_V2=y |
| 69 | CONFIG_NETFILTER=y | 69 | CONFIG_NETFILTER=y |
| 70 | CONFIG_NF_CONNTRACK=y | 70 | CONFIG_NF_CONNTRACK=y |
| 71 | CONFIG_NF_CT_NETLINK=y | 71 | CONFIG_NF_CT_NETLINK=y |
| 72 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y | 72 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y |
| 73 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=y | 73 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=y |
| 74 | CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y | 74 | CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y |
| 75 | CONFIG_NETFILTER_XT_TARGET_MARK=y | 75 | CONFIG_NETFILTER_XT_TARGET_MARK=y |
| 76 | CONFIG_NETFILTER_XT_MATCH_COMMENT=y | 76 | CONFIG_NETFILTER_XT_MATCH_COMMENT=y |
| 77 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y | 77 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y |
| 78 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y | 78 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y |
| 79 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=y | 79 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=y |
| 80 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y | 80 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y |
| 81 | CONFIG_NETFILTER_XT_MATCH_CPU=y | 81 | CONFIG_NETFILTER_XT_MATCH_CPU=y |
| 82 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=y | 82 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=y |
| 83 | CONFIG_NETFILTER_XT_MATCH_LENGTH=y | 83 | CONFIG_NETFILTER_XT_MATCH_LENGTH=y |
| 84 | CONFIG_NETFILTER_XT_MATCH_MAC=y | 84 | CONFIG_NETFILTER_XT_MATCH_MAC=y |
| 85 | CONFIG_NETFILTER_XT_MATCH_MARK=y | 85 | CONFIG_NETFILTER_XT_MATCH_MARK=y |
| 86 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y | 86 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y |
| 87 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y | 87 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y |
| 88 | CONFIG_NETFILTER_XT_MATCH_STATE=y | 88 | CONFIG_NETFILTER_XT_MATCH_STATE=y |
| 89 | CONFIG_NF_CONNTRACK_IPV4=y | 89 | CONFIG_NF_CONNTRACK_IPV4=y |
| 90 | CONFIG_IP_NF_IPTABLES=y | 90 | CONFIG_IP_NF_IPTABLES=y |
| 91 | CONFIG_IP_NF_MATCH_AH=y | 91 | CONFIG_IP_NF_MATCH_AH=y |
| 92 | CONFIG_IP_NF_MATCH_ECN=y | 92 | CONFIG_IP_NF_MATCH_ECN=y |
| 93 | CONFIG_IP_NF_MATCH_TTL=y | 93 | CONFIG_IP_NF_MATCH_TTL=y |
| 94 | CONFIG_IP_NF_FILTER=y | 94 | CONFIG_IP_NF_FILTER=y |
| 95 | CONFIG_IP_NF_TARGET_REJECT=y | 95 | CONFIG_IP_NF_TARGET_REJECT=y |
| 96 | CONFIG_IP_NF_TARGET_ULOG=y | 96 | CONFIG_IP_NF_TARGET_ULOG=y |
| 97 | CONFIG_IP_NF_MANGLE=y | 97 | CONFIG_IP_NF_MANGLE=y |
| 98 | CONFIG_IP_NF_TARGET_CLUSTERIP=y | 98 | CONFIG_IP_NF_TARGET_CLUSTERIP=y |
| 99 | CONFIG_IP_NF_TARGET_ECN=y | 99 | CONFIG_IP_NF_TARGET_ECN=y |
| 100 | CONFIG_IP_NF_TARGET_TTL=y | 100 | CONFIG_IP_NF_TARGET_TTL=y |
| 101 | CONFIG_IP_NF_RAW=y | 101 | CONFIG_IP_NF_RAW=y |
| 102 | CONFIG_IP_NF_ARPTABLES=y | 102 | CONFIG_IP_NF_ARPTABLES=y |
| 103 | CONFIG_IP_NF_ARPFILTER=y | 103 | CONFIG_IP_NF_ARPFILTER=y |
| 104 | CONFIG_IP_NF_ARP_MANGLE=y | 104 | CONFIG_IP_NF_ARP_MANGLE=y |
| 105 | CONFIG_IP6_NF_IPTABLES=m | 105 | CONFIG_IP6_NF_IPTABLES=m |
| 106 | CONFIG_IP_SCTP=y | 106 | CONFIG_IP_SCTP=y |
| 107 | CONFIG_VLAN_8021Q=y | 107 | CONFIG_VLAN_8021Q=y |
| 108 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 108 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 109 | CONFIG_CMA=y | 109 | CONFIG_CMA=y |
| 110 | CONFIG_DMA_CMA=y | 110 | CONFIG_DMA_CMA=y |
| 111 | CONFIG_MTD=y | 111 | CONFIG_MTD=y |
| 112 | CONFIG_MTD_CMDLINE_PARTS=y | 112 | CONFIG_MTD_CMDLINE_PARTS=y |
| 113 | CONFIG_MTD_BLOCK=y | 113 | CONFIG_MTD_BLOCK=y |
| 114 | CONFIG_MTD_PLATRAM=y | 114 | CONFIG_MTD_PLATRAM=y |
| 115 | CONFIG_MTD_M25P80=y | 115 | CONFIG_MTD_M25P80=y |
| 116 | CONFIG_MTD_NAND=y | 116 | CONFIG_MTD_NAND=y |
| 117 | CONFIG_MTD_NAND_DAVINCI=y | 117 | CONFIG_MTD_NAND_DAVINCI=y |
| 118 | CONFIG_MTD_SPI_NOR=y | 118 | CONFIG_MTD_SPI_NOR=y |
| 119 | CONFIG_MTD_UBI=y | 119 | CONFIG_MTD_UBI=y |
| 120 | CONFIG_PROC_DEVICETREE=y | 120 | CONFIG_PROC_DEVICETREE=y |
| 121 | CONFIG_BLK_DEV_LOOP=y | 121 | CONFIG_BLK_DEV_LOOP=y |
| 122 | CONFIG_EEPROM_AT24=y | 122 | CONFIG_EEPROM_AT24=y |
| 123 | CONFIG_SCSI=y | 123 | CONFIG_SCSI=y |
| 124 | CONFIG_BLK_DEV_SD=y | 124 | CONFIG_BLK_DEV_SD=y |
| 125 | CONFIG_NETDEVICES=y | 125 | CONFIG_NETDEVICES=y |
| 126 | CONFIG_SERIAL_8250=y | 126 | CONFIG_SERIAL_8250=y |
| 127 | CONFIG_SERIAL_8250_CONSOLE=y | 127 | CONFIG_SERIAL_8250_CONSOLE=y |
| 128 | CONFIG_SERIAL_OF_PLATFORM=y | 128 | CONFIG_SERIAL_OF_PLATFORM=y |
| 129 | # CONFIG_HW_RANDOM is not set | 129 | # CONFIG_HW_RANDOM is not set |
| 130 | CONFIG_I2C=y | 130 | CONFIG_I2C=y |
| 131 | # CONFIG_I2C_COMPAT is not set | 131 | # CONFIG_I2C_COMPAT is not set |
| 132 | CONFIG_I2C_CHARDEV=y | 132 | CONFIG_I2C_CHARDEV=y |
| 133 | CONFIG_I2C_DAVINCI=y | 133 | CONFIG_I2C_DAVINCI=y |
| 134 | CONFIG_SPI=y | 134 | CONFIG_SPI=y |
| 135 | CONFIG_SPI_DAVINCI=y | 135 | CONFIG_SPI_DAVINCI=y |
| 136 | CONFIG_SPI_SPIDEV=y | 136 | CONFIG_SPI_SPIDEV=y |
| 137 | # CONFIG_HWMON is not set | 137 | # CONFIG_HWMON is not set |
| 138 | CONFIG_POWER_SUPPLY=y | 138 | CONFIG_POWER_SUPPLY=y |
| 139 | CONFIG_POWER_RESET=y | 139 | CONFIG_POWER_RESET=y |
| 140 | CONFIG_POWER_RESET_KEYSTONE=y | 140 | CONFIG_POWER_RESET_KEYSTONE=y |
| 141 | CONFIG_WATCHDOG=y | 141 | CONFIG_WATCHDOG=y |
| 142 | CONFIG_WATCHDOG_CORE=y | 142 | CONFIG_WATCHDOG_CORE=y |
| 143 | CONFIG_DAVINCI_WATCHDOG=y | 143 | CONFIG_DAVINCI_WATCHDOG=y |
| 144 | CONFIG_USB=y | 144 | CONFIG_USB=y |
| 145 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 145 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 146 | CONFIG_USB_MON=y | 146 | CONFIG_USB_MON=y |
| 147 | CONFIG_USB_XHCI_HCD=y | 147 | CONFIG_USB_XHCI_HCD=y |
| 148 | CONFIG_USB_STORAGE=y | 148 | CONFIG_USB_STORAGE=y |
| 149 | CONFIG_USB_DWC3=y | 149 | CONFIG_USB_DWC3=y |
| 150 | CONFIG_USB_DWC3_DEBUG=y | 150 | CONFIG_USB_DWC3_DEBUG=y |
| 151 | CONFIG_USB_DWC3_VERBOSE=y | 151 | CONFIG_USB_DWC3_VERBOSE=y |
| 152 | CONFIG_KEYSTONE_USB_PHY=y | 152 | CONFIG_KEYSTONE_USB_PHY=y |
| 153 | CONFIG_DMADEVICES=y | 153 | CONFIG_DMADEVICES=y |
| 154 | CONFIG_TI_EDMA=y | 154 | CONFIG_TI_EDMA=y |
| 155 | CONFIG_MEMORY=y | 155 | CONFIG_MEMORY=y |
| 156 | CONFIG_TI_AEMIF=y | 156 | CONFIG_TI_AEMIF=y |
| 157 | CONFIG_EXT4_FS=y | 157 | CONFIG_EXT4_FS=y |
| 158 | CONFIG_EXT4_FS_POSIX_ACL=y | 158 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 159 | CONFIG_MSDOS_FS=y | 159 | CONFIG_MSDOS_FS=y |
| 160 | CONFIG_VFAT_FS=y | 160 | CONFIG_VFAT_FS=y |
| 161 | CONFIG_NTFS_FS=y | 161 | CONFIG_NTFS_FS=y |
| 162 | CONFIG_TMPFS=y | 162 | CONFIG_TMPFS=y |
| 163 | CONFIG_JFFS2_FS=y | 163 | CONFIG_JFFS2_FS=y |
| 164 | CONFIG_JFFS2_FS_WBUF_VERIFY=y | 164 | CONFIG_JFFS2_FS_WBUF_VERIFY=y |
| 165 | CONFIG_UBIFS_FS=y | 165 | CONFIG_UBIFS_FS=y |
| 166 | CONFIG_CRAMFS=y | 166 | CONFIG_CRAMFS=y |
| 167 | CONFIG_NFS_FS=y | 167 | CONFIG_NFS_FS=y |
| 168 | CONFIG_NFS_V3_ACL=y | 168 | CONFIG_NFS_V3_ACL=y |
| 169 | CONFIG_ROOT_NFS=y | 169 | CONFIG_ROOT_NFS=y |
| 170 | CONFIG_NFSD=y | 170 | CONFIG_NFSD=y |
| 171 | CONFIG_NFSD_V3=y | 171 | CONFIG_NFSD_V3=y |
| 172 | CONFIG_NFSD_V3_ACL=y | 172 | CONFIG_NFSD_V3_ACL=y |
| 173 | CONFIG_NLS_CODEPAGE_437=y | 173 | CONFIG_NLS_CODEPAGE_437=y |
| 174 | CONFIG_NLS_ISO8859_1=y | 174 | CONFIG_NLS_ISO8859_1=y |
| 175 | CONFIG_PRINTK_TIME=y | 175 | CONFIG_PRINTK_TIME=y |
| 176 | CONFIG_DEBUG_SHIRQ=y | 176 | CONFIG_DEBUG_SHIRQ=y |
| 177 | CONFIG_DEBUG_INFO=y | 177 | CONFIG_DEBUG_INFO=y |
| 178 | CONFIG_DEBUG_USER=y | 178 | CONFIG_DEBUG_USER=y |
| 179 | CONFIG_CRYPTO_USER=y | 179 | CONFIG_CRYPTO_USER=y |
| 180 | CONFIG_CRYPTO_NULL=y | 180 | CONFIG_CRYPTO_NULL=y |
| 181 | CONFIG_CRYPTO_AUTHENC=y | 181 | CONFIG_CRYPTO_AUTHENC=y |
| 182 | CONFIG_CRYPTO_CBC=y | 182 | CONFIG_CRYPTO_CBC=y |
| 183 | CONFIG_CRYPTO_CTR=y | 183 | CONFIG_CRYPTO_CTR=y |
| 184 | CONFIG_CRYPTO_XCBC=y | 184 | CONFIG_CRYPTO_XCBC=y |
| 185 | CONFIG_CRYPTO_DES=y | 185 | CONFIG_CRYPTO_DES=y |
| 186 | CONFIG_CRYPTO_ANSI_CPRNG=y | 186 | CONFIG_CRYPTO_ANSI_CPRNG=y |
| 187 | CONFIG_CRYPTO_USER_API_HASH=y | 187 | CONFIG_CRYPTO_USER_API_HASH=y |
| 188 | CONFIG_CRYPTO_USER_API_SKCIPHER=y | 188 | CONFIG_CRYPTO_USER_API_SKCIPHER=y |
| 189 | CONFIG_GPIOLIB=y | 189 | CONFIG_GPIOLIB=y |
| 190 | CONFIG_GPIO_SYSFS=y | 190 | CONFIG_GPIO_SYSFS=y |
| 191 | CONFIG_GPIO_DAVINCI=y | 191 | CONFIG_GPIO_DAVINCI=y |
| 192 | CONFIG_LEDS_CLASS=y | 192 | CONFIG_LEDS_CLASS=y |
| 193 | CONFIG_NEW_LEDS=y | 193 | CONFIG_NEW_LEDS=y |
| 194 | CONFIG_LEDS_GPIO=y | 194 | CONFIG_LEDS_GPIO=y |
| 195 | CONFIG_LEDS_TRIGGERS=y | 195 | CONFIG_LEDS_TRIGGERS=y |
| 196 | CONFIG_LEDS_TRIGGER_ONESHOT=y | 196 | CONFIG_LEDS_TRIGGER_ONESHOT=y |
| 197 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 197 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 198 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | 198 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y |
| 199 | CONFIG_LEDS_TRIGGER_GPIO=y | 199 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 200 | CONFIG_KEYSTONE_IRQ=y | 200 | CONFIG_KEYSTONE_IRQ=y |
| 201 | CONFIG_GPIO_SYSCON=y | 201 | CONFIG_GPIO_SYSCON=y |
| 202 | CONFIG_TI_DAVINCI_MDIO=y | 202 | CONFIG_TI_DAVINCI_MDIO=y |
| 203 | CONFIG_MARVELL_PHY=y | 203 | CONFIG_MARVELL_PHY=y |
| 204 | 204 |
arch/arm/configs/kzm9g_defconfig
| 1 | # CONFIG_ARM_PATCH_PHYS_VIRT is not set | 1 | # CONFIG_ARM_PATCH_PHYS_VIRT is not set |
| 2 | CONFIG_EXPERIMENTAL=y | 2 | CONFIG_EXPERIMENTAL=y |
| 3 | # CONFIG_LOCALVERSION_AUTO is not set | 3 | # CONFIG_LOCALVERSION_AUTO is not set |
| 4 | CONFIG_SYSVIPC=y | 4 | CONFIG_SYSVIPC=y |
| 5 | CONFIG_IKCONFIG=y | 5 | CONFIG_IKCONFIG=y |
| 6 | CONFIG_IKCONFIG_PROC=y | 6 | CONFIG_IKCONFIG_PROC=y |
| 7 | CONFIG_LOG_BUF_SHIFT=16 | 7 | CONFIG_LOG_BUF_SHIFT=16 |
| 8 | CONFIG_NAMESPACES=y | 8 | CONFIG_NAMESPACES=y |
| 9 | # CONFIG_UTS_NS is not set | 9 | # CONFIG_UTS_NS is not set |
| 10 | # CONFIG_IPC_NS is not set | 10 | # CONFIG_IPC_NS is not set |
| 11 | # CONFIG_USER_NS is not set | 11 | # CONFIG_USER_NS is not set |
| 12 | # CONFIG_PID_NS is not set | 12 | # CONFIG_PID_NS is not set |
| 13 | # CONFIG_NET_NS is not set | 13 | # CONFIG_NET_NS is not set |
| 14 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 14 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 15 | CONFIG_SYSCTL_SYSCALL=y | 15 | CONFIG_SYSCTL_SYSCALL=y |
| 16 | CONFIG_EMBEDDED=y | 16 | CONFIG_EMBEDDED=y |
| 17 | CONFIG_PERF_EVENTS=y | 17 | CONFIG_PERF_EVENTS=y |
| 18 | CONFIG_SLAB=y | 18 | CONFIG_SLAB=y |
| 19 | CONFIG_MODULES=y | 19 | CONFIG_MODULES=y |
| 20 | CONFIG_MODULE_FORCE_LOAD=y | 20 | CONFIG_MODULE_FORCE_LOAD=y |
| 21 | CONFIG_MODULE_UNLOAD=y | 21 | CONFIG_MODULE_UNLOAD=y |
| 22 | # CONFIG_BLK_DEV_BSG is not set | 22 | # CONFIG_BLK_DEV_BSG is not set |
| 23 | # CONFIG_IOSCHED_DEADLINE is not set | 23 | # CONFIG_IOSCHED_DEADLINE is not set |
| 24 | # CONFIG_IOSCHED_CFQ is not set | 24 | # CONFIG_IOSCHED_CFQ is not set |
| 25 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 25 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 26 | CONFIG_ARCH_SH73A0=y | 26 | CONFIG_ARCH_SH73A0=y |
| 27 | CONFIG_MACH_KZM9G=y | 27 | CONFIG_MACH_KZM9G=y |
| 28 | CONFIG_MEMORY_START=0x41000000 | 28 | CONFIG_MEMORY_START=0x41000000 |
| 29 | CONFIG_MEMORY_SIZE=0x1f000000 | 29 | CONFIG_MEMORY_SIZE=0x1f000000 |
| 30 | CONFIG_ARM_ERRATA_743622=y | 30 | CONFIG_ARM_ERRATA_743622=y |
| 31 | CONFIG_ARM_ERRATA_754322=y | 31 | CONFIG_ARM_ERRATA_754322=y |
| 32 | CONFIG_NO_HZ=y | 32 | CONFIG_NO_HZ=y |
| 33 | CONFIG_HIGH_RES_TIMERS=y | 33 | CONFIG_HIGH_RES_TIMERS=y |
| 34 | CONFIG_SMP=y | 34 | CONFIG_SMP=y |
| 35 | CONFIG_SCHED_MC=y | 35 | CONFIG_SCHED_MC=y |
| 36 | CONFIG_AEABI=y | 36 | CONFIG_AEABI=y |
| 37 | # CONFIG_OABI_COMPAT is not set | 37 | # CONFIG_OABI_COMPAT is not set |
| 38 | CONFIG_HIGHMEM=y | 38 | CONFIG_HIGHMEM=y |
| 39 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 39 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 40 | CONFIG_ZBOOT_ROM_BSS=0x0 | 40 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 41 | CONFIG_ARM_APPENDED_DTB=y | 41 | CONFIG_ARM_APPENDED_DTB=y |
| 42 | CONFIG_KEXEC=y | 42 | CONFIG_KEXEC=y |
| 43 | CONFIG_VFP=y | 43 | CONFIG_VFP=y |
| 44 | CONFIG_NEON=y | 44 | CONFIG_NEON=y |
| 45 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 45 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 46 | CONFIG_PM_RUNTIME=y | 46 | CONFIG_PM=y |
| 47 | CONFIG_NET=y | 47 | CONFIG_NET=y |
| 48 | CONFIG_PACKET=y | 48 | CONFIG_PACKET=y |
| 49 | CONFIG_UNIX=y | 49 | CONFIG_UNIX=y |
| 50 | CONFIG_INET=y | 50 | CONFIG_INET=y |
| 51 | CONFIG_IP_PNP=y | 51 | CONFIG_IP_PNP=y |
| 52 | CONFIG_IP_PNP_DHCP=y | 52 | CONFIG_IP_PNP_DHCP=y |
| 53 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 53 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 54 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 54 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 55 | # CONFIG_INET_XFRM_MODE_BEET is not set | 55 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 56 | # CONFIG_INET_LRO is not set | 56 | # CONFIG_INET_LRO is not set |
| 57 | # CONFIG_INET_DIAG is not set | 57 | # CONFIG_INET_DIAG is not set |
| 58 | # CONFIG_IPV6 is not set | 58 | # CONFIG_IPV6 is not set |
| 59 | CONFIG_IRDA=y | 59 | CONFIG_IRDA=y |
| 60 | CONFIG_SH_IRDA=y | 60 | CONFIG_SH_IRDA=y |
| 61 | # CONFIG_WIRELESS is not set | 61 | # CONFIG_WIRELESS is not set |
| 62 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 62 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 63 | CONFIG_DEVTMPFS=y | 63 | CONFIG_DEVTMPFS=y |
| 64 | CONFIG_DEVTMPFS_MOUNT=y | 64 | CONFIG_DEVTMPFS_MOUNT=y |
| 65 | CONFIG_SCSI=y | 65 | CONFIG_SCSI=y |
| 66 | CONFIG_BLK_DEV_SD=y | 66 | CONFIG_BLK_DEV_SD=y |
| 67 | CONFIG_NETDEVICES=y | 67 | CONFIG_NETDEVICES=y |
| 68 | CONFIG_SMSC911X=y | 68 | CONFIG_SMSC911X=y |
| 69 | # CONFIG_WLAN is not set | 69 | # CONFIG_WLAN is not set |
| 70 | CONFIG_INPUT_SPARSEKMAP=y | 70 | CONFIG_INPUT_SPARSEKMAP=y |
| 71 | # CONFIG_INPUT_MOUSEDEV is not set | 71 | # CONFIG_INPUT_MOUSEDEV is not set |
| 72 | CONFIG_INPUT_EVDEV=y | 72 | CONFIG_INPUT_EVDEV=y |
| 73 | # CONFIG_KEYBOARD_ATKBD is not set | 73 | # CONFIG_KEYBOARD_ATKBD is not set |
| 74 | CONFIG_KEYBOARD_GPIO=y | 74 | CONFIG_KEYBOARD_GPIO=y |
| 75 | # CONFIG_INPUT_MOUSE is not set | 75 | # CONFIG_INPUT_MOUSE is not set |
| 76 | CONFIG_INPUT_TOUCHSCREEN=y | 76 | CONFIG_INPUT_TOUCHSCREEN=y |
| 77 | CONFIG_TOUCHSCREEN_ST1232=y | 77 | CONFIG_TOUCHSCREEN_ST1232=y |
| 78 | CONFIG_INPUT_MISC=y | 78 | CONFIG_INPUT_MISC=y |
| 79 | CONFIG_INPUT_ADXL34X=y | 79 | CONFIG_INPUT_ADXL34X=y |
| 80 | # CONFIG_LEGACY_PTYS is not set | 80 | # CONFIG_LEGACY_PTYS is not set |
| 81 | CONFIG_SERIAL_SH_SCI=y | 81 | CONFIG_SERIAL_SH_SCI=y |
| 82 | CONFIG_SERIAL_SH_SCI_NR_UARTS=9 | 82 | CONFIG_SERIAL_SH_SCI_NR_UARTS=9 |
| 83 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 83 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 84 | # CONFIG_HW_RANDOM is not set | 84 | # CONFIG_HW_RANDOM is not set |
| 85 | CONFIG_I2C_CHARDEV=y | 85 | CONFIG_I2C_CHARDEV=y |
| 86 | CONFIG_I2C_SH_MOBILE=y | 86 | CONFIG_I2C_SH_MOBILE=y |
| 87 | CONFIG_GPIO_PCF857X=y | 87 | CONFIG_GPIO_PCF857X=y |
| 88 | # CONFIG_HWMON is not set | 88 | # CONFIG_HWMON is not set |
| 89 | CONFIG_MFD_AS3711=y | 89 | CONFIG_MFD_AS3711=y |
| 90 | CONFIG_REGULATOR=y | 90 | CONFIG_REGULATOR=y |
| 91 | CONFIG_REGULATOR_AS3711=y | 91 | CONFIG_REGULATOR_AS3711=y |
| 92 | CONFIG_FB=y | 92 | CONFIG_FB=y |
| 93 | CONFIG_FB_SH_MOBILE_LCDC=y | 93 | CONFIG_FB_SH_MOBILE_LCDC=y |
| 94 | CONFIG_BACKLIGHT_AS3711=y | 94 | CONFIG_BACKLIGHT_AS3711=y |
| 95 | CONFIG_FRAMEBUFFER_CONSOLE=y | 95 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 96 | CONFIG_LOGO=y | 96 | CONFIG_LOGO=y |
| 97 | CONFIG_FB_SH_MOBILE_MERAM=y | 97 | CONFIG_FB_SH_MOBILE_MERAM=y |
| 98 | CONFIG_SOUND=y | 98 | CONFIG_SOUND=y |
| 99 | CONFIG_SND=y | 99 | CONFIG_SND=y |
| 100 | # CONFIG_SND_SUPPORT_OLD_API is not set | 100 | # CONFIG_SND_SUPPORT_OLD_API is not set |
| 101 | # CONFIG_SND_VERBOSE_PROCFS is not set | 101 | # CONFIG_SND_VERBOSE_PROCFS is not set |
| 102 | # CONFIG_SND_DRIVERS is not set | 102 | # CONFIG_SND_DRIVERS is not set |
| 103 | # CONFIG_SND_ARM is not set | 103 | # CONFIG_SND_ARM is not set |
| 104 | # CONFIG_SND_USB is not set | 104 | # CONFIG_SND_USB is not set |
| 105 | CONFIG_SND_SOC=y | 105 | CONFIG_SND_SOC=y |
| 106 | CONFIG_SND_SOC_SH4_FSI=y | 106 | CONFIG_SND_SOC_SH4_FSI=y |
| 107 | # CONFIG_HID_SUPPORT is not set | 107 | # CONFIG_HID_SUPPORT is not set |
| 108 | CONFIG_USB=y | 108 | CONFIG_USB=y |
| 109 | CONFIG_USB_R8A66597_HCD=y | 109 | CONFIG_USB_R8A66597_HCD=y |
| 110 | CONFIG_USB_RENESAS_USBHS=y | 110 | CONFIG_USB_RENESAS_USBHS=y |
| 111 | CONFIG_USB_STORAGE=y | 111 | CONFIG_USB_STORAGE=y |
| 112 | CONFIG_USB_GADGET=y | 112 | CONFIG_USB_GADGET=y |
| 113 | CONFIG_USB_RENESAS_USBHS_UDC=y | 113 | CONFIG_USB_RENESAS_USBHS_UDC=y |
| 114 | CONFIG_USB_ETH=m | 114 | CONFIG_USB_ETH=m |
| 115 | CONFIG_USB_MASS_STORAGE=m | 115 | CONFIG_USB_MASS_STORAGE=m |
| 116 | CONFIG_MMC=y | 116 | CONFIG_MMC=y |
| 117 | # CONFIG_MMC_BLOCK_BOUNCE is not set | 117 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 118 | CONFIG_MMC_SDHI=y | 118 | CONFIG_MMC_SDHI=y |
| 119 | CONFIG_MMC_SH_MMCIF=y | 119 | CONFIG_MMC_SH_MMCIF=y |
| 120 | CONFIG_NEW_LEDS=y | 120 | CONFIG_NEW_LEDS=y |
| 121 | CONFIG_LEDS_CLASS=y | 121 | CONFIG_LEDS_CLASS=y |
| 122 | CONFIG_LEDS_GPIO=y | 122 | CONFIG_LEDS_GPIO=y |
| 123 | CONFIG_RTC_CLASS=y | 123 | CONFIG_RTC_CLASS=y |
| 124 | CONFIG_RTC_DRV_RS5C372=y | 124 | CONFIG_RTC_DRV_RS5C372=y |
| 125 | CONFIG_DMADEVICES=y | 125 | CONFIG_DMADEVICES=y |
| 126 | CONFIG_SH_DMAE=y | 126 | CONFIG_SH_DMAE=y |
| 127 | CONFIG_ASYNC_TX_DMA=y | 127 | CONFIG_ASYNC_TX_DMA=y |
| 128 | CONFIG_STAGING=y | 128 | CONFIG_STAGING=y |
| 129 | CONFIG_SENSORS_AK8975=y | 129 | CONFIG_SENSORS_AK8975=y |
| 130 | CONFIG_IIO=y | 130 | CONFIG_IIO=y |
| 131 | # CONFIG_DNOTIFY is not set | 131 | # CONFIG_DNOTIFY is not set |
| 132 | CONFIG_VFAT_FS=y | 132 | CONFIG_VFAT_FS=y |
| 133 | CONFIG_TMPFS=y | 133 | CONFIG_TMPFS=y |
| 134 | # CONFIG_MISC_FILESYSTEMS is not set | 134 | # CONFIG_MISC_FILESYSTEMS is not set |
| 135 | CONFIG_NFS_FS=y | 135 | CONFIG_NFS_FS=y |
| 136 | CONFIG_NFS_V3=y | 136 | CONFIG_NFS_V3=y |
| 137 | CONFIG_NFS_V3_ACL=y | 137 | CONFIG_NFS_V3_ACL=y |
| 138 | CONFIG_NFS_V4=y | 138 | CONFIG_NFS_V4=y |
| 139 | CONFIG_NFS_V4_1=y | 139 | CONFIG_NFS_V4_1=y |
| 140 | CONFIG_ROOT_NFS=y | 140 | CONFIG_ROOT_NFS=y |
| 141 | CONFIG_NLS_CODEPAGE_437=y | 141 | CONFIG_NLS_CODEPAGE_437=y |
| 142 | CONFIG_NLS_ISO8859_1=y | 142 | CONFIG_NLS_ISO8859_1=y |
| 143 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 143 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 144 | # CONFIG_ENABLE_MUST_CHECK is not set | 144 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 145 | # CONFIG_SCHED_DEBUG is not set | 145 | # CONFIG_SCHED_DEBUG is not set |
| 146 | # CONFIG_DEBUG_PREEMPT is not set | 146 | # CONFIG_DEBUG_PREEMPT is not set |
| 147 | # CONFIG_DEBUG_BUGVERBOSE is not set | 147 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 148 | # CONFIG_FTRACE is not set | 148 | # CONFIG_FTRACE is not set |
| 149 | # CONFIG_ARM_UNWIND is not set | 149 | # CONFIG_ARM_UNWIND is not set |
| 150 | CONFIG_CRYPTO=y | 150 | CONFIG_CRYPTO=y |
| 151 | CONFIG_CRYPTO_CBC=y | 151 | CONFIG_CRYPTO_CBC=y |
| 152 | CONFIG_CRYPTO_MD5=y | 152 | CONFIG_CRYPTO_MD5=y |
| 153 | CONFIG_CRYPTO_DES=y | 153 | CONFIG_CRYPTO_DES=y |
| 154 | CONFIG_CRC16=y | 154 | CONFIG_CRC16=y |
| 155 | 155 |
arch/arm/configs/lager_defconfig
| 1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 2 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 3 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
| 4 | CONFIG_IKCONFIG_PROC=y | 4 | CONFIG_IKCONFIG_PROC=y |
| 5 | CONFIG_LOG_BUF_SHIFT=16 | 5 | CONFIG_LOG_BUF_SHIFT=16 |
| 6 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 6 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 7 | CONFIG_SYSCTL_SYSCALL=y | 7 | CONFIG_SYSCTL_SYSCALL=y |
| 8 | CONFIG_EMBEDDED=y | 8 | CONFIG_EMBEDDED=y |
| 9 | CONFIG_PERF_EVENTS=y | 9 | CONFIG_PERF_EVENTS=y |
| 10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
| 11 | # CONFIG_LBDAF is not set | 11 | # CONFIG_LBDAF is not set |
| 12 | # CONFIG_BLK_DEV_BSG is not set | 12 | # CONFIG_BLK_DEV_BSG is not set |
| 13 | # CONFIG_IOSCHED_DEADLINE is not set | 13 | # CONFIG_IOSCHED_DEADLINE is not set |
| 14 | # CONFIG_IOSCHED_CFQ is not set | 14 | # CONFIG_IOSCHED_CFQ is not set |
| 15 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 15 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 16 | CONFIG_ARCH_R8A7790=y | 16 | CONFIG_ARCH_R8A7790=y |
| 17 | CONFIG_MACH_LAGER=y | 17 | CONFIG_MACH_LAGER=y |
| 18 | # CONFIG_SH_TIMER_TMU is not set | 18 | # CONFIG_SH_TIMER_TMU is not set |
| 19 | # CONFIG_EM_TIMER_STI is not set | 19 | # CONFIG_EM_TIMER_STI is not set |
| 20 | CONFIG_ARM_ERRATA_430973=y | 20 | CONFIG_ARM_ERRATA_430973=y |
| 21 | CONFIG_ARM_ERRATA_458693=y | 21 | CONFIG_ARM_ERRATA_458693=y |
| 22 | CONFIG_ARM_ERRATA_460075=y | 22 | CONFIG_ARM_ERRATA_460075=y |
| 23 | CONFIG_ARM_ERRATA_743622=y | 23 | CONFIG_ARM_ERRATA_743622=y |
| 24 | CONFIG_ARM_ERRATA_754322=y | 24 | CONFIG_ARM_ERRATA_754322=y |
| 25 | CONFIG_PCI=y | 25 | CONFIG_PCI=y |
| 26 | CONFIG_PCI_RCAR_GEN2=y | 26 | CONFIG_PCI_RCAR_GEN2=y |
| 27 | CONFIG_PCI_RCAR_GEN2_PCIE=y | 27 | CONFIG_PCI_RCAR_GEN2_PCIE=y |
| 28 | CONFIG_HAVE_ARM_ARCH_TIMER=y | 28 | CONFIG_HAVE_ARM_ARCH_TIMER=y |
| 29 | CONFIG_AEABI=y | 29 | CONFIG_AEABI=y |
| 30 | # CONFIG_OABI_COMPAT is not set | 30 | # CONFIG_OABI_COMPAT is not set |
| 31 | CONFIG_FORCE_MAX_ZONEORDER=13 | 31 | CONFIG_FORCE_MAX_ZONEORDER=13 |
| 32 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 32 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 33 | CONFIG_ZBOOT_ROM_BSS=0x0 | 33 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 34 | CONFIG_ARM_APPENDED_DTB=y | 34 | CONFIG_ARM_APPENDED_DTB=y |
| 35 | CONFIG_KEXEC=y | 35 | CONFIG_KEXEC=y |
| 36 | CONFIG_AUTO_ZRELADDR=y | 36 | CONFIG_AUTO_ZRELADDR=y |
| 37 | CONFIG_VFP=y | 37 | CONFIG_VFP=y |
| 38 | CONFIG_NEON=y | 38 | CONFIG_NEON=y |
| 39 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 39 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 40 | CONFIG_PM_RUNTIME=y | 40 | CONFIG_PM=y |
| 41 | CONFIG_NET=y | 41 | CONFIG_NET=y |
| 42 | CONFIG_PACKET=y | 42 | CONFIG_PACKET=y |
| 43 | CONFIG_UNIX=y | 43 | CONFIG_UNIX=y |
| 44 | CONFIG_INET=y | 44 | CONFIG_INET=y |
| 45 | CONFIG_IP_PNP=y | 45 | CONFIG_IP_PNP=y |
| 46 | CONFIG_IP_PNP_DHCP=y | 46 | CONFIG_IP_PNP_DHCP=y |
| 47 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 47 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 48 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 48 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 49 | # CONFIG_INET_XFRM_MODE_BEET is not set | 49 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 50 | # CONFIG_INET_LRO is not set | 50 | # CONFIG_INET_LRO is not set |
| 51 | # CONFIG_INET_DIAG is not set | 51 | # CONFIG_INET_DIAG is not set |
| 52 | # CONFIG_IPV6 is not set | 52 | # CONFIG_IPV6 is not set |
| 53 | # CONFIG_WIRELESS is not set | 53 | # CONFIG_WIRELESS is not set |
| 54 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 54 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 55 | CONFIG_DEVTMPFS=y | 55 | CONFIG_DEVTMPFS=y |
| 56 | CONFIG_DEVTMPFS_MOUNT=y | 56 | CONFIG_DEVTMPFS_MOUNT=y |
| 57 | CONFIG_MTD=y | 57 | CONFIG_MTD=y |
| 58 | CONFIG_MTD_M25P80=y | 58 | CONFIG_MTD_M25P80=y |
| 59 | CONFIG_MTD_SPI_NOR=y | 59 | CONFIG_MTD_SPI_NOR=y |
| 60 | CONFIG_BLK_DEV_SD=y | 60 | CONFIG_BLK_DEV_SD=y |
| 61 | CONFIG_ATA=y | 61 | CONFIG_ATA=y |
| 62 | CONFIG_SATA_RCAR=y | 62 | CONFIG_SATA_RCAR=y |
| 63 | CONFIG_NETDEVICES=y | 63 | CONFIG_NETDEVICES=y |
| 64 | # CONFIG_NET_CORE is not set | 64 | # CONFIG_NET_CORE is not set |
| 65 | # CONFIG_NET_VENDOR_ARC is not set | 65 | # CONFIG_NET_VENDOR_ARC is not set |
| 66 | # CONFIG_NET_CADENCE is not set | 66 | # CONFIG_NET_CADENCE is not set |
| 67 | # CONFIG_NET_VENDOR_BROADCOM is not set | 67 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 68 | # CONFIG_NET_VENDOR_CIRRUS is not set | 68 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 69 | # CONFIG_NET_VENDOR_FARADAY is not set | 69 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 70 | # CONFIG_NET_VENDOR_INTEL is not set | 70 | # CONFIG_NET_VENDOR_INTEL is not set |
| 71 | # CONFIG_NET_VENDOR_MARVELL is not set | 71 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 72 | # CONFIG_NET_VENDOR_MICREL is not set | 72 | # CONFIG_NET_VENDOR_MICREL is not set |
| 73 | # CONFIG_NET_VENDOR_NATSEMI is not set | 73 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 74 | CONFIG_SH_ETH=y | 74 | CONFIG_SH_ETH=y |
| 75 | # CONFIG_NET_VENDOR_SEEQ is not set | 75 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 76 | # CONFIG_NET_VENDOR_SMSC is not set | 76 | # CONFIG_NET_VENDOR_SMSC is not set |
| 77 | # CONFIG_NET_VENDOR_STMICRO is not set | 77 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 78 | # CONFIG_NET_VENDOR_VIA is not set | 78 | # CONFIG_NET_VENDOR_VIA is not set |
| 79 | # CONFIG_NET_VENDOR_WIZNET is not set | 79 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 80 | # CONFIG_WLAN is not set | 80 | # CONFIG_WLAN is not set |
| 81 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 81 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 82 | CONFIG_INPUT_EVDEV=y | 82 | CONFIG_INPUT_EVDEV=y |
| 83 | # CONFIG_KEYBOARD_ATKBD is not set | 83 | # CONFIG_KEYBOARD_ATKBD is not set |
| 84 | CONFIG_KEYBOARD_GPIO=y | 84 | CONFIG_KEYBOARD_GPIO=y |
| 85 | # CONFIG_INPUT_MOUSE is not set | 85 | # CONFIG_INPUT_MOUSE is not set |
| 86 | # CONFIG_SERIO is not set | 86 | # CONFIG_SERIO is not set |
| 87 | # CONFIG_LEGACY_PTYS is not set | 87 | # CONFIG_LEGACY_PTYS is not set |
| 88 | CONFIG_SERIAL_SH_SCI=y | 88 | CONFIG_SERIAL_SH_SCI=y |
| 89 | CONFIG_SERIAL_SH_SCI_NR_UARTS=10 | 89 | CONFIG_SERIAL_SH_SCI_NR_UARTS=10 |
| 90 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 90 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 91 | # CONFIG_HW_RANDOM is not set | 91 | # CONFIG_HW_RANDOM is not set |
| 92 | CONFIG_I2C_GPIO=y | 92 | CONFIG_I2C_GPIO=y |
| 93 | CONFIG_I2C_SH_MOBILE=y | 93 | CONFIG_I2C_SH_MOBILE=y |
| 94 | CONFIG_I2C_RCAR=y | 94 | CONFIG_I2C_RCAR=y |
| 95 | CONFIG_SPI=y | 95 | CONFIG_SPI=y |
| 96 | CONFIG_SPI_RSPI=y | 96 | CONFIG_SPI_RSPI=y |
| 97 | CONFIG_SPI_SH_MSIOF=y | 97 | CONFIG_SPI_SH_MSIOF=y |
| 98 | CONFIG_GPIO_SH_PFC=y | 98 | CONFIG_GPIO_SH_PFC=y |
| 99 | CONFIG_GPIOLIB=y | 99 | CONFIG_GPIOLIB=y |
| 100 | CONFIG_GPIO_RCAR=y | 100 | CONFIG_GPIO_RCAR=y |
| 101 | # CONFIG_HWMON is not set | 101 | # CONFIG_HWMON is not set |
| 102 | CONFIG_THERMAL=y | 102 | CONFIG_THERMAL=y |
| 103 | CONFIG_RCAR_THERMAL=y | 103 | CONFIG_RCAR_THERMAL=y |
| 104 | CONFIG_REGULATOR=y | 104 | CONFIG_REGULATOR=y |
| 105 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 105 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 106 | CONFIG_REGULATOR_DA9210=y | 106 | CONFIG_REGULATOR_DA9210=y |
| 107 | CONFIG_REGULATOR_GPIO=y | 107 | CONFIG_REGULATOR_GPIO=y |
| 108 | CONFIG_MEDIA_SUPPORT=y | 108 | CONFIG_MEDIA_SUPPORT=y |
| 109 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 109 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 110 | CONFIG_V4L_PLATFORM_DRIVERS=y | 110 | CONFIG_V4L_PLATFORM_DRIVERS=y |
| 111 | CONFIG_SOC_CAMERA=y | 111 | CONFIG_SOC_CAMERA=y |
| 112 | CONFIG_SOC_CAMERA_PLATFORM=y | 112 | CONFIG_SOC_CAMERA_PLATFORM=y |
| 113 | CONFIG_VIDEO_RCAR_VIN=y | 113 | CONFIG_VIDEO_RCAR_VIN=y |
| 114 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set | 114 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set |
| 115 | CONFIG_VIDEO_ADV7180=y | 115 | CONFIG_VIDEO_ADV7180=y |
| 116 | CONFIG_DRM=y | 116 | CONFIG_DRM=y |
| 117 | CONFIG_DRM_RCAR_DU=y | 117 | CONFIG_DRM_RCAR_DU=y |
| 118 | CONFIG_SOUND=y | 118 | CONFIG_SOUND=y |
| 119 | CONFIG_SND=y | 119 | CONFIG_SND=y |
| 120 | CONFIG_SND_SOC=y | 120 | CONFIG_SND_SOC=y |
| 121 | CONFIG_SND_SOC_RCAR=y | 121 | CONFIG_SND_SOC_RCAR=y |
| 122 | # CONFIG_USB_SUPPORT is not set | 122 | # CONFIG_USB_SUPPORT is not set |
| 123 | CONFIG_MMC=y | 123 | CONFIG_MMC=y |
| 124 | CONFIG_MMC_SDHI=y | 124 | CONFIG_MMC_SDHI=y |
| 125 | CONFIG_MMC_SH_MMCIF=y | 125 | CONFIG_MMC_SH_MMCIF=y |
| 126 | CONFIG_NEW_LEDS=y | 126 | CONFIG_NEW_LEDS=y |
| 127 | CONFIG_LEDS_CLASS=y | 127 | CONFIG_LEDS_CLASS=y |
| 128 | CONFIG_LEDS_GPIO=y | 128 | CONFIG_LEDS_GPIO=y |
| 129 | CONFIG_RTC_CLASS=y | 129 | CONFIG_RTC_CLASS=y |
| 130 | CONFIG_DMADEVICES=y | 130 | CONFIG_DMADEVICES=y |
| 131 | CONFIG_SH_DMAE=y | 131 | CONFIG_SH_DMAE=y |
| 132 | # CONFIG_IOMMU_SUPPORT is not set | 132 | # CONFIG_IOMMU_SUPPORT is not set |
| 133 | # CONFIG_DNOTIFY is not set | 133 | # CONFIG_DNOTIFY is not set |
| 134 | CONFIG_MSDOS_FS=y | 134 | CONFIG_MSDOS_FS=y |
| 135 | CONFIG_VFAT_FS=y | 135 | CONFIG_VFAT_FS=y |
| 136 | CONFIG_TMPFS=y | 136 | CONFIG_TMPFS=y |
| 137 | CONFIG_CONFIGFS_FS=y | 137 | CONFIG_CONFIGFS_FS=y |
| 138 | # CONFIG_MISC_FILESYSTEMS is not set | 138 | # CONFIG_MISC_FILESYSTEMS is not set |
| 139 | CONFIG_NFS_FS=y | 139 | CONFIG_NFS_FS=y |
| 140 | CONFIG_NFS_V3_ACL=y | 140 | CONFIG_NFS_V3_ACL=y |
| 141 | CONFIG_NFS_V4=y | 141 | CONFIG_NFS_V4=y |
| 142 | CONFIG_NFS_V4_1=y | 142 | CONFIG_NFS_V4_1=y |
| 143 | CONFIG_ROOT_NFS=y | 143 | CONFIG_ROOT_NFS=y |
| 144 | CONFIG_NLS_CODEPAGE_437=y | 144 | CONFIG_NLS_CODEPAGE_437=y |
| 145 | CONFIG_NLS_ISO8859_1=y | 145 | CONFIG_NLS_ISO8859_1=y |
| 146 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 146 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 147 | # CONFIG_ENABLE_MUST_CHECK is not set | 147 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 148 | # CONFIG_ARM_UNWIND is not set | 148 | # CONFIG_ARM_UNWIND is not set |
| 149 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 149 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 150 | # CONFIG_CRYPTO_HW is not set | 150 | # CONFIG_CRYPTO_HW is not set |
| 151 | 151 |
arch/arm/configs/mackerel_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
| 4 | CONFIG_IKCONFIG_PROC=y | 4 | CONFIG_IKCONFIG_PROC=y |
| 5 | CONFIG_LOG_BUF_SHIFT=16 | 5 | CONFIG_LOG_BUF_SHIFT=16 |
| 6 | # CONFIG_UTS_NS is not set | 6 | # CONFIG_UTS_NS is not set |
| 7 | # CONFIG_IPC_NS is not set | 7 | # CONFIG_IPC_NS is not set |
| 8 | # CONFIG_USER_NS is not set | 8 | # CONFIG_USER_NS is not set |
| 9 | # CONFIG_PID_NS is not set | 9 | # CONFIG_PID_NS is not set |
| 10 | # CONFIG_NET_NS is not set | 10 | # CONFIG_NET_NS is not set |
| 11 | CONFIG_SLAB=y | 11 | CONFIG_SLAB=y |
| 12 | CONFIG_MODULES=y | 12 | CONFIG_MODULES=y |
| 13 | CONFIG_MODULE_UNLOAD=y | 13 | CONFIG_MODULE_UNLOAD=y |
| 14 | # CONFIG_BLK_DEV_BSG is not set | 14 | # CONFIG_BLK_DEV_BSG is not set |
| 15 | # CONFIG_IOSCHED_DEADLINE is not set | 15 | # CONFIG_IOSCHED_DEADLINE is not set |
| 16 | # CONFIG_IOSCHED_CFQ is not set | 16 | # CONFIG_IOSCHED_CFQ is not set |
| 17 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 17 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 18 | CONFIG_ARCH_SH7372=y | 18 | CONFIG_ARCH_SH7372=y |
| 19 | CONFIG_MACH_MACKEREL=y | 19 | CONFIG_MACH_MACKEREL=y |
| 20 | CONFIG_MEMORY_SIZE=0x10000000 | 20 | CONFIG_MEMORY_SIZE=0x10000000 |
| 21 | CONFIG_AEABI=y | 21 | CONFIG_AEABI=y |
| 22 | # CONFIG_OABI_COMPAT is not set | 22 | # CONFIG_OABI_COMPAT is not set |
| 23 | CONFIG_FORCE_MAX_ZONEORDER=15 | 23 | CONFIG_FORCE_MAX_ZONEORDER=15 |
| 24 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 24 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 25 | CONFIG_ZBOOT_ROM_BSS=0x0 | 25 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 26 | CONFIG_ARM_APPENDED_DTB=y | 26 | CONFIG_ARM_APPENDED_DTB=y |
| 27 | CONFIG_KEXEC=y | 27 | CONFIG_KEXEC=y |
| 28 | CONFIG_VFP=y | 28 | CONFIG_VFP=y |
| 29 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 29 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 30 | CONFIG_PM=y | 30 | CONFIG_PM=y |
| 31 | CONFIG_PM_RUNTIME=y | ||
| 32 | CONFIG_NET=y | 31 | CONFIG_NET=y |
| 33 | CONFIG_PACKET=y | 32 | CONFIG_PACKET=y |
| 34 | CONFIG_UNIX=y | 33 | CONFIG_UNIX=y |
| 35 | CONFIG_INET=y | 34 | CONFIG_INET=y |
| 36 | CONFIG_IP_MULTICAST=y | 35 | CONFIG_IP_MULTICAST=y |
| 37 | CONFIG_IP_PNP=y | 36 | CONFIG_IP_PNP=y |
| 38 | CONFIG_IP_PNP_DHCP=y | 37 | CONFIG_IP_PNP_DHCP=y |
| 39 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 38 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 40 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 39 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 41 | # CONFIG_INET_XFRM_MODE_BEET is not set | 40 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 42 | # CONFIG_IPV6 is not set | 41 | # CONFIG_IPV6 is not set |
| 43 | # CONFIG_WIRELESS is not set | 42 | # CONFIG_WIRELESS is not set |
| 44 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 43 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 45 | CONFIG_DEVTMPFS=y | 44 | CONFIG_DEVTMPFS=y |
| 46 | CONFIG_DEVTMPFS_MOUNT=y | 45 | CONFIG_DEVTMPFS_MOUNT=y |
| 47 | # CONFIG_FIRMWARE_IN_KERNEL is not set | 46 | # CONFIG_FIRMWARE_IN_KERNEL is not set |
| 48 | CONFIG_MTD=y | 47 | CONFIG_MTD=y |
| 49 | CONFIG_MTD_CONCAT=y | 48 | CONFIG_MTD_CONCAT=y |
| 50 | CONFIG_MTD_PARTITIONS=y | 49 | CONFIG_MTD_PARTITIONS=y |
| 51 | CONFIG_MTD_CHAR=y | 50 | CONFIG_MTD_CHAR=y |
| 52 | CONFIG_MTD_BLOCK=y | 51 | CONFIG_MTD_BLOCK=y |
| 53 | CONFIG_MTD_CFI=y | 52 | CONFIG_MTD_CFI=y |
| 54 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 53 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| 55 | CONFIG_MTD_CFI_INTELEXT=y | 54 | CONFIG_MTD_CFI_INTELEXT=y |
| 56 | CONFIG_MTD_PHYSMAP=y | 55 | CONFIG_MTD_PHYSMAP=y |
| 57 | CONFIG_MTD_ARM_INTEGRATOR=y | 56 | CONFIG_MTD_ARM_INTEGRATOR=y |
| 58 | CONFIG_MTD_BLOCK2MTD=y | 57 | CONFIG_MTD_BLOCK2MTD=y |
| 59 | CONFIG_SCSI=y | 58 | CONFIG_SCSI=y |
| 60 | CONFIG_BLK_DEV_SD=y | 59 | CONFIG_BLK_DEV_SD=y |
| 61 | # CONFIG_SCSI_LOWLEVEL is not set | 60 | # CONFIG_SCSI_LOWLEVEL is not set |
| 62 | CONFIG_NETDEVICES=y | 61 | CONFIG_NETDEVICES=y |
| 63 | CONFIG_NET_ETHERNET=y | 62 | CONFIG_NET_ETHERNET=y |
| 64 | CONFIG_SMSC911X=y | 63 | CONFIG_SMSC911X=y |
| 65 | # CONFIG_NETDEV_1000 is not set | 64 | # CONFIG_NETDEV_1000 is not set |
| 66 | # CONFIG_NETDEV_10000 is not set | 65 | # CONFIG_NETDEV_10000 is not set |
| 67 | # CONFIG_WLAN is not set | 66 | # CONFIG_WLAN is not set |
| 68 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 67 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 69 | # CONFIG_INPUT_KEYBOARD is not set | 68 | # CONFIG_INPUT_KEYBOARD is not set |
| 70 | # CONFIG_INPUT_MOUSE is not set | 69 | # CONFIG_INPUT_MOUSE is not set |
| 71 | CONFIG_SERIAL_SH_SCI=y | 70 | CONFIG_SERIAL_SH_SCI=y |
| 72 | CONFIG_SERIAL_SH_SCI_NR_UARTS=8 | 71 | CONFIG_SERIAL_SH_SCI_NR_UARTS=8 |
| 73 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 72 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 74 | # CONFIG_LEGACY_PTYS is not set | 73 | # CONFIG_LEGACY_PTYS is not set |
| 75 | # CONFIG_HW_RANDOM is not set | 74 | # CONFIG_HW_RANDOM is not set |
| 76 | CONFIG_I2C=y | 75 | CONFIG_I2C=y |
| 77 | CONFIG_I2C_SH_MOBILE=y | 76 | CONFIG_I2C_SH_MOBILE=y |
| 78 | # CONFIG_HWMON is not set | 77 | # CONFIG_HWMON is not set |
| 79 | # CONFIG_MFD_SUPPORT is not set | 78 | # CONFIG_MFD_SUPPORT is not set |
| 80 | CONFIG_REGULATOR=y | 79 | CONFIG_REGULATOR=y |
| 81 | CONFIG_FB=y | 80 | CONFIG_FB=y |
| 82 | CONFIG_FB_MODE_HELPERS=y | 81 | CONFIG_FB_MODE_HELPERS=y |
| 83 | CONFIG_FB_SH_MOBILE_LCDC=y | 82 | CONFIG_FB_SH_MOBILE_LCDC=y |
| 84 | CONFIG_FB_SH_MOBILE_HDMI=y | 83 | CONFIG_FB_SH_MOBILE_HDMI=y |
| 85 | CONFIG_FRAMEBUFFER_CONSOLE=y | 84 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 86 | CONFIG_LOGO=y | 85 | CONFIG_LOGO=y |
| 87 | # CONFIG_LOGO_LINUX_MONO is not set | 86 | # CONFIG_LOGO_LINUX_MONO is not set |
| 88 | # CONFIG_LOGO_LINUX_CLUT224 is not set | 87 | # CONFIG_LOGO_LINUX_CLUT224 is not set |
| 89 | # CONFIG_SND_SUPPORT_OLD_API is not set | 88 | # CONFIG_SND_SUPPORT_OLD_API is not set |
| 90 | # CONFIG_SND_VERBOSE_PROCFS is not set | 89 | # CONFIG_SND_VERBOSE_PROCFS is not set |
| 91 | # CONFIG_SND_DRIVERS is not set | 90 | # CONFIG_SND_DRIVERS is not set |
| 92 | # CONFIG_SND_ARM is not set | 91 | # CONFIG_SND_ARM is not set |
| 93 | CONFIG_SND_SOC_SH4_FSI=y | 92 | CONFIG_SND_SOC_SH4_FSI=y |
| 94 | CONFIG_USB=y | 93 | CONFIG_USB=y |
| 95 | CONFIG_USB_RENESAS_USBHS_HCD=y | 94 | CONFIG_USB_RENESAS_USBHS_HCD=y |
| 96 | CONFIG_USB_RENESAS_USBHS=y | 95 | CONFIG_USB_RENESAS_USBHS=y |
| 97 | CONFIG_USB_STORAGE=y | 96 | CONFIG_USB_STORAGE=y |
| 98 | CONFIG_USB_GADGET=y | 97 | CONFIG_USB_GADGET=y |
| 99 | CONFIG_USB_RENESAS_USBHS_UDC=y | 98 | CONFIG_USB_RENESAS_USBHS_UDC=y |
| 100 | CONFIG_MMC=y | 99 | CONFIG_MMC=y |
| 101 | CONFIG_MMC_SDHI=y | 100 | CONFIG_MMC_SDHI=y |
| 102 | CONFIG_MMC_SH_MMCIF=y | 101 | CONFIG_MMC_SH_MMCIF=y |
| 103 | CONFIG_DMADEVICES=y | 102 | CONFIG_DMADEVICES=y |
| 104 | CONFIG_SH_DMAE=y | 103 | CONFIG_SH_DMAE=y |
| 105 | CONFIG_EXT2_FS=y | 104 | CONFIG_EXT2_FS=y |
| 106 | CONFIG_EXT2_FS_XATTR=y | 105 | CONFIG_EXT2_FS_XATTR=y |
| 107 | CONFIG_EXT2_FS_POSIX_ACL=y | 106 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 108 | CONFIG_EXT2_FS_SECURITY=y | 107 | CONFIG_EXT2_FS_SECURITY=y |
| 109 | CONFIG_EXT2_FS_XIP=y | 108 | CONFIG_EXT2_FS_XIP=y |
| 110 | CONFIG_EXT3_FS=y | 109 | CONFIG_EXT3_FS=y |
| 111 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 110 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 112 | CONFIG_EXT3_FS_POSIX_ACL=y | 111 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 113 | CONFIG_EXT3_FS_SECURITY=y | 112 | CONFIG_EXT3_FS_SECURITY=y |
| 114 | # CONFIG_DNOTIFY is not set | 113 | # CONFIG_DNOTIFY is not set |
| 115 | CONFIG_MSDOS_FS=y | 114 | CONFIG_MSDOS_FS=y |
| 116 | CONFIG_VFAT_FS=y | 115 | CONFIG_VFAT_FS=y |
| 117 | CONFIG_TMPFS=y | 116 | CONFIG_TMPFS=y |
| 118 | # CONFIG_MISC_FILESYSTEMS is not set | 117 | # CONFIG_MISC_FILESYSTEMS is not set |
| 119 | CONFIG_NFS_FS=y | 118 | CONFIG_NFS_FS=y |
| 120 | CONFIG_NFS_V3=y | 119 | CONFIG_NFS_V3=y |
| 121 | CONFIG_NFS_V3_ACL=y | 120 | CONFIG_NFS_V3_ACL=y |
| 122 | CONFIG_NFS_V4=y | 121 | CONFIG_NFS_V4=y |
| 123 | CONFIG_NFS_V4_1=y | 122 | CONFIG_NFS_V4_1=y |
| 124 | CONFIG_ROOT_NFS=y | 123 | CONFIG_ROOT_NFS=y |
| 125 | CONFIG_NLS_CODEPAGE_437=y | 124 | CONFIG_NLS_CODEPAGE_437=y |
| 126 | CONFIG_NLS_CODEPAGE_737=y | 125 | CONFIG_NLS_CODEPAGE_737=y |
| 127 | CONFIG_NLS_CODEPAGE_775=y | 126 | CONFIG_NLS_CODEPAGE_775=y |
| 128 | CONFIG_NLS_CODEPAGE_850=y | 127 | CONFIG_NLS_CODEPAGE_850=y |
| 129 | CONFIG_NLS_CODEPAGE_852=y | 128 | CONFIG_NLS_CODEPAGE_852=y |
| 130 | CONFIG_NLS_CODEPAGE_855=y | 129 | CONFIG_NLS_CODEPAGE_855=y |
| 131 | CONFIG_NLS_CODEPAGE_857=y | 130 | CONFIG_NLS_CODEPAGE_857=y |
| 132 | CONFIG_NLS_CODEPAGE_860=y | 131 | CONFIG_NLS_CODEPAGE_860=y |
| 133 | CONFIG_NLS_CODEPAGE_861=y | 132 | CONFIG_NLS_CODEPAGE_861=y |
| 134 | CONFIG_NLS_CODEPAGE_862=y | 133 | CONFIG_NLS_CODEPAGE_862=y |
| 135 | CONFIG_NLS_CODEPAGE_863=y | 134 | CONFIG_NLS_CODEPAGE_863=y |
| 136 | CONFIG_NLS_CODEPAGE_864=y | 135 | CONFIG_NLS_CODEPAGE_864=y |
| 137 | CONFIG_NLS_CODEPAGE_865=y | 136 | CONFIG_NLS_CODEPAGE_865=y |
| 138 | CONFIG_NLS_CODEPAGE_866=y | 137 | CONFIG_NLS_CODEPAGE_866=y |
| 139 | CONFIG_NLS_CODEPAGE_869=y | 138 | CONFIG_NLS_CODEPAGE_869=y |
| 140 | CONFIG_NLS_ISO8859_1=y | 139 | CONFIG_NLS_ISO8859_1=y |
| 141 | CONFIG_NLS_ISO8859_2=y | 140 | CONFIG_NLS_ISO8859_2=y |
| 142 | CONFIG_NLS_ISO8859_3=y | 141 | CONFIG_NLS_ISO8859_3=y |
| 143 | CONFIG_NLS_ISO8859_4=y | 142 | CONFIG_NLS_ISO8859_4=y |
| 144 | CONFIG_NLS_ISO8859_5=y | 143 | CONFIG_NLS_ISO8859_5=y |
| 145 | CONFIG_NLS_ISO8859_6=y | 144 | CONFIG_NLS_ISO8859_6=y |
| 146 | CONFIG_NLS_ISO8859_7=y | 145 | CONFIG_NLS_ISO8859_7=y |
| 147 | CONFIG_NLS_ISO8859_9=y | 146 | CONFIG_NLS_ISO8859_9=y |
| 148 | CONFIG_NLS_ISO8859_13=y | 147 | CONFIG_NLS_ISO8859_13=y |
| 149 | CONFIG_NLS_ISO8859_14=y | 148 | CONFIG_NLS_ISO8859_14=y |
| 150 | CONFIG_NLS_ISO8859_15=y | 149 | CONFIG_NLS_ISO8859_15=y |
| 151 | CONFIG_NLS_KOI8_R=y | 150 | CONFIG_NLS_KOI8_R=y |
| 152 | CONFIG_NLS_KOI8_U=y | 151 | CONFIG_NLS_KOI8_U=y |
| 153 | CONFIG_NLS_UTF8=y | 152 | CONFIG_NLS_UTF8=y |
| 154 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 153 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 155 | # CONFIG_ENABLE_MUST_CHECK is not set | 154 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 156 | # CONFIG_ARM_UNWIND is not set | 155 | # CONFIG_ARM_UNWIND is not set |
| 157 | CONFIG_CRYPTO=y | 156 | CONFIG_CRYPTO=y |
| 158 | CONFIG_CRYPTO_ANSI_CPRNG=y | 157 | CONFIG_CRYPTO_ANSI_CPRNG=y |
| 159 | 158 |
arch/arm/configs/marzen_defconfig
| 1 | # CONFIG_ARM_PATCH_PHYS_VIRT is not set | 1 | # CONFIG_ARM_PATCH_PHYS_VIRT is not set |
| 2 | CONFIG_EXPERIMENTAL=y | 2 | CONFIG_EXPERIMENTAL=y |
| 3 | CONFIG_KERNEL_LZMA=y | 3 | CONFIG_KERNEL_LZMA=y |
| 4 | CONFIG_NO_HZ=y | 4 | CONFIG_NO_HZ=y |
| 5 | CONFIG_IKCONFIG=y | 5 | CONFIG_IKCONFIG=y |
| 6 | CONFIG_IKCONFIG_PROC=y | 6 | CONFIG_IKCONFIG_PROC=y |
| 7 | CONFIG_LOG_BUF_SHIFT=16 | 7 | CONFIG_LOG_BUF_SHIFT=16 |
| 8 | CONFIG_SYSCTL_SYSCALL=y | 8 | CONFIG_SYSCTL_SYSCALL=y |
| 9 | CONFIG_EMBEDDED=y | 9 | CONFIG_EMBEDDED=y |
| 10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
| 11 | # CONFIG_IOSCHED_CFQ is not set | 11 | # CONFIG_IOSCHED_CFQ is not set |
| 12 | CONFIG_ARCH_SHMOBILE_LEGACY=y | 12 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 13 | CONFIG_ARCH_R8A7779=y | 13 | CONFIG_ARCH_R8A7779=y |
| 14 | CONFIG_MACH_MARZEN=y | 14 | CONFIG_MACH_MARZEN=y |
| 15 | CONFIG_MEMORY_START=0x60000000 | 15 | CONFIG_MEMORY_START=0x60000000 |
| 16 | CONFIG_MEMORY_SIZE=0x10000000 | 16 | CONFIG_MEMORY_SIZE=0x10000000 |
| 17 | CONFIG_SHMOBILE_TIMER_HZ=1024 | 17 | CONFIG_SHMOBILE_TIMER_HZ=1024 |
| 18 | # CONFIG_SH_TIMER_CMT is not set | 18 | # CONFIG_SH_TIMER_CMT is not set |
| 19 | # CONFIG_SWP_EMULATE is not set | 19 | # CONFIG_SWP_EMULATE is not set |
| 20 | CONFIG_ARM_ERRATA_430973=y | 20 | CONFIG_ARM_ERRATA_430973=y |
| 21 | CONFIG_ARM_ERRATA_458693=y | 21 | CONFIG_ARM_ERRATA_458693=y |
| 22 | CONFIG_ARM_ERRATA_460075=y | 22 | CONFIG_ARM_ERRATA_460075=y |
| 23 | CONFIG_ARM_ERRATA_743622=y | 23 | CONFIG_ARM_ERRATA_743622=y |
| 24 | CONFIG_ARM_ERRATA_754322=y | 24 | CONFIG_ARM_ERRATA_754322=y |
| 25 | CONFIG_SMP=y | 25 | CONFIG_SMP=y |
| 26 | # CONFIG_ARM_CPU_TOPOLOGY is not set | 26 | # CONFIG_ARM_CPU_TOPOLOGY is not set |
| 27 | CONFIG_AEABI=y | 27 | CONFIG_AEABI=y |
| 28 | # CONFIG_OABI_COMPAT is not set | 28 | # CONFIG_OABI_COMPAT is not set |
| 29 | CONFIG_HIGHMEM=y | 29 | CONFIG_HIGHMEM=y |
| 30 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 30 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 31 | CONFIG_ZBOOT_ROM_BSS=0x0 | 31 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 32 | CONFIG_ARM_APPENDED_DTB=y | 32 | CONFIG_ARM_APPENDED_DTB=y |
| 33 | CONFIG_VFP=y | 33 | CONFIG_VFP=y |
| 34 | CONFIG_KEXEC=y | 34 | CONFIG_KEXEC=y |
| 35 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 35 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 36 | CONFIG_PM_RUNTIME=y | 36 | CONFIG_PM=y |
| 37 | CONFIG_NET=y | 37 | CONFIG_NET=y |
| 38 | CONFIG_PACKET=y | 38 | CONFIG_PACKET=y |
| 39 | CONFIG_UNIX=y | 39 | CONFIG_UNIX=y |
| 40 | CONFIG_INET=y | 40 | CONFIG_INET=y |
| 41 | CONFIG_IP_PNP=y | 41 | CONFIG_IP_PNP=y |
| 42 | CONFIG_IP_PNP_DHCP=y | 42 | CONFIG_IP_PNP_DHCP=y |
| 43 | # CONFIG_IPV6 is not set | 43 | # CONFIG_IPV6 is not set |
| 44 | # CONFIG_WIRELESS is not set | 44 | # CONFIG_WIRELESS is not set |
| 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 46 | CONFIG_DEVTMPFS=y | 46 | CONFIG_DEVTMPFS=y |
| 47 | CONFIG_DEVTMPFS_MOUNT=y | 47 | CONFIG_DEVTMPFS_MOUNT=y |
| 48 | # CONFIG_STANDALONE is not set | 48 | # CONFIG_STANDALONE is not set |
| 49 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 49 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 50 | # CONFIG_FW_LOADER is not set | 50 | # CONFIG_FW_LOADER is not set |
| 51 | CONFIG_SCSI=y | 51 | CONFIG_SCSI=y |
| 52 | CONFIG_BLK_DEV_SD=y | 52 | CONFIG_BLK_DEV_SD=y |
| 53 | CONFIG_ATA=y | 53 | CONFIG_ATA=y |
| 54 | CONFIG_ATA_SFF=y | 54 | CONFIG_ATA_SFF=y |
| 55 | CONFIG_ATA_BMDMA=y | 55 | CONFIG_ATA_BMDMA=y |
| 56 | CONFIG_SATA_RCAR=y | 56 | CONFIG_SATA_RCAR=y |
| 57 | CONFIG_NETDEVICES=y | 57 | CONFIG_NETDEVICES=y |
| 58 | # CONFIG_NET_VENDOR_BROADCOM is not set | 58 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 59 | # CONFIG_NET_VENDOR_FARADAY is not set | 59 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 60 | # CONFIG_NET_VENDOR_INTEL is not set | 60 | # CONFIG_NET_VENDOR_INTEL is not set |
| 61 | # CONFIG_NET_VENDOR_MICREL is not set | 61 | # CONFIG_NET_VENDOR_MICREL is not set |
| 62 | # CONFIG_NET_VENDOR_NATSEMI is not set | 62 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 63 | # CONFIG_NET_VENDOR_SEEQ is not set | 63 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 64 | CONFIG_SMSC911X=y | 64 | CONFIG_SMSC911X=y |
| 65 | # CONFIG_NET_VENDOR_STMICRO is not set | 65 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 66 | # CONFIG_WLAN is not set | 66 | # CONFIG_WLAN is not set |
| 67 | # CONFIG_INPUT_MOUSEDEV is not set | 67 | # CONFIG_INPUT_MOUSEDEV is not set |
| 68 | CONFIG_INPUT_EVDEV=y | 68 | CONFIG_INPUT_EVDEV=y |
| 69 | # CONFIG_INPUT_MOUSE is not set | 69 | # CONFIG_INPUT_MOUSE is not set |
| 70 | # CONFIG_VT is not set | 70 | # CONFIG_VT is not set |
| 71 | # CONFIG_LEGACY_PTYS is not set | 71 | # CONFIG_LEGACY_PTYS is not set |
| 72 | # CONFIG_DEVKMEM is not set | 72 | # CONFIG_DEVKMEM is not set |
| 73 | CONFIG_SERIAL_SH_SCI=y | 73 | CONFIG_SERIAL_SH_SCI=y |
| 74 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 | 74 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 |
| 75 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 75 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 76 | # CONFIG_HW_RANDOM is not set | 76 | # CONFIG_HW_RANDOM is not set |
| 77 | CONFIG_I2C=y | 77 | CONFIG_I2C=y |
| 78 | CONFIG_I2C_RCAR=y | 78 | CONFIG_I2C_RCAR=y |
| 79 | CONFIG_SPI=y | 79 | CONFIG_SPI=y |
| 80 | CONFIG_SPI_SH_HSPI=y | 80 | CONFIG_SPI_SH_HSPI=y |
| 81 | CONFIG_GPIO_SYSFS=y | 81 | CONFIG_GPIO_SYSFS=y |
| 82 | CONFIG_GPIO_RCAR=y | 82 | CONFIG_GPIO_RCAR=y |
| 83 | # CONFIG_HWMON is not set | 83 | # CONFIG_HWMON is not set |
| 84 | CONFIG_THERMAL=y | 84 | CONFIG_THERMAL=y |
| 85 | CONFIG_RCAR_THERMAL=y | 85 | CONFIG_RCAR_THERMAL=y |
| 86 | CONFIG_SSB=y | 86 | CONFIG_SSB=y |
| 87 | CONFIG_REGULATOR=y | 87 | CONFIG_REGULATOR=y |
| 88 | CONFIG_MEDIA_SUPPORT=y | 88 | CONFIG_MEDIA_SUPPORT=y |
| 89 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 89 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 90 | CONFIG_V4L_PLATFORM_DRIVERS=y | 90 | CONFIG_V4L_PLATFORM_DRIVERS=y |
| 91 | CONFIG_SOC_CAMERA=y | 91 | CONFIG_SOC_CAMERA=y |
| 92 | CONFIG_VIDEO_RCAR_VIN=y | 92 | CONFIG_VIDEO_RCAR_VIN=y |
| 93 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set | 93 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set |
| 94 | CONFIG_VIDEO_ADV7180=y | 94 | CONFIG_VIDEO_ADV7180=y |
| 95 | CONFIG_DRM=y | 95 | CONFIG_DRM=y |
| 96 | CONFIG_DRM_RCAR_DU=y | 96 | CONFIG_DRM_RCAR_DU=y |
| 97 | CONFIG_USB=y | 97 | CONFIG_USB=y |
| 98 | CONFIG_USB_RCAR_PHY=y | 98 | CONFIG_USB_RCAR_PHY=y |
| 99 | CONFIG_MMC=y | 99 | CONFIG_MMC=y |
| 100 | CONFIG_MMC_SDHI=y | 100 | CONFIG_MMC_SDHI=y |
| 101 | CONFIG_USB_EHCI_HCD=y | 101 | CONFIG_USB_EHCI_HCD=y |
| 102 | CONFIG_USB_OHCI_HCD=y | 102 | CONFIG_USB_OHCI_HCD=y |
| 103 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 103 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 104 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 104 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 105 | CONFIG_USB_STORAGE=y | 105 | CONFIG_USB_STORAGE=y |
| 106 | CONFIG_NEW_LEDS=y | 106 | CONFIG_NEW_LEDS=y |
| 107 | CONFIG_LEDS_CLASS=y | 107 | CONFIG_LEDS_CLASS=y |
| 108 | CONFIG_LEDS_GPIO=y | 108 | CONFIG_LEDS_GPIO=y |
| 109 | CONFIG_DMADEVICES=y | 109 | CONFIG_DMADEVICES=y |
| 110 | CONFIG_RCAR_HPB_DMAE=y | 110 | CONFIG_RCAR_HPB_DMAE=y |
| 111 | CONFIG_UIO=y | 111 | CONFIG_UIO=y |
| 112 | CONFIG_UIO_PDRV_GENIRQ=y | 112 | CONFIG_UIO_PDRV_GENIRQ=y |
| 113 | # CONFIG_IOMMU_SUPPORT is not set | 113 | # CONFIG_IOMMU_SUPPORT is not set |
| 114 | # CONFIG_DNOTIFY is not set | 114 | # CONFIG_DNOTIFY is not set |
| 115 | CONFIG_TMPFS=y | 115 | CONFIG_TMPFS=y |
| 116 | # CONFIG_MISC_FILESYSTEMS is not set | 116 | # CONFIG_MISC_FILESYSTEMS is not set |
| 117 | CONFIG_NFS_FS=y | 117 | CONFIG_NFS_FS=y |
| 118 | CONFIG_ROOT_NFS=y | 118 | CONFIG_ROOT_NFS=y |
| 119 | CONFIG_MAGIC_SYSRQ=y | 119 | CONFIG_MAGIC_SYSRQ=y |
| 120 | CONFIG_DEBUG_INFO=y | 120 | CONFIG_DEBUG_INFO=y |
| 121 | CONFIG_DEBUG_INFO_REDUCED=y | 121 | CONFIG_DEBUG_INFO_REDUCED=y |
| 122 | # CONFIG_FTRACE is not set | 122 | # CONFIG_FTRACE is not set |
| 123 | CONFIG_DEBUG_USER=y | 123 | CONFIG_DEBUG_USER=y |
| 124 | CONFIG_AVERAGE=y | 124 | CONFIG_AVERAGE=y |
| 125 | 125 |
arch/arm/configs/omap1_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_POSIX_MQUEUE=y | 4 | CONFIG_POSIX_MQUEUE=y |
| 5 | CONFIG_BSD_PROCESS_ACCT=y | 5 | CONFIG_BSD_PROCESS_ACCT=y |
| 6 | CONFIG_IKCONFIG=y | 6 | CONFIG_IKCONFIG=y |
| 7 | CONFIG_LOG_BUF_SHIFT=14 | 7 | CONFIG_LOG_BUF_SHIFT=14 |
| 8 | CONFIG_BLK_DEV_INITRD=y | 8 | CONFIG_BLK_DEV_INITRD=y |
| 9 | CONFIG_EXPERT=y | 9 | CONFIG_EXPERT=y |
| 10 | # CONFIG_KALLSYMS is not set | 10 | # CONFIG_KALLSYMS is not set |
| 11 | # CONFIG_ELF_CORE is not set | 11 | # CONFIG_ELF_CORE is not set |
| 12 | # CONFIG_BASE_FULL is not set | 12 | # CONFIG_BASE_FULL is not set |
| 13 | # CONFIG_SHMEM is not set | 13 | # CONFIG_SHMEM is not set |
| 14 | # CONFIG_VM_EVENT_COUNTERS is not set | 14 | # CONFIG_VM_EVENT_COUNTERS is not set |
| 15 | CONFIG_SLOB=y | 15 | CONFIG_SLOB=y |
| 16 | CONFIG_PROFILING=y | 16 | CONFIG_PROFILING=y |
| 17 | CONFIG_OPROFILE=y | 17 | CONFIG_OPROFILE=y |
| 18 | CONFIG_MODULES=y | 18 | CONFIG_MODULES=y |
| 19 | CONFIG_MODULE_UNLOAD=y | 19 | CONFIG_MODULE_UNLOAD=y |
| 20 | CONFIG_MODULE_FORCE_UNLOAD=y | 20 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 21 | # CONFIG_LBDAF is not set | 21 | # CONFIG_LBDAF is not set |
| 22 | # CONFIG_BLK_DEV_BSG is not set | 22 | # CONFIG_BLK_DEV_BSG is not set |
| 23 | # CONFIG_IOSCHED_DEADLINE is not set | 23 | # CONFIG_IOSCHED_DEADLINE is not set |
| 24 | # CONFIG_IOSCHED_CFQ is not set | 24 | # CONFIG_IOSCHED_CFQ is not set |
| 25 | CONFIG_ARCH_OMAP=y | 25 | CONFIG_ARCH_OMAP=y |
| 26 | CONFIG_ARCH_OMAP1=y | 26 | CONFIG_ARCH_OMAP1=y |
| 27 | CONFIG_OMAP_RESET_CLOCKS=y | 27 | CONFIG_OMAP_RESET_CLOCKS=y |
| 28 | # CONFIG_OMAP_MUX is not set | 28 | # CONFIG_OMAP_MUX is not set |
| 29 | CONFIG_OMAP_32K_TIMER=y | 29 | CONFIG_OMAP_32K_TIMER=y |
| 30 | CONFIG_OMAP_DM_TIMER=y | 30 | CONFIG_OMAP_DM_TIMER=y |
| 31 | CONFIG_ARCH_OMAP730=y | 31 | CONFIG_ARCH_OMAP730=y |
| 32 | CONFIG_ARCH_OMAP850=y | 32 | CONFIG_ARCH_OMAP850=y |
| 33 | CONFIG_ARCH_OMAP16XX=y | 33 | CONFIG_ARCH_OMAP16XX=y |
| 34 | CONFIG_MACH_OMAP_INNOVATOR=y | 34 | CONFIG_MACH_OMAP_INNOVATOR=y |
| 35 | CONFIG_MACH_OMAP_H2=y | 35 | CONFIG_MACH_OMAP_H2=y |
| 36 | CONFIG_MACH_OMAP_H3=y | 36 | CONFIG_MACH_OMAP_H3=y |
| 37 | CONFIG_MACH_OMAP_HTCWIZARD=y | 37 | CONFIG_MACH_OMAP_HTCWIZARD=y |
| 38 | CONFIG_MACH_HERALD=y | 38 | CONFIG_MACH_HERALD=y |
| 39 | CONFIG_MACH_OMAP_OSK=y | 39 | CONFIG_MACH_OMAP_OSK=y |
| 40 | CONFIG_MACH_OMAP_PERSEUS2=y | 40 | CONFIG_MACH_OMAP_PERSEUS2=y |
| 41 | CONFIG_MACH_OMAP_FSAMPLE=y | 41 | CONFIG_MACH_OMAP_FSAMPLE=y |
| 42 | CONFIG_MACH_VOICEBLUE=y | 42 | CONFIG_MACH_VOICEBLUE=y |
| 43 | CONFIG_MACH_OMAP_PALMTE=y | 43 | CONFIG_MACH_OMAP_PALMTE=y |
| 44 | CONFIG_MACH_OMAP_PALMZ71=y | 44 | CONFIG_MACH_OMAP_PALMZ71=y |
| 45 | CONFIG_MACH_OMAP_PALMTT=y | 45 | CONFIG_MACH_OMAP_PALMTT=y |
| 46 | CONFIG_MACH_SX1=y | 46 | CONFIG_MACH_SX1=y |
| 47 | CONFIG_MACH_NOKIA770=y | 47 | CONFIG_MACH_NOKIA770=y |
| 48 | CONFIG_MACH_AMS_DELTA=y | 48 | CONFIG_MACH_AMS_DELTA=y |
| 49 | CONFIG_MACH_OMAP_GENERIC=y | 49 | CONFIG_MACH_OMAP_GENERIC=y |
| 50 | # CONFIG_ARM_THUMB is not set | 50 | # CONFIG_ARM_THUMB is not set |
| 51 | CONFIG_PCCARD=y | 51 | CONFIG_PCCARD=y |
| 52 | CONFIG_OMAP_CF=y | 52 | CONFIG_OMAP_CF=y |
| 53 | CONFIG_NO_HZ=y | 53 | CONFIG_NO_HZ=y |
| 54 | CONFIG_HIGH_RES_TIMERS=y | 54 | CONFIG_HIGH_RES_TIMERS=y |
| 55 | CONFIG_PREEMPT=y | 55 | CONFIG_PREEMPT=y |
| 56 | CONFIG_AEABI=y | 56 | CONFIG_AEABI=y |
| 57 | CONFIG_LEDS=y | 57 | CONFIG_LEDS=y |
| 58 | CONFIG_LEDS_CPU=y | 58 | CONFIG_LEDS_CPU=y |
| 59 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 59 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 60 | CONFIG_ZBOOT_ROM_BSS=0x0 | 60 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 61 | CONFIG_CMDLINE="root=1f03 rootfstype=jffs2" | 61 | CONFIG_CMDLINE="root=1f03 rootfstype=jffs2" |
| 62 | CONFIG_FPE_NWFPE=y | 62 | CONFIG_FPE_NWFPE=y |
| 63 | CONFIG_BINFMT_MISC=y | 63 | CONFIG_BINFMT_MISC=y |
| 64 | CONFIG_PM=y | 64 | CONFIG_PM=y |
| 65 | # CONFIG_SUSPEND is not set | 65 | # CONFIG_SUSPEND is not set |
| 66 | CONFIG_PM_RUNTIME=y | ||
| 67 | CONFIG_NET=y | 66 | CONFIG_NET=y |
| 68 | CONFIG_PACKET=y | 67 | CONFIG_PACKET=y |
| 69 | CONFIG_UNIX=y | 68 | CONFIG_UNIX=y |
| 70 | CONFIG_NET_KEY=y | 69 | CONFIG_NET_KEY=y |
| 71 | CONFIG_INET=y | 70 | CONFIG_INET=y |
| 72 | CONFIG_IP_MULTICAST=y | 71 | CONFIG_IP_MULTICAST=y |
| 73 | CONFIG_IP_PNP=y | 72 | CONFIG_IP_PNP=y |
| 74 | CONFIG_IP_PNP_DHCP=y | 73 | CONFIG_IP_PNP_DHCP=y |
| 75 | CONFIG_IP_PNP_BOOTP=y | 74 | CONFIG_IP_PNP_BOOTP=y |
| 76 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 75 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 77 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 76 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 78 | # CONFIG_INET_XFRM_MODE_BEET is not set | 77 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 79 | # CONFIG_INET_LRO is not set | 78 | # CONFIG_INET_LRO is not set |
| 80 | # CONFIG_INET_DIAG is not set | 79 | # CONFIG_INET_DIAG is not set |
| 81 | CONFIG_IPV6=y | 80 | CONFIG_IPV6=y |
| 82 | CONFIG_NETFILTER=y | 81 | CONFIG_NETFILTER=y |
| 83 | CONFIG_BT=y | 82 | CONFIG_BT=y |
| 84 | CONFIG_BT_L2CAP=y | 83 | CONFIG_BT_L2CAP=y |
| 85 | CONFIG_BT_SCO=y | 84 | CONFIG_BT_SCO=y |
| 86 | CONFIG_BT_RFCOMM=y | 85 | CONFIG_BT_RFCOMM=y |
| 87 | CONFIG_BT_RFCOMM_TTY=y | 86 | CONFIG_BT_RFCOMM_TTY=y |
| 88 | CONFIG_BT_BNEP=y | 87 | CONFIG_BT_BNEP=y |
| 89 | CONFIG_BT_HIDP=y | 88 | CONFIG_BT_HIDP=y |
| 90 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 89 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 91 | # CONFIG_STANDALONE is not set | 90 | # CONFIG_STANDALONE is not set |
| 92 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 91 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 93 | CONFIG_CONNECTOR=y | 92 | CONFIG_CONNECTOR=y |
| 94 | # CONFIG_PROC_EVENTS is not set | 93 | # CONFIG_PROC_EVENTS is not set |
| 95 | CONFIG_MTD=y | 94 | CONFIG_MTD=y |
| 96 | CONFIG_MTD_DEBUG=y | 95 | CONFIG_MTD_DEBUG=y |
| 97 | CONFIG_MTD_DEBUG_VERBOSE=3 | 96 | CONFIG_MTD_DEBUG_VERBOSE=3 |
| 98 | CONFIG_MTD_PARTITIONS=y | 97 | CONFIG_MTD_PARTITIONS=y |
| 99 | CONFIG_MTD_CMDLINE_PARTS=y | 98 | CONFIG_MTD_CMDLINE_PARTS=y |
| 100 | CONFIG_MTD_CHAR=y | 99 | CONFIG_MTD_CHAR=y |
| 101 | CONFIG_MTD_BLOCK=y | 100 | CONFIG_MTD_BLOCK=y |
| 102 | CONFIG_MTD_CFI=y | 101 | CONFIG_MTD_CFI=y |
| 103 | CONFIG_MTD_CFI_INTELEXT=y | 102 | CONFIG_MTD_CFI_INTELEXT=y |
| 104 | CONFIG_MTD_NAND=y | 103 | CONFIG_MTD_NAND=y |
| 105 | CONFIG_BLK_DEV_LOOP=y | 104 | CONFIG_BLK_DEV_LOOP=y |
| 106 | CONFIG_BLK_DEV_RAM=y | 105 | CONFIG_BLK_DEV_RAM=y |
| 107 | CONFIG_BLK_DEV_RAM_COUNT=2 | 106 | CONFIG_BLK_DEV_RAM_COUNT=2 |
| 108 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 107 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 109 | CONFIG_IDE=m | 108 | CONFIG_IDE=m |
| 110 | CONFIG_BLK_DEV_IDECS=m | 109 | CONFIG_BLK_DEV_IDECS=m |
| 111 | CONFIG_SCSI=y | 110 | CONFIG_SCSI=y |
| 112 | # CONFIG_SCSI_PROC_FS is not set | 111 | # CONFIG_SCSI_PROC_FS is not set |
| 113 | CONFIG_BLK_DEV_SD=y | 112 | CONFIG_BLK_DEV_SD=y |
| 114 | CONFIG_CHR_DEV_ST=y | 113 | CONFIG_CHR_DEV_ST=y |
| 115 | CONFIG_BLK_DEV_SR=y | 114 | CONFIG_BLK_DEV_SR=y |
| 116 | CONFIG_CHR_DEV_SG=y | 115 | CONFIG_CHR_DEV_SG=y |
| 117 | CONFIG_SCSI_MULTI_LUN=y | 116 | CONFIG_SCSI_MULTI_LUN=y |
| 118 | CONFIG_NETDEVICES=y | 117 | CONFIG_NETDEVICES=y |
| 119 | CONFIG_TUN=y | 118 | CONFIG_TUN=y |
| 120 | CONFIG_PHYLIB=y | 119 | CONFIG_PHYLIB=y |
| 121 | CONFIG_NET_ETHERNET=y | 120 | CONFIG_NET_ETHERNET=y |
| 122 | CONFIG_SMC91X=y | 121 | CONFIG_SMC91X=y |
| 123 | CONFIG_USB_CATC=y | 122 | CONFIG_USB_CATC=y |
| 124 | CONFIG_USB_KAWETH=y | 123 | CONFIG_USB_KAWETH=y |
| 125 | CONFIG_USB_PEGASUS=y | 124 | CONFIG_USB_PEGASUS=y |
| 126 | CONFIG_USB_RTL8150=y | 125 | CONFIG_USB_RTL8150=y |
| 127 | CONFIG_USB_USBNET=y | 126 | CONFIG_USB_USBNET=y |
| 128 | # CONFIG_USB_NET_AX8817X is not set | 127 | # CONFIG_USB_NET_AX8817X is not set |
| 129 | # CONFIG_USB_NET_CDC_SUBSET is not set | 128 | # CONFIG_USB_NET_CDC_SUBSET is not set |
| 130 | CONFIG_PPP=y | 129 | CONFIG_PPP=y |
| 131 | CONFIG_PPP_MULTILINK=y | 130 | CONFIG_PPP_MULTILINK=y |
| 132 | CONFIG_PPP_FILTER=y | 131 | CONFIG_PPP_FILTER=y |
| 133 | CONFIG_PPP_ASYNC=y | 132 | CONFIG_PPP_ASYNC=y |
| 134 | CONFIG_PPP_DEFLATE=y | 133 | CONFIG_PPP_DEFLATE=y |
| 135 | CONFIG_PPP_BSDCOMP=y | 134 | CONFIG_PPP_BSDCOMP=y |
| 136 | CONFIG_SLIP=y | 135 | CONFIG_SLIP=y |
| 137 | CONFIG_SLIP_COMPRESSED=y | 136 | CONFIG_SLIP_COMPRESSED=y |
| 138 | # CONFIG_INPUT_MOUSEDEV is not set | 137 | # CONFIG_INPUT_MOUSEDEV is not set |
| 139 | CONFIG_INPUT_EVDEV=y | 138 | CONFIG_INPUT_EVDEV=y |
| 140 | CONFIG_INPUT_EVBUG=y | 139 | CONFIG_INPUT_EVBUG=y |
| 141 | # CONFIG_INPUT_KEYBOARD is not set | 140 | # CONFIG_INPUT_KEYBOARD is not set |
| 142 | # CONFIG_INPUT_MOUSE is not set | 141 | # CONFIG_INPUT_MOUSE is not set |
| 143 | CONFIG_INPUT_TOUCHSCREEN=y | 142 | CONFIG_INPUT_TOUCHSCREEN=y |
| 144 | CONFIG_TOUCHSCREEN_ADS7846=y | 143 | CONFIG_TOUCHSCREEN_ADS7846=y |
| 145 | CONFIG_INPUT_MISC=y | 144 | CONFIG_INPUT_MISC=y |
| 146 | CONFIG_INPUT_UINPUT=y | 145 | CONFIG_INPUT_UINPUT=y |
| 147 | # CONFIG_SERIO is not set | 146 | # CONFIG_SERIO is not set |
| 148 | CONFIG_SERIAL_8250=y | 147 | CONFIG_SERIAL_8250=y |
| 149 | CONFIG_SERIAL_8250_CONSOLE=y | 148 | CONFIG_SERIAL_8250_CONSOLE=y |
| 150 | CONFIG_SERIAL_8250_NR_UARTS=3 | 149 | CONFIG_SERIAL_8250_NR_UARTS=3 |
| 151 | CONFIG_SERIAL_8250_RUNTIME_UARTS=3 | 150 | CONFIG_SERIAL_8250_RUNTIME_UARTS=3 |
| 152 | # CONFIG_LEGACY_PTYS is not set | 151 | # CONFIG_LEGACY_PTYS is not set |
| 153 | CONFIG_HW_RANDOM=y | 152 | CONFIG_HW_RANDOM=y |
| 154 | CONFIG_I2C=y | 153 | CONFIG_I2C=y |
| 155 | CONFIG_I2C_CHARDEV=y | 154 | CONFIG_I2C_CHARDEV=y |
| 156 | CONFIG_SPI=y | 155 | CONFIG_SPI=y |
| 157 | CONFIG_SPI_OMAP_UWIRE=y | 156 | CONFIG_SPI_OMAP_UWIRE=y |
| 158 | # CONFIG_HWMON is not set | 157 | # CONFIG_HWMON is not set |
| 159 | CONFIG_WATCHDOG=y | 158 | CONFIG_WATCHDOG=y |
| 160 | CONFIG_WATCHDOG_NOWAYOUT=y | 159 | CONFIG_WATCHDOG_NOWAYOUT=y |
| 161 | CONFIG_OMAP_WATCHDOG=y | 160 | CONFIG_OMAP_WATCHDOG=y |
| 162 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 161 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 163 | CONFIG_FB=y | 162 | CONFIG_FB=y |
| 164 | CONFIG_FIRMWARE_EDID=y | 163 | CONFIG_FIRMWARE_EDID=y |
| 165 | CONFIG_FB_MODE_HELPERS=y | 164 | CONFIG_FB_MODE_HELPERS=y |
| 166 | CONFIG_FB_VIRTUAL=y | 165 | CONFIG_FB_VIRTUAL=y |
| 167 | CONFIG_FB_OMAP=y | 166 | CONFIG_FB_OMAP=y |
| 168 | CONFIG_FB_OMAP_LCDC_EXTERNAL=y | 167 | CONFIG_FB_OMAP_LCDC_EXTERNAL=y |
| 169 | CONFIG_FB_OMAP_LCDC_HWA742=y | 168 | CONFIG_FB_OMAP_LCDC_HWA742=y |
| 170 | CONFIG_FB_OMAP_MANUAL_UPDATE=y | 169 | CONFIG_FB_OMAP_MANUAL_UPDATE=y |
| 171 | CONFIG_FB_OMAP_LCD_MIPID=y | 170 | CONFIG_FB_OMAP_LCD_MIPID=y |
| 172 | CONFIG_FB_OMAP_BOOTLOADER_INIT=y | 171 | CONFIG_FB_OMAP_BOOTLOADER_INIT=y |
| 173 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 172 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 174 | CONFIG_LCD_CLASS_DEVICE=y | 173 | CONFIG_LCD_CLASS_DEVICE=y |
| 175 | CONFIG_FRAMEBUFFER_CONSOLE=y | 174 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 176 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | 175 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y |
| 177 | CONFIG_FONTS=y | 176 | CONFIG_FONTS=y |
| 178 | CONFIG_FONT_8x8=y | 177 | CONFIG_FONT_8x8=y |
| 179 | CONFIG_FONT_8x16=y | 178 | CONFIG_FONT_8x16=y |
| 180 | CONFIG_FONT_6x11=y | 179 | CONFIG_FONT_6x11=y |
| 181 | CONFIG_FONT_MINI_4x6=y | 180 | CONFIG_FONT_MINI_4x6=y |
| 182 | CONFIG_LOGO=y | 181 | CONFIG_LOGO=y |
| 183 | # CONFIG_LOGO_LINUX_MONO is not set | 182 | # CONFIG_LOGO_LINUX_MONO is not set |
| 184 | # CONFIG_LOGO_LINUX_VGA16 is not set | 183 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 185 | CONFIG_SOUND=y | 184 | CONFIG_SOUND=y |
| 186 | CONFIG_SND=y | 185 | CONFIG_SND=y |
| 187 | CONFIG_SND_MIXER_OSS=y | 186 | CONFIG_SND_MIXER_OSS=y |
| 188 | CONFIG_SND_PCM_OSS=y | 187 | CONFIG_SND_PCM_OSS=y |
| 189 | # CONFIG_SND_SUPPORT_OLD_API is not set | 188 | # CONFIG_SND_SUPPORT_OLD_API is not set |
| 190 | # CONFIG_SND_VERBOSE_PROCFS is not set | 189 | # CONFIG_SND_VERBOSE_PROCFS is not set |
| 191 | CONFIG_SND_DUMMY=y | 190 | CONFIG_SND_DUMMY=y |
| 192 | CONFIG_SND_USB_AUDIO=y | 191 | CONFIG_SND_USB_AUDIO=y |
| 193 | CONFIG_SND_SOC=y | 192 | CONFIG_SND_SOC=y |
| 194 | CONFIG_SND_OMAP_SOC=y | 193 | CONFIG_SND_OMAP_SOC=y |
| 195 | # CONFIG_USB_HID is not set | 194 | # CONFIG_USB_HID is not set |
| 196 | CONFIG_USB=y | 195 | CONFIG_USB=y |
| 197 | CONFIG_USB_PHY=y | 196 | CONFIG_USB_PHY=y |
| 198 | # CONFIG_USB_DEVICE_CLASS is not set | 197 | # CONFIG_USB_DEVICE_CLASS is not set |
| 199 | CONFIG_USB_MON=y | 198 | CONFIG_USB_MON=y |
| 200 | CONFIG_USB_OHCI_HCD=y | 199 | CONFIG_USB_OHCI_HCD=y |
| 201 | CONFIG_USB_STORAGE=y | 200 | CONFIG_USB_STORAGE=y |
| 202 | CONFIG_USB_STORAGE_DATAFAB=y | 201 | CONFIG_USB_STORAGE_DATAFAB=y |
| 203 | CONFIG_USB_STORAGE_FREECOM=y | 202 | CONFIG_USB_STORAGE_FREECOM=y |
| 204 | CONFIG_USB_STORAGE_SDDR09=y | 203 | CONFIG_USB_STORAGE_SDDR09=y |
| 205 | CONFIG_USB_STORAGE_SDDR55=y | 204 | CONFIG_USB_STORAGE_SDDR55=y |
| 206 | CONFIG_USB_STORAGE_JUMPSHOT=y | 205 | CONFIG_USB_STORAGE_JUMPSHOT=y |
| 207 | CONFIG_USB_SERIAL=y | 206 | CONFIG_USB_SERIAL=y |
| 208 | CONFIG_USB_SERIAL_CONSOLE=y | 207 | CONFIG_USB_SERIAL_CONSOLE=y |
| 209 | CONFIG_USB_SERIAL_PL2303=y | 208 | CONFIG_USB_SERIAL_PL2303=y |
| 210 | CONFIG_USB_TEST=y | 209 | CONFIG_USB_TEST=y |
| 211 | CONFIG_USB_GADGET=y | 210 | CONFIG_USB_GADGET=y |
| 212 | CONFIG_USB_ETH=m | 211 | CONFIG_USB_ETH=m |
| 213 | # CONFIG_USB_ETH_RNDIS is not set | 212 | # CONFIG_USB_ETH_RNDIS is not set |
| 214 | CONFIG_USB_MASS_STORAGE=m | 213 | CONFIG_USB_MASS_STORAGE=m |
| 215 | CONFIG_MMC=y | 214 | CONFIG_MMC=y |
| 216 | CONFIG_MMC_SDHCI=y | 215 | CONFIG_MMC_SDHCI=y |
| 217 | CONFIG_MMC_SDHCI_PLTFM=y | 216 | CONFIG_MMC_SDHCI_PLTFM=y |
| 218 | CONFIG_MMC_OMAP=y | 217 | CONFIG_MMC_OMAP=y |
| 219 | CONFIG_NEW_LEDS=y | 218 | CONFIG_NEW_LEDS=y |
| 220 | CONFIG_LEDS_CLASS=y | 219 | CONFIG_LEDS_CLASS=y |
| 221 | CONFIG_LEDS_TRIGGERS=y | 220 | CONFIG_LEDS_TRIGGERS=y |
| 222 | CONFIG_LEDS_TRIGGER_TIMER=y | 221 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 223 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 222 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 224 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 223 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 225 | CONFIG_RTC_CLASS=y | 224 | CONFIG_RTC_CLASS=y |
| 226 | CONFIG_RTC_DRV_OMAP=y | 225 | CONFIG_RTC_DRV_OMAP=y |
| 227 | CONFIG_EXT2_FS=y | 226 | CONFIG_EXT2_FS=y |
| 228 | CONFIG_EXT3_FS=y | 227 | CONFIG_EXT3_FS=y |
| 229 | # CONFIG_DNOTIFY is not set | 228 | # CONFIG_DNOTIFY is not set |
| 230 | CONFIG_AUTOFS4_FS=y | 229 | CONFIG_AUTOFS4_FS=y |
| 231 | CONFIG_ISO9660_FS=y | 230 | CONFIG_ISO9660_FS=y |
| 232 | CONFIG_JOLIET=y | 231 | CONFIG_JOLIET=y |
| 233 | CONFIG_MSDOS_FS=y | 232 | CONFIG_MSDOS_FS=y |
| 234 | CONFIG_VFAT_FS=y | 233 | CONFIG_VFAT_FS=y |
| 235 | CONFIG_FAT_DEFAULT_CODEPAGE=866 | 234 | CONFIG_FAT_DEFAULT_CODEPAGE=866 |
| 236 | CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r" | 235 | CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r" |
| 237 | CONFIG_JFFS2_FS=y | 236 | CONFIG_JFFS2_FS=y |
| 238 | CONFIG_JFFS2_SUMMARY=y | 237 | CONFIG_JFFS2_SUMMARY=y |
| 239 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | 238 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y |
| 240 | CONFIG_CRAMFS=y | 239 | CONFIG_CRAMFS=y |
| 241 | CONFIG_ROMFS_FS=y | 240 | CONFIG_ROMFS_FS=y |
| 242 | CONFIG_NFS_FS=y | 241 | CONFIG_NFS_FS=y |
| 243 | CONFIG_NFS_V3=y | 242 | CONFIG_NFS_V3=y |
| 244 | CONFIG_NFS_V4=y | 243 | CONFIG_NFS_V4=y |
| 245 | CONFIG_ROOT_NFS=y | 244 | CONFIG_ROOT_NFS=y |
| 246 | CONFIG_PARTITION_ADVANCED=y | 245 | CONFIG_PARTITION_ADVANCED=y |
| 247 | CONFIG_NLS_CODEPAGE_437=y | 246 | CONFIG_NLS_CODEPAGE_437=y |
| 248 | CONFIG_NLS_CODEPAGE_850=y | 247 | CONFIG_NLS_CODEPAGE_850=y |
| 249 | CONFIG_NLS_CODEPAGE_852=y | 248 | CONFIG_NLS_CODEPAGE_852=y |
| 250 | CONFIG_NLS_CODEPAGE_866=y | 249 | CONFIG_NLS_CODEPAGE_866=y |
| 251 | CONFIG_NLS_CODEPAGE_1251=y | 250 | CONFIG_NLS_CODEPAGE_1251=y |
| 252 | CONFIG_NLS_ISO8859_1=y | 251 | CONFIG_NLS_ISO8859_1=y |
| 253 | CONFIG_NLS_ISO8859_2=y | 252 | CONFIG_NLS_ISO8859_2=y |
| 254 | CONFIG_NLS_ISO8859_5=y | 253 | CONFIG_NLS_ISO8859_5=y |
| 255 | CONFIG_NLS_ISO8859_15=y | 254 | CONFIG_NLS_ISO8859_15=y |
| 256 | CONFIG_NLS_KOI8_R=y | 255 | CONFIG_NLS_KOI8_R=y |
| 257 | CONFIG_NLS_UTF8=y | 256 | CONFIG_NLS_UTF8=y |
| 258 | # CONFIG_ENABLE_MUST_CHECK is not set | 257 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 259 | CONFIG_MAGIC_SYSRQ=y | 258 | CONFIG_MAGIC_SYSRQ=y |
| 260 | CONFIG_DEBUG_KERNEL=y | 259 | CONFIG_DEBUG_KERNEL=y |
| 261 | CONFIG_DEBUG_SPINLOCK=y | 260 | CONFIG_DEBUG_SPINLOCK=y |
| 262 | CONFIG_DEBUG_MUTEXES=y | 261 | CONFIG_DEBUG_MUTEXES=y |
| 263 | # CONFIG_DEBUG_BUGVERBOSE is not set | 262 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 264 | CONFIG_DEBUG_INFO=y | 263 | CONFIG_DEBUG_INFO=y |
| 265 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 264 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 266 | CONFIG_DEBUG_USER=y | 265 | CONFIG_DEBUG_USER=y |
| 267 | CONFIG_DEBUG_ERRORS=y | 266 | CONFIG_DEBUG_ERRORS=y |
| 268 | CONFIG_SECURITY=y | 267 | CONFIG_SECURITY=y |
| 269 | CONFIG_CRYPTO_ECB=y | 268 | CONFIG_CRYPTO_ECB=y |
| 270 | CONFIG_CRYPTO_PCBC=y | 269 | CONFIG_CRYPTO_PCBC=y |
| 271 | CONFIG_CRYPTO_DEFLATE=y | 270 | CONFIG_CRYPTO_DEFLATE=y |
| 272 | CONFIG_CRYPTO_ZLIB=y | 271 | CONFIG_CRYPTO_ZLIB=y |
| 273 | CONFIG_CRYPTO_LZO=y | 272 | CONFIG_CRYPTO_LZO=y |
| 274 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 273 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 275 | CONFIG_LIBCRC32C=y | 274 | CONFIG_LIBCRC32C=y |
| 276 | 275 |
arch/arm/configs/prima2_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_RELAY=y | 4 | CONFIG_RELAY=y |
| 5 | CONFIG_BLK_DEV_INITRD=y | 5 | CONFIG_BLK_DEV_INITRD=y |
| 6 | CONFIG_KALLSYMS_ALL=y | 6 | CONFIG_KALLSYMS_ALL=y |
| 7 | CONFIG_MODULES=y | 7 | CONFIG_MODULES=y |
| 8 | CONFIG_MODULE_UNLOAD=y | 8 | CONFIG_MODULE_UNLOAD=y |
| 9 | # CONFIG_BLK_DEV_BSG is not set | 9 | # CONFIG_BLK_DEV_BSG is not set |
| 10 | CONFIG_PARTITION_ADVANCED=y | 10 | CONFIG_PARTITION_ADVANCED=y |
| 11 | CONFIG_BSD_DISKLABEL=y | 11 | CONFIG_BSD_DISKLABEL=y |
| 12 | CONFIG_SOLARIS_X86_PARTITION=y | 12 | CONFIG_SOLARIS_X86_PARTITION=y |
| 13 | CONFIG_ARCH_SIRF=y | 13 | CONFIG_ARCH_SIRF=y |
| 14 | # CONFIG_SWP_EMULATE is not set | 14 | # CONFIG_SWP_EMULATE is not set |
| 15 | CONFIG_SMP=y | 15 | CONFIG_SMP=y |
| 16 | CONFIG_SCHED_MC=y | 16 | CONFIG_SCHED_MC=y |
| 17 | CONFIG_PREEMPT=y | 17 | CONFIG_PREEMPT=y |
| 18 | CONFIG_AEABI=y | 18 | CONFIG_AEABI=y |
| 19 | CONFIG_KEXEC=y | 19 | CONFIG_KEXEC=y |
| 20 | CONFIG_BINFMT_MISC=y | 20 | CONFIG_BINFMT_MISC=y |
| 21 | CONFIG_PM_RUNTIME=y | 21 | CONFIG_PM=y |
| 22 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 22 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 23 | CONFIG_BLK_DEV_LOOP=y | 23 | CONFIG_BLK_DEV_LOOP=y |
| 24 | CONFIG_BLK_DEV_RAM=y | 24 | CONFIG_BLK_DEV_RAM=y |
| 25 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 25 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 26 | CONFIG_SCSI=y | 26 | CONFIG_SCSI=y |
| 27 | CONFIG_BLK_DEV_SD=y | 27 | CONFIG_BLK_DEV_SD=y |
| 28 | CONFIG_CHR_DEV_SG=y | 28 | CONFIG_CHR_DEV_SG=y |
| 29 | CONFIG_INPUT_EVDEV=y | 29 | CONFIG_INPUT_EVDEV=y |
| 30 | # CONFIG_INPUT_MOUSE is not set | 30 | # CONFIG_INPUT_MOUSE is not set |
| 31 | CONFIG_INPUT_TOUCHSCREEN=y | 31 | CONFIG_INPUT_TOUCHSCREEN=y |
| 32 | CONFIG_SERIAL_SIRFSOC=y | 32 | CONFIG_SERIAL_SIRFSOC=y |
| 33 | CONFIG_SERIAL_SIRFSOC_CONSOLE=y | 33 | CONFIG_SERIAL_SIRFSOC_CONSOLE=y |
| 34 | CONFIG_HW_RANDOM=y | 34 | CONFIG_HW_RANDOM=y |
| 35 | CONFIG_I2C=y | 35 | CONFIG_I2C=y |
| 36 | CONFIG_I2C_CHARDEV=y | 36 | CONFIG_I2C_CHARDEV=y |
| 37 | CONFIG_I2C_SIRF=y | 37 | CONFIG_I2C_SIRF=y |
| 38 | CONFIG_SPI=y | 38 | CONFIG_SPI=y |
| 39 | CONFIG_SPI_SIRF=y | 39 | CONFIG_SPI_SIRF=y |
| 40 | CONFIG_SPI_SPIDEV=y | 40 | CONFIG_SPI_SPIDEV=y |
| 41 | # CONFIG_HWMON is not set | 41 | # CONFIG_HWMON is not set |
| 42 | CONFIG_WATCHDOG=y | 42 | CONFIG_WATCHDOG=y |
| 43 | CONFIG_USB_GADGET=y | 43 | CONFIG_USB_GADGET=y |
| 44 | CONFIG_USB_MASS_STORAGE=m | 44 | CONFIG_USB_MASS_STORAGE=m |
| 45 | CONFIG_MMC=y | 45 | CONFIG_MMC=y |
| 46 | CONFIG_MMC_SDHCI=y | 46 | CONFIG_MMC_SDHCI=y |
| 47 | CONFIG_MMC_SDHCI_PLTFM=y | 47 | CONFIG_MMC_SDHCI_PLTFM=y |
| 48 | CONFIG_DMADEVICES=y | 48 | CONFIG_DMADEVICES=y |
| 49 | CONFIG_DMADEVICES_DEBUG=y | 49 | CONFIG_DMADEVICES_DEBUG=y |
| 50 | CONFIG_DMADEVICES_VDEBUG=y | 50 | CONFIG_DMADEVICES_VDEBUG=y |
| 51 | CONFIG_SIRF_DMA=y | 51 | CONFIG_SIRF_DMA=y |
| 52 | # CONFIG_IOMMU_SUPPORT is not set | 52 | # CONFIG_IOMMU_SUPPORT is not set |
| 53 | CONFIG_EXT2_FS=y | 53 | CONFIG_EXT2_FS=y |
| 54 | CONFIG_MSDOS_FS=y | 54 | CONFIG_MSDOS_FS=y |
| 55 | CONFIG_VFAT_FS=y | 55 | CONFIG_VFAT_FS=y |
| 56 | CONFIG_TMPFS=y | 56 | CONFIG_TMPFS=y |
| 57 | CONFIG_TMPFS_POSIX_ACL=y | 57 | CONFIG_TMPFS_POSIX_ACL=y |
| 58 | CONFIG_CRAMFS=y | 58 | CONFIG_CRAMFS=y |
| 59 | CONFIG_ROMFS_FS=y | 59 | CONFIG_ROMFS_FS=y |
| 60 | CONFIG_NLS_CODEPAGE_437=y | 60 | CONFIG_NLS_CODEPAGE_437=y |
| 61 | CONFIG_NLS_ASCII=y | 61 | CONFIG_NLS_ASCII=y |
| 62 | CONFIG_NLS_ISO8859_1=y | 62 | CONFIG_NLS_ISO8859_1=y |
| 63 | CONFIG_MAGIC_SYSRQ=y | 63 | CONFIG_MAGIC_SYSRQ=y |
| 64 | CONFIG_DEBUG_SECTION_MISMATCH=y | 64 | CONFIG_DEBUG_SECTION_MISMATCH=y |
| 65 | CONFIG_DEBUG_KERNEL=y | 65 | CONFIG_DEBUG_KERNEL=y |
| 66 | # CONFIG_DEBUG_PREEMPT is not set | 66 | # CONFIG_DEBUG_PREEMPT is not set |
| 67 | CONFIG_DEBUG_RT_MUTEXES=y | 67 | CONFIG_DEBUG_RT_MUTEXES=y |
| 68 | CONFIG_DEBUG_SPINLOCK=y | 68 | CONFIG_DEBUG_SPINLOCK=y |
| 69 | CONFIG_DEBUG_MUTEXES=y | 69 | CONFIG_DEBUG_MUTEXES=y |
| 70 | CONFIG_DEBUG_INFO=y | 70 | CONFIG_DEBUG_INFO=y |
| 71 | CONFIG_CRC_CCITT=y | 71 | CONFIG_CRC_CCITT=y |
| 72 | 72 |
arch/arm/configs/sama5_defconfig
| 1 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 2 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_IRQ_DOMAIN_DEBUG=y | 4 | CONFIG_IRQ_DOMAIN_DEBUG=y |
| 5 | CONFIG_LOG_BUF_SHIFT=14 | 5 | CONFIG_LOG_BUF_SHIFT=14 |
| 6 | CONFIG_SYSFS_DEPRECATED=y | 6 | CONFIG_SYSFS_DEPRECATED=y |
| 7 | CONFIG_SYSFS_DEPRECATED_V2=y | 7 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 8 | CONFIG_BLK_DEV_INITRD=y | 8 | CONFIG_BLK_DEV_INITRD=y |
| 9 | CONFIG_EMBEDDED=y | 9 | CONFIG_EMBEDDED=y |
| 10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
| 11 | CONFIG_MODULES=y | 11 | CONFIG_MODULES=y |
| 12 | CONFIG_MODULE_FORCE_LOAD=y | 12 | CONFIG_MODULE_FORCE_LOAD=y |
| 13 | CONFIG_MODULE_UNLOAD=y | 13 | CONFIG_MODULE_UNLOAD=y |
| 14 | CONFIG_MODULE_FORCE_UNLOAD=y | 14 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 15 | CONFIG_LBDAF=y | 15 | CONFIG_LBDAF=y |
| 16 | # CONFIG_BLK_DEV_BSG is not set | 16 | # CONFIG_BLK_DEV_BSG is not set |
| 17 | # CONFIG_IOSCHED_DEADLINE is not set | 17 | # CONFIG_IOSCHED_DEADLINE is not set |
| 18 | # CONFIG_IOSCHED_CFQ is not set | 18 | # CONFIG_IOSCHED_CFQ is not set |
| 19 | CONFIG_ARCH_AT91=y | 19 | CONFIG_ARCH_AT91=y |
| 20 | CONFIG_SOC_SAM_V7=y | 20 | CONFIG_SOC_SAM_V7=y |
| 21 | CONFIG_SOC_SAMA5D3=y | 21 | CONFIG_SOC_SAMA5D3=y |
| 22 | CONFIG_SOC_SAMA5D4=y | 22 | CONFIG_SOC_SAMA5D4=y |
| 23 | CONFIG_AEABI=y | 23 | CONFIG_AEABI=y |
| 24 | CONFIG_UACCESS_WITH_MEMCPY=y | 24 | CONFIG_UACCESS_WITH_MEMCPY=y |
| 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 26 | CONFIG_ZBOOT_ROM_BSS=0x0 | 26 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 27 | CONFIG_ARM_APPENDED_DTB=y | 27 | CONFIG_ARM_APPENDED_DTB=y |
| 28 | CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" | 28 | CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" |
| 29 | CONFIG_KEXEC=y | 29 | CONFIG_KEXEC=y |
| 30 | CONFIG_AUTO_ZRELADDR=y | 30 | CONFIG_AUTO_ZRELADDR=y |
| 31 | CONFIG_VFP=y | 31 | CONFIG_VFP=y |
| 32 | CONFIG_NEON=y | 32 | CONFIG_NEON=y |
| 33 | CONFIG_KERNEL_MODE_NEON=y | 33 | CONFIG_KERNEL_MODE_NEON=y |
| 34 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 34 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 35 | CONFIG_PM_RUNTIME=y | 35 | CONFIG_PM=y |
| 36 | CONFIG_PM_DEBUG=y | 36 | CONFIG_PM_DEBUG=y |
| 37 | CONFIG_PM_ADVANCED_DEBUG=y | 37 | CONFIG_PM_ADVANCED_DEBUG=y |
| 38 | CONFIG_NET=y | 38 | CONFIG_NET=y |
| 39 | CONFIG_PACKET=y | 39 | CONFIG_PACKET=y |
| 40 | CONFIG_UNIX=y | 40 | CONFIG_UNIX=y |
| 41 | CONFIG_INET=y | 41 | CONFIG_INET=y |
| 42 | CONFIG_IP_MULTICAST=y | 42 | CONFIG_IP_MULTICAST=y |
| 43 | CONFIG_IP_PNP=y | 43 | CONFIG_IP_PNP=y |
| 44 | CONFIG_IP_PNP_DHCP=y | 44 | CONFIG_IP_PNP_DHCP=y |
| 45 | CONFIG_IP_PNP_BOOTP=y | 45 | CONFIG_IP_PNP_BOOTP=y |
| 46 | CONFIG_IP_PNP_RARP=y | 46 | CONFIG_IP_PNP_RARP=y |
| 47 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 47 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 48 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 48 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 49 | # CONFIG_INET_XFRM_MODE_BEET is not set | 49 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 50 | # CONFIG_INET_LRO is not set | 50 | # CONFIG_INET_LRO is not set |
| 51 | # CONFIG_INET_DIAG is not set | 51 | # CONFIG_INET_DIAG is not set |
| 52 | CONFIG_IPV6=y | 52 | CONFIG_IPV6=y |
| 53 | # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set | 53 | # CONFIG_INET6_XFRM_MODE_TRANSPORT is not set |
| 54 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set | 54 | # CONFIG_INET6_XFRM_MODE_TUNNEL is not set |
| 55 | # CONFIG_INET6_XFRM_MODE_BEET is not set | 55 | # CONFIG_INET6_XFRM_MODE_BEET is not set |
| 56 | CONFIG_IPV6_SIT_6RD=y | 56 | CONFIG_IPV6_SIT_6RD=y |
| 57 | CONFIG_CAN=y | 57 | CONFIG_CAN=y |
| 58 | CONFIG_CAN_AT91=y | 58 | CONFIG_CAN_AT91=y |
| 59 | CONFIG_CFG80211=y | 59 | CONFIG_CFG80211=y |
| 60 | CONFIG_MAC80211=y | 60 | CONFIG_MAC80211=y |
| 61 | CONFIG_MAC80211_LEDS=y | 61 | CONFIG_MAC80211_LEDS=y |
| 62 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 62 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 63 | CONFIG_DEVTMPFS=y | 63 | CONFIG_DEVTMPFS=y |
| 64 | CONFIG_DEVTMPFS_MOUNT=y | 64 | CONFIG_DEVTMPFS_MOUNT=y |
| 65 | # CONFIG_STANDALONE is not set | 65 | # CONFIG_STANDALONE is not set |
| 66 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 66 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 67 | CONFIG_MTD=y | 67 | CONFIG_MTD=y |
| 68 | CONFIG_MTD_CMDLINE_PARTS=y | 68 | CONFIG_MTD_CMDLINE_PARTS=y |
| 69 | CONFIG_MTD_BLOCK=y | 69 | CONFIG_MTD_BLOCK=y |
| 70 | CONFIG_MTD_CFI=y | 70 | CONFIG_MTD_CFI=y |
| 71 | CONFIG_MTD_M25P80=y | 71 | CONFIG_MTD_M25P80=y |
| 72 | CONFIG_MTD_NAND=y | 72 | CONFIG_MTD_NAND=y |
| 73 | CONFIG_MTD_NAND_ATMEL=y | 73 | CONFIG_MTD_NAND_ATMEL=y |
| 74 | CONFIG_MTD_SPI_NOR=y | 74 | CONFIG_MTD_SPI_NOR=y |
| 75 | CONFIG_MTD_UBI=y | 75 | CONFIG_MTD_UBI=y |
| 76 | CONFIG_MTD_UBI_GLUEBI=y | 76 | CONFIG_MTD_UBI_GLUEBI=y |
| 77 | CONFIG_BLK_DEV_LOOP=y | 77 | CONFIG_BLK_DEV_LOOP=y |
| 78 | CONFIG_BLK_DEV_RAM=y | 78 | CONFIG_BLK_DEV_RAM=y |
| 79 | CONFIG_BLK_DEV_RAM_COUNT=4 | 79 | CONFIG_BLK_DEV_RAM_COUNT=4 |
| 80 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 80 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 81 | CONFIG_ATMEL_TCLIB=y | 81 | CONFIG_ATMEL_TCLIB=y |
| 82 | CONFIG_ATMEL_SSC=y | 82 | CONFIG_ATMEL_SSC=y |
| 83 | CONFIG_EEPROM_AT24=y | 83 | CONFIG_EEPROM_AT24=y |
| 84 | CONFIG_SCSI=y | 84 | CONFIG_SCSI=y |
| 85 | CONFIG_BLK_DEV_SD=y | 85 | CONFIG_BLK_DEV_SD=y |
| 86 | # CONFIG_SCSI_LOWLEVEL is not set | 86 | # CONFIG_SCSI_LOWLEVEL is not set |
| 87 | CONFIG_NETDEVICES=y | 87 | CONFIG_NETDEVICES=y |
| 88 | CONFIG_MACB=y | 88 | CONFIG_MACB=y |
| 89 | # CONFIG_NET_VENDOR_BROADCOM is not set | 89 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 90 | # CONFIG_NET_VENDOR_CIRRUS is not set | 90 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 91 | # CONFIG_NET_VENDOR_FARADAY is not set | 91 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 92 | # CONFIG_NET_VENDOR_INTEL is not set | 92 | # CONFIG_NET_VENDOR_INTEL is not set |
| 93 | # CONFIG_NET_VENDOR_MARVELL is not set | 93 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 94 | # CONFIG_NET_VENDOR_MICREL is not set | 94 | # CONFIG_NET_VENDOR_MICREL is not set |
| 95 | # CONFIG_NET_VENDOR_MICROCHIP is not set | 95 | # CONFIG_NET_VENDOR_MICROCHIP is not set |
| 96 | # CONFIG_NET_VENDOR_NATSEMI is not set | 96 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 97 | # CONFIG_NET_VENDOR_SEEQ is not set | 97 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 98 | # CONFIG_NET_VENDOR_SMSC is not set | 98 | # CONFIG_NET_VENDOR_SMSC is not set |
| 99 | # CONFIG_NET_VENDOR_STMICRO is not set | 99 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 100 | # CONFIG_NET_VENDOR_WIZNET is not set | 100 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 101 | CONFIG_MICREL_PHY=y | 101 | CONFIG_MICREL_PHY=y |
| 102 | CONFIG_LIBERTAS_THINFIRM=m | 102 | CONFIG_LIBERTAS_THINFIRM=m |
| 103 | CONFIG_LIBERTAS_THINFIRM_USB=m | 103 | CONFIG_LIBERTAS_THINFIRM_USB=m |
| 104 | CONFIG_RTL8187=m | 104 | CONFIG_RTL8187=m |
| 105 | CONFIG_RT2X00=m | 105 | CONFIG_RT2X00=m |
| 106 | CONFIG_RT2500USB=m | 106 | CONFIG_RT2500USB=m |
| 107 | CONFIG_RT73USB=m | 107 | CONFIG_RT73USB=m |
| 108 | CONFIG_RT2800USB=m | 108 | CONFIG_RT2800USB=m |
| 109 | CONFIG_RT2800USB_RT53XX=y | 109 | CONFIG_RT2800USB_RT53XX=y |
| 110 | CONFIG_RT2800USB_RT55XX=y | 110 | CONFIG_RT2800USB_RT55XX=y |
| 111 | CONFIG_RT2800USB_UNKNOWN=y | 111 | CONFIG_RT2800USB_UNKNOWN=y |
| 112 | CONFIG_MWIFIEX=m | 112 | CONFIG_MWIFIEX=m |
| 113 | CONFIG_MWIFIEX_SDIO=m | 113 | CONFIG_MWIFIEX_SDIO=m |
| 114 | CONFIG_MWIFIEX_USB=m | 114 | CONFIG_MWIFIEX_USB=m |
| 115 | # CONFIG_INPUT_MOUSEDEV is not set | 115 | # CONFIG_INPUT_MOUSEDEV is not set |
| 116 | CONFIG_INPUT_EVDEV=y | 116 | CONFIG_INPUT_EVDEV=y |
| 117 | # CONFIG_KEYBOARD_ATKBD is not set | 117 | # CONFIG_KEYBOARD_ATKBD is not set |
| 118 | CONFIG_KEYBOARD_QT1070=y | 118 | CONFIG_KEYBOARD_QT1070=y |
| 119 | CONFIG_KEYBOARD_GPIO=y | 119 | CONFIG_KEYBOARD_GPIO=y |
| 120 | # CONFIG_INPUT_MOUSE is not set | 120 | # CONFIG_INPUT_MOUSE is not set |
| 121 | CONFIG_INPUT_TOUCHSCREEN=y | 121 | CONFIG_INPUT_TOUCHSCREEN=y |
| 122 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y | 122 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y |
| 123 | # CONFIG_SERIO is not set | 123 | # CONFIG_SERIO is not set |
| 124 | CONFIG_LEGACY_PTY_COUNT=4 | 124 | CONFIG_LEGACY_PTY_COUNT=4 |
| 125 | CONFIG_SERIAL_ATMEL=y | 125 | CONFIG_SERIAL_ATMEL=y |
| 126 | CONFIG_SERIAL_ATMEL_CONSOLE=y | 126 | CONFIG_SERIAL_ATMEL_CONSOLE=y |
| 127 | CONFIG_HW_RANDOM=y | 127 | CONFIG_HW_RANDOM=y |
| 128 | CONFIG_I2C=y | 128 | CONFIG_I2C=y |
| 129 | CONFIG_I2C_CHARDEV=y | 129 | CONFIG_I2C_CHARDEV=y |
| 130 | CONFIG_I2C_AT91=y | 130 | CONFIG_I2C_AT91=y |
| 131 | CONFIG_I2C_GPIO=y | 131 | CONFIG_I2C_GPIO=y |
| 132 | CONFIG_SPI=y | 132 | CONFIG_SPI=y |
| 133 | CONFIG_SPI_ATMEL=y | 133 | CONFIG_SPI_ATMEL=y |
| 134 | CONFIG_SPI_GPIO=y | 134 | CONFIG_SPI_GPIO=y |
| 135 | CONFIG_GPIO_SYSFS=y | 135 | CONFIG_GPIO_SYSFS=y |
| 136 | CONFIG_POWER_SUPPLY=y | 136 | CONFIG_POWER_SUPPLY=y |
| 137 | CONFIG_POWER_RESET=y | 137 | CONFIG_POWER_RESET=y |
| 138 | # CONFIG_HWMON is not set | 138 | # CONFIG_HWMON is not set |
| 139 | CONFIG_SSB=m | 139 | CONFIG_SSB=m |
| 140 | CONFIG_REGULATOR=y | 140 | CONFIG_REGULATOR=y |
| 141 | CONFIG_REGULATOR_ACT8865=y | 141 | CONFIG_REGULATOR_ACT8865=y |
| 142 | CONFIG_FB=y | 142 | CONFIG_FB=y |
| 143 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 143 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 144 | # CONFIG_LCD_CLASS_DEVICE is not set | 144 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 145 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 145 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 146 | # CONFIG_BACKLIGHT_GENERIC is not set | 146 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 147 | CONFIG_FRAMEBUFFER_CONSOLE=y | 147 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 148 | CONFIG_SOUND=y | 148 | CONFIG_SOUND=y |
| 149 | CONFIG_SND=y | 149 | CONFIG_SND=y |
| 150 | CONFIG_SND_SOC=y | 150 | CONFIG_SND_SOC=y |
| 151 | CONFIG_SND_ATMEL_SOC=y | 151 | CONFIG_SND_ATMEL_SOC=y |
| 152 | CONFIG_SND_ATMEL_SOC_WM8904=y | 152 | CONFIG_SND_ATMEL_SOC_WM8904=y |
| 153 | # CONFIG_HID_GENERIC is not set | 153 | # CONFIG_HID_GENERIC is not set |
| 154 | CONFIG_USB=y | 154 | CONFIG_USB=y |
| 155 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 155 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 156 | CONFIG_USB_EHCI_HCD=y | 156 | CONFIG_USB_EHCI_HCD=y |
| 157 | CONFIG_USB_OHCI_HCD=y | 157 | CONFIG_USB_OHCI_HCD=y |
| 158 | CONFIG_USB_ACM=y | 158 | CONFIG_USB_ACM=y |
| 159 | CONFIG_USB_STORAGE=y | 159 | CONFIG_USB_STORAGE=y |
| 160 | CONFIG_USB_SERIAL=y | 160 | CONFIG_USB_SERIAL=y |
| 161 | CONFIG_USB_SERIAL_GENERIC=y | 161 | CONFIG_USB_SERIAL_GENERIC=y |
| 162 | CONFIG_USB_SERIAL_FTDI_SIO=y | 162 | CONFIG_USB_SERIAL_FTDI_SIO=y |
| 163 | CONFIG_USB_SERIAL_PL2303=y | 163 | CONFIG_USB_SERIAL_PL2303=y |
| 164 | CONFIG_USB_GADGET=y | 164 | CONFIG_USB_GADGET=y |
| 165 | CONFIG_USB_ATMEL_USBA=y | 165 | CONFIG_USB_ATMEL_USBA=y |
| 166 | CONFIG_USB_G_SERIAL=y | 166 | CONFIG_USB_G_SERIAL=y |
| 167 | CONFIG_MMC=y | 167 | CONFIG_MMC=y |
| 168 | # CONFIG_MMC_BLOCK_BOUNCE is not set | 168 | # CONFIG_MMC_BLOCK_BOUNCE is not set |
| 169 | CONFIG_MMC_ATMELMCI=y | 169 | CONFIG_MMC_ATMELMCI=y |
| 170 | CONFIG_NEW_LEDS=y | 170 | CONFIG_NEW_LEDS=y |
| 171 | CONFIG_LEDS_CLASS=y | 171 | CONFIG_LEDS_CLASS=y |
| 172 | CONFIG_LEDS_GPIO=y | 172 | CONFIG_LEDS_GPIO=y |
| 173 | CONFIG_LEDS_PWM=y | 173 | CONFIG_LEDS_PWM=y |
| 174 | CONFIG_LEDS_TRIGGER_TIMER=y | 174 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 175 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 175 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 176 | CONFIG_LEDS_TRIGGER_GPIO=y | 176 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 177 | CONFIG_RTC_CLASS=y | 177 | CONFIG_RTC_CLASS=y |
| 178 | CONFIG_RTC_DRV_AT91RM9200=y | 178 | CONFIG_RTC_DRV_AT91RM9200=y |
| 179 | CONFIG_DMADEVICES=y | 179 | CONFIG_DMADEVICES=y |
| 180 | CONFIG_AT_XDMAC=y | 180 | CONFIG_AT_XDMAC=y |
| 181 | # CONFIG_IOMMU_SUPPORT is not set | 181 | # CONFIG_IOMMU_SUPPORT is not set |
| 182 | CONFIG_IIO=y | 182 | CONFIG_IIO=y |
| 183 | CONFIG_AT91_ADC=y | 183 | CONFIG_AT91_ADC=y |
| 184 | CONFIG_PWM=y | 184 | CONFIG_PWM=y |
| 185 | CONFIG_PWM_ATMEL=y | 185 | CONFIG_PWM_ATMEL=y |
| 186 | CONFIG_PWM_ATMEL_TCB=y | 186 | CONFIG_PWM_ATMEL_TCB=y |
| 187 | CONFIG_EXT4_FS=y | 187 | CONFIG_EXT4_FS=y |
| 188 | CONFIG_FANOTIFY=y | 188 | CONFIG_FANOTIFY=y |
| 189 | CONFIG_VFAT_FS=y | 189 | CONFIG_VFAT_FS=y |
| 190 | CONFIG_TMPFS=y | 190 | CONFIG_TMPFS=y |
| 191 | CONFIG_UBIFS_FS=y | 191 | CONFIG_UBIFS_FS=y |
| 192 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y | 192 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y |
| 193 | CONFIG_NFS_FS=y | 193 | CONFIG_NFS_FS=y |
| 194 | CONFIG_ROOT_NFS=y | 194 | CONFIG_ROOT_NFS=y |
| 195 | CONFIG_NLS_CODEPAGE_437=y | 195 | CONFIG_NLS_CODEPAGE_437=y |
| 196 | CONFIG_NLS_CODEPAGE_850=y | 196 | CONFIG_NLS_CODEPAGE_850=y |
| 197 | CONFIG_NLS_ISO8859_1=y | 197 | CONFIG_NLS_ISO8859_1=y |
| 198 | CONFIG_NLS_UTF8=y | 198 | CONFIG_NLS_UTF8=y |
| 199 | CONFIG_STRIP_ASM_SYMS=y | 199 | CONFIG_STRIP_ASM_SYMS=y |
| 200 | CONFIG_DEBUG_FS=y | 200 | CONFIG_DEBUG_FS=y |
| 201 | CONFIG_DEBUG_MEMORY_INIT=y | 201 | CONFIG_DEBUG_MEMORY_INIT=y |
| 202 | # CONFIG_SCHED_DEBUG is not set | 202 | # CONFIG_SCHED_DEBUG is not set |
| 203 | # CONFIG_FTRACE is not set | 203 | # CONFIG_FTRACE is not set |
| 204 | CONFIG_DEBUG_USER=y | 204 | CONFIG_DEBUG_USER=y |
| 205 | CONFIG_DEBUG_LL=y | 205 | CONFIG_DEBUG_LL=y |
| 206 | CONFIG_EARLY_PRINTK=y | 206 | CONFIG_EARLY_PRINTK=y |
| 207 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 207 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 208 | CONFIG_CRYPTO_USER_API_HASH=m | 208 | CONFIG_CRYPTO_USER_API_HASH=m |
| 209 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | 209 | CONFIG_CRYPTO_USER_API_SKCIPHER=m |
| 210 | CONFIG_CRYPTO_DEV_ATMEL_AES=y | 210 | CONFIG_CRYPTO_DEV_ATMEL_AES=y |
| 211 | CONFIG_CRYPTO_DEV_ATMEL_TDES=y | 211 | CONFIG_CRYPTO_DEV_ATMEL_TDES=y |
| 212 | CONFIG_CRYPTO_DEV_ATMEL_SHA=y | 212 | CONFIG_CRYPTO_DEV_ATMEL_SHA=y |
| 213 | CONFIG_CRC_CCITT=m | 213 | CONFIG_CRC_CCITT=m |
| 214 | CONFIG_CRC_ITU_T=m | 214 | CONFIG_CRC_ITU_T=m |
| 215 | 215 |
arch/arm/configs/shmobile_defconfig
| 1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 2 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 3 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
| 4 | CONFIG_IKCONFIG_PROC=y | 4 | CONFIG_IKCONFIG_PROC=y |
| 5 | CONFIG_LOG_BUF_SHIFT=16 | 5 | CONFIG_LOG_BUF_SHIFT=16 |
| 6 | CONFIG_BLK_DEV_INITRD=y | 6 | CONFIG_BLK_DEV_INITRD=y |
| 7 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 7 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 8 | CONFIG_SYSCTL_SYSCALL=y | 8 | CONFIG_SYSCTL_SYSCALL=y |
| 9 | CONFIG_EMBEDDED=y | 9 | CONFIG_EMBEDDED=y |
| 10 | CONFIG_PERF_EVENTS=y | 10 | CONFIG_PERF_EVENTS=y |
| 11 | CONFIG_SLAB=y | 11 | CONFIG_SLAB=y |
| 12 | CONFIG_ARCH_SHMOBILE_MULTI=y | 12 | CONFIG_ARCH_SHMOBILE_MULTI=y |
| 13 | CONFIG_ARCH_EMEV2=y | 13 | CONFIG_ARCH_EMEV2=y |
| 14 | CONFIG_ARCH_R7S72100=y | 14 | CONFIG_ARCH_R7S72100=y |
| 15 | CONFIG_ARCH_R8A7740=y | 15 | CONFIG_ARCH_R8A7740=y |
| 16 | CONFIG_ARCH_R8A7779=y | 16 | CONFIG_ARCH_R8A7779=y |
| 17 | CONFIG_ARCH_R8A7790=y | 17 | CONFIG_ARCH_R8A7790=y |
| 18 | CONFIG_ARCH_R8A7791=y | 18 | CONFIG_ARCH_R8A7791=y |
| 19 | CONFIG_ARCH_R8A7794=y | 19 | CONFIG_ARCH_R8A7794=y |
| 20 | CONFIG_MACH_LAGER=y | 20 | CONFIG_MACH_LAGER=y |
| 21 | CONFIG_MACH_MARZEN=y | 21 | CONFIG_MACH_MARZEN=y |
| 22 | # CONFIG_SWP_EMULATE is not set | 22 | # CONFIG_SWP_EMULATE is not set |
| 23 | CONFIG_CPU_BPREDICT_DISABLE=y | 23 | CONFIG_CPU_BPREDICT_DISABLE=y |
| 24 | CONFIG_PL310_ERRATA_588369=y | 24 | CONFIG_PL310_ERRATA_588369=y |
| 25 | CONFIG_ARM_ERRATA_754322=y | 25 | CONFIG_ARM_ERRATA_754322=y |
| 26 | CONFIG_PCI=y | 26 | CONFIG_PCI=y |
| 27 | CONFIG_PCI_RCAR_GEN2=y | 27 | CONFIG_PCI_RCAR_GEN2=y |
| 28 | CONFIG_PCI_RCAR_GEN2_PCIE=y | 28 | CONFIG_PCI_RCAR_GEN2_PCIE=y |
| 29 | CONFIG_SMP=y | 29 | CONFIG_SMP=y |
| 30 | CONFIG_SCHED_MC=y | 30 | CONFIG_SCHED_MC=y |
| 31 | CONFIG_HAVE_ARM_ARCH_TIMER=y | 31 | CONFIG_HAVE_ARM_ARCH_TIMER=y |
| 32 | CONFIG_NR_CPUS=8 | 32 | CONFIG_NR_CPUS=8 |
| 33 | CONFIG_AEABI=y | 33 | CONFIG_AEABI=y |
| 34 | CONFIG_HIGHMEM=y | 34 | CONFIG_HIGHMEM=y |
| 35 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 35 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 36 | CONFIG_ZBOOT_ROM_BSS=0x0 | 36 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 37 | CONFIG_ARM_APPENDED_DTB=y | 37 | CONFIG_ARM_APPENDED_DTB=y |
| 38 | CONFIG_KEXEC=y | 38 | CONFIG_KEXEC=y |
| 39 | CONFIG_VFP=y | 39 | CONFIG_VFP=y |
| 40 | CONFIG_NEON=y | 40 | CONFIG_NEON=y |
| 41 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 41 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 42 | CONFIG_PM_RUNTIME=y | 42 | CONFIG_PM=y |
| 43 | CONFIG_NET=y | 43 | CONFIG_NET=y |
| 44 | CONFIG_PACKET=y | 44 | CONFIG_PACKET=y |
| 45 | CONFIG_UNIX=y | 45 | CONFIG_UNIX=y |
| 46 | CONFIG_INET=y | 46 | CONFIG_INET=y |
| 47 | CONFIG_IP_PNP=y | 47 | CONFIG_IP_PNP=y |
| 48 | CONFIG_IP_PNP_DHCP=y | 48 | CONFIG_IP_PNP_DHCP=y |
| 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 50 | CONFIG_DEVTMPFS=y | 50 | CONFIG_DEVTMPFS=y |
| 51 | CONFIG_DEVTMPFS_MOUNT=y | 51 | CONFIG_DEVTMPFS_MOUNT=y |
| 52 | CONFIG_MTD=y | 52 | CONFIG_MTD=y |
| 53 | CONFIG_MTD_M25P80=y | 53 | CONFIG_MTD_M25P80=y |
| 54 | CONFIG_MTD_SPI_NOR=y | 54 | CONFIG_MTD_SPI_NOR=y |
| 55 | CONFIG_EEPROM_AT24=y | 55 | CONFIG_EEPROM_AT24=y |
| 56 | CONFIG_BLK_DEV_SD=y | 56 | CONFIG_BLK_DEV_SD=y |
| 57 | CONFIG_ATA=y | 57 | CONFIG_ATA=y |
| 58 | CONFIG_SATA_RCAR=y | 58 | CONFIG_SATA_RCAR=y |
| 59 | CONFIG_NETDEVICES=y | 59 | CONFIG_NETDEVICES=y |
| 60 | # CONFIG_NET_VENDOR_ARC is not set | 60 | # CONFIG_NET_VENDOR_ARC is not set |
| 61 | # CONFIG_NET_CADENCE is not set | 61 | # CONFIG_NET_CADENCE is not set |
| 62 | # CONFIG_NET_VENDOR_BROADCOM is not set | 62 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 63 | # CONFIG_NET_VENDOR_CIRRUS is not set | 63 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 64 | # CONFIG_NET_VENDOR_FARADAY is not set | 64 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 65 | # CONFIG_NET_VENDOR_INTEL is not set | 65 | # CONFIG_NET_VENDOR_INTEL is not set |
| 66 | # CONFIG_NET_VENDOR_MARVELL is not set | 66 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 67 | # CONFIG_NET_VENDOR_MICREL is not set | 67 | # CONFIG_NET_VENDOR_MICREL is not set |
| 68 | # CONFIG_NET_VENDOR_NATSEMI is not set | 68 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 69 | CONFIG_SH_ETH=y | 69 | CONFIG_SH_ETH=y |
| 70 | # CONFIG_NET_VENDOR_SEEQ is not set | 70 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 71 | CONFIG_SMSC911X=y | 71 | CONFIG_SMSC911X=y |
| 72 | # CONFIG_NET_VENDOR_STMICRO is not set | 72 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 73 | # CONFIG_NET_VENDOR_VIA is not set | 73 | # CONFIG_NET_VENDOR_VIA is not set |
| 74 | # CONFIG_NET_VENDOR_WIZNET is not set | 74 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 75 | CONFIG_SMSC_PHY=y | 75 | CONFIG_SMSC_PHY=y |
| 76 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 76 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 77 | CONFIG_KEYBOARD_GPIO=y | 77 | CONFIG_KEYBOARD_GPIO=y |
| 78 | # CONFIG_INPUT_MOUSE is not set | 78 | # CONFIG_INPUT_MOUSE is not set |
| 79 | CONFIG_INPUT_TOUCHSCREEN=y | 79 | CONFIG_INPUT_TOUCHSCREEN=y |
| 80 | CONFIG_TOUCHSCREEN_ST1232=y | 80 | CONFIG_TOUCHSCREEN_ST1232=y |
| 81 | # CONFIG_LEGACY_PTYS is not set | 81 | # CONFIG_LEGACY_PTYS is not set |
| 82 | CONFIG_SERIAL_8250=y | 82 | CONFIG_SERIAL_8250=y |
| 83 | CONFIG_SERIAL_8250_CONSOLE=y | 83 | CONFIG_SERIAL_8250_CONSOLE=y |
| 84 | CONFIG_SERIAL_8250_EXTENDED=y | 84 | CONFIG_SERIAL_8250_EXTENDED=y |
| 85 | CONFIG_SERIAL_8250_EM=y | 85 | CONFIG_SERIAL_8250_EM=y |
| 86 | CONFIG_SERIAL_SH_SCI=y | 86 | CONFIG_SERIAL_SH_SCI=y |
| 87 | CONFIG_SERIAL_SH_SCI_NR_UARTS=20 | 87 | CONFIG_SERIAL_SH_SCI_NR_UARTS=20 |
| 88 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 88 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 89 | CONFIG_I2C_GPIO=y | 89 | CONFIG_I2C_GPIO=y |
| 90 | CONFIG_I2C_RIIC=y | 90 | CONFIG_I2C_RIIC=y |
| 91 | CONFIG_I2C_SH_MOBILE=y | 91 | CONFIG_I2C_SH_MOBILE=y |
| 92 | CONFIG_I2C_RCAR=y | 92 | CONFIG_I2C_RCAR=y |
| 93 | CONFIG_SPI=y | 93 | CONFIG_SPI=y |
| 94 | CONFIG_SPI_RSPI=y | 94 | CONFIG_SPI_RSPI=y |
| 95 | CONFIG_SPI_SH_MSIOF=y | 95 | CONFIG_SPI_SH_MSIOF=y |
| 96 | CONFIG_SPI_SH_HSPI=y | 96 | CONFIG_SPI_SH_HSPI=y |
| 97 | CONFIG_GPIO_EM=y | 97 | CONFIG_GPIO_EM=y |
| 98 | CONFIG_GPIO_RCAR=y | 98 | CONFIG_GPIO_RCAR=y |
| 99 | # CONFIG_HWMON is not set | 99 | # CONFIG_HWMON is not set |
| 100 | CONFIG_THERMAL=y | 100 | CONFIG_THERMAL=y |
| 101 | CONFIG_RCAR_THERMAL=y | 101 | CONFIG_RCAR_THERMAL=y |
| 102 | CONFIG_REGULATOR=y | 102 | CONFIG_REGULATOR=y |
| 103 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 103 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 104 | CONFIG_REGULATOR_GPIO=y | 104 | CONFIG_REGULATOR_GPIO=y |
| 105 | CONFIG_MEDIA_SUPPORT=y | 105 | CONFIG_MEDIA_SUPPORT=y |
| 106 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 106 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 107 | CONFIG_MEDIA_CONTROLLER=y | 107 | CONFIG_MEDIA_CONTROLLER=y |
| 108 | CONFIG_VIDEO_V4L2_SUBDEV_API=y | 108 | CONFIG_VIDEO_V4L2_SUBDEV_API=y |
| 109 | CONFIG_V4L_PLATFORM_DRIVERS=y | 109 | CONFIG_V4L_PLATFORM_DRIVERS=y |
| 110 | CONFIG_SOC_CAMERA=y | 110 | CONFIG_SOC_CAMERA=y |
| 111 | CONFIG_SOC_CAMERA_PLATFORM=y | 111 | CONFIG_SOC_CAMERA_PLATFORM=y |
| 112 | CONFIG_VIDEO_RCAR_VIN=y | 112 | CONFIG_VIDEO_RCAR_VIN=y |
| 113 | CONFIG_V4L_MEM2MEM_DRIVERS=y | 113 | CONFIG_V4L_MEM2MEM_DRIVERS=y |
| 114 | CONFIG_VIDEO_RENESAS_VSP1=y | 114 | CONFIG_VIDEO_RENESAS_VSP1=y |
| 115 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set | 115 | # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set |
| 116 | CONFIG_VIDEO_ADV7180=y | 116 | CONFIG_VIDEO_ADV7180=y |
| 117 | CONFIG_DRM=y | 117 | CONFIG_DRM=y |
| 118 | CONFIG_DRM_RCAR_DU=y | 118 | CONFIG_DRM_RCAR_DU=y |
| 119 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 119 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 120 | # CONFIG_LCD_CLASS_DEVICE is not set | 120 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 121 | # CONFIG_BACKLIGHT_GENERIC is not set | 121 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 122 | CONFIG_BACKLIGHT_PWM=y | 122 | CONFIG_BACKLIGHT_PWM=y |
| 123 | CONFIG_SOUND=y | 123 | CONFIG_SOUND=y |
| 124 | CONFIG_SND=y | 124 | CONFIG_SND=y |
| 125 | CONFIG_SND_SOC=y | 125 | CONFIG_SND_SOC=y |
| 126 | CONFIG_SND_SOC_SH4_FSI=y | 126 | CONFIG_SND_SOC_SH4_FSI=y |
| 127 | CONFIG_SND_SOC_RCAR=y | 127 | CONFIG_SND_SOC_RCAR=y |
| 128 | CONFIG_SND_SOC_AK4642=y | 128 | CONFIG_SND_SOC_AK4642=y |
| 129 | CONFIG_SND_SOC_WM8978=y | 129 | CONFIG_SND_SOC_WM8978=y |
| 130 | CONFIG_USB=y | 130 | CONFIG_USB=y |
| 131 | CONFIG_USB_EHCI_HCD=y | 131 | CONFIG_USB_EHCI_HCD=y |
| 132 | CONFIG_USB_OHCI_HCD=y | 132 | CONFIG_USB_OHCI_HCD=y |
| 133 | CONFIG_USB_RENESAS_USBHS=y | 133 | CONFIG_USB_RENESAS_USBHS=y |
| 134 | CONFIG_USB_RCAR_PHY=y | 134 | CONFIG_USB_RCAR_PHY=y |
| 135 | CONFIG_USB_RCAR_GEN2_PHY=y | 135 | CONFIG_USB_RCAR_GEN2_PHY=y |
| 136 | CONFIG_USB_GADGET=y | 136 | CONFIG_USB_GADGET=y |
| 137 | CONFIG_USB_RENESAS_USBHS_UDC=y | 137 | CONFIG_USB_RENESAS_USBHS_UDC=y |
| 138 | CONFIG_USB_ETH=y | 138 | CONFIG_USB_ETH=y |
| 139 | CONFIG_MMC=y | 139 | CONFIG_MMC=y |
| 140 | CONFIG_MMC_SDHI=y | 140 | CONFIG_MMC_SDHI=y |
| 141 | CONFIG_MMC_SH_MMCIF=y | 141 | CONFIG_MMC_SH_MMCIF=y |
| 142 | CONFIG_NEW_LEDS=y | 142 | CONFIG_NEW_LEDS=y |
| 143 | CONFIG_LEDS_CLASS=y | 143 | CONFIG_LEDS_CLASS=y |
| 144 | CONFIG_LEDS_GPIO=y | 144 | CONFIG_LEDS_GPIO=y |
| 145 | CONFIG_RTC_CLASS=y | 145 | CONFIG_RTC_CLASS=y |
| 146 | CONFIG_RTC_DRV_S35390A=y | 146 | CONFIG_RTC_DRV_S35390A=y |
| 147 | CONFIG_DMADEVICES=y | 147 | CONFIG_DMADEVICES=y |
| 148 | CONFIG_SH_DMAE=y | 148 | CONFIG_SH_DMAE=y |
| 149 | CONFIG_RCAR_DMAC=y | 149 | CONFIG_RCAR_DMAC=y |
| 150 | # CONFIG_IOMMU_SUPPORT is not set | 150 | # CONFIG_IOMMU_SUPPORT is not set |
| 151 | CONFIG_PWM=y | 151 | CONFIG_PWM=y |
| 152 | CONFIG_PWM_RENESAS_TPU=y | 152 | CONFIG_PWM_RENESAS_TPU=y |
| 153 | # CONFIG_DNOTIFY is not set | 153 | # CONFIG_DNOTIFY is not set |
| 154 | CONFIG_MSDOS_FS=y | 154 | CONFIG_MSDOS_FS=y |
| 155 | CONFIG_VFAT_FS=y | 155 | CONFIG_VFAT_FS=y |
| 156 | CONFIG_TMPFS=y | 156 | CONFIG_TMPFS=y |
| 157 | CONFIG_CONFIGFS_FS=y | 157 | CONFIG_CONFIGFS_FS=y |
| 158 | # CONFIG_MISC_FILESYSTEMS is not set | 158 | # CONFIG_MISC_FILESYSTEMS is not set |
| 159 | CONFIG_NFS_FS=y | 159 | CONFIG_NFS_FS=y |
| 160 | CONFIG_NFS_V3_ACL=y | 160 | CONFIG_NFS_V3_ACL=y |
| 161 | CONFIG_NFS_V4=y | 161 | CONFIG_NFS_V4=y |
| 162 | CONFIG_NFS_V4_1=y | 162 | CONFIG_NFS_V4_1=y |
| 163 | CONFIG_ROOT_NFS=y | 163 | CONFIG_ROOT_NFS=y |
| 164 | CONFIG_NLS_CODEPAGE_437=y | 164 | CONFIG_NLS_CODEPAGE_437=y |
| 165 | CONFIG_NLS_ISO8859_1=y | 165 | CONFIG_NLS_ISO8859_1=y |
| 166 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 166 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 167 | # CONFIG_ENABLE_MUST_CHECK is not set | 167 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 168 | # CONFIG_ARM_UNWIND is not set | 168 | # CONFIG_ARM_UNWIND is not set |
| 169 | CONFIG_CPU_FREQ=y | 169 | CONFIG_CPU_FREQ=y |
| 170 | CONFIG_CPU_FREQ_GOV_COMMON=y | 170 | CONFIG_CPU_FREQ_GOV_COMMON=y |
| 171 | CONFIG_CPU_FREQ_STAT=y | 171 | CONFIG_CPU_FREQ_STAT=y |
| 172 | CONFIG_CPU_FREQ_STAT_DETAILS=y | 172 | CONFIG_CPU_FREQ_STAT_DETAILS=y |
| 173 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | 173 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y |
| 174 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | 174 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y |
| 175 | CONFIG_CPU_FREQ_GOV_POWERSAVE=y | 175 | CONFIG_CPU_FREQ_GOV_POWERSAVE=y |
| 176 | CONFIG_CPU_FREQ_GOV_USERSPACE=y | 176 | CONFIG_CPU_FREQ_GOV_USERSPACE=y |
| 177 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | 177 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y |
| 178 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y | 178 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y |
| 179 | CONFIG_CPU_THERMAL=y | 179 | CONFIG_CPU_THERMAL=y |
| 180 | CONFIG_CPUFREQ_DT=y | 180 | CONFIG_CPUFREQ_DT=y |
| 181 | CONFIG_REGULATOR_DA9210=y | 181 | CONFIG_REGULATOR_DA9210=y |
| 182 | 182 |
arch/arm/configs/sunxi_defconfig
| 1 | CONFIG_NO_HZ=y | 1 | CONFIG_NO_HZ=y |
| 2 | CONFIG_HIGH_RES_TIMERS=y | 2 | CONFIG_HIGH_RES_TIMERS=y |
| 3 | CONFIG_BLK_DEV_INITRD=y | 3 | CONFIG_BLK_DEV_INITRD=y |
| 4 | CONFIG_PERF_EVENTS=y | 4 | CONFIG_PERF_EVENTS=y |
| 5 | CONFIG_ARCH_SUNXI=y | 5 | CONFIG_ARCH_SUNXI=y |
| 6 | CONFIG_SMP=y | 6 | CONFIG_SMP=y |
| 7 | CONFIG_AEABI=y | 7 | CONFIG_AEABI=y |
| 8 | CONFIG_HIGHMEM=y | 8 | CONFIG_HIGHMEM=y |
| 9 | CONFIG_HIGHPTE=y | 9 | CONFIG_HIGHPTE=y |
| 10 | CONFIG_ARM_APPENDED_DTB=y | 10 | CONFIG_ARM_APPENDED_DTB=y |
| 11 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 11 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 12 | CONFIG_VFP=y | 12 | CONFIG_VFP=y |
| 13 | CONFIG_NEON=y | 13 | CONFIG_NEON=y |
| 14 | CONFIG_PM_RUNTIME=y | 14 | CONFIG_PM=y |
| 15 | CONFIG_NET=y | 15 | CONFIG_NET=y |
| 16 | CONFIG_PACKET=y | 16 | CONFIG_PACKET=y |
| 17 | CONFIG_UNIX=y | 17 | CONFIG_UNIX=y |
| 18 | CONFIG_INET=y | 18 | CONFIG_INET=y |
| 19 | CONFIG_IP_PNP=y | 19 | CONFIG_IP_PNP=y |
| 20 | CONFIG_IP_PNP_DHCP=y | 20 | CONFIG_IP_PNP_DHCP=y |
| 21 | CONFIG_IP_PNP_BOOTP=y | 21 | CONFIG_IP_PNP_BOOTP=y |
| 22 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 22 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 23 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 23 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 24 | # CONFIG_INET_XFRM_MODE_BEET is not set | 24 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 25 | # CONFIG_INET_LRO is not set | 25 | # CONFIG_INET_LRO is not set |
| 26 | # CONFIG_INET_DIAG is not set | 26 | # CONFIG_INET_DIAG is not set |
| 27 | # CONFIG_IPV6 is not set | 27 | # CONFIG_IPV6 is not set |
| 28 | # CONFIG_WIRELESS is not set | 28 | # CONFIG_WIRELESS is not set |
| 29 | CONFIG_DEVTMPFS=y | 29 | CONFIG_DEVTMPFS=y |
| 30 | CONFIG_DEVTMPFS_MOUNT=y | 30 | CONFIG_DEVTMPFS_MOUNT=y |
| 31 | CONFIG_EEPROM_SUNXI_SID=y | 31 | CONFIG_EEPROM_SUNXI_SID=y |
| 32 | CONFIG_BLK_DEV_SD=y | 32 | CONFIG_BLK_DEV_SD=y |
| 33 | CONFIG_ATA=y | 33 | CONFIG_ATA=y |
| 34 | CONFIG_AHCI_SUNXI=y | 34 | CONFIG_AHCI_SUNXI=y |
| 35 | CONFIG_NETDEVICES=y | 35 | CONFIG_NETDEVICES=y |
| 36 | CONFIG_SUN4I_EMAC=y | 36 | CONFIG_SUN4I_EMAC=y |
| 37 | # CONFIG_NET_VENDOR_ARC is not set | 37 | # CONFIG_NET_VENDOR_ARC is not set |
| 38 | # CONFIG_NET_CADENCE is not set | 38 | # CONFIG_NET_CADENCE is not set |
| 39 | # CONFIG_NET_VENDOR_BROADCOM is not set | 39 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 40 | # CONFIG_NET_VENDOR_CIRRUS is not set | 40 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 41 | # CONFIG_NET_VENDOR_FARADAY is not set | 41 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 42 | # CONFIG_NET_VENDOR_INTEL is not set | 42 | # CONFIG_NET_VENDOR_INTEL is not set |
| 43 | # CONFIG_NET_VENDOR_MARVELL is not set | 43 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 44 | # CONFIG_NET_VENDOR_MICREL is not set | 44 | # CONFIG_NET_VENDOR_MICREL is not set |
| 45 | # CONFIG_NET_VENDOR_MICROCHIP is not set | 45 | # CONFIG_NET_VENDOR_MICROCHIP is not set |
| 46 | # CONFIG_NET_VENDOR_NATSEMI is not set | 46 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 47 | # CONFIG_NET_VENDOR_SAMSUNG is not set | 47 | # CONFIG_NET_VENDOR_SAMSUNG is not set |
| 48 | # CONFIG_NET_VENDOR_SEEQ is not set | 48 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 49 | # CONFIG_NET_VENDOR_SMSC is not set | 49 | # CONFIG_NET_VENDOR_SMSC is not set |
| 50 | CONFIG_STMMAC_ETH=y | 50 | CONFIG_STMMAC_ETH=y |
| 51 | # CONFIG_NET_VENDOR_VIA is not set | 51 | # CONFIG_NET_VENDOR_VIA is not set |
| 52 | # CONFIG_NET_VENDOR_WIZNET is not set | 52 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 53 | # CONFIG_WLAN is not set | 53 | # CONFIG_WLAN is not set |
| 54 | # CONFIG_INPUT_MOUSEDEV is not set | 54 | # CONFIG_INPUT_MOUSEDEV is not set |
| 55 | # CONFIG_INPUT_KEYBOARD is not set | 55 | # CONFIG_INPUT_KEYBOARD is not set |
| 56 | # CONFIG_INPUT_MOUSE is not set | 56 | # CONFIG_INPUT_MOUSE is not set |
| 57 | CONFIG_SERIAL_8250=y | 57 | CONFIG_SERIAL_8250=y |
| 58 | CONFIG_SERIAL_8250_CONSOLE=y | 58 | CONFIG_SERIAL_8250_CONSOLE=y |
| 59 | CONFIG_SERIAL_8250_NR_UARTS=8 | 59 | CONFIG_SERIAL_8250_NR_UARTS=8 |
| 60 | CONFIG_SERIAL_8250_RUNTIME_UARTS=8 | 60 | CONFIG_SERIAL_8250_RUNTIME_UARTS=8 |
| 61 | CONFIG_SERIAL_8250_DW=y | 61 | CONFIG_SERIAL_8250_DW=y |
| 62 | CONFIG_SERIAL_OF_PLATFORM=y | 62 | CONFIG_SERIAL_OF_PLATFORM=y |
| 63 | # CONFIG_HW_RANDOM is not set | 63 | # CONFIG_HW_RANDOM is not set |
| 64 | CONFIG_I2C=y | 64 | CONFIG_I2C=y |
| 65 | CONFIG_I2C_CHARDEV=y | 65 | CONFIG_I2C_CHARDEV=y |
| 66 | CONFIG_I2C_MV64XXX=y | 66 | CONFIG_I2C_MV64XXX=y |
| 67 | CONFIG_SPI=y | 67 | CONFIG_SPI=y |
| 68 | CONFIG_SPI_SUN4I=y | 68 | CONFIG_SPI_SUN4I=y |
| 69 | CONFIG_SPI_SUN6I=y | 69 | CONFIG_SPI_SUN6I=y |
| 70 | CONFIG_GPIO_SYSFS=y | 70 | CONFIG_GPIO_SYSFS=y |
| 71 | CONFIG_POWER_SUPPLY=y | 71 | CONFIG_POWER_SUPPLY=y |
| 72 | CONFIG_POWER_RESET=y | 72 | CONFIG_POWER_RESET=y |
| 73 | CONFIG_POWER_RESET_SUN6I=y | 73 | CONFIG_POWER_RESET_SUN6I=y |
| 74 | # CONFIG_HWMON is not set | 74 | # CONFIG_HWMON is not set |
| 75 | CONFIG_WATCHDOG=y | 75 | CONFIG_WATCHDOG=y |
| 76 | CONFIG_SUNXI_WATCHDOG=y | 76 | CONFIG_SUNXI_WATCHDOG=y |
| 77 | CONFIG_MFD_AXP20X=y | 77 | CONFIG_MFD_AXP20X=y |
| 78 | CONFIG_REGULATOR=y | 78 | CONFIG_REGULATOR=y |
| 79 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 79 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 80 | CONFIG_REGULATOR_GPIO=y | 80 | CONFIG_REGULATOR_GPIO=y |
| 81 | CONFIG_USB=y | 81 | CONFIG_USB=y |
| 82 | CONFIG_USB_EHCI_HCD=y | 82 | CONFIG_USB_EHCI_HCD=y |
| 83 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 83 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 84 | CONFIG_USB_OHCI_HCD=y | 84 | CONFIG_USB_OHCI_HCD=y |
| 85 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 85 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 86 | CONFIG_MMC=y | 86 | CONFIG_MMC=y |
| 87 | CONFIG_MMC_SUNXI=y | 87 | CONFIG_MMC_SUNXI=y |
| 88 | CONFIG_NEW_LEDS=y | 88 | CONFIG_NEW_LEDS=y |
| 89 | CONFIG_LEDS_CLASS=y | 89 | CONFIG_LEDS_CLASS=y |
| 90 | CONFIG_LEDS_GPIO=y | 90 | CONFIG_LEDS_GPIO=y |
| 91 | CONFIG_LEDS_TRIGGERS=y | 91 | CONFIG_LEDS_TRIGGERS=y |
| 92 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 92 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 93 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 93 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 94 | CONFIG_RTC_CLASS=y | 94 | CONFIG_RTC_CLASS=y |
| 95 | # CONFIG_RTC_INTF_SYSFS is not set | 95 | # CONFIG_RTC_INTF_SYSFS is not set |
| 96 | # CONFIG_RTC_INTF_PROC is not set | 96 | # CONFIG_RTC_INTF_PROC is not set |
| 97 | CONFIG_RTC_DRV_SUN6I=y | 97 | CONFIG_RTC_DRV_SUN6I=y |
| 98 | CONFIG_RTC_DRV_SUNXI=y | 98 | CONFIG_RTC_DRV_SUNXI=y |
| 99 | # CONFIG_IOMMU_SUPPORT is not set | 99 | # CONFIG_IOMMU_SUPPORT is not set |
| 100 | CONFIG_PHY_SUN4I_USB=y | 100 | CONFIG_PHY_SUN4I_USB=y |
| 101 | CONFIG_EXT4_FS=y | 101 | CONFIG_EXT4_FS=y |
| 102 | CONFIG_VFAT_FS=y | 102 | CONFIG_VFAT_FS=y |
| 103 | CONFIG_TMPFS=y | 103 | CONFIG_TMPFS=y |
| 104 | CONFIG_NFS_FS=y | 104 | CONFIG_NFS_FS=y |
| 105 | CONFIG_NFS_V3_ACL=y | 105 | CONFIG_NFS_V3_ACL=y |
| 106 | CONFIG_NFS_V4=y | 106 | CONFIG_NFS_V4=y |
| 107 | CONFIG_ROOT_NFS=y | 107 | CONFIG_ROOT_NFS=y |
| 108 | CONFIG_NLS_CODEPAGE_437=y | 108 | CONFIG_NLS_CODEPAGE_437=y |
| 109 | CONFIG_NLS_ISO8859_1=y | 109 | CONFIG_NLS_ISO8859_1=y |
| 110 | CONFIG_PRINTK_TIME=y | 110 | CONFIG_PRINTK_TIME=y |
| 111 | CONFIG_DEBUG_FS=y | 111 | CONFIG_DEBUG_FS=y |
| 112 | 112 |
arch/arm/configs/tegra_defconfig
| 1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 2 | CONFIG_FHANDLE=y | 2 | CONFIG_FHANDLE=y |
| 3 | CONFIG_NO_HZ=y | 3 | CONFIG_NO_HZ=y |
| 4 | CONFIG_HIGH_RES_TIMERS=y | 4 | CONFIG_HIGH_RES_TIMERS=y |
| 5 | CONFIG_IKCONFIG=y | 5 | CONFIG_IKCONFIG=y |
| 6 | CONFIG_IKCONFIG_PROC=y | 6 | CONFIG_IKCONFIG_PROC=y |
| 7 | CONFIG_CGROUPS=y | 7 | CONFIG_CGROUPS=y |
| 8 | CONFIG_CGROUP_DEBUG=y | 8 | CONFIG_CGROUP_DEBUG=y |
| 9 | CONFIG_CGROUP_FREEZER=y | 9 | CONFIG_CGROUP_FREEZER=y |
| 10 | CONFIG_CGROUP_CPUACCT=y | 10 | CONFIG_CGROUP_CPUACCT=y |
| 11 | CONFIG_RESOURCE_COUNTERS=y | 11 | CONFIG_RESOURCE_COUNTERS=y |
| 12 | CONFIG_CGROUP_SCHED=y | 12 | CONFIG_CGROUP_SCHED=y |
| 13 | CONFIG_RT_GROUP_SCHED=y | 13 | CONFIG_RT_GROUP_SCHED=y |
| 14 | CONFIG_BLK_DEV_INITRD=y | 14 | CONFIG_BLK_DEV_INITRD=y |
| 15 | # CONFIG_ELF_CORE is not set | 15 | # CONFIG_ELF_CORE is not set |
| 16 | CONFIG_EMBEDDED=y | 16 | CONFIG_EMBEDDED=y |
| 17 | CONFIG_PERF_EVENTS=y | 17 | CONFIG_PERF_EVENTS=y |
| 18 | CONFIG_SLAB=y | 18 | CONFIG_SLAB=y |
| 19 | CONFIG_MODULES=y | 19 | CONFIG_MODULES=y |
| 20 | CONFIG_MODULE_UNLOAD=y | 20 | CONFIG_MODULE_UNLOAD=y |
| 21 | CONFIG_MODULE_FORCE_UNLOAD=y | 21 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 22 | # CONFIG_BLK_DEV_BSG is not set | 22 | # CONFIG_BLK_DEV_BSG is not set |
| 23 | CONFIG_PARTITION_ADVANCED=y | 23 | CONFIG_PARTITION_ADVANCED=y |
| 24 | # CONFIG_IOSCHED_DEADLINE is not set | 24 | # CONFIG_IOSCHED_DEADLINE is not set |
| 25 | # CONFIG_IOSCHED_CFQ is not set | 25 | # CONFIG_IOSCHED_CFQ is not set |
| 26 | CONFIG_ARCH_TEGRA=y | 26 | CONFIG_ARCH_TEGRA=y |
| 27 | CONFIG_ARCH_TEGRA_2x_SOC=y | 27 | CONFIG_ARCH_TEGRA_2x_SOC=y |
| 28 | CONFIG_ARCH_TEGRA_3x_SOC=y | 28 | CONFIG_ARCH_TEGRA_3x_SOC=y |
| 29 | CONFIG_ARCH_TEGRA_114_SOC=y | 29 | CONFIG_ARCH_TEGRA_114_SOC=y |
| 30 | CONFIG_ARCH_TEGRA_124_SOC=y | 30 | CONFIG_ARCH_TEGRA_124_SOC=y |
| 31 | CONFIG_PCI=y | 31 | CONFIG_PCI=y |
| 32 | CONFIG_PCI_MSI=y | 32 | CONFIG_PCI_MSI=y |
| 33 | CONFIG_PCI_TEGRA=y | 33 | CONFIG_PCI_TEGRA=y |
| 34 | CONFIG_PCIEPORTBUS=y | 34 | CONFIG_PCIEPORTBUS=y |
| 35 | CONFIG_SMP=y | 35 | CONFIG_SMP=y |
| 36 | CONFIG_PREEMPT=y | 36 | CONFIG_PREEMPT=y |
| 37 | CONFIG_AEABI=y | 37 | CONFIG_AEABI=y |
| 38 | CONFIG_HIGHMEM=y | 38 | CONFIG_HIGHMEM=y |
| 39 | CONFIG_CMA=y | 39 | CONFIG_CMA=y |
| 40 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 40 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 41 | CONFIG_ZBOOT_ROM_BSS=0x0 | 41 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 42 | CONFIG_KEXEC=y | 42 | CONFIG_KEXEC=y |
| 43 | CONFIG_CPU_FREQ=y | 43 | CONFIG_CPU_FREQ=y |
| 44 | CONFIG_CPU_FREQ_STAT_DETAILS=y | 44 | CONFIG_CPU_FREQ_STAT_DETAILS=y |
| 45 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | 45 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y |
| 46 | CONFIG_CPU_IDLE=y | 46 | CONFIG_CPU_IDLE=y |
| 47 | CONFIG_VFP=y | 47 | CONFIG_VFP=y |
| 48 | CONFIG_NEON=y | 48 | CONFIG_NEON=y |
| 49 | CONFIG_PM_RUNTIME=y | 49 | CONFIG_PM=y |
| 50 | CONFIG_NET=y | 50 | CONFIG_NET=y |
| 51 | CONFIG_PACKET=y | 51 | CONFIG_PACKET=y |
| 52 | CONFIG_UNIX=y | 52 | CONFIG_UNIX=y |
| 53 | CONFIG_NET_KEY=y | 53 | CONFIG_NET_KEY=y |
| 54 | CONFIG_INET=y | 54 | CONFIG_INET=y |
| 55 | CONFIG_IP_PNP=y | 55 | CONFIG_IP_PNP=y |
| 56 | CONFIG_IP_PNP_DHCP=y | 56 | CONFIG_IP_PNP_DHCP=y |
| 57 | CONFIG_IP_PNP_BOOTP=y | 57 | CONFIG_IP_PNP_BOOTP=y |
| 58 | CONFIG_IP_PNP_RARP=y | 58 | CONFIG_IP_PNP_RARP=y |
| 59 | CONFIG_INET_ESP=y | 59 | CONFIG_INET_ESP=y |
| 60 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 60 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 61 | # CONFIG_INET_XFRM_MODE_BEET is not set | 61 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 62 | # CONFIG_INET_LRO is not set | 62 | # CONFIG_INET_LRO is not set |
| 63 | # CONFIG_INET_DIAG is not set | 63 | # CONFIG_INET_DIAG is not set |
| 64 | CONFIG_IPV6=y | 64 | CONFIG_IPV6=y |
| 65 | CONFIG_IPV6_ROUTER_PREF=y | 65 | CONFIG_IPV6_ROUTER_PREF=y |
| 66 | CONFIG_IPV6_OPTIMISTIC_DAD=y | 66 | CONFIG_IPV6_OPTIMISTIC_DAD=y |
| 67 | CONFIG_INET6_AH=y | 67 | CONFIG_INET6_AH=y |
| 68 | CONFIG_INET6_ESP=y | 68 | CONFIG_INET6_ESP=y |
| 69 | CONFIG_INET6_IPCOMP=y | 69 | CONFIG_INET6_IPCOMP=y |
| 70 | CONFIG_IPV6_MIP6=y | 70 | CONFIG_IPV6_MIP6=y |
| 71 | CONFIG_IPV6_TUNNEL=y | 71 | CONFIG_IPV6_TUNNEL=y |
| 72 | CONFIG_IPV6_MULTIPLE_TABLES=y | 72 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 73 | CONFIG_CAN=y | 73 | CONFIG_CAN=y |
| 74 | CONFIG_CAN_MCP251X=y | 74 | CONFIG_CAN_MCP251X=y |
| 75 | CONFIG_BT=y | 75 | CONFIG_BT=y |
| 76 | CONFIG_BT_RFCOMM=y | 76 | CONFIG_BT_RFCOMM=y |
| 77 | CONFIG_BT_BNEP=y | 77 | CONFIG_BT_BNEP=y |
| 78 | CONFIG_BT_HIDP=y | 78 | CONFIG_BT_HIDP=y |
| 79 | CONFIG_BT_HCIBTUSB=m | 79 | CONFIG_BT_HCIBTUSB=m |
| 80 | CONFIG_CFG80211=y | 80 | CONFIG_CFG80211=y |
| 81 | CONFIG_MAC80211=y | 81 | CONFIG_MAC80211=y |
| 82 | CONFIG_RFKILL=y | 82 | CONFIG_RFKILL=y |
| 83 | CONFIG_RFKILL_INPUT=y | 83 | CONFIG_RFKILL_INPUT=y |
| 84 | CONFIG_RFKILL_GPIO=y | 84 | CONFIG_RFKILL_GPIO=y |
| 85 | CONFIG_DEVTMPFS=y | 85 | CONFIG_DEVTMPFS=y |
| 86 | CONFIG_DEVTMPFS_MOUNT=y | 86 | CONFIG_DEVTMPFS_MOUNT=y |
| 87 | # CONFIG_FIRMWARE_IN_KERNEL is not set | 87 | # CONFIG_FIRMWARE_IN_KERNEL is not set |
| 88 | CONFIG_DMA_CMA=y | 88 | CONFIG_DMA_CMA=y |
| 89 | CONFIG_CMA_SIZE_MBYTES=64 | 89 | CONFIG_CMA_SIZE_MBYTES=64 |
| 90 | CONFIG_MTD=y | 90 | CONFIG_MTD=y |
| 91 | CONFIG_MTD_M25P80=y | 91 | CONFIG_MTD_M25P80=y |
| 92 | CONFIG_MTD_SPI_NOR=y | 92 | CONFIG_MTD_SPI_NOR=y |
| 93 | CONFIG_BLK_DEV_LOOP=y | 93 | CONFIG_BLK_DEV_LOOP=y |
| 94 | CONFIG_AD525X_DPOT=y | 94 | CONFIG_AD525X_DPOT=y |
| 95 | CONFIG_AD525X_DPOT_I2C=y | 95 | CONFIG_AD525X_DPOT_I2C=y |
| 96 | CONFIG_ICS932S401=y | 96 | CONFIG_ICS932S401=y |
| 97 | CONFIG_APDS9802ALS=y | 97 | CONFIG_APDS9802ALS=y |
| 98 | CONFIG_ISL29003=y | 98 | CONFIG_ISL29003=y |
| 99 | CONFIG_EEPROM_AT24=y | 99 | CONFIG_EEPROM_AT24=y |
| 100 | CONFIG_BLK_DEV_SD=y | 100 | CONFIG_BLK_DEV_SD=y |
| 101 | CONFIG_BLK_DEV_SR=y | 101 | CONFIG_BLK_DEV_SR=y |
| 102 | # CONFIG_SCSI_LOWLEVEL is not set | 102 | # CONFIG_SCSI_LOWLEVEL is not set |
| 103 | CONFIG_ATA=y | 103 | CONFIG_ATA=y |
| 104 | CONFIG_SATA_AHCI=y | 104 | CONFIG_SATA_AHCI=y |
| 105 | CONFIG_AHCI_TEGRA=y | 105 | CONFIG_AHCI_TEGRA=y |
| 106 | CONFIG_NETDEVICES=y | 106 | CONFIG_NETDEVICES=y |
| 107 | CONFIG_DUMMY=y | 107 | CONFIG_DUMMY=y |
| 108 | CONFIG_IGB=y | 108 | CONFIG_IGB=y |
| 109 | CONFIG_R8169=y | 109 | CONFIG_R8169=y |
| 110 | CONFIG_USB_PEGASUS=y | 110 | CONFIG_USB_PEGASUS=y |
| 111 | CONFIG_USB_USBNET=y | 111 | CONFIG_USB_USBNET=y |
| 112 | CONFIG_USB_NET_SMSC75XX=y | 112 | CONFIG_USB_NET_SMSC75XX=y |
| 113 | CONFIG_USB_NET_SMSC95XX=y | 113 | CONFIG_USB_NET_SMSC95XX=y |
| 114 | CONFIG_BRCMFMAC=m | 114 | CONFIG_BRCMFMAC=m |
| 115 | CONFIG_RT2X00=y | 115 | CONFIG_RT2X00=y |
| 116 | CONFIG_RT2800USB=m | 116 | CONFIG_RT2800USB=m |
| 117 | CONFIG_INPUT_JOYDEV=y | 117 | CONFIG_INPUT_JOYDEV=y |
| 118 | CONFIG_INPUT_EVDEV=y | 118 | CONFIG_INPUT_EVDEV=y |
| 119 | CONFIG_KEYBOARD_GPIO=y | 119 | CONFIG_KEYBOARD_GPIO=y |
| 120 | CONFIG_KEYBOARD_TEGRA=y | 120 | CONFIG_KEYBOARD_TEGRA=y |
| 121 | CONFIG_KEYBOARD_CROS_EC=y | 121 | CONFIG_KEYBOARD_CROS_EC=y |
| 122 | CONFIG_MOUSE_PS2_ELANTECH=y | 122 | CONFIG_MOUSE_PS2_ELANTECH=y |
| 123 | CONFIG_INPUT_TOUCHSCREEN=y | 123 | CONFIG_INPUT_TOUCHSCREEN=y |
| 124 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y | 124 | CONFIG_TOUCHSCREEN_ATMEL_MXT=y |
| 125 | CONFIG_TOUCHSCREEN_STMPE=y | 125 | CONFIG_TOUCHSCREEN_STMPE=y |
| 126 | CONFIG_INPUT_MISC=y | 126 | CONFIG_INPUT_MISC=y |
| 127 | CONFIG_INPUT_MPU3050=y | 127 | CONFIG_INPUT_MPU3050=y |
| 128 | # CONFIG_LEGACY_PTYS is not set | 128 | # CONFIG_LEGACY_PTYS is not set |
| 129 | # CONFIG_DEVKMEM is not set | 129 | # CONFIG_DEVKMEM is not set |
| 130 | CONFIG_SERIAL_8250=y | 130 | CONFIG_SERIAL_8250=y |
| 131 | CONFIG_SERIAL_8250_CONSOLE=y | 131 | CONFIG_SERIAL_8250_CONSOLE=y |
| 132 | CONFIG_SERIAL_TEGRA=y | 132 | CONFIG_SERIAL_TEGRA=y |
| 133 | CONFIG_SERIAL_OF_PLATFORM=y | 133 | CONFIG_SERIAL_OF_PLATFORM=y |
| 134 | # CONFIG_HW_RANDOM is not set | 134 | # CONFIG_HW_RANDOM is not set |
| 135 | # CONFIG_I2C_COMPAT is not set | 135 | # CONFIG_I2C_COMPAT is not set |
| 136 | CONFIG_I2C_CHARDEV=y | 136 | CONFIG_I2C_CHARDEV=y |
| 137 | CONFIG_I2C_MUX_PCA954x=y | 137 | CONFIG_I2C_MUX_PCA954x=y |
| 138 | CONFIG_I2C_MUX_PINCTRL=y | 138 | CONFIG_I2C_MUX_PINCTRL=y |
| 139 | CONFIG_I2C_TEGRA=y | 139 | CONFIG_I2C_TEGRA=y |
| 140 | CONFIG_SPI=y | 140 | CONFIG_SPI=y |
| 141 | CONFIG_SPI_TEGRA114=y | 141 | CONFIG_SPI_TEGRA114=y |
| 142 | CONFIG_SPI_TEGRA20_SFLASH=y | 142 | CONFIG_SPI_TEGRA20_SFLASH=y |
| 143 | CONFIG_SPI_TEGRA20_SLINK=y | 143 | CONFIG_SPI_TEGRA20_SLINK=y |
| 144 | CONFIG_PINCTRL_AS3722=y | 144 | CONFIG_PINCTRL_AS3722=y |
| 145 | CONFIG_PINCTRL_PALMAS=y | 145 | CONFIG_PINCTRL_PALMAS=y |
| 146 | CONFIG_GPIO_PCA953X=y | 146 | CONFIG_GPIO_PCA953X=y |
| 147 | CONFIG_GPIO_PCA953X_IRQ=y | 147 | CONFIG_GPIO_PCA953X_IRQ=y |
| 148 | CONFIG_GPIO_PALMAS=y | 148 | CONFIG_GPIO_PALMAS=y |
| 149 | CONFIG_GPIO_TPS6586X=y | 149 | CONFIG_GPIO_TPS6586X=y |
| 150 | CONFIG_GPIO_TPS65910=y | 150 | CONFIG_GPIO_TPS65910=y |
| 151 | CONFIG_POWER_SUPPLY=y | 151 | CONFIG_POWER_SUPPLY=y |
| 152 | CONFIG_BATTERY_SBS=y | 152 | CONFIG_BATTERY_SBS=y |
| 153 | CONFIG_CHARGER_TPS65090=y | 153 | CONFIG_CHARGER_TPS65090=y |
| 154 | CONFIG_POWER_RESET=y | 154 | CONFIG_POWER_RESET=y |
| 155 | CONFIG_POWER_RESET_AS3722=y | 155 | CONFIG_POWER_RESET_AS3722=y |
| 156 | CONFIG_POWER_RESET_GPIO=y | 156 | CONFIG_POWER_RESET_GPIO=y |
| 157 | CONFIG_SENSORS_LM90=y | 157 | CONFIG_SENSORS_LM90=y |
| 158 | CONFIG_SENSORS_LM95245=y | 158 | CONFIG_SENSORS_LM95245=y |
| 159 | CONFIG_MFD_AS3722=y | 159 | CONFIG_MFD_AS3722=y |
| 160 | CONFIG_MFD_CROS_EC=y | 160 | CONFIG_MFD_CROS_EC=y |
| 161 | CONFIG_MFD_CROS_EC_SPI=y | 161 | CONFIG_MFD_CROS_EC_SPI=y |
| 162 | CONFIG_MFD_MAX8907=y | 162 | CONFIG_MFD_MAX8907=y |
| 163 | CONFIG_MFD_STMPE=y | 163 | CONFIG_MFD_STMPE=y |
| 164 | CONFIG_MFD_PALMAS=y | 164 | CONFIG_MFD_PALMAS=y |
| 165 | CONFIG_MFD_TPS65090=y | 165 | CONFIG_MFD_TPS65090=y |
| 166 | CONFIG_MFD_TPS6586X=y | 166 | CONFIG_MFD_TPS6586X=y |
| 167 | CONFIG_MFD_TPS65910=y | 167 | CONFIG_MFD_TPS65910=y |
| 168 | CONFIG_REGULATOR=y | 168 | CONFIG_REGULATOR=y |
| 169 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 169 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 170 | CONFIG_REGULATOR_AS3722=y | 170 | CONFIG_REGULATOR_AS3722=y |
| 171 | CONFIG_REGULATOR_GPIO=y | 171 | CONFIG_REGULATOR_GPIO=y |
| 172 | CONFIG_REGULATOR_MAX8907=y | 172 | CONFIG_REGULATOR_MAX8907=y |
| 173 | CONFIG_REGULATOR_PALMAS=y | 173 | CONFIG_REGULATOR_PALMAS=y |
| 174 | CONFIG_REGULATOR_TPS51632=y | 174 | CONFIG_REGULATOR_TPS51632=y |
| 175 | CONFIG_REGULATOR_TPS62360=y | 175 | CONFIG_REGULATOR_TPS62360=y |
| 176 | CONFIG_REGULATOR_TPS65090=y | 176 | CONFIG_REGULATOR_TPS65090=y |
| 177 | CONFIG_REGULATOR_TPS6586X=y | 177 | CONFIG_REGULATOR_TPS6586X=y |
| 178 | CONFIG_REGULATOR_TPS65910=y | 178 | CONFIG_REGULATOR_TPS65910=y |
| 179 | CONFIG_MEDIA_SUPPORT=y | 179 | CONFIG_MEDIA_SUPPORT=y |
| 180 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 180 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 181 | CONFIG_MEDIA_USB_SUPPORT=y | 181 | CONFIG_MEDIA_USB_SUPPORT=y |
| 182 | CONFIG_USB_VIDEO_CLASS=y | 182 | CONFIG_USB_VIDEO_CLASS=y |
| 183 | CONFIG_USB_GSPCA=y | 183 | CONFIG_USB_GSPCA=y |
| 184 | CONFIG_DRM=y | 184 | CONFIG_DRM=y |
| 185 | CONFIG_DRM_TEGRA=y | 185 | CONFIG_DRM_TEGRA=y |
| 186 | CONFIG_DRM_PANEL_SIMPLE=y | 186 | CONFIG_DRM_PANEL_SIMPLE=y |
| 187 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 187 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 188 | # CONFIG_LCD_CLASS_DEVICE is not set | 188 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 189 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 189 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 190 | # CONFIG_BACKLIGHT_GENERIC is not set | 190 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 191 | CONFIG_BACKLIGHT_PWM=y | 191 | CONFIG_BACKLIGHT_PWM=y |
| 192 | CONFIG_FRAMEBUFFER_CONSOLE=y | 192 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 193 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | 193 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y |
| 194 | CONFIG_LOGO=y | 194 | CONFIG_LOGO=y |
| 195 | CONFIG_SOUND=y | 195 | CONFIG_SOUND=y |
| 196 | CONFIG_SND=y | 196 | CONFIG_SND=y |
| 197 | # CONFIG_SND_SUPPORT_OLD_API is not set | 197 | # CONFIG_SND_SUPPORT_OLD_API is not set |
| 198 | # CONFIG_SND_DRIVERS is not set | 198 | # CONFIG_SND_DRIVERS is not set |
| 199 | # CONFIG_SND_ARM is not set | 199 | # CONFIG_SND_ARM is not set |
| 200 | # CONFIG_SND_SPI is not set | 200 | # CONFIG_SND_SPI is not set |
| 201 | # CONFIG_SND_USB is not set | 201 | # CONFIG_SND_USB is not set |
| 202 | CONFIG_SND_SOC=y | 202 | CONFIG_SND_SOC=y |
| 203 | CONFIG_SND_SOC_TEGRA=y | 203 | CONFIG_SND_SOC_TEGRA=y |
| 204 | CONFIG_SND_SOC_TEGRA_RT5640=y | 204 | CONFIG_SND_SOC_TEGRA_RT5640=y |
| 205 | CONFIG_SND_SOC_TEGRA_WM8753=y | 205 | CONFIG_SND_SOC_TEGRA_WM8753=y |
| 206 | CONFIG_SND_SOC_TEGRA_WM8903=y | 206 | CONFIG_SND_SOC_TEGRA_WM8903=y |
| 207 | CONFIG_SND_SOC_TEGRA_TRIMSLICE=y | 207 | CONFIG_SND_SOC_TEGRA_TRIMSLICE=y |
| 208 | CONFIG_SND_SOC_TEGRA_ALC5632=y | 208 | CONFIG_SND_SOC_TEGRA_ALC5632=y |
| 209 | CONFIG_SND_SOC_TEGRA_MAX98090=y | 209 | CONFIG_SND_SOC_TEGRA_MAX98090=y |
| 210 | CONFIG_USB=y | 210 | CONFIG_USB=y |
| 211 | CONFIG_USB_XHCI_HCD=y | 211 | CONFIG_USB_XHCI_HCD=y |
| 212 | CONFIG_USB_EHCI_HCD=y | 212 | CONFIG_USB_EHCI_HCD=y |
| 213 | CONFIG_USB_EHCI_TEGRA=y | 213 | CONFIG_USB_EHCI_TEGRA=y |
| 214 | CONFIG_USB_ACM=y | 214 | CONFIG_USB_ACM=y |
| 215 | CONFIG_USB_WDM=y | 215 | CONFIG_USB_WDM=y |
| 216 | CONFIG_USB_STORAGE=y | 216 | CONFIG_USB_STORAGE=y |
| 217 | CONFIG_MMC=y | 217 | CONFIG_MMC=y |
| 218 | CONFIG_MMC_BLOCK_MINORS=16 | 218 | CONFIG_MMC_BLOCK_MINORS=16 |
| 219 | CONFIG_MMC_SDHCI=y | 219 | CONFIG_MMC_SDHCI=y |
| 220 | CONFIG_MMC_SDHCI_PLTFM=y | 220 | CONFIG_MMC_SDHCI_PLTFM=y |
| 221 | CONFIG_MMC_SDHCI_TEGRA=y | 221 | CONFIG_MMC_SDHCI_TEGRA=y |
| 222 | CONFIG_NEW_LEDS=y | 222 | CONFIG_NEW_LEDS=y |
| 223 | CONFIG_LEDS_CLASS=y | 223 | CONFIG_LEDS_CLASS=y |
| 224 | CONFIG_LEDS_GPIO=y | 224 | CONFIG_LEDS_GPIO=y |
| 225 | CONFIG_LEDS_PWM=y | 225 | CONFIG_LEDS_PWM=y |
| 226 | CONFIG_LEDS_TRIGGERS=y | 226 | CONFIG_LEDS_TRIGGERS=y |
| 227 | CONFIG_LEDS_TRIGGER_TIMER=y | 227 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 228 | CONFIG_LEDS_TRIGGER_ONESHOT=y | 228 | CONFIG_LEDS_TRIGGER_ONESHOT=y |
| 229 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 229 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 230 | CONFIG_LEDS_TRIGGER_GPIO=y | 230 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 231 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | 231 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y |
| 232 | CONFIG_LEDS_TRIGGER_TRANSIENT=y | 232 | CONFIG_LEDS_TRIGGER_TRANSIENT=y |
| 233 | CONFIG_LEDS_TRIGGER_CAMERA=y | 233 | CONFIG_LEDS_TRIGGER_CAMERA=y |
| 234 | CONFIG_RTC_CLASS=y | 234 | CONFIG_RTC_CLASS=y |
| 235 | CONFIG_RTC_DRV_AS3722=y | 235 | CONFIG_RTC_DRV_AS3722=y |
| 236 | CONFIG_RTC_DRV_DS1307=y | 236 | CONFIG_RTC_DRV_DS1307=y |
| 237 | CONFIG_RTC_DRV_MAX8907=y | 237 | CONFIG_RTC_DRV_MAX8907=y |
| 238 | CONFIG_RTC_DRV_PALMAS=y | 238 | CONFIG_RTC_DRV_PALMAS=y |
| 239 | CONFIG_RTC_DRV_TPS6586X=y | 239 | CONFIG_RTC_DRV_TPS6586X=y |
| 240 | CONFIG_RTC_DRV_TPS65910=y | 240 | CONFIG_RTC_DRV_TPS65910=y |
| 241 | CONFIG_RTC_DRV_EM3027=y | 241 | CONFIG_RTC_DRV_EM3027=y |
| 242 | CONFIG_RTC_DRV_TEGRA=y | 242 | CONFIG_RTC_DRV_TEGRA=y |
| 243 | CONFIG_DMADEVICES=y | 243 | CONFIG_DMADEVICES=y |
| 244 | CONFIG_TEGRA20_APB_DMA=y | 244 | CONFIG_TEGRA20_APB_DMA=y |
| 245 | CONFIG_STAGING=y | 245 | CONFIG_STAGING=y |
| 246 | CONFIG_SENSORS_ISL29018=y | 246 | CONFIG_SENSORS_ISL29018=y |
| 247 | CONFIG_SENSORS_ISL29028=y | 247 | CONFIG_SENSORS_ISL29028=y |
| 248 | CONFIG_MFD_NVEC=y | 248 | CONFIG_MFD_NVEC=y |
| 249 | CONFIG_KEYBOARD_NVEC=y | 249 | CONFIG_KEYBOARD_NVEC=y |
| 250 | CONFIG_SERIO_NVEC_PS2=y | 250 | CONFIG_SERIO_NVEC_PS2=y |
| 251 | CONFIG_NVEC_POWER=y | 251 | CONFIG_NVEC_POWER=y |
| 252 | CONFIG_NVEC_PAZ00=y | 252 | CONFIG_NVEC_PAZ00=y |
| 253 | CONFIG_TEGRA_IOMMU_GART=y | 253 | CONFIG_TEGRA_IOMMU_GART=y |
| 254 | CONFIG_TEGRA_IOMMU_SMMU=y | 254 | CONFIG_TEGRA_IOMMU_SMMU=y |
| 255 | CONFIG_MEMORY=y | 255 | CONFIG_MEMORY=y |
| 256 | CONFIG_IIO=y | 256 | CONFIG_IIO=y |
| 257 | CONFIG_AK8975=y | 257 | CONFIG_AK8975=y |
| 258 | CONFIG_PWM=y | 258 | CONFIG_PWM=y |
| 259 | CONFIG_PWM_TEGRA=y | 259 | CONFIG_PWM_TEGRA=y |
| 260 | CONFIG_EXT2_FS=y | 260 | CONFIG_EXT2_FS=y |
| 261 | CONFIG_EXT2_FS_XATTR=y | 261 | CONFIG_EXT2_FS_XATTR=y |
| 262 | CONFIG_EXT2_FS_POSIX_ACL=y | 262 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 263 | CONFIG_EXT2_FS_SECURITY=y | 263 | CONFIG_EXT2_FS_SECURITY=y |
| 264 | CONFIG_EXT3_FS=y | 264 | CONFIG_EXT3_FS=y |
| 265 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 265 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 266 | CONFIG_EXT3_FS_POSIX_ACL=y | 266 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 267 | CONFIG_EXT3_FS_SECURITY=y | 267 | CONFIG_EXT3_FS_SECURITY=y |
| 268 | CONFIG_EXT4_FS=y | 268 | CONFIG_EXT4_FS=y |
| 269 | # CONFIG_DNOTIFY is not set | 269 | # CONFIG_DNOTIFY is not set |
| 270 | CONFIG_VFAT_FS=y | 270 | CONFIG_VFAT_FS=y |
| 271 | CONFIG_TMPFS=y | 271 | CONFIG_TMPFS=y |
| 272 | CONFIG_TMPFS_POSIX_ACL=y | 272 | CONFIG_TMPFS_POSIX_ACL=y |
| 273 | CONFIG_SQUASHFS=y | 273 | CONFIG_SQUASHFS=y |
| 274 | CONFIG_SQUASHFS_LZO=y | 274 | CONFIG_SQUASHFS_LZO=y |
| 275 | CONFIG_SQUASHFS_XZ=y | 275 | CONFIG_SQUASHFS_XZ=y |
| 276 | CONFIG_NFS_FS=y | 276 | CONFIG_NFS_FS=y |
| 277 | CONFIG_ROOT_NFS=y | 277 | CONFIG_ROOT_NFS=y |
| 278 | CONFIG_NLS_CODEPAGE_437=y | 278 | CONFIG_NLS_CODEPAGE_437=y |
| 279 | CONFIG_NLS_ISO8859_1=y | 279 | CONFIG_NLS_ISO8859_1=y |
| 280 | CONFIG_PRINTK_TIME=y | 280 | CONFIG_PRINTK_TIME=y |
| 281 | CONFIG_DEBUG_INFO=y | 281 | CONFIG_DEBUG_INFO=y |
| 282 | CONFIG_DEBUG_FS=y | 282 | CONFIG_DEBUG_FS=y |
| 283 | CONFIG_MAGIC_SYSRQ=y | 283 | CONFIG_MAGIC_SYSRQ=y |
| 284 | CONFIG_DEBUG_SLAB=y | 284 | CONFIG_DEBUG_SLAB=y |
| 285 | CONFIG_DEBUG_VM=y | 285 | CONFIG_DEBUG_VM=y |
| 286 | CONFIG_DETECT_HUNG_TASK=y | 286 | CONFIG_DETECT_HUNG_TASK=y |
| 287 | CONFIG_SCHEDSTATS=y | 287 | CONFIG_SCHEDSTATS=y |
| 288 | CONFIG_TIMER_STATS=y | 288 | CONFIG_TIMER_STATS=y |
| 289 | # CONFIG_DEBUG_PREEMPT is not set | 289 | # CONFIG_DEBUG_PREEMPT is not set |
| 290 | CONFIG_DEBUG_MUTEXES=y | 290 | CONFIG_DEBUG_MUTEXES=y |
| 291 | CONFIG_DEBUG_SG=y | 291 | CONFIG_DEBUG_SG=y |
| 292 | CONFIG_DEBUG_LL=y | 292 | CONFIG_DEBUG_LL=y |
| 293 | CONFIG_EARLY_PRINTK=y | 293 | CONFIG_EARLY_PRINTK=y |
| 294 | CONFIG_CRYPTO_TWOFISH=y | 294 | CONFIG_CRYPTO_TWOFISH=y |
| 295 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 295 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 296 | CONFIG_CRC_CCITT=y | 296 | CONFIG_CRC_CCITT=y |
| 297 | 297 |
arch/arm/configs/u8500_defconfig
| 1 | # CONFIG_SWAP is not set | 1 | # CONFIG_SWAP is not set |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_NO_HZ_IDLE=y | 3 | CONFIG_NO_HZ_IDLE=y |
| 4 | CONFIG_HIGH_RES_TIMERS=y | 4 | CONFIG_HIGH_RES_TIMERS=y |
| 5 | CONFIG_BLK_DEV_INITRD=y | 5 | CONFIG_BLK_DEV_INITRD=y |
| 6 | CONFIG_KALLSYMS_ALL=y | 6 | CONFIG_KALLSYMS_ALL=y |
| 7 | CONFIG_MODULES=y | 7 | CONFIG_MODULES=y |
| 8 | CONFIG_MODULE_UNLOAD=y | 8 | CONFIG_MODULE_UNLOAD=y |
| 9 | # CONFIG_BLK_DEV_BSG is not set | 9 | # CONFIG_BLK_DEV_BSG is not set |
| 10 | CONFIG_PARTITION_ADVANCED=y | 10 | CONFIG_PARTITION_ADVANCED=y |
| 11 | CONFIG_ARCH_U8500=y | 11 | CONFIG_ARCH_U8500=y |
| 12 | CONFIG_MACH_HREFV60=y | 12 | CONFIG_MACH_HREFV60=y |
| 13 | CONFIG_MACH_SNOWBALL=y | 13 | CONFIG_MACH_SNOWBALL=y |
| 14 | CONFIG_SMP=y | 14 | CONFIG_SMP=y |
| 15 | CONFIG_NR_CPUS=2 | 15 | CONFIG_NR_CPUS=2 |
| 16 | CONFIG_PREEMPT=y | 16 | CONFIG_PREEMPT=y |
| 17 | CONFIG_AEABI=y | 17 | CONFIG_AEABI=y |
| 18 | CONFIG_HIGHMEM=y | 18 | CONFIG_HIGHMEM=y |
| 19 | CONFIG_ARM_APPENDED_DTB=y | 19 | CONFIG_ARM_APPENDED_DTB=y |
| 20 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 20 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 21 | CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" | 21 | CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" |
| 22 | CONFIG_CPU_FREQ=y | 22 | CONFIG_CPU_FREQ=y |
| 23 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | 23 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y |
| 24 | CONFIG_CPU_IDLE=y | 24 | CONFIG_CPU_IDLE=y |
| 25 | CONFIG_ARM_U8500_CPUIDLE=y | 25 | CONFIG_ARM_U8500_CPUIDLE=y |
| 26 | CONFIG_VFP=y | 26 | CONFIG_VFP=y |
| 27 | CONFIG_NEON=y | 27 | CONFIG_NEON=y |
| 28 | CONFIG_PM_RUNTIME=y | 28 | CONFIG_PM=y |
| 29 | CONFIG_NET=y | 29 | CONFIG_NET=y |
| 30 | CONFIG_PACKET=y | 30 | CONFIG_PACKET=y |
| 31 | CONFIG_UNIX=y | 31 | CONFIG_UNIX=y |
| 32 | CONFIG_INET=y | 32 | CONFIG_INET=y |
| 33 | CONFIG_IP_PNP=y | 33 | CONFIG_IP_PNP=y |
| 34 | CONFIG_IP_PNP_DHCP=y | 34 | CONFIG_IP_PNP_DHCP=y |
| 35 | CONFIG_NETFILTER=y | 35 | CONFIG_NETFILTER=y |
| 36 | CONFIG_PHONET=y | 36 | CONFIG_PHONET=y |
| 37 | CONFIG_CFG80211=y | 37 | CONFIG_CFG80211=y |
| 38 | CONFIG_CFG80211_DEBUGFS=y | 38 | CONFIG_CFG80211_DEBUGFS=y |
| 39 | CONFIG_MAC80211=y | 39 | CONFIG_MAC80211=y |
| 40 | CONFIG_MAC80211_LEDS=y | 40 | CONFIG_MAC80211_LEDS=y |
| 41 | CONFIG_CAIF=y | 41 | CONFIG_CAIF=y |
| 42 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 42 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 43 | CONFIG_DEVTMPFS=y | 43 | CONFIG_DEVTMPFS=y |
| 44 | CONFIG_DEVTMPFS_MOUNT=y | 44 | CONFIG_DEVTMPFS_MOUNT=y |
| 45 | CONFIG_BLK_DEV_RAM=y | 45 | CONFIG_BLK_DEV_RAM=y |
| 46 | CONFIG_BLK_DEV_RAM_SIZE=65536 | 46 | CONFIG_BLK_DEV_RAM_SIZE=65536 |
| 47 | CONFIG_SENSORS_BH1780=y | 47 | CONFIG_SENSORS_BH1780=y |
| 48 | CONFIG_NETDEVICES=y | 48 | CONFIG_NETDEVICES=y |
| 49 | CONFIG_SMSC911X=y | 49 | CONFIG_SMSC911X=y |
| 50 | CONFIG_SMSC_PHY=y | 50 | CONFIG_SMSC_PHY=y |
| 51 | CONFIG_CW1200=y | 51 | CONFIG_CW1200=y |
| 52 | CONFIG_CW1200_WLAN_SDIO=y | 52 | CONFIG_CW1200_WLAN_SDIO=y |
| 53 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 53 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 54 | CONFIG_INPUT_EVDEV=y | 54 | CONFIG_INPUT_EVDEV=y |
| 55 | # CONFIG_KEYBOARD_ATKBD is not set | 55 | # CONFIG_KEYBOARD_ATKBD is not set |
| 56 | CONFIG_KEYBOARD_GPIO=y | 56 | CONFIG_KEYBOARD_GPIO=y |
| 57 | CONFIG_KEYBOARD_NOMADIK=y | 57 | CONFIG_KEYBOARD_NOMADIK=y |
| 58 | CONFIG_KEYBOARD_STMPE=y | 58 | CONFIG_KEYBOARD_STMPE=y |
| 59 | CONFIG_KEYBOARD_TC3589X=y | 59 | CONFIG_KEYBOARD_TC3589X=y |
| 60 | # CONFIG_INPUT_MOUSE is not set | 60 | # CONFIG_INPUT_MOUSE is not set |
| 61 | CONFIG_INPUT_TOUCHSCREEN=y | 61 | CONFIG_INPUT_TOUCHSCREEN=y |
| 62 | CONFIG_TOUCHSCREEN_BU21013=y | 62 | CONFIG_TOUCHSCREEN_BU21013=y |
| 63 | CONFIG_INPUT_MISC=y | 63 | CONFIG_INPUT_MISC=y |
| 64 | CONFIG_INPUT_AB8500_PONKEY=y | 64 | CONFIG_INPUT_AB8500_PONKEY=y |
| 65 | # CONFIG_SERIO is not set | 65 | # CONFIG_SERIO is not set |
| 66 | CONFIG_VT_HW_CONSOLE_BINDING=y | 66 | CONFIG_VT_HW_CONSOLE_BINDING=y |
| 67 | # CONFIG_LEGACY_PTYS is not set | 67 | # CONFIG_LEGACY_PTYS is not set |
| 68 | CONFIG_SERIAL_AMBA_PL011=y | 68 | CONFIG_SERIAL_AMBA_PL011=y |
| 69 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 69 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
| 70 | CONFIG_HW_RANDOM=y | 70 | CONFIG_HW_RANDOM=y |
| 71 | CONFIG_SPI=y | 71 | CONFIG_SPI=y |
| 72 | CONFIG_SPI_PL022=y | 72 | CONFIG_SPI_PL022=y |
| 73 | CONFIG_GPIO_STMPE=y | 73 | CONFIG_GPIO_STMPE=y |
| 74 | CONFIG_GPIO_TC3589X=y | 74 | CONFIG_GPIO_TC3589X=y |
| 75 | CONFIG_THERMAL=y | 75 | CONFIG_THERMAL=y |
| 76 | CONFIG_CPU_THERMAL=y | 76 | CONFIG_CPU_THERMAL=y |
| 77 | CONFIG_WATCHDOG=y | 77 | CONFIG_WATCHDOG=y |
| 78 | CONFIG_MFD_STMPE=y | 78 | CONFIG_MFD_STMPE=y |
| 79 | CONFIG_MFD_TC3589X=y | 79 | CONFIG_MFD_TC3589X=y |
| 80 | CONFIG_REGULATOR_AB8500=y | 80 | CONFIG_REGULATOR_AB8500=y |
| 81 | CONFIG_REGULATOR_GPIO=y | 81 | CONFIG_REGULATOR_GPIO=y |
| 82 | CONFIG_SOUND=y | 82 | CONFIG_SOUND=y |
| 83 | CONFIG_SND=y | 83 | CONFIG_SND=y |
| 84 | CONFIG_SND_SOC=y | 84 | CONFIG_SND_SOC=y |
| 85 | CONFIG_SND_SOC_UX500=y | 85 | CONFIG_SND_SOC_UX500=y |
| 86 | CONFIG_SND_SOC_UX500_MACH_MOP500=y | 86 | CONFIG_SND_SOC_UX500_MACH_MOP500=y |
| 87 | CONFIG_USB=y | 87 | CONFIG_USB=y |
| 88 | CONFIG_USB_MUSB_HDRC=y | 88 | CONFIG_USB_MUSB_HDRC=y |
| 89 | CONFIG_USB_MUSB_UX500=y | 89 | CONFIG_USB_MUSB_UX500=y |
| 90 | CONFIG_AB8500_USB=y | 90 | CONFIG_AB8500_USB=y |
| 91 | CONFIG_USB_GADGET=y | 91 | CONFIG_USB_GADGET=y |
| 92 | CONFIG_USB_ETH=m | 92 | CONFIG_USB_ETH=m |
| 93 | CONFIG_MMC=y | 93 | CONFIG_MMC=y |
| 94 | CONFIG_MMC_ARMMMCI=y | 94 | CONFIG_MMC_ARMMMCI=y |
| 95 | CONFIG_NEW_LEDS=y | 95 | CONFIG_NEW_LEDS=y |
| 96 | CONFIG_LEDS_CLASS=y | 96 | CONFIG_LEDS_CLASS=y |
| 97 | CONFIG_LEDS_LM3530=y | 97 | CONFIG_LEDS_LM3530=y |
| 98 | CONFIG_LEDS_GPIO=y | 98 | CONFIG_LEDS_GPIO=y |
| 99 | CONFIG_LEDS_LP5521=y | 99 | CONFIG_LEDS_LP5521=y |
| 100 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 100 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 101 | CONFIG_RTC_CLASS=y | 101 | CONFIG_RTC_CLASS=y |
| 102 | CONFIG_RTC_DRV_AB8500=y | 102 | CONFIG_RTC_DRV_AB8500=y |
| 103 | CONFIG_RTC_DRV_PL031=y | 103 | CONFIG_RTC_DRV_PL031=y |
| 104 | CONFIG_DMADEVICES=y | 104 | CONFIG_DMADEVICES=y |
| 105 | CONFIG_STE_DMA40=y | 105 | CONFIG_STE_DMA40=y |
| 106 | CONFIG_STAGING=y | 106 | CONFIG_STAGING=y |
| 107 | CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y | 107 | CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y |
| 108 | CONFIG_HSEM_U8500=y | 108 | CONFIG_HSEM_U8500=y |
| 109 | CONFIG_IIO=y | 109 | CONFIG_IIO=y |
| 110 | CONFIG_IIO_ST_ACCEL_3AXIS=y | 110 | CONFIG_IIO_ST_ACCEL_3AXIS=y |
| 111 | CONFIG_IIO_ST_GYRO_3AXIS=y | 111 | CONFIG_IIO_ST_GYRO_3AXIS=y |
| 112 | CONFIG_IIO_ST_MAGN_3AXIS=y | 112 | CONFIG_IIO_ST_MAGN_3AXIS=y |
| 113 | CONFIG_IIO_ST_PRESS=y | 113 | CONFIG_IIO_ST_PRESS=y |
| 114 | CONFIG_EXT2_FS=y | 114 | CONFIG_EXT2_FS=y |
| 115 | CONFIG_EXT2_FS_XATTR=y | 115 | CONFIG_EXT2_FS_XATTR=y |
| 116 | CONFIG_EXT2_FS_POSIX_ACL=y | 116 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 117 | CONFIG_EXT2_FS_SECURITY=y | 117 | CONFIG_EXT2_FS_SECURITY=y |
| 118 | CONFIG_EXT3_FS=y | 118 | CONFIG_EXT3_FS=y |
| 119 | CONFIG_EXT4_FS=y | 119 | CONFIG_EXT4_FS=y |
| 120 | CONFIG_VFAT_FS=y | 120 | CONFIG_VFAT_FS=y |
| 121 | CONFIG_TMPFS=y | 121 | CONFIG_TMPFS=y |
| 122 | CONFIG_TMPFS_POSIX_ACL=y | 122 | CONFIG_TMPFS_POSIX_ACL=y |
| 123 | # CONFIG_MISC_FILESYSTEMS is not set | 123 | # CONFIG_MISC_FILESYSTEMS is not set |
| 124 | CONFIG_NFS_FS=y | 124 | CONFIG_NFS_FS=y |
| 125 | CONFIG_ROOT_NFS=y | 125 | CONFIG_ROOT_NFS=y |
| 126 | CONFIG_NLS_CODEPAGE_437=y | 126 | CONFIG_NLS_CODEPAGE_437=y |
| 127 | CONFIG_NLS_ISO8859_1=y | 127 | CONFIG_NLS_ISO8859_1=y |
| 128 | CONFIG_PRINTK_TIME=y | 128 | CONFIG_PRINTK_TIME=y |
| 129 | CONFIG_DEBUG_INFO=y | 129 | CONFIG_DEBUG_INFO=y |
| 130 | CONFIG_DEBUG_FS=y | 130 | CONFIG_DEBUG_FS=y |
| 131 | CONFIG_MAGIC_SYSRQ=y | 131 | CONFIG_MAGIC_SYSRQ=y |
| 132 | CONFIG_DEBUG_KERNEL=y | 132 | CONFIG_DEBUG_KERNEL=y |
| 133 | # CONFIG_SCHED_DEBUG is not set | 133 | # CONFIG_SCHED_DEBUG is not set |
| 134 | # CONFIG_DEBUG_PREEMPT is not set | 134 | # CONFIG_DEBUG_PREEMPT is not set |
| 135 | # CONFIG_FTRACE is not set | 135 | # CONFIG_FTRACE is not set |
| 136 | CONFIG_DEBUG_USER=y | 136 | CONFIG_DEBUG_USER=y |
| 137 | CONFIG_CRYPTO_DEV_UX500=y | 137 | CONFIG_CRYPTO_DEV_UX500=y |
| 138 | CONFIG_CRYPTO_DEV_UX500_CRYP=y | 138 | CONFIG_CRYPTO_DEV_UX500_CRYP=y |
| 139 | CONFIG_CRYPTO_DEV_UX500_HASH=y | 139 | CONFIG_CRYPTO_DEV_UX500_HASH=y |
| 140 | CONFIG_CRYPTO_DEV_UX500_DEBUG=y | 140 | CONFIG_CRYPTO_DEV_UX500_DEBUG=y |
| 141 | 141 |
arch/arm/configs/vt8500_v6_v7_defconfig
| 1 | CONFIG_IRQ_DOMAIN_DEBUG=y | 1 | CONFIG_IRQ_DOMAIN_DEBUG=y |
| 2 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_BLK_DEV_INITRD=y | 4 | CONFIG_BLK_DEV_INITRD=y |
| 5 | CONFIG_ARCH_MULTI_V6=y | 5 | CONFIG_ARCH_MULTI_V6=y |
| 6 | CONFIG_ARCH_WM8750=y | 6 | CONFIG_ARCH_WM8750=y |
| 7 | CONFIG_ARCH_WM8850=y | 7 | CONFIG_ARCH_WM8850=y |
| 8 | CONFIG_ARM_ERRATA_720789=y | 8 | CONFIG_ARM_ERRATA_720789=y |
| 9 | CONFIG_ARM_ERRATA_754322=y | 9 | CONFIG_ARM_ERRATA_754322=y |
| 10 | CONFIG_ARM_ERRATA_775420=y | 10 | CONFIG_ARM_ERRATA_775420=y |
| 11 | CONFIG_HAVE_ARM_ARCH_TIMER=y | 11 | CONFIG_HAVE_ARM_ARCH_TIMER=y |
| 12 | CONFIG_AEABI=y | 12 | CONFIG_AEABI=y |
| 13 | CONFIG_HIGHMEM=y | 13 | CONFIG_HIGHMEM=y |
| 14 | CONFIG_HIGHPTE=y | 14 | CONFIG_HIGHPTE=y |
| 15 | CONFIG_ARM_APPENDED_DTB=y | 15 | CONFIG_ARM_APPENDED_DTB=y |
| 16 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 16 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| 17 | CONFIG_VFP=y | 17 | CONFIG_VFP=y |
| 18 | CONFIG_NEON=y | 18 | CONFIG_NEON=y |
| 19 | CONFIG_PM_RUNTIME=y | 19 | CONFIG_PM=y |
| 20 | CONFIG_NET=y | 20 | CONFIG_NET=y |
| 21 | CONFIG_UNIX=y | 21 | CONFIG_UNIX=y |
| 22 | CONFIG_INET=y | 22 | CONFIG_INET=y |
| 23 | CONFIG_IP_PNP=y | 23 | CONFIG_IP_PNP=y |
| 24 | CONFIG_IP_PNP_DHCP=y | 24 | CONFIG_IP_PNP_DHCP=y |
| 25 | CONFIG_DEVTMPFS=y | 25 | CONFIG_DEVTMPFS=y |
| 26 | CONFIG_DEVTMPFS_MOUNT=y | 26 | CONFIG_DEVTMPFS_MOUNT=y |
| 27 | CONFIG_PROC_DEVICETREE=y | 27 | CONFIG_PROC_DEVICETREE=y |
| 28 | CONFIG_EEPROM_93CX6=y | 28 | CONFIG_EEPROM_93CX6=y |
| 29 | CONFIG_SCSI=y | 29 | CONFIG_SCSI=y |
| 30 | CONFIG_BLK_DEV_SD=y | 30 | CONFIG_BLK_DEV_SD=y |
| 31 | CONFIG_NETDEVICES=y | 31 | CONFIG_NETDEVICES=y |
| 32 | # CONFIG_NET_CADENCE is not set | 32 | # CONFIG_NET_CADENCE is not set |
| 33 | # CONFIG_NET_VENDOR_BROADCOM is not set | 33 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 34 | # CONFIG_NET_VENDOR_CIRRUS is not set | 34 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 35 | # CONFIG_NET_VENDOR_FARADAY is not set | 35 | # CONFIG_NET_VENDOR_FARADAY is not set |
| 36 | # CONFIG_NET_VENDOR_INTEL is not set | 36 | # CONFIG_NET_VENDOR_INTEL is not set |
| 37 | # CONFIG_NET_VENDOR_MARVELL is not set | 37 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 38 | # CONFIG_NET_VENDOR_MICREL is not set | 38 | # CONFIG_NET_VENDOR_MICREL is not set |
| 39 | # CONFIG_NET_VENDOR_NATSEMI is not set | 39 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 40 | # CONFIG_NET_VENDOR_SEEQ is not set | 40 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 41 | # CONFIG_NET_VENDOR_SMSC is not set | 41 | # CONFIG_NET_VENDOR_SMSC is not set |
| 42 | # CONFIG_NET_VENDOR_STMICRO is not set | 42 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 43 | CONFIG_VIA_VELOCITY=y | 43 | CONFIG_VIA_VELOCITY=y |
| 44 | # CONFIG_NET_VENDOR_WIZNET is not set | 44 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 45 | CONFIG_PHYLIB=y | 45 | CONFIG_PHYLIB=y |
| 46 | CONFIG_INPUT_MATRIXKMAP=y | 46 | CONFIG_INPUT_MATRIXKMAP=y |
| 47 | CONFIG_SERIAL_VT8500=y | 47 | CONFIG_SERIAL_VT8500=y |
| 48 | CONFIG_SERIAL_VT8500_CONSOLE=y | 48 | CONFIG_SERIAL_VT8500_CONSOLE=y |
| 49 | CONFIG_I2C=y | 49 | CONFIG_I2C=y |
| 50 | CONFIG_I2C_WMT=y | 50 | CONFIG_I2C_WMT=y |
| 51 | CONFIG_PINCTRL_SINGLE=y | 51 | CONFIG_PINCTRL_SINGLE=y |
| 52 | CONFIG_PINCTRL_WM8750=y | 52 | CONFIG_PINCTRL_WM8750=y |
| 53 | CONFIG_GPIO_GENERIC_PLATFORM=y | 53 | CONFIG_GPIO_GENERIC_PLATFORM=y |
| 54 | CONFIG_POWER_SUPPLY=y | 54 | CONFIG_POWER_SUPPLY=y |
| 55 | CONFIG_POWER_RESET=y | 55 | CONFIG_POWER_RESET=y |
| 56 | CONFIG_MFD_SYSCON=y | 56 | CONFIG_MFD_SYSCON=y |
| 57 | CONFIG_REGULATOR=y | 57 | CONFIG_REGULATOR=y |
| 58 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 58 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 59 | CONFIG_REGULATOR_GPIO=y | 59 | CONFIG_REGULATOR_GPIO=y |
| 60 | CONFIG_USB=y | 60 | CONFIG_USB=y |
| 61 | CONFIG_USB_EHCI_HCD=y | 61 | CONFIG_USB_EHCI_HCD=y |
| 62 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 62 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 63 | CONFIG_USB_UHCI_HCD=y | 63 | CONFIG_USB_UHCI_HCD=y |
| 64 | CONFIG_USB_STORAGE=y | 64 | CONFIG_USB_STORAGE=y |
| 65 | CONFIG_NOP_USB_XCEIV=y | 65 | CONFIG_NOP_USB_XCEIV=y |
| 66 | CONFIG_USB_GPIO_VBUS=y | 66 | CONFIG_USB_GPIO_VBUS=y |
| 67 | CONFIG_USB_ULPI=y | 67 | CONFIG_USB_ULPI=y |
| 68 | CONFIG_MMC=y | 68 | CONFIG_MMC=y |
| 69 | CONFIG_MMC_DEBUG=y | 69 | CONFIG_MMC_DEBUG=y |
| 70 | CONFIG_NEW_LEDS=y | 70 | CONFIG_NEW_LEDS=y |
| 71 | CONFIG_LEDS_CLASS=y | 71 | CONFIG_LEDS_CLASS=y |
| 72 | CONFIG_LEDS_TRIGGERS=y | 72 | CONFIG_LEDS_TRIGGERS=y |
| 73 | CONFIG_RTC_CLASS=y | 73 | CONFIG_RTC_CLASS=y |
| 74 | CONFIG_RTC_DRV_VT8500=y | 74 | CONFIG_RTC_DRV_VT8500=y |
| 75 | CONFIG_DMADEVICES=y | 75 | CONFIG_DMADEVICES=y |
| 76 | # CONFIG_IOMMU_SUPPORT is not set | 76 | # CONFIG_IOMMU_SUPPORT is not set |
| 77 | CONFIG_PWM=y | 77 | CONFIG_PWM=y |
| 78 | CONFIG_PWM_VT8500=y | 78 | CONFIG_PWM_VT8500=y |
| 79 | CONFIG_RESET_CONTROLLER=y | 79 | CONFIG_RESET_CONTROLLER=y |
| 80 | CONFIG_GENERIC_PHY=y | 80 | CONFIG_GENERIC_PHY=y |
| 81 | CONFIG_EXT4_FS=y | 81 | CONFIG_EXT4_FS=y |
| 82 | CONFIG_TMPFS=y | 82 | CONFIG_TMPFS=y |
| 83 | CONFIG_NFS_FS=y | 83 | CONFIG_NFS_FS=y |
| 84 | CONFIG_NFS_V3_ACL=y | 84 | CONFIG_NFS_V3_ACL=y |
| 85 | CONFIG_NFS_V4=y | 85 | CONFIG_NFS_V4=y |
| 86 | CONFIG_ROOT_NFS=y | 86 | CONFIG_ROOT_NFS=y |
| 87 | CONFIG_PRINTK_TIME=y | 87 | CONFIG_PRINTK_TIME=y |
| 88 | CONFIG_DEBUG_KERNEL=y | 88 | CONFIG_DEBUG_KERNEL=y |
| 89 | CONFIG_LOCKUP_DETECTOR=y | 89 | CONFIG_LOCKUP_DETECTOR=y |
| 90 | 90 |
arch/arm/mach-omap2/Kconfig
| 1 | menu "TI OMAP/AM/DM/DRA Family" | 1 | menu "TI OMAP/AM/DM/DRA Family" |
| 2 | depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 | 2 | depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 |
| 3 | 3 | ||
| 4 | config ARCH_OMAP2 | 4 | config ARCH_OMAP2 |
| 5 | bool "TI OMAP2" | 5 | bool "TI OMAP2" |
| 6 | depends on ARCH_MULTI_V6 | 6 | depends on ARCH_MULTI_V6 |
| 7 | select ARCH_OMAP2PLUS | 7 | select ARCH_OMAP2PLUS |
| 8 | select CPU_V6 | 8 | select CPU_V6 |
| 9 | select SOC_HAS_OMAP2_SDRC | 9 | select SOC_HAS_OMAP2_SDRC |
| 10 | 10 | ||
| 11 | config ARCH_OMAP3 | 11 | config ARCH_OMAP3 |
| 12 | bool "TI OMAP3" | 12 | bool "TI OMAP3" |
| 13 | depends on ARCH_MULTI_V7 | 13 | depends on ARCH_MULTI_V7 |
| 14 | select ARCH_OMAP2PLUS | 14 | select ARCH_OMAP2PLUS |
| 15 | select ARM_CPU_SUSPEND if PM | 15 | select ARM_CPU_SUSPEND if PM |
| 16 | select OMAP_INTERCONNECT | 16 | select OMAP_INTERCONNECT |
| 17 | select PM_OPP if PM | 17 | select PM_OPP if PM |
| 18 | select PM_RUNTIME if CPU_IDLE | 18 | select PM if CPU_IDLE |
| 19 | select SOC_HAS_OMAP2_SDRC | 19 | select SOC_HAS_OMAP2_SDRC |
| 20 | 20 | ||
| 21 | config ARCH_OMAP4 | 21 | config ARCH_OMAP4 |
| 22 | bool "TI OMAP4" | 22 | bool "TI OMAP4" |
| 23 | depends on ARCH_MULTI_V7 | 23 | depends on ARCH_MULTI_V7 |
| 24 | select ARCH_OMAP2PLUS | 24 | select ARCH_OMAP2PLUS |
| 25 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP | 25 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| 26 | select ARM_CPU_SUSPEND if PM | 26 | select ARM_CPU_SUSPEND if PM |
| 27 | select ARM_ERRATA_720789 | 27 | select ARM_ERRATA_720789 |
| 28 | select ARM_GIC | 28 | select ARM_GIC |
| 29 | select HAVE_ARM_SCU if SMP | 29 | select HAVE_ARM_SCU if SMP |
| 30 | select HAVE_ARM_TWD if SMP | 30 | select HAVE_ARM_TWD if SMP |
| 31 | select OMAP_INTERCONNECT | 31 | select OMAP_INTERCONNECT |
| 32 | select PL310_ERRATA_588369 if CACHE_L2X0 | 32 | select PL310_ERRATA_588369 if CACHE_L2X0 |
| 33 | select PL310_ERRATA_727915 if CACHE_L2X0 | 33 | select PL310_ERRATA_727915 if CACHE_L2X0 |
| 34 | select PM_OPP if PM | 34 | select PM_OPP if PM |
| 35 | select PM_RUNTIME if CPU_IDLE | 35 | select PM if CPU_IDLE |
| 36 | select ARM_ERRATA_754322 | 36 | select ARM_ERRATA_754322 |
| 37 | select ARM_ERRATA_775420 | 37 | select ARM_ERRATA_775420 |
| 38 | 38 | ||
| 39 | config SOC_OMAP5 | 39 | config SOC_OMAP5 |
| 40 | bool "TI OMAP5" | 40 | bool "TI OMAP5" |
| 41 | depends on ARCH_MULTI_V7 | 41 | depends on ARCH_MULTI_V7 |
| 42 | select ARCH_OMAP2PLUS | 42 | select ARCH_OMAP2PLUS |
| 43 | select ARM_CPU_SUSPEND if PM | 43 | select ARM_CPU_SUSPEND if PM |
| 44 | select ARM_GIC | 44 | select ARM_GIC |
| 45 | select HAVE_ARM_SCU if SMP | 45 | select HAVE_ARM_SCU if SMP |
| 46 | select HAVE_ARM_TWD if SMP | 46 | select HAVE_ARM_TWD if SMP |
| 47 | select HAVE_ARM_ARCH_TIMER | 47 | select HAVE_ARM_ARCH_TIMER |
| 48 | select ARM_ERRATA_798181 if SMP | 48 | select ARM_ERRATA_798181 if SMP |
| 49 | 49 | ||
| 50 | config SOC_AM33XX | 50 | config SOC_AM33XX |
| 51 | bool "TI AM33XX" | 51 | bool "TI AM33XX" |
| 52 | depends on ARCH_MULTI_V7 | 52 | depends on ARCH_MULTI_V7 |
| 53 | select ARCH_OMAP2PLUS | 53 | select ARCH_OMAP2PLUS |
| 54 | select ARM_CPU_SUSPEND if PM | 54 | select ARM_CPU_SUSPEND if PM |
| 55 | 55 | ||
| 56 | config SOC_AM43XX | 56 | config SOC_AM43XX |
| 57 | bool "TI AM43x" | 57 | bool "TI AM43x" |
| 58 | depends on ARCH_MULTI_V7 | 58 | depends on ARCH_MULTI_V7 |
| 59 | select ARCH_OMAP2PLUS | 59 | select ARCH_OMAP2PLUS |
| 60 | select ARM_GIC | 60 | select ARM_GIC |
| 61 | select MACH_OMAP_GENERIC | 61 | select MACH_OMAP_GENERIC |
| 62 | select MIGHT_HAVE_CACHE_L2X0 | 62 | select MIGHT_HAVE_CACHE_L2X0 |
| 63 | 63 | ||
| 64 | config SOC_DRA7XX | 64 | config SOC_DRA7XX |
| 65 | bool "TI DRA7XX" | 65 | bool "TI DRA7XX" |
| 66 | depends on ARCH_MULTI_V7 | 66 | depends on ARCH_MULTI_V7 |
| 67 | select ARCH_OMAP2PLUS | 67 | select ARCH_OMAP2PLUS |
| 68 | select ARM_CPU_SUSPEND if PM | 68 | select ARM_CPU_SUSPEND if PM |
| 69 | select ARM_GIC | 69 | select ARM_GIC |
| 70 | select HAVE_ARM_ARCH_TIMER | 70 | select HAVE_ARM_ARCH_TIMER |
| 71 | select IRQ_CROSSBAR | 71 | select IRQ_CROSSBAR |
| 72 | 72 | ||
| 73 | config ARCH_OMAP2PLUS | 73 | config ARCH_OMAP2PLUS |
| 74 | bool | 74 | bool |
| 75 | select ARCH_HAS_BANDGAP | 75 | select ARCH_HAS_BANDGAP |
| 76 | select ARCH_HAS_HOLES_MEMORYMODEL | 76 | select ARCH_HAS_HOLES_MEMORYMODEL |
| 77 | select ARCH_OMAP | 77 | select ARCH_OMAP |
| 78 | select ARCH_REQUIRE_GPIOLIB | 78 | select ARCH_REQUIRE_GPIOLIB |
| 79 | select CLKSRC_MMIO | 79 | select CLKSRC_MMIO |
| 80 | select GENERIC_IRQ_CHIP | 80 | select GENERIC_IRQ_CHIP |
| 81 | select MACH_OMAP_GENERIC | 81 | select MACH_OMAP_GENERIC |
| 82 | select MEMORY | 82 | select MEMORY |
| 83 | select OMAP_DM_TIMER | 83 | select OMAP_DM_TIMER |
| 84 | select OMAP_GPMC | 84 | select OMAP_GPMC |
| 85 | select PINCTRL | 85 | select PINCTRL |
| 86 | select SOC_BUS | 86 | select SOC_BUS |
| 87 | select TI_PRIV_EDMA | 87 | select TI_PRIV_EDMA |
| 88 | select OMAP_IRQCHIP | 88 | select OMAP_IRQCHIP |
| 89 | help | 89 | help |
| 90 | Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 | 90 | Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 |
| 91 | 91 | ||
| 92 | 92 | ||
| 93 | if ARCH_OMAP2PLUS | 93 | if ARCH_OMAP2PLUS |
| 94 | 94 | ||
| 95 | menu "TI OMAP2/3/4 Specific Features" | 95 | menu "TI OMAP2/3/4 Specific Features" |
| 96 | 96 | ||
| 97 | config ARCH_OMAP2PLUS_TYPICAL | 97 | config ARCH_OMAP2PLUS_TYPICAL |
| 98 | bool "Typical OMAP configuration" | 98 | bool "Typical OMAP configuration" |
| 99 | default y | 99 | default y |
| 100 | select AEABI | 100 | select AEABI |
| 101 | select HIGHMEM | 101 | select HIGHMEM |
| 102 | select I2C | 102 | select I2C |
| 103 | select I2C_OMAP | 103 | select I2C_OMAP |
| 104 | select MENELAUS if ARCH_OMAP2 | 104 | select MENELAUS if ARCH_OMAP2 |
| 105 | select NEON if CPU_V7 | 105 | select NEON if CPU_V7 |
| 106 | select PM_RUNTIME | 106 | select PM |
| 107 | select REGULATOR | 107 | select REGULATOR |
| 108 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 | 108 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 |
| 109 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 | 109 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 |
| 110 | select VFP | 110 | select VFP |
| 111 | help | 111 | help |
| 112 | Compile a kernel suitable for booting most boards | 112 | Compile a kernel suitable for booting most boards |
| 113 | 113 | ||
| 114 | config SOC_HAS_OMAP2_SDRC | 114 | config SOC_HAS_OMAP2_SDRC |
| 115 | bool "OMAP2 SDRAM Controller support" | 115 | bool "OMAP2 SDRAM Controller support" |
| 116 | 116 | ||
| 117 | config SOC_HAS_REALTIME_COUNTER | 117 | config SOC_HAS_REALTIME_COUNTER |
| 118 | bool "Real time free running counter" | 118 | bool "Real time free running counter" |
| 119 | depends on SOC_OMAP5 || SOC_DRA7XX | 119 | depends on SOC_OMAP5 || SOC_DRA7XX |
| 120 | default y | 120 | default y |
| 121 | 121 | ||
| 122 | comment "OMAP Core Type" | 122 | comment "OMAP Core Type" |
| 123 | depends on ARCH_OMAP2 | 123 | depends on ARCH_OMAP2 |
| 124 | 124 | ||
| 125 | config SOC_OMAP2420 | 125 | config SOC_OMAP2420 |
| 126 | bool "OMAP2420 support" | 126 | bool "OMAP2420 support" |
| 127 | depends on ARCH_OMAP2 | 127 | depends on ARCH_OMAP2 |
| 128 | default y | 128 | default y |
| 129 | select OMAP_DM_TIMER | 129 | select OMAP_DM_TIMER |
| 130 | select SOC_HAS_OMAP2_SDRC | 130 | select SOC_HAS_OMAP2_SDRC |
| 131 | 131 | ||
| 132 | config SOC_OMAP2430 | 132 | config SOC_OMAP2430 |
| 133 | bool "OMAP2430 support" | 133 | bool "OMAP2430 support" |
| 134 | depends on ARCH_OMAP2 | 134 | depends on ARCH_OMAP2 |
| 135 | default y | 135 | default y |
| 136 | select SOC_HAS_OMAP2_SDRC | 136 | select SOC_HAS_OMAP2_SDRC |
| 137 | 137 | ||
| 138 | config SOC_OMAP3430 | 138 | config SOC_OMAP3430 |
| 139 | bool "OMAP3430 support" | 139 | bool "OMAP3430 support" |
| 140 | depends on ARCH_OMAP3 | 140 | depends on ARCH_OMAP3 |
| 141 | default y | 141 | default y |
| 142 | select SOC_HAS_OMAP2_SDRC | 142 | select SOC_HAS_OMAP2_SDRC |
| 143 | 143 | ||
| 144 | config SOC_TI81XX | 144 | config SOC_TI81XX |
| 145 | bool "TI81XX support" | 145 | bool "TI81XX support" |
| 146 | depends on ARCH_OMAP3 | 146 | depends on ARCH_OMAP3 |
| 147 | default y | 147 | default y |
| 148 | 148 | ||
| 149 | config OMAP_PACKAGE_CBC | 149 | config OMAP_PACKAGE_CBC |
| 150 | bool | 150 | bool |
| 151 | 151 | ||
| 152 | config OMAP_PACKAGE_CBB | 152 | config OMAP_PACKAGE_CBB |
| 153 | bool | 153 | bool |
| 154 | 154 | ||
| 155 | config OMAP_PACKAGE_CUS | 155 | config OMAP_PACKAGE_CUS |
| 156 | bool | 156 | bool |
| 157 | 157 | ||
| 158 | config OMAP_PACKAGE_CBP | 158 | config OMAP_PACKAGE_CBP |
| 159 | bool | 159 | bool |
| 160 | 160 | ||
| 161 | comment "OMAP Legacy Platform Data Board Type" | 161 | comment "OMAP Legacy Platform Data Board Type" |
| 162 | depends on ARCH_OMAP2PLUS | 162 | depends on ARCH_OMAP2PLUS |
| 163 | 163 | ||
| 164 | config MACH_OMAP_GENERIC | 164 | config MACH_OMAP_GENERIC |
| 165 | bool | 165 | bool |
| 166 | 166 | ||
| 167 | config MACH_OMAP2_TUSB6010 | 167 | config MACH_OMAP2_TUSB6010 |
| 168 | bool | 168 | bool |
| 169 | depends on ARCH_OMAP2 && SOC_OMAP2420 | 169 | depends on ARCH_OMAP2 && SOC_OMAP2420 |
| 170 | default y if MACH_NOKIA_N8X0 | 170 | default y if MACH_NOKIA_N8X0 |
| 171 | 171 | ||
| 172 | config MACH_OMAP3_BEAGLE | 172 | config MACH_OMAP3_BEAGLE |
| 173 | bool "OMAP3 BEAGLE board" | 173 | bool "OMAP3 BEAGLE board" |
| 174 | depends on ARCH_OMAP3 | 174 | depends on ARCH_OMAP3 |
| 175 | default y | 175 | default y |
| 176 | select OMAP_PACKAGE_CBB | 176 | select OMAP_PACKAGE_CBB |
| 177 | 177 | ||
| 178 | config MACH_DEVKIT8000 | 178 | config MACH_DEVKIT8000 |
| 179 | bool "DEVKIT8000 board" | 179 | bool "DEVKIT8000 board" |
| 180 | depends on ARCH_OMAP3 | 180 | depends on ARCH_OMAP3 |
| 181 | default y | 181 | default y |
| 182 | select OMAP_PACKAGE_CUS | 182 | select OMAP_PACKAGE_CUS |
| 183 | 183 | ||
| 184 | config MACH_OMAP_LDP | 184 | config MACH_OMAP_LDP |
| 185 | bool "OMAP3 LDP board" | 185 | bool "OMAP3 LDP board" |
| 186 | depends on ARCH_OMAP3 | 186 | depends on ARCH_OMAP3 |
| 187 | default y | 187 | default y |
| 188 | select OMAP_PACKAGE_CBB | 188 | select OMAP_PACKAGE_CBB |
| 189 | 189 | ||
| 190 | config MACH_OMAP3530_LV_SOM | 190 | config MACH_OMAP3530_LV_SOM |
| 191 | bool "OMAP3 Logic 3530 LV SOM board" | 191 | bool "OMAP3 Logic 3530 LV SOM board" |
| 192 | depends on ARCH_OMAP3 | 192 | depends on ARCH_OMAP3 |
| 193 | default y | 193 | default y |
| 194 | select OMAP_PACKAGE_CBB | 194 | select OMAP_PACKAGE_CBB |
| 195 | help | 195 | help |
| 196 | Support for the LogicPD OMAP3530 SOM Development kit | 196 | Support for the LogicPD OMAP3530 SOM Development kit |
| 197 | for full description please see the products webpage at | 197 | for full description please see the products webpage at |
| 198 | http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit | 198 | http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit |
| 199 | 199 | ||
| 200 | config MACH_OMAP3_TORPEDO | 200 | config MACH_OMAP3_TORPEDO |
| 201 | bool "OMAP3 Logic 35x Torpedo board" | 201 | bool "OMAP3 Logic 35x Torpedo board" |
| 202 | depends on ARCH_OMAP3 | 202 | depends on ARCH_OMAP3 |
| 203 | default y | 203 | default y |
| 204 | select OMAP_PACKAGE_CBB | 204 | select OMAP_PACKAGE_CBB |
| 205 | help | 205 | help |
| 206 | Support for the LogicPD OMAP35x Torpedo Development kit | 206 | Support for the LogicPD OMAP35x Torpedo Development kit |
| 207 | for full description please see the products webpage at | 207 | for full description please see the products webpage at |
| 208 | http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit | 208 | http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit |
| 209 | 209 | ||
| 210 | config MACH_OVERO | 210 | config MACH_OVERO |
| 211 | bool "Gumstix Overo board" | 211 | bool "Gumstix Overo board" |
| 212 | depends on ARCH_OMAP3 | 212 | depends on ARCH_OMAP3 |
| 213 | default y | 213 | default y |
| 214 | select OMAP_PACKAGE_CBB | 214 | select OMAP_PACKAGE_CBB |
| 215 | 215 | ||
| 216 | config MACH_OMAP3517EVM | 216 | config MACH_OMAP3517EVM |
| 217 | bool "OMAP3517/ AM3517 EVM board" | 217 | bool "OMAP3517/ AM3517 EVM board" |
| 218 | depends on ARCH_OMAP3 | 218 | depends on ARCH_OMAP3 |
| 219 | default y | 219 | default y |
| 220 | select OMAP_PACKAGE_CBB | 220 | select OMAP_PACKAGE_CBB |
| 221 | 221 | ||
| 222 | config MACH_CRANEBOARD | 222 | config MACH_CRANEBOARD |
| 223 | bool "AM3517/05 CRANE board" | 223 | bool "AM3517/05 CRANE board" |
| 224 | depends on ARCH_OMAP3 | 224 | depends on ARCH_OMAP3 |
| 225 | select OMAP_PACKAGE_CBB | 225 | select OMAP_PACKAGE_CBB |
| 226 | 226 | ||
| 227 | config MACH_OMAP3_PANDORA | 227 | config MACH_OMAP3_PANDORA |
| 228 | bool "OMAP3 Pandora" | 228 | bool "OMAP3 Pandora" |
| 229 | depends on ARCH_OMAP3 | 229 | depends on ARCH_OMAP3 |
| 230 | default y | 230 | default y |
| 231 | select OMAP_PACKAGE_CBB | 231 | select OMAP_PACKAGE_CBB |
| 232 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | 232 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
| 233 | 233 | ||
| 234 | config MACH_TOUCHBOOK | 234 | config MACH_TOUCHBOOK |
| 235 | bool "OMAP3 Touch Book" | 235 | bool "OMAP3 Touch Book" |
| 236 | depends on ARCH_OMAP3 | 236 | depends on ARCH_OMAP3 |
| 237 | default y | 237 | default y |
| 238 | select OMAP_PACKAGE_CBB | 238 | select OMAP_PACKAGE_CBB |
| 239 | 239 | ||
| 240 | config MACH_NOKIA_N810 | 240 | config MACH_NOKIA_N810 |
| 241 | bool | 241 | bool |
| 242 | 242 | ||
| 243 | config MACH_NOKIA_N810_WIMAX | 243 | config MACH_NOKIA_N810_WIMAX |
| 244 | bool | 244 | bool |
| 245 | 245 | ||
| 246 | config MACH_NOKIA_N8X0 | 246 | config MACH_NOKIA_N8X0 |
| 247 | bool "Nokia N800/N810" | 247 | bool "Nokia N800/N810" |
| 248 | depends on SOC_OMAP2420 | 248 | depends on SOC_OMAP2420 |
| 249 | default y | 249 | default y |
| 250 | select MACH_NOKIA_N810 | 250 | select MACH_NOKIA_N810 |
| 251 | select MACH_NOKIA_N810_WIMAX | 251 | select MACH_NOKIA_N810_WIMAX |
| 252 | 252 | ||
| 253 | config MACH_NOKIA_RX51 | 253 | config MACH_NOKIA_RX51 |
| 254 | bool "Nokia N900 (RX-51) phone" | 254 | bool "Nokia N900 (RX-51) phone" |
| 255 | depends on ARCH_OMAP3 | 255 | depends on ARCH_OMAP3 |
| 256 | default y | 256 | default y |
| 257 | select OMAP_PACKAGE_CBB | 257 | select OMAP_PACKAGE_CBB |
| 258 | 258 | ||
| 259 | config MACH_CM_T35 | 259 | config MACH_CM_T35 |
| 260 | bool "CompuLab CM-T35/CM-T3730 modules" | 260 | bool "CompuLab CM-T35/CM-T3730 modules" |
| 261 | depends on ARCH_OMAP3 | 261 | depends on ARCH_OMAP3 |
| 262 | default y | 262 | default y |
| 263 | select MACH_CM_T3730 | 263 | select MACH_CM_T3730 |
| 264 | select OMAP_PACKAGE_CUS | 264 | select OMAP_PACKAGE_CUS |
| 265 | 265 | ||
| 266 | config MACH_CM_T3517 | 266 | config MACH_CM_T3517 |
| 267 | bool "CompuLab CM-T3517 module" | 267 | bool "CompuLab CM-T3517 module" |
| 268 | depends on ARCH_OMAP3 | 268 | depends on ARCH_OMAP3 |
| 269 | default y | 269 | default y |
| 270 | select OMAP_PACKAGE_CBB | 270 | select OMAP_PACKAGE_CBB |
| 271 | 271 | ||
| 272 | config MACH_CM_T3730 | 272 | config MACH_CM_T3730 |
| 273 | bool | 273 | bool |
| 274 | 274 | ||
| 275 | config MACH_SBC3530 | 275 | config MACH_SBC3530 |
| 276 | bool "OMAP3 SBC STALKER board" | 276 | bool "OMAP3 SBC STALKER board" |
| 277 | depends on ARCH_OMAP3 | 277 | depends on ARCH_OMAP3 |
| 278 | default y | 278 | default y |
| 279 | select OMAP_PACKAGE_CUS | 279 | select OMAP_PACKAGE_CUS |
| 280 | 280 | ||
| 281 | config OMAP3_SDRC_AC_TIMING | 281 | config OMAP3_SDRC_AC_TIMING |
| 282 | bool "Enable SDRC AC timing register changes" | 282 | bool "Enable SDRC AC timing register changes" |
| 283 | depends on ARCH_OMAP3 | 283 | depends on ARCH_OMAP3 |
| 284 | default n | 284 | default n |
| 285 | help | 285 | help |
| 286 | If you know that none of your system initiators will attempt to | 286 | If you know that none of your system initiators will attempt to |
| 287 | access SDRAM during CORE DVFS, select Y here. This should boost | 287 | access SDRAM during CORE DVFS, select Y here. This should boost |
| 288 | SDRAM performance at lower CORE OPPs. There are relatively few | 288 | SDRAM performance at lower CORE OPPs. There are relatively few |
| 289 | users who will wish to say yes at this point - almost everyone will | 289 | users who will wish to say yes at this point - almost everyone will |
| 290 | wish to say no. Selecting yes without understanding what is | 290 | wish to say no. Selecting yes without understanding what is |
| 291 | going on could result in system crashes; | 291 | going on could result in system crashes; |
| 292 | 292 | ||
| 293 | config OMAP4_ERRATA_I688 | 293 | config OMAP4_ERRATA_I688 |
| 294 | bool "OMAP4 errata: Async Bridge Corruption" | 294 | bool "OMAP4 errata: Async Bridge Corruption" |
| 295 | depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM | 295 | depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM |
| 296 | select ARCH_HAS_BARRIERS | 296 | select ARCH_HAS_BARRIERS |
| 297 | help | 297 | help |
| 298 | If a data is stalled inside asynchronous bridge because of back | 298 | If a data is stalled inside asynchronous bridge because of back |
| 299 | pressure, it may be accepted multiple times, creating pointer | 299 | pressure, it may be accepted multiple times, creating pointer |
| 300 | misalignment that will corrupt next transfers on that data path | 300 | misalignment that will corrupt next transfers on that data path |
| 301 | until next reset of the system (No recovery procedure once the | 301 | until next reset of the system (No recovery procedure once the |
| 302 | issue is hit, the path remains consistently broken). Async bridge | 302 | issue is hit, the path remains consistently broken). Async bridge |
| 303 | can be found on path between MPU to EMIF and MPU to L3 interconnect. | 303 | can be found on path between MPU to EMIF and MPU to L3 interconnect. |
| 304 | This situation can happen only when the idle is initiated by a | 304 | This situation can happen only when the idle is initiated by a |
| 305 | Master Request Disconnection (which is trigged by software when | 305 | Master Request Disconnection (which is trigged by software when |
| 306 | executing WFI on CPU). | 306 | executing WFI on CPU). |
| 307 | The work-around for this errata needs all the initiators connected | 307 | The work-around for this errata needs all the initiators connected |
| 308 | through async bridge must ensure that data path is properly drained | 308 | through async bridge must ensure that data path is properly drained |
| 309 | before issuing WFI. This condition will be met if one Strongly ordered | 309 | before issuing WFI. This condition will be met if one Strongly ordered |
| 310 | access is performed to the target right before executing the WFI. | 310 | access is performed to the target right before executing the WFI. |
| 311 | In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. | 311 | In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. |
| 312 | IO barrier ensure that there is no synchronisation loss on initiators | 312 | IO barrier ensure that there is no synchronisation loss on initiators |
| 313 | operating on both interconnect port simultaneously. | 313 | operating on both interconnect port simultaneously. |
| 314 | endmenu | 314 | endmenu |
| 315 | 315 | ||
| 316 | endif | 316 | endif |
| 317 | 317 | ||
| 318 | endmenu | 318 | endmenu |
| 319 | 319 |
arch/mips/configs/db1xxx_defconfig
| 1 | CONFIG_MIPS_ALCHEMY=y | 1 | CONFIG_MIPS_ALCHEMY=y |
| 2 | CONFIG_MIPS_DB1XXX=y | 2 | CONFIG_MIPS_DB1XXX=y |
| 3 | CONFIG_CMA=y | 3 | CONFIG_CMA=y |
| 4 | CONFIG_CMA_DEBUG=y | 4 | CONFIG_CMA_DEBUG=y |
| 5 | CONFIG_HZ_100=y | 5 | CONFIG_HZ_100=y |
| 6 | CONFIG_LOCALVERSION="-db1xxx" | 6 | CONFIG_LOCALVERSION="-db1xxx" |
| 7 | CONFIG_KERNEL_XZ=y | 7 | CONFIG_KERNEL_XZ=y |
| 8 | CONFIG_DEFAULT_HOSTNAME="db1xxx" | 8 | CONFIG_DEFAULT_HOSTNAME="db1xxx" |
| 9 | CONFIG_SYSVIPC=y | 9 | CONFIG_SYSVIPC=y |
| 10 | CONFIG_POSIX_MQUEUE=y | 10 | CONFIG_POSIX_MQUEUE=y |
| 11 | CONFIG_FHANDLE=y | 11 | CONFIG_FHANDLE=y |
| 12 | CONFIG_AUDIT=y | 12 | CONFIG_AUDIT=y |
| 13 | CONFIG_NO_HZ=y | 13 | CONFIG_NO_HZ=y |
| 14 | CONFIG_HIGH_RES_TIMERS=y | 14 | CONFIG_HIGH_RES_TIMERS=y |
| 15 | CONFIG_LOG_BUF_SHIFT=16 | 15 | CONFIG_LOG_BUF_SHIFT=16 |
| 16 | CONFIG_CGROUPS=y | 16 | CONFIG_CGROUPS=y |
| 17 | CONFIG_CGROUP_FREEZER=y | 17 | CONFIG_CGROUP_FREEZER=y |
| 18 | CONFIG_CGROUP_DEVICE=y | 18 | CONFIG_CGROUP_DEVICE=y |
| 19 | CONFIG_CPUSETS=y | 19 | CONFIG_CPUSETS=y |
| 20 | CONFIG_CGROUP_CPUACCT=y | 20 | CONFIG_CGROUP_CPUACCT=y |
| 21 | CONFIG_RESOURCE_COUNTERS=y | 21 | CONFIG_RESOURCE_COUNTERS=y |
| 22 | CONFIG_MEMCG=y | 22 | CONFIG_MEMCG=y |
| 23 | CONFIG_MEMCG_SWAP=y | 23 | CONFIG_MEMCG_SWAP=y |
| 24 | CONFIG_MEMCG_KMEM=y | 24 | CONFIG_MEMCG_KMEM=y |
| 25 | CONFIG_CGROUP_SCHED=y | 25 | CONFIG_CGROUP_SCHED=y |
| 26 | CONFIG_CFS_BANDWIDTH=y | 26 | CONFIG_CFS_BANDWIDTH=y |
| 27 | CONFIG_RT_GROUP_SCHED=y | 27 | CONFIG_RT_GROUP_SCHED=y |
| 28 | CONFIG_BLK_CGROUP=y | 28 | CONFIG_BLK_CGROUP=y |
| 29 | CONFIG_KALLSYMS_ALL=y | 29 | CONFIG_KALLSYMS_ALL=y |
| 30 | CONFIG_EMBEDDED=y | 30 | CONFIG_EMBEDDED=y |
| 31 | CONFIG_SLAB=y | 31 | CONFIG_SLAB=y |
| 32 | CONFIG_BLK_DEV_BSGLIB=y | 32 | CONFIG_BLK_DEV_BSGLIB=y |
| 33 | CONFIG_PARTITION_ADVANCED=y | 33 | CONFIG_PARTITION_ADVANCED=y |
| 34 | CONFIG_DEFAULT_NOOP=y | 34 | CONFIG_DEFAULT_NOOP=y |
| 35 | CONFIG_PCI=y | 35 | CONFIG_PCI=y |
| 36 | CONFIG_PCI_REALLOC_ENABLE_AUTO=y | 36 | CONFIG_PCI_REALLOC_ENABLE_AUTO=y |
| 37 | CONFIG_PCCARD=y | 37 | CONFIG_PCCARD=y |
| 38 | CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y | 38 | CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y |
| 39 | CONFIG_PM_RUNTIME=y | 39 | CONFIG_PM=y |
| 40 | CONFIG_NET=y | 40 | CONFIG_NET=y |
| 41 | CONFIG_PACKET=y | 41 | CONFIG_PACKET=y |
| 42 | CONFIG_PACKET_DIAG=y | 42 | CONFIG_PACKET_DIAG=y |
| 43 | CONFIG_UNIX=y | 43 | CONFIG_UNIX=y |
| 44 | CONFIG_UNIX_DIAG=y | 44 | CONFIG_UNIX_DIAG=y |
| 45 | CONFIG_XFRM_USER=y | 45 | CONFIG_XFRM_USER=y |
| 46 | CONFIG_XFRM_SUB_POLICY=y | 46 | CONFIG_XFRM_SUB_POLICY=y |
| 47 | CONFIG_XFRM_MIGRATE=y | 47 | CONFIG_XFRM_MIGRATE=y |
| 48 | CONFIG_INET=y | 48 | CONFIG_INET=y |
| 49 | CONFIG_IP_MULTICAST=y | 49 | CONFIG_IP_MULTICAST=y |
| 50 | CONFIG_IP_ADVANCED_ROUTER=y | 50 | CONFIG_IP_ADVANCED_ROUTER=y |
| 51 | CONFIG_IP_FIB_TRIE_STATS=y | 51 | CONFIG_IP_FIB_TRIE_STATS=y |
| 52 | CONFIG_NET_IPIP=y | 52 | CONFIG_NET_IPIP=y |
| 53 | CONFIG_NET_IPGRE_DEMUX=y | 53 | CONFIG_NET_IPGRE_DEMUX=y |
| 54 | CONFIG_NET_IPGRE=y | 54 | CONFIG_NET_IPGRE=y |
| 55 | CONFIG_NET_IPGRE_BROADCAST=y | 55 | CONFIG_NET_IPGRE_BROADCAST=y |
| 56 | CONFIG_SYN_COOKIES=y | 56 | CONFIG_SYN_COOKIES=y |
| 57 | CONFIG_INET_AH=y | 57 | CONFIG_INET_AH=y |
| 58 | CONFIG_INET_ESP=y | 58 | CONFIG_INET_ESP=y |
| 59 | CONFIG_INET_IPCOMP=y | 59 | CONFIG_INET_IPCOMP=y |
| 60 | CONFIG_INET_UDP_DIAG=y | 60 | CONFIG_INET_UDP_DIAG=y |
| 61 | CONFIG_TCP_CONG_ADVANCED=y | 61 | CONFIG_TCP_CONG_ADVANCED=y |
| 62 | CONFIG_TCP_CONG_VENO=y | 62 | CONFIG_TCP_CONG_VENO=y |
| 63 | CONFIG_DEFAULT_VENO=y | 63 | CONFIG_DEFAULT_VENO=y |
| 64 | CONFIG_IPV6_ROUTER_PREF=y | 64 | CONFIG_IPV6_ROUTER_PREF=y |
| 65 | CONFIG_IPV6_ROUTE_INFO=y | 65 | CONFIG_IPV6_ROUTE_INFO=y |
| 66 | CONFIG_IPV6_OPTIMISTIC_DAD=y | 66 | CONFIG_IPV6_OPTIMISTIC_DAD=y |
| 67 | CONFIG_INET6_AH=y | 67 | CONFIG_INET6_AH=y |
| 68 | CONFIG_INET6_ESP=y | 68 | CONFIG_INET6_ESP=y |
| 69 | CONFIG_INET6_IPCOMP=y | 69 | CONFIG_INET6_IPCOMP=y |
| 70 | CONFIG_IPV6_MIP6=y | 70 | CONFIG_IPV6_MIP6=y |
| 71 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y | 71 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y |
| 72 | CONFIG_IPV6_VTI=y | 72 | CONFIG_IPV6_VTI=y |
| 73 | CONFIG_IPV6_SIT_6RD=y | 73 | CONFIG_IPV6_SIT_6RD=y |
| 74 | CONFIG_IPV6_GRE=y | 74 | CONFIG_IPV6_GRE=y |
| 75 | CONFIG_IPV6_MULTIPLE_TABLES=y | 75 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 76 | CONFIG_IPV6_SUBTREES=y | 76 | CONFIG_IPV6_SUBTREES=y |
| 77 | CONFIG_IPV6_MROUTE=y | 77 | CONFIG_IPV6_MROUTE=y |
| 78 | CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y | 78 | CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y |
| 79 | CONFIG_IPV6_PIMSM_V2=y | 79 | CONFIG_IPV6_PIMSM_V2=y |
| 80 | CONFIG_BRIDGE=y | 80 | CONFIG_BRIDGE=y |
| 81 | CONFIG_NETLINK_MMAP=y | 81 | CONFIG_NETLINK_MMAP=y |
| 82 | CONFIG_NETLINK_DIAG=y | 82 | CONFIG_NETLINK_DIAG=y |
| 83 | CONFIG_IRDA=y | 83 | CONFIG_IRDA=y |
| 84 | CONFIG_IRLAN=y | 84 | CONFIG_IRLAN=y |
| 85 | CONFIG_IRCOMM=y | 85 | CONFIG_IRCOMM=y |
| 86 | CONFIG_IRDA_ULTRA=y | 86 | CONFIG_IRDA_ULTRA=y |
| 87 | CONFIG_IRDA_CACHE_LAST_LSAP=y | 87 | CONFIG_IRDA_CACHE_LAST_LSAP=y |
| 88 | CONFIG_IRDA_FAST_RR=y | 88 | CONFIG_IRDA_FAST_RR=y |
| 89 | CONFIG_AU1000_FIR=y | 89 | CONFIG_AU1000_FIR=y |
| 90 | CONFIG_BT=y | 90 | CONFIG_BT=y |
| 91 | CONFIG_BT_RFCOMM=y | 91 | CONFIG_BT_RFCOMM=y |
| 92 | CONFIG_BT_RFCOMM_TTY=y | 92 | CONFIG_BT_RFCOMM_TTY=y |
| 93 | CONFIG_BT_BNEP=y | 93 | CONFIG_BT_BNEP=y |
| 94 | CONFIG_BT_BNEP_MC_FILTER=y | 94 | CONFIG_BT_BNEP_MC_FILTER=y |
| 95 | CONFIG_BT_BNEP_PROTO_FILTER=y | 95 | CONFIG_BT_BNEP_PROTO_FILTER=y |
| 96 | CONFIG_BT_HIDP=y | 96 | CONFIG_BT_HIDP=y |
| 97 | CONFIG_BT_HCIBTUSB=y | 97 | CONFIG_BT_HCIBTUSB=y |
| 98 | CONFIG_CFG80211=y | 98 | CONFIG_CFG80211=y |
| 99 | CONFIG_CFG80211_WEXT=y | 99 | CONFIG_CFG80211_WEXT=y |
| 100 | CONFIG_MAC80211=y | 100 | CONFIG_MAC80211=y |
| 101 | CONFIG_DEVTMPFS=y | 101 | CONFIG_DEVTMPFS=y |
| 102 | CONFIG_DEVTMPFS_MOUNT=y | 102 | CONFIG_DEVTMPFS_MOUNT=y |
| 103 | CONFIG_MTD=y | 103 | CONFIG_MTD=y |
| 104 | CONFIG_MTD_CMDLINE_PARTS=y | 104 | CONFIG_MTD_CMDLINE_PARTS=y |
| 105 | CONFIG_MTD_BLOCK=y | 105 | CONFIG_MTD_BLOCK=y |
| 106 | CONFIG_MTD_CFI=y | 106 | CONFIG_MTD_CFI=y |
| 107 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 107 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| 108 | CONFIG_MTD_CFI_AMDSTD=y | 108 | CONFIG_MTD_CFI_AMDSTD=y |
| 109 | CONFIG_MTD_PHYSMAP=y | 109 | CONFIG_MTD_PHYSMAP=y |
| 110 | CONFIG_MTD_M25P80=y | 110 | CONFIG_MTD_M25P80=y |
| 111 | CONFIG_MTD_SST25L=y | 111 | CONFIG_MTD_SST25L=y |
| 112 | CONFIG_MTD_NAND=y | 112 | CONFIG_MTD_NAND=y |
| 113 | CONFIG_MTD_NAND_ECC_BCH=y | 113 | CONFIG_MTD_NAND_ECC_BCH=y |
| 114 | CONFIG_MTD_NAND_AU1550=y | 114 | CONFIG_MTD_NAND_AU1550=y |
| 115 | CONFIG_MTD_NAND_PLATFORM=y | 115 | CONFIG_MTD_NAND_PLATFORM=y |
| 116 | CONFIG_MTD_SPI_NOR=y | 116 | CONFIG_MTD_SPI_NOR=y |
| 117 | CONFIG_EEPROM_AT24=y | 117 | CONFIG_EEPROM_AT24=y |
| 118 | CONFIG_EEPROM_AT25=y | 118 | CONFIG_EEPROM_AT25=y |
| 119 | CONFIG_BLK_DEV_SD=y | 119 | CONFIG_BLK_DEV_SD=y |
| 120 | CONFIG_CHR_DEV_SG=y | 120 | CONFIG_CHR_DEV_SG=y |
| 121 | CONFIG_SCSI_MULTI_LUN=y | 121 | CONFIG_SCSI_MULTI_LUN=y |
| 122 | CONFIG_ATA=y | 122 | CONFIG_ATA=y |
| 123 | CONFIG_PATA_HPT37X=y | 123 | CONFIG_PATA_HPT37X=y |
| 124 | CONFIG_PATA_HPT3X2N=y | 124 | CONFIG_PATA_HPT3X2N=y |
| 125 | CONFIG_PATA_PCMCIA=y | 125 | CONFIG_PATA_PCMCIA=y |
| 126 | CONFIG_PATA_PLATFORM=y | 126 | CONFIG_PATA_PLATFORM=y |
| 127 | CONFIG_NETDEVICES=y | 127 | CONFIG_NETDEVICES=y |
| 128 | CONFIG_NLMON=y | 128 | CONFIG_NLMON=y |
| 129 | CONFIG_PCMCIA_3C589=y | 129 | CONFIG_PCMCIA_3C589=y |
| 130 | CONFIG_MIPS_AU1X00_ENET=y | 130 | CONFIG_MIPS_AU1X00_ENET=y |
| 131 | CONFIG_SMC91X=y | 131 | CONFIG_SMC91X=y |
| 132 | CONFIG_SMSC911X=y | 132 | CONFIG_SMSC911X=y |
| 133 | CONFIG_AMD_PHY=y | 133 | CONFIG_AMD_PHY=y |
| 134 | CONFIG_SMSC_PHY=y | 134 | CONFIG_SMSC_PHY=y |
| 135 | CONFIG_INPUT_EVDEV=y | 135 | CONFIG_INPUT_EVDEV=y |
| 136 | CONFIG_KEYBOARD_GPIO=y | 136 | CONFIG_KEYBOARD_GPIO=y |
| 137 | CONFIG_INPUT_TOUCHSCREEN=y | 137 | CONFIG_INPUT_TOUCHSCREEN=y |
| 138 | CONFIG_TOUCHSCREEN_ADS7846=y | 138 | CONFIG_TOUCHSCREEN_ADS7846=y |
| 139 | CONFIG_TOUCHSCREEN_WM97XX=y | 139 | CONFIG_TOUCHSCREEN_WM97XX=y |
| 140 | CONFIG_INPUT_MISC=y | 140 | CONFIG_INPUT_MISC=y |
| 141 | CONFIG_INPUT_UINPUT=y | 141 | CONFIG_INPUT_UINPUT=y |
| 142 | CONFIG_SERIAL_8250=y | 142 | CONFIG_SERIAL_8250=y |
| 143 | CONFIG_SERIAL_8250_CONSOLE=y | 143 | CONFIG_SERIAL_8250_CONSOLE=y |
| 144 | CONFIG_TTY_PRINTK=y | 144 | CONFIG_TTY_PRINTK=y |
| 145 | CONFIG_I2C=y | 145 | CONFIG_I2C=y |
| 146 | CONFIG_I2C_CHARDEV=y | 146 | CONFIG_I2C_CHARDEV=y |
| 147 | CONFIG_I2C_AU1550=y | 147 | CONFIG_I2C_AU1550=y |
| 148 | CONFIG_SPI=y | 148 | CONFIG_SPI=y |
| 149 | CONFIG_SPI_AU1550=y | 149 | CONFIG_SPI_AU1550=y |
| 150 | CONFIG_SPI_GPIO=y | 150 | CONFIG_SPI_GPIO=y |
| 151 | CONFIG_SENSORS_ADM1025=y | 151 | CONFIG_SENSORS_ADM1025=y |
| 152 | CONFIG_SENSORS_LM70=y | 152 | CONFIG_SENSORS_LM70=y |
| 153 | CONFIG_FB=y | 153 | CONFIG_FB=y |
| 154 | CONFIG_FB_AU1100=y | 154 | CONFIG_FB_AU1100=y |
| 155 | CONFIG_FB_AU1200=y | 155 | CONFIG_FB_AU1200=y |
| 156 | CONFIG_FRAMEBUFFER_CONSOLE=y | 156 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 157 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | 157 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y |
| 158 | CONFIG_SOUND=y | 158 | CONFIG_SOUND=y |
| 159 | CONFIG_SND=y | 159 | CONFIG_SND=y |
| 160 | CONFIG_SND_SEQUENCER=y | 160 | CONFIG_SND_SEQUENCER=y |
| 161 | CONFIG_SND_HRTIMER=y | 161 | CONFIG_SND_HRTIMER=y |
| 162 | CONFIG_SND_DYNAMIC_MINORS=y | 162 | CONFIG_SND_DYNAMIC_MINORS=y |
| 163 | CONFIG_SND_AC97_POWER_SAVE=y | 163 | CONFIG_SND_AC97_POWER_SAVE=y |
| 164 | CONFIG_SND_AC97_POWER_SAVE_DEFAULT=1 | 164 | CONFIG_SND_AC97_POWER_SAVE_DEFAULT=1 |
| 165 | CONFIG_SND_SOC=y | 165 | CONFIG_SND_SOC=y |
| 166 | CONFIG_SND_SOC_AU1XPSC=y | 166 | CONFIG_SND_SOC_AU1XPSC=y |
| 167 | CONFIG_SND_SOC_AU1XAUDIO=y | 167 | CONFIG_SND_SOC_AU1XAUDIO=y |
| 168 | CONFIG_SND_SOC_DB1000=y | 168 | CONFIG_SND_SOC_DB1000=y |
| 169 | CONFIG_SND_SOC_DB1200=y | 169 | CONFIG_SND_SOC_DB1200=y |
| 170 | CONFIG_HIDRAW=y | 170 | CONFIG_HIDRAW=y |
| 171 | CONFIG_UHID=y | 171 | CONFIG_UHID=y |
| 172 | CONFIG_HID_LOGITECH=y | 172 | CONFIG_HID_LOGITECH=y |
| 173 | CONFIG_HID_LOGITECH_DJ=y | 173 | CONFIG_HID_LOGITECH_DJ=y |
| 174 | CONFIG_USB_HIDDEV=y | 174 | CONFIG_USB_HIDDEV=y |
| 175 | CONFIG_USB=y | 175 | CONFIG_USB=y |
| 176 | CONFIG_USB_DYNAMIC_MINORS=y | 176 | CONFIG_USB_DYNAMIC_MINORS=y |
| 177 | CONFIG_USB_OTG=y | 177 | CONFIG_USB_OTG=y |
| 178 | CONFIG_USB_EHCI_HCD=y | 178 | CONFIG_USB_EHCI_HCD=y |
| 179 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | 179 | CONFIG_USB_EHCI_ROOT_HUB_TT=y |
| 180 | CONFIG_USB_EHCI_HCD_PLATFORM=y | 180 | CONFIG_USB_EHCI_HCD_PLATFORM=y |
| 181 | CONFIG_USB_OHCI_HCD=y | 181 | CONFIG_USB_OHCI_HCD=y |
| 182 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 182 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 183 | CONFIG_USB_STORAGE=y | 183 | CONFIG_USB_STORAGE=y |
| 184 | CONFIG_MMC=y | 184 | CONFIG_MMC=y |
| 185 | CONFIG_MMC_CLKGATE=y | 185 | CONFIG_MMC_CLKGATE=y |
| 186 | CONFIG_SDIO_UART=y | 186 | CONFIG_SDIO_UART=y |
| 187 | CONFIG_MMC_AU1X=y | 187 | CONFIG_MMC_AU1X=y |
| 188 | CONFIG_NEW_LEDS=y | 188 | CONFIG_NEW_LEDS=y |
| 189 | CONFIG_LEDS_CLASS=y | 189 | CONFIG_LEDS_CLASS=y |
| 190 | CONFIG_LEDS_TRIGGERS=y | 190 | CONFIG_LEDS_TRIGGERS=y |
| 191 | CONFIG_RTC_CLASS=y | 191 | CONFIG_RTC_CLASS=y |
| 192 | CONFIG_RTC_DRV_AU1XXX=y | 192 | CONFIG_RTC_DRV_AU1XXX=y |
| 193 | CONFIG_FIRMWARE_MEMMAP=y | 193 | CONFIG_FIRMWARE_MEMMAP=y |
| 194 | CONFIG_EXT4_FS=y | 194 | CONFIG_EXT4_FS=y |
| 195 | CONFIG_EXT4_FS_POSIX_ACL=y | 195 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 196 | CONFIG_EXT4_FS_SECURITY=y | 196 | CONFIG_EXT4_FS_SECURITY=y |
| 197 | CONFIG_XFS_FS=y | 197 | CONFIG_XFS_FS=y |
| 198 | CONFIG_XFS_POSIX_ACL=y | 198 | CONFIG_XFS_POSIX_ACL=y |
| 199 | CONFIG_FANOTIFY=y | 199 | CONFIG_FANOTIFY=y |
| 200 | CONFIG_FUSE_FS=y | 200 | CONFIG_FUSE_FS=y |
| 201 | CONFIG_CUSE=y | 201 | CONFIG_CUSE=y |
| 202 | CONFIG_VFAT_FS=y | 202 | CONFIG_VFAT_FS=y |
| 203 | CONFIG_TMPFS=y | 203 | CONFIG_TMPFS=y |
| 204 | CONFIG_TMPFS_POSIX_ACL=y | 204 | CONFIG_TMPFS_POSIX_ACL=y |
| 205 | CONFIG_CONFIGFS_FS=y | 205 | CONFIG_CONFIGFS_FS=y |
| 206 | CONFIG_JFFS2_FS=y | 206 | CONFIG_JFFS2_FS=y |
| 207 | CONFIG_JFFS2_SUMMARY=y | 207 | CONFIG_JFFS2_SUMMARY=y |
| 208 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | 208 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y |
| 209 | CONFIG_JFFS2_LZO=y | 209 | CONFIG_JFFS2_LZO=y |
| 210 | CONFIG_JFFS2_RUBIN=y | 210 | CONFIG_JFFS2_RUBIN=y |
| 211 | CONFIG_SQUASHFS=y | 211 | CONFIG_SQUASHFS=y |
| 212 | CONFIG_SQUASHFS_FILE_DIRECT=y | 212 | CONFIG_SQUASHFS_FILE_DIRECT=y |
| 213 | CONFIG_SQUASHFS_XATTR=y | 213 | CONFIG_SQUASHFS_XATTR=y |
| 214 | CONFIG_SQUASHFS_LZO=y | 214 | CONFIG_SQUASHFS_LZO=y |
| 215 | CONFIG_SQUASHFS_XZ=y | 215 | CONFIG_SQUASHFS_XZ=y |
| 216 | CONFIG_F2FS_FS=y | 216 | CONFIG_F2FS_FS=y |
| 217 | CONFIG_F2FS_FS_SECURITY=y | 217 | CONFIG_F2FS_FS_SECURITY=y |
| 218 | CONFIG_NFS_FS=y | 218 | CONFIG_NFS_FS=y |
| 219 | CONFIG_NFS_V3_ACL=y | 219 | CONFIG_NFS_V3_ACL=y |
| 220 | CONFIG_NFS_V4=y | 220 | CONFIG_NFS_V4=y |
| 221 | CONFIG_NFS_V4_1=y | 221 | CONFIG_NFS_V4_1=y |
| 222 | CONFIG_NFS_V4_2=y | 222 | CONFIG_NFS_V4_2=y |
| 223 | CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="local" | 223 | CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="local" |
| 224 | CONFIG_NFS_V4_1_MIGRATION=y | 224 | CONFIG_NFS_V4_1_MIGRATION=y |
| 225 | CONFIG_NFSD=y | 225 | CONFIG_NFSD=y |
| 226 | CONFIG_NFSD_V3_ACL=y | 226 | CONFIG_NFSD_V3_ACL=y |
| 227 | CONFIG_NFSD_V4=y | 227 | CONFIG_NFSD_V4=y |
| 228 | CONFIG_NLS_CODEPAGE_437=y | 228 | CONFIG_NLS_CODEPAGE_437=y |
| 229 | CONFIG_NLS_CODEPAGE_850=y | 229 | CONFIG_NLS_CODEPAGE_850=y |
| 230 | CONFIG_NLS_CODEPAGE_852=y | 230 | CONFIG_NLS_CODEPAGE_852=y |
| 231 | CONFIG_NLS_CODEPAGE_1250=y | 231 | CONFIG_NLS_CODEPAGE_1250=y |
| 232 | CONFIG_NLS_ASCII=y | 232 | CONFIG_NLS_ASCII=y |
| 233 | CONFIG_NLS_ISO8859_1=y | 233 | CONFIG_NLS_ISO8859_1=y |
| 234 | CONFIG_NLS_ISO8859_2=y | 234 | CONFIG_NLS_ISO8859_2=y |
| 235 | CONFIG_NLS_ISO8859_15=y | 235 | CONFIG_NLS_ISO8859_15=y |
| 236 | CONFIG_NLS_UTF8=y | 236 | CONFIG_NLS_UTF8=y |
| 237 | CONFIG_MAGIC_SYSRQ=y | 237 | CONFIG_MAGIC_SYSRQ=y |
| 238 | CONFIG_SECURITYFS=y | 238 | CONFIG_SECURITYFS=y |
| 239 | CONFIG_CRYPTO_USER=y | 239 | CONFIG_CRYPTO_USER=y |
| 240 | CONFIG_CRYPTO_CRYPTD=y | 240 | CONFIG_CRYPTO_CRYPTD=y |
| 241 | CONFIG_CRYPTO_USER_API_HASH=y | 241 | CONFIG_CRYPTO_USER_API_HASH=y |
| 242 | CONFIG_CRYPTO_USER_API_SKCIPHER=y | 242 | CONFIG_CRYPTO_USER_API_SKCIPHER=y |
| 243 | CONFIG_CRC32_SLICEBY4=y | 243 | CONFIG_CRC32_SLICEBY4=y |
| 244 | CONFIG_FONTS=y | 244 | CONFIG_FONTS=y |
| 245 | CONFIG_FONT_8x8=y | 245 | CONFIG_FONT_8x8=y |
| 246 | 246 |
arch/mips/configs/lemote2f_defconfig
| 1 | CONFIG_MACH_LOONGSON=y | 1 | CONFIG_MACH_LOONGSON=y |
| 2 | CONFIG_LEMOTE_MACH2F=y | 2 | CONFIG_LEMOTE_MACH2F=y |
| 3 | CONFIG_CS5536_MFGPT=y | 3 | CONFIG_CS5536_MFGPT=y |
| 4 | CONFIG_64BIT=y | 4 | CONFIG_64BIT=y |
| 5 | CONFIG_NO_HZ=y | 5 | CONFIG_NO_HZ=y |
| 6 | CONFIG_HIGH_RES_TIMERS=y | 6 | CONFIG_HIGH_RES_TIMERS=y |
| 7 | CONFIG_PREEMPT=y | 7 | CONFIG_PREEMPT=y |
| 8 | CONFIG_KEXEC=y | 8 | CONFIG_KEXEC=y |
| 9 | # CONFIG_SECCOMP is not set | 9 | # CONFIG_SECCOMP is not set |
| 10 | CONFIG_EXPERIMENTAL=y | 10 | CONFIG_EXPERIMENTAL=y |
| 11 | # CONFIG_LOCALVERSION_AUTO is not set | 11 | # CONFIG_LOCALVERSION_AUTO is not set |
| 12 | CONFIG_SYSVIPC=y | 12 | CONFIG_SYSVIPC=y |
| 13 | CONFIG_BSD_PROCESS_ACCT=y | 13 | CONFIG_BSD_PROCESS_ACCT=y |
| 14 | CONFIG_BSD_PROCESS_ACCT_V3=y | 14 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 15 | CONFIG_AUDIT=y | 15 | CONFIG_AUDIT=y |
| 16 | CONFIG_IKCONFIG=y | 16 | CONFIG_IKCONFIG=y |
| 17 | CONFIG_IKCONFIG_PROC=y | 17 | CONFIG_IKCONFIG_PROC=y |
| 18 | CONFIG_LOG_BUF_SHIFT=15 | 18 | CONFIG_LOG_BUF_SHIFT=15 |
| 19 | CONFIG_SYSFS_DEPRECATED_V2=y | 19 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 20 | CONFIG_BLK_DEV_INITRD=y | 20 | CONFIG_BLK_DEV_INITRD=y |
| 21 | CONFIG_RD_BZIP2=y | 21 | CONFIG_RD_BZIP2=y |
| 22 | CONFIG_RD_LZMA=y | 22 | CONFIG_RD_LZMA=y |
| 23 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 23 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 24 | CONFIG_EXPERT=y | 24 | CONFIG_EXPERT=y |
| 25 | CONFIG_PROFILING=y | 25 | CONFIG_PROFILING=y |
| 26 | CONFIG_OPROFILE=m | 26 | CONFIG_OPROFILE=m |
| 27 | CONFIG_MODULES=y | 27 | CONFIG_MODULES=y |
| 28 | CONFIG_MODULE_UNLOAD=y | 28 | CONFIG_MODULE_UNLOAD=y |
| 29 | CONFIG_MODVERSIONS=y | 29 | CONFIG_MODVERSIONS=y |
| 30 | CONFIG_BLK_DEV_INTEGRITY=y | 30 | CONFIG_BLK_DEV_INTEGRITY=y |
| 31 | CONFIG_IOSCHED_DEADLINE=m | 31 | CONFIG_IOSCHED_DEADLINE=m |
| 32 | CONFIG_PCI=y | 32 | CONFIG_PCI=y |
| 33 | CONFIG_BINFMT_MISC=m | 33 | CONFIG_BINFMT_MISC=m |
| 34 | CONFIG_MIPS32_COMPAT=y | 34 | CONFIG_MIPS32_COMPAT=y |
| 35 | CONFIG_MIPS32_O32=y | 35 | CONFIG_MIPS32_O32=y |
| 36 | CONFIG_MIPS32_N32=y | 36 | CONFIG_MIPS32_N32=y |
| 37 | CONFIG_PM=y | 37 | CONFIG_PM=y |
| 38 | CONFIG_HIBERNATION=y | 38 | CONFIG_HIBERNATION=y |
| 39 | CONFIG_PM_STD_PARTITION="/dev/hda3" | 39 | CONFIG_PM_STD_PARTITION="/dev/hda3" |
| 40 | CONFIG_PM_RUNTIME=y | ||
| 41 | CONFIG_CPU_FREQ=y | 40 | CONFIG_CPU_FREQ=y |
| 42 | CONFIG_CPU_FREQ_DEBUG=y | 41 | CONFIG_CPU_FREQ_DEBUG=y |
| 43 | CONFIG_CPU_FREQ_STAT=m | 42 | CONFIG_CPU_FREQ_STAT=m |
| 44 | CONFIG_CPU_FREQ_STAT_DETAILS=y | 43 | CONFIG_CPU_FREQ_STAT_DETAILS=y |
| 45 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | 44 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y |
| 46 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | 45 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m |
| 47 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | 46 | CONFIG_CPU_FREQ_GOV_USERSPACE=m |
| 48 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m | 47 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m |
| 49 | CONFIG_LOONGSON2_CPUFREQ=m | 48 | CONFIG_LOONGSON2_CPUFREQ=m |
| 50 | CONFIG_NET=y | 49 | CONFIG_NET=y |
| 51 | CONFIG_PACKET=y | 50 | CONFIG_PACKET=y |
| 52 | CONFIG_UNIX=y | 51 | CONFIG_UNIX=y |
| 53 | CONFIG_XFRM_USER=m | 52 | CONFIG_XFRM_USER=m |
| 54 | CONFIG_NET_KEY=m | 53 | CONFIG_NET_KEY=m |
| 55 | CONFIG_INET=y | 54 | CONFIG_INET=y |
| 56 | CONFIG_IP_MULTICAST=y | 55 | CONFIG_IP_MULTICAST=y |
| 57 | CONFIG_IP_ADVANCED_ROUTER=y | 56 | CONFIG_IP_ADVANCED_ROUTER=y |
| 58 | CONFIG_IP_MULTIPLE_TABLES=y | 57 | CONFIG_IP_MULTIPLE_TABLES=y |
| 59 | CONFIG_IP_ROUTE_MULTIPATH=y | 58 | CONFIG_IP_ROUTE_MULTIPATH=y |
| 60 | CONFIG_IP_ROUTE_VERBOSE=y | 59 | CONFIG_IP_ROUTE_VERBOSE=y |
| 61 | CONFIG_NET_IPIP=m | 60 | CONFIG_NET_IPIP=m |
| 62 | CONFIG_NET_IPGRE=m | 61 | CONFIG_NET_IPGRE=m |
| 63 | CONFIG_IP_MROUTE=y | 62 | CONFIG_IP_MROUTE=y |
| 64 | CONFIG_IP_PIMSM_V1=y | 63 | CONFIG_IP_PIMSM_V1=y |
| 65 | CONFIG_IP_PIMSM_V2=y | 64 | CONFIG_IP_PIMSM_V2=y |
| 66 | CONFIG_ARPD=y | 65 | CONFIG_ARPD=y |
| 67 | CONFIG_SYN_COOKIES=y | 66 | CONFIG_SYN_COOKIES=y |
| 68 | CONFIG_INET_XFRM_MODE_TRANSPORT=m | 67 | CONFIG_INET_XFRM_MODE_TRANSPORT=m |
| 69 | CONFIG_INET_XFRM_MODE_TUNNEL=m | 68 | CONFIG_INET_XFRM_MODE_TUNNEL=m |
| 70 | CONFIG_INET_XFRM_MODE_BEET=m | 69 | CONFIG_INET_XFRM_MODE_BEET=m |
| 71 | CONFIG_TCP_CONG_ADVANCED=y | 70 | CONFIG_TCP_CONG_ADVANCED=y |
| 72 | CONFIG_TCP_CONG_BIC=y | 71 | CONFIG_TCP_CONG_BIC=y |
| 73 | CONFIG_DEFAULT_BIC=y | 72 | CONFIG_DEFAULT_BIC=y |
| 74 | CONFIG_TCP_MD5SIG=y | 73 | CONFIG_TCP_MD5SIG=y |
| 75 | CONFIG_IPV6_PRIVACY=y | 74 | CONFIG_IPV6_PRIVACY=y |
| 76 | CONFIG_IPV6_ROUTER_PREF=y | 75 | CONFIG_IPV6_ROUTER_PREF=y |
| 77 | CONFIG_IPV6_TUNNEL=m | 76 | CONFIG_IPV6_TUNNEL=m |
| 78 | CONFIG_IPV6_MULTIPLE_TABLES=y | 77 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 79 | CONFIG_IPV6_SUBTREES=y | 78 | CONFIG_IPV6_SUBTREES=y |
| 80 | CONFIG_NETWORK_SECMARK=y | 79 | CONFIG_NETWORK_SECMARK=y |
| 81 | CONFIG_NETFILTER=y | 80 | CONFIG_NETFILTER=y |
| 82 | CONFIG_BRIDGE=m | 81 | CONFIG_BRIDGE=m |
| 83 | CONFIG_VLAN_8021Q=m | 82 | CONFIG_VLAN_8021Q=m |
| 84 | CONFIG_IPX=m | 83 | CONFIG_IPX=m |
| 85 | CONFIG_NET_SCHED=y | 84 | CONFIG_NET_SCHED=y |
| 86 | CONFIG_NET_EMATCH=y | 85 | CONFIG_NET_EMATCH=y |
| 87 | CONFIG_NET_CLS_ACT=y | 86 | CONFIG_NET_CLS_ACT=y |
| 88 | CONFIG_BT=m | 87 | CONFIG_BT=m |
| 89 | CONFIG_BT_L2CAP=y | 88 | CONFIG_BT_L2CAP=y |
| 90 | CONFIG_BT_SCO=y | 89 | CONFIG_BT_SCO=y |
| 91 | CONFIG_BT_RFCOMM=m | 90 | CONFIG_BT_RFCOMM=m |
| 92 | CONFIG_BT_RFCOMM_TTY=y | 91 | CONFIG_BT_RFCOMM_TTY=y |
| 93 | CONFIG_BT_BNEP=m | 92 | CONFIG_BT_BNEP=m |
| 94 | CONFIG_BT_BNEP_MC_FILTER=y | 93 | CONFIG_BT_BNEP_MC_FILTER=y |
| 95 | CONFIG_BT_BNEP_PROTO_FILTER=y | 94 | CONFIG_BT_BNEP_PROTO_FILTER=y |
| 96 | CONFIG_BT_HIDP=m | 95 | CONFIG_BT_HIDP=m |
| 97 | CONFIG_BT_HCIBTUSB=m | 96 | CONFIG_BT_HCIBTUSB=m |
| 98 | CONFIG_BT_HCIBFUSB=m | 97 | CONFIG_BT_HCIBFUSB=m |
| 99 | CONFIG_BT_HCIVHCI=m | 98 | CONFIG_BT_HCIVHCI=m |
| 100 | CONFIG_CFG80211=m | 99 | CONFIG_CFG80211=m |
| 101 | CONFIG_LIB80211=m | 100 | CONFIG_LIB80211=m |
| 102 | CONFIG_LIB80211_DEBUG=y | 101 | CONFIG_LIB80211_DEBUG=y |
| 103 | CONFIG_MAC80211=m | 102 | CONFIG_MAC80211=m |
| 104 | CONFIG_MAC80211_LEDS=y | 103 | CONFIG_MAC80211_LEDS=y |
| 105 | CONFIG_RFKILL=m | 104 | CONFIG_RFKILL=m |
| 106 | CONFIG_RFKILL_INPUT=y | 105 | CONFIG_RFKILL_INPUT=y |
| 107 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 106 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 108 | CONFIG_BLK_DEV_LOOP=y | 107 | CONFIG_BLK_DEV_LOOP=y |
| 109 | CONFIG_BLK_DEV_CRYPTOLOOP=m | 108 | CONFIG_BLK_DEV_CRYPTOLOOP=m |
| 110 | CONFIG_BLK_DEV_RAM=y | 109 | CONFIG_BLK_DEV_RAM=y |
| 111 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 110 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 112 | # CONFIG_MISC_DEVICES is not set | 111 | # CONFIG_MISC_DEVICES is not set |
| 113 | CONFIG_IDE=y | 112 | CONFIG_IDE=y |
| 114 | CONFIG_IDE_TASK_IOCTL=y | 113 | CONFIG_IDE_TASK_IOCTL=y |
| 115 | # CONFIG_IDEPCI_PCIBUS_ORDER is not set | 114 | # CONFIG_IDEPCI_PCIBUS_ORDER is not set |
| 116 | CONFIG_BLK_DEV_AMD74XX=y | 115 | CONFIG_BLK_DEV_AMD74XX=y |
| 117 | CONFIG_SCSI=m | 116 | CONFIG_SCSI=m |
| 118 | CONFIG_BLK_DEV_SD=m | 117 | CONFIG_BLK_DEV_SD=m |
| 119 | CONFIG_CHR_DEV_SG=m | 118 | CONFIG_CHR_DEV_SG=m |
| 120 | CONFIG_SCSI_MULTI_LUN=y | 119 | CONFIG_SCSI_MULTI_LUN=y |
| 121 | # CONFIG_SCSI_LOWLEVEL is not set | 120 | # CONFIG_SCSI_LOWLEVEL is not set |
| 122 | CONFIG_MD=y | 121 | CONFIG_MD=y |
| 123 | CONFIG_BLK_DEV_MD=m | 122 | CONFIG_BLK_DEV_MD=m |
| 124 | CONFIG_MD_LINEAR=m | 123 | CONFIG_MD_LINEAR=m |
| 125 | CONFIG_MD_RAID0=m | 124 | CONFIG_MD_RAID0=m |
| 126 | CONFIG_MD_RAID1=m | 125 | CONFIG_MD_RAID1=m |
| 127 | CONFIG_MD_RAID10=m | 126 | CONFIG_MD_RAID10=m |
| 128 | CONFIG_MD_RAID456=m | 127 | CONFIG_MD_RAID456=m |
| 129 | CONFIG_MD_MULTIPATH=m | 128 | CONFIG_MD_MULTIPATH=m |
| 130 | CONFIG_MD_FAULTY=m | 129 | CONFIG_MD_FAULTY=m |
| 131 | CONFIG_BLK_DEV_DM=m | 130 | CONFIG_BLK_DEV_DM=m |
| 132 | CONFIG_DM_DEBUG=y | 131 | CONFIG_DM_DEBUG=y |
| 133 | CONFIG_DM_CRYPT=m | 132 | CONFIG_DM_CRYPT=m |
| 134 | CONFIG_DM_SNAPSHOT=m | 133 | CONFIG_DM_SNAPSHOT=m |
| 135 | CONFIG_DM_MIRROR=m | 134 | CONFIG_DM_MIRROR=m |
| 136 | CONFIG_DM_LOG_USERSPACE=m | 135 | CONFIG_DM_LOG_USERSPACE=m |
| 137 | CONFIG_DM_ZERO=m | 136 | CONFIG_DM_ZERO=m |
| 138 | CONFIG_DM_MULTIPATH=m | 137 | CONFIG_DM_MULTIPATH=m |
| 139 | CONFIG_DM_MULTIPATH_QL=m | 138 | CONFIG_DM_MULTIPATH_QL=m |
| 140 | CONFIG_DM_MULTIPATH_ST=m | 139 | CONFIG_DM_MULTIPATH_ST=m |
| 141 | CONFIG_DM_DELAY=m | 140 | CONFIG_DM_DELAY=m |
| 142 | CONFIG_DM_UEVENT=y | 141 | CONFIG_DM_UEVENT=y |
| 143 | CONFIG_NETDEVICES=y | 142 | CONFIG_NETDEVICES=y |
| 144 | CONFIG_DUMMY=m | 143 | CONFIG_DUMMY=m |
| 145 | CONFIG_TUN=m | 144 | CONFIG_TUN=m |
| 146 | CONFIG_VETH=m | 145 | CONFIG_VETH=m |
| 147 | CONFIG_NET_ETHERNET=y | 146 | CONFIG_NET_ETHERNET=y |
| 148 | CONFIG_NET_PCI=y | 147 | CONFIG_NET_PCI=y |
| 149 | CONFIG_8139TOO=y | 148 | CONFIG_8139TOO=y |
| 150 | # CONFIG_8139TOO_PIO is not set | 149 | # CONFIG_8139TOO_PIO is not set |
| 151 | CONFIG_R8169=y | 150 | CONFIG_R8169=y |
| 152 | CONFIG_R8169_VLAN=y | 151 | CONFIG_R8169_VLAN=y |
| 153 | # CONFIG_NETDEV_10000 is not set | 152 | # CONFIG_NETDEV_10000 is not set |
| 154 | CONFIG_USB_USBNET=m | 153 | CONFIG_USB_USBNET=m |
| 155 | CONFIG_USB_NET_CDC_EEM=m | 154 | CONFIG_USB_NET_CDC_EEM=m |
| 156 | CONFIG_NETCONSOLE=m | 155 | CONFIG_NETCONSOLE=m |
| 157 | CONFIG_NETCONSOLE_DYNAMIC=y | 156 | CONFIG_NETCONSOLE_DYNAMIC=y |
| 158 | CONFIG_INPUT_POLLDEV=m | 157 | CONFIG_INPUT_POLLDEV=m |
| 159 | CONFIG_INPUT_EVDEV=y | 158 | CONFIG_INPUT_EVDEV=y |
| 160 | # CONFIG_MOUSE_PS2_ALPS is not set | 159 | # CONFIG_MOUSE_PS2_ALPS is not set |
| 161 | # CONFIG_MOUSE_PS2_LOGIPS2PP is not set | 160 | # CONFIG_MOUSE_PS2_LOGIPS2PP is not set |
| 162 | # CONFIG_MOUSE_PS2_TRACKPOINT is not set | 161 | # CONFIG_MOUSE_PS2_TRACKPOINT is not set |
| 163 | CONFIG_MOUSE_APPLETOUCH=m | 162 | CONFIG_MOUSE_APPLETOUCH=m |
| 164 | # CONFIG_SERIO_SERPORT is not set | 163 | # CONFIG_SERIO_SERPORT is not set |
| 165 | CONFIG_SERIAL_NONSTANDARD=y | 164 | CONFIG_SERIAL_NONSTANDARD=y |
| 166 | CONFIG_SERIAL_8250=m | 165 | CONFIG_SERIAL_8250=m |
| 167 | # CONFIG_SERIAL_8250_PCI is not set | 166 | # CONFIG_SERIAL_8250_PCI is not set |
| 168 | CONFIG_SERIAL_8250_NR_UARTS=16 | 167 | CONFIG_SERIAL_8250_NR_UARTS=16 |
| 169 | CONFIG_SERIAL_8250_EXTENDED=y | 168 | CONFIG_SERIAL_8250_EXTENDED=y |
| 170 | CONFIG_SERIAL_8250_MANY_PORTS=y | 169 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 171 | CONFIG_SERIAL_8250_FOURPORT=y | 170 | CONFIG_SERIAL_8250_FOURPORT=y |
| 172 | CONFIG_LEGACY_PTY_COUNT=16 | 171 | CONFIG_LEGACY_PTY_COUNT=16 |
| 173 | CONFIG_HW_RANDOM=y | 172 | CONFIG_HW_RANDOM=y |
| 174 | CONFIG_RTC=y | 173 | CONFIG_RTC=y |
| 175 | CONFIG_THERMAL=y | 174 | CONFIG_THERMAL=y |
| 176 | CONFIG_MEDIA_SUPPORT=m | 175 | CONFIG_MEDIA_SUPPORT=m |
| 177 | CONFIG_VIDEO_DEV=m | 176 | CONFIG_VIDEO_DEV=m |
| 178 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | 177 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y |
| 179 | CONFIG_VIDEO_VIVI=m | 178 | CONFIG_VIDEO_VIVI=m |
| 180 | CONFIG_USB_VIDEO_CLASS=m | 179 | CONFIG_USB_VIDEO_CLASS=m |
| 181 | CONFIG_USB_M5602=m | 180 | CONFIG_USB_M5602=m |
| 182 | CONFIG_USB_STV06XX=m | 181 | CONFIG_USB_STV06XX=m |
| 183 | CONFIG_USB_GSPCA_CONEX=m | 182 | CONFIG_USB_GSPCA_CONEX=m |
| 184 | CONFIG_USB_GSPCA_ETOMS=m | 183 | CONFIG_USB_GSPCA_ETOMS=m |
| 185 | CONFIG_USB_GSPCA_FINEPIX=m | 184 | CONFIG_USB_GSPCA_FINEPIX=m |
| 186 | CONFIG_USB_GSPCA_MARS=m | 185 | CONFIG_USB_GSPCA_MARS=m |
| 187 | CONFIG_USB_GSPCA_MR97310A=m | 186 | CONFIG_USB_GSPCA_MR97310A=m |
| 188 | CONFIG_USB_GSPCA_OV519=m | 187 | CONFIG_USB_GSPCA_OV519=m |
| 189 | CONFIG_USB_GSPCA_OV534=m | 188 | CONFIG_USB_GSPCA_OV534=m |
| 190 | CONFIG_USB_GSPCA_PAC207=m | 189 | CONFIG_USB_GSPCA_PAC207=m |
| 191 | CONFIG_USB_GSPCA_PAC7311=m | 190 | CONFIG_USB_GSPCA_PAC7311=m |
| 192 | CONFIG_USB_GSPCA_SN9C20X=m | 191 | CONFIG_USB_GSPCA_SN9C20X=m |
| 193 | CONFIG_USB_GSPCA_SONIXB=m | 192 | CONFIG_USB_GSPCA_SONIXB=m |
| 194 | CONFIG_USB_GSPCA_SONIXJ=m | 193 | CONFIG_USB_GSPCA_SONIXJ=m |
| 195 | CONFIG_USB_GSPCA_SPCA500=m | 194 | CONFIG_USB_GSPCA_SPCA500=m |
| 196 | CONFIG_USB_GSPCA_SPCA501=m | 195 | CONFIG_USB_GSPCA_SPCA501=m |
| 197 | CONFIG_USB_GSPCA_SPCA505=m | 196 | CONFIG_USB_GSPCA_SPCA505=m |
| 198 | CONFIG_USB_GSPCA_SPCA506=m | 197 | CONFIG_USB_GSPCA_SPCA506=m |
| 199 | CONFIG_USB_GSPCA_SPCA508=m | 198 | CONFIG_USB_GSPCA_SPCA508=m |
| 200 | CONFIG_USB_GSPCA_SPCA561=m | 199 | CONFIG_USB_GSPCA_SPCA561=m |
| 201 | CONFIG_USB_GSPCA_SQ905=m | 200 | CONFIG_USB_GSPCA_SQ905=m |
| 202 | CONFIG_USB_GSPCA_SQ905C=m | 201 | CONFIG_USB_GSPCA_SQ905C=m |
| 203 | CONFIG_USB_GSPCA_STK014=m | 202 | CONFIG_USB_GSPCA_STK014=m |
| 204 | CONFIG_USB_GSPCA_SUNPLUS=m | 203 | CONFIG_USB_GSPCA_SUNPLUS=m |
| 205 | CONFIG_USB_GSPCA_T613=m | 204 | CONFIG_USB_GSPCA_T613=m |
| 206 | CONFIG_USB_GSPCA_TV8532=m | 205 | CONFIG_USB_GSPCA_TV8532=m |
| 207 | CONFIG_USB_GSPCA_VC032X=m | 206 | CONFIG_USB_GSPCA_VC032X=m |
| 208 | CONFIG_USB_GSPCA_ZC3XX=m | 207 | CONFIG_USB_GSPCA_ZC3XX=m |
| 209 | CONFIG_USB_ET61X251=m | 208 | CONFIG_USB_ET61X251=m |
| 210 | CONFIG_USB_SN9C102=m | 209 | CONFIG_USB_SN9C102=m |
| 211 | CONFIG_USB_ZR364XX=m | 210 | CONFIG_USB_ZR364XX=m |
| 212 | CONFIG_USB_STKWEBCAM=m | 211 | CONFIG_USB_STKWEBCAM=m |
| 213 | CONFIG_USB_S2255=m | 212 | CONFIG_USB_S2255=m |
| 214 | # CONFIG_RADIO_ADAPTERS is not set | 213 | # CONFIG_RADIO_ADAPTERS is not set |
| 215 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 214 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 216 | CONFIG_FB=y | 215 | CONFIG_FB=y |
| 217 | CONFIG_FIRMWARE_EDID=y | 216 | CONFIG_FIRMWARE_EDID=y |
| 218 | CONFIG_FB_MODE_HELPERS=y | 217 | CONFIG_FB_MODE_HELPERS=y |
| 219 | CONFIG_FB_TILEBLITTING=y | 218 | CONFIG_FB_TILEBLITTING=y |
| 220 | CONFIG_FB_SIS=y | 219 | CONFIG_FB_SIS=y |
| 221 | CONFIG_FB_SIS_300=y | 220 | CONFIG_FB_SIS_300=y |
| 222 | CONFIG_FB_SIS_315=y | 221 | CONFIG_FB_SIS_315=y |
| 223 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 222 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 224 | # CONFIG_LCD_CLASS_DEVICE is not set | 223 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 225 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 224 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 226 | CONFIG_BACKLIGHT_GENERIC=m | 225 | CONFIG_BACKLIGHT_GENERIC=m |
| 227 | # CONFIG_VGA_CONSOLE is not set | 226 | # CONFIG_VGA_CONSOLE is not set |
| 228 | CONFIG_FRAMEBUFFER_CONSOLE=y | 227 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 229 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | 228 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y |
| 230 | CONFIG_FONTS=y | 229 | CONFIG_FONTS=y |
| 231 | CONFIG_FONT_8x8=y | 230 | CONFIG_FONT_8x8=y |
| 232 | CONFIG_FONT_6x11=y | 231 | CONFIG_FONT_6x11=y |
| 233 | CONFIG_FONT_7x14=y | 232 | CONFIG_FONT_7x14=y |
| 234 | CONFIG_FONT_PEARL_8x8=y | 233 | CONFIG_FONT_PEARL_8x8=y |
| 235 | CONFIG_FONT_ACORN_8x8=y | 234 | CONFIG_FONT_ACORN_8x8=y |
| 236 | CONFIG_FONT_MINI_4x6=y | 235 | CONFIG_FONT_MINI_4x6=y |
| 237 | CONFIG_FONT_SUN8x16=y | 236 | CONFIG_FONT_SUN8x16=y |
| 238 | CONFIG_FONT_SUN12x22=y | 237 | CONFIG_FONT_SUN12x22=y |
| 239 | CONFIG_FONT_10x18=y | 238 | CONFIG_FONT_10x18=y |
| 240 | CONFIG_LOGO=y | 239 | CONFIG_LOGO=y |
| 241 | # CONFIG_LOGO_LINUX_MONO is not set | 240 | # CONFIG_LOGO_LINUX_MONO is not set |
| 242 | # CONFIG_LOGO_LINUX_VGA16 is not set | 241 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 243 | CONFIG_SOUND=m | 242 | CONFIG_SOUND=m |
| 244 | CONFIG_SND=m | 243 | CONFIG_SND=m |
| 245 | CONFIG_SND_SEQUENCER=m | 244 | CONFIG_SND_SEQUENCER=m |
| 246 | CONFIG_SND_SEQ_DUMMY=m | 245 | CONFIG_SND_SEQ_DUMMY=m |
| 247 | CONFIG_SND_MIXER_OSS=m | 246 | CONFIG_SND_MIXER_OSS=m |
| 248 | CONFIG_SND_PCM_OSS=m | 247 | CONFIG_SND_PCM_OSS=m |
| 249 | CONFIG_SND_SEQUENCER_OSS=y | 248 | CONFIG_SND_SEQUENCER_OSS=y |
| 250 | CONFIG_SND_HRTIMER=m | 249 | CONFIG_SND_HRTIMER=m |
| 251 | CONFIG_SND_DUMMY=m | 250 | CONFIG_SND_DUMMY=m |
| 252 | CONFIG_SND_VIRMIDI=m | 251 | CONFIG_SND_VIRMIDI=m |
| 253 | CONFIG_SND_SERIAL_U16550=m | 252 | CONFIG_SND_SERIAL_U16550=m |
| 254 | CONFIG_SND_MPU401=m | 253 | CONFIG_SND_MPU401=m |
| 255 | CONFIG_SND_AC97_POWER_SAVE=y | 254 | CONFIG_SND_AC97_POWER_SAVE=y |
| 256 | CONFIG_SND_AC97_POWER_SAVE_DEFAULT=10 | 255 | CONFIG_SND_AC97_POWER_SAVE_DEFAULT=10 |
| 257 | CONFIG_SND_CS5535AUDIO=m | 256 | CONFIG_SND_CS5535AUDIO=m |
| 258 | # CONFIG_SND_MIPS is not set | 257 | # CONFIG_SND_MIPS is not set |
| 259 | CONFIG_SND_USB_AUDIO=m | 258 | CONFIG_SND_USB_AUDIO=m |
| 260 | CONFIG_SND_USB_CAIAQ=m | 259 | CONFIG_SND_USB_CAIAQ=m |
| 261 | CONFIG_SND_USB_CAIAQ_INPUT=y | 260 | CONFIG_SND_USB_CAIAQ_INPUT=y |
| 262 | CONFIG_HIDRAW=y | 261 | CONFIG_HIDRAW=y |
| 263 | CONFIG_USB_HIDDEV=y | 262 | CONFIG_USB_HIDDEV=y |
| 264 | CONFIG_HID_A4TECH=m | 263 | CONFIG_HID_A4TECH=m |
| 265 | CONFIG_HID_APPLE=m | 264 | CONFIG_HID_APPLE=m |
| 266 | CONFIG_HID_BELKIN=m | 265 | CONFIG_HID_BELKIN=m |
| 267 | CONFIG_HID_CHERRY=m | 266 | CONFIG_HID_CHERRY=m |
| 268 | CONFIG_HID_CHICONY=m | 267 | CONFIG_HID_CHICONY=m |
| 269 | CONFIG_HID_CYPRESS=m | 268 | CONFIG_HID_CYPRESS=m |
| 270 | CONFIG_HID_DRAGONRISE=m | 269 | CONFIG_HID_DRAGONRISE=m |
| 271 | CONFIG_DRAGONRISE_FF=y | 270 | CONFIG_DRAGONRISE_FF=y |
| 272 | CONFIG_HID_EZKEY=m | 271 | CONFIG_HID_EZKEY=m |
| 273 | CONFIG_HID_KYE=m | 272 | CONFIG_HID_KYE=m |
| 274 | CONFIG_HID_GYRATION=m | 273 | CONFIG_HID_GYRATION=m |
| 275 | CONFIG_HID_TWINHAN=m | 274 | CONFIG_HID_TWINHAN=m |
| 276 | CONFIG_HID_KENSINGTON=m | 275 | CONFIG_HID_KENSINGTON=m |
| 277 | CONFIG_HID_LOGITECH=m | 276 | CONFIG_HID_LOGITECH=m |
| 278 | CONFIG_LOGITECH_FF=y | 277 | CONFIG_LOGITECH_FF=y |
| 279 | CONFIG_LOGIRUMBLEPAD2_FF=y | 278 | CONFIG_LOGIRUMBLEPAD2_FF=y |
| 280 | CONFIG_HID_MICROSOFT=m | 279 | CONFIG_HID_MICROSOFT=m |
| 281 | CONFIG_HID_MONTEREY=m | 280 | CONFIG_HID_MONTEREY=m |
| 282 | CONFIG_HID_NTRIG=m | 281 | CONFIG_HID_NTRIG=m |
| 283 | CONFIG_HID_PANTHERLORD=m | 282 | CONFIG_HID_PANTHERLORD=m |
| 284 | CONFIG_PANTHERLORD_FF=y | 283 | CONFIG_PANTHERLORD_FF=y |
| 285 | CONFIG_HID_PETALYNX=m | 284 | CONFIG_HID_PETALYNX=m |
| 286 | CONFIG_HID_SAMSUNG=m | 285 | CONFIG_HID_SAMSUNG=m |
| 287 | CONFIG_HID_SONY=m | 286 | CONFIG_HID_SONY=m |
| 288 | CONFIG_HID_SUNPLUS=m | 287 | CONFIG_HID_SUNPLUS=m |
| 289 | CONFIG_HID_GREENASIA=m | 288 | CONFIG_HID_GREENASIA=m |
| 290 | CONFIG_GREENASIA_FF=y | 289 | CONFIG_GREENASIA_FF=y |
| 291 | CONFIG_HID_SMARTJOYPLUS=m | 290 | CONFIG_HID_SMARTJOYPLUS=m |
| 292 | CONFIG_SMARTJOYPLUS_FF=y | 291 | CONFIG_SMARTJOYPLUS_FF=y |
| 293 | CONFIG_HID_TOPSEED=m | 292 | CONFIG_HID_TOPSEED=m |
| 294 | CONFIG_HID_THRUSTMASTER=m | 293 | CONFIG_HID_THRUSTMASTER=m |
| 295 | CONFIG_THRUSTMASTER_FF=y | 294 | CONFIG_THRUSTMASTER_FF=y |
| 296 | CONFIG_HID_WACOM=m | 295 | CONFIG_HID_WACOM=m |
| 297 | CONFIG_HID_ZEROPLUS=m | 296 | CONFIG_HID_ZEROPLUS=m |
| 298 | CONFIG_ZEROPLUS_FF=y | 297 | CONFIG_ZEROPLUS_FF=y |
| 299 | CONFIG_USB=y | 298 | CONFIG_USB=y |
| 300 | # CONFIG_USB_DEVICE_CLASS is not set | 299 | # CONFIG_USB_DEVICE_CLASS is not set |
| 301 | CONFIG_USB_DYNAMIC_MINORS=y | 300 | CONFIG_USB_DYNAMIC_MINORS=y |
| 302 | CONFIG_USB_OTG_WHITELIST=y | 301 | CONFIG_USB_OTG_WHITELIST=y |
| 303 | CONFIG_USB_MON=y | 302 | CONFIG_USB_MON=y |
| 304 | CONFIG_USB_EHCI_HCD=y | 303 | CONFIG_USB_EHCI_HCD=y |
| 305 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | 304 | CONFIG_USB_EHCI_ROOT_HUB_TT=y |
| 306 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | 305 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set |
| 307 | CONFIG_USB_OHCI_HCD=y | 306 | CONFIG_USB_OHCI_HCD=y |
| 308 | CONFIG_USB_UHCI_HCD=m | 307 | CONFIG_USB_UHCI_HCD=m |
| 309 | CONFIG_USB_WHCI_HCD=m | 308 | CONFIG_USB_WHCI_HCD=m |
| 310 | CONFIG_USB_HWA_HCD=m | 309 | CONFIG_USB_HWA_HCD=m |
| 311 | CONFIG_USB_ACM=m | 310 | CONFIG_USB_ACM=m |
| 312 | CONFIG_USB_PRINTER=m | 311 | CONFIG_USB_PRINTER=m |
| 313 | CONFIG_USB_WDM=m | 312 | CONFIG_USB_WDM=m |
| 314 | CONFIG_USB_STORAGE=m | 313 | CONFIG_USB_STORAGE=m |
| 315 | CONFIG_USB_STORAGE_DATAFAB=m | 314 | CONFIG_USB_STORAGE_DATAFAB=m |
| 316 | CONFIG_USB_STORAGE_FREECOM=m | 315 | CONFIG_USB_STORAGE_FREECOM=m |
| 317 | CONFIG_USB_STORAGE_ISD200=m | 316 | CONFIG_USB_STORAGE_ISD200=m |
| 318 | CONFIG_USB_STORAGE_USBAT=m | 317 | CONFIG_USB_STORAGE_USBAT=m |
| 319 | CONFIG_USB_STORAGE_SDDR09=m | 318 | CONFIG_USB_STORAGE_SDDR09=m |
| 320 | CONFIG_USB_STORAGE_SDDR55=m | 319 | CONFIG_USB_STORAGE_SDDR55=m |
| 321 | CONFIG_USB_STORAGE_JUMPSHOT=m | 320 | CONFIG_USB_STORAGE_JUMPSHOT=m |
| 322 | CONFIG_USB_STORAGE_ALAUDA=m | 321 | CONFIG_USB_STORAGE_ALAUDA=m |
| 323 | CONFIG_USB_LIBUSUAL=y | 322 | CONFIG_USB_LIBUSUAL=y |
| 324 | CONFIG_USB_SERIAL=m | 323 | CONFIG_USB_SERIAL=m |
| 325 | CONFIG_USB_SERIAL_GENERIC=y | 324 | CONFIG_USB_SERIAL_GENERIC=y |
| 326 | CONFIG_USB_LED=m | 325 | CONFIG_USB_LED=m |
| 327 | CONFIG_USB_GADGET=m | 326 | CONFIG_USB_GADGET=m |
| 328 | CONFIG_USB_GADGET_M66592=y | 327 | CONFIG_USB_GADGET_M66592=y |
| 329 | CONFIG_MMC=m | 328 | CONFIG_MMC=m |
| 330 | CONFIG_LEDS_CLASS=y | 329 | CONFIG_LEDS_CLASS=y |
| 331 | CONFIG_STAGING=y | 330 | CONFIG_STAGING=y |
| 332 | # CONFIG_STAGING_EXCLUDE_BUILD is not set | 331 | # CONFIG_STAGING_EXCLUDE_BUILD is not set |
| 333 | CONFIG_FB_SM7XX=y | 332 | CONFIG_FB_SM7XX=y |
| 334 | CONFIG_EXT2_FS=m | 333 | CONFIG_EXT2_FS=m |
| 335 | CONFIG_EXT3_FS=y | 334 | CONFIG_EXT3_FS=y |
| 336 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 335 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 337 | CONFIG_EXT3_FS_POSIX_ACL=y | 336 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 338 | CONFIG_EXT3_FS_SECURITY=y | 337 | CONFIG_EXT3_FS_SECURITY=y |
| 339 | CONFIG_EXT4_FS=y | 338 | CONFIG_EXT4_FS=y |
| 340 | CONFIG_REISERFS_FS=m | 339 | CONFIG_REISERFS_FS=m |
| 341 | CONFIG_REISERFS_PROC_INFO=y | 340 | CONFIG_REISERFS_PROC_INFO=y |
| 342 | CONFIG_REISERFS_FS_XATTR=y | 341 | CONFIG_REISERFS_FS_XATTR=y |
| 343 | CONFIG_JFS_FS=m | 342 | CONFIG_JFS_FS=m |
| 344 | CONFIG_JFS_POSIX_ACL=y | 343 | CONFIG_JFS_POSIX_ACL=y |
| 345 | CONFIG_XFS_FS=m | 344 | CONFIG_XFS_FS=m |
| 346 | CONFIG_XFS_QUOTA=y | 345 | CONFIG_XFS_QUOTA=y |
| 347 | CONFIG_XFS_POSIX_ACL=y | 346 | CONFIG_XFS_POSIX_ACL=y |
| 348 | CONFIG_BTRFS_FS=m | 347 | CONFIG_BTRFS_FS=m |
| 349 | CONFIG_QUOTA=y | 348 | CONFIG_QUOTA=y |
| 350 | CONFIG_QFMT_V2=m | 349 | CONFIG_QFMT_V2=m |
| 351 | CONFIG_AUTOFS_FS=m | 350 | CONFIG_AUTOFS_FS=m |
| 352 | CONFIG_AUTOFS4_FS=m | 351 | CONFIG_AUTOFS4_FS=m |
| 353 | CONFIG_FSCACHE=m | 352 | CONFIG_FSCACHE=m |
| 354 | CONFIG_CACHEFILES=m | 353 | CONFIG_CACHEFILES=m |
| 355 | CONFIG_ISO9660_FS=m | 354 | CONFIG_ISO9660_FS=m |
| 356 | CONFIG_JOLIET=y | 355 | CONFIG_JOLIET=y |
| 357 | CONFIG_ZISOFS=y | 356 | CONFIG_ZISOFS=y |
| 358 | CONFIG_MSDOS_FS=m | 357 | CONFIG_MSDOS_FS=m |
| 359 | CONFIG_VFAT_FS=m | 358 | CONFIG_VFAT_FS=m |
| 360 | CONFIG_NTFS_FS=m | 359 | CONFIG_NTFS_FS=m |
| 361 | CONFIG_NTFS_RW=y | 360 | CONFIG_NTFS_RW=y |
| 362 | CONFIG_PROC_KCORE=y | 361 | CONFIG_PROC_KCORE=y |
| 363 | CONFIG_TMPFS=y | 362 | CONFIG_TMPFS=y |
| 364 | CONFIG_CRAMFS=m | 363 | CONFIG_CRAMFS=m |
| 365 | CONFIG_SQUASHFS=m | 364 | CONFIG_SQUASHFS=m |
| 366 | CONFIG_SQUASHFS_EMBEDDED=y | 365 | CONFIG_SQUASHFS_EMBEDDED=y |
| 367 | CONFIG_ROMFS_FS=m | 366 | CONFIG_ROMFS_FS=m |
| 368 | CONFIG_NFS_FS=m | 367 | CONFIG_NFS_FS=m |
| 369 | CONFIG_NFS_V3=y | 368 | CONFIG_NFS_V3=y |
| 370 | CONFIG_NFS_V3_ACL=y | 369 | CONFIG_NFS_V3_ACL=y |
| 371 | CONFIG_NFSD=m | 370 | CONFIG_NFSD=m |
| 372 | CONFIG_NFSD_V4=y | 371 | CONFIG_NFSD_V4=y |
| 373 | CONFIG_CIFS=m | 372 | CONFIG_CIFS=m |
| 374 | CONFIG_NLS_DEFAULT="utf8" | 373 | CONFIG_NLS_DEFAULT="utf8" |
| 375 | CONFIG_NLS_CODEPAGE_437=m | 374 | CONFIG_NLS_CODEPAGE_437=m |
| 376 | CONFIG_NLS_CODEPAGE_737=m | 375 | CONFIG_NLS_CODEPAGE_737=m |
| 377 | CONFIG_NLS_CODEPAGE_775=m | 376 | CONFIG_NLS_CODEPAGE_775=m |
| 378 | CONFIG_NLS_CODEPAGE_850=m | 377 | CONFIG_NLS_CODEPAGE_850=m |
| 379 | CONFIG_NLS_CODEPAGE_852=m | 378 | CONFIG_NLS_CODEPAGE_852=m |
| 380 | CONFIG_NLS_CODEPAGE_855=m | 379 | CONFIG_NLS_CODEPAGE_855=m |
| 381 | CONFIG_NLS_CODEPAGE_857=m | 380 | CONFIG_NLS_CODEPAGE_857=m |
| 382 | CONFIG_NLS_CODEPAGE_860=m | 381 | CONFIG_NLS_CODEPAGE_860=m |
| 383 | CONFIG_NLS_CODEPAGE_861=m | 382 | CONFIG_NLS_CODEPAGE_861=m |
| 384 | CONFIG_NLS_CODEPAGE_862=m | 383 | CONFIG_NLS_CODEPAGE_862=m |
| 385 | CONFIG_NLS_CODEPAGE_863=m | 384 | CONFIG_NLS_CODEPAGE_863=m |
| 386 | CONFIG_NLS_CODEPAGE_864=m | 385 | CONFIG_NLS_CODEPAGE_864=m |
| 387 | CONFIG_NLS_CODEPAGE_865=m | 386 | CONFIG_NLS_CODEPAGE_865=m |
| 388 | CONFIG_NLS_CODEPAGE_866=m | 387 | CONFIG_NLS_CODEPAGE_866=m |
| 389 | CONFIG_NLS_CODEPAGE_869=m | 388 | CONFIG_NLS_CODEPAGE_869=m |
| 390 | CONFIG_NLS_CODEPAGE_936=m | 389 | CONFIG_NLS_CODEPAGE_936=m |
| 391 | CONFIG_NLS_CODEPAGE_950=m | 390 | CONFIG_NLS_CODEPAGE_950=m |
| 392 | CONFIG_NLS_CODEPAGE_932=m | 391 | CONFIG_NLS_CODEPAGE_932=m |
| 393 | CONFIG_NLS_CODEPAGE_949=m | 392 | CONFIG_NLS_CODEPAGE_949=m |
| 394 | CONFIG_NLS_CODEPAGE_874=m | 393 | CONFIG_NLS_CODEPAGE_874=m |
| 395 | CONFIG_NLS_ISO8859_8=m | 394 | CONFIG_NLS_ISO8859_8=m |
| 396 | CONFIG_NLS_CODEPAGE_1250=m | 395 | CONFIG_NLS_CODEPAGE_1250=m |
| 397 | CONFIG_NLS_CODEPAGE_1251=m | 396 | CONFIG_NLS_CODEPAGE_1251=m |
| 398 | CONFIG_NLS_ASCII=m | 397 | CONFIG_NLS_ASCII=m |
| 399 | CONFIG_NLS_ISO8859_1=m | 398 | CONFIG_NLS_ISO8859_1=m |
| 400 | CONFIG_NLS_ISO8859_2=m | 399 | CONFIG_NLS_ISO8859_2=m |
| 401 | CONFIG_NLS_ISO8859_3=m | 400 | CONFIG_NLS_ISO8859_3=m |
| 402 | CONFIG_NLS_ISO8859_4=m | 401 | CONFIG_NLS_ISO8859_4=m |
| 403 | CONFIG_NLS_ISO8859_5=m | 402 | CONFIG_NLS_ISO8859_5=m |
| 404 | CONFIG_NLS_ISO8859_6=m | 403 | CONFIG_NLS_ISO8859_6=m |
| 405 | CONFIG_NLS_ISO8859_7=m | 404 | CONFIG_NLS_ISO8859_7=m |
| 406 | CONFIG_NLS_ISO8859_9=m | 405 | CONFIG_NLS_ISO8859_9=m |
| 407 | CONFIG_NLS_ISO8859_13=m | 406 | CONFIG_NLS_ISO8859_13=m |
| 408 | CONFIG_NLS_ISO8859_14=m | 407 | CONFIG_NLS_ISO8859_14=m |
| 409 | CONFIG_NLS_ISO8859_15=m | 408 | CONFIG_NLS_ISO8859_15=m |
| 410 | CONFIG_NLS_KOI8_R=m | 409 | CONFIG_NLS_KOI8_R=m |
| 411 | CONFIG_NLS_KOI8_U=m | 410 | CONFIG_NLS_KOI8_U=m |
| 412 | CONFIG_NLS_UTF8=y | 411 | CONFIG_NLS_UTF8=y |
| 413 | CONFIG_PRINTK_TIME=y | 412 | CONFIG_PRINTK_TIME=y |
| 414 | CONFIG_FRAME_WARN=1024 | 413 | CONFIG_FRAME_WARN=1024 |
| 415 | CONFIG_STRIP_ASM_SYMS=y | 414 | CONFIG_STRIP_ASM_SYMS=y |
| 416 | CONFIG_DEBUG_FS=y | 415 | CONFIG_DEBUG_FS=y |
| 417 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 416 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 418 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 417 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 419 | CONFIG_KEYS=y | 418 | CONFIG_KEYS=y |
| 420 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | 419 | CONFIG_KEYS_DEBUG_PROC_KEYS=y |
| 421 | CONFIG_CRYPTO_FIPS=y | 420 | CONFIG_CRYPTO_FIPS=y |
| 422 | CONFIG_CRYPTO_NULL=m | 421 | CONFIG_CRYPTO_NULL=m |
| 423 | CONFIG_CRYPTO_CRYPTD=m | 422 | CONFIG_CRYPTO_CRYPTD=m |
| 424 | CONFIG_CRYPTO_AUTHENC=m | 423 | CONFIG_CRYPTO_AUTHENC=m |
| 425 | CONFIG_CRYPTO_TEST=m | 424 | CONFIG_CRYPTO_TEST=m |
| 426 | CONFIG_CRYPTO_CCM=m | 425 | CONFIG_CRYPTO_CCM=m |
| 427 | CONFIG_CRYPTO_GCM=m | 426 | CONFIG_CRYPTO_GCM=m |
| 428 | CONFIG_CRYPTO_LRW=m | 427 | CONFIG_CRYPTO_LRW=m |
| 429 | CONFIG_CRYPTO_PCBC=m | 428 | CONFIG_CRYPTO_PCBC=m |
| 430 | CONFIG_CRYPTO_XTS=m | 429 | CONFIG_CRYPTO_XTS=m |
| 431 | CONFIG_CRYPTO_HMAC=m | 430 | CONFIG_CRYPTO_HMAC=m |
| 432 | CONFIG_CRYPTO_XCBC=m | 431 | CONFIG_CRYPTO_XCBC=m |
| 433 | CONFIG_CRYPTO_MD4=m | 432 | CONFIG_CRYPTO_MD4=m |
| 434 | CONFIG_CRYPTO_MICHAEL_MIC=m | 433 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 435 | CONFIG_CRYPTO_RMD128=m | 434 | CONFIG_CRYPTO_RMD128=m |
| 436 | CONFIG_CRYPTO_RMD160=m | 435 | CONFIG_CRYPTO_RMD160=m |
| 437 | CONFIG_CRYPTO_RMD256=m | 436 | CONFIG_CRYPTO_RMD256=m |
| 438 | CONFIG_CRYPTO_RMD320=m | 437 | CONFIG_CRYPTO_RMD320=m |
| 439 | CONFIG_CRYPTO_SHA1=m | 438 | CONFIG_CRYPTO_SHA1=m |
| 440 | CONFIG_CRYPTO_SHA256=m | 439 | CONFIG_CRYPTO_SHA256=m |
| 441 | CONFIG_CRYPTO_SHA512=m | 440 | CONFIG_CRYPTO_SHA512=m |
| 442 | CONFIG_CRYPTO_TGR192=m | 441 | CONFIG_CRYPTO_TGR192=m |
| 443 | CONFIG_CRYPTO_WP512=m | 442 | CONFIG_CRYPTO_WP512=m |
| 444 | CONFIG_CRYPTO_ANUBIS=m | 443 | CONFIG_CRYPTO_ANUBIS=m |
| 445 | CONFIG_CRYPTO_BLOWFISH=m | 444 | CONFIG_CRYPTO_BLOWFISH=m |
| 446 | CONFIG_CRYPTO_CAMELLIA=m | 445 | CONFIG_CRYPTO_CAMELLIA=m |
| 447 | CONFIG_CRYPTO_CAST5=m | 446 | CONFIG_CRYPTO_CAST5=m |
| 448 | CONFIG_CRYPTO_CAST6=m | 447 | CONFIG_CRYPTO_CAST6=m |
| 449 | CONFIG_CRYPTO_FCRYPT=m | 448 | CONFIG_CRYPTO_FCRYPT=m |
| 450 | CONFIG_CRYPTO_KHAZAD=m | 449 | CONFIG_CRYPTO_KHAZAD=m |
| 451 | CONFIG_CRYPTO_SALSA20=m | 450 | CONFIG_CRYPTO_SALSA20=m |
| 452 | CONFIG_CRYPTO_SEED=m | 451 | CONFIG_CRYPTO_SEED=m |
| 453 | CONFIG_CRYPTO_SERPENT=m | 452 | CONFIG_CRYPTO_SERPENT=m |
| 454 | CONFIG_CRYPTO_TEA=m | 453 | CONFIG_CRYPTO_TEA=m |
| 455 | CONFIG_CRYPTO_TWOFISH=m | 454 | CONFIG_CRYPTO_TWOFISH=m |
| 456 | CONFIG_CRYPTO_DEFLATE=m | 455 | CONFIG_CRYPTO_DEFLATE=m |
| 457 | CONFIG_CRYPTO_ZLIB=m | 456 | CONFIG_CRYPTO_ZLIB=m |
| 458 | CONFIG_CRYPTO_LZO=m | 457 | CONFIG_CRYPTO_LZO=m |
| 459 | CONFIG_CRC_T10DIF=y | 458 | CONFIG_CRC_T10DIF=y |
| 460 | 459 |
arch/mips/configs/loongson3_defconfig
| 1 | CONFIG_MACH_LOONGSON=y | 1 | CONFIG_MACH_LOONGSON=y |
| 2 | CONFIG_SWIOTLB=y | 2 | CONFIG_SWIOTLB=y |
| 3 | CONFIG_LOONGSON_MACH3X=y | 3 | CONFIG_LOONGSON_MACH3X=y |
| 4 | CONFIG_CPU_LOONGSON3=y | 4 | CONFIG_CPU_LOONGSON3=y |
| 5 | CONFIG_64BIT=y | 5 | CONFIG_64BIT=y |
| 6 | CONFIG_PAGE_SIZE_16KB=y | 6 | CONFIG_PAGE_SIZE_16KB=y |
| 7 | CONFIG_KSM=y | 7 | CONFIG_KSM=y |
| 8 | CONFIG_SMP=y | 8 | CONFIG_SMP=y |
| 9 | CONFIG_NR_CPUS=4 | 9 | CONFIG_NR_CPUS=4 |
| 10 | CONFIG_HZ_256=y | 10 | CONFIG_HZ_256=y |
| 11 | CONFIG_PREEMPT=y | 11 | CONFIG_PREEMPT=y |
| 12 | CONFIG_KEXEC=y | 12 | CONFIG_KEXEC=y |
| 13 | # CONFIG_LOCALVERSION_AUTO is not set | 13 | # CONFIG_LOCALVERSION_AUTO is not set |
| 14 | CONFIG_KERNEL_LZMA=y | 14 | CONFIG_KERNEL_LZMA=y |
| 15 | CONFIG_SYSVIPC=y | 15 | CONFIG_SYSVIPC=y |
| 16 | CONFIG_POSIX_MQUEUE=y | 16 | CONFIG_POSIX_MQUEUE=y |
| 17 | CONFIG_AUDIT=y | 17 | CONFIG_AUDIT=y |
| 18 | CONFIG_NO_HZ=y | 18 | CONFIG_NO_HZ=y |
| 19 | CONFIG_HIGH_RES_TIMERS=y | 19 | CONFIG_HIGH_RES_TIMERS=y |
| 20 | CONFIG_BSD_PROCESS_ACCT=y | 20 | CONFIG_BSD_PROCESS_ACCT=y |
| 21 | CONFIG_BSD_PROCESS_ACCT_V3=y | 21 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 22 | CONFIG_TASKSTATS=y | 22 | CONFIG_TASKSTATS=y |
| 23 | CONFIG_TASK_DELAY_ACCT=y | 23 | CONFIG_TASK_DELAY_ACCT=y |
| 24 | CONFIG_TASK_XACCT=y | 24 | CONFIG_TASK_XACCT=y |
| 25 | CONFIG_TASK_IO_ACCOUNTING=y | 25 | CONFIG_TASK_IO_ACCOUNTING=y |
| 26 | CONFIG_LOG_BUF_SHIFT=14 | 26 | CONFIG_LOG_BUF_SHIFT=14 |
| 27 | CONFIG_CPUSETS=y | 27 | CONFIG_CPUSETS=y |
| 28 | CONFIG_RESOURCE_COUNTERS=y | 28 | CONFIG_RESOURCE_COUNTERS=y |
| 29 | CONFIG_MEMCG=y | 29 | CONFIG_MEMCG=y |
| 30 | CONFIG_MEMCG_SWAP=y | 30 | CONFIG_MEMCG_SWAP=y |
| 31 | CONFIG_BLK_CGROUP=y | 31 | CONFIG_BLK_CGROUP=y |
| 32 | CONFIG_SCHED_AUTOGROUP=y | 32 | CONFIG_SCHED_AUTOGROUP=y |
| 33 | CONFIG_SYSFS_DEPRECATED=y | 33 | CONFIG_SYSFS_DEPRECATED=y |
| 34 | CONFIG_RELAY=y | 34 | CONFIG_RELAY=y |
| 35 | CONFIG_BLK_DEV_INITRD=y | 35 | CONFIG_BLK_DEV_INITRD=y |
| 36 | CONFIG_RD_BZIP2=y | 36 | CONFIG_RD_BZIP2=y |
| 37 | CONFIG_RD_LZMA=y | 37 | CONFIG_RD_LZMA=y |
| 38 | CONFIG_SYSCTL_SYSCALL=y | 38 | CONFIG_SYSCTL_SYSCALL=y |
| 39 | CONFIG_EMBEDDED=y | 39 | CONFIG_EMBEDDED=y |
| 40 | CONFIG_MODULES=y | 40 | CONFIG_MODULES=y |
| 41 | CONFIG_MODULE_FORCE_LOAD=y | 41 | CONFIG_MODULE_FORCE_LOAD=y |
| 42 | CONFIG_MODULE_UNLOAD=y | 42 | CONFIG_MODULE_UNLOAD=y |
| 43 | CONFIG_MODULE_FORCE_UNLOAD=y | 43 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 44 | CONFIG_MODVERSIONS=y | 44 | CONFIG_MODVERSIONS=y |
| 45 | CONFIG_BLK_DEV_INTEGRITY=y | 45 | CONFIG_BLK_DEV_INTEGRITY=y |
| 46 | CONFIG_PARTITION_ADVANCED=y | 46 | CONFIG_PARTITION_ADVANCED=y |
| 47 | CONFIG_IOSCHED_DEADLINE=m | 47 | CONFIG_IOSCHED_DEADLINE=m |
| 48 | CONFIG_CFQ_GROUP_IOSCHED=y | 48 | CONFIG_CFQ_GROUP_IOSCHED=y |
| 49 | CONFIG_PCI=y | 49 | CONFIG_PCI=y |
| 50 | CONFIG_HT_PCI=y | 50 | CONFIG_HT_PCI=y |
| 51 | CONFIG_PCIEPORTBUS=y | 51 | CONFIG_PCIEPORTBUS=y |
| 52 | CONFIG_HOTPLUG_PCI_PCIE=y | 52 | CONFIG_HOTPLUG_PCI_PCIE=y |
| 53 | # CONFIG_PCIEAER is not set | 53 | # CONFIG_PCIEAER is not set |
| 54 | CONFIG_PCIEASPM_PERFORMANCE=y | 54 | CONFIG_PCIEASPM_PERFORMANCE=y |
| 55 | CONFIG_HOTPLUG_PCI=y | 55 | CONFIG_HOTPLUG_PCI=y |
| 56 | CONFIG_HOTPLUG_PCI_SHPC=m | 56 | CONFIG_HOTPLUG_PCI_SHPC=m |
| 57 | CONFIG_BINFMT_MISC=m | 57 | CONFIG_BINFMT_MISC=m |
| 58 | CONFIG_MIPS32_COMPAT=y | 58 | CONFIG_MIPS32_COMPAT=y |
| 59 | CONFIG_MIPS32_O32=y | 59 | CONFIG_MIPS32_O32=y |
| 60 | CONFIG_MIPS32_N32=y | 60 | CONFIG_MIPS32_N32=y |
| 61 | CONFIG_PM_RUNTIME=y | 61 | CONFIG_PM=y |
| 62 | CONFIG_NET=y | 62 | CONFIG_NET=y |
| 63 | CONFIG_PACKET=y | 63 | CONFIG_PACKET=y |
| 64 | CONFIG_UNIX=y | 64 | CONFIG_UNIX=y |
| 65 | CONFIG_XFRM_USER=y | 65 | CONFIG_XFRM_USER=y |
| 66 | CONFIG_NET_KEY=y | 66 | CONFIG_NET_KEY=y |
| 67 | CONFIG_INET=y | 67 | CONFIG_INET=y |
| 68 | CONFIG_IP_MULTICAST=y | 68 | CONFIG_IP_MULTICAST=y |
| 69 | CONFIG_IP_ADVANCED_ROUTER=y | 69 | CONFIG_IP_ADVANCED_ROUTER=y |
| 70 | CONFIG_IP_MULTIPLE_TABLES=y | 70 | CONFIG_IP_MULTIPLE_TABLES=y |
| 71 | CONFIG_IP_ROUTE_MULTIPATH=y | 71 | CONFIG_IP_ROUTE_MULTIPATH=y |
| 72 | CONFIG_IP_ROUTE_VERBOSE=y | 72 | CONFIG_IP_ROUTE_VERBOSE=y |
| 73 | CONFIG_NETFILTER=y | 73 | CONFIG_NETFILTER=y |
| 74 | CONFIG_NETFILTER_NETLINK_LOG=m | 74 | CONFIG_NETFILTER_NETLINK_LOG=m |
| 75 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 75 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 76 | CONFIG_NETFILTER_XT_TARGET_MARK=m | 76 | CONFIG_NETFILTER_XT_TARGET_MARK=m |
| 77 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | 77 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m |
| 78 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | 78 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m |
| 79 | CONFIG_NETFILTER_XT_MATCH_DCCP=m | 79 | CONFIG_NETFILTER_XT_MATCH_DCCP=m |
| 80 | CONFIG_NETFILTER_XT_MATCH_ESP=m | 80 | CONFIG_NETFILTER_XT_MATCH_ESP=m |
| 81 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | 81 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m |
| 82 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | 82 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m |
| 83 | CONFIG_NETFILTER_XT_MATCH_MAC=m | 83 | CONFIG_NETFILTER_XT_MATCH_MAC=m |
| 84 | CONFIG_NETFILTER_XT_MATCH_MARK=m | 84 | CONFIG_NETFILTER_XT_MATCH_MARK=m |
| 85 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | 85 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m |
| 86 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | 86 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m |
| 87 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | 87 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m |
| 88 | CONFIG_NETFILTER_XT_MATCH_REALM=m | 88 | CONFIG_NETFILTER_XT_MATCH_REALM=m |
| 89 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | 89 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m |
| 90 | CONFIG_NETFILTER_XT_MATCH_STRING=m | 90 | CONFIG_NETFILTER_XT_MATCH_STRING=m |
| 91 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 91 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 92 | CONFIG_IP_VS=m | 92 | CONFIG_IP_VS=m |
| 93 | CONFIG_IP_NF_IPTABLES=m | 93 | CONFIG_IP_NF_IPTABLES=m |
| 94 | CONFIG_IP_NF_MATCH_AH=m | 94 | CONFIG_IP_NF_MATCH_AH=m |
| 95 | CONFIG_IP_NF_MATCH_ECN=m | 95 | CONFIG_IP_NF_MATCH_ECN=m |
| 96 | CONFIG_IP_NF_MATCH_TTL=m | 96 | CONFIG_IP_NF_MATCH_TTL=m |
| 97 | CONFIG_IP_NF_FILTER=m | 97 | CONFIG_IP_NF_FILTER=m |
| 98 | CONFIG_IP_NF_TARGET_REJECT=m | 98 | CONFIG_IP_NF_TARGET_REJECT=m |
| 99 | CONFIG_IP_NF_TARGET_ULOG=m | 99 | CONFIG_IP_NF_TARGET_ULOG=m |
| 100 | CONFIG_IP_NF_MANGLE=m | 100 | CONFIG_IP_NF_MANGLE=m |
| 101 | CONFIG_IP_NF_TARGET_ECN=m | 101 | CONFIG_IP_NF_TARGET_ECN=m |
| 102 | CONFIG_IP_NF_TARGET_TTL=m | 102 | CONFIG_IP_NF_TARGET_TTL=m |
| 103 | CONFIG_IP_NF_RAW=m | 103 | CONFIG_IP_NF_RAW=m |
| 104 | CONFIG_IP_NF_ARPTABLES=m | 104 | CONFIG_IP_NF_ARPTABLES=m |
| 105 | CONFIG_IP_NF_ARPFILTER=m | 105 | CONFIG_IP_NF_ARPFILTER=m |
| 106 | CONFIG_IP_NF_ARP_MANGLE=m | 106 | CONFIG_IP_NF_ARP_MANGLE=m |
| 107 | CONFIG_IP_SCTP=m | 107 | CONFIG_IP_SCTP=m |
| 108 | CONFIG_L2TP=m | 108 | CONFIG_L2TP=m |
| 109 | CONFIG_BRIDGE=m | 109 | CONFIG_BRIDGE=m |
| 110 | CONFIG_CFG80211=m | 110 | CONFIG_CFG80211=m |
| 111 | CONFIG_CFG80211_WEXT=y | 111 | CONFIG_CFG80211_WEXT=y |
| 112 | CONFIG_MAC80211=m | 112 | CONFIG_MAC80211=m |
| 113 | CONFIG_RFKILL=m | 113 | CONFIG_RFKILL=m |
| 114 | CONFIG_RFKILL_INPUT=y | 114 | CONFIG_RFKILL_INPUT=y |
| 115 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 115 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 116 | CONFIG_DEVTMPFS=y | 116 | CONFIG_DEVTMPFS=y |
| 117 | CONFIG_DEVTMPFS_MOUNT=y | 117 | CONFIG_DEVTMPFS_MOUNT=y |
| 118 | CONFIG_MTD=m | 118 | CONFIG_MTD=m |
| 119 | CONFIG_BLK_DEV_LOOP=y | 119 | CONFIG_BLK_DEV_LOOP=y |
| 120 | CONFIG_BLK_DEV_CRYPTOLOOP=y | 120 | CONFIG_BLK_DEV_CRYPTOLOOP=y |
| 121 | CONFIG_BLK_DEV_RAM=y | 121 | CONFIG_BLK_DEV_RAM=y |
| 122 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 122 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 123 | CONFIG_RAID_ATTRS=m | 123 | CONFIG_RAID_ATTRS=m |
| 124 | CONFIG_BLK_DEV_SD=y | 124 | CONFIG_BLK_DEV_SD=y |
| 125 | CONFIG_BLK_DEV_SR=y | 125 | CONFIG_BLK_DEV_SR=y |
| 126 | CONFIG_CHR_DEV_SG=y | 126 | CONFIG_CHR_DEV_SG=y |
| 127 | CONFIG_CHR_DEV_SCH=m | 127 | CONFIG_CHR_DEV_SCH=m |
| 128 | CONFIG_SCSI_MULTI_LUN=y | 128 | CONFIG_SCSI_MULTI_LUN=y |
| 129 | CONFIG_SCSI_CONSTANTS=y | 129 | CONFIG_SCSI_CONSTANTS=y |
| 130 | CONFIG_SCSI_LOGGING=y | 130 | CONFIG_SCSI_LOGGING=y |
| 131 | CONFIG_SCSI_SPI_ATTRS=m | 131 | CONFIG_SCSI_SPI_ATTRS=m |
| 132 | CONFIG_SCSI_FC_ATTRS=m | 132 | CONFIG_SCSI_FC_ATTRS=m |
| 133 | CONFIG_ISCSI_TCP=m | 133 | CONFIG_ISCSI_TCP=m |
| 134 | CONFIG_MEGARAID_NEWGEN=y | 134 | CONFIG_MEGARAID_NEWGEN=y |
| 135 | CONFIG_MEGARAID_MM=y | 135 | CONFIG_MEGARAID_MM=y |
| 136 | CONFIG_MEGARAID_MAILBOX=y | 136 | CONFIG_MEGARAID_MAILBOX=y |
| 137 | CONFIG_MEGARAID_LEGACY=y | 137 | CONFIG_MEGARAID_LEGACY=y |
| 138 | CONFIG_MEGARAID_SAS=y | 138 | CONFIG_MEGARAID_SAS=y |
| 139 | CONFIG_ATA=y | 139 | CONFIG_ATA=y |
| 140 | CONFIG_SATA_AHCI=y | 140 | CONFIG_SATA_AHCI=y |
| 141 | CONFIG_PATA_ATIIXP=y | 141 | CONFIG_PATA_ATIIXP=y |
| 142 | CONFIG_MD=y | 142 | CONFIG_MD=y |
| 143 | CONFIG_BLK_DEV_MD=m | 143 | CONFIG_BLK_DEV_MD=m |
| 144 | CONFIG_MD_LINEAR=m | 144 | CONFIG_MD_LINEAR=m |
| 145 | CONFIG_MD_RAID0=m | 145 | CONFIG_MD_RAID0=m |
| 146 | CONFIG_MD_RAID1=m | 146 | CONFIG_MD_RAID1=m |
| 147 | CONFIG_MD_RAID10=m | 147 | CONFIG_MD_RAID10=m |
| 148 | CONFIG_MD_RAID456=m | 148 | CONFIG_MD_RAID456=m |
| 149 | CONFIG_MD_MULTIPATH=m | 149 | CONFIG_MD_MULTIPATH=m |
| 150 | CONFIG_BLK_DEV_DM=m | 150 | CONFIG_BLK_DEV_DM=m |
| 151 | CONFIG_DM_CRYPT=m | 151 | CONFIG_DM_CRYPT=m |
| 152 | CONFIG_DM_SNAPSHOT=m | 152 | CONFIG_DM_SNAPSHOT=m |
| 153 | CONFIG_DM_MIRROR=m | 153 | CONFIG_DM_MIRROR=m |
| 154 | CONFIG_DM_ZERO=m | 154 | CONFIG_DM_ZERO=m |
| 155 | CONFIG_TARGET_CORE=m | 155 | CONFIG_TARGET_CORE=m |
| 156 | CONFIG_TCM_IBLOCK=m | 156 | CONFIG_TCM_IBLOCK=m |
| 157 | CONFIG_TCM_FILEIO=m | 157 | CONFIG_TCM_FILEIO=m |
| 158 | CONFIG_TCM_PSCSI=m | 158 | CONFIG_TCM_PSCSI=m |
| 159 | CONFIG_LOOPBACK_TARGET=m | 159 | CONFIG_LOOPBACK_TARGET=m |
| 160 | CONFIG_ISCSI_TARGET=m | 160 | CONFIG_ISCSI_TARGET=m |
| 161 | CONFIG_NETDEVICES=y | 161 | CONFIG_NETDEVICES=y |
| 162 | CONFIG_TUN=m | 162 | CONFIG_TUN=m |
| 163 | # CONFIG_NET_VENDOR_3COM is not set | 163 | # CONFIG_NET_VENDOR_3COM is not set |
| 164 | # CONFIG_NET_VENDOR_ADAPTEC is not set | 164 | # CONFIG_NET_VENDOR_ADAPTEC is not set |
| 165 | # CONFIG_NET_VENDOR_ALTEON is not set | 165 | # CONFIG_NET_VENDOR_ALTEON is not set |
| 166 | # CONFIG_NET_VENDOR_AMD is not set | 166 | # CONFIG_NET_VENDOR_AMD is not set |
| 167 | # CONFIG_NET_VENDOR_ARC is not set | 167 | # CONFIG_NET_VENDOR_ARC is not set |
| 168 | # CONFIG_NET_VENDOR_ATHEROS is not set | 168 | # CONFIG_NET_VENDOR_ATHEROS is not set |
| 169 | # CONFIG_NET_CADENCE is not set | 169 | # CONFIG_NET_CADENCE is not set |
| 170 | # CONFIG_NET_VENDOR_BROADCOM is not set | 170 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 171 | # CONFIG_NET_VENDOR_BROCADE is not set | 171 | # CONFIG_NET_VENDOR_BROCADE is not set |
| 172 | # CONFIG_NET_VENDOR_CHELSIO is not set | 172 | # CONFIG_NET_VENDOR_CHELSIO is not set |
| 173 | # CONFIG_NET_VENDOR_CIRRUS is not set | 173 | # CONFIG_NET_VENDOR_CIRRUS is not set |
| 174 | # CONFIG_NET_VENDOR_CISCO is not set | 174 | # CONFIG_NET_VENDOR_CISCO is not set |
| 175 | # CONFIG_NET_VENDOR_DEC is not set | 175 | # CONFIG_NET_VENDOR_DEC is not set |
| 176 | # CONFIG_NET_VENDOR_DLINK is not set | 176 | # CONFIG_NET_VENDOR_DLINK is not set |
| 177 | # CONFIG_NET_VENDOR_EMULEX is not set | 177 | # CONFIG_NET_VENDOR_EMULEX is not set |
| 178 | # CONFIG_NET_VENDOR_EXAR is not set | 178 | # CONFIG_NET_VENDOR_EXAR is not set |
| 179 | # CONFIG_NET_VENDOR_HP is not set | 179 | # CONFIG_NET_VENDOR_HP is not set |
| 180 | CONFIG_E1000=y | 180 | CONFIG_E1000=y |
| 181 | CONFIG_E1000E=y | 181 | CONFIG_E1000E=y |
| 182 | CONFIG_IGB=y | 182 | CONFIG_IGB=y |
| 183 | CONFIG_IXGB=y | 183 | CONFIG_IXGB=y |
| 184 | CONFIG_IXGBE=y | 184 | CONFIG_IXGBE=y |
| 185 | # CONFIG_NET_VENDOR_I825XX is not set | 185 | # CONFIG_NET_VENDOR_I825XX is not set |
| 186 | # CONFIG_NET_VENDOR_MARVELL is not set | 186 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 187 | # CONFIG_NET_VENDOR_MELLANOX is not set | 187 | # CONFIG_NET_VENDOR_MELLANOX is not set |
| 188 | # CONFIG_NET_VENDOR_MICREL is not set | 188 | # CONFIG_NET_VENDOR_MICREL is not set |
| 189 | # CONFIG_NET_VENDOR_MYRI is not set | 189 | # CONFIG_NET_VENDOR_MYRI is not set |
| 190 | # CONFIG_NET_VENDOR_NATSEMI is not set | 190 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 191 | # CONFIG_NET_VENDOR_NVIDIA is not set | 191 | # CONFIG_NET_VENDOR_NVIDIA is not set |
| 192 | # CONFIG_NET_VENDOR_OKI is not set | 192 | # CONFIG_NET_VENDOR_OKI is not set |
| 193 | # CONFIG_NET_PACKET_ENGINE is not set | 193 | # CONFIG_NET_PACKET_ENGINE is not set |
| 194 | # CONFIG_NET_VENDOR_QLOGIC is not set | 194 | # CONFIG_NET_VENDOR_QLOGIC is not set |
| 195 | CONFIG_8139CP=m | 195 | CONFIG_8139CP=m |
| 196 | CONFIG_8139TOO=m | 196 | CONFIG_8139TOO=m |
| 197 | CONFIG_R8169=y | 197 | CONFIG_R8169=y |
| 198 | # CONFIG_NET_VENDOR_RDC is not set | 198 | # CONFIG_NET_VENDOR_RDC is not set |
| 199 | # CONFIG_NET_VENDOR_SEEQ is not set | 199 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 200 | # CONFIG_NET_VENDOR_SILAN is not set | 200 | # CONFIG_NET_VENDOR_SILAN is not set |
| 201 | # CONFIG_NET_VENDOR_SIS is not set | 201 | # CONFIG_NET_VENDOR_SIS is not set |
| 202 | # CONFIG_NET_VENDOR_SMSC is not set | 202 | # CONFIG_NET_VENDOR_SMSC is not set |
| 203 | # CONFIG_NET_VENDOR_STMICRO is not set | 203 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 204 | # CONFIG_NET_VENDOR_SUN is not set | 204 | # CONFIG_NET_VENDOR_SUN is not set |
| 205 | # CONFIG_NET_VENDOR_TEHUTI is not set | 205 | # CONFIG_NET_VENDOR_TEHUTI is not set |
| 206 | # CONFIG_NET_VENDOR_TI is not set | 206 | # CONFIG_NET_VENDOR_TI is not set |
| 207 | # CONFIG_NET_VENDOR_TOSHIBA is not set | 207 | # CONFIG_NET_VENDOR_TOSHIBA is not set |
| 208 | # CONFIG_NET_VENDOR_VIA is not set | 208 | # CONFIG_NET_VENDOR_VIA is not set |
| 209 | # CONFIG_NET_VENDOR_WIZNET is not set | 209 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 210 | CONFIG_PPP=m | 210 | CONFIG_PPP=m |
| 211 | CONFIG_PPP_BSDCOMP=m | 211 | CONFIG_PPP_BSDCOMP=m |
| 212 | CONFIG_PPP_DEFLATE=m | 212 | CONFIG_PPP_DEFLATE=m |
| 213 | CONFIG_PPP_FILTER=y | 213 | CONFIG_PPP_FILTER=y |
| 214 | CONFIG_PPP_MPPE=m | 214 | CONFIG_PPP_MPPE=m |
| 215 | CONFIG_PPP_MULTILINK=y | 215 | CONFIG_PPP_MULTILINK=y |
| 216 | CONFIG_PPPOE=m | 216 | CONFIG_PPPOE=m |
| 217 | CONFIG_PPPOL2TP=m | 217 | CONFIG_PPPOL2TP=m |
| 218 | CONFIG_PPP_ASYNC=m | 218 | CONFIG_PPP_ASYNC=m |
| 219 | CONFIG_PPP_SYNC_TTY=m | 219 | CONFIG_PPP_SYNC_TTY=m |
| 220 | CONFIG_ATH_CARDS=m | 220 | CONFIG_ATH_CARDS=m |
| 221 | CONFIG_ATH9K=m | 221 | CONFIG_ATH9K=m |
| 222 | CONFIG_HOSTAP=m | 222 | CONFIG_HOSTAP=m |
| 223 | CONFIG_INPUT_POLLDEV=m | 223 | CONFIG_INPUT_POLLDEV=m |
| 224 | CONFIG_INPUT_SPARSEKMAP=y | 224 | CONFIG_INPUT_SPARSEKMAP=y |
| 225 | CONFIG_INPUT_EVDEV=y | 225 | CONFIG_INPUT_EVDEV=y |
| 226 | CONFIG_KEYBOARD_XTKBD=m | 226 | CONFIG_KEYBOARD_XTKBD=m |
| 227 | CONFIG_MOUSE_PS2_SENTELIC=y | 227 | CONFIG_MOUSE_PS2_SENTELIC=y |
| 228 | CONFIG_MOUSE_SERIAL=m | 228 | CONFIG_MOUSE_SERIAL=m |
| 229 | CONFIG_INPUT_MISC=y | 229 | CONFIG_INPUT_MISC=y |
| 230 | CONFIG_INPUT_UINPUT=m | 230 | CONFIG_INPUT_UINPUT=m |
| 231 | CONFIG_SERIO_SERPORT=m | 231 | CONFIG_SERIO_SERPORT=m |
| 232 | CONFIG_SERIO_RAW=m | 232 | CONFIG_SERIO_RAW=m |
| 233 | CONFIG_LEGACY_PTY_COUNT=16 | 233 | CONFIG_LEGACY_PTY_COUNT=16 |
| 234 | CONFIG_SERIAL_NONSTANDARD=y | 234 | CONFIG_SERIAL_NONSTANDARD=y |
| 235 | CONFIG_SERIAL_8250=y | 235 | CONFIG_SERIAL_8250=y |
| 236 | CONFIG_SERIAL_8250_CONSOLE=y | 236 | CONFIG_SERIAL_8250_CONSOLE=y |
| 237 | CONFIG_SERIAL_8250_NR_UARTS=16 | 237 | CONFIG_SERIAL_8250_NR_UARTS=16 |
| 238 | CONFIG_SERIAL_8250_EXTENDED=y | 238 | CONFIG_SERIAL_8250_EXTENDED=y |
| 239 | CONFIG_SERIAL_8250_MANY_PORTS=y | 239 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 240 | CONFIG_SERIAL_8250_SHARE_IRQ=y | 240 | CONFIG_SERIAL_8250_SHARE_IRQ=y |
| 241 | CONFIG_SERIAL_8250_RSA=y | 241 | CONFIG_SERIAL_8250_RSA=y |
| 242 | CONFIG_HW_RANDOM=y | 242 | CONFIG_HW_RANDOM=y |
| 243 | CONFIG_RAW_DRIVER=m | 243 | CONFIG_RAW_DRIVER=m |
| 244 | CONFIG_I2C_CHARDEV=y | 244 | CONFIG_I2C_CHARDEV=y |
| 245 | CONFIG_I2C_PIIX4=y | 245 | CONFIG_I2C_PIIX4=y |
| 246 | CONFIG_SENSORS_LM75=m | 246 | CONFIG_SENSORS_LM75=m |
| 247 | CONFIG_SENSORS_LM93=m | 247 | CONFIG_SENSORS_LM93=m |
| 248 | CONFIG_SENSORS_W83627HF=m | 248 | CONFIG_SENSORS_W83627HF=m |
| 249 | CONFIG_MEDIA_SUPPORT=m | 249 | CONFIG_MEDIA_SUPPORT=m |
| 250 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 250 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 251 | CONFIG_MEDIA_USB_SUPPORT=y | 251 | CONFIG_MEDIA_USB_SUPPORT=y |
| 252 | CONFIG_USB_VIDEO_CLASS=m | 252 | CONFIG_USB_VIDEO_CLASS=m |
| 253 | CONFIG_DRM=y | 253 | CONFIG_DRM=y |
| 254 | CONFIG_DRM_RADEON=y | 254 | CONFIG_DRM_RADEON=y |
| 255 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 255 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 256 | CONFIG_FB_RADEON=y | 256 | CONFIG_FB_RADEON=y |
| 257 | CONFIG_LCD_CLASS_DEVICE=y | 257 | CONFIG_LCD_CLASS_DEVICE=y |
| 258 | CONFIG_LCD_PLATFORM=m | 258 | CONFIG_LCD_PLATFORM=m |
| 259 | CONFIG_BACKLIGHT_GENERIC=m | 259 | CONFIG_BACKLIGHT_GENERIC=m |
| 260 | # CONFIG_VGA_CONSOLE is not set | 260 | # CONFIG_VGA_CONSOLE is not set |
| 261 | CONFIG_FRAMEBUFFER_CONSOLE=y | 261 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 262 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | 262 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y |
| 263 | CONFIG_LOGO=y | 263 | CONFIG_LOGO=y |
| 264 | CONFIG_SOUND=y | 264 | CONFIG_SOUND=y |
| 265 | CONFIG_SND=m | 265 | CONFIG_SND=m |
| 266 | CONFIG_SND_SEQUENCER=m | 266 | CONFIG_SND_SEQUENCER=m |
| 267 | CONFIG_SND_SEQ_DUMMY=m | 267 | CONFIG_SND_SEQ_DUMMY=m |
| 268 | # CONFIG_SND_ISA is not set | 268 | # CONFIG_SND_ISA is not set |
| 269 | CONFIG_SND_HDA_INTEL=m | 269 | CONFIG_SND_HDA_INTEL=m |
| 270 | CONFIG_SND_HDA_PATCH_LOADER=y | 270 | CONFIG_SND_HDA_PATCH_LOADER=y |
| 271 | CONFIG_SND_HDA_CODEC_REALTEK=m | 271 | CONFIG_SND_HDA_CODEC_REALTEK=m |
| 272 | CONFIG_SND_HDA_CODEC_CONEXANT=m | 272 | CONFIG_SND_HDA_CODEC_CONEXANT=m |
| 273 | # CONFIG_SND_USB is not set | 273 | # CONFIG_SND_USB is not set |
| 274 | CONFIG_HID_A4TECH=m | 274 | CONFIG_HID_A4TECH=m |
| 275 | CONFIG_HID_SUNPLUS=m | 275 | CONFIG_HID_SUNPLUS=m |
| 276 | CONFIG_USB=y | 276 | CONFIG_USB=y |
| 277 | CONFIG_USB_MON=y | 277 | CONFIG_USB_MON=y |
| 278 | CONFIG_USB_XHCI_HCD=m | 278 | CONFIG_USB_XHCI_HCD=m |
| 279 | CONFIG_USB_EHCI_HCD=y | 279 | CONFIG_USB_EHCI_HCD=y |
| 280 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | 280 | CONFIG_USB_EHCI_ROOT_HUB_TT=y |
| 281 | CONFIG_USB_OHCI_HCD=y | 281 | CONFIG_USB_OHCI_HCD=y |
| 282 | CONFIG_USB_UHCI_HCD=m | 282 | CONFIG_USB_UHCI_HCD=m |
| 283 | CONFIG_USB_STORAGE=m | 283 | CONFIG_USB_STORAGE=m |
| 284 | CONFIG_USB_SERIAL=m | 284 | CONFIG_USB_SERIAL=m |
| 285 | CONFIG_USB_SERIAL_OPTION=m | 285 | CONFIG_USB_SERIAL_OPTION=m |
| 286 | CONFIG_RTC_CLASS=y | 286 | CONFIG_RTC_CLASS=y |
| 287 | CONFIG_RTC_DRV_CMOS=y | 287 | CONFIG_RTC_DRV_CMOS=y |
| 288 | CONFIG_DMADEVICES=y | 288 | CONFIG_DMADEVICES=y |
| 289 | CONFIG_PM_DEVFREQ=y | 289 | CONFIG_PM_DEVFREQ=y |
| 290 | CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y | 290 | CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y |
| 291 | CONFIG_DEVFREQ_GOV_PERFORMANCE=y | 291 | CONFIG_DEVFREQ_GOV_PERFORMANCE=y |
| 292 | CONFIG_DEVFREQ_GOV_POWERSAVE=y | 292 | CONFIG_DEVFREQ_GOV_POWERSAVE=y |
| 293 | CONFIG_DEVFREQ_GOV_USERSPACE=y | 293 | CONFIG_DEVFREQ_GOV_USERSPACE=y |
| 294 | CONFIG_EXT2_FS=y | 294 | CONFIG_EXT2_FS=y |
| 295 | CONFIG_EXT2_FS_XATTR=y | 295 | CONFIG_EXT2_FS_XATTR=y |
| 296 | CONFIG_EXT2_FS_POSIX_ACL=y | 296 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 297 | CONFIG_EXT2_FS_SECURITY=y | 297 | CONFIG_EXT2_FS_SECURITY=y |
| 298 | CONFIG_EXT3_FS=y | 298 | CONFIG_EXT3_FS=y |
| 299 | CONFIG_EXT3_FS_POSIX_ACL=y | 299 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 300 | CONFIG_EXT3_FS_SECURITY=y | 300 | CONFIG_EXT3_FS_SECURITY=y |
| 301 | CONFIG_EXT4_FS=y | 301 | CONFIG_EXT4_FS=y |
| 302 | CONFIG_EXT4_FS_POSIX_ACL=y | 302 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 303 | CONFIG_EXT4_FS_SECURITY=y | 303 | CONFIG_EXT4_FS_SECURITY=y |
| 304 | CONFIG_QUOTA=y | 304 | CONFIG_QUOTA=y |
| 305 | # CONFIG_PRINT_QUOTA_WARNING is not set | 305 | # CONFIG_PRINT_QUOTA_WARNING is not set |
| 306 | CONFIG_AUTOFS4_FS=y | 306 | CONFIG_AUTOFS4_FS=y |
| 307 | CONFIG_FUSE_FS=m | 307 | CONFIG_FUSE_FS=m |
| 308 | CONFIG_ISO9660_FS=m | 308 | CONFIG_ISO9660_FS=m |
| 309 | CONFIG_JOLIET=y | 309 | CONFIG_JOLIET=y |
| 310 | CONFIG_MSDOS_FS=m | 310 | CONFIG_MSDOS_FS=m |
| 311 | CONFIG_VFAT_FS=m | 311 | CONFIG_VFAT_FS=m |
| 312 | CONFIG_FAT_DEFAULT_CODEPAGE=936 | 312 | CONFIG_FAT_DEFAULT_CODEPAGE=936 |
| 313 | CONFIG_FAT_DEFAULT_IOCHARSET="gb2312" | 313 | CONFIG_FAT_DEFAULT_IOCHARSET="gb2312" |
| 314 | CONFIG_PROC_KCORE=y | 314 | CONFIG_PROC_KCORE=y |
| 315 | CONFIG_TMPFS=y | 315 | CONFIG_TMPFS=y |
| 316 | CONFIG_TMPFS_POSIX_ACL=y | 316 | CONFIG_TMPFS_POSIX_ACL=y |
| 317 | CONFIG_CONFIGFS_FS=y | 317 | CONFIG_CONFIGFS_FS=y |
| 318 | CONFIG_CRAMFS=m | 318 | CONFIG_CRAMFS=m |
| 319 | CONFIG_SQUASHFS=y | 319 | CONFIG_SQUASHFS=y |
| 320 | CONFIG_SQUASHFS_XATTR=y | 320 | CONFIG_SQUASHFS_XATTR=y |
| 321 | CONFIG_NFS_FS=m | 321 | CONFIG_NFS_FS=m |
| 322 | CONFIG_NFS_V3_ACL=y | 322 | CONFIG_NFS_V3_ACL=y |
| 323 | CONFIG_NFS_V4=m | 323 | CONFIG_NFS_V4=m |
| 324 | CONFIG_NFSD=m | 324 | CONFIG_NFSD=m |
| 325 | CONFIG_NFSD_V3_ACL=y | 325 | CONFIG_NFSD_V3_ACL=y |
| 326 | CONFIG_NFSD_V4=y | 326 | CONFIG_NFSD_V4=y |
| 327 | CONFIG_CIFS=m | 327 | CONFIG_CIFS=m |
| 328 | CONFIG_NLS_CODEPAGE_437=y | 328 | CONFIG_NLS_CODEPAGE_437=y |
| 329 | CONFIG_NLS_CODEPAGE_936=y | 329 | CONFIG_NLS_CODEPAGE_936=y |
| 330 | CONFIG_NLS_ASCII=y | 330 | CONFIG_NLS_ASCII=y |
| 331 | CONFIG_NLS_UTF8=y | 331 | CONFIG_NLS_UTF8=y |
| 332 | CONFIG_PRINTK_TIME=y | 332 | CONFIG_PRINTK_TIME=y |
| 333 | CONFIG_FRAME_WARN=1024 | 333 | CONFIG_FRAME_WARN=1024 |
| 334 | CONFIG_STRIP_ASM_SYMS=y | 334 | CONFIG_STRIP_ASM_SYMS=y |
| 335 | CONFIG_MAGIC_SYSRQ=y | 335 | CONFIG_MAGIC_SYSRQ=y |
| 336 | # CONFIG_SCHED_DEBUG is not set | 336 | # CONFIG_SCHED_DEBUG is not set |
| 337 | # CONFIG_DEBUG_PREEMPT is not set | 337 | # CONFIG_DEBUG_PREEMPT is not set |
| 338 | # CONFIG_RCU_CPU_STALL_VERBOSE is not set | 338 | # CONFIG_RCU_CPU_STALL_VERBOSE is not set |
| 339 | # CONFIG_FTRACE is not set | 339 | # CONFIG_FTRACE is not set |
| 340 | CONFIG_SECURITY=y | 340 | CONFIG_SECURITY=y |
| 341 | CONFIG_SECURITYFS=y | 341 | CONFIG_SECURITYFS=y |
| 342 | CONFIG_SECURITY_NETWORK=y | 342 | CONFIG_SECURITY_NETWORK=y |
| 343 | CONFIG_SECURITY_PATH=y | 343 | CONFIG_SECURITY_PATH=y |
| 344 | CONFIG_SECURITY_SELINUX=y | 344 | CONFIG_SECURITY_SELINUX=y |
| 345 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y | 345 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y |
| 346 | CONFIG_SECURITY_SELINUX_DISABLE=y | 346 | CONFIG_SECURITY_SELINUX_DISABLE=y |
| 347 | CONFIG_DEFAULT_SECURITY_DAC=y | 347 | CONFIG_DEFAULT_SECURITY_DAC=y |
| 348 | CONFIG_CRYPTO_AUTHENC=m | 348 | CONFIG_CRYPTO_AUTHENC=m |
| 349 | CONFIG_CRYPTO_HMAC=y | 349 | CONFIG_CRYPTO_HMAC=y |
| 350 | CONFIG_CRYPTO_MD5=y | 350 | CONFIG_CRYPTO_MD5=y |
| 351 | CONFIG_CRYPTO_SHA512=m | 351 | CONFIG_CRYPTO_SHA512=m |
| 352 | CONFIG_CRYPTO_TGR192=m | 352 | CONFIG_CRYPTO_TGR192=m |
| 353 | CONFIG_CRYPTO_WP512=m | 353 | CONFIG_CRYPTO_WP512=m |
| 354 | CONFIG_CRYPTO_ANUBIS=m | 354 | CONFIG_CRYPTO_ANUBIS=m |
| 355 | CONFIG_CRYPTO_BLOWFISH=m | 355 | CONFIG_CRYPTO_BLOWFISH=m |
| 356 | CONFIG_CRYPTO_CAST5=m | 356 | CONFIG_CRYPTO_CAST5=m |
| 357 | CONFIG_CRYPTO_CAST6=m | 357 | CONFIG_CRYPTO_CAST6=m |
| 358 | CONFIG_CRYPTO_KHAZAD=m | 358 | CONFIG_CRYPTO_KHAZAD=m |
| 359 | CONFIG_CRYPTO_SERPENT=m | 359 | CONFIG_CRYPTO_SERPENT=m |
| 360 | CONFIG_CRYPTO_TEA=m | 360 | CONFIG_CRYPTO_TEA=m |
| 361 | CONFIG_CRYPTO_TWOFISH=m | 361 | CONFIG_CRYPTO_TWOFISH=m |
| 362 | CONFIG_CRYPTO_DEFLATE=m | 362 | CONFIG_CRYPTO_DEFLATE=m |
| 363 | 363 |
arch/mips/configs/nlm_xlp_defconfig
| 1 | CONFIG_NLM_XLP_BOARD=y | 1 | CONFIG_NLM_XLP_BOARD=y |
| 2 | CONFIG_64BIT=y | 2 | CONFIG_64BIT=y |
| 3 | CONFIG_PAGE_SIZE_16KB=y | 3 | CONFIG_PAGE_SIZE_16KB=y |
| 4 | # CONFIG_HW_PERF_EVENTS is not set | 4 | # CONFIG_HW_PERF_EVENTS is not set |
| 5 | CONFIG_KSM=y | 5 | CONFIG_KSM=y |
| 6 | CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 | 6 | CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 |
| 7 | CONFIG_SMP=y | 7 | CONFIG_SMP=y |
| 8 | # CONFIG_SECCOMP is not set | 8 | # CONFIG_SECCOMP is not set |
| 9 | CONFIG_EXPERIMENTAL=y | 9 | CONFIG_EXPERIMENTAL=y |
| 10 | # CONFIG_LOCALVERSION_AUTO is not set | 10 | # CONFIG_LOCALVERSION_AUTO is not set |
| 11 | CONFIG_SYSVIPC=y | 11 | CONFIG_SYSVIPC=y |
| 12 | CONFIG_POSIX_MQUEUE=y | 12 | CONFIG_POSIX_MQUEUE=y |
| 13 | CONFIG_BSD_PROCESS_ACCT=y | 13 | CONFIG_BSD_PROCESS_ACCT=y |
| 14 | CONFIG_BSD_PROCESS_ACCT_V3=y | 14 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 15 | CONFIG_TASKSTATS=y | 15 | CONFIG_TASKSTATS=y |
| 16 | CONFIG_TASK_DELAY_ACCT=y | 16 | CONFIG_TASK_DELAY_ACCT=y |
| 17 | CONFIG_TASK_XACCT=y | 17 | CONFIG_TASK_XACCT=y |
| 18 | CONFIG_TASK_IO_ACCOUNTING=y | 18 | CONFIG_TASK_IO_ACCOUNTING=y |
| 19 | CONFIG_AUDIT=y | 19 | CONFIG_AUDIT=y |
| 20 | CONFIG_NO_HZ=y | 20 | CONFIG_NO_HZ=y |
| 21 | CONFIG_HIGH_RES_TIMERS=y | 21 | CONFIG_HIGH_RES_TIMERS=y |
| 22 | CONFIG_CGROUPS=y | 22 | CONFIG_CGROUPS=y |
| 23 | CONFIG_NAMESPACES=y | 23 | CONFIG_NAMESPACES=y |
| 24 | CONFIG_BLK_DEV_INITRD=y | 24 | CONFIG_BLK_DEV_INITRD=y |
| 25 | CONFIG_RD_BZIP2=y | 25 | CONFIG_RD_BZIP2=y |
| 26 | CONFIG_RD_LZMA=y | 26 | CONFIG_RD_LZMA=y |
| 27 | CONFIG_KALLSYMS_ALL=y | 27 | CONFIG_KALLSYMS_ALL=y |
| 28 | CONFIG_EMBEDDED=y | 28 | CONFIG_EMBEDDED=y |
| 29 | # CONFIG_COMPAT_BRK is not set | 29 | # CONFIG_COMPAT_BRK is not set |
| 30 | CONFIG_PROFILING=y | 30 | CONFIG_PROFILING=y |
| 31 | CONFIG_MODULES=y | 31 | CONFIG_MODULES=y |
| 32 | CONFIG_MODULE_UNLOAD=y | 32 | CONFIG_MODULE_UNLOAD=y |
| 33 | CONFIG_MODVERSIONS=y | 33 | CONFIG_MODVERSIONS=y |
| 34 | CONFIG_MODULE_SRCVERSION_ALL=y | 34 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 35 | CONFIG_BLK_DEV_INTEGRITY=y | 35 | CONFIG_BLK_DEV_INTEGRITY=y |
| 36 | CONFIG_PARTITION_ADVANCED=y | 36 | CONFIG_PARTITION_ADVANCED=y |
| 37 | CONFIG_ACORN_PARTITION=y | 37 | CONFIG_ACORN_PARTITION=y |
| 38 | CONFIG_ACORN_PARTITION_ICS=y | 38 | CONFIG_ACORN_PARTITION_ICS=y |
| 39 | CONFIG_ACORN_PARTITION_RISCIX=y | 39 | CONFIG_ACORN_PARTITION_RISCIX=y |
| 40 | CONFIG_OSF_PARTITION=y | 40 | CONFIG_OSF_PARTITION=y |
| 41 | CONFIG_AMIGA_PARTITION=y | 41 | CONFIG_AMIGA_PARTITION=y |
| 42 | CONFIG_ATARI_PARTITION=y | 42 | CONFIG_ATARI_PARTITION=y |
| 43 | CONFIG_MAC_PARTITION=y | 43 | CONFIG_MAC_PARTITION=y |
| 44 | CONFIG_BSD_DISKLABEL=y | 44 | CONFIG_BSD_DISKLABEL=y |
| 45 | CONFIG_MINIX_SUBPARTITION=y | 45 | CONFIG_MINIX_SUBPARTITION=y |
| 46 | CONFIG_SOLARIS_X86_PARTITION=y | 46 | CONFIG_SOLARIS_X86_PARTITION=y |
| 47 | CONFIG_UNIXWARE_DISKLABEL=y | 47 | CONFIG_UNIXWARE_DISKLABEL=y |
| 48 | CONFIG_LDM_PARTITION=y | 48 | CONFIG_LDM_PARTITION=y |
| 49 | CONFIG_SGI_PARTITION=y | 49 | CONFIG_SGI_PARTITION=y |
| 50 | CONFIG_ULTRIX_PARTITION=y | 50 | CONFIG_ULTRIX_PARTITION=y |
| 51 | CONFIG_SUN_PARTITION=y | 51 | CONFIG_SUN_PARTITION=y |
| 52 | CONFIG_KARMA_PARTITION=y | 52 | CONFIG_KARMA_PARTITION=y |
| 53 | CONFIG_EFI_PARTITION=y | 53 | CONFIG_EFI_PARTITION=y |
| 54 | CONFIG_SYSV68_PARTITION=y | 54 | CONFIG_SYSV68_PARTITION=y |
| 55 | CONFIG_PCI=y | 55 | CONFIG_PCI=y |
| 56 | CONFIG_PCI_DEBUG=y | 56 | CONFIG_PCI_DEBUG=y |
| 57 | CONFIG_PCI_REALLOC_ENABLE_AUTO=y | 57 | CONFIG_PCI_REALLOC_ENABLE_AUTO=y |
| 58 | CONFIG_PCI_STUB=y | 58 | CONFIG_PCI_STUB=y |
| 59 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 59 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 60 | CONFIG_BINFMT_MISC=y | 60 | CONFIG_BINFMT_MISC=y |
| 61 | CONFIG_MIPS32_COMPAT=y | 61 | CONFIG_MIPS32_COMPAT=y |
| 62 | CONFIG_MIPS32_O32=y | 62 | CONFIG_MIPS32_O32=y |
| 63 | CONFIG_MIPS32_N32=y | 63 | CONFIG_MIPS32_N32=y |
| 64 | CONFIG_PM_RUNTIME=y | 64 | CONFIG_PM=y |
| 65 | CONFIG_PM_DEBUG=y | 65 | CONFIG_PM_DEBUG=y |
| 66 | CONFIG_NET=y | 66 | CONFIG_NET=y |
| 67 | CONFIG_PACKET=y | 67 | CONFIG_PACKET=y |
| 68 | CONFIG_UNIX=y | 68 | CONFIG_UNIX=y |
| 69 | CONFIG_XFRM_USER=m | 69 | CONFIG_XFRM_USER=m |
| 70 | CONFIG_NET_KEY=m | 70 | CONFIG_NET_KEY=m |
| 71 | CONFIG_INET=y | 71 | CONFIG_INET=y |
| 72 | CONFIG_IP_MULTICAST=y | 72 | CONFIG_IP_MULTICAST=y |
| 73 | CONFIG_IP_ADVANCED_ROUTER=y | 73 | CONFIG_IP_ADVANCED_ROUTER=y |
| 74 | CONFIG_IP_MULTIPLE_TABLES=y | 74 | CONFIG_IP_MULTIPLE_TABLES=y |
| 75 | CONFIG_IP_ROUTE_MULTIPATH=y | 75 | CONFIG_IP_ROUTE_MULTIPATH=y |
| 76 | CONFIG_IP_ROUTE_VERBOSE=y | 76 | CONFIG_IP_ROUTE_VERBOSE=y |
| 77 | CONFIG_NET_IPIP=m | 77 | CONFIG_NET_IPIP=m |
| 78 | CONFIG_IP_MROUTE=y | 78 | CONFIG_IP_MROUTE=y |
| 79 | CONFIG_IP_PIMSM_V1=y | 79 | CONFIG_IP_PIMSM_V1=y |
| 80 | CONFIG_IP_PIMSM_V2=y | 80 | CONFIG_IP_PIMSM_V2=y |
| 81 | CONFIG_SYN_COOKIES=y | 81 | CONFIG_SYN_COOKIES=y |
| 82 | CONFIG_INET_AH=m | 82 | CONFIG_INET_AH=m |
| 83 | CONFIG_INET_ESP=m | 83 | CONFIG_INET_ESP=m |
| 84 | CONFIG_INET_IPCOMP=m | 84 | CONFIG_INET_IPCOMP=m |
| 85 | CONFIG_INET_XFRM_MODE_TRANSPORT=m | 85 | CONFIG_INET_XFRM_MODE_TRANSPORT=m |
| 86 | CONFIG_INET_XFRM_MODE_TUNNEL=m | 86 | CONFIG_INET_XFRM_MODE_TUNNEL=m |
| 87 | CONFIG_INET_XFRM_MODE_BEET=m | 87 | CONFIG_INET_XFRM_MODE_BEET=m |
| 88 | CONFIG_TCP_CONG_ADVANCED=y | 88 | CONFIG_TCP_CONG_ADVANCED=y |
| 89 | CONFIG_TCP_CONG_HSTCP=m | 89 | CONFIG_TCP_CONG_HSTCP=m |
| 90 | CONFIG_TCP_CONG_HYBLA=m | 90 | CONFIG_TCP_CONG_HYBLA=m |
| 91 | CONFIG_TCP_CONG_SCALABLE=m | 91 | CONFIG_TCP_CONG_SCALABLE=m |
| 92 | CONFIG_TCP_CONG_LP=m | 92 | CONFIG_TCP_CONG_LP=m |
| 93 | CONFIG_TCP_CONG_VENO=m | 93 | CONFIG_TCP_CONG_VENO=m |
| 94 | CONFIG_TCP_CONG_YEAH=m | 94 | CONFIG_TCP_CONG_YEAH=m |
| 95 | CONFIG_TCP_CONG_ILLINOIS=m | 95 | CONFIG_TCP_CONG_ILLINOIS=m |
| 96 | CONFIG_TCP_MD5SIG=y | 96 | CONFIG_TCP_MD5SIG=y |
| 97 | CONFIG_IPV6=y | 97 | CONFIG_IPV6=y |
| 98 | CONFIG_IPV6_PRIVACY=y | 98 | CONFIG_IPV6_PRIVACY=y |
| 99 | CONFIG_INET6_AH=m | 99 | CONFIG_INET6_AH=m |
| 100 | CONFIG_INET6_ESP=m | 100 | CONFIG_INET6_ESP=m |
| 101 | CONFIG_INET6_IPCOMP=m | 101 | CONFIG_INET6_IPCOMP=m |
| 102 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | 102 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m |
| 103 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | 103 | CONFIG_INET6_XFRM_MODE_TUNNEL=m |
| 104 | CONFIG_INET6_XFRM_MODE_BEET=m | 104 | CONFIG_INET6_XFRM_MODE_BEET=m |
| 105 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | 105 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m |
| 106 | CONFIG_IPV6_SIT=m | 106 | CONFIG_IPV6_SIT=m |
| 107 | CONFIG_IPV6_TUNNEL=m | 107 | CONFIG_IPV6_TUNNEL=m |
| 108 | CONFIG_IPV6_MULTIPLE_TABLES=y | 108 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 109 | CONFIG_NETLABEL=y | 109 | CONFIG_NETLABEL=y |
| 110 | CONFIG_NETFILTER=y | 110 | CONFIG_NETFILTER=y |
| 111 | CONFIG_NF_CONNTRACK=m | 111 | CONFIG_NF_CONNTRACK=m |
| 112 | CONFIG_NF_CONNTRACK_SECMARK=y | 112 | CONFIG_NF_CONNTRACK_SECMARK=y |
| 113 | CONFIG_NF_CONNTRACK_EVENTS=y | 113 | CONFIG_NF_CONNTRACK_EVENTS=y |
| 114 | CONFIG_NF_CT_PROTO_UDPLITE=m | 114 | CONFIG_NF_CT_PROTO_UDPLITE=m |
| 115 | CONFIG_NF_CONNTRACK_AMANDA=m | 115 | CONFIG_NF_CONNTRACK_AMANDA=m |
| 116 | CONFIG_NF_CONNTRACK_FTP=m | 116 | CONFIG_NF_CONNTRACK_FTP=m |
| 117 | CONFIG_NF_CONNTRACK_H323=m | 117 | CONFIG_NF_CONNTRACK_H323=m |
| 118 | CONFIG_NF_CONNTRACK_IRC=m | 118 | CONFIG_NF_CONNTRACK_IRC=m |
| 119 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m | 119 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m |
| 120 | CONFIG_NF_CONNTRACK_PPTP=m | 120 | CONFIG_NF_CONNTRACK_PPTP=m |
| 121 | CONFIG_NF_CONNTRACK_SANE=m | 121 | CONFIG_NF_CONNTRACK_SANE=m |
| 122 | CONFIG_NF_CONNTRACK_SIP=m | 122 | CONFIG_NF_CONNTRACK_SIP=m |
| 123 | CONFIG_NF_CONNTRACK_TFTP=m | 123 | CONFIG_NF_CONNTRACK_TFTP=m |
| 124 | CONFIG_NF_CT_NETLINK=m | 124 | CONFIG_NF_CT_NETLINK=m |
| 125 | CONFIG_NETFILTER_TPROXY=m | 125 | CONFIG_NETFILTER_TPROXY=m |
| 126 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 126 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 127 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m | 127 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m |
| 128 | CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m | 128 | CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m |
| 129 | CONFIG_NETFILTER_XT_TARGET_DSCP=m | 129 | CONFIG_NETFILTER_XT_TARGET_DSCP=m |
| 130 | CONFIG_NETFILTER_XT_TARGET_MARK=m | 130 | CONFIG_NETFILTER_XT_TARGET_MARK=m |
| 131 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | 131 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m |
| 132 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | 132 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m |
| 133 | CONFIG_NETFILTER_XT_TARGET_TPROXY=m | 133 | CONFIG_NETFILTER_XT_TARGET_TPROXY=m |
| 134 | CONFIG_NETFILTER_XT_TARGET_TRACE=m | 134 | CONFIG_NETFILTER_XT_TARGET_TRACE=m |
| 135 | CONFIG_NETFILTER_XT_TARGET_SECMARK=m | 135 | CONFIG_NETFILTER_XT_TARGET_SECMARK=m |
| 136 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | 136 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m |
| 137 | CONFIG_NETFILTER_XT_MATCH_CLUSTER=m | 137 | CONFIG_NETFILTER_XT_MATCH_CLUSTER=m |
| 138 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | 138 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m |
| 139 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | 139 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m |
| 140 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | 140 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m |
| 141 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m | 141 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m |
| 142 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | 142 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m |
| 143 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | 143 | CONFIG_NETFILTER_XT_MATCH_DSCP=m |
| 144 | CONFIG_NETFILTER_XT_MATCH_ESP=m | 144 | CONFIG_NETFILTER_XT_MATCH_ESP=m |
| 145 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | 145 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m |
| 146 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | 146 | CONFIG_NETFILTER_XT_MATCH_HELPER=m |
| 147 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=m | 147 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=m |
| 148 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | 148 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m |
| 149 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | 149 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m |
| 150 | CONFIG_NETFILTER_XT_MATCH_MAC=m | 150 | CONFIG_NETFILTER_XT_MATCH_MAC=m |
| 151 | CONFIG_NETFILTER_XT_MATCH_MARK=m | 151 | CONFIG_NETFILTER_XT_MATCH_MARK=m |
| 152 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | 152 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m |
| 153 | CONFIG_NETFILTER_XT_MATCH_OSF=m | 153 | CONFIG_NETFILTER_XT_MATCH_OSF=m |
| 154 | CONFIG_NETFILTER_XT_MATCH_OWNER=m | 154 | CONFIG_NETFILTER_XT_MATCH_OWNER=m |
| 155 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | 155 | CONFIG_NETFILTER_XT_MATCH_POLICY=m |
| 156 | CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m | 156 | CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m |
| 157 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | 157 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m |
| 158 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | 158 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m |
| 159 | CONFIG_NETFILTER_XT_MATCH_RATEEST=m | 159 | CONFIG_NETFILTER_XT_MATCH_RATEEST=m |
| 160 | CONFIG_NETFILTER_XT_MATCH_REALM=m | 160 | CONFIG_NETFILTER_XT_MATCH_REALM=m |
| 161 | CONFIG_NETFILTER_XT_MATCH_RECENT=m | 161 | CONFIG_NETFILTER_XT_MATCH_RECENT=m |
| 162 | CONFIG_NETFILTER_XT_MATCH_SOCKET=m | 162 | CONFIG_NETFILTER_XT_MATCH_SOCKET=m |
| 163 | CONFIG_NETFILTER_XT_MATCH_STATE=m | 163 | CONFIG_NETFILTER_XT_MATCH_STATE=m |
| 164 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | 164 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m |
| 165 | CONFIG_NETFILTER_XT_MATCH_STRING=m | 165 | CONFIG_NETFILTER_XT_MATCH_STRING=m |
| 166 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 166 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 167 | CONFIG_NETFILTER_XT_MATCH_TIME=m | 167 | CONFIG_NETFILTER_XT_MATCH_TIME=m |
| 168 | CONFIG_NETFILTER_XT_MATCH_U32=m | 168 | CONFIG_NETFILTER_XT_MATCH_U32=m |
| 169 | CONFIG_IP_VS=m | 169 | CONFIG_IP_VS=m |
| 170 | CONFIG_IP_VS_IPV6=y | 170 | CONFIG_IP_VS_IPV6=y |
| 171 | CONFIG_IP_VS_PROTO_TCP=y | 171 | CONFIG_IP_VS_PROTO_TCP=y |
| 172 | CONFIG_IP_VS_PROTO_UDP=y | 172 | CONFIG_IP_VS_PROTO_UDP=y |
| 173 | CONFIG_IP_VS_PROTO_ESP=y | 173 | CONFIG_IP_VS_PROTO_ESP=y |
| 174 | CONFIG_IP_VS_PROTO_AH=y | 174 | CONFIG_IP_VS_PROTO_AH=y |
| 175 | CONFIG_IP_VS_RR=m | 175 | CONFIG_IP_VS_RR=m |
| 176 | CONFIG_IP_VS_WRR=m | 176 | CONFIG_IP_VS_WRR=m |
| 177 | CONFIG_IP_VS_LC=m | 177 | CONFIG_IP_VS_LC=m |
| 178 | CONFIG_IP_VS_WLC=m | 178 | CONFIG_IP_VS_WLC=m |
| 179 | CONFIG_IP_VS_LBLC=m | 179 | CONFIG_IP_VS_LBLC=m |
| 180 | CONFIG_IP_VS_LBLCR=m | 180 | CONFIG_IP_VS_LBLCR=m |
| 181 | CONFIG_IP_VS_DH=m | 181 | CONFIG_IP_VS_DH=m |
| 182 | CONFIG_IP_VS_SH=m | 182 | CONFIG_IP_VS_SH=m |
| 183 | CONFIG_IP_VS_SED=m | 183 | CONFIG_IP_VS_SED=m |
| 184 | CONFIG_IP_VS_NQ=m | 184 | CONFIG_IP_VS_NQ=m |
| 185 | CONFIG_IP_VS_FTP=m | 185 | CONFIG_IP_VS_FTP=m |
| 186 | CONFIG_NF_CONNTRACK_IPV4=m | 186 | CONFIG_NF_CONNTRACK_IPV4=m |
| 187 | CONFIG_IP_NF_QUEUE=m | 187 | CONFIG_IP_NF_QUEUE=m |
| 188 | CONFIG_IP_NF_IPTABLES=m | 188 | CONFIG_IP_NF_IPTABLES=m |
| 189 | CONFIG_IP_NF_MATCH_AH=m | 189 | CONFIG_IP_NF_MATCH_AH=m |
| 190 | CONFIG_IP_NF_MATCH_ECN=m | 190 | CONFIG_IP_NF_MATCH_ECN=m |
| 191 | CONFIG_IP_NF_MATCH_TTL=m | 191 | CONFIG_IP_NF_MATCH_TTL=m |
| 192 | CONFIG_IP_NF_FILTER=m | 192 | CONFIG_IP_NF_FILTER=m |
| 193 | CONFIG_IP_NF_TARGET_REJECT=m | 193 | CONFIG_IP_NF_TARGET_REJECT=m |
| 194 | CONFIG_IP_NF_TARGET_ULOG=m | 194 | CONFIG_IP_NF_TARGET_ULOG=m |
| 195 | CONFIG_NF_NAT=m | 195 | CONFIG_NF_NAT=m |
| 196 | CONFIG_IP_NF_TARGET_MASQUERADE=m | 196 | CONFIG_IP_NF_TARGET_MASQUERADE=m |
| 197 | CONFIG_IP_NF_TARGET_NETMAP=m | 197 | CONFIG_IP_NF_TARGET_NETMAP=m |
| 198 | CONFIG_IP_NF_TARGET_REDIRECT=m | 198 | CONFIG_IP_NF_TARGET_REDIRECT=m |
| 199 | CONFIG_IP_NF_MANGLE=m | 199 | CONFIG_IP_NF_MANGLE=m |
| 200 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | 200 | CONFIG_IP_NF_TARGET_CLUSTERIP=m |
| 201 | CONFIG_IP_NF_TARGET_ECN=m | 201 | CONFIG_IP_NF_TARGET_ECN=m |
| 202 | CONFIG_IP_NF_TARGET_TTL=m | 202 | CONFIG_IP_NF_TARGET_TTL=m |
| 203 | CONFIG_IP_NF_RAW=m | 203 | CONFIG_IP_NF_RAW=m |
| 204 | CONFIG_IP_NF_SECURITY=m | 204 | CONFIG_IP_NF_SECURITY=m |
| 205 | CONFIG_IP_NF_ARPTABLES=m | 205 | CONFIG_IP_NF_ARPTABLES=m |
| 206 | CONFIG_IP_NF_ARPFILTER=m | 206 | CONFIG_IP_NF_ARPFILTER=m |
| 207 | CONFIG_IP_NF_ARP_MANGLE=m | 207 | CONFIG_IP_NF_ARP_MANGLE=m |
| 208 | CONFIG_NF_CONNTRACK_IPV6=m | 208 | CONFIG_NF_CONNTRACK_IPV6=m |
| 209 | CONFIG_IP6_NF_IPTABLES=m | 209 | CONFIG_IP6_NF_IPTABLES=m |
| 210 | CONFIG_IP6_NF_MATCH_AH=m | 210 | CONFIG_IP6_NF_MATCH_AH=m |
| 211 | CONFIG_IP6_NF_MATCH_EUI64=m | 211 | CONFIG_IP6_NF_MATCH_EUI64=m |
| 212 | CONFIG_IP6_NF_MATCH_FRAG=m | 212 | CONFIG_IP6_NF_MATCH_FRAG=m |
| 213 | CONFIG_IP6_NF_MATCH_OPTS=m | 213 | CONFIG_IP6_NF_MATCH_OPTS=m |
| 214 | CONFIG_IP6_NF_MATCH_HL=m | 214 | CONFIG_IP6_NF_MATCH_HL=m |
| 215 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | 215 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m |
| 216 | CONFIG_IP6_NF_MATCH_MH=m | 216 | CONFIG_IP6_NF_MATCH_MH=m |
| 217 | CONFIG_IP6_NF_MATCH_RT=m | 217 | CONFIG_IP6_NF_MATCH_RT=m |
| 218 | CONFIG_IP6_NF_TARGET_HL=m | 218 | CONFIG_IP6_NF_TARGET_HL=m |
| 219 | CONFIG_IP6_NF_FILTER=m | 219 | CONFIG_IP6_NF_FILTER=m |
| 220 | CONFIG_IP6_NF_TARGET_REJECT=m | 220 | CONFIG_IP6_NF_TARGET_REJECT=m |
| 221 | CONFIG_IP6_NF_MANGLE=m | 221 | CONFIG_IP6_NF_MANGLE=m |
| 222 | CONFIG_IP6_NF_RAW=m | 222 | CONFIG_IP6_NF_RAW=m |
| 223 | CONFIG_IP6_NF_SECURITY=m | 223 | CONFIG_IP6_NF_SECURITY=m |
| 224 | CONFIG_DECNET_NF_GRABULATOR=m | 224 | CONFIG_DECNET_NF_GRABULATOR=m |
| 225 | CONFIG_BRIDGE_NF_EBTABLES=m | 225 | CONFIG_BRIDGE_NF_EBTABLES=m |
| 226 | CONFIG_BRIDGE_EBT_BROUTE=m | 226 | CONFIG_BRIDGE_EBT_BROUTE=m |
| 227 | CONFIG_BRIDGE_EBT_T_FILTER=m | 227 | CONFIG_BRIDGE_EBT_T_FILTER=m |
| 228 | CONFIG_BRIDGE_EBT_T_NAT=m | 228 | CONFIG_BRIDGE_EBT_T_NAT=m |
| 229 | CONFIG_BRIDGE_EBT_802_3=m | 229 | CONFIG_BRIDGE_EBT_802_3=m |
| 230 | CONFIG_BRIDGE_EBT_AMONG=m | 230 | CONFIG_BRIDGE_EBT_AMONG=m |
| 231 | CONFIG_BRIDGE_EBT_ARP=m | 231 | CONFIG_BRIDGE_EBT_ARP=m |
| 232 | CONFIG_BRIDGE_EBT_IP=m | 232 | CONFIG_BRIDGE_EBT_IP=m |
| 233 | CONFIG_BRIDGE_EBT_IP6=m | 233 | CONFIG_BRIDGE_EBT_IP6=m |
| 234 | CONFIG_BRIDGE_EBT_LIMIT=m | 234 | CONFIG_BRIDGE_EBT_LIMIT=m |
| 235 | CONFIG_BRIDGE_EBT_MARK=m | 235 | CONFIG_BRIDGE_EBT_MARK=m |
| 236 | CONFIG_BRIDGE_EBT_PKTTYPE=m | 236 | CONFIG_BRIDGE_EBT_PKTTYPE=m |
| 237 | CONFIG_BRIDGE_EBT_STP=m | 237 | CONFIG_BRIDGE_EBT_STP=m |
| 238 | CONFIG_BRIDGE_EBT_VLAN=m | 238 | CONFIG_BRIDGE_EBT_VLAN=m |
| 239 | CONFIG_BRIDGE_EBT_ARPREPLY=m | 239 | CONFIG_BRIDGE_EBT_ARPREPLY=m |
| 240 | CONFIG_BRIDGE_EBT_DNAT=m | 240 | CONFIG_BRIDGE_EBT_DNAT=m |
| 241 | CONFIG_BRIDGE_EBT_MARK_T=m | 241 | CONFIG_BRIDGE_EBT_MARK_T=m |
| 242 | CONFIG_BRIDGE_EBT_REDIRECT=m | 242 | CONFIG_BRIDGE_EBT_REDIRECT=m |
| 243 | CONFIG_BRIDGE_EBT_SNAT=m | 243 | CONFIG_BRIDGE_EBT_SNAT=m |
| 244 | CONFIG_BRIDGE_EBT_LOG=m | 244 | CONFIG_BRIDGE_EBT_LOG=m |
| 245 | CONFIG_BRIDGE_EBT_ULOG=m | 245 | CONFIG_BRIDGE_EBT_ULOG=m |
| 246 | CONFIG_BRIDGE_EBT_NFLOG=m | 246 | CONFIG_BRIDGE_EBT_NFLOG=m |
| 247 | CONFIG_IP_DCCP=m | 247 | CONFIG_IP_DCCP=m |
| 248 | CONFIG_RDS=m | 248 | CONFIG_RDS=m |
| 249 | CONFIG_RDS_TCP=m | 249 | CONFIG_RDS_TCP=m |
| 250 | CONFIG_TIPC=m | 250 | CONFIG_TIPC=m |
| 251 | CONFIG_ATM=m | 251 | CONFIG_ATM=m |
| 252 | CONFIG_ATM_CLIP=m | 252 | CONFIG_ATM_CLIP=m |
| 253 | CONFIG_ATM_LANE=m | 253 | CONFIG_ATM_LANE=m |
| 254 | CONFIG_ATM_MPOA=m | 254 | CONFIG_ATM_MPOA=m |
| 255 | CONFIG_ATM_BR2684=m | 255 | CONFIG_ATM_BR2684=m |
| 256 | CONFIG_BRIDGE=m | 256 | CONFIG_BRIDGE=m |
| 257 | CONFIG_VLAN_8021Q=m | 257 | CONFIG_VLAN_8021Q=m |
| 258 | CONFIG_VLAN_8021Q_GVRP=y | 258 | CONFIG_VLAN_8021Q_GVRP=y |
| 259 | CONFIG_DECNET=m | 259 | CONFIG_DECNET=m |
| 260 | CONFIG_LLC2=m | 260 | CONFIG_LLC2=m |
| 261 | CONFIG_IPX=m | 261 | CONFIG_IPX=m |
| 262 | CONFIG_ATALK=m | 262 | CONFIG_ATALK=m |
| 263 | CONFIG_DEV_APPLETALK=m | 263 | CONFIG_DEV_APPLETALK=m |
| 264 | CONFIG_IPDDP=m | 264 | CONFIG_IPDDP=m |
| 265 | CONFIG_IPDDP_ENCAP=y | 265 | CONFIG_IPDDP_ENCAP=y |
| 266 | CONFIG_IPDDP_DECAP=y | 266 | CONFIG_IPDDP_DECAP=y |
| 267 | CONFIG_X25=m | 267 | CONFIG_X25=m |
| 268 | CONFIG_LAPB=m | 268 | CONFIG_LAPB=m |
| 269 | CONFIG_WAN_ROUTER=m | 269 | CONFIG_WAN_ROUTER=m |
| 270 | CONFIG_PHONET=m | 270 | CONFIG_PHONET=m |
| 271 | CONFIG_IEEE802154=m | 271 | CONFIG_IEEE802154=m |
| 272 | CONFIG_NET_SCHED=y | 272 | CONFIG_NET_SCHED=y |
| 273 | CONFIG_NET_SCH_CBQ=m | 273 | CONFIG_NET_SCH_CBQ=m |
| 274 | CONFIG_NET_SCH_HTB=m | 274 | CONFIG_NET_SCH_HTB=m |
| 275 | CONFIG_NET_SCH_HFSC=m | 275 | CONFIG_NET_SCH_HFSC=m |
| 276 | CONFIG_NET_SCH_ATM=m | 276 | CONFIG_NET_SCH_ATM=m |
| 277 | CONFIG_NET_SCH_PRIO=m | 277 | CONFIG_NET_SCH_PRIO=m |
| 278 | CONFIG_NET_SCH_MULTIQ=m | 278 | CONFIG_NET_SCH_MULTIQ=m |
| 279 | CONFIG_NET_SCH_RED=m | 279 | CONFIG_NET_SCH_RED=m |
| 280 | CONFIG_NET_SCH_SFQ=m | 280 | CONFIG_NET_SCH_SFQ=m |
| 281 | CONFIG_NET_SCH_TEQL=m | 281 | CONFIG_NET_SCH_TEQL=m |
| 282 | CONFIG_NET_SCH_TBF=m | 282 | CONFIG_NET_SCH_TBF=m |
| 283 | CONFIG_NET_SCH_GRED=m | 283 | CONFIG_NET_SCH_GRED=m |
| 284 | CONFIG_NET_SCH_DSMARK=m | 284 | CONFIG_NET_SCH_DSMARK=m |
| 285 | CONFIG_NET_SCH_NETEM=m | 285 | CONFIG_NET_SCH_NETEM=m |
| 286 | CONFIG_NET_SCH_DRR=m | 286 | CONFIG_NET_SCH_DRR=m |
| 287 | CONFIG_NET_SCH_INGRESS=m | 287 | CONFIG_NET_SCH_INGRESS=m |
| 288 | CONFIG_NET_CLS_BASIC=m | 288 | CONFIG_NET_CLS_BASIC=m |
| 289 | CONFIG_NET_CLS_TCINDEX=m | 289 | CONFIG_NET_CLS_TCINDEX=m |
| 290 | CONFIG_NET_CLS_ROUTE4=m | 290 | CONFIG_NET_CLS_ROUTE4=m |
| 291 | CONFIG_NET_CLS_FW=m | 291 | CONFIG_NET_CLS_FW=m |
| 292 | CONFIG_NET_CLS_U32=m | 292 | CONFIG_NET_CLS_U32=m |
| 293 | CONFIG_CLS_U32_MARK=y | 293 | CONFIG_CLS_U32_MARK=y |
| 294 | CONFIG_NET_CLS_RSVP=m | 294 | CONFIG_NET_CLS_RSVP=m |
| 295 | CONFIG_NET_CLS_RSVP6=m | 295 | CONFIG_NET_CLS_RSVP6=m |
| 296 | CONFIG_NET_CLS_FLOW=m | 296 | CONFIG_NET_CLS_FLOW=m |
| 297 | CONFIG_NET_EMATCH=y | 297 | CONFIG_NET_EMATCH=y |
| 298 | CONFIG_NET_EMATCH_CMP=m | 298 | CONFIG_NET_EMATCH_CMP=m |
| 299 | CONFIG_NET_EMATCH_NBYTE=m | 299 | CONFIG_NET_EMATCH_NBYTE=m |
| 300 | CONFIG_NET_EMATCH_U32=m | 300 | CONFIG_NET_EMATCH_U32=m |
| 301 | CONFIG_NET_EMATCH_META=m | 301 | CONFIG_NET_EMATCH_META=m |
| 302 | CONFIG_NET_EMATCH_TEXT=m | 302 | CONFIG_NET_EMATCH_TEXT=m |
| 303 | CONFIG_NET_CLS_ACT=y | 303 | CONFIG_NET_CLS_ACT=y |
| 304 | CONFIG_NET_ACT_POLICE=m | 304 | CONFIG_NET_ACT_POLICE=m |
| 305 | CONFIG_NET_ACT_GACT=m | 305 | CONFIG_NET_ACT_GACT=m |
| 306 | CONFIG_GACT_PROB=y | 306 | CONFIG_GACT_PROB=y |
| 307 | CONFIG_NET_ACT_MIRRED=m | 307 | CONFIG_NET_ACT_MIRRED=m |
| 308 | CONFIG_NET_ACT_IPT=m | 308 | CONFIG_NET_ACT_IPT=m |
| 309 | CONFIG_NET_ACT_NAT=m | 309 | CONFIG_NET_ACT_NAT=m |
| 310 | CONFIG_NET_ACT_PEDIT=m | 310 | CONFIG_NET_ACT_PEDIT=m |
| 311 | CONFIG_NET_ACT_SIMP=m | 311 | CONFIG_NET_ACT_SIMP=m |
| 312 | CONFIG_NET_ACT_SKBEDIT=m | 312 | CONFIG_NET_ACT_SKBEDIT=m |
| 313 | CONFIG_DCB=y | 313 | CONFIG_DCB=y |
| 314 | CONFIG_NET_PKTGEN=m | 314 | CONFIG_NET_PKTGEN=m |
| 315 | CONFIG_DEVTMPFS=y | 315 | CONFIG_DEVTMPFS=y |
| 316 | CONFIG_DEVTMPFS_MOUNT=y | 316 | CONFIG_DEVTMPFS_MOUNT=y |
| 317 | # CONFIG_STANDALONE is not set | 317 | # CONFIG_STANDALONE is not set |
| 318 | CONFIG_CONNECTOR=y | 318 | CONFIG_CONNECTOR=y |
| 319 | CONFIG_MTD=y | 319 | CONFIG_MTD=y |
| 320 | CONFIG_MTD_CMDLINE_PARTS=y | 320 | CONFIG_MTD_CMDLINE_PARTS=y |
| 321 | CONFIG_MTD_CHAR=y | 321 | CONFIG_MTD_CHAR=y |
| 322 | CONFIG_MTD_BLOCK=y | 322 | CONFIG_MTD_BLOCK=y |
| 323 | CONFIG_MTD_CFI=y | 323 | CONFIG_MTD_CFI=y |
| 324 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 324 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| 325 | CONFIG_MTD_CFI_LE_BYTE_SWAP=y | 325 | CONFIG_MTD_CFI_LE_BYTE_SWAP=y |
| 326 | CONFIG_MTD_CFI_GEOMETRY=y | 326 | CONFIG_MTD_CFI_GEOMETRY=y |
| 327 | CONFIG_MTD_CFI_INTELEXT=y | 327 | CONFIG_MTD_CFI_INTELEXT=y |
| 328 | CONFIG_MTD_PHYSMAP=y | 328 | CONFIG_MTD_PHYSMAP=y |
| 329 | CONFIG_MTD_PHYSMAP_OF=y | 329 | CONFIG_MTD_PHYSMAP_OF=y |
| 330 | CONFIG_BLK_DEV_LOOP=y | 330 | CONFIG_BLK_DEV_LOOP=y |
| 331 | CONFIG_BLK_DEV_CRYPTOLOOP=m | 331 | CONFIG_BLK_DEV_CRYPTOLOOP=m |
| 332 | CONFIG_BLK_DEV_NBD=m | 332 | CONFIG_BLK_DEV_NBD=m |
| 333 | CONFIG_BLK_DEV_OSD=m | 333 | CONFIG_BLK_DEV_OSD=m |
| 334 | CONFIG_BLK_DEV_RAM=y | 334 | CONFIG_BLK_DEV_RAM=y |
| 335 | CONFIG_BLK_DEV_RAM_SIZE=65536 | 335 | CONFIG_BLK_DEV_RAM_SIZE=65536 |
| 336 | CONFIG_CDROM_PKTCDVD=y | 336 | CONFIG_CDROM_PKTCDVD=y |
| 337 | CONFIG_RAID_ATTRS=m | 337 | CONFIG_RAID_ATTRS=m |
| 338 | CONFIG_BLK_DEV_SD=y | 338 | CONFIG_BLK_DEV_SD=y |
| 339 | CONFIG_CHR_DEV_ST=m | 339 | CONFIG_CHR_DEV_ST=m |
| 340 | CONFIG_CHR_DEV_OSST=m | 340 | CONFIG_CHR_DEV_OSST=m |
| 341 | CONFIG_BLK_DEV_SR=y | 341 | CONFIG_BLK_DEV_SR=y |
| 342 | CONFIG_CHR_DEV_SG=y | 342 | CONFIG_CHR_DEV_SG=y |
| 343 | CONFIG_CHR_DEV_SCH=m | 343 | CONFIG_CHR_DEV_SCH=m |
| 344 | CONFIG_SCSI_MULTI_LUN=y | 344 | CONFIG_SCSI_MULTI_LUN=y |
| 345 | CONFIG_SCSI_CONSTANTS=y | 345 | CONFIG_SCSI_CONSTANTS=y |
| 346 | CONFIG_SCSI_LOGGING=y | 346 | CONFIG_SCSI_LOGGING=y |
| 347 | CONFIG_SCSI_SCAN_ASYNC=y | 347 | CONFIG_SCSI_SCAN_ASYNC=y |
| 348 | CONFIG_SCSI_SPI_ATTRS=m | 348 | CONFIG_SCSI_SPI_ATTRS=m |
| 349 | CONFIG_SCSI_SAS_LIBSAS=m | 349 | CONFIG_SCSI_SAS_LIBSAS=m |
| 350 | CONFIG_SCSI_SRP_ATTRS=m | 350 | CONFIG_SCSI_SRP_ATTRS=m |
| 351 | CONFIG_ISCSI_TCP=m | 351 | CONFIG_ISCSI_TCP=m |
| 352 | CONFIG_LIBFCOE=m | 352 | CONFIG_LIBFCOE=m |
| 353 | CONFIG_SCSI_DEBUG=m | 353 | CONFIG_SCSI_DEBUG=m |
| 354 | CONFIG_SCSI_DH=y | 354 | CONFIG_SCSI_DH=y |
| 355 | CONFIG_SCSI_DH_RDAC=m | 355 | CONFIG_SCSI_DH_RDAC=m |
| 356 | CONFIG_SCSI_DH_HP_SW=m | 356 | CONFIG_SCSI_DH_HP_SW=m |
| 357 | CONFIG_SCSI_DH_EMC=m | 357 | CONFIG_SCSI_DH_EMC=m |
| 358 | CONFIG_SCSI_DH_ALUA=m | 358 | CONFIG_SCSI_DH_ALUA=m |
| 359 | CONFIG_SCSI_OSD_INITIATOR=m | 359 | CONFIG_SCSI_OSD_INITIATOR=m |
| 360 | CONFIG_SCSI_OSD_ULD=m | 360 | CONFIG_SCSI_OSD_ULD=m |
| 361 | CONFIG_ATA=y | 361 | CONFIG_ATA=y |
| 362 | CONFIG_SATA_AHCI=y | 362 | CONFIG_SATA_AHCI=y |
| 363 | CONFIG_SATA_SIL24=y | 363 | CONFIG_SATA_SIL24=y |
| 364 | # CONFIG_ATA_SFF is not set | 364 | # CONFIG_ATA_SFF is not set |
| 365 | CONFIG_NETDEVICES=y | 365 | CONFIG_NETDEVICES=y |
| 366 | # CONFIG_NET_VENDOR_3COM is not set | 366 | # CONFIG_NET_VENDOR_3COM is not set |
| 367 | # CONFIG_NET_VENDOR_ADAPTEC is not set | 367 | # CONFIG_NET_VENDOR_ADAPTEC is not set |
| 368 | # CONFIG_NET_VENDOR_ALTEON is not set | 368 | # CONFIG_NET_VENDOR_ALTEON is not set |
| 369 | # CONFIG_NET_VENDOR_AMD is not set | 369 | # CONFIG_NET_VENDOR_AMD is not set |
| 370 | # CONFIG_NET_VENDOR_ATHEROS is not set | 370 | # CONFIG_NET_VENDOR_ATHEROS is not set |
| 371 | # CONFIG_NET_VENDOR_BROADCOM is not set | 371 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 372 | # CONFIG_NET_VENDOR_BROCADE is not set | 372 | # CONFIG_NET_VENDOR_BROCADE is not set |
| 373 | # CONFIG_NET_VENDOR_CHELSIO is not set | 373 | # CONFIG_NET_VENDOR_CHELSIO is not set |
| 374 | # CONFIG_NET_VENDOR_DEC is not set | 374 | # CONFIG_NET_VENDOR_DEC is not set |
| 375 | # CONFIG_NET_VENDOR_DLINK is not set | 375 | # CONFIG_NET_VENDOR_DLINK is not set |
| 376 | # CONFIG_NET_VENDOR_EMULEX is not set | 376 | # CONFIG_NET_VENDOR_EMULEX is not set |
| 377 | # CONFIG_NET_VENDOR_EXAR is not set | 377 | # CONFIG_NET_VENDOR_EXAR is not set |
| 378 | # CONFIG_NET_VENDOR_HP is not set | 378 | # CONFIG_NET_VENDOR_HP is not set |
| 379 | CONFIG_E1000E=y | 379 | CONFIG_E1000E=y |
| 380 | # CONFIG_NET_VENDOR_I825XX is not set | 380 | # CONFIG_NET_VENDOR_I825XX is not set |
| 381 | CONFIG_SKY2=y | 381 | CONFIG_SKY2=y |
| 382 | # CONFIG_NET_VENDOR_MELLANOX is not set | 382 | # CONFIG_NET_VENDOR_MELLANOX is not set |
| 383 | # CONFIG_NET_VENDOR_MICREL is not set | 383 | # CONFIG_NET_VENDOR_MICREL is not set |
| 384 | # CONFIG_NET_VENDOR_MYRI is not set | 384 | # CONFIG_NET_VENDOR_MYRI is not set |
| 385 | # CONFIG_NET_VENDOR_NATSEMI is not set | 385 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 386 | # CONFIG_NET_VENDOR_NVIDIA is not set | 386 | # CONFIG_NET_VENDOR_NVIDIA is not set |
| 387 | # CONFIG_NET_VENDOR_OKI is not set | 387 | # CONFIG_NET_VENDOR_OKI is not set |
| 388 | # CONFIG_NET_PACKET_ENGINE is not set | 388 | # CONFIG_NET_PACKET_ENGINE is not set |
| 389 | # CONFIG_NET_VENDOR_QLOGIC is not set | 389 | # CONFIG_NET_VENDOR_QLOGIC is not set |
| 390 | # CONFIG_NET_VENDOR_REALTEK is not set | 390 | # CONFIG_NET_VENDOR_REALTEK is not set |
| 391 | # CONFIG_NET_VENDOR_RDC is not set | 391 | # CONFIG_NET_VENDOR_RDC is not set |
| 392 | # CONFIG_NET_VENDOR_SEEQ is not set | 392 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 393 | # CONFIG_NET_VENDOR_SILAN is not set | 393 | # CONFIG_NET_VENDOR_SILAN is not set |
| 394 | # CONFIG_NET_VENDOR_SIS is not set | 394 | # CONFIG_NET_VENDOR_SIS is not set |
| 395 | # CONFIG_NET_VENDOR_SMSC is not set | 395 | # CONFIG_NET_VENDOR_SMSC is not set |
| 396 | # CONFIG_NET_VENDOR_STMICRO is not set | 396 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 397 | # CONFIG_NET_VENDOR_SUN is not set | 397 | # CONFIG_NET_VENDOR_SUN is not set |
| 398 | # CONFIG_NET_VENDOR_TEHUTI is not set | 398 | # CONFIG_NET_VENDOR_TEHUTI is not set |
| 399 | # CONFIG_NET_VENDOR_TI is not set | 399 | # CONFIG_NET_VENDOR_TI is not set |
| 400 | # CONFIG_NET_VENDOR_TOSHIBA is not set | 400 | # CONFIG_NET_VENDOR_TOSHIBA is not set |
| 401 | # CONFIG_NET_VENDOR_VIA is not set | 401 | # CONFIG_NET_VENDOR_VIA is not set |
| 402 | # CONFIG_NET_VENDOR_WIZNET is not set | 402 | # CONFIG_NET_VENDOR_WIZNET is not set |
| 403 | # CONFIG_INPUT_MOUSEDEV is not set | 403 | # CONFIG_INPUT_MOUSEDEV is not set |
| 404 | CONFIG_INPUT_EVDEV=y | 404 | CONFIG_INPUT_EVDEV=y |
| 405 | CONFIG_INPUT_EVBUG=m | 405 | CONFIG_INPUT_EVBUG=m |
| 406 | # CONFIG_INPUT_KEYBOARD is not set | 406 | # CONFIG_INPUT_KEYBOARD is not set |
| 407 | # CONFIG_INPUT_MOUSE is not set | 407 | # CONFIG_INPUT_MOUSE is not set |
| 408 | # CONFIG_SERIO_I8042 is not set | 408 | # CONFIG_SERIO_I8042 is not set |
| 409 | CONFIG_SERIO_SERPORT=m | 409 | CONFIG_SERIO_SERPORT=m |
| 410 | CONFIG_SERIO_LIBPS2=y | 410 | CONFIG_SERIO_LIBPS2=y |
| 411 | CONFIG_SERIO_RAW=m | 411 | CONFIG_SERIO_RAW=m |
| 412 | CONFIG_VT_HW_CONSOLE_BINDING=y | 412 | CONFIG_VT_HW_CONSOLE_BINDING=y |
| 413 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y | 413 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y |
| 414 | CONFIG_LEGACY_PTY_COUNT=0 | 414 | CONFIG_LEGACY_PTY_COUNT=0 |
| 415 | CONFIG_SERIAL_NONSTANDARD=y | 415 | CONFIG_SERIAL_NONSTANDARD=y |
| 416 | CONFIG_N_HDLC=m | 416 | CONFIG_N_HDLC=m |
| 417 | # CONFIG_DEVKMEM is not set | 417 | # CONFIG_DEVKMEM is not set |
| 418 | CONFIG_STALDRV=y | 418 | CONFIG_STALDRV=y |
| 419 | CONFIG_SERIAL_8250=y | 419 | CONFIG_SERIAL_8250=y |
| 420 | CONFIG_SERIAL_8250_CONSOLE=y | 420 | CONFIG_SERIAL_8250_CONSOLE=y |
| 421 | CONFIG_SERIAL_8250_NR_UARTS=48 | 421 | CONFIG_SERIAL_8250_NR_UARTS=48 |
| 422 | CONFIG_SERIAL_8250_EXTENDED=y | 422 | CONFIG_SERIAL_8250_EXTENDED=y |
| 423 | CONFIG_SERIAL_8250_MANY_PORTS=y | 423 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 424 | CONFIG_SERIAL_8250_SHARE_IRQ=y | 424 | CONFIG_SERIAL_8250_SHARE_IRQ=y |
| 425 | CONFIG_SERIAL_8250_RSA=y | 425 | CONFIG_SERIAL_8250_RSA=y |
| 426 | CONFIG_SERIAL_OF_PLATFORM=y | 426 | CONFIG_SERIAL_OF_PLATFORM=y |
| 427 | CONFIG_HW_RANDOM=y | 427 | CONFIG_HW_RANDOM=y |
| 428 | CONFIG_HW_RANDOM_TIMERIOMEM=m | 428 | CONFIG_HW_RANDOM_TIMERIOMEM=m |
| 429 | CONFIG_RAW_DRIVER=m | 429 | CONFIG_RAW_DRIVER=m |
| 430 | CONFIG_I2C=y | 430 | CONFIG_I2C=y |
| 431 | CONFIG_I2C_CHARDEV=y | 431 | CONFIG_I2C_CHARDEV=y |
| 432 | CONFIG_I2C_OCORES=y | 432 | CONFIG_I2C_OCORES=y |
| 433 | CONFIG_SENSORS_LM90=y | 433 | CONFIG_SENSORS_LM90=y |
| 434 | CONFIG_THERMAL=y | 434 | CONFIG_THERMAL=y |
| 435 | # CONFIG_VGA_CONSOLE is not set | 435 | # CONFIG_VGA_CONSOLE is not set |
| 436 | # CONFIG_USB_SUPPORT is not set | 436 | # CONFIG_USB_SUPPORT is not set |
| 437 | CONFIG_RTC_CLASS=y | 437 | CONFIG_RTC_CLASS=y |
| 438 | CONFIG_RTC_DRV_DS1374=y | 438 | CONFIG_RTC_DRV_DS1374=y |
| 439 | CONFIG_UIO=y | 439 | CONFIG_UIO=y |
| 440 | CONFIG_UIO_PDRV=m | 440 | CONFIG_UIO_PDRV=m |
| 441 | CONFIG_UIO_PDRV_GENIRQ=m | 441 | CONFIG_UIO_PDRV_GENIRQ=m |
| 442 | # CONFIG_IOMMU_SUPPORT is not set | 442 | # CONFIG_IOMMU_SUPPORT is not set |
| 443 | CONFIG_EXT2_FS=y | 443 | CONFIG_EXT2_FS=y |
| 444 | CONFIG_EXT2_FS_XATTR=y | 444 | CONFIG_EXT2_FS_XATTR=y |
| 445 | CONFIG_EXT2_FS_POSIX_ACL=y | 445 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 446 | CONFIG_EXT2_FS_SECURITY=y | 446 | CONFIG_EXT2_FS_SECURITY=y |
| 447 | CONFIG_EXT3_FS=y | 447 | CONFIG_EXT3_FS=y |
| 448 | CONFIG_EXT3_FS_POSIX_ACL=y | 448 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 449 | CONFIG_EXT3_FS_SECURITY=y | 449 | CONFIG_EXT3_FS_SECURITY=y |
| 450 | CONFIG_EXT4_FS=y | 450 | CONFIG_EXT4_FS=y |
| 451 | CONFIG_EXT4_FS_POSIX_ACL=y | 451 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 452 | CONFIG_EXT4_FS_SECURITY=y | 452 | CONFIG_EXT4_FS_SECURITY=y |
| 453 | CONFIG_GFS2_FS=m | 453 | CONFIG_GFS2_FS=m |
| 454 | CONFIG_BTRFS_FS=m | 454 | CONFIG_BTRFS_FS=m |
| 455 | CONFIG_BTRFS_FS_POSIX_ACL=y | 455 | CONFIG_BTRFS_FS_POSIX_ACL=y |
| 456 | CONFIG_NILFS2_FS=m | 456 | CONFIG_NILFS2_FS=m |
| 457 | CONFIG_QUOTA_NETLINK_INTERFACE=y | 457 | CONFIG_QUOTA_NETLINK_INTERFACE=y |
| 458 | CONFIG_AUTOFS4_FS=m | 458 | CONFIG_AUTOFS4_FS=m |
| 459 | CONFIG_FUSE_FS=y | 459 | CONFIG_FUSE_FS=y |
| 460 | CONFIG_CUSE=m | 460 | CONFIG_CUSE=m |
| 461 | CONFIG_FSCACHE=m | 461 | CONFIG_FSCACHE=m |
| 462 | CONFIG_FSCACHE_STATS=y | 462 | CONFIG_FSCACHE_STATS=y |
| 463 | CONFIG_FSCACHE_HISTOGRAM=y | 463 | CONFIG_FSCACHE_HISTOGRAM=y |
| 464 | CONFIG_CACHEFILES=m | 464 | CONFIG_CACHEFILES=m |
| 465 | CONFIG_ISO9660_FS=m | 465 | CONFIG_ISO9660_FS=m |
| 466 | CONFIG_JOLIET=y | 466 | CONFIG_JOLIET=y |
| 467 | CONFIG_ZISOFS=y | 467 | CONFIG_ZISOFS=y |
| 468 | CONFIG_UDF_FS=m | 468 | CONFIG_UDF_FS=m |
| 469 | CONFIG_MSDOS_FS=m | 469 | CONFIG_MSDOS_FS=m |
| 470 | CONFIG_VFAT_FS=m | 470 | CONFIG_VFAT_FS=m |
| 471 | CONFIG_NTFS_FS=m | 471 | CONFIG_NTFS_FS=m |
| 472 | CONFIG_PROC_KCORE=y | 472 | CONFIG_PROC_KCORE=y |
| 473 | CONFIG_TMPFS=y | 473 | CONFIG_TMPFS=y |
| 474 | CONFIG_TMPFS_POSIX_ACL=y | 474 | CONFIG_TMPFS_POSIX_ACL=y |
| 475 | CONFIG_ADFS_FS=m | 475 | CONFIG_ADFS_FS=m |
| 476 | CONFIG_AFFS_FS=m | 476 | CONFIG_AFFS_FS=m |
| 477 | CONFIG_ECRYPT_FS=y | 477 | CONFIG_ECRYPT_FS=y |
| 478 | CONFIG_HFS_FS=m | 478 | CONFIG_HFS_FS=m |
| 479 | CONFIG_HFSPLUS_FS=m | 479 | CONFIG_HFSPLUS_FS=m |
| 480 | CONFIG_BEFS_FS=m | 480 | CONFIG_BEFS_FS=m |
| 481 | CONFIG_BFS_FS=m | 481 | CONFIG_BFS_FS=m |
| 482 | CONFIG_EFS_FS=m | 482 | CONFIG_EFS_FS=m |
| 483 | CONFIG_JFFS2_FS=y | 483 | CONFIG_JFFS2_FS=y |
| 484 | CONFIG_CRAMFS=m | 484 | CONFIG_CRAMFS=m |
| 485 | CONFIG_SQUASHFS=m | 485 | CONFIG_SQUASHFS=m |
| 486 | CONFIG_VXFS_FS=m | 486 | CONFIG_VXFS_FS=m |
| 487 | CONFIG_MINIX_FS=m | 487 | CONFIG_MINIX_FS=m |
| 488 | CONFIG_OMFS_FS=m | 488 | CONFIG_OMFS_FS=m |
| 489 | CONFIG_HPFS_FS=m | 489 | CONFIG_HPFS_FS=m |
| 490 | CONFIG_QNX4FS_FS=m | 490 | CONFIG_QNX4FS_FS=m |
| 491 | CONFIG_ROMFS_FS=m | 491 | CONFIG_ROMFS_FS=m |
| 492 | CONFIG_SYSV_FS=m | 492 | CONFIG_SYSV_FS=m |
| 493 | CONFIG_UFS_FS=m | 493 | CONFIG_UFS_FS=m |
| 494 | CONFIG_EXOFS_FS=m | 494 | CONFIG_EXOFS_FS=m |
| 495 | CONFIG_NFS_FS=m | 495 | CONFIG_NFS_FS=m |
| 496 | CONFIG_NFS_V3_ACL=y | 496 | CONFIG_NFS_V3_ACL=y |
| 497 | CONFIG_NFS_V4=y | 497 | CONFIG_NFS_V4=y |
| 498 | CONFIG_NFS_FSCACHE=y | 498 | CONFIG_NFS_FSCACHE=y |
| 499 | CONFIG_NFSD=m | 499 | CONFIG_NFSD=m |
| 500 | CONFIG_NFSD_V3_ACL=y | 500 | CONFIG_NFSD_V3_ACL=y |
| 501 | CONFIG_NFSD_V4=y | 501 | CONFIG_NFSD_V4=y |
| 502 | CONFIG_CIFS=m | 502 | CONFIG_CIFS=m |
| 503 | CONFIG_CIFS_WEAK_PW_HASH=y | 503 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 504 | CONFIG_CIFS_UPCALL=y | 504 | CONFIG_CIFS_UPCALL=y |
| 505 | CONFIG_CIFS_XATTR=y | 505 | CONFIG_CIFS_XATTR=y |
| 506 | CONFIG_CIFS_POSIX=y | 506 | CONFIG_CIFS_POSIX=y |
| 507 | CONFIG_CIFS_DFS_UPCALL=y | 507 | CONFIG_CIFS_DFS_UPCALL=y |
| 508 | CONFIG_NCP_FS=m | 508 | CONFIG_NCP_FS=m |
| 509 | CONFIG_NCPFS_PACKET_SIGNING=y | 509 | CONFIG_NCPFS_PACKET_SIGNING=y |
| 510 | CONFIG_NCPFS_IOCTL_LOCKING=y | 510 | CONFIG_NCPFS_IOCTL_LOCKING=y |
| 511 | CONFIG_NCPFS_STRONG=y | 511 | CONFIG_NCPFS_STRONG=y |
| 512 | CONFIG_NCPFS_NFS_NS=y | 512 | CONFIG_NCPFS_NFS_NS=y |
| 513 | CONFIG_NCPFS_OS2_NS=y | 513 | CONFIG_NCPFS_OS2_NS=y |
| 514 | CONFIG_NCPFS_NLS=y | 514 | CONFIG_NCPFS_NLS=y |
| 515 | CONFIG_NCPFS_EXTRAS=y | 515 | CONFIG_NCPFS_EXTRAS=y |
| 516 | CONFIG_CODA_FS=m | 516 | CONFIG_CODA_FS=m |
| 517 | CONFIG_AFS_FS=m | 517 | CONFIG_AFS_FS=m |
| 518 | CONFIG_NLS=y | 518 | CONFIG_NLS=y |
| 519 | CONFIG_NLS_DEFAULT="cp437" | 519 | CONFIG_NLS_DEFAULT="cp437" |
| 520 | CONFIG_NLS_CODEPAGE_437=m | 520 | CONFIG_NLS_CODEPAGE_437=m |
| 521 | CONFIG_NLS_CODEPAGE_737=m | 521 | CONFIG_NLS_CODEPAGE_737=m |
| 522 | CONFIG_NLS_CODEPAGE_775=m | 522 | CONFIG_NLS_CODEPAGE_775=m |
| 523 | CONFIG_NLS_CODEPAGE_850=m | 523 | CONFIG_NLS_CODEPAGE_850=m |
| 524 | CONFIG_NLS_CODEPAGE_852=m | 524 | CONFIG_NLS_CODEPAGE_852=m |
| 525 | CONFIG_NLS_CODEPAGE_855=m | 525 | CONFIG_NLS_CODEPAGE_855=m |
| 526 | CONFIG_NLS_CODEPAGE_857=m | 526 | CONFIG_NLS_CODEPAGE_857=m |
| 527 | CONFIG_NLS_CODEPAGE_860=m | 527 | CONFIG_NLS_CODEPAGE_860=m |
| 528 | CONFIG_NLS_CODEPAGE_861=m | 528 | CONFIG_NLS_CODEPAGE_861=m |
| 529 | CONFIG_NLS_CODEPAGE_862=m | 529 | CONFIG_NLS_CODEPAGE_862=m |
| 530 | CONFIG_NLS_CODEPAGE_863=m | 530 | CONFIG_NLS_CODEPAGE_863=m |
| 531 | CONFIG_NLS_CODEPAGE_864=m | 531 | CONFIG_NLS_CODEPAGE_864=m |
| 532 | CONFIG_NLS_CODEPAGE_865=m | 532 | CONFIG_NLS_CODEPAGE_865=m |
| 533 | CONFIG_NLS_CODEPAGE_866=m | 533 | CONFIG_NLS_CODEPAGE_866=m |
| 534 | CONFIG_NLS_CODEPAGE_869=m | 534 | CONFIG_NLS_CODEPAGE_869=m |
| 535 | CONFIG_NLS_CODEPAGE_936=m | 535 | CONFIG_NLS_CODEPAGE_936=m |
| 536 | CONFIG_NLS_CODEPAGE_950=m | 536 | CONFIG_NLS_CODEPAGE_950=m |
| 537 | CONFIG_NLS_CODEPAGE_932=m | 537 | CONFIG_NLS_CODEPAGE_932=m |
| 538 | CONFIG_NLS_CODEPAGE_949=m | 538 | CONFIG_NLS_CODEPAGE_949=m |
| 539 | CONFIG_NLS_CODEPAGE_874=m | 539 | CONFIG_NLS_CODEPAGE_874=m |
| 540 | CONFIG_NLS_ISO8859_8=m | 540 | CONFIG_NLS_ISO8859_8=m |
| 541 | CONFIG_NLS_CODEPAGE_1250=m | 541 | CONFIG_NLS_CODEPAGE_1250=m |
| 542 | CONFIG_NLS_CODEPAGE_1251=m | 542 | CONFIG_NLS_CODEPAGE_1251=m |
| 543 | CONFIG_NLS_ASCII=m | 543 | CONFIG_NLS_ASCII=m |
| 544 | CONFIG_NLS_ISO8859_1=m | 544 | CONFIG_NLS_ISO8859_1=m |
| 545 | CONFIG_NLS_ISO8859_2=m | 545 | CONFIG_NLS_ISO8859_2=m |
| 546 | CONFIG_NLS_ISO8859_3=m | 546 | CONFIG_NLS_ISO8859_3=m |
| 547 | CONFIG_NLS_ISO8859_4=m | 547 | CONFIG_NLS_ISO8859_4=m |
| 548 | CONFIG_NLS_ISO8859_5=m | 548 | CONFIG_NLS_ISO8859_5=m |
| 549 | CONFIG_NLS_ISO8859_6=m | 549 | CONFIG_NLS_ISO8859_6=m |
| 550 | CONFIG_NLS_ISO8859_7=m | 550 | CONFIG_NLS_ISO8859_7=m |
| 551 | CONFIG_NLS_ISO8859_9=m | 551 | CONFIG_NLS_ISO8859_9=m |
| 552 | CONFIG_NLS_ISO8859_13=m | 552 | CONFIG_NLS_ISO8859_13=m |
| 553 | CONFIG_NLS_ISO8859_14=m | 553 | CONFIG_NLS_ISO8859_14=m |
| 554 | CONFIG_NLS_ISO8859_15=m | 554 | CONFIG_NLS_ISO8859_15=m |
| 555 | CONFIG_NLS_KOI8_R=m | 555 | CONFIG_NLS_KOI8_R=m |
| 556 | CONFIG_NLS_KOI8_U=m | 556 | CONFIG_NLS_KOI8_U=m |
| 557 | CONFIG_PRINTK_TIME=y | 557 | CONFIG_PRINTK_TIME=y |
| 558 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 558 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 559 | # CONFIG_ENABLE_MUST_CHECK is not set | 559 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 560 | CONFIG_FRAME_WARN=1024 | 560 | CONFIG_FRAME_WARN=1024 |
| 561 | CONFIG_UNUSED_SYMBOLS=y | 561 | CONFIG_UNUSED_SYMBOLS=y |
| 562 | CONFIG_DETECT_HUNG_TASK=y | 562 | CONFIG_DETECT_HUNG_TASK=y |
| 563 | CONFIG_SCHEDSTATS=y | 563 | CONFIG_SCHEDSTATS=y |
| 564 | CONFIG_TIMER_STATS=y | 564 | CONFIG_TIMER_STATS=y |
| 565 | CONFIG_DEBUG_INFO=y | 565 | CONFIG_DEBUG_INFO=y |
| 566 | CONFIG_DEBUG_MEMORY_INIT=y | 566 | CONFIG_DEBUG_MEMORY_INIT=y |
| 567 | CONFIG_SCHED_TRACER=y | 567 | CONFIG_SCHED_TRACER=y |
| 568 | CONFIG_BLK_DEV_IO_TRACE=y | 568 | CONFIG_BLK_DEV_IO_TRACE=y |
| 569 | CONFIG_KGDB=y | 569 | CONFIG_KGDB=y |
| 570 | CONFIG_SECURITY=y | 570 | CONFIG_SECURITY=y |
| 571 | CONFIG_LSM_MMAP_MIN_ADDR=0 | 571 | CONFIG_LSM_MMAP_MIN_ADDR=0 |
| 572 | CONFIG_SECURITY_SELINUX=y | 572 | CONFIG_SECURITY_SELINUX=y |
| 573 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y | 573 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y |
| 574 | CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 | 574 | CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 |
| 575 | CONFIG_SECURITY_SELINUX_DISABLE=y | 575 | CONFIG_SECURITY_SELINUX_DISABLE=y |
| 576 | CONFIG_SECURITY_SMACK=y | 576 | CONFIG_SECURITY_SMACK=y |
| 577 | CONFIG_SECURITY_TOMOYO=y | 577 | CONFIG_SECURITY_TOMOYO=y |
| 578 | CONFIG_CRYPTO_NULL=m | 578 | CONFIG_CRYPTO_NULL=m |
| 579 | CONFIG_CRYPTO_CRYPTD=m | 579 | CONFIG_CRYPTO_CRYPTD=m |
| 580 | CONFIG_CRYPTO_TEST=m | 580 | CONFIG_CRYPTO_TEST=m |
| 581 | CONFIG_CRYPTO_CCM=m | 581 | CONFIG_CRYPTO_CCM=m |
| 582 | CONFIG_CRYPTO_GCM=m | 582 | CONFIG_CRYPTO_GCM=m |
| 583 | CONFIG_CRYPTO_CTS=m | 583 | CONFIG_CRYPTO_CTS=m |
| 584 | CONFIG_CRYPTO_LRW=m | 584 | CONFIG_CRYPTO_LRW=m |
| 585 | CONFIG_CRYPTO_PCBC=m | 585 | CONFIG_CRYPTO_PCBC=m |
| 586 | CONFIG_CRYPTO_XTS=m | 586 | CONFIG_CRYPTO_XTS=m |
| 587 | CONFIG_CRYPTO_HMAC=y | 587 | CONFIG_CRYPTO_HMAC=y |
| 588 | CONFIG_CRYPTO_XCBC=m | 588 | CONFIG_CRYPTO_XCBC=m |
| 589 | CONFIG_CRYPTO_VMAC=m | 589 | CONFIG_CRYPTO_VMAC=m |
| 590 | CONFIG_CRYPTO_MICHAEL_MIC=m | 590 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 591 | CONFIG_CRYPTO_RMD128=m | 591 | CONFIG_CRYPTO_RMD128=m |
| 592 | CONFIG_CRYPTO_RMD160=m | 592 | CONFIG_CRYPTO_RMD160=m |
| 593 | CONFIG_CRYPTO_RMD256=m | 593 | CONFIG_CRYPTO_RMD256=m |
| 594 | CONFIG_CRYPTO_RMD320=m | 594 | CONFIG_CRYPTO_RMD320=m |
| 595 | CONFIG_CRYPTO_SHA256=m | 595 | CONFIG_CRYPTO_SHA256=m |
| 596 | CONFIG_CRYPTO_SHA512=m | 596 | CONFIG_CRYPTO_SHA512=m |
| 597 | CONFIG_CRYPTO_TGR192=m | 597 | CONFIG_CRYPTO_TGR192=m |
| 598 | CONFIG_CRYPTO_WP512=m | 598 | CONFIG_CRYPTO_WP512=m |
| 599 | CONFIG_CRYPTO_ANUBIS=m | 599 | CONFIG_CRYPTO_ANUBIS=m |
| 600 | CONFIG_CRYPTO_BLOWFISH=m | 600 | CONFIG_CRYPTO_BLOWFISH=m |
| 601 | CONFIG_CRYPTO_CAMELLIA=m | 601 | CONFIG_CRYPTO_CAMELLIA=m |
| 602 | CONFIG_CRYPTO_CAST5=m | 602 | CONFIG_CRYPTO_CAST5=m |
| 603 | CONFIG_CRYPTO_CAST6=m | 603 | CONFIG_CRYPTO_CAST6=m |
| 604 | CONFIG_CRYPTO_FCRYPT=m | 604 | CONFIG_CRYPTO_FCRYPT=m |
| 605 | CONFIG_CRYPTO_KHAZAD=m | 605 | CONFIG_CRYPTO_KHAZAD=m |
| 606 | CONFIG_CRYPTO_SALSA20=m | 606 | CONFIG_CRYPTO_SALSA20=m |
| 607 | CONFIG_CRYPTO_SEED=m | 607 | CONFIG_CRYPTO_SEED=m |
| 608 | CONFIG_CRYPTO_SERPENT=m | 608 | CONFIG_CRYPTO_SERPENT=m |
| 609 | CONFIG_CRYPTO_TEA=m | 609 | CONFIG_CRYPTO_TEA=m |
| 610 | CONFIG_CRYPTO_TWOFISH=m | 610 | CONFIG_CRYPTO_TWOFISH=m |
| 611 | CONFIG_CRYPTO_ZLIB=m | 611 | CONFIG_CRYPTO_ZLIB=m |
| 612 | CONFIG_CRYPTO_LZO=m | 612 | CONFIG_CRYPTO_LZO=m |
| 613 | CONFIG_CRC_CCITT=m | 613 | CONFIG_CRC_CCITT=m |
| 614 | CONFIG_CRC7=m | 614 | CONFIG_CRC7=m |
| 615 | 615 |
arch/mips/configs/nlm_xlr_defconfig
| 1 | CONFIG_NLM_XLR_BOARD=y | 1 | CONFIG_NLM_XLR_BOARD=y |
| 2 | CONFIG_HIGHMEM=y | 2 | CONFIG_HIGHMEM=y |
| 3 | CONFIG_KSM=y | 3 | CONFIG_KSM=y |
| 4 | CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 | 4 | CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 |
| 5 | CONFIG_SMP=y | 5 | CONFIG_SMP=y |
| 6 | CONFIG_NO_HZ=y | 6 | CONFIG_NO_HZ=y |
| 7 | CONFIG_HIGH_RES_TIMERS=y | 7 | CONFIG_HIGH_RES_TIMERS=y |
| 8 | CONFIG_PREEMPT_VOLUNTARY=y | 8 | CONFIG_PREEMPT_VOLUNTARY=y |
| 9 | CONFIG_KEXEC=y | 9 | CONFIG_KEXEC=y |
| 10 | CONFIG_EXPERIMENTAL=y | 10 | CONFIG_EXPERIMENTAL=y |
| 11 | CONFIG_CROSS_COMPILE="" | 11 | CONFIG_CROSS_COMPILE="" |
| 12 | # CONFIG_LOCALVERSION_AUTO is not set | 12 | # CONFIG_LOCALVERSION_AUTO is not set |
| 13 | CONFIG_SYSVIPC=y | 13 | CONFIG_SYSVIPC=y |
| 14 | CONFIG_POSIX_MQUEUE=y | 14 | CONFIG_POSIX_MQUEUE=y |
| 15 | CONFIG_BSD_PROCESS_ACCT=y | 15 | CONFIG_BSD_PROCESS_ACCT=y |
| 16 | CONFIG_BSD_PROCESS_ACCT_V3=y | 16 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 17 | CONFIG_TASKSTATS=y | 17 | CONFIG_TASKSTATS=y |
| 18 | CONFIG_TASK_DELAY_ACCT=y | 18 | CONFIG_TASK_DELAY_ACCT=y |
| 19 | CONFIG_TASK_XACCT=y | 19 | CONFIG_TASK_XACCT=y |
| 20 | CONFIG_TASK_IO_ACCOUNTING=y | 20 | CONFIG_TASK_IO_ACCOUNTING=y |
| 21 | CONFIG_AUDIT=y | 21 | CONFIG_AUDIT=y |
| 22 | CONFIG_NAMESPACES=y | 22 | CONFIG_NAMESPACES=y |
| 23 | CONFIG_SCHED_AUTOGROUP=y | 23 | CONFIG_SCHED_AUTOGROUP=y |
| 24 | CONFIG_BLK_DEV_INITRD=y | 24 | CONFIG_BLK_DEV_INITRD=y |
| 25 | CONFIG_INITRAMFS_SOURCE="" | 25 | CONFIG_INITRAMFS_SOURCE="" |
| 26 | CONFIG_RD_BZIP2=y | 26 | CONFIG_RD_BZIP2=y |
| 27 | CONFIG_RD_LZMA=y | 27 | CONFIG_RD_LZMA=y |
| 28 | CONFIG_INITRAMFS_COMPRESSION_GZIP=y | 28 | CONFIG_INITRAMFS_COMPRESSION_GZIP=y |
| 29 | CONFIG_EXPERT=y | 29 | CONFIG_EXPERT=y |
| 30 | CONFIG_KALLSYMS_ALL=y | 30 | CONFIG_KALLSYMS_ALL=y |
| 31 | # CONFIG_ELF_CORE is not set | 31 | # CONFIG_ELF_CORE is not set |
| 32 | # CONFIG_PERF_EVENTS is not set | 32 | # CONFIG_PERF_EVENTS is not set |
| 33 | # CONFIG_COMPAT_BRK is not set | 33 | # CONFIG_COMPAT_BRK is not set |
| 34 | CONFIG_PROFILING=y | 34 | CONFIG_PROFILING=y |
| 35 | CONFIG_MODULES=y | 35 | CONFIG_MODULES=y |
| 36 | CONFIG_MODULE_UNLOAD=y | 36 | CONFIG_MODULE_UNLOAD=y |
| 37 | CONFIG_MODVERSIONS=y | 37 | CONFIG_MODVERSIONS=y |
| 38 | CONFIG_MODULE_SRCVERSION_ALL=y | 38 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 39 | CONFIG_BLK_DEV_INTEGRITY=y | 39 | CONFIG_BLK_DEV_INTEGRITY=y |
| 40 | CONFIG_PCI=y | 40 | CONFIG_PCI=y |
| 41 | CONFIG_PCI_MSI=y | 41 | CONFIG_PCI_MSI=y |
| 42 | CONFIG_PCI_DEBUG=y | 42 | CONFIG_PCI_DEBUG=y |
| 43 | CONFIG_BINFMT_MISC=m | 43 | CONFIG_BINFMT_MISC=m |
| 44 | CONFIG_PM_RUNTIME=y | 44 | CONFIG_PM=y |
| 45 | CONFIG_PM_DEBUG=y | 45 | CONFIG_PM_DEBUG=y |
| 46 | CONFIG_NET=y | 46 | CONFIG_NET=y |
| 47 | CONFIG_PACKET=y | 47 | CONFIG_PACKET=y |
| 48 | CONFIG_UNIX=y | 48 | CONFIG_UNIX=y |
| 49 | CONFIG_XFRM_USER=m | 49 | CONFIG_XFRM_USER=m |
| 50 | CONFIG_NET_KEY=m | 50 | CONFIG_NET_KEY=m |
| 51 | CONFIG_INET=y | 51 | CONFIG_INET=y |
| 52 | CONFIG_IP_MULTICAST=y | 52 | CONFIG_IP_MULTICAST=y |
| 53 | CONFIG_IP_ADVANCED_ROUTER=y | 53 | CONFIG_IP_ADVANCED_ROUTER=y |
| 54 | CONFIG_IP_MULTIPLE_TABLES=y | 54 | CONFIG_IP_MULTIPLE_TABLES=y |
| 55 | CONFIG_IP_ROUTE_MULTIPATH=y | 55 | CONFIG_IP_ROUTE_MULTIPATH=y |
| 56 | CONFIG_IP_ROUTE_VERBOSE=y | 56 | CONFIG_IP_ROUTE_VERBOSE=y |
| 57 | CONFIG_NET_IPIP=m | 57 | CONFIG_NET_IPIP=m |
| 58 | CONFIG_IP_MROUTE=y | 58 | CONFIG_IP_MROUTE=y |
| 59 | CONFIG_IP_PIMSM_V1=y | 59 | CONFIG_IP_PIMSM_V1=y |
| 60 | CONFIG_IP_PIMSM_V2=y | 60 | CONFIG_IP_PIMSM_V2=y |
| 61 | CONFIG_SYN_COOKIES=y | 61 | CONFIG_SYN_COOKIES=y |
| 62 | CONFIG_INET_AH=m | 62 | CONFIG_INET_AH=m |
| 63 | CONFIG_INET_ESP=m | 63 | CONFIG_INET_ESP=m |
| 64 | CONFIG_INET_IPCOMP=m | 64 | CONFIG_INET_IPCOMP=m |
| 65 | CONFIG_INET_XFRM_MODE_TRANSPORT=m | 65 | CONFIG_INET_XFRM_MODE_TRANSPORT=m |
| 66 | CONFIG_INET_XFRM_MODE_TUNNEL=m | 66 | CONFIG_INET_XFRM_MODE_TUNNEL=m |
| 67 | CONFIG_INET_XFRM_MODE_BEET=m | 67 | CONFIG_INET_XFRM_MODE_BEET=m |
| 68 | CONFIG_TCP_CONG_ADVANCED=y | 68 | CONFIG_TCP_CONG_ADVANCED=y |
| 69 | CONFIG_TCP_CONG_HSTCP=m | 69 | CONFIG_TCP_CONG_HSTCP=m |
| 70 | CONFIG_TCP_CONG_HYBLA=m | 70 | CONFIG_TCP_CONG_HYBLA=m |
| 71 | CONFIG_TCP_CONG_SCALABLE=m | 71 | CONFIG_TCP_CONG_SCALABLE=m |
| 72 | CONFIG_TCP_CONG_LP=m | 72 | CONFIG_TCP_CONG_LP=m |
| 73 | CONFIG_TCP_CONG_VENO=m | 73 | CONFIG_TCP_CONG_VENO=m |
| 74 | CONFIG_TCP_CONG_YEAH=m | 74 | CONFIG_TCP_CONG_YEAH=m |
| 75 | CONFIG_TCP_CONG_ILLINOIS=m | 75 | CONFIG_TCP_CONG_ILLINOIS=m |
| 76 | CONFIG_TCP_MD5SIG=y | 76 | CONFIG_TCP_MD5SIG=y |
| 77 | CONFIG_IPV6=y | 77 | CONFIG_IPV6=y |
| 78 | CONFIG_IPV6_PRIVACY=y | 78 | CONFIG_IPV6_PRIVACY=y |
| 79 | CONFIG_INET6_AH=m | 79 | CONFIG_INET6_AH=m |
| 80 | CONFIG_INET6_ESP=m | 80 | CONFIG_INET6_ESP=m |
| 81 | CONFIG_INET6_IPCOMP=m | 81 | CONFIG_INET6_IPCOMP=m |
| 82 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | 82 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m |
| 83 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | 83 | CONFIG_INET6_XFRM_MODE_TUNNEL=m |
| 84 | CONFIG_INET6_XFRM_MODE_BEET=m | 84 | CONFIG_INET6_XFRM_MODE_BEET=m |
| 85 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | 85 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m |
| 86 | CONFIG_IPV6_SIT=m | 86 | CONFIG_IPV6_SIT=m |
| 87 | CONFIG_IPV6_TUNNEL=m | 87 | CONFIG_IPV6_TUNNEL=m |
| 88 | CONFIG_IPV6_MULTIPLE_TABLES=y | 88 | CONFIG_IPV6_MULTIPLE_TABLES=y |
| 89 | CONFIG_NETLABEL=y | 89 | CONFIG_NETLABEL=y |
| 90 | CONFIG_NETFILTER=y | 90 | CONFIG_NETFILTER=y |
| 91 | CONFIG_NF_CONNTRACK=m | 91 | CONFIG_NF_CONNTRACK=m |
| 92 | CONFIG_NF_CONNTRACK_SECMARK=y | 92 | CONFIG_NF_CONNTRACK_SECMARK=y |
| 93 | CONFIG_NF_CONNTRACK_EVENTS=y | 93 | CONFIG_NF_CONNTRACK_EVENTS=y |
| 94 | CONFIG_NF_CT_PROTO_UDPLITE=m | 94 | CONFIG_NF_CT_PROTO_UDPLITE=m |
| 95 | CONFIG_NF_CONNTRACK_AMANDA=m | 95 | CONFIG_NF_CONNTRACK_AMANDA=m |
| 96 | CONFIG_NF_CONNTRACK_FTP=m | 96 | CONFIG_NF_CONNTRACK_FTP=m |
| 97 | CONFIG_NF_CONNTRACK_H323=m | 97 | CONFIG_NF_CONNTRACK_H323=m |
| 98 | CONFIG_NF_CONNTRACK_IRC=m | 98 | CONFIG_NF_CONNTRACK_IRC=m |
| 99 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m | 99 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m |
| 100 | CONFIG_NF_CONNTRACK_PPTP=m | 100 | CONFIG_NF_CONNTRACK_PPTP=m |
| 101 | CONFIG_NF_CONNTRACK_SANE=m | 101 | CONFIG_NF_CONNTRACK_SANE=m |
| 102 | CONFIG_NF_CONNTRACK_SIP=m | 102 | CONFIG_NF_CONNTRACK_SIP=m |
| 103 | CONFIG_NF_CONNTRACK_TFTP=m | 103 | CONFIG_NF_CONNTRACK_TFTP=m |
| 104 | CONFIG_NF_CT_NETLINK=m | 104 | CONFIG_NF_CT_NETLINK=m |
| 105 | CONFIG_NETFILTER_TPROXY=m | 105 | CONFIG_NETFILTER_TPROXY=m |
| 106 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 106 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 107 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m | 107 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m |
| 108 | CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m | 108 | CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m |
| 109 | CONFIG_NETFILTER_XT_TARGET_DSCP=m | 109 | CONFIG_NETFILTER_XT_TARGET_DSCP=m |
| 110 | CONFIG_NETFILTER_XT_TARGET_MARK=m | 110 | CONFIG_NETFILTER_XT_TARGET_MARK=m |
| 111 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | 111 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m |
| 112 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | 112 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m |
| 113 | CONFIG_NETFILTER_XT_TARGET_TPROXY=m | 113 | CONFIG_NETFILTER_XT_TARGET_TPROXY=m |
| 114 | CONFIG_NETFILTER_XT_TARGET_TRACE=m | 114 | CONFIG_NETFILTER_XT_TARGET_TRACE=m |
| 115 | CONFIG_NETFILTER_XT_TARGET_SECMARK=m | 115 | CONFIG_NETFILTER_XT_TARGET_SECMARK=m |
| 116 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | 116 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m |
| 117 | CONFIG_NETFILTER_XT_MATCH_CLUSTER=m | 117 | CONFIG_NETFILTER_XT_MATCH_CLUSTER=m |
| 118 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | 118 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m |
| 119 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | 119 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m |
| 120 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | 120 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m |
| 121 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m | 121 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m |
| 122 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | 122 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m |
| 123 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | 123 | CONFIG_NETFILTER_XT_MATCH_DSCP=m |
| 124 | CONFIG_NETFILTER_XT_MATCH_ESP=m | 124 | CONFIG_NETFILTER_XT_MATCH_ESP=m |
| 125 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | 125 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m |
| 126 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | 126 | CONFIG_NETFILTER_XT_MATCH_HELPER=m |
| 127 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=m | 127 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=m |
| 128 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | 128 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m |
| 129 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | 129 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m |
| 130 | CONFIG_NETFILTER_XT_MATCH_MAC=m | 130 | CONFIG_NETFILTER_XT_MATCH_MAC=m |
| 131 | CONFIG_NETFILTER_XT_MATCH_MARK=m | 131 | CONFIG_NETFILTER_XT_MATCH_MARK=m |
| 132 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | 132 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m |
| 133 | CONFIG_NETFILTER_XT_MATCH_OSF=m | 133 | CONFIG_NETFILTER_XT_MATCH_OSF=m |
| 134 | CONFIG_NETFILTER_XT_MATCH_OWNER=m | 134 | CONFIG_NETFILTER_XT_MATCH_OWNER=m |
| 135 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | 135 | CONFIG_NETFILTER_XT_MATCH_POLICY=m |
| 136 | CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m | 136 | CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m |
| 137 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | 137 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m |
| 138 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | 138 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m |
| 139 | CONFIG_NETFILTER_XT_MATCH_RATEEST=m | 139 | CONFIG_NETFILTER_XT_MATCH_RATEEST=m |
| 140 | CONFIG_NETFILTER_XT_MATCH_REALM=m | 140 | CONFIG_NETFILTER_XT_MATCH_REALM=m |
| 141 | CONFIG_NETFILTER_XT_MATCH_RECENT=m | 141 | CONFIG_NETFILTER_XT_MATCH_RECENT=m |
| 142 | CONFIG_NETFILTER_XT_MATCH_SOCKET=m | 142 | CONFIG_NETFILTER_XT_MATCH_SOCKET=m |
| 143 | CONFIG_NETFILTER_XT_MATCH_STATE=m | 143 | CONFIG_NETFILTER_XT_MATCH_STATE=m |
| 144 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | 144 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m |
| 145 | CONFIG_NETFILTER_XT_MATCH_STRING=m | 145 | CONFIG_NETFILTER_XT_MATCH_STRING=m |
| 146 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 146 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 147 | CONFIG_NETFILTER_XT_MATCH_TIME=m | 147 | CONFIG_NETFILTER_XT_MATCH_TIME=m |
| 148 | CONFIG_NETFILTER_XT_MATCH_U32=m | 148 | CONFIG_NETFILTER_XT_MATCH_U32=m |
| 149 | CONFIG_IP_VS=m | 149 | CONFIG_IP_VS=m |
| 150 | CONFIG_IP_VS_IPV6=y | 150 | CONFIG_IP_VS_IPV6=y |
| 151 | CONFIG_IP_VS_PROTO_TCP=y | 151 | CONFIG_IP_VS_PROTO_TCP=y |
| 152 | CONFIG_IP_VS_PROTO_UDP=y | 152 | CONFIG_IP_VS_PROTO_UDP=y |
| 153 | CONFIG_IP_VS_PROTO_ESP=y | 153 | CONFIG_IP_VS_PROTO_ESP=y |
| 154 | CONFIG_IP_VS_PROTO_AH=y | 154 | CONFIG_IP_VS_PROTO_AH=y |
| 155 | CONFIG_IP_VS_RR=m | 155 | CONFIG_IP_VS_RR=m |
| 156 | CONFIG_IP_VS_WRR=m | 156 | CONFIG_IP_VS_WRR=m |
| 157 | CONFIG_IP_VS_LC=m | 157 | CONFIG_IP_VS_LC=m |
| 158 | CONFIG_IP_VS_WLC=m | 158 | CONFIG_IP_VS_WLC=m |
| 159 | CONFIG_IP_VS_LBLC=m | 159 | CONFIG_IP_VS_LBLC=m |
| 160 | CONFIG_IP_VS_LBLCR=m | 160 | CONFIG_IP_VS_LBLCR=m |
| 161 | CONFIG_IP_VS_DH=m | 161 | CONFIG_IP_VS_DH=m |
| 162 | CONFIG_IP_VS_SH=m | 162 | CONFIG_IP_VS_SH=m |
| 163 | CONFIG_IP_VS_SED=m | 163 | CONFIG_IP_VS_SED=m |
| 164 | CONFIG_IP_VS_NQ=m | 164 | CONFIG_IP_VS_NQ=m |
| 165 | CONFIG_IP_VS_FTP=m | 165 | CONFIG_IP_VS_FTP=m |
| 166 | CONFIG_NF_CONNTRACK_IPV4=m | 166 | CONFIG_NF_CONNTRACK_IPV4=m |
| 167 | CONFIG_IP_NF_QUEUE=m | 167 | CONFIG_IP_NF_QUEUE=m |
| 168 | CONFIG_IP_NF_IPTABLES=m | 168 | CONFIG_IP_NF_IPTABLES=m |
| 169 | CONFIG_IP_NF_MATCH_AH=m | 169 | CONFIG_IP_NF_MATCH_AH=m |
| 170 | CONFIG_IP_NF_MATCH_ECN=m | 170 | CONFIG_IP_NF_MATCH_ECN=m |
| 171 | CONFIG_IP_NF_MATCH_TTL=m | 171 | CONFIG_IP_NF_MATCH_TTL=m |
| 172 | CONFIG_IP_NF_FILTER=m | 172 | CONFIG_IP_NF_FILTER=m |
| 173 | CONFIG_IP_NF_TARGET_REJECT=m | 173 | CONFIG_IP_NF_TARGET_REJECT=m |
| 174 | CONFIG_IP_NF_TARGET_LOG=m | 174 | CONFIG_IP_NF_TARGET_LOG=m |
| 175 | CONFIG_IP_NF_TARGET_ULOG=m | 175 | CONFIG_IP_NF_TARGET_ULOG=m |
| 176 | CONFIG_NF_NAT=m | 176 | CONFIG_NF_NAT=m |
| 177 | CONFIG_IP_NF_TARGET_MASQUERADE=m | 177 | CONFIG_IP_NF_TARGET_MASQUERADE=m |
| 178 | CONFIG_IP_NF_TARGET_NETMAP=m | 178 | CONFIG_IP_NF_TARGET_NETMAP=m |
| 179 | CONFIG_IP_NF_TARGET_REDIRECT=m | 179 | CONFIG_IP_NF_TARGET_REDIRECT=m |
| 180 | CONFIG_IP_NF_MANGLE=m | 180 | CONFIG_IP_NF_MANGLE=m |
| 181 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | 181 | CONFIG_IP_NF_TARGET_CLUSTERIP=m |
| 182 | CONFIG_IP_NF_TARGET_ECN=m | 182 | CONFIG_IP_NF_TARGET_ECN=m |
| 183 | CONFIG_IP_NF_TARGET_TTL=m | 183 | CONFIG_IP_NF_TARGET_TTL=m |
| 184 | CONFIG_IP_NF_RAW=m | 184 | CONFIG_IP_NF_RAW=m |
| 185 | CONFIG_IP_NF_SECURITY=m | 185 | CONFIG_IP_NF_SECURITY=m |
| 186 | CONFIG_IP_NF_ARPTABLES=m | 186 | CONFIG_IP_NF_ARPTABLES=m |
| 187 | CONFIG_IP_NF_ARPFILTER=m | 187 | CONFIG_IP_NF_ARPFILTER=m |
| 188 | CONFIG_IP_NF_ARP_MANGLE=m | 188 | CONFIG_IP_NF_ARP_MANGLE=m |
| 189 | CONFIG_NF_CONNTRACK_IPV6=m | 189 | CONFIG_NF_CONNTRACK_IPV6=m |
| 190 | CONFIG_IP6_NF_QUEUE=m | 190 | CONFIG_IP6_NF_QUEUE=m |
| 191 | CONFIG_IP6_NF_IPTABLES=m | 191 | CONFIG_IP6_NF_IPTABLES=m |
| 192 | CONFIG_IP6_NF_MATCH_AH=m | 192 | CONFIG_IP6_NF_MATCH_AH=m |
| 193 | CONFIG_IP6_NF_MATCH_EUI64=m | 193 | CONFIG_IP6_NF_MATCH_EUI64=m |
| 194 | CONFIG_IP6_NF_MATCH_FRAG=m | 194 | CONFIG_IP6_NF_MATCH_FRAG=m |
| 195 | CONFIG_IP6_NF_MATCH_OPTS=m | 195 | CONFIG_IP6_NF_MATCH_OPTS=m |
| 196 | CONFIG_IP6_NF_MATCH_HL=m | 196 | CONFIG_IP6_NF_MATCH_HL=m |
| 197 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | 197 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m |
| 198 | CONFIG_IP6_NF_MATCH_MH=m | 198 | CONFIG_IP6_NF_MATCH_MH=m |
| 199 | CONFIG_IP6_NF_MATCH_RT=m | 199 | CONFIG_IP6_NF_MATCH_RT=m |
| 200 | CONFIG_IP6_NF_TARGET_HL=m | 200 | CONFIG_IP6_NF_TARGET_HL=m |
| 201 | CONFIG_IP6_NF_TARGET_LOG=m | 201 | CONFIG_IP6_NF_TARGET_LOG=m |
| 202 | CONFIG_IP6_NF_FILTER=m | 202 | CONFIG_IP6_NF_FILTER=m |
| 203 | CONFIG_IP6_NF_TARGET_REJECT=m | 203 | CONFIG_IP6_NF_TARGET_REJECT=m |
| 204 | CONFIG_IP6_NF_MANGLE=m | 204 | CONFIG_IP6_NF_MANGLE=m |
| 205 | CONFIG_IP6_NF_RAW=m | 205 | CONFIG_IP6_NF_RAW=m |
| 206 | CONFIG_IP6_NF_SECURITY=m | 206 | CONFIG_IP6_NF_SECURITY=m |
| 207 | CONFIG_DECNET_NF_GRABULATOR=m | 207 | CONFIG_DECNET_NF_GRABULATOR=m |
| 208 | CONFIG_BRIDGE_NF_EBTABLES=m | 208 | CONFIG_BRIDGE_NF_EBTABLES=m |
| 209 | CONFIG_BRIDGE_EBT_BROUTE=m | 209 | CONFIG_BRIDGE_EBT_BROUTE=m |
| 210 | CONFIG_BRIDGE_EBT_T_FILTER=m | 210 | CONFIG_BRIDGE_EBT_T_FILTER=m |
| 211 | CONFIG_BRIDGE_EBT_T_NAT=m | 211 | CONFIG_BRIDGE_EBT_T_NAT=m |
| 212 | CONFIG_BRIDGE_EBT_802_3=m | 212 | CONFIG_BRIDGE_EBT_802_3=m |
| 213 | CONFIG_BRIDGE_EBT_AMONG=m | 213 | CONFIG_BRIDGE_EBT_AMONG=m |
| 214 | CONFIG_BRIDGE_EBT_ARP=m | 214 | CONFIG_BRIDGE_EBT_ARP=m |
| 215 | CONFIG_BRIDGE_EBT_IP=m | 215 | CONFIG_BRIDGE_EBT_IP=m |
| 216 | CONFIG_BRIDGE_EBT_IP6=m | 216 | CONFIG_BRIDGE_EBT_IP6=m |
| 217 | CONFIG_BRIDGE_EBT_LIMIT=m | 217 | CONFIG_BRIDGE_EBT_LIMIT=m |
| 218 | CONFIG_BRIDGE_EBT_MARK=m | 218 | CONFIG_BRIDGE_EBT_MARK=m |
| 219 | CONFIG_BRIDGE_EBT_PKTTYPE=m | 219 | CONFIG_BRIDGE_EBT_PKTTYPE=m |
| 220 | CONFIG_BRIDGE_EBT_STP=m | 220 | CONFIG_BRIDGE_EBT_STP=m |
| 221 | CONFIG_BRIDGE_EBT_VLAN=m | 221 | CONFIG_BRIDGE_EBT_VLAN=m |
| 222 | CONFIG_BRIDGE_EBT_ARPREPLY=m | 222 | CONFIG_BRIDGE_EBT_ARPREPLY=m |
| 223 | CONFIG_BRIDGE_EBT_DNAT=m | 223 | CONFIG_BRIDGE_EBT_DNAT=m |
| 224 | CONFIG_BRIDGE_EBT_MARK_T=m | 224 | CONFIG_BRIDGE_EBT_MARK_T=m |
| 225 | CONFIG_BRIDGE_EBT_REDIRECT=m | 225 | CONFIG_BRIDGE_EBT_REDIRECT=m |
| 226 | CONFIG_BRIDGE_EBT_SNAT=m | 226 | CONFIG_BRIDGE_EBT_SNAT=m |
| 227 | CONFIG_BRIDGE_EBT_LOG=m | 227 | CONFIG_BRIDGE_EBT_LOG=m |
| 228 | CONFIG_BRIDGE_EBT_ULOG=m | 228 | CONFIG_BRIDGE_EBT_ULOG=m |
| 229 | CONFIG_BRIDGE_EBT_NFLOG=m | 229 | CONFIG_BRIDGE_EBT_NFLOG=m |
| 230 | CONFIG_IP_DCCP=m | 230 | CONFIG_IP_DCCP=m |
| 231 | CONFIG_RDS=m | 231 | CONFIG_RDS=m |
| 232 | CONFIG_RDS_TCP=m | 232 | CONFIG_RDS_TCP=m |
| 233 | CONFIG_TIPC=m | 233 | CONFIG_TIPC=m |
| 234 | CONFIG_ATM=m | 234 | CONFIG_ATM=m |
| 235 | CONFIG_ATM_CLIP=m | 235 | CONFIG_ATM_CLIP=m |
| 236 | CONFIG_ATM_LANE=m | 236 | CONFIG_ATM_LANE=m |
| 237 | CONFIG_ATM_MPOA=m | 237 | CONFIG_ATM_MPOA=m |
| 238 | CONFIG_ATM_BR2684=m | 238 | CONFIG_ATM_BR2684=m |
| 239 | CONFIG_BRIDGE=m | 239 | CONFIG_BRIDGE=m |
| 240 | CONFIG_VLAN_8021Q=m | 240 | CONFIG_VLAN_8021Q=m |
| 241 | CONFIG_VLAN_8021Q_GVRP=y | 241 | CONFIG_VLAN_8021Q_GVRP=y |
| 242 | CONFIG_DECNET=m | 242 | CONFIG_DECNET=m |
| 243 | CONFIG_LLC2=m | 243 | CONFIG_LLC2=m |
| 244 | CONFIG_IPX=m | 244 | CONFIG_IPX=m |
| 245 | CONFIG_ATALK=m | 245 | CONFIG_ATALK=m |
| 246 | CONFIG_DEV_APPLETALK=m | 246 | CONFIG_DEV_APPLETALK=m |
| 247 | CONFIG_IPDDP=m | 247 | CONFIG_IPDDP=m |
| 248 | CONFIG_IPDDP_ENCAP=y | 248 | CONFIG_IPDDP_ENCAP=y |
| 249 | CONFIG_IPDDP_DECAP=y | 249 | CONFIG_IPDDP_DECAP=y |
| 250 | CONFIG_X25=m | 250 | CONFIG_X25=m |
| 251 | CONFIG_LAPB=m | 251 | CONFIG_LAPB=m |
| 252 | CONFIG_ECONET=m | 252 | CONFIG_ECONET=m |
| 253 | CONFIG_ECONET_AUNUDP=y | 253 | CONFIG_ECONET_AUNUDP=y |
| 254 | CONFIG_ECONET_NATIVE=y | 254 | CONFIG_ECONET_NATIVE=y |
| 255 | CONFIG_WAN_ROUTER=m | 255 | CONFIG_WAN_ROUTER=m |
| 256 | CONFIG_PHONET=m | 256 | CONFIG_PHONET=m |
| 257 | CONFIG_IEEE802154=m | 257 | CONFIG_IEEE802154=m |
| 258 | CONFIG_NET_SCHED=y | 258 | CONFIG_NET_SCHED=y |
| 259 | CONFIG_NET_SCH_CBQ=m | 259 | CONFIG_NET_SCH_CBQ=m |
| 260 | CONFIG_NET_SCH_HTB=m | 260 | CONFIG_NET_SCH_HTB=m |
| 261 | CONFIG_NET_SCH_HFSC=m | 261 | CONFIG_NET_SCH_HFSC=m |
| 262 | CONFIG_NET_SCH_ATM=m | 262 | CONFIG_NET_SCH_ATM=m |
| 263 | CONFIG_NET_SCH_PRIO=m | 263 | CONFIG_NET_SCH_PRIO=m |
| 264 | CONFIG_NET_SCH_MULTIQ=m | 264 | CONFIG_NET_SCH_MULTIQ=m |
| 265 | CONFIG_NET_SCH_RED=m | 265 | CONFIG_NET_SCH_RED=m |
| 266 | CONFIG_NET_SCH_SFQ=m | 266 | CONFIG_NET_SCH_SFQ=m |
| 267 | CONFIG_NET_SCH_TEQL=m | 267 | CONFIG_NET_SCH_TEQL=m |
| 268 | CONFIG_NET_SCH_TBF=m | 268 | CONFIG_NET_SCH_TBF=m |
| 269 | CONFIG_NET_SCH_GRED=m | 269 | CONFIG_NET_SCH_GRED=m |
| 270 | CONFIG_NET_SCH_DSMARK=m | 270 | CONFIG_NET_SCH_DSMARK=m |
| 271 | CONFIG_NET_SCH_NETEM=m | 271 | CONFIG_NET_SCH_NETEM=m |
| 272 | CONFIG_NET_SCH_DRR=m | 272 | CONFIG_NET_SCH_DRR=m |
| 273 | CONFIG_NET_SCH_INGRESS=m | 273 | CONFIG_NET_SCH_INGRESS=m |
| 274 | CONFIG_NET_CLS_BASIC=m | 274 | CONFIG_NET_CLS_BASIC=m |
| 275 | CONFIG_NET_CLS_TCINDEX=m | 275 | CONFIG_NET_CLS_TCINDEX=m |
| 276 | CONFIG_NET_CLS_ROUTE4=m | 276 | CONFIG_NET_CLS_ROUTE4=m |
| 277 | CONFIG_NET_CLS_FW=m | 277 | CONFIG_NET_CLS_FW=m |
| 278 | CONFIG_NET_CLS_U32=m | 278 | CONFIG_NET_CLS_U32=m |
| 279 | CONFIG_CLS_U32_MARK=y | 279 | CONFIG_CLS_U32_MARK=y |
| 280 | CONFIG_NET_CLS_RSVP=m | 280 | CONFIG_NET_CLS_RSVP=m |
| 281 | CONFIG_NET_CLS_RSVP6=m | 281 | CONFIG_NET_CLS_RSVP6=m |
| 282 | CONFIG_NET_CLS_FLOW=m | 282 | CONFIG_NET_CLS_FLOW=m |
| 283 | CONFIG_NET_EMATCH=y | 283 | CONFIG_NET_EMATCH=y |
| 284 | CONFIG_NET_EMATCH_CMP=m | 284 | CONFIG_NET_EMATCH_CMP=m |
| 285 | CONFIG_NET_EMATCH_NBYTE=m | 285 | CONFIG_NET_EMATCH_NBYTE=m |
| 286 | CONFIG_NET_EMATCH_U32=m | 286 | CONFIG_NET_EMATCH_U32=m |
| 287 | CONFIG_NET_EMATCH_META=m | 287 | CONFIG_NET_EMATCH_META=m |
| 288 | CONFIG_NET_EMATCH_TEXT=m | 288 | CONFIG_NET_EMATCH_TEXT=m |
| 289 | CONFIG_NET_CLS_ACT=y | 289 | CONFIG_NET_CLS_ACT=y |
| 290 | CONFIG_NET_ACT_POLICE=m | 290 | CONFIG_NET_ACT_POLICE=m |
| 291 | CONFIG_NET_ACT_GACT=m | 291 | CONFIG_NET_ACT_GACT=m |
| 292 | CONFIG_GACT_PROB=y | 292 | CONFIG_GACT_PROB=y |
| 293 | CONFIG_NET_ACT_MIRRED=m | 293 | CONFIG_NET_ACT_MIRRED=m |
| 294 | CONFIG_NET_ACT_IPT=m | 294 | CONFIG_NET_ACT_IPT=m |
| 295 | CONFIG_NET_ACT_NAT=m | 295 | CONFIG_NET_ACT_NAT=m |
| 296 | CONFIG_NET_ACT_PEDIT=m | 296 | CONFIG_NET_ACT_PEDIT=m |
| 297 | CONFIG_NET_ACT_SIMP=m | 297 | CONFIG_NET_ACT_SIMP=m |
| 298 | CONFIG_NET_ACT_SKBEDIT=m | 298 | CONFIG_NET_ACT_SKBEDIT=m |
| 299 | CONFIG_DCB=y | 299 | CONFIG_DCB=y |
| 300 | CONFIG_NET_PKTGEN=m | 300 | CONFIG_NET_PKTGEN=m |
| 301 | CONFIG_DEVTMPFS=y | 301 | CONFIG_DEVTMPFS=y |
| 302 | CONFIG_DEVTMPFS_MOUNT=y | 302 | CONFIG_DEVTMPFS_MOUNT=y |
| 303 | # CONFIG_STANDALONE is not set | 303 | # CONFIG_STANDALONE is not set |
| 304 | CONFIG_CONNECTOR=y | 304 | CONFIG_CONNECTOR=y |
| 305 | CONFIG_BLK_DEV_LOOP=y | 305 | CONFIG_BLK_DEV_LOOP=y |
| 306 | CONFIG_BLK_DEV_CRYPTOLOOP=m | 306 | CONFIG_BLK_DEV_CRYPTOLOOP=m |
| 307 | CONFIG_BLK_DEV_NBD=m | 307 | CONFIG_BLK_DEV_NBD=m |
| 308 | CONFIG_BLK_DEV_OSD=m | 308 | CONFIG_BLK_DEV_OSD=m |
| 309 | CONFIG_BLK_DEV_RAM=y | 309 | CONFIG_BLK_DEV_RAM=y |
| 310 | CONFIG_BLK_DEV_RAM_SIZE=65536 | 310 | CONFIG_BLK_DEV_RAM_SIZE=65536 |
| 311 | CONFIG_CDROM_PKTCDVD=y | 311 | CONFIG_CDROM_PKTCDVD=y |
| 312 | CONFIG_MISC_DEVICES=y | 312 | CONFIG_MISC_DEVICES=y |
| 313 | CONFIG_RAID_ATTRS=m | 313 | CONFIG_RAID_ATTRS=m |
| 314 | CONFIG_SCSI=y | 314 | CONFIG_SCSI=y |
| 315 | CONFIG_BLK_DEV_SD=y | 315 | CONFIG_BLK_DEV_SD=y |
| 316 | CONFIG_CHR_DEV_ST=m | 316 | CONFIG_CHR_DEV_ST=m |
| 317 | CONFIG_CHR_DEV_OSST=m | 317 | CONFIG_CHR_DEV_OSST=m |
| 318 | CONFIG_BLK_DEV_SR=y | 318 | CONFIG_BLK_DEV_SR=y |
| 319 | CONFIG_CHR_DEV_SG=y | 319 | CONFIG_CHR_DEV_SG=y |
| 320 | CONFIG_CHR_DEV_SCH=m | 320 | CONFIG_CHR_DEV_SCH=m |
| 321 | CONFIG_SCSI_MULTI_LUN=y | 321 | CONFIG_SCSI_MULTI_LUN=y |
| 322 | CONFIG_SCSI_CONSTANTS=y | 322 | CONFIG_SCSI_CONSTANTS=y |
| 323 | CONFIG_SCSI_LOGGING=y | 323 | CONFIG_SCSI_LOGGING=y |
| 324 | CONFIG_SCSI_SCAN_ASYNC=y | 324 | CONFIG_SCSI_SCAN_ASYNC=y |
| 325 | CONFIG_SCSI_SPI_ATTRS=m | 325 | CONFIG_SCSI_SPI_ATTRS=m |
| 326 | CONFIG_SCSI_SAS_LIBSAS=m | 326 | CONFIG_SCSI_SAS_LIBSAS=m |
| 327 | CONFIG_SCSI_SRP_ATTRS=m | 327 | CONFIG_SCSI_SRP_ATTRS=m |
| 328 | CONFIG_ISCSI_TCP=m | 328 | CONFIG_ISCSI_TCP=m |
| 329 | CONFIG_LIBFCOE=m | 329 | CONFIG_LIBFCOE=m |
| 330 | CONFIG_SCSI_DEBUG=m | 330 | CONFIG_SCSI_DEBUG=m |
| 331 | CONFIG_SCSI_DH=y | 331 | CONFIG_SCSI_DH=y |
| 332 | CONFIG_SCSI_DH_RDAC=m | 332 | CONFIG_SCSI_DH_RDAC=m |
| 333 | CONFIG_SCSI_DH_HP_SW=m | 333 | CONFIG_SCSI_DH_HP_SW=m |
| 334 | CONFIG_SCSI_DH_EMC=m | 334 | CONFIG_SCSI_DH_EMC=m |
| 335 | CONFIG_SCSI_DH_ALUA=m | 335 | CONFIG_SCSI_DH_ALUA=m |
| 336 | CONFIG_SCSI_OSD_INITIATOR=m | 336 | CONFIG_SCSI_OSD_INITIATOR=m |
| 337 | CONFIG_SCSI_OSD_ULD=m | 337 | CONFIG_SCSI_OSD_ULD=m |
| 338 | CONFIG_NETDEVICES=y | 338 | CONFIG_NETDEVICES=y |
| 339 | CONFIG_E1000E=y | 339 | CONFIG_E1000E=y |
| 340 | CONFIG_SKY2=y | 340 | CONFIG_SKY2=y |
| 341 | # CONFIG_INPUT_MOUSEDEV is not set | 341 | # CONFIG_INPUT_MOUSEDEV is not set |
| 342 | CONFIG_INPUT_EVDEV=y | 342 | CONFIG_INPUT_EVDEV=y |
| 343 | CONFIG_INPUT_EVBUG=m | 343 | CONFIG_INPUT_EVBUG=m |
| 344 | # CONFIG_INPUT_KEYBOARD is not set | 344 | # CONFIG_INPUT_KEYBOARD is not set |
| 345 | # CONFIG_INPUT_MOUSE is not set | 345 | # CONFIG_INPUT_MOUSE is not set |
| 346 | # CONFIG_SERIO_I8042 is not set | 346 | # CONFIG_SERIO_I8042 is not set |
| 347 | CONFIG_SERIO_SERPORT=m | 347 | CONFIG_SERIO_SERPORT=m |
| 348 | CONFIG_SERIO_LIBPS2=y | 348 | CONFIG_SERIO_LIBPS2=y |
| 349 | CONFIG_SERIO_RAW=m | 349 | CONFIG_SERIO_RAW=m |
| 350 | CONFIG_VT_HW_CONSOLE_BINDING=y | 350 | CONFIG_VT_HW_CONSOLE_BINDING=y |
| 351 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y | 351 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y |
| 352 | CONFIG_LEGACY_PTY_COUNT=0 | 352 | CONFIG_LEGACY_PTY_COUNT=0 |
| 353 | CONFIG_SERIAL_NONSTANDARD=y | 353 | CONFIG_SERIAL_NONSTANDARD=y |
| 354 | CONFIG_N_HDLC=m | 354 | CONFIG_N_HDLC=m |
| 355 | # CONFIG_DEVKMEM is not set | 355 | # CONFIG_DEVKMEM is not set |
| 356 | CONFIG_STALDRV=y | 356 | CONFIG_STALDRV=y |
| 357 | CONFIG_SERIAL_8250=y | 357 | CONFIG_SERIAL_8250=y |
| 358 | CONFIG_SERIAL_8250_CONSOLE=y | 358 | CONFIG_SERIAL_8250_CONSOLE=y |
| 359 | CONFIG_SERIAL_8250_NR_UARTS=48 | 359 | CONFIG_SERIAL_8250_NR_UARTS=48 |
| 360 | CONFIG_SERIAL_8250_EXTENDED=y | 360 | CONFIG_SERIAL_8250_EXTENDED=y |
| 361 | CONFIG_SERIAL_8250_MANY_PORTS=y | 361 | CONFIG_SERIAL_8250_MANY_PORTS=y |
| 362 | CONFIG_SERIAL_8250_SHARE_IRQ=y | 362 | CONFIG_SERIAL_8250_SHARE_IRQ=y |
| 363 | CONFIG_SERIAL_8250_RSA=y | 363 | CONFIG_SERIAL_8250_RSA=y |
| 364 | CONFIG_HW_RANDOM=y | 364 | CONFIG_HW_RANDOM=y |
| 365 | CONFIG_HW_RANDOM_TIMERIOMEM=m | 365 | CONFIG_HW_RANDOM_TIMERIOMEM=m |
| 366 | CONFIG_RAW_DRIVER=m | 366 | CONFIG_RAW_DRIVER=m |
| 367 | CONFIG_I2C=y | 367 | CONFIG_I2C=y |
| 368 | CONFIG_I2C_XLR=y | 368 | CONFIG_I2C_XLR=y |
| 369 | CONFIG_RTC_CLASS=y | 369 | CONFIG_RTC_CLASS=y |
| 370 | CONFIG_RTC_DRV_DS1374=y | 370 | CONFIG_RTC_DRV_DS1374=y |
| 371 | # CONFIG_HWMON is not set | 371 | # CONFIG_HWMON is not set |
| 372 | # CONFIG_VGA_CONSOLE is not set | 372 | # CONFIG_VGA_CONSOLE is not set |
| 373 | # CONFIG_HID_SUPPORT is not set | 373 | # CONFIG_HID_SUPPORT is not set |
| 374 | # CONFIG_USB_SUPPORT is not set | 374 | # CONFIG_USB_SUPPORT is not set |
| 375 | CONFIG_UIO=y | 375 | CONFIG_UIO=y |
| 376 | CONFIG_UIO_PDRV=m | 376 | CONFIG_UIO_PDRV=m |
| 377 | CONFIG_UIO_PDRV_GENIRQ=m | 377 | CONFIG_UIO_PDRV_GENIRQ=m |
| 378 | CONFIG_EXT2_FS=y | 378 | CONFIG_EXT2_FS=y |
| 379 | CONFIG_EXT2_FS_XATTR=y | 379 | CONFIG_EXT2_FS_XATTR=y |
| 380 | CONFIG_EXT2_FS_POSIX_ACL=y | 380 | CONFIG_EXT2_FS_POSIX_ACL=y |
| 381 | CONFIG_EXT2_FS_SECURITY=y | 381 | CONFIG_EXT2_FS_SECURITY=y |
| 382 | CONFIG_EXT3_FS=y | 382 | CONFIG_EXT3_FS=y |
| 383 | CONFIG_EXT3_FS_POSIX_ACL=y | 383 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 384 | CONFIG_EXT3_FS_SECURITY=y | 384 | CONFIG_EXT3_FS_SECURITY=y |
| 385 | CONFIG_EXT4_FS=y | 385 | CONFIG_EXT4_FS=y |
| 386 | CONFIG_EXT4_FS_POSIX_ACL=y | 386 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 387 | CONFIG_EXT4_FS_SECURITY=y | 387 | CONFIG_EXT4_FS_SECURITY=y |
| 388 | CONFIG_GFS2_FS=m | 388 | CONFIG_GFS2_FS=m |
| 389 | CONFIG_GFS2_FS_LOCKING_DLM=y | 389 | CONFIG_GFS2_FS_LOCKING_DLM=y |
| 390 | CONFIG_OCFS2_FS=m | 390 | CONFIG_OCFS2_FS=m |
| 391 | CONFIG_BTRFS_FS=m | 391 | CONFIG_BTRFS_FS=m |
| 392 | CONFIG_BTRFS_FS_POSIX_ACL=y | 392 | CONFIG_BTRFS_FS_POSIX_ACL=y |
| 393 | CONFIG_NILFS2_FS=m | 393 | CONFIG_NILFS2_FS=m |
| 394 | CONFIG_QUOTA_NETLINK_INTERFACE=y | 394 | CONFIG_QUOTA_NETLINK_INTERFACE=y |
| 395 | # CONFIG_PRINT_QUOTA_WARNING is not set | 395 | # CONFIG_PRINT_QUOTA_WARNING is not set |
| 396 | CONFIG_QFMT_V1=m | 396 | CONFIG_QFMT_V1=m |
| 397 | CONFIG_QFMT_V2=m | 397 | CONFIG_QFMT_V2=m |
| 398 | CONFIG_AUTOFS4_FS=m | 398 | CONFIG_AUTOFS4_FS=m |
| 399 | CONFIG_FUSE_FS=y | 399 | CONFIG_FUSE_FS=y |
| 400 | CONFIG_CUSE=m | 400 | CONFIG_CUSE=m |
| 401 | CONFIG_FSCACHE=m | 401 | CONFIG_FSCACHE=m |
| 402 | CONFIG_FSCACHE_STATS=y | 402 | CONFIG_FSCACHE_STATS=y |
| 403 | CONFIG_FSCACHE_HISTOGRAM=y | 403 | CONFIG_FSCACHE_HISTOGRAM=y |
| 404 | CONFIG_CACHEFILES=m | 404 | CONFIG_CACHEFILES=m |
| 405 | CONFIG_ISO9660_FS=m | 405 | CONFIG_ISO9660_FS=m |
| 406 | CONFIG_JOLIET=y | 406 | CONFIG_JOLIET=y |
| 407 | CONFIG_ZISOFS=y | 407 | CONFIG_ZISOFS=y |
| 408 | CONFIG_UDF_FS=m | 408 | CONFIG_UDF_FS=m |
| 409 | CONFIG_MSDOS_FS=m | 409 | CONFIG_MSDOS_FS=m |
| 410 | CONFIG_VFAT_FS=m | 410 | CONFIG_VFAT_FS=m |
| 411 | CONFIG_NTFS_FS=m | 411 | CONFIG_NTFS_FS=m |
| 412 | CONFIG_PROC_KCORE=y | 412 | CONFIG_PROC_KCORE=y |
| 413 | CONFIG_TMPFS=y | 413 | CONFIG_TMPFS=y |
| 414 | CONFIG_TMPFS_POSIX_ACL=y | 414 | CONFIG_TMPFS_POSIX_ACL=y |
| 415 | CONFIG_CONFIGFS_FS=y | 415 | CONFIG_CONFIGFS_FS=y |
| 416 | CONFIG_ADFS_FS=m | 416 | CONFIG_ADFS_FS=m |
| 417 | CONFIG_AFFS_FS=m | 417 | CONFIG_AFFS_FS=m |
| 418 | CONFIG_ECRYPT_FS=y | 418 | CONFIG_ECRYPT_FS=y |
| 419 | CONFIG_HFS_FS=m | 419 | CONFIG_HFS_FS=m |
| 420 | CONFIG_HFSPLUS_FS=m | 420 | CONFIG_HFSPLUS_FS=m |
| 421 | CONFIG_BEFS_FS=m | 421 | CONFIG_BEFS_FS=m |
| 422 | CONFIG_BFS_FS=m | 422 | CONFIG_BFS_FS=m |
| 423 | CONFIG_EFS_FS=m | 423 | CONFIG_EFS_FS=m |
| 424 | CONFIG_CRAMFS=m | 424 | CONFIG_CRAMFS=m |
| 425 | CONFIG_SQUASHFS=m | 425 | CONFIG_SQUASHFS=m |
| 426 | CONFIG_VXFS_FS=m | 426 | CONFIG_VXFS_FS=m |
| 427 | CONFIG_MINIX_FS=m | 427 | CONFIG_MINIX_FS=m |
| 428 | CONFIG_OMFS_FS=m | 428 | CONFIG_OMFS_FS=m |
| 429 | CONFIG_HPFS_FS=m | 429 | CONFIG_HPFS_FS=m |
| 430 | CONFIG_QNX4FS_FS=m | 430 | CONFIG_QNX4FS_FS=m |
| 431 | CONFIG_ROMFS_FS=m | 431 | CONFIG_ROMFS_FS=m |
| 432 | CONFIG_SYSV_FS=m | 432 | CONFIG_SYSV_FS=m |
| 433 | CONFIG_UFS_FS=m | 433 | CONFIG_UFS_FS=m |
| 434 | CONFIG_EXOFS_FS=m | 434 | CONFIG_EXOFS_FS=m |
| 435 | CONFIG_NFS_FS=m | 435 | CONFIG_NFS_FS=m |
| 436 | CONFIG_NFS_V3=y | 436 | CONFIG_NFS_V3=y |
| 437 | CONFIG_NFS_V3_ACL=y | 437 | CONFIG_NFS_V3_ACL=y |
| 438 | CONFIG_NFS_V4=y | 438 | CONFIG_NFS_V4=y |
| 439 | CONFIG_NFS_FSCACHE=y | 439 | CONFIG_NFS_FSCACHE=y |
| 440 | CONFIG_NFSD=m | 440 | CONFIG_NFSD=m |
| 441 | CONFIG_NFSD_V3_ACL=y | 441 | CONFIG_NFSD_V3_ACL=y |
| 442 | CONFIG_NFSD_V4=y | 442 | CONFIG_NFSD_V4=y |
| 443 | CONFIG_CIFS=m | 443 | CONFIG_CIFS=m |
| 444 | CONFIG_CIFS_WEAK_PW_HASH=y | 444 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 445 | CONFIG_CIFS_UPCALL=y | 445 | CONFIG_CIFS_UPCALL=y |
| 446 | CONFIG_CIFS_XATTR=y | 446 | CONFIG_CIFS_XATTR=y |
| 447 | CONFIG_CIFS_POSIX=y | 447 | CONFIG_CIFS_POSIX=y |
| 448 | CONFIG_CIFS_DFS_UPCALL=y | 448 | CONFIG_CIFS_DFS_UPCALL=y |
| 449 | CONFIG_NCP_FS=m | 449 | CONFIG_NCP_FS=m |
| 450 | CONFIG_NCPFS_PACKET_SIGNING=y | 450 | CONFIG_NCPFS_PACKET_SIGNING=y |
| 451 | CONFIG_NCPFS_IOCTL_LOCKING=y | 451 | CONFIG_NCPFS_IOCTL_LOCKING=y |
| 452 | CONFIG_NCPFS_STRONG=y | 452 | CONFIG_NCPFS_STRONG=y |
| 453 | CONFIG_NCPFS_NFS_NS=y | 453 | CONFIG_NCPFS_NFS_NS=y |
| 454 | CONFIG_NCPFS_OS2_NS=y | 454 | CONFIG_NCPFS_OS2_NS=y |
| 455 | CONFIG_NCPFS_NLS=y | 455 | CONFIG_NCPFS_NLS=y |
| 456 | CONFIG_NCPFS_EXTRAS=y | 456 | CONFIG_NCPFS_EXTRAS=y |
| 457 | CONFIG_CODA_FS=m | 457 | CONFIG_CODA_FS=m |
| 458 | CONFIG_AFS_FS=m | 458 | CONFIG_AFS_FS=m |
| 459 | CONFIG_PARTITION_ADVANCED=y | 459 | CONFIG_PARTITION_ADVANCED=y |
| 460 | CONFIG_ACORN_PARTITION=y | 460 | CONFIG_ACORN_PARTITION=y |
| 461 | CONFIG_ACORN_PARTITION_ICS=y | 461 | CONFIG_ACORN_PARTITION_ICS=y |
| 462 | CONFIG_ACORN_PARTITION_RISCIX=y | 462 | CONFIG_ACORN_PARTITION_RISCIX=y |
| 463 | CONFIG_OSF_PARTITION=y | 463 | CONFIG_OSF_PARTITION=y |
| 464 | CONFIG_AMIGA_PARTITION=y | 464 | CONFIG_AMIGA_PARTITION=y |
| 465 | CONFIG_ATARI_PARTITION=y | 465 | CONFIG_ATARI_PARTITION=y |
| 466 | CONFIG_MAC_PARTITION=y | 466 | CONFIG_MAC_PARTITION=y |
| 467 | CONFIG_BSD_DISKLABEL=y | 467 | CONFIG_BSD_DISKLABEL=y |
| 468 | CONFIG_MINIX_SUBPARTITION=y | 468 | CONFIG_MINIX_SUBPARTITION=y |
| 469 | CONFIG_SOLARIS_X86_PARTITION=y | 469 | CONFIG_SOLARIS_X86_PARTITION=y |
| 470 | CONFIG_UNIXWARE_DISKLABEL=y | 470 | CONFIG_UNIXWARE_DISKLABEL=y |
| 471 | CONFIG_LDM_PARTITION=y | 471 | CONFIG_LDM_PARTITION=y |
| 472 | CONFIG_SGI_PARTITION=y | 472 | CONFIG_SGI_PARTITION=y |
| 473 | CONFIG_ULTRIX_PARTITION=y | 473 | CONFIG_ULTRIX_PARTITION=y |
| 474 | CONFIG_SUN_PARTITION=y | 474 | CONFIG_SUN_PARTITION=y |
| 475 | CONFIG_KARMA_PARTITION=y | 475 | CONFIG_KARMA_PARTITION=y |
| 476 | CONFIG_EFI_PARTITION=y | 476 | CONFIG_EFI_PARTITION=y |
| 477 | CONFIG_SYSV68_PARTITION=y | 477 | CONFIG_SYSV68_PARTITION=y |
| 478 | CONFIG_NLS=y | 478 | CONFIG_NLS=y |
| 479 | CONFIG_NLS_DEFAULT="cp437" | 479 | CONFIG_NLS_DEFAULT="cp437" |
| 480 | CONFIG_NLS_CODEPAGE_437=m | 480 | CONFIG_NLS_CODEPAGE_437=m |
| 481 | CONFIG_NLS_CODEPAGE_737=m | 481 | CONFIG_NLS_CODEPAGE_737=m |
| 482 | CONFIG_NLS_CODEPAGE_775=m | 482 | CONFIG_NLS_CODEPAGE_775=m |
| 483 | CONFIG_NLS_CODEPAGE_850=m | 483 | CONFIG_NLS_CODEPAGE_850=m |
| 484 | CONFIG_NLS_CODEPAGE_852=m | 484 | CONFIG_NLS_CODEPAGE_852=m |
| 485 | CONFIG_NLS_CODEPAGE_855=m | 485 | CONFIG_NLS_CODEPAGE_855=m |
| 486 | CONFIG_NLS_CODEPAGE_857=m | 486 | CONFIG_NLS_CODEPAGE_857=m |
| 487 | CONFIG_NLS_CODEPAGE_860=m | 487 | CONFIG_NLS_CODEPAGE_860=m |
| 488 | CONFIG_NLS_CODEPAGE_861=m | 488 | CONFIG_NLS_CODEPAGE_861=m |
| 489 | CONFIG_NLS_CODEPAGE_862=m | 489 | CONFIG_NLS_CODEPAGE_862=m |
| 490 | CONFIG_NLS_CODEPAGE_863=m | 490 | CONFIG_NLS_CODEPAGE_863=m |
| 491 | CONFIG_NLS_CODEPAGE_864=m | 491 | CONFIG_NLS_CODEPAGE_864=m |
| 492 | CONFIG_NLS_CODEPAGE_865=m | 492 | CONFIG_NLS_CODEPAGE_865=m |
| 493 | CONFIG_NLS_CODEPAGE_866=m | 493 | CONFIG_NLS_CODEPAGE_866=m |
| 494 | CONFIG_NLS_CODEPAGE_869=m | 494 | CONFIG_NLS_CODEPAGE_869=m |
| 495 | CONFIG_NLS_CODEPAGE_936=m | 495 | CONFIG_NLS_CODEPAGE_936=m |
| 496 | CONFIG_NLS_CODEPAGE_950=m | 496 | CONFIG_NLS_CODEPAGE_950=m |
| 497 | CONFIG_NLS_CODEPAGE_932=m | 497 | CONFIG_NLS_CODEPAGE_932=m |
| 498 | CONFIG_NLS_CODEPAGE_949=m | 498 | CONFIG_NLS_CODEPAGE_949=m |
| 499 | CONFIG_NLS_CODEPAGE_874=m | 499 | CONFIG_NLS_CODEPAGE_874=m |
| 500 | CONFIG_NLS_ISO8859_8=m | 500 | CONFIG_NLS_ISO8859_8=m |
| 501 | CONFIG_NLS_CODEPAGE_1250=m | 501 | CONFIG_NLS_CODEPAGE_1250=m |
| 502 | CONFIG_NLS_CODEPAGE_1251=m | 502 | CONFIG_NLS_CODEPAGE_1251=m |
| 503 | CONFIG_NLS_ASCII=m | 503 | CONFIG_NLS_ASCII=m |
| 504 | CONFIG_NLS_ISO8859_1=m | 504 | CONFIG_NLS_ISO8859_1=m |
| 505 | CONFIG_NLS_ISO8859_2=m | 505 | CONFIG_NLS_ISO8859_2=m |
| 506 | CONFIG_NLS_ISO8859_3=m | 506 | CONFIG_NLS_ISO8859_3=m |
| 507 | CONFIG_NLS_ISO8859_4=m | 507 | CONFIG_NLS_ISO8859_4=m |
| 508 | CONFIG_NLS_ISO8859_5=m | 508 | CONFIG_NLS_ISO8859_5=m |
| 509 | CONFIG_NLS_ISO8859_6=m | 509 | CONFIG_NLS_ISO8859_6=m |
| 510 | CONFIG_NLS_ISO8859_7=m | 510 | CONFIG_NLS_ISO8859_7=m |
| 511 | CONFIG_NLS_ISO8859_9=m | 511 | CONFIG_NLS_ISO8859_9=m |
| 512 | CONFIG_NLS_ISO8859_13=m | 512 | CONFIG_NLS_ISO8859_13=m |
| 513 | CONFIG_NLS_ISO8859_14=m | 513 | CONFIG_NLS_ISO8859_14=m |
| 514 | CONFIG_NLS_ISO8859_15=m | 514 | CONFIG_NLS_ISO8859_15=m |
| 515 | CONFIG_NLS_KOI8_R=m | 515 | CONFIG_NLS_KOI8_R=m |
| 516 | CONFIG_NLS_KOI8_U=m | 516 | CONFIG_NLS_KOI8_U=m |
| 517 | CONFIG_PRINTK_TIME=y | 517 | CONFIG_PRINTK_TIME=y |
| 518 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 518 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 519 | # CONFIG_ENABLE_MUST_CHECK is not set | 519 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 520 | CONFIG_UNUSED_SYMBOLS=y | 520 | CONFIG_UNUSED_SYMBOLS=y |
| 521 | CONFIG_DETECT_HUNG_TASK=y | 521 | CONFIG_DETECT_HUNG_TASK=y |
| 522 | CONFIG_SCHEDSTATS=y | 522 | CONFIG_SCHEDSTATS=y |
| 523 | CONFIG_TIMER_STATS=y | 523 | CONFIG_TIMER_STATS=y |
| 524 | CONFIG_DEBUG_INFO=y | 524 | CONFIG_DEBUG_INFO=y |
| 525 | CONFIG_DEBUG_MEMORY_INIT=y | 525 | CONFIG_DEBUG_MEMORY_INIT=y |
| 526 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 526 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 527 | CONFIG_SCHED_TRACER=y | 527 | CONFIG_SCHED_TRACER=y |
| 528 | CONFIG_BLK_DEV_IO_TRACE=y | 528 | CONFIG_BLK_DEV_IO_TRACE=y |
| 529 | CONFIG_KGDB=y | 529 | CONFIG_KGDB=y |
| 530 | CONFIG_SECURITY=y | 530 | CONFIG_SECURITY=y |
| 531 | CONFIG_SECURITY_NETWORK=y | 531 | CONFIG_SECURITY_NETWORK=y |
| 532 | CONFIG_LSM_MMAP_MIN_ADDR=0 | 532 | CONFIG_LSM_MMAP_MIN_ADDR=0 |
| 533 | CONFIG_SECURITY_SELINUX=y | 533 | CONFIG_SECURITY_SELINUX=y |
| 534 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y | 534 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y |
| 535 | CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 | 535 | CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 |
| 536 | CONFIG_SECURITY_SELINUX_DISABLE=y | 536 | CONFIG_SECURITY_SELINUX_DISABLE=y |
| 537 | CONFIG_SECURITY_SMACK=y | 537 | CONFIG_SECURITY_SMACK=y |
| 538 | CONFIG_SECURITY_TOMOYO=y | 538 | CONFIG_SECURITY_TOMOYO=y |
| 539 | CONFIG_CRYPTO_NULL=m | 539 | CONFIG_CRYPTO_NULL=m |
| 540 | CONFIG_CRYPTO_CRYPTD=m | 540 | CONFIG_CRYPTO_CRYPTD=m |
| 541 | CONFIG_CRYPTO_TEST=m | 541 | CONFIG_CRYPTO_TEST=m |
| 542 | CONFIG_CRYPTO_CCM=m | 542 | CONFIG_CRYPTO_CCM=m |
| 543 | CONFIG_CRYPTO_GCM=m | 543 | CONFIG_CRYPTO_GCM=m |
| 544 | CONFIG_CRYPTO_CTS=m | 544 | CONFIG_CRYPTO_CTS=m |
| 545 | CONFIG_CRYPTO_LRW=m | 545 | CONFIG_CRYPTO_LRW=m |
| 546 | CONFIG_CRYPTO_PCBC=m | 546 | CONFIG_CRYPTO_PCBC=m |
| 547 | CONFIG_CRYPTO_XTS=m | 547 | CONFIG_CRYPTO_XTS=m |
| 548 | CONFIG_CRYPTO_HMAC=y | 548 | CONFIG_CRYPTO_HMAC=y |
| 549 | CONFIG_CRYPTO_XCBC=m | 549 | CONFIG_CRYPTO_XCBC=m |
| 550 | CONFIG_CRYPTO_VMAC=m | 550 | CONFIG_CRYPTO_VMAC=m |
| 551 | CONFIG_CRYPTO_MICHAEL_MIC=m | 551 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 552 | CONFIG_CRYPTO_RMD128=m | 552 | CONFIG_CRYPTO_RMD128=m |
| 553 | CONFIG_CRYPTO_RMD160=m | 553 | CONFIG_CRYPTO_RMD160=m |
| 554 | CONFIG_CRYPTO_RMD256=m | 554 | CONFIG_CRYPTO_RMD256=m |
| 555 | CONFIG_CRYPTO_RMD320=m | 555 | CONFIG_CRYPTO_RMD320=m |
| 556 | CONFIG_CRYPTO_SHA256=m | 556 | CONFIG_CRYPTO_SHA256=m |
| 557 | CONFIG_CRYPTO_SHA512=m | 557 | CONFIG_CRYPTO_SHA512=m |
| 558 | CONFIG_CRYPTO_TGR192=m | 558 | CONFIG_CRYPTO_TGR192=m |
| 559 | CONFIG_CRYPTO_WP512=m | 559 | CONFIG_CRYPTO_WP512=m |
| 560 | CONFIG_CRYPTO_ANUBIS=m | 560 | CONFIG_CRYPTO_ANUBIS=m |
| 561 | CONFIG_CRYPTO_BLOWFISH=m | 561 | CONFIG_CRYPTO_BLOWFISH=m |
| 562 | CONFIG_CRYPTO_CAMELLIA=m | 562 | CONFIG_CRYPTO_CAMELLIA=m |
| 563 | CONFIG_CRYPTO_CAST5=m | 563 | CONFIG_CRYPTO_CAST5=m |
| 564 | CONFIG_CRYPTO_CAST6=m | 564 | CONFIG_CRYPTO_CAST6=m |
| 565 | CONFIG_CRYPTO_FCRYPT=m | 565 | CONFIG_CRYPTO_FCRYPT=m |
| 566 | CONFIG_CRYPTO_KHAZAD=m | 566 | CONFIG_CRYPTO_KHAZAD=m |
| 567 | CONFIG_CRYPTO_SALSA20=m | 567 | CONFIG_CRYPTO_SALSA20=m |
| 568 | CONFIG_CRYPTO_SEED=m | 568 | CONFIG_CRYPTO_SEED=m |
| 569 | CONFIG_CRYPTO_SERPENT=m | 569 | CONFIG_CRYPTO_SERPENT=m |
| 570 | CONFIG_CRYPTO_TEA=m | 570 | CONFIG_CRYPTO_TEA=m |
| 571 | CONFIG_CRYPTO_TWOFISH=m | 571 | CONFIG_CRYPTO_TWOFISH=m |
| 572 | CONFIG_CRYPTO_ZLIB=m | 572 | CONFIG_CRYPTO_ZLIB=m |
| 573 | CONFIG_CRYPTO_LZO=m | 573 | CONFIG_CRYPTO_LZO=m |
| 574 | CONFIG_CRC_CCITT=m | 574 | CONFIG_CRC_CCITT=m |
| 575 | CONFIG_CRC7=m | 575 | CONFIG_CRC7=m |
| 576 | 576 |
arch/powerpc/configs/ps3_defconfig
| 1 | CONFIG_PPC64=y | 1 | CONFIG_PPC64=y |
| 2 | CONFIG_TUNE_CELL=y | 2 | CONFIG_TUNE_CELL=y |
| 3 | CONFIG_ALTIVEC=y | 3 | CONFIG_ALTIVEC=y |
| 4 | CONFIG_SMP=y | 4 | CONFIG_SMP=y |
| 5 | CONFIG_NR_CPUS=2 | 5 | CONFIG_NR_CPUS=2 |
| 6 | CONFIG_SYSVIPC=y | 6 | CONFIG_SYSVIPC=y |
| 7 | CONFIG_POSIX_MQUEUE=y | 7 | CONFIG_POSIX_MQUEUE=y |
| 8 | CONFIG_FHANDLE=y | 8 | CONFIG_FHANDLE=y |
| 9 | CONFIG_HIGH_RES_TIMERS=y | 9 | CONFIG_HIGH_RES_TIMERS=y |
| 10 | CONFIG_BLK_DEV_INITRD=y | 10 | CONFIG_BLK_DEV_INITRD=y |
| 11 | CONFIG_RD_LZMA=y | 11 | CONFIG_RD_LZMA=y |
| 12 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 12 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 13 | CONFIG_EMBEDDED=y | 13 | CONFIG_EMBEDDED=y |
| 14 | # CONFIG_PERF_EVENTS is not set | 14 | # CONFIG_PERF_EVENTS is not set |
| 15 | # CONFIG_COMPAT_BRK is not set | 15 | # CONFIG_COMPAT_BRK is not set |
| 16 | CONFIG_SLAB=y | 16 | CONFIG_SLAB=y |
| 17 | CONFIG_PROFILING=y | 17 | CONFIG_PROFILING=y |
| 18 | CONFIG_OPROFILE=m | 18 | CONFIG_OPROFILE=m |
| 19 | CONFIG_MODULES=y | 19 | CONFIG_MODULES=y |
| 20 | CONFIG_MODULE_UNLOAD=y | 20 | CONFIG_MODULE_UNLOAD=y |
| 21 | # CONFIG_PPC_POWERNV is not set | 21 | # CONFIG_PPC_POWERNV is not set |
| 22 | # CONFIG_PPC_PSERIES is not set | 22 | # CONFIG_PPC_PSERIES is not set |
| 23 | # CONFIG_PPC_PMAC is not set | 23 | # CONFIG_PPC_PMAC is not set |
| 24 | CONFIG_PPC_PS3=y | 24 | CONFIG_PPC_PS3=y |
| 25 | CONFIG_PS3_DISK=y | 25 | CONFIG_PS3_DISK=y |
| 26 | CONFIG_PS3_ROM=y | 26 | CONFIG_PS3_ROM=y |
| 27 | CONFIG_PS3_FLASH=y | 27 | CONFIG_PS3_FLASH=y |
| 28 | CONFIG_PS3_VRAM=m | 28 | CONFIG_PS3_VRAM=m |
| 29 | CONFIG_PS3_LPM=m | 29 | CONFIG_PS3_LPM=m |
| 30 | # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set | 30 | # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set |
| 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 31 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 32 | CONFIG_BINFMT_MISC=y | 32 | CONFIG_BINFMT_MISC=y |
| 33 | CONFIG_KEXEC=y | 33 | CONFIG_KEXEC=y |
| 34 | # CONFIG_SPARSEMEM_VMEMMAP is not set | 34 | # CONFIG_SPARSEMEM_VMEMMAP is not set |
| 35 | # CONFIG_COMPACTION is not set | 35 | # CONFIG_COMPACTION is not set |
| 36 | CONFIG_SCHED_SMT=y | 36 | CONFIG_SCHED_SMT=y |
| 37 | CONFIG_CMDLINE_BOOL=y | 37 | CONFIG_CMDLINE_BOOL=y |
| 38 | CONFIG_CMDLINE="" | 38 | CONFIG_CMDLINE="" |
| 39 | CONFIG_PM_RUNTIME=y | 39 | CONFIG_PM=y |
| 40 | CONFIG_PM_DEBUG=y | 40 | CONFIG_PM_DEBUG=y |
| 41 | # CONFIG_SECCOMP is not set | 41 | # CONFIG_SECCOMP is not set |
| 42 | # CONFIG_PCI is not set | 42 | # CONFIG_PCI is not set |
| 43 | CONFIG_NET=y | 43 | CONFIG_NET=y |
| 44 | CONFIG_PACKET=y | 44 | CONFIG_PACKET=y |
| 45 | CONFIG_UNIX=y | 45 | CONFIG_UNIX=y |
| 46 | CONFIG_INET=y | 46 | CONFIG_INET=y |
| 47 | CONFIG_IP_MULTICAST=y | 47 | CONFIG_IP_MULTICAST=y |
| 48 | CONFIG_IP_PNP=y | 48 | CONFIG_IP_PNP=y |
| 49 | CONFIG_IP_PNP_DHCP=y | 49 | CONFIG_IP_PNP_DHCP=y |
| 50 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 50 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 51 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 51 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 52 | # CONFIG_INET_XFRM_MODE_BEET is not set | 52 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 53 | # CONFIG_INET_LRO is not set | 53 | # CONFIG_INET_LRO is not set |
| 54 | # CONFIG_INET_DIAG is not set | 54 | # CONFIG_INET_DIAG is not set |
| 55 | CONFIG_IPV6=y | 55 | CONFIG_IPV6=y |
| 56 | CONFIG_BT=m | 56 | CONFIG_BT=m |
| 57 | CONFIG_BT_RFCOMM=m | 57 | CONFIG_BT_RFCOMM=m |
| 58 | CONFIG_BT_RFCOMM_TTY=y | 58 | CONFIG_BT_RFCOMM_TTY=y |
| 59 | CONFIG_BT_BNEP=m | 59 | CONFIG_BT_BNEP=m |
| 60 | CONFIG_BT_BNEP_MC_FILTER=y | 60 | CONFIG_BT_BNEP_MC_FILTER=y |
| 61 | CONFIG_BT_BNEP_PROTO_FILTER=y | 61 | CONFIG_BT_BNEP_PROTO_FILTER=y |
| 62 | CONFIG_BT_HIDP=m | 62 | CONFIG_BT_HIDP=m |
| 63 | CONFIG_BT_HCIBTUSB=m | 63 | CONFIG_BT_HCIBTUSB=m |
| 64 | CONFIG_CFG80211=m | 64 | CONFIG_CFG80211=m |
| 65 | CONFIG_CFG80211_WEXT=y | 65 | CONFIG_CFG80211_WEXT=y |
| 66 | CONFIG_MAC80211=m | 66 | CONFIG_MAC80211=m |
| 67 | CONFIG_MAC80211_RC_PID=y | 67 | CONFIG_MAC80211_RC_PID=y |
| 68 | # CONFIG_MAC80211_RC_MINSTREL is not set | 68 | # CONFIG_MAC80211_RC_MINSTREL is not set |
| 69 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 69 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 70 | # CONFIG_FIRMWARE_IN_KERNEL is not set | 70 | # CONFIG_FIRMWARE_IN_KERNEL is not set |
| 71 | CONFIG_PROC_DEVICETREE=y | 71 | CONFIG_PROC_DEVICETREE=y |
| 72 | CONFIG_BLK_DEV_LOOP=y | 72 | CONFIG_BLK_DEV_LOOP=y |
| 73 | CONFIG_BLK_DEV_RAM=y | 73 | CONFIG_BLK_DEV_RAM=y |
| 74 | CONFIG_BLK_DEV_RAM_SIZE=65535 | 74 | CONFIG_BLK_DEV_RAM_SIZE=65535 |
| 75 | CONFIG_SCSI=y | 75 | CONFIG_SCSI=y |
| 76 | CONFIG_BLK_DEV_SD=y | 76 | CONFIG_BLK_DEV_SD=y |
| 77 | CONFIG_BLK_DEV_SR=y | 77 | CONFIG_BLK_DEV_SR=y |
| 78 | CONFIG_CHR_DEV_SG=m | 78 | CONFIG_CHR_DEV_SG=m |
| 79 | CONFIG_SCSI_MULTI_LUN=y | 79 | CONFIG_SCSI_MULTI_LUN=y |
| 80 | # CONFIG_SCSI_LOWLEVEL is not set | 80 | # CONFIG_SCSI_LOWLEVEL is not set |
| 81 | CONFIG_MD=y | 81 | CONFIG_MD=y |
| 82 | CONFIG_BLK_DEV_DM=m | 82 | CONFIG_BLK_DEV_DM=m |
| 83 | CONFIG_NETDEVICES=y | 83 | CONFIG_NETDEVICES=y |
| 84 | # CONFIG_NET_VENDOR_BROADCOM is not set | 84 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 85 | # CONFIG_NET_VENDOR_INTEL is not set | 85 | # CONFIG_NET_VENDOR_INTEL is not set |
| 86 | # CONFIG_NET_VENDOR_MARVELL is not set | 86 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 87 | # CONFIG_NET_VENDOR_MICREL is not set | 87 | # CONFIG_NET_VENDOR_MICREL is not set |
| 88 | # CONFIG_NET_VENDOR_NATSEMI is not set | 88 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 89 | # CONFIG_NET_VENDOR_SEEQ is not set | 89 | # CONFIG_NET_VENDOR_SEEQ is not set |
| 90 | # CONFIG_NET_VENDOR_STMICRO is not set | 90 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 91 | CONFIG_GELIC_NET=y | 91 | CONFIG_GELIC_NET=y |
| 92 | CONFIG_GELIC_WIRELESS=y | 92 | CONFIG_GELIC_WIRELESS=y |
| 93 | # CONFIG_NET_VENDOR_XILINX is not set | 93 | # CONFIG_NET_VENDOR_XILINX is not set |
| 94 | CONFIG_USB_USBNET=m | 94 | CONFIG_USB_USBNET=m |
| 95 | # CONFIG_USB_NET_CDCETHER is not set | 95 | # CONFIG_USB_NET_CDCETHER is not set |
| 96 | # CONFIG_USB_NET_CDC_NCM is not set | 96 | # CONFIG_USB_NET_CDC_NCM is not set |
| 97 | # CONFIG_USB_NET_NET1080 is not set | 97 | # CONFIG_USB_NET_NET1080 is not set |
| 98 | # CONFIG_USB_NET_CDC_SUBSET is not set | 98 | # CONFIG_USB_NET_CDC_SUBSET is not set |
| 99 | # CONFIG_USB_NET_ZAURUS is not set | 99 | # CONFIG_USB_NET_ZAURUS is not set |
| 100 | CONFIG_INPUT_FF_MEMLESS=m | 100 | CONFIG_INPUT_FF_MEMLESS=m |
| 101 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 101 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 102 | CONFIG_INPUT_JOYDEV=m | 102 | CONFIG_INPUT_JOYDEV=m |
| 103 | CONFIG_INPUT_EVDEV=m | 103 | CONFIG_INPUT_EVDEV=m |
| 104 | # CONFIG_INPUT_KEYBOARD is not set | 104 | # CONFIG_INPUT_KEYBOARD is not set |
| 105 | # CONFIG_INPUT_MOUSE is not set | 105 | # CONFIG_INPUT_MOUSE is not set |
| 106 | # CONFIG_SERIO is not set | 106 | # CONFIG_SERIO is not set |
| 107 | # CONFIG_LEGACY_PTYS is not set | 107 | # CONFIG_LEGACY_PTYS is not set |
| 108 | # CONFIG_HW_RANDOM is not set | 108 | # CONFIG_HW_RANDOM is not set |
| 109 | # CONFIG_HWMON is not set | 109 | # CONFIG_HWMON is not set |
| 110 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 110 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 111 | CONFIG_FB=y | 111 | CONFIG_FB=y |
| 112 | CONFIG_FB_PS3=y | 112 | CONFIG_FB_PS3=y |
| 113 | # CONFIG_VGA_CONSOLE is not set | 113 | # CONFIG_VGA_CONSOLE is not set |
| 114 | CONFIG_FRAMEBUFFER_CONSOLE=y | 114 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 115 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | 115 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y |
| 116 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | 116 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y |
| 117 | CONFIG_LOGO=y | 117 | CONFIG_LOGO=y |
| 118 | # CONFIG_LOGO_LINUX_MONO is not set | 118 | # CONFIG_LOGO_LINUX_MONO is not set |
| 119 | # CONFIG_LOGO_LINUX_VGA16 is not set | 119 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 120 | CONFIG_SOUND=m | 120 | CONFIG_SOUND=m |
| 121 | CONFIG_SND=m | 121 | CONFIG_SND=m |
| 122 | # CONFIG_SND_DRIVERS is not set | 122 | # CONFIG_SND_DRIVERS is not set |
| 123 | CONFIG_SND_USB_AUDIO=m | 123 | CONFIG_SND_USB_AUDIO=m |
| 124 | CONFIG_HIDRAW=y | 124 | CONFIG_HIDRAW=y |
| 125 | CONFIG_HID_APPLE=m | 125 | CONFIG_HID_APPLE=m |
| 126 | CONFIG_HID_BELKIN=m | 126 | CONFIG_HID_BELKIN=m |
| 127 | CONFIG_HID_CHERRY=m | 127 | CONFIG_HID_CHERRY=m |
| 128 | CONFIG_HID_EZKEY=m | 128 | CONFIG_HID_EZKEY=m |
| 129 | CONFIG_HID_TWINHAN=m | 129 | CONFIG_HID_TWINHAN=m |
| 130 | CONFIG_HID_LOGITECH=m | 130 | CONFIG_HID_LOGITECH=m |
| 131 | CONFIG_HID_LOGITECH_DJ=m | 131 | CONFIG_HID_LOGITECH_DJ=m |
| 132 | CONFIG_HID_MICROSOFT=m | 132 | CONFIG_HID_MICROSOFT=m |
| 133 | CONFIG_HID_PS3REMOTE=m | 133 | CONFIG_HID_PS3REMOTE=m |
| 134 | CONFIG_HID_SONY=m | 134 | CONFIG_HID_SONY=m |
| 135 | CONFIG_HID_SUNPLUS=m | 135 | CONFIG_HID_SUNPLUS=m |
| 136 | CONFIG_HID_SMARTJOYPLUS=m | 136 | CONFIG_HID_SMARTJOYPLUS=m |
| 137 | CONFIG_USB_HIDDEV=y | 137 | CONFIG_USB_HIDDEV=y |
| 138 | CONFIG_USB=m | 138 | CONFIG_USB=m |
| 139 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 139 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
| 140 | CONFIG_USB_MON=m | 140 | CONFIG_USB_MON=m |
| 141 | CONFIG_USB_EHCI_HCD=m | 141 | CONFIG_USB_EHCI_HCD=m |
| 142 | # CONFIG_USB_EHCI_HCD_PPC_OF is not set | 142 | # CONFIG_USB_EHCI_HCD_PPC_OF is not set |
| 143 | CONFIG_USB_OHCI_HCD=m | 143 | CONFIG_USB_OHCI_HCD=m |
| 144 | CONFIG_USB_STORAGE=m | 144 | CONFIG_USB_STORAGE=m |
| 145 | CONFIG_RTC_CLASS=y | 145 | CONFIG_RTC_CLASS=y |
| 146 | CONFIG_RTC_DRV_PS3=y | 146 | CONFIG_RTC_DRV_PS3=y |
| 147 | # CONFIG_IOMMU_SUPPORT is not set | 147 | # CONFIG_IOMMU_SUPPORT is not set |
| 148 | CONFIG_EXT2_FS=m | 148 | CONFIG_EXT2_FS=m |
| 149 | CONFIG_EXT3_FS=m | 149 | CONFIG_EXT3_FS=m |
| 150 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 150 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 151 | CONFIG_EXT4_FS=y | 151 | CONFIG_EXT4_FS=y |
| 152 | CONFIG_QUOTA=y | 152 | CONFIG_QUOTA=y |
| 153 | CONFIG_QFMT_V2=y | 153 | CONFIG_QFMT_V2=y |
| 154 | CONFIG_AUTOFS4_FS=m | 154 | CONFIG_AUTOFS4_FS=m |
| 155 | CONFIG_ISO9660_FS=m | 155 | CONFIG_ISO9660_FS=m |
| 156 | CONFIG_JOLIET=y | 156 | CONFIG_JOLIET=y |
| 157 | CONFIG_UDF_FS=m | 157 | CONFIG_UDF_FS=m |
| 158 | CONFIG_VFAT_FS=m | 158 | CONFIG_VFAT_FS=m |
| 159 | CONFIG_PROC_KCORE=y | 159 | CONFIG_PROC_KCORE=y |
| 160 | CONFIG_TMPFS=y | 160 | CONFIG_TMPFS=y |
| 161 | CONFIG_HUGETLBFS=y | 161 | CONFIG_HUGETLBFS=y |
| 162 | CONFIG_NFS_FS=y | 162 | CONFIG_NFS_FS=y |
| 163 | CONFIG_NFS_V4=y | 163 | CONFIG_NFS_V4=y |
| 164 | CONFIG_NFS_SWAP=y | 164 | CONFIG_NFS_SWAP=y |
| 165 | CONFIG_ROOT_NFS=y | 165 | CONFIG_ROOT_NFS=y |
| 166 | CONFIG_CIFS=m | 166 | CONFIG_CIFS=m |
| 167 | CONFIG_NLS=y | 167 | CONFIG_NLS=y |
| 168 | CONFIG_NLS_CODEPAGE_437=y | 168 | CONFIG_NLS_CODEPAGE_437=y |
| 169 | CONFIG_NLS_ISO8859_1=y | 169 | CONFIG_NLS_ISO8859_1=y |
| 170 | CONFIG_CRC_CCITT=m | 170 | CONFIG_CRC_CCITT=m |
| 171 | CONFIG_CRC_T10DIF=y | 171 | CONFIG_CRC_T10DIF=y |
| 172 | CONFIG_MAGIC_SYSRQ=y | 172 | CONFIG_MAGIC_SYSRQ=y |
| 173 | CONFIG_DEBUG_FS=y | 173 | CONFIG_DEBUG_FS=y |
| 174 | CONFIG_DETECT_HUNG_TASK=y | 174 | CONFIG_DETECT_HUNG_TASK=y |
| 175 | CONFIG_PROVE_LOCKING=y | 175 | CONFIG_PROVE_LOCKING=y |
| 176 | CONFIG_DEBUG_LOCKDEP=y | 176 | CONFIG_DEBUG_LOCKDEP=y |
| 177 | CONFIG_DEBUG_INFO=y | 177 | CONFIG_DEBUG_INFO=y |
| 178 | CONFIG_DEBUG_MEMORY_INIT=y | 178 | CONFIG_DEBUG_MEMORY_INIT=y |
| 179 | CONFIG_DEBUG_LIST=y | 179 | CONFIG_DEBUG_LIST=y |
| 180 | CONFIG_RCU_CPU_STALL_TIMEOUT=60 | 180 | CONFIG_RCU_CPU_STALL_TIMEOUT=60 |
| 181 | # CONFIG_FTRACE is not set | 181 | # CONFIG_FTRACE is not set |
| 182 | CONFIG_DEBUG_STACKOVERFLOW=y | 182 | CONFIG_DEBUG_STACKOVERFLOW=y |
| 183 | CONFIG_CRYPTO_CCM=m | 183 | CONFIG_CRYPTO_CCM=m |
| 184 | CONFIG_CRYPTO_GCM=m | 184 | CONFIG_CRYPTO_GCM=m |
| 185 | CONFIG_CRYPTO_PCBC=m | 185 | CONFIG_CRYPTO_PCBC=m |
| 186 | CONFIG_CRYPTO_MICHAEL_MIC=m | 186 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 187 | CONFIG_CRYPTO_SALSA20=m | 187 | CONFIG_CRYPTO_SALSA20=m |
| 188 | CONFIG_CRYPTO_LZO=m | 188 | CONFIG_CRYPTO_LZO=m |
| 189 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 189 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 190 | 190 |
arch/sh/Kconfig
| 1 | config SUPERH | 1 | config SUPERH |
| 2 | def_bool y | 2 | def_bool y |
| 3 | select ARCH_MIGHT_HAVE_PC_PARPORT | 3 | select ARCH_MIGHT_HAVE_PC_PARPORT |
| 4 | select EXPERT | 4 | select EXPERT |
| 5 | select CLKDEV_LOOKUP | 5 | select CLKDEV_LOOKUP |
| 6 | select HAVE_IDE if HAS_IOPORT_MAP | 6 | select HAVE_IDE if HAS_IOPORT_MAP |
| 7 | select HAVE_MEMBLOCK | 7 | select HAVE_MEMBLOCK |
| 8 | select HAVE_MEMBLOCK_NODE_MAP | 8 | select HAVE_MEMBLOCK_NODE_MAP |
| 9 | select ARCH_DISCARD_MEMBLOCK | 9 | select ARCH_DISCARD_MEMBLOCK |
| 10 | select HAVE_OPROFILE | 10 | select HAVE_OPROFILE |
| 11 | select HAVE_GENERIC_DMA_COHERENT | 11 | select HAVE_GENERIC_DMA_COHERENT |
| 12 | select HAVE_ARCH_TRACEHOOK | 12 | select HAVE_ARCH_TRACEHOOK |
| 13 | select HAVE_DMA_API_DEBUG | 13 | select HAVE_DMA_API_DEBUG |
| 14 | select HAVE_DMA_ATTRS | 14 | select HAVE_DMA_ATTRS |
| 15 | select HAVE_PERF_EVENTS | 15 | select HAVE_PERF_EVENTS |
| 16 | select HAVE_DEBUG_BUGVERBOSE | 16 | select HAVE_DEBUG_BUGVERBOSE |
| 17 | select ARCH_HAVE_CUSTOM_GPIO_H | 17 | select ARCH_HAVE_CUSTOM_GPIO_H |
| 18 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) | 18 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) |
| 19 | select ARCH_HAS_GCOV_PROFILE_ALL | 19 | select ARCH_HAS_GCOV_PROFILE_ALL |
| 20 | select PERF_USE_VMALLOC | 20 | select PERF_USE_VMALLOC |
| 21 | select HAVE_DEBUG_KMEMLEAK | 21 | select HAVE_DEBUG_KMEMLEAK |
| 22 | select HAVE_KERNEL_GZIP | 22 | select HAVE_KERNEL_GZIP |
| 23 | select HAVE_KERNEL_BZIP2 | 23 | select HAVE_KERNEL_BZIP2 |
| 24 | select HAVE_KERNEL_LZMA | 24 | select HAVE_KERNEL_LZMA |
| 25 | select HAVE_KERNEL_XZ | 25 | select HAVE_KERNEL_XZ |
| 26 | select HAVE_KERNEL_LZO | 26 | select HAVE_KERNEL_LZO |
| 27 | select HAVE_UID16 | 27 | select HAVE_UID16 |
| 28 | select ARCH_WANT_IPC_PARSE_VERSION | 28 | select ARCH_WANT_IPC_PARSE_VERSION |
| 29 | select HAVE_SYSCALL_TRACEPOINTS | 29 | select HAVE_SYSCALL_TRACEPOINTS |
| 30 | select HAVE_REGS_AND_STACK_ACCESS_API | 30 | select HAVE_REGS_AND_STACK_ACCESS_API |
| 31 | select MAY_HAVE_SPARSE_IRQ | 31 | select MAY_HAVE_SPARSE_IRQ |
| 32 | select IRQ_FORCED_THREADING | 32 | select IRQ_FORCED_THREADING |
| 33 | select RTC_LIB | 33 | select RTC_LIB |
| 34 | select GENERIC_ATOMIC64 | 34 | select GENERIC_ATOMIC64 |
| 35 | select GENERIC_IRQ_SHOW | 35 | select GENERIC_IRQ_SHOW |
| 36 | select GENERIC_SMP_IDLE_THREAD | 36 | select GENERIC_SMP_IDLE_THREAD |
| 37 | select GENERIC_IDLE_POLL_SETUP | 37 | select GENERIC_IDLE_POLL_SETUP |
| 38 | select GENERIC_CLOCKEVENTS | 38 | select GENERIC_CLOCKEVENTS |
| 39 | select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST | 39 | select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST |
| 40 | select GENERIC_STRNCPY_FROM_USER | 40 | select GENERIC_STRNCPY_FROM_USER |
| 41 | select GENERIC_STRNLEN_USER | 41 | select GENERIC_STRNLEN_USER |
| 42 | select HAVE_MOD_ARCH_SPECIFIC if DWARF_UNWINDER | 42 | select HAVE_MOD_ARCH_SPECIFIC if DWARF_UNWINDER |
| 43 | select MODULES_USE_ELF_RELA | 43 | select MODULES_USE_ELF_RELA |
| 44 | select OLD_SIGSUSPEND | 44 | select OLD_SIGSUSPEND |
| 45 | select OLD_SIGACTION | 45 | select OLD_SIGACTION |
| 46 | select HAVE_ARCH_AUDITSYSCALL | 46 | select HAVE_ARCH_AUDITSYSCALL |
| 47 | help | 47 | help |
| 48 | The SuperH is a RISC processor targeted for use in embedded systems | 48 | The SuperH is a RISC processor targeted for use in embedded systems |
| 49 | and consumer electronics; it was also used in the Sega Dreamcast | 49 | and consumer electronics; it was also used in the Sega Dreamcast |
| 50 | gaming console. The SuperH port has a home page at | 50 | gaming console. The SuperH port has a home page at |
| 51 | <http://www.linux-sh.org/>. | 51 | <http://www.linux-sh.org/>. |
| 52 | 52 | ||
| 53 | config SUPERH32 | 53 | config SUPERH32 |
| 54 | def_bool ARCH = "sh" | 54 | def_bool ARCH = "sh" |
| 55 | select HAVE_KPROBES | 55 | select HAVE_KPROBES |
| 56 | select HAVE_KRETPROBES | 56 | select HAVE_KRETPROBES |
| 57 | select HAVE_IOREMAP_PROT if MMU && !X2TLB | 57 | select HAVE_IOREMAP_PROT if MMU && !X2TLB |
| 58 | select HAVE_FUNCTION_TRACER | 58 | select HAVE_FUNCTION_TRACER |
| 59 | select HAVE_FTRACE_MCOUNT_RECORD | 59 | select HAVE_FTRACE_MCOUNT_RECORD |
| 60 | select HAVE_DYNAMIC_FTRACE | 60 | select HAVE_DYNAMIC_FTRACE |
| 61 | select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE | 61 | select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE |
| 62 | select ARCH_WANT_IPC_PARSE_VERSION | 62 | select ARCH_WANT_IPC_PARSE_VERSION |
| 63 | select HAVE_FUNCTION_GRAPH_TRACER | 63 | select HAVE_FUNCTION_GRAPH_TRACER |
| 64 | select HAVE_ARCH_KGDB | 64 | select HAVE_ARCH_KGDB |
| 65 | select HAVE_HW_BREAKPOINT | 65 | select HAVE_HW_BREAKPOINT |
| 66 | select HAVE_MIXED_BREAKPOINTS_REGS | 66 | select HAVE_MIXED_BREAKPOINTS_REGS |
| 67 | select PERF_EVENTS | 67 | select PERF_EVENTS |
| 68 | select ARCH_HIBERNATION_POSSIBLE if MMU | 68 | select ARCH_HIBERNATION_POSSIBLE if MMU |
| 69 | select SPARSE_IRQ | 69 | select SPARSE_IRQ |
| 70 | select HAVE_CC_STACKPROTECTOR | 70 | select HAVE_CC_STACKPROTECTOR |
| 71 | 71 | ||
| 72 | config SUPERH64 | 72 | config SUPERH64 |
| 73 | def_bool ARCH = "sh64" | 73 | def_bool ARCH = "sh64" |
| 74 | select KALLSYMS | 74 | select KALLSYMS |
| 75 | 75 | ||
| 76 | config ARCH_DEFCONFIG | 76 | config ARCH_DEFCONFIG |
| 77 | string | 77 | string |
| 78 | default "arch/sh/configs/shx3_defconfig" if SUPERH32 | 78 | default "arch/sh/configs/shx3_defconfig" if SUPERH32 |
| 79 | default "arch/sh/configs/cayman_defconfig" if SUPERH64 | 79 | default "arch/sh/configs/cayman_defconfig" if SUPERH64 |
| 80 | 80 | ||
| 81 | config RWSEM_GENERIC_SPINLOCK | 81 | config RWSEM_GENERIC_SPINLOCK |
| 82 | def_bool y | 82 | def_bool y |
| 83 | 83 | ||
| 84 | config RWSEM_XCHGADD_ALGORITHM | 84 | config RWSEM_XCHGADD_ALGORITHM |
| 85 | bool | 85 | bool |
| 86 | 86 | ||
| 87 | config GENERIC_BUG | 87 | config GENERIC_BUG |
| 88 | def_bool y | 88 | def_bool y |
| 89 | depends on BUG && SUPERH32 | 89 | depends on BUG && SUPERH32 |
| 90 | 90 | ||
| 91 | config GENERIC_CSUM | 91 | config GENERIC_CSUM |
| 92 | def_bool y | 92 | def_bool y |
| 93 | depends on SUPERH64 | 93 | depends on SUPERH64 |
| 94 | 94 | ||
| 95 | config GENERIC_HWEIGHT | 95 | config GENERIC_HWEIGHT |
| 96 | def_bool y | 96 | def_bool y |
| 97 | 97 | ||
| 98 | config GENERIC_CALIBRATE_DELAY | 98 | config GENERIC_CALIBRATE_DELAY |
| 99 | bool | 99 | bool |
| 100 | 100 | ||
| 101 | config GENERIC_LOCKBREAK | 101 | config GENERIC_LOCKBREAK |
| 102 | def_bool y | 102 | def_bool y |
| 103 | depends on SMP && PREEMPT | 103 | depends on SMP && PREEMPT |
| 104 | 104 | ||
| 105 | config ARCH_SUSPEND_POSSIBLE | 105 | config ARCH_SUSPEND_POSSIBLE |
| 106 | def_bool n | 106 | def_bool n |
| 107 | 107 | ||
| 108 | config ARCH_HIBERNATION_POSSIBLE | 108 | config ARCH_HIBERNATION_POSSIBLE |
| 109 | def_bool n | 109 | def_bool n |
| 110 | 110 | ||
| 111 | config SYS_SUPPORTS_APM_EMULATION | 111 | config SYS_SUPPORTS_APM_EMULATION |
| 112 | bool | 112 | bool |
| 113 | select ARCH_SUSPEND_POSSIBLE | 113 | select ARCH_SUSPEND_POSSIBLE |
| 114 | 114 | ||
| 115 | config SYS_SUPPORTS_HUGETLBFS | 115 | config SYS_SUPPORTS_HUGETLBFS |
| 116 | bool | 116 | bool |
| 117 | 117 | ||
| 118 | config SYS_SUPPORTS_SMP | 118 | config SYS_SUPPORTS_SMP |
| 119 | bool | 119 | bool |
| 120 | 120 | ||
| 121 | config SYS_SUPPORTS_NUMA | 121 | config SYS_SUPPORTS_NUMA |
| 122 | bool | 122 | bool |
| 123 | 123 | ||
| 124 | config SYS_SUPPORTS_PCI | 124 | config SYS_SUPPORTS_PCI |
| 125 | bool | 125 | bool |
| 126 | 126 | ||
| 127 | config STACKTRACE_SUPPORT | 127 | config STACKTRACE_SUPPORT |
| 128 | def_bool y | 128 | def_bool y |
| 129 | 129 | ||
| 130 | config LOCKDEP_SUPPORT | 130 | config LOCKDEP_SUPPORT |
| 131 | def_bool y | 131 | def_bool y |
| 132 | 132 | ||
| 133 | config HAVE_LATENCYTOP_SUPPORT | 133 | config HAVE_LATENCYTOP_SUPPORT |
| 134 | def_bool y | 134 | def_bool y |
| 135 | 135 | ||
| 136 | config ARCH_HAS_ILOG2_U32 | 136 | config ARCH_HAS_ILOG2_U32 |
| 137 | def_bool n | 137 | def_bool n |
| 138 | 138 | ||
| 139 | config ARCH_HAS_ILOG2_U64 | 139 | config ARCH_HAS_ILOG2_U64 |
| 140 | def_bool n | 140 | def_bool n |
| 141 | 141 | ||
| 142 | config NO_IOPORT_MAP | 142 | config NO_IOPORT_MAP |
| 143 | def_bool !PCI | 143 | def_bool !PCI |
| 144 | depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \ | 144 | depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \ |
| 145 | !SH_HP6XX && !SH_SOLUTION_ENGINE | 145 | !SH_HP6XX && !SH_SOLUTION_ENGINE |
| 146 | 146 | ||
| 147 | config IO_TRAPPED | 147 | config IO_TRAPPED |
| 148 | bool | 148 | bool |
| 149 | 149 | ||
| 150 | config SWAP_IO_SPACE | 150 | config SWAP_IO_SPACE |
| 151 | bool | 151 | bool |
| 152 | 152 | ||
| 153 | config DMA_COHERENT | 153 | config DMA_COHERENT |
| 154 | bool | 154 | bool |
| 155 | 155 | ||
| 156 | config DMA_NONCOHERENT | 156 | config DMA_NONCOHERENT |
| 157 | def_bool !DMA_COHERENT | 157 | def_bool !DMA_COHERENT |
| 158 | 158 | ||
| 159 | config NEED_DMA_MAP_STATE | 159 | config NEED_DMA_MAP_STATE |
| 160 | def_bool DMA_NONCOHERENT | 160 | def_bool DMA_NONCOHERENT |
| 161 | 161 | ||
| 162 | config NEED_SG_DMA_LENGTH | 162 | config NEED_SG_DMA_LENGTH |
| 163 | def_bool y | 163 | def_bool y |
| 164 | 164 | ||
| 165 | source "init/Kconfig" | 165 | source "init/Kconfig" |
| 166 | 166 | ||
| 167 | source "kernel/Kconfig.freezer" | 167 | source "kernel/Kconfig.freezer" |
| 168 | 168 | ||
| 169 | menu "System type" | 169 | menu "System type" |
| 170 | 170 | ||
| 171 | # | 171 | # |
| 172 | # Processor families | 172 | # Processor families |
| 173 | # | 173 | # |
| 174 | config CPU_SH2 | 174 | config CPU_SH2 |
| 175 | bool | 175 | bool |
| 176 | select SH_INTC | 176 | select SH_INTC |
| 177 | 177 | ||
| 178 | config CPU_SH2A | 178 | config CPU_SH2A |
| 179 | bool | 179 | bool |
| 180 | select CPU_SH2 | 180 | select CPU_SH2 |
| 181 | select UNCACHED_MAPPING | 181 | select UNCACHED_MAPPING |
| 182 | 182 | ||
| 183 | config CPU_SH3 | 183 | config CPU_SH3 |
| 184 | bool | 184 | bool |
| 185 | select CPU_HAS_INTEVT | 185 | select CPU_HAS_INTEVT |
| 186 | select CPU_HAS_SR_RB | 186 | select CPU_HAS_SR_RB |
| 187 | select SH_INTC | 187 | select SH_INTC |
| 188 | select SYS_SUPPORTS_SH_TMU | 188 | select SYS_SUPPORTS_SH_TMU |
| 189 | 189 | ||
| 190 | config CPU_SH4 | 190 | config CPU_SH4 |
| 191 | bool | 191 | bool |
| 192 | select CPU_HAS_INTEVT | 192 | select CPU_HAS_INTEVT |
| 193 | select CPU_HAS_SR_RB | 193 | select CPU_HAS_SR_RB |
| 194 | select CPU_HAS_FPU if !CPU_SH4AL_DSP | 194 | select CPU_HAS_FPU if !CPU_SH4AL_DSP |
| 195 | select SH_INTC | 195 | select SH_INTC |
| 196 | select SYS_SUPPORTS_SH_TMU | 196 | select SYS_SUPPORTS_SH_TMU |
| 197 | select SYS_SUPPORTS_HUGETLBFS if MMU | 197 | select SYS_SUPPORTS_HUGETLBFS if MMU |
| 198 | 198 | ||
| 199 | config CPU_SH4A | 199 | config CPU_SH4A |
| 200 | bool | 200 | bool |
| 201 | select CPU_SH4 | 201 | select CPU_SH4 |
| 202 | 202 | ||
| 203 | config CPU_SH4AL_DSP | 203 | config CPU_SH4AL_DSP |
| 204 | bool | 204 | bool |
| 205 | select CPU_SH4A | 205 | select CPU_SH4A |
| 206 | select CPU_HAS_DSP | 206 | select CPU_HAS_DSP |
| 207 | 207 | ||
| 208 | config CPU_SH5 | 208 | config CPU_SH5 |
| 209 | bool | 209 | bool |
| 210 | select CPU_HAS_FPU | 210 | select CPU_HAS_FPU |
| 211 | select SYS_SUPPORTS_SH_TMU | 211 | select SYS_SUPPORTS_SH_TMU |
| 212 | select SYS_SUPPORTS_HUGETLBFS if MMU | 212 | select SYS_SUPPORTS_HUGETLBFS if MMU |
| 213 | 213 | ||
| 214 | config CPU_SHX2 | 214 | config CPU_SHX2 |
| 215 | bool | 215 | bool |
| 216 | 216 | ||
| 217 | config CPU_SHX3 | 217 | config CPU_SHX3 |
| 218 | bool | 218 | bool |
| 219 | select DMA_COHERENT | 219 | select DMA_COHERENT |
| 220 | select SYS_SUPPORTS_SMP | 220 | select SYS_SUPPORTS_SMP |
| 221 | select SYS_SUPPORTS_NUMA | 221 | select SYS_SUPPORTS_NUMA |
| 222 | 222 | ||
| 223 | config ARCH_SHMOBILE | 223 | config ARCH_SHMOBILE |
| 224 | bool | 224 | bool |
| 225 | select ARCH_SUSPEND_POSSIBLE | 225 | select ARCH_SUSPEND_POSSIBLE |
| 226 | select PM_RUNTIME | 226 | select PM |
| 227 | 227 | ||
| 228 | config CPU_HAS_PMU | 228 | config CPU_HAS_PMU |
| 229 | depends on CPU_SH4 || CPU_SH4A | 229 | depends on CPU_SH4 || CPU_SH4A |
| 230 | default y | 230 | default y |
| 231 | bool | 231 | bool |
| 232 | 232 | ||
| 233 | if SUPERH32 | 233 | if SUPERH32 |
| 234 | 234 | ||
| 235 | choice | 235 | choice |
| 236 | prompt "Processor sub-type selection" | 236 | prompt "Processor sub-type selection" |
| 237 | 237 | ||
| 238 | # | 238 | # |
| 239 | # Processor subtypes | 239 | # Processor subtypes |
| 240 | # | 240 | # |
| 241 | 241 | ||
| 242 | # SH-2 Processor Support | 242 | # SH-2 Processor Support |
| 243 | 243 | ||
| 244 | config CPU_SUBTYPE_SH7619 | 244 | config CPU_SUBTYPE_SH7619 |
| 245 | bool "Support SH7619 processor" | 245 | bool "Support SH7619 processor" |
| 246 | select CPU_SH2 | 246 | select CPU_SH2 |
| 247 | select SYS_SUPPORTS_SH_CMT | 247 | select SYS_SUPPORTS_SH_CMT |
| 248 | 248 | ||
| 249 | # SH-2A Processor Support | 249 | # SH-2A Processor Support |
| 250 | 250 | ||
| 251 | config CPU_SUBTYPE_SH7201 | 251 | config CPU_SUBTYPE_SH7201 |
| 252 | bool "Support SH7201 processor" | 252 | bool "Support SH7201 processor" |
| 253 | select CPU_SH2A | 253 | select CPU_SH2A |
| 254 | select CPU_HAS_FPU | 254 | select CPU_HAS_FPU |
| 255 | select SYS_SUPPORTS_SH_MTU2 | 255 | select SYS_SUPPORTS_SH_MTU2 |
| 256 | 256 | ||
| 257 | config CPU_SUBTYPE_SH7203 | 257 | config CPU_SUBTYPE_SH7203 |
| 258 | bool "Support SH7203 processor" | 258 | bool "Support SH7203 processor" |
| 259 | select CPU_SH2A | 259 | select CPU_SH2A |
| 260 | select CPU_HAS_FPU | 260 | select CPU_HAS_FPU |
| 261 | select SYS_SUPPORTS_SH_CMT | 261 | select SYS_SUPPORTS_SH_CMT |
| 262 | select SYS_SUPPORTS_SH_MTU2 | 262 | select SYS_SUPPORTS_SH_MTU2 |
| 263 | select ARCH_WANT_OPTIONAL_GPIOLIB | 263 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 264 | select PINCTRL | 264 | select PINCTRL |
| 265 | 265 | ||
| 266 | config CPU_SUBTYPE_SH7206 | 266 | config CPU_SUBTYPE_SH7206 |
| 267 | bool "Support SH7206 processor" | 267 | bool "Support SH7206 processor" |
| 268 | select CPU_SH2A | 268 | select CPU_SH2A |
| 269 | select SYS_SUPPORTS_SH_CMT | 269 | select SYS_SUPPORTS_SH_CMT |
| 270 | select SYS_SUPPORTS_SH_MTU2 | 270 | select SYS_SUPPORTS_SH_MTU2 |
| 271 | 271 | ||
| 272 | config CPU_SUBTYPE_SH7263 | 272 | config CPU_SUBTYPE_SH7263 |
| 273 | bool "Support SH7263 processor" | 273 | bool "Support SH7263 processor" |
| 274 | select CPU_SH2A | 274 | select CPU_SH2A |
| 275 | select CPU_HAS_FPU | 275 | select CPU_HAS_FPU |
| 276 | select SYS_SUPPORTS_SH_CMT | 276 | select SYS_SUPPORTS_SH_CMT |
| 277 | select SYS_SUPPORTS_SH_MTU2 | 277 | select SYS_SUPPORTS_SH_MTU2 |
| 278 | 278 | ||
| 279 | config CPU_SUBTYPE_SH7264 | 279 | config CPU_SUBTYPE_SH7264 |
| 280 | bool "Support SH7264 processor" | 280 | bool "Support SH7264 processor" |
| 281 | select CPU_SH2A | 281 | select CPU_SH2A |
| 282 | select CPU_HAS_FPU | 282 | select CPU_HAS_FPU |
| 283 | select SYS_SUPPORTS_SH_CMT | 283 | select SYS_SUPPORTS_SH_CMT |
| 284 | select SYS_SUPPORTS_SH_MTU2 | 284 | select SYS_SUPPORTS_SH_MTU2 |
| 285 | select PINCTRL | 285 | select PINCTRL |
| 286 | 286 | ||
| 287 | config CPU_SUBTYPE_SH7269 | 287 | config CPU_SUBTYPE_SH7269 |
| 288 | bool "Support SH7269 processor" | 288 | bool "Support SH7269 processor" |
| 289 | select CPU_SH2A | 289 | select CPU_SH2A |
| 290 | select CPU_HAS_FPU | 290 | select CPU_HAS_FPU |
| 291 | select SYS_SUPPORTS_SH_CMT | 291 | select SYS_SUPPORTS_SH_CMT |
| 292 | select SYS_SUPPORTS_SH_MTU2 | 292 | select SYS_SUPPORTS_SH_MTU2 |
| 293 | select PINCTRL | 293 | select PINCTRL |
| 294 | 294 | ||
| 295 | config CPU_SUBTYPE_MXG | 295 | config CPU_SUBTYPE_MXG |
| 296 | bool "Support MX-G processor" | 296 | bool "Support MX-G processor" |
| 297 | select CPU_SH2A | 297 | select CPU_SH2A |
| 298 | select SYS_SUPPORTS_SH_MTU2 | 298 | select SYS_SUPPORTS_SH_MTU2 |
| 299 | help | 299 | help |
| 300 | Select MX-G if running on an R8A03022BG part. | 300 | Select MX-G if running on an R8A03022BG part. |
| 301 | 301 | ||
| 302 | # SH-3 Processor Support | 302 | # SH-3 Processor Support |
| 303 | 303 | ||
| 304 | config CPU_SUBTYPE_SH7705 | 304 | config CPU_SUBTYPE_SH7705 |
| 305 | bool "Support SH7705 processor" | 305 | bool "Support SH7705 processor" |
| 306 | select CPU_SH3 | 306 | select CPU_SH3 |
| 307 | 307 | ||
| 308 | config CPU_SUBTYPE_SH7706 | 308 | config CPU_SUBTYPE_SH7706 |
| 309 | bool "Support SH7706 processor" | 309 | bool "Support SH7706 processor" |
| 310 | select CPU_SH3 | 310 | select CPU_SH3 |
| 311 | help | 311 | help |
| 312 | Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. | 312 | Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. |
| 313 | 313 | ||
| 314 | config CPU_SUBTYPE_SH7707 | 314 | config CPU_SUBTYPE_SH7707 |
| 315 | bool "Support SH7707 processor" | 315 | bool "Support SH7707 processor" |
| 316 | select CPU_SH3 | 316 | select CPU_SH3 |
| 317 | help | 317 | help |
| 318 | Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. | 318 | Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. |
| 319 | 319 | ||
| 320 | config CPU_SUBTYPE_SH7708 | 320 | config CPU_SUBTYPE_SH7708 |
| 321 | bool "Support SH7708 processor" | 321 | bool "Support SH7708 processor" |
| 322 | select CPU_SH3 | 322 | select CPU_SH3 |
| 323 | help | 323 | help |
| 324 | Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or | 324 | Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or |
| 325 | if you have a 100 Mhz SH-3 HD6417708R CPU. | 325 | if you have a 100 Mhz SH-3 HD6417708R CPU. |
| 326 | 326 | ||
| 327 | config CPU_SUBTYPE_SH7709 | 327 | config CPU_SUBTYPE_SH7709 |
| 328 | bool "Support SH7709 processor" | 328 | bool "Support SH7709 processor" |
| 329 | select CPU_SH3 | 329 | select CPU_SH3 |
| 330 | help | 330 | help |
| 331 | Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. | 331 | Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. |
| 332 | 332 | ||
| 333 | config CPU_SUBTYPE_SH7710 | 333 | config CPU_SUBTYPE_SH7710 |
| 334 | bool "Support SH7710 processor" | 334 | bool "Support SH7710 processor" |
| 335 | select CPU_SH3 | 335 | select CPU_SH3 |
| 336 | select CPU_HAS_DSP | 336 | select CPU_HAS_DSP |
| 337 | help | 337 | help |
| 338 | Select SH7710 if you have a SH3-DSP SH7710 CPU. | 338 | Select SH7710 if you have a SH3-DSP SH7710 CPU. |
| 339 | 339 | ||
| 340 | config CPU_SUBTYPE_SH7712 | 340 | config CPU_SUBTYPE_SH7712 |
| 341 | bool "Support SH7712 processor" | 341 | bool "Support SH7712 processor" |
| 342 | select CPU_SH3 | 342 | select CPU_SH3 |
| 343 | select CPU_HAS_DSP | 343 | select CPU_HAS_DSP |
| 344 | help | 344 | help |
| 345 | Select SH7712 if you have a SH3-DSP SH7712 CPU. | 345 | Select SH7712 if you have a SH3-DSP SH7712 CPU. |
| 346 | 346 | ||
| 347 | config CPU_SUBTYPE_SH7720 | 347 | config CPU_SUBTYPE_SH7720 |
| 348 | bool "Support SH7720 processor" | 348 | bool "Support SH7720 processor" |
| 349 | select CPU_SH3 | 349 | select CPU_SH3 |
| 350 | select CPU_HAS_DSP | 350 | select CPU_HAS_DSP |
| 351 | select SYS_SUPPORTS_SH_CMT | 351 | select SYS_SUPPORTS_SH_CMT |
| 352 | select ARCH_WANT_OPTIONAL_GPIOLIB | 352 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 353 | select USB_OHCI_SH if USB_OHCI_HCD | 353 | select USB_OHCI_SH if USB_OHCI_HCD |
| 354 | select PINCTRL | 354 | select PINCTRL |
| 355 | help | 355 | help |
| 356 | Select SH7720 if you have a SH3-DSP SH7720 CPU. | 356 | Select SH7720 if you have a SH3-DSP SH7720 CPU. |
| 357 | 357 | ||
| 358 | config CPU_SUBTYPE_SH7721 | 358 | config CPU_SUBTYPE_SH7721 |
| 359 | bool "Support SH7721 processor" | 359 | bool "Support SH7721 processor" |
| 360 | select CPU_SH3 | 360 | select CPU_SH3 |
| 361 | select CPU_HAS_DSP | 361 | select CPU_HAS_DSP |
| 362 | select SYS_SUPPORTS_SH_CMT | 362 | select SYS_SUPPORTS_SH_CMT |
| 363 | select USB_OHCI_SH if USB_OHCI_HCD | 363 | select USB_OHCI_SH if USB_OHCI_HCD |
| 364 | help | 364 | help |
| 365 | Select SH7721 if you have a SH3-DSP SH7721 CPU. | 365 | Select SH7721 if you have a SH3-DSP SH7721 CPU. |
| 366 | 366 | ||
| 367 | # SH-4 Processor Support | 367 | # SH-4 Processor Support |
| 368 | 368 | ||
| 369 | config CPU_SUBTYPE_SH7750 | 369 | config CPU_SUBTYPE_SH7750 |
| 370 | bool "Support SH7750 processor" | 370 | bool "Support SH7750 processor" |
| 371 | select CPU_SH4 | 371 | select CPU_SH4 |
| 372 | help | 372 | help |
| 373 | Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. | 373 | Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. |
| 374 | 374 | ||
| 375 | config CPU_SUBTYPE_SH7091 | 375 | config CPU_SUBTYPE_SH7091 |
| 376 | bool "Support SH7091 processor" | 376 | bool "Support SH7091 processor" |
| 377 | select CPU_SH4 | 377 | select CPU_SH4 |
| 378 | help | 378 | help |
| 379 | Select SH7091 if you have an SH-4 based Sega device (such as | 379 | Select SH7091 if you have an SH-4 based Sega device (such as |
| 380 | the Dreamcast, Naomi, and Naomi 2). | 380 | the Dreamcast, Naomi, and Naomi 2). |
| 381 | 381 | ||
| 382 | config CPU_SUBTYPE_SH7750R | 382 | config CPU_SUBTYPE_SH7750R |
| 383 | bool "Support SH7750R processor" | 383 | bool "Support SH7750R processor" |
| 384 | select CPU_SH4 | 384 | select CPU_SH4 |
| 385 | 385 | ||
| 386 | config CPU_SUBTYPE_SH7750S | 386 | config CPU_SUBTYPE_SH7750S |
| 387 | bool "Support SH7750S processor" | 387 | bool "Support SH7750S processor" |
| 388 | select CPU_SH4 | 388 | select CPU_SH4 |
| 389 | 389 | ||
| 390 | config CPU_SUBTYPE_SH7751 | 390 | config CPU_SUBTYPE_SH7751 |
| 391 | bool "Support SH7751 processor" | 391 | bool "Support SH7751 processor" |
| 392 | select CPU_SH4 | 392 | select CPU_SH4 |
| 393 | help | 393 | help |
| 394 | Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, | 394 | Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, |
| 395 | or if you have a HD6417751R CPU. | 395 | or if you have a HD6417751R CPU. |
| 396 | 396 | ||
| 397 | config CPU_SUBTYPE_SH7751R | 397 | config CPU_SUBTYPE_SH7751R |
| 398 | bool "Support SH7751R processor" | 398 | bool "Support SH7751R processor" |
| 399 | select CPU_SH4 | 399 | select CPU_SH4 |
| 400 | 400 | ||
| 401 | config CPU_SUBTYPE_SH7760 | 401 | config CPU_SUBTYPE_SH7760 |
| 402 | bool "Support SH7760 processor" | 402 | bool "Support SH7760 processor" |
| 403 | select CPU_SH4 | 403 | select CPU_SH4 |
| 404 | 404 | ||
| 405 | config CPU_SUBTYPE_SH4_202 | 405 | config CPU_SUBTYPE_SH4_202 |
| 406 | bool "Support SH4-202 processor" | 406 | bool "Support SH4-202 processor" |
| 407 | select CPU_SH4 | 407 | select CPU_SH4 |
| 408 | 408 | ||
| 409 | # SH-4A Processor Support | 409 | # SH-4A Processor Support |
| 410 | 410 | ||
| 411 | config CPU_SUBTYPE_SH7723 | 411 | config CPU_SUBTYPE_SH7723 |
| 412 | bool "Support SH7723 processor" | 412 | bool "Support SH7723 processor" |
| 413 | select CPU_SH4A | 413 | select CPU_SH4A |
| 414 | select CPU_SHX2 | 414 | select CPU_SHX2 |
| 415 | select ARCH_SHMOBILE | 415 | select ARCH_SHMOBILE |
| 416 | select ARCH_SPARSEMEM_ENABLE | 416 | select ARCH_SPARSEMEM_ENABLE |
| 417 | select SYS_SUPPORTS_SH_CMT | 417 | select SYS_SUPPORTS_SH_CMT |
| 418 | select ARCH_WANT_OPTIONAL_GPIOLIB | 418 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 419 | select PINCTRL | 419 | select PINCTRL |
| 420 | help | 420 | help |
| 421 | Select SH7723 if you have an SH-MobileR2 CPU. | 421 | Select SH7723 if you have an SH-MobileR2 CPU. |
| 422 | 422 | ||
| 423 | config CPU_SUBTYPE_SH7724 | 423 | config CPU_SUBTYPE_SH7724 |
| 424 | bool "Support SH7724 processor" | 424 | bool "Support SH7724 processor" |
| 425 | select CPU_SH4A | 425 | select CPU_SH4A |
| 426 | select CPU_SHX2 | 426 | select CPU_SHX2 |
| 427 | select ARCH_SHMOBILE | 427 | select ARCH_SHMOBILE |
| 428 | select ARCH_SPARSEMEM_ENABLE | 428 | select ARCH_SPARSEMEM_ENABLE |
| 429 | select SYS_SUPPORTS_SH_CMT | 429 | select SYS_SUPPORTS_SH_CMT |
| 430 | select ARCH_WANT_OPTIONAL_GPIOLIB | 430 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 431 | select PINCTRL | 431 | select PINCTRL |
| 432 | help | 432 | help |
| 433 | Select SH7724 if you have an SH-MobileR2R CPU. | 433 | Select SH7724 if you have an SH-MobileR2R CPU. |
| 434 | 434 | ||
| 435 | config CPU_SUBTYPE_SH7734 | 435 | config CPU_SUBTYPE_SH7734 |
| 436 | bool "Support SH7734 processor" | 436 | bool "Support SH7734 processor" |
| 437 | select CPU_SH4A | 437 | select CPU_SH4A |
| 438 | select CPU_SHX2 | 438 | select CPU_SHX2 |
| 439 | select ARCH_WANT_OPTIONAL_GPIOLIB | 439 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 440 | select PINCTRL | 440 | select PINCTRL |
| 441 | help | 441 | help |
| 442 | Select SH7734 if you have a SH4A SH7734 CPU. | 442 | Select SH7734 if you have a SH4A SH7734 CPU. |
| 443 | 443 | ||
| 444 | config CPU_SUBTYPE_SH7757 | 444 | config CPU_SUBTYPE_SH7757 |
| 445 | bool "Support SH7757 processor" | 445 | bool "Support SH7757 processor" |
| 446 | select CPU_SH4A | 446 | select CPU_SH4A |
| 447 | select CPU_SHX2 | 447 | select CPU_SHX2 |
| 448 | select ARCH_WANT_OPTIONAL_GPIOLIB | 448 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 449 | select PINCTRL | 449 | select PINCTRL |
| 450 | help | 450 | help |
| 451 | Select SH7757 if you have a SH4A SH7757 CPU. | 451 | Select SH7757 if you have a SH4A SH7757 CPU. |
| 452 | 452 | ||
| 453 | config CPU_SUBTYPE_SH7763 | 453 | config CPU_SUBTYPE_SH7763 |
| 454 | bool "Support SH7763 processor" | 454 | bool "Support SH7763 processor" |
| 455 | select CPU_SH4A | 455 | select CPU_SH4A |
| 456 | select USB_OHCI_SH if USB_OHCI_HCD | 456 | select USB_OHCI_SH if USB_OHCI_HCD |
| 457 | help | 457 | help |
| 458 | Select SH7763 if you have a SH4A SH7763(R5S77631) CPU. | 458 | Select SH7763 if you have a SH4A SH7763(R5S77631) CPU. |
| 459 | 459 | ||
| 460 | config CPU_SUBTYPE_SH7770 | 460 | config CPU_SUBTYPE_SH7770 |
| 461 | bool "Support SH7770 processor" | 461 | bool "Support SH7770 processor" |
| 462 | select CPU_SH4A | 462 | select CPU_SH4A |
| 463 | 463 | ||
| 464 | config CPU_SUBTYPE_SH7780 | 464 | config CPU_SUBTYPE_SH7780 |
| 465 | bool "Support SH7780 processor" | 465 | bool "Support SH7780 processor" |
| 466 | select CPU_SH4A | 466 | select CPU_SH4A |
| 467 | 467 | ||
| 468 | config CPU_SUBTYPE_SH7785 | 468 | config CPU_SUBTYPE_SH7785 |
| 469 | bool "Support SH7785 processor" | 469 | bool "Support SH7785 processor" |
| 470 | select CPU_SH4A | 470 | select CPU_SH4A |
| 471 | select CPU_SHX2 | 471 | select CPU_SHX2 |
| 472 | select ARCH_SPARSEMEM_ENABLE | 472 | select ARCH_SPARSEMEM_ENABLE |
| 473 | select SYS_SUPPORTS_NUMA | 473 | select SYS_SUPPORTS_NUMA |
| 474 | select ARCH_WANT_OPTIONAL_GPIOLIB | 474 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 475 | select PINCTRL | 475 | select PINCTRL |
| 476 | 476 | ||
| 477 | config CPU_SUBTYPE_SH7786 | 477 | config CPU_SUBTYPE_SH7786 |
| 478 | bool "Support SH7786 processor" | 478 | bool "Support SH7786 processor" |
| 479 | select CPU_SH4A | 479 | select CPU_SH4A |
| 480 | select CPU_SHX3 | 480 | select CPU_SHX3 |
| 481 | select CPU_HAS_PTEAEX | 481 | select CPU_HAS_PTEAEX |
| 482 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP | 482 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
| 483 | select ARCH_WANT_OPTIONAL_GPIOLIB | 483 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 484 | select USB_OHCI_SH if USB_OHCI_HCD | 484 | select USB_OHCI_SH if USB_OHCI_HCD |
| 485 | select USB_EHCI_SH if USB_EHCI_HCD | 485 | select USB_EHCI_SH if USB_EHCI_HCD |
| 486 | select PINCTRL | 486 | select PINCTRL |
| 487 | 487 | ||
| 488 | config CPU_SUBTYPE_SHX3 | 488 | config CPU_SUBTYPE_SHX3 |
| 489 | bool "Support SH-X3 processor" | 489 | bool "Support SH-X3 processor" |
| 490 | select CPU_SH4A | 490 | select CPU_SH4A |
| 491 | select CPU_SHX3 | 491 | select CPU_SHX3 |
| 492 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP | 492 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
| 493 | select ARCH_REQUIRE_GPIOLIB | 493 | select ARCH_REQUIRE_GPIOLIB |
| 494 | select PINCTRL | 494 | select PINCTRL |
| 495 | 495 | ||
| 496 | # SH4AL-DSP Processor Support | 496 | # SH4AL-DSP Processor Support |
| 497 | 497 | ||
| 498 | config CPU_SUBTYPE_SH7343 | 498 | config CPU_SUBTYPE_SH7343 |
| 499 | bool "Support SH7343 processor" | 499 | bool "Support SH7343 processor" |
| 500 | select CPU_SH4AL_DSP | 500 | select CPU_SH4AL_DSP |
| 501 | select ARCH_SHMOBILE | 501 | select ARCH_SHMOBILE |
| 502 | select SYS_SUPPORTS_SH_CMT | 502 | select SYS_SUPPORTS_SH_CMT |
| 503 | 503 | ||
| 504 | config CPU_SUBTYPE_SH7722 | 504 | config CPU_SUBTYPE_SH7722 |
| 505 | bool "Support SH7722 processor" | 505 | bool "Support SH7722 processor" |
| 506 | select CPU_SH4AL_DSP | 506 | select CPU_SH4AL_DSP |
| 507 | select CPU_SHX2 | 507 | select CPU_SHX2 |
| 508 | select ARCH_SHMOBILE | 508 | select ARCH_SHMOBILE |
| 509 | select ARCH_SPARSEMEM_ENABLE | 509 | select ARCH_SPARSEMEM_ENABLE |
| 510 | select SYS_SUPPORTS_NUMA | 510 | select SYS_SUPPORTS_NUMA |
| 511 | select SYS_SUPPORTS_SH_CMT | 511 | select SYS_SUPPORTS_SH_CMT |
| 512 | select ARCH_WANT_OPTIONAL_GPIOLIB | 512 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 513 | select PINCTRL | 513 | select PINCTRL |
| 514 | 514 | ||
| 515 | config CPU_SUBTYPE_SH7366 | 515 | config CPU_SUBTYPE_SH7366 |
| 516 | bool "Support SH7366 processor" | 516 | bool "Support SH7366 processor" |
| 517 | select CPU_SH4AL_DSP | 517 | select CPU_SH4AL_DSP |
| 518 | select CPU_SHX2 | 518 | select CPU_SHX2 |
| 519 | select ARCH_SHMOBILE | 519 | select ARCH_SHMOBILE |
| 520 | select ARCH_SPARSEMEM_ENABLE | 520 | select ARCH_SPARSEMEM_ENABLE |
| 521 | select SYS_SUPPORTS_NUMA | 521 | select SYS_SUPPORTS_NUMA |
| 522 | select SYS_SUPPORTS_SH_CMT | 522 | select SYS_SUPPORTS_SH_CMT |
| 523 | 523 | ||
| 524 | endchoice | 524 | endchoice |
| 525 | 525 | ||
| 526 | endif | 526 | endif |
| 527 | 527 | ||
| 528 | if SUPERH64 | 528 | if SUPERH64 |
| 529 | 529 | ||
| 530 | choice | 530 | choice |
| 531 | prompt "Processor sub-type selection" | 531 | prompt "Processor sub-type selection" |
| 532 | 532 | ||
| 533 | # SH-5 Processor Support | 533 | # SH-5 Processor Support |
| 534 | 534 | ||
| 535 | config CPU_SUBTYPE_SH5_101 | 535 | config CPU_SUBTYPE_SH5_101 |
| 536 | bool "Support SH5-101 processor" | 536 | bool "Support SH5-101 processor" |
| 537 | select CPU_SH5 | 537 | select CPU_SH5 |
| 538 | 538 | ||
| 539 | config CPU_SUBTYPE_SH5_103 | 539 | config CPU_SUBTYPE_SH5_103 |
| 540 | bool "Support SH5-103 processor" | 540 | bool "Support SH5-103 processor" |
| 541 | select CPU_SH5 | 541 | select CPU_SH5 |
| 542 | 542 | ||
| 543 | endchoice | 543 | endchoice |
| 544 | 544 | ||
| 545 | endif | 545 | endif |
| 546 | 546 | ||
| 547 | source "arch/sh/mm/Kconfig" | 547 | source "arch/sh/mm/Kconfig" |
| 548 | 548 | ||
| 549 | source "arch/sh/Kconfig.cpu" | 549 | source "arch/sh/Kconfig.cpu" |
| 550 | 550 | ||
| 551 | source "arch/sh/boards/Kconfig" | 551 | source "arch/sh/boards/Kconfig" |
| 552 | 552 | ||
| 553 | menu "Timer and clock configuration" | 553 | menu "Timer and clock configuration" |
| 554 | 554 | ||
| 555 | config SH_PCLK_FREQ | 555 | config SH_PCLK_FREQ |
| 556 | int "Peripheral clock frequency (in Hz)" | 556 | int "Peripheral clock frequency (in Hz)" |
| 557 | depends on SH_CLK_CPG_LEGACY | 557 | depends on SH_CLK_CPG_LEGACY |
| 558 | default "31250000" if CPU_SUBTYPE_SH7619 | 558 | default "31250000" if CPU_SUBTYPE_SH7619 |
| 559 | default "33333333" if CPU_SUBTYPE_SH7770 || \ | 559 | default "33333333" if CPU_SUBTYPE_SH7770 || \ |
| 560 | CPU_SUBTYPE_SH7760 || \ | 560 | CPU_SUBTYPE_SH7760 || \ |
| 561 | CPU_SUBTYPE_SH7705 || \ | 561 | CPU_SUBTYPE_SH7705 || \ |
| 562 | CPU_SUBTYPE_SH7203 || \ | 562 | CPU_SUBTYPE_SH7203 || \ |
| 563 | CPU_SUBTYPE_SH7206 || \ | 563 | CPU_SUBTYPE_SH7206 || \ |
| 564 | CPU_SUBTYPE_SH7263 || \ | 564 | CPU_SUBTYPE_SH7263 || \ |
| 565 | CPU_SUBTYPE_MXG | 565 | CPU_SUBTYPE_MXG |
| 566 | default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R | 566 | default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R |
| 567 | default "66000000" if CPU_SUBTYPE_SH4_202 | 567 | default "66000000" if CPU_SUBTYPE_SH4_202 |
| 568 | default "50000000" | 568 | default "50000000" |
| 569 | help | 569 | help |
| 570 | This option is used to specify the peripheral clock frequency. | 570 | This option is used to specify the peripheral clock frequency. |
| 571 | This is necessary for determining the reference clock value on | 571 | This is necessary for determining the reference clock value on |
| 572 | platforms lacking an RTC. | 572 | platforms lacking an RTC. |
| 573 | 573 | ||
| 574 | config SH_CLK_CPG | 574 | config SH_CLK_CPG |
| 575 | def_bool y | 575 | def_bool y |
| 576 | 576 | ||
| 577 | config SH_CLK_CPG_LEGACY | 577 | config SH_CLK_CPG_LEGACY |
| 578 | depends on SH_CLK_CPG | 578 | depends on SH_CLK_CPG |
| 579 | def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ | 579 | def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ |
| 580 | !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ | 580 | !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ |
| 581 | !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \ | 581 | !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \ |
| 582 | !CPU_SUBTYPE_SH7269 | 582 | !CPU_SUBTYPE_SH7269 |
| 583 | 583 | ||
| 584 | endmenu | 584 | endmenu |
| 585 | 585 | ||
| 586 | menu "CPU Frequency scaling" | 586 | menu "CPU Frequency scaling" |
| 587 | source "drivers/cpufreq/Kconfig" | 587 | source "drivers/cpufreq/Kconfig" |
| 588 | endmenu | 588 | endmenu |
| 589 | 589 | ||
| 590 | source "arch/sh/drivers/Kconfig" | 590 | source "arch/sh/drivers/Kconfig" |
| 591 | 591 | ||
| 592 | endmenu | 592 | endmenu |
| 593 | 593 | ||
| 594 | menu "Kernel features" | 594 | menu "Kernel features" |
| 595 | 595 | ||
| 596 | source kernel/Kconfig.hz | 596 | source kernel/Kconfig.hz |
| 597 | 597 | ||
| 598 | config KEXEC | 598 | config KEXEC |
| 599 | bool "kexec system call (EXPERIMENTAL)" | 599 | bool "kexec system call (EXPERIMENTAL)" |
| 600 | depends on SUPERH32 && MMU | 600 | depends on SUPERH32 && MMU |
| 601 | help | 601 | help |
| 602 | kexec is a system call that implements the ability to shutdown your | 602 | kexec is a system call that implements the ability to shutdown your |
| 603 | current kernel, and to start another kernel. It is like a reboot | 603 | current kernel, and to start another kernel. It is like a reboot |
| 604 | but it is independent of the system firmware. And like a reboot | 604 | but it is independent of the system firmware. And like a reboot |
| 605 | you can start any kernel with it, not just Linux. | 605 | you can start any kernel with it, not just Linux. |
| 606 | 606 | ||
| 607 | The name comes from the similarity to the exec system call. | 607 | The name comes from the similarity to the exec system call. |
| 608 | 608 | ||
| 609 | It is an ongoing process to be certain the hardware in a machine | 609 | It is an ongoing process to be certain the hardware in a machine |
| 610 | is properly shutdown, so do not be surprised if this code does not | 610 | is properly shutdown, so do not be surprised if this code does not |
| 611 | initially work for you. As of this writing the exact hardware | 611 | initially work for you. As of this writing the exact hardware |
| 612 | interface is strongly in flux, so no good recommendation can be | 612 | interface is strongly in flux, so no good recommendation can be |
| 613 | made. | 613 | made. |
| 614 | 614 | ||
| 615 | config CRASH_DUMP | 615 | config CRASH_DUMP |
| 616 | bool "kernel crash dumps (EXPERIMENTAL)" | 616 | bool "kernel crash dumps (EXPERIMENTAL)" |
| 617 | depends on SUPERH32 && BROKEN_ON_SMP | 617 | depends on SUPERH32 && BROKEN_ON_SMP |
| 618 | help | 618 | help |
| 619 | Generate crash dump after being started by kexec. | 619 | Generate crash dump after being started by kexec. |
| 620 | This should be normally only set in special crash dump kernels | 620 | This should be normally only set in special crash dump kernels |
| 621 | which are loaded in the main kernel with kexec-tools into | 621 | which are loaded in the main kernel with kexec-tools into |
| 622 | a specially reserved region and then later executed after | 622 | a specially reserved region and then later executed after |
| 623 | a crash by kdump/kexec. The crash dump kernel must be compiled | 623 | a crash by kdump/kexec. The crash dump kernel must be compiled |
| 624 | to a memory address not used by the main kernel using | 624 | to a memory address not used by the main kernel using |
| 625 | PHYSICAL_START. | 625 | PHYSICAL_START. |
| 626 | 626 | ||
| 627 | For more details see Documentation/kdump/kdump.txt | 627 | For more details see Documentation/kdump/kdump.txt |
| 628 | 628 | ||
| 629 | config KEXEC_JUMP | 629 | config KEXEC_JUMP |
| 630 | bool "kexec jump (EXPERIMENTAL)" | 630 | bool "kexec jump (EXPERIMENTAL)" |
| 631 | depends on SUPERH32 && KEXEC && HIBERNATION | 631 | depends on SUPERH32 && KEXEC && HIBERNATION |
| 632 | help | 632 | help |
| 633 | Jump between original kernel and kexeced kernel and invoke | 633 | Jump between original kernel and kexeced kernel and invoke |
| 634 | code via KEXEC | 634 | code via KEXEC |
| 635 | 635 | ||
| 636 | config PHYSICAL_START | 636 | config PHYSICAL_START |
| 637 | hex "Physical address where the kernel is loaded" if (EXPERT || CRASH_DUMP) | 637 | hex "Physical address where the kernel is loaded" if (EXPERT || CRASH_DUMP) |
| 638 | default MEMORY_START | 638 | default MEMORY_START |
| 639 | ---help--- | 639 | ---help--- |
| 640 | This gives the physical address where the kernel is loaded | 640 | This gives the physical address where the kernel is loaded |
| 641 | and is ordinarily the same as MEMORY_START. | 641 | and is ordinarily the same as MEMORY_START. |
| 642 | 642 | ||
| 643 | Different values are primarily used in the case of kexec on panic | 643 | Different values are primarily used in the case of kexec on panic |
| 644 | where the fail safe kernel needs to run at a different address | 644 | where the fail safe kernel needs to run at a different address |
| 645 | than the panic-ed kernel. | 645 | than the panic-ed kernel. |
| 646 | 646 | ||
| 647 | config SECCOMP | 647 | config SECCOMP |
| 648 | bool "Enable seccomp to safely compute untrusted bytecode" | 648 | bool "Enable seccomp to safely compute untrusted bytecode" |
| 649 | depends on PROC_FS | 649 | depends on PROC_FS |
| 650 | help | 650 | help |
| 651 | This kernel feature is useful for number crunching applications | 651 | This kernel feature is useful for number crunching applications |
| 652 | that may need to compute untrusted bytecode during their | 652 | that may need to compute untrusted bytecode during their |
| 653 | execution. By using pipes or other transports made available to | 653 | execution. By using pipes or other transports made available to |
| 654 | the process as file descriptors supporting the read/write | 654 | the process as file descriptors supporting the read/write |
| 655 | syscalls, it's possible to isolate those applications in | 655 | syscalls, it's possible to isolate those applications in |
| 656 | their own address space using seccomp. Once seccomp is | 656 | their own address space using seccomp. Once seccomp is |
| 657 | enabled via prctl, it cannot be disabled and the task is only | 657 | enabled via prctl, it cannot be disabled and the task is only |
| 658 | allowed to execute a few safe syscalls defined by each seccomp | 658 | allowed to execute a few safe syscalls defined by each seccomp |
| 659 | mode. | 659 | mode. |
| 660 | 660 | ||
| 661 | If unsure, say N. | 661 | If unsure, say N. |
| 662 | 662 | ||
| 663 | config SMP | 663 | config SMP |
| 664 | bool "Symmetric multi-processing support" | 664 | bool "Symmetric multi-processing support" |
| 665 | depends on SYS_SUPPORTS_SMP | 665 | depends on SYS_SUPPORTS_SMP |
| 666 | ---help--- | 666 | ---help--- |
| 667 | This enables support for systems with more than one CPU. If you have | 667 | This enables support for systems with more than one CPU. If you have |
| 668 | a system with only one CPU, say N. If you have a system with more | 668 | a system with only one CPU, say N. If you have a system with more |
| 669 | than one CPU, say Y. | 669 | than one CPU, say Y. |
| 670 | 670 | ||
| 671 | If you say N here, the kernel will run on uni- and multiprocessor | 671 | If you say N here, the kernel will run on uni- and multiprocessor |
| 672 | machines, but will use only one CPU of a multiprocessor machine. If | 672 | machines, but will use only one CPU of a multiprocessor machine. If |
| 673 | you say Y here, the kernel will run on many, but not all, | 673 | you say Y here, the kernel will run on many, but not all, |
| 674 | uniprocessor machines. On a uniprocessor machine, the kernel | 674 | uniprocessor machines. On a uniprocessor machine, the kernel |
| 675 | will run faster if you say N here. | 675 | will run faster if you say N here. |
| 676 | 676 | ||
| 677 | People using multiprocessor machines who say Y here should also say | 677 | People using multiprocessor machines who say Y here should also say |
| 678 | Y to "Enhanced Real Time Clock Support", below. | 678 | Y to "Enhanced Real Time Clock Support", below. |
| 679 | 679 | ||
| 680 | See also <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO | 680 | See also <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO |
| 681 | available at <http://www.tldp.org/docs.html#howto>. | 681 | available at <http://www.tldp.org/docs.html#howto>. |
| 682 | 682 | ||
| 683 | If you don't know what to do here, say N. | 683 | If you don't know what to do here, say N. |
| 684 | 684 | ||
| 685 | config NR_CPUS | 685 | config NR_CPUS |
| 686 | int "Maximum number of CPUs (2-32)" | 686 | int "Maximum number of CPUs (2-32)" |
| 687 | range 2 32 | 687 | range 2 32 |
| 688 | depends on SMP | 688 | depends on SMP |
| 689 | default "4" if CPU_SUBTYPE_SHX3 | 689 | default "4" if CPU_SUBTYPE_SHX3 |
| 690 | default "2" | 690 | default "2" |
| 691 | help | 691 | help |
| 692 | This allows you to specify the maximum number of CPUs which this | 692 | This allows you to specify the maximum number of CPUs which this |
| 693 | kernel will support. The maximum supported value is 32 and the | 693 | kernel will support. The maximum supported value is 32 and the |
| 694 | minimum value which makes sense is 2. | 694 | minimum value which makes sense is 2. |
| 695 | 695 | ||
| 696 | This is purely to save memory - each supported CPU adds | 696 | This is purely to save memory - each supported CPU adds |
| 697 | approximately eight kilobytes to the kernel image. | 697 | approximately eight kilobytes to the kernel image. |
| 698 | 698 | ||
| 699 | config HOTPLUG_CPU | 699 | config HOTPLUG_CPU |
| 700 | bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" | 700 | bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" |
| 701 | depends on SMP | 701 | depends on SMP |
| 702 | help | 702 | help |
| 703 | Say Y here to experiment with turning CPUs off and on. CPUs | 703 | Say Y here to experiment with turning CPUs off and on. CPUs |
| 704 | can be controlled through /sys/devices/system/cpu. | 704 | can be controlled through /sys/devices/system/cpu. |
| 705 | 705 | ||
| 706 | source "kernel/Kconfig.preempt" | 706 | source "kernel/Kconfig.preempt" |
| 707 | 707 | ||
| 708 | config GUSA | 708 | config GUSA |
| 709 | def_bool y | 709 | def_bool y |
| 710 | depends on !SMP && SUPERH32 | 710 | depends on !SMP && SUPERH32 |
| 711 | help | 711 | help |
| 712 | This enables support for gUSA (general UserSpace Atomicity). | 712 | This enables support for gUSA (general UserSpace Atomicity). |
| 713 | This is the default implementation for both UP and non-ll/sc | 713 | This is the default implementation for both UP and non-ll/sc |
| 714 | CPUs, and is used by the libc, amongst others. | 714 | CPUs, and is used by the libc, amongst others. |
| 715 | 715 | ||
| 716 | For additional information, design information can be found | 716 | For additional information, design information can be found |
| 717 | in <http://lc.linux.or.jp/lc2002/papers/niibe0919p.pdf>. | 717 | in <http://lc.linux.or.jp/lc2002/papers/niibe0919p.pdf>. |
| 718 | 718 | ||
| 719 | This should only be disabled for special cases where alternate | 719 | This should only be disabled for special cases where alternate |
| 720 | atomicity implementations exist. | 720 | atomicity implementations exist. |
| 721 | 721 | ||
| 722 | config GUSA_RB | 722 | config GUSA_RB |
| 723 | bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)" | 723 | bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)" |
| 724 | depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A) | 724 | depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A) |
| 725 | help | 725 | help |
| 726 | Enabling this option will allow the kernel to implement some | 726 | Enabling this option will allow the kernel to implement some |
| 727 | atomic operations using a software implementation of load-locked/ | 727 | atomic operations using a software implementation of load-locked/ |
| 728 | store-conditional (LLSC). On machines which do not have hardware | 728 | store-conditional (LLSC). On machines which do not have hardware |
| 729 | LLSC, this should be more efficient than the other alternative of | 729 | LLSC, this should be more efficient than the other alternative of |
| 730 | disabling interrupts around the atomic sequence. | 730 | disabling interrupts around the atomic sequence. |
| 731 | 731 | ||
| 732 | config HW_PERF_EVENTS | 732 | config HW_PERF_EVENTS |
| 733 | bool "Enable hardware performance counter support for perf events" | 733 | bool "Enable hardware performance counter support for perf events" |
| 734 | depends on PERF_EVENTS && CPU_HAS_PMU | 734 | depends on PERF_EVENTS && CPU_HAS_PMU |
| 735 | default y | 735 | default y |
| 736 | help | 736 | help |
| 737 | Enable hardware performance counter support for perf events. If | 737 | Enable hardware performance counter support for perf events. If |
| 738 | disabled, perf events will use software events only. | 738 | disabled, perf events will use software events only. |
| 739 | 739 | ||
| 740 | source "drivers/sh/Kconfig" | 740 | source "drivers/sh/Kconfig" |
| 741 | 741 | ||
| 742 | endmenu | 742 | endmenu |
| 743 | 743 | ||
| 744 | menu "Boot options" | 744 | menu "Boot options" |
| 745 | 745 | ||
| 746 | config ZERO_PAGE_OFFSET | 746 | config ZERO_PAGE_OFFSET |
| 747 | hex | 747 | hex |
| 748 | default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ | 748 | default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ |
| 749 | SH_7751_SOLUTION_ENGINE | 749 | SH_7751_SOLUTION_ENGINE |
| 750 | default "0x00004000" if PAGE_SIZE_16KB || SH_SH03 | 750 | default "0x00004000" if PAGE_SIZE_16KB || SH_SH03 |
| 751 | default "0x00002000" if PAGE_SIZE_8KB | 751 | default "0x00002000" if PAGE_SIZE_8KB |
| 752 | default "0x00001000" | 752 | default "0x00001000" |
| 753 | help | 753 | help |
| 754 | This sets the default offset of zero page. | 754 | This sets the default offset of zero page. |
| 755 | 755 | ||
| 756 | config BOOT_LINK_OFFSET | 756 | config BOOT_LINK_OFFSET |
| 757 | hex | 757 | hex |
| 758 | default "0x00210000" if SH_SHMIN | 758 | default "0x00210000" if SH_SHMIN |
| 759 | default "0x00400000" if SH_CAYMAN | 759 | default "0x00400000" if SH_CAYMAN |
| 760 | default "0x00810000" if SH_7780_SOLUTION_ENGINE | 760 | default "0x00810000" if SH_7780_SOLUTION_ENGINE |
| 761 | default "0x009e0000" if SH_TITAN | 761 | default "0x009e0000" if SH_TITAN |
| 762 | default "0x01800000" if SH_SDK7780 | 762 | default "0x01800000" if SH_SDK7780 |
| 763 | default "0x02000000" if SH_EDOSK7760 | 763 | default "0x02000000" if SH_EDOSK7760 |
| 764 | default "0x00800000" | 764 | default "0x00800000" |
| 765 | help | 765 | help |
| 766 | This option allows you to set the link address offset of the zImage. | 766 | This option allows you to set the link address offset of the zImage. |
| 767 | This can be useful if you are on a board which has a small amount of | 767 | This can be useful if you are on a board which has a small amount of |
| 768 | memory. | 768 | memory. |
| 769 | 769 | ||
| 770 | config ENTRY_OFFSET | 770 | config ENTRY_OFFSET |
| 771 | hex | 771 | hex |
| 772 | default "0x00001000" if PAGE_SIZE_4KB | 772 | default "0x00001000" if PAGE_SIZE_4KB |
| 773 | default "0x00002000" if PAGE_SIZE_8KB | 773 | default "0x00002000" if PAGE_SIZE_8KB |
| 774 | default "0x00004000" if PAGE_SIZE_16KB | 774 | default "0x00004000" if PAGE_SIZE_16KB |
| 775 | default "0x00010000" if PAGE_SIZE_64KB | 775 | default "0x00010000" if PAGE_SIZE_64KB |
| 776 | default "0x00000000" | 776 | default "0x00000000" |
| 777 | 777 | ||
| 778 | config ROMIMAGE_MMCIF | 778 | config ROMIMAGE_MMCIF |
| 779 | bool "Include MMCIF loader in romImage (EXPERIMENTAL)" | 779 | bool "Include MMCIF loader in romImage (EXPERIMENTAL)" |
| 780 | depends on CPU_SUBTYPE_SH7724 | 780 | depends on CPU_SUBTYPE_SH7724 |
| 781 | help | 781 | help |
| 782 | Say Y here to include experimental MMCIF loading code in | 782 | Say Y here to include experimental MMCIF loading code in |
| 783 | romImage. With this enabled it is possible to write the romImage | 783 | romImage. With this enabled it is possible to write the romImage |
| 784 | kernel image to an MMC card and boot the kernel straight from | 784 | kernel image to an MMC card and boot the kernel straight from |
| 785 | the reset vector. At reset the processor Mask ROM will load the | 785 | the reset vector. At reset the processor Mask ROM will load the |
| 786 | first part of the romImage which in turn loads the rest the kernel | 786 | first part of the romImage which in turn loads the rest the kernel |
| 787 | image to RAM using the MMCIF hardware block. | 787 | image to RAM using the MMCIF hardware block. |
| 788 | 788 | ||
| 789 | choice | 789 | choice |
| 790 | prompt "Kernel command line" | 790 | prompt "Kernel command line" |
| 791 | optional | 791 | optional |
| 792 | default CMDLINE_OVERWRITE | 792 | default CMDLINE_OVERWRITE |
| 793 | help | 793 | help |
| 794 | Setting this option allows the kernel command line arguments | 794 | Setting this option allows the kernel command line arguments |
| 795 | to be set. | 795 | to be set. |
| 796 | 796 | ||
| 797 | config CMDLINE_OVERWRITE | 797 | config CMDLINE_OVERWRITE |
| 798 | bool "Overwrite bootloader kernel arguments" | 798 | bool "Overwrite bootloader kernel arguments" |
| 799 | help | 799 | help |
| 800 | Given string will overwrite any arguments passed in by | 800 | Given string will overwrite any arguments passed in by |
| 801 | a bootloader. | 801 | a bootloader. |
| 802 | 802 | ||
| 803 | config CMDLINE_EXTEND | 803 | config CMDLINE_EXTEND |
| 804 | bool "Extend bootloader kernel arguments" | 804 | bool "Extend bootloader kernel arguments" |
| 805 | help | 805 | help |
| 806 | Given string will be concatenated with arguments passed in | 806 | Given string will be concatenated with arguments passed in |
| 807 | by a bootloader. | 807 | by a bootloader. |
| 808 | 808 | ||
| 809 | endchoice | 809 | endchoice |
| 810 | 810 | ||
| 811 | config CMDLINE | 811 | config CMDLINE |
| 812 | string "Kernel command line arguments string" | 812 | string "Kernel command line arguments string" |
| 813 | depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND | 813 | depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND |
| 814 | default "console=ttySC1,115200" | 814 | default "console=ttySC1,115200" |
| 815 | 815 | ||
| 816 | endmenu | 816 | endmenu |
| 817 | 817 | ||
| 818 | menu "Bus options" | 818 | menu "Bus options" |
| 819 | 819 | ||
| 820 | config SUPERHYWAY | 820 | config SUPERHYWAY |
| 821 | tristate "SuperHyway Bus support" | 821 | tristate "SuperHyway Bus support" |
| 822 | depends on CPU_SUBTYPE_SH4_202 | 822 | depends on CPU_SUBTYPE_SH4_202 |
| 823 | 823 | ||
| 824 | config MAPLE | 824 | config MAPLE |
| 825 | bool "Maple Bus support" | 825 | bool "Maple Bus support" |
| 826 | depends on SH_DREAMCAST | 826 | depends on SH_DREAMCAST |
| 827 | help | 827 | help |
| 828 | The Maple Bus is SEGA's serial communication bus for peripherals | 828 | The Maple Bus is SEGA's serial communication bus for peripherals |
| 829 | on the Dreamcast. Without this bus support you won't be able to | 829 | on the Dreamcast. Without this bus support you won't be able to |
| 830 | get your Dreamcast keyboard etc to work, so most users | 830 | get your Dreamcast keyboard etc to work, so most users |
| 831 | probably want to say 'Y' here, unless you are only using the | 831 | probably want to say 'Y' here, unless you are only using the |
| 832 | Dreamcast with a serial line terminal or a remote network | 832 | Dreamcast with a serial line terminal or a remote network |
| 833 | connection. | 833 | connection. |
| 834 | 834 | ||
| 835 | config PCI | 835 | config PCI |
| 836 | bool "PCI support" | 836 | bool "PCI support" |
| 837 | depends on SYS_SUPPORTS_PCI | 837 | depends on SYS_SUPPORTS_PCI |
| 838 | select PCI_DOMAINS | 838 | select PCI_DOMAINS |
| 839 | select GENERIC_PCI_IOMAP | 839 | select GENERIC_PCI_IOMAP |
| 840 | select NO_GENERIC_PCI_IOPORT_MAP | 840 | select NO_GENERIC_PCI_IOPORT_MAP |
| 841 | help | 841 | help |
| 842 | Find out whether you have a PCI motherboard. PCI is the name of a | 842 | Find out whether you have a PCI motherboard. PCI is the name of a |
| 843 | bus system, i.e. the way the CPU talks to the other stuff inside | 843 | bus system, i.e. the way the CPU talks to the other stuff inside |
| 844 | your box. If you have PCI, say Y, otherwise N. | 844 | your box. If you have PCI, say Y, otherwise N. |
| 845 | 845 | ||
| 846 | config PCI_DOMAINS | 846 | config PCI_DOMAINS |
| 847 | bool | 847 | bool |
| 848 | 848 | ||
| 849 | source "drivers/pci/pcie/Kconfig" | 849 | source "drivers/pci/pcie/Kconfig" |
| 850 | 850 | ||
| 851 | source "drivers/pci/Kconfig" | 851 | source "drivers/pci/Kconfig" |
| 852 | 852 | ||
| 853 | source "drivers/pcmcia/Kconfig" | 853 | source "drivers/pcmcia/Kconfig" |
| 854 | 854 | ||
| 855 | source "drivers/pci/hotplug/Kconfig" | 855 | source "drivers/pci/hotplug/Kconfig" |
| 856 | 856 | ||
| 857 | endmenu | 857 | endmenu |
| 858 | 858 | ||
| 859 | menu "Executable file formats" | 859 | menu "Executable file formats" |
| 860 | 860 | ||
| 861 | source "fs/Kconfig.binfmt" | 861 | source "fs/Kconfig.binfmt" |
| 862 | 862 | ||
| 863 | endmenu | 863 | endmenu |
| 864 | 864 | ||
| 865 | menu "Power management options (EXPERIMENTAL)" | 865 | menu "Power management options (EXPERIMENTAL)" |
| 866 | 866 | ||
| 867 | source "kernel/power/Kconfig" | 867 | source "kernel/power/Kconfig" |
| 868 | 868 | ||
| 869 | source "drivers/cpuidle/Kconfig" | 869 | source "drivers/cpuidle/Kconfig" |
| 870 | 870 | ||
| 871 | endmenu | 871 | endmenu |
| 872 | 872 | ||
| 873 | source "net/Kconfig" | 873 | source "net/Kconfig" |
| 874 | 874 | ||
| 875 | source "drivers/Kconfig" | 875 | source "drivers/Kconfig" |
| 876 | 876 | ||
| 877 | source "fs/Kconfig" | 877 | source "fs/Kconfig" |
| 878 | 878 | ||
| 879 | source "arch/sh/Kconfig.debug" | 879 | source "arch/sh/Kconfig.debug" |
| 880 | 880 | ||
| 881 | source "security/Kconfig" | 881 | source "security/Kconfig" |
| 882 | 882 | ||
| 883 | source "crypto/Kconfig" | 883 | source "crypto/Kconfig" |
| 884 | 884 | ||
| 885 | source "lib/Kconfig" | 885 | source "lib/Kconfig" |
| 886 | 886 |
arch/sh/configs/apsh4ad0a_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_POSIX_MQUEUE=y | 3 | CONFIG_POSIX_MQUEUE=y |
| 4 | CONFIG_BSD_PROCESS_ACCT=y | 4 | CONFIG_BSD_PROCESS_ACCT=y |
| 5 | CONFIG_RCU_TRACE=y | 5 | CONFIG_RCU_TRACE=y |
| 6 | CONFIG_IKCONFIG=y | 6 | CONFIG_IKCONFIG=y |
| 7 | CONFIG_IKCONFIG_PROC=y | 7 | CONFIG_IKCONFIG_PROC=y |
| 8 | CONFIG_LOG_BUF_SHIFT=14 | 8 | CONFIG_LOG_BUF_SHIFT=14 |
| 9 | CONFIG_CGROUPS=y | 9 | CONFIG_CGROUPS=y |
| 10 | CONFIG_CGROUP_FREEZER=y | 10 | CONFIG_CGROUP_FREEZER=y |
| 11 | CONFIG_CGROUP_DEVICE=y | 11 | CONFIG_CGROUP_DEVICE=y |
| 12 | CONFIG_CGROUP_CPUACCT=y | 12 | CONFIG_CGROUP_CPUACCT=y |
| 13 | CONFIG_RESOURCE_COUNTERS=y | 13 | CONFIG_RESOURCE_COUNTERS=y |
| 14 | CONFIG_CGROUP_MEMCG=y | 14 | CONFIG_CGROUP_MEMCG=y |
| 15 | CONFIG_BLK_CGROUP=y | 15 | CONFIG_BLK_CGROUP=y |
| 16 | CONFIG_NAMESPACES=y | 16 | CONFIG_NAMESPACES=y |
| 17 | CONFIG_BLK_DEV_INITRD=y | 17 | CONFIG_BLK_DEV_INITRD=y |
| 18 | CONFIG_KALLSYMS_ALL=y | 18 | CONFIG_KALLSYMS_ALL=y |
| 19 | # CONFIG_COMPAT_BRK is not set | 19 | # CONFIG_COMPAT_BRK is not set |
| 20 | CONFIG_SLAB=y | 20 | CONFIG_SLAB=y |
| 21 | CONFIG_PROFILING=y | 21 | CONFIG_PROFILING=y |
| 22 | CONFIG_MODULES=y | 22 | CONFIG_MODULES=y |
| 23 | CONFIG_MODULE_UNLOAD=y | 23 | CONFIG_MODULE_UNLOAD=y |
| 24 | # CONFIG_LBDAF is not set | 24 | # CONFIG_LBDAF is not set |
| 25 | # CONFIG_BLK_DEV_BSG is not set | 25 | # CONFIG_BLK_DEV_BSG is not set |
| 26 | CONFIG_CFQ_GROUP_IOSCHED=y | 26 | CONFIG_CFQ_GROUP_IOSCHED=y |
| 27 | CONFIG_CPU_SUBTYPE_SH7786=y | 27 | CONFIG_CPU_SUBTYPE_SH7786=y |
| 28 | CONFIG_MEMORY_SIZE=0x10000000 | 28 | CONFIG_MEMORY_SIZE=0x10000000 |
| 29 | CONFIG_HUGETLB_PAGE_SIZE_1MB=y | 29 | CONFIG_HUGETLB_PAGE_SIZE_1MB=y |
| 30 | CONFIG_MEMORY_HOTPLUG=y | 30 | CONFIG_MEMORY_HOTPLUG=y |
| 31 | CONFIG_MEMORY_HOTREMOVE=y | 31 | CONFIG_MEMORY_HOTREMOVE=y |
| 32 | CONFIG_KSM=y | 32 | CONFIG_KSM=y |
| 33 | CONFIG_SH_STORE_QUEUES=y | 33 | CONFIG_SH_STORE_QUEUES=y |
| 34 | CONFIG_SH_APSH4AD0A=y | 34 | CONFIG_SH_APSH4AD0A=y |
| 35 | CONFIG_NO_HZ=y | 35 | CONFIG_NO_HZ=y |
| 36 | CONFIG_HIGH_RES_TIMERS=y | 36 | CONFIG_HIGH_RES_TIMERS=y |
| 37 | CONFIG_CPU_FREQ=y | 37 | CONFIG_CPU_FREQ=y |
| 38 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | 38 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m |
| 39 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | 39 | CONFIG_CPU_FREQ_GOV_USERSPACE=m |
| 40 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m | 40 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m |
| 41 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m | 41 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m |
| 42 | CONFIG_SH_CPU_FREQ=y | 42 | CONFIG_SH_CPU_FREQ=y |
| 43 | CONFIG_KEXEC=y | 43 | CONFIG_KEXEC=y |
| 44 | CONFIG_SECCOMP=y | 44 | CONFIG_SECCOMP=y |
| 45 | CONFIG_PREEMPT=y | 45 | CONFIG_PREEMPT=y |
| 46 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 46 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
| 47 | CONFIG_BINFMT_MISC=y | 47 | CONFIG_BINFMT_MISC=y |
| 48 | CONFIG_PM=y | 48 | CONFIG_PM=y |
| 49 | CONFIG_PM_DEBUG=y | 49 | CONFIG_PM_DEBUG=y |
| 50 | CONFIG_PM_RUNTIME=y | 50 | CONFIG_PM=y |
| 51 | CONFIG_CPU_IDLE=y | 51 | CONFIG_CPU_IDLE=y |
| 52 | CONFIG_NET=y | 52 | CONFIG_NET=y |
| 53 | CONFIG_PACKET=y | 53 | CONFIG_PACKET=y |
| 54 | CONFIG_UNIX=y | 54 | CONFIG_UNIX=y |
| 55 | CONFIG_NET_KEY=y | 55 | CONFIG_NET_KEY=y |
| 56 | CONFIG_INET=y | 56 | CONFIG_INET=y |
| 57 | # CONFIG_INET_LRO is not set | 57 | # CONFIG_INET_LRO is not set |
| 58 | # CONFIG_IPV6 is not set | 58 | # CONFIG_IPV6 is not set |
| 59 | # CONFIG_WIRELESS is not set | 59 | # CONFIG_WIRELESS is not set |
| 60 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 60 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 61 | # CONFIG_FW_LOADER is not set | 61 | # CONFIG_FW_LOADER is not set |
| 62 | CONFIG_MTD=y | 62 | CONFIG_MTD=y |
| 63 | CONFIG_MTD_CFI=y | 63 | CONFIG_MTD_CFI=y |
| 64 | CONFIG_BLK_DEV_RAM=y | 64 | CONFIG_BLK_DEV_RAM=y |
| 65 | CONFIG_BLK_DEV_RAM_SIZE=16384 | 65 | CONFIG_BLK_DEV_RAM_SIZE=16384 |
| 66 | CONFIG_SCSI=y | 66 | CONFIG_SCSI=y |
| 67 | CONFIG_BLK_DEV_SD=y | 67 | CONFIG_BLK_DEV_SD=y |
| 68 | CONFIG_SCSI_MULTI_LUN=y | 68 | CONFIG_SCSI_MULTI_LUN=y |
| 69 | # CONFIG_SCSI_LOWLEVEL is not set | 69 | # CONFIG_SCSI_LOWLEVEL is not set |
| 70 | CONFIG_NETDEVICES=y | 70 | CONFIG_NETDEVICES=y |
| 71 | CONFIG_MDIO_BITBANG=y | 71 | CONFIG_MDIO_BITBANG=y |
| 72 | CONFIG_NET_ETHERNET=y | 72 | CONFIG_NET_ETHERNET=y |
| 73 | CONFIG_SMSC911X=y | 73 | CONFIG_SMSC911X=y |
| 74 | # CONFIG_NETDEV_1000 is not set | 74 | # CONFIG_NETDEV_1000 is not set |
| 75 | # CONFIG_NETDEV_10000 is not set | 75 | # CONFIG_NETDEV_10000 is not set |
| 76 | # CONFIG_WLAN is not set | 76 | # CONFIG_WLAN is not set |
| 77 | CONFIG_INPUT_EVDEV=y | 77 | CONFIG_INPUT_EVDEV=y |
| 78 | # CONFIG_INPUT_KEYBOARD is not set | 78 | # CONFIG_INPUT_KEYBOARD is not set |
| 79 | # CONFIG_INPUT_MOUSE is not set | 79 | # CONFIG_INPUT_MOUSE is not set |
| 80 | # CONFIG_SERIO is not set | 80 | # CONFIG_SERIO is not set |
| 81 | CONFIG_SERIAL_SH_SCI=y | 81 | CONFIG_SERIAL_SH_SCI=y |
| 82 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 | 82 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 |
| 83 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 83 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 84 | # CONFIG_LEGACY_PTYS is not set | 84 | # CONFIG_LEGACY_PTYS is not set |
| 85 | # CONFIG_HW_RANDOM is not set | 85 | # CONFIG_HW_RANDOM is not set |
| 86 | # CONFIG_HWMON is not set | 86 | # CONFIG_HWMON is not set |
| 87 | CONFIG_VIDEO_OUTPUT_CONTROL=y | 87 | CONFIG_VIDEO_OUTPUT_CONTROL=y |
| 88 | CONFIG_FB=y | 88 | CONFIG_FB=y |
| 89 | CONFIG_FB_SH7785FB=y | 89 | CONFIG_FB_SH7785FB=y |
| 90 | CONFIG_FRAMEBUFFER_CONSOLE=y | 90 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 91 | CONFIG_FONTS=y | 91 | CONFIG_FONTS=y |
| 92 | CONFIG_FONT_8x8=y | 92 | CONFIG_FONT_8x8=y |
| 93 | CONFIG_FONT_8x16=y | 93 | CONFIG_FONT_8x16=y |
| 94 | CONFIG_LOGO=y | 94 | CONFIG_LOGO=y |
| 95 | CONFIG_USB=y | 95 | CONFIG_USB=y |
| 96 | CONFIG_USB_MON=y | 96 | CONFIG_USB_MON=y |
| 97 | CONFIG_USB_OHCI_HCD=y | 97 | CONFIG_USB_OHCI_HCD=y |
| 98 | CONFIG_USB_STORAGE=y | 98 | CONFIG_USB_STORAGE=y |
| 99 | CONFIG_EXT2_FS=y | 99 | CONFIG_EXT2_FS=y |
| 100 | CONFIG_EXT3_FS=y | 100 | CONFIG_EXT3_FS=y |
| 101 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 101 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 102 | CONFIG_MSDOS_FS=y | 102 | CONFIG_MSDOS_FS=y |
| 103 | CONFIG_VFAT_FS=y | 103 | CONFIG_VFAT_FS=y |
| 104 | CONFIG_NTFS_FS=y | 104 | CONFIG_NTFS_FS=y |
| 105 | CONFIG_NTFS_RW=y | 105 | CONFIG_NTFS_RW=y |
| 106 | CONFIG_PROC_KCORE=y | 106 | CONFIG_PROC_KCORE=y |
| 107 | CONFIG_TMPFS=y | 107 | CONFIG_TMPFS=y |
| 108 | CONFIG_HUGETLBFS=y | 108 | CONFIG_HUGETLBFS=y |
| 109 | CONFIG_JFFS2_FS=y | 109 | CONFIG_JFFS2_FS=y |
| 110 | CONFIG_CRAMFS=y | 110 | CONFIG_CRAMFS=y |
| 111 | CONFIG_NFS_FS=y | 111 | CONFIG_NFS_FS=y |
| 112 | CONFIG_NFS_V3=y | 112 | CONFIG_NFS_V3=y |
| 113 | CONFIG_NFS_V4=y | 113 | CONFIG_NFS_V4=y |
| 114 | CONFIG_CIFS=y | 114 | CONFIG_CIFS=y |
| 115 | CONFIG_NLS_DEFAULT="utf8" | 115 | CONFIG_NLS_DEFAULT="utf8" |
| 116 | CONFIG_NLS_CODEPAGE_437=y | 116 | CONFIG_NLS_CODEPAGE_437=y |
| 117 | CONFIG_NLS_CODEPAGE_932=y | 117 | CONFIG_NLS_CODEPAGE_932=y |
| 118 | CONFIG_NLS_ASCII=y | 118 | CONFIG_NLS_ASCII=y |
| 119 | CONFIG_NLS_ISO8859_1=y | 119 | CONFIG_NLS_ISO8859_1=y |
| 120 | CONFIG_NLS_UTF8=y | 120 | CONFIG_NLS_UTF8=y |
| 121 | # CONFIG_ENABLE_MUST_CHECK is not set | 121 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 122 | CONFIG_MAGIC_SYSRQ=y | 122 | CONFIG_MAGIC_SYSRQ=y |
| 123 | CONFIG_DEBUG_KERNEL=y | 123 | CONFIG_DEBUG_KERNEL=y |
| 124 | CONFIG_DEBUG_SHIRQ=y | 124 | CONFIG_DEBUG_SHIRQ=y |
| 125 | CONFIG_DETECT_HUNG_TASK=y | 125 | CONFIG_DETECT_HUNG_TASK=y |
| 126 | CONFIG_DEBUG_INFO=y | 126 | CONFIG_DEBUG_INFO=y |
| 127 | CONFIG_DEBUG_VM=y | 127 | CONFIG_DEBUG_VM=y |
| 128 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 128 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 129 | CONFIG_DWARF_UNWINDER=y | 129 | CONFIG_DWARF_UNWINDER=y |
| 130 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 130 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 131 | 131 |
arch/sh/configs/sdk7786_defconfig
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | CONFIG_KERNEL_LZO=y | 2 | CONFIG_KERNEL_LZO=y |
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_POSIX_MQUEUE=y | 4 | CONFIG_POSIX_MQUEUE=y |
| 5 | CONFIG_BSD_PROCESS_ACCT=y | 5 | CONFIG_BSD_PROCESS_ACCT=y |
| 6 | CONFIG_BSD_PROCESS_ACCT_V3=y | 6 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 7 | CONFIG_AUDIT=y | 7 | CONFIG_AUDIT=y |
| 8 | CONFIG_AUDITSYSCALL=y | 8 | CONFIG_AUDITSYSCALL=y |
| 9 | CONFIG_TREE_PREEMPT_RCU=y | 9 | CONFIG_TREE_PREEMPT_RCU=y |
| 10 | CONFIG_RCU_TRACE=y | 10 | CONFIG_RCU_TRACE=y |
| 11 | CONFIG_IKCONFIG=y | 11 | CONFIG_IKCONFIG=y |
| 12 | CONFIG_IKCONFIG_PROC=y | 12 | CONFIG_IKCONFIG_PROC=y |
| 13 | CONFIG_CGROUPS=y | 13 | CONFIG_CGROUPS=y |
| 14 | CONFIG_CGROUP_DEBUG=y | 14 | CONFIG_CGROUP_DEBUG=y |
| 15 | CONFIG_CGROUP_FREEZER=y | 15 | CONFIG_CGROUP_FREEZER=y |
| 16 | CONFIG_CGROUP_DEVICE=y | 16 | CONFIG_CGROUP_DEVICE=y |
| 17 | CONFIG_CPUSETS=y | 17 | CONFIG_CPUSETS=y |
| 18 | # CONFIG_PROC_PID_CPUSET is not set | 18 | # CONFIG_PROC_PID_CPUSET is not set |
| 19 | CONFIG_CGROUP_CPUACCT=y | 19 | CONFIG_CGROUP_CPUACCT=y |
| 20 | CONFIG_RESOURCE_COUNTERS=y | 20 | CONFIG_RESOURCE_COUNTERS=y |
| 21 | CONFIG_CGROUP_MEMCG=y | 21 | CONFIG_CGROUP_MEMCG=y |
| 22 | CONFIG_CGROUP_MEMCG_SWAP=y | 22 | CONFIG_CGROUP_MEMCG_SWAP=y |
| 23 | CONFIG_CGROUP_SCHED=y | 23 | CONFIG_CGROUP_SCHED=y |
| 24 | CONFIG_RT_GROUP_SCHED=y | 24 | CONFIG_RT_GROUP_SCHED=y |
| 25 | CONFIG_BLK_CGROUP=y | 25 | CONFIG_BLK_CGROUP=y |
| 26 | CONFIG_RELAY=y | 26 | CONFIG_RELAY=y |
| 27 | CONFIG_NAMESPACES=y | 27 | CONFIG_NAMESPACES=y |
| 28 | CONFIG_UTS_NS=y | 28 | CONFIG_UTS_NS=y |
| 29 | CONFIG_IPC_NS=y | 29 | CONFIG_IPC_NS=y |
| 30 | CONFIG_USER_NS=y | 30 | CONFIG_USER_NS=y |
| 31 | CONFIG_PID_NS=y | 31 | CONFIG_PID_NS=y |
| 32 | CONFIG_NET_NS=y | 32 | CONFIG_NET_NS=y |
| 33 | CONFIG_BLK_DEV_INITRD=y | 33 | CONFIG_BLK_DEV_INITRD=y |
| 34 | CONFIG_RD_BZIP2=y | 34 | CONFIG_RD_BZIP2=y |
| 35 | CONFIG_RD_LZMA=y | 35 | CONFIG_RD_LZMA=y |
| 36 | CONFIG_RD_LZO=y | 36 | CONFIG_RD_LZO=y |
| 37 | # CONFIG_COMPAT_BRK is not set | 37 | # CONFIG_COMPAT_BRK is not set |
| 38 | CONFIG_SLAB=y | 38 | CONFIG_SLAB=y |
| 39 | CONFIG_PROFILING=y | 39 | CONFIG_PROFILING=y |
| 40 | CONFIG_OPROFILE=m | 40 | CONFIG_OPROFILE=m |
| 41 | CONFIG_KPROBES=y | 41 | CONFIG_KPROBES=y |
| 42 | CONFIG_MODULES=y | 42 | CONFIG_MODULES=y |
| 43 | CONFIG_MODULE_UNLOAD=y | 43 | CONFIG_MODULE_UNLOAD=y |
| 44 | CONFIG_CFQ_GROUP_IOSCHED=y | 44 | CONFIG_CFQ_GROUP_IOSCHED=y |
| 45 | CONFIG_CPU_SUBTYPE_SH7786=y | 45 | CONFIG_CPU_SUBTYPE_SH7786=y |
| 46 | CONFIG_MEMORY_START=0x40000000 | 46 | CONFIG_MEMORY_START=0x40000000 |
| 47 | CONFIG_MEMORY_SIZE=0x20000000 | 47 | CONFIG_MEMORY_SIZE=0x20000000 |
| 48 | CONFIG_PMB=y | 48 | CONFIG_PMB=y |
| 49 | CONFIG_NUMA=y | 49 | CONFIG_NUMA=y |
| 50 | CONFIG_HUGETLB_PAGE_SIZE_64MB=y | 50 | CONFIG_HUGETLB_PAGE_SIZE_64MB=y |
| 51 | CONFIG_MEMORY_HOTPLUG=y | 51 | CONFIG_MEMORY_HOTPLUG=y |
| 52 | CONFIG_MEMORY_HOTREMOVE=y | 52 | CONFIG_MEMORY_HOTREMOVE=y |
| 53 | CONFIG_KSM=y | 53 | CONFIG_KSM=y |
| 54 | CONFIG_SH_STORE_QUEUES=y | 54 | CONFIG_SH_STORE_QUEUES=y |
| 55 | CONFIG_SPECULATIVE_EXECUTION=y | 55 | CONFIG_SPECULATIVE_EXECUTION=y |
| 56 | CONFIG_SH_SDK7786=y | 56 | CONFIG_SH_SDK7786=y |
| 57 | CONFIG_NO_HZ=y | 57 | CONFIG_NO_HZ=y |
| 58 | CONFIG_HIGH_RES_TIMERS=y | 58 | CONFIG_HIGH_RES_TIMERS=y |
| 59 | CONFIG_CPU_FREQ=y | 59 | CONFIG_CPU_FREQ=y |
| 60 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | 60 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m |
| 61 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | 61 | CONFIG_CPU_FREQ_GOV_USERSPACE=m |
| 62 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m | 62 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m |
| 63 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m | 63 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m |
| 64 | CONFIG_SH_CPU_FREQ=y | 64 | CONFIG_SH_CPU_FREQ=y |
| 65 | CONFIG_SH_DMA=y | 65 | CONFIG_SH_DMA=y |
| 66 | CONFIG_HEARTBEAT=y | 66 | CONFIG_HEARTBEAT=y |
| 67 | CONFIG_HZ_1000=y | 67 | CONFIG_HZ_1000=y |
| 68 | CONFIG_KEXEC=y | 68 | CONFIG_KEXEC=y |
| 69 | CONFIG_SECCOMP=y | 69 | CONFIG_SECCOMP=y |
| 70 | CONFIG_SMP=y | 70 | CONFIG_SMP=y |
| 71 | CONFIG_HOTPLUG_CPU=y | 71 | CONFIG_HOTPLUG_CPU=y |
| 72 | CONFIG_PREEMPT=y | 72 | CONFIG_PREEMPT=y |
| 73 | CONFIG_INTC_USERIMASK=y | 73 | CONFIG_INTC_USERIMASK=y |
| 74 | CONFIG_INTC_BALANCING=y | 74 | CONFIG_INTC_BALANCING=y |
| 75 | CONFIG_CMDLINE_OVERWRITE=y | 75 | CONFIG_CMDLINE_OVERWRITE=y |
| 76 | CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200 root=/dev/sda1 nmi_debug=state,debounce rootdelay=5 pmb=iomap ignore_loglevel" | 76 | CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200 root=/dev/sda1 nmi_debug=state,debounce rootdelay=5 pmb=iomap ignore_loglevel" |
| 77 | CONFIG_PCI=y | 77 | CONFIG_PCI=y |
| 78 | CONFIG_PCIEPORTBUS=y | 78 | CONFIG_PCIEPORTBUS=y |
| 79 | CONFIG_PCIEAER_INJECT=y | 79 | CONFIG_PCIEAER_INJECT=y |
| 80 | CONFIG_PCIEASPM_DEBUG=y | 80 | CONFIG_PCIEASPM_DEBUG=y |
| 81 | CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y | 81 | CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y |
| 82 | CONFIG_BINFMT_MISC=y | 82 | CONFIG_BINFMT_MISC=y |
| 83 | CONFIG_PM=y | 83 | CONFIG_PM=y |
| 84 | CONFIG_PM_DEBUG=y | 84 | CONFIG_PM_DEBUG=y |
| 85 | CONFIG_PM_RUNTIME=y | 85 | CONFIG_PM=y |
| 86 | CONFIG_CPU_IDLE=y | 86 | CONFIG_CPU_IDLE=y |
| 87 | CONFIG_NET=y | 87 | CONFIG_NET=y |
| 88 | CONFIG_PACKET=y | 88 | CONFIG_PACKET=y |
| 89 | CONFIG_UNIX=y | 89 | CONFIG_UNIX=y |
| 90 | CONFIG_NET_KEY=y | 90 | CONFIG_NET_KEY=y |
| 91 | CONFIG_INET=y | 91 | CONFIG_INET=y |
| 92 | CONFIG_IP_PNP=y | 92 | CONFIG_IP_PNP=y |
| 93 | CONFIG_IP_PNP_DHCP=y | 93 | CONFIG_IP_PNP_DHCP=y |
| 94 | # CONFIG_INET_LRO is not set | 94 | # CONFIG_INET_LRO is not set |
| 95 | # CONFIG_IPV6 is not set | 95 | # CONFIG_IPV6 is not set |
| 96 | # CONFIG_WIRELESS is not set | 96 | # CONFIG_WIRELESS is not set |
| 97 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 97 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 98 | # CONFIG_FW_LOADER is not set | 98 | # CONFIG_FW_LOADER is not set |
| 99 | CONFIG_MTD=y | 99 | CONFIG_MTD=y |
| 100 | CONFIG_MTD_PARTITIONS=y | 100 | CONFIG_MTD_PARTITIONS=y |
| 101 | CONFIG_MTD_CMDLINE_PARTS=y | 101 | CONFIG_MTD_CMDLINE_PARTS=y |
| 102 | CONFIG_MTD_BLOCK=y | 102 | CONFIG_MTD_BLOCK=y |
| 103 | CONFIG_FTL=y | 103 | CONFIG_FTL=y |
| 104 | CONFIG_NFTL=y | 104 | CONFIG_NFTL=y |
| 105 | CONFIG_MTD_OOPS=m | 105 | CONFIG_MTD_OOPS=m |
| 106 | CONFIG_MTD_CFI=y | 106 | CONFIG_MTD_CFI=y |
| 107 | CONFIG_MTD_JEDECPROBE=y | 107 | CONFIG_MTD_JEDECPROBE=y |
| 108 | CONFIG_MTD_CFI_INTELEXT=m | 108 | CONFIG_MTD_CFI_INTELEXT=m |
| 109 | CONFIG_MTD_CFI_AMDSTD=m | 109 | CONFIG_MTD_CFI_AMDSTD=m |
| 110 | CONFIG_MTD_CFI_STAA=m | 110 | CONFIG_MTD_CFI_STAA=m |
| 111 | CONFIG_MTD_ROM=m | 111 | CONFIG_MTD_ROM=m |
| 112 | CONFIG_MTD_ABSENT=m | 112 | CONFIG_MTD_ABSENT=m |
| 113 | CONFIG_MTD_PLATRAM=y | 113 | CONFIG_MTD_PLATRAM=y |
| 114 | CONFIG_MTD_PHRAM=y | 114 | CONFIG_MTD_PHRAM=y |
| 115 | CONFIG_MTD_NAND=y | 115 | CONFIG_MTD_NAND=y |
| 116 | CONFIG_MTD_NAND_PLATFORM=y | 116 | CONFIG_MTD_NAND_PLATFORM=y |
| 117 | CONFIG_MTD_NAND_SH_FLCTL=m | 117 | CONFIG_MTD_NAND_SH_FLCTL=m |
| 118 | CONFIG_MTD_UBI=y | 118 | CONFIG_MTD_UBI=y |
| 119 | CONFIG_MTD_UBI_GLUEBI=m | 119 | CONFIG_MTD_UBI_GLUEBI=m |
| 120 | CONFIG_BLK_DEV_LOOP=y | 120 | CONFIG_BLK_DEV_LOOP=y |
| 121 | CONFIG_BLK_DEV_CRYPTOLOOP=y | 121 | CONFIG_BLK_DEV_CRYPTOLOOP=y |
| 122 | CONFIG_BLK_DEV_RAM=y | 122 | CONFIG_BLK_DEV_RAM=y |
| 123 | # CONFIG_MISC_DEVICES is not set | 123 | # CONFIG_MISC_DEVICES is not set |
| 124 | CONFIG_IDE=y | 124 | CONFIG_IDE=y |
| 125 | CONFIG_BLK_DEV_IDECD=y | 125 | CONFIG_BLK_DEV_IDECD=y |
| 126 | CONFIG_BLK_DEV_PLATFORM=y | 126 | CONFIG_BLK_DEV_PLATFORM=y |
| 127 | CONFIG_BLK_DEV_SD=y | 127 | CONFIG_BLK_DEV_SD=y |
| 128 | CONFIG_BLK_DEV_SR=y | 128 | CONFIG_BLK_DEV_SR=y |
| 129 | CONFIG_SCSI_MULTI_LUN=y | 129 | CONFIG_SCSI_MULTI_LUN=y |
| 130 | CONFIG_SCSI_CONSTANTS=y | 130 | CONFIG_SCSI_CONSTANTS=y |
| 131 | # CONFIG_SCSI_LOWLEVEL is not set | 131 | # CONFIG_SCSI_LOWLEVEL is not set |
| 132 | CONFIG_ATA=y | 132 | CONFIG_ATA=y |
| 133 | CONFIG_SATA_SIL24=y | 133 | CONFIG_SATA_SIL24=y |
| 134 | CONFIG_PATA_PLATFORM=y | 134 | CONFIG_PATA_PLATFORM=y |
| 135 | CONFIG_MD=y | 135 | CONFIG_MD=y |
| 136 | CONFIG_BLK_DEV_DM=y | 136 | CONFIG_BLK_DEV_DM=y |
| 137 | CONFIG_DM_DEBUG=y | 137 | CONFIG_DM_DEBUG=y |
| 138 | CONFIG_DM_UEVENT=y | 138 | CONFIG_DM_UEVENT=y |
| 139 | CONFIG_NETDEVICES=y | 139 | CONFIG_NETDEVICES=y |
| 140 | CONFIG_MDIO_BITBANG=y | 140 | CONFIG_MDIO_BITBANG=y |
| 141 | CONFIG_NET_ETHERNET=y | 141 | CONFIG_NET_ETHERNET=y |
| 142 | CONFIG_SMC91X=y | 142 | CONFIG_SMC91X=y |
| 143 | CONFIG_SMSC911X=y | 143 | CONFIG_SMSC911X=y |
| 144 | # CONFIG_NETDEV_1000 is not set | 144 | # CONFIG_NETDEV_1000 is not set |
| 145 | # CONFIG_NETDEV_10000 is not set | 145 | # CONFIG_NETDEV_10000 is not set |
| 146 | # CONFIG_WLAN is not set | 146 | # CONFIG_WLAN is not set |
| 147 | CONFIG_VT_HW_CONSOLE_BINDING=y | 147 | CONFIG_VT_HW_CONSOLE_BINDING=y |
| 148 | CONFIG_SERIAL_SH_SCI=y | 148 | CONFIG_SERIAL_SH_SCI=y |
| 149 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 | 149 | CONFIG_SERIAL_SH_SCI_NR_UARTS=6 |
| 150 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | 150 | CONFIG_SERIAL_SH_SCI_CONSOLE=y |
| 151 | CONFIG_SERIAL_SH_SCI_DMA=y | 151 | CONFIG_SERIAL_SH_SCI_DMA=y |
| 152 | # CONFIG_LEGACY_PTYS is not set | 152 | # CONFIG_LEGACY_PTYS is not set |
| 153 | # CONFIG_HW_RANDOM is not set | 153 | # CONFIG_HW_RANDOM is not set |
| 154 | CONFIG_I2C=y | 154 | CONFIG_I2C=y |
| 155 | # CONFIG_I2C_COMPAT is not set | 155 | # CONFIG_I2C_COMPAT is not set |
| 156 | CONFIG_I2C_CHARDEV=y | 156 | CONFIG_I2C_CHARDEV=y |
| 157 | CONFIG_SPI=y | 157 | CONFIG_SPI=y |
| 158 | # CONFIG_HWMON is not set | 158 | # CONFIG_HWMON is not set |
| 159 | CONFIG_WATCHDOG=y | 159 | CONFIG_WATCHDOG=y |
| 160 | CONFIG_SH_WDT=y | 160 | CONFIG_SH_WDT=y |
| 161 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 161 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 162 | CONFIG_USB=y | 162 | CONFIG_USB=y |
| 163 | CONFIG_USB_MON=y | 163 | CONFIG_USB_MON=y |
| 164 | CONFIG_USB_OHCI_HCD=y | 164 | CONFIG_USB_OHCI_HCD=y |
| 165 | CONFIG_USB_STORAGE=y | 165 | CONFIG_USB_STORAGE=y |
| 166 | CONFIG_USB_GADGET=y | 166 | CONFIG_USB_GADGET=y |
| 167 | CONFIG_USB_GADGET_M66592=y | 167 | CONFIG_USB_GADGET_M66592=y |
| 168 | CONFIG_RTC_CLASS=y | 168 | CONFIG_RTC_CLASS=y |
| 169 | CONFIG_RTC_DRV_MAX6900=y | 169 | CONFIG_RTC_DRV_MAX6900=y |
| 170 | CONFIG_RTC_DRV_SH=y | 170 | CONFIG_RTC_DRV_SH=y |
| 171 | CONFIG_DMADEVICES=y | 171 | CONFIG_DMADEVICES=y |
| 172 | CONFIG_SH_DMAE=y | 172 | CONFIG_SH_DMAE=y |
| 173 | CONFIG_UIO=m | 173 | CONFIG_UIO=m |
| 174 | CONFIG_UIO_PDRV=m | 174 | CONFIG_UIO_PDRV=m |
| 175 | CONFIG_UIO_PDRV_GENIRQ=m | 175 | CONFIG_UIO_PDRV_GENIRQ=m |
| 176 | CONFIG_UIO_PCI_GENERIC=m | 176 | CONFIG_UIO_PCI_GENERIC=m |
| 177 | CONFIG_STAGING=y | 177 | CONFIG_STAGING=y |
| 178 | # CONFIG_STAGING_EXCLUDE_BUILD is not set | 178 | # CONFIG_STAGING_EXCLUDE_BUILD is not set |
| 179 | CONFIG_EXT2_FS=y | 179 | CONFIG_EXT2_FS=y |
| 180 | CONFIG_EXT2_FS_XATTR=y | 180 | CONFIG_EXT2_FS_XATTR=y |
| 181 | CONFIG_EXT3_FS=y | 181 | CONFIG_EXT3_FS=y |
| 182 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 182 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
| 183 | CONFIG_EXT4_FS=y | 183 | CONFIG_EXT4_FS=y |
| 184 | CONFIG_XFS_FS=y | 184 | CONFIG_XFS_FS=y |
| 185 | CONFIG_BTRFS_FS=y | 185 | CONFIG_BTRFS_FS=y |
| 186 | CONFIG_AUTOFS4_FS=m | 186 | CONFIG_AUTOFS4_FS=m |
| 187 | CONFIG_FUSE_FS=y | 187 | CONFIG_FUSE_FS=y |
| 188 | CONFIG_CUSE=m | 188 | CONFIG_CUSE=m |
| 189 | CONFIG_FSCACHE=m | 189 | CONFIG_FSCACHE=m |
| 190 | CONFIG_CACHEFILES=m | 190 | CONFIG_CACHEFILES=m |
| 191 | CONFIG_ISO9660_FS=m | 191 | CONFIG_ISO9660_FS=m |
| 192 | CONFIG_JOLIET=y | 192 | CONFIG_JOLIET=y |
| 193 | CONFIG_ZISOFS=y | 193 | CONFIG_ZISOFS=y |
| 194 | CONFIG_UDF_FS=m | 194 | CONFIG_UDF_FS=m |
| 195 | CONFIG_PROC_KCORE=y | 195 | CONFIG_PROC_KCORE=y |
| 196 | CONFIG_TMPFS=y | 196 | CONFIG_TMPFS=y |
| 197 | CONFIG_HUGETLBFS=y | 197 | CONFIG_HUGETLBFS=y |
| 198 | CONFIG_CONFIGFS_FS=y | 198 | CONFIG_CONFIGFS_FS=y |
| 199 | CONFIG_JFFS2_FS=m | 199 | CONFIG_JFFS2_FS=m |
| 200 | CONFIG_JFFS2_FS_XATTR=y | 200 | CONFIG_JFFS2_FS_XATTR=y |
| 201 | CONFIG_UBIFS_FS=m | 201 | CONFIG_UBIFS_FS=m |
| 202 | CONFIG_LOGFS=m | 202 | CONFIG_LOGFS=m |
| 203 | CONFIG_CRAMFS=m | 203 | CONFIG_CRAMFS=m |
| 204 | CONFIG_SQUASHFS=m | 204 | CONFIG_SQUASHFS=m |
| 205 | CONFIG_ROMFS_FS=m | 205 | CONFIG_ROMFS_FS=m |
| 206 | CONFIG_NFS_FS=y | 206 | CONFIG_NFS_FS=y |
| 207 | CONFIG_NFS_V3=y | 207 | CONFIG_NFS_V3=y |
| 208 | CONFIG_NFS_V4=y | 208 | CONFIG_NFS_V4=y |
| 209 | CONFIG_ROOT_NFS=y | 209 | CONFIG_ROOT_NFS=y |
| 210 | CONFIG_NLS_CODEPAGE_437=y | 210 | CONFIG_NLS_CODEPAGE_437=y |
| 211 | CONFIG_NLS_CODEPAGE_936=m | 211 | CONFIG_NLS_CODEPAGE_936=m |
| 212 | CONFIG_NLS_CODEPAGE_950=m | 212 | CONFIG_NLS_CODEPAGE_950=m |
| 213 | CONFIG_NLS_CODEPAGE_932=y | 213 | CONFIG_NLS_CODEPAGE_932=y |
| 214 | CONFIG_NLS_CODEPAGE_949=m | 214 | CONFIG_NLS_CODEPAGE_949=m |
| 215 | CONFIG_NLS_ASCII=m | 215 | CONFIG_NLS_ASCII=m |
| 216 | CONFIG_NLS_ISO8859_1=y | 216 | CONFIG_NLS_ISO8859_1=y |
| 217 | CONFIG_NLS_ISO8859_15=m | 217 | CONFIG_NLS_ISO8859_15=m |
| 218 | CONFIG_NLS_UTF8=m | 218 | CONFIG_NLS_UTF8=m |
| 219 | CONFIG_PRINTK_TIME=y | 219 | CONFIG_PRINTK_TIME=y |
| 220 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | 220 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 221 | # CONFIG_ENABLE_MUST_CHECK is not set | 221 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 222 | CONFIG_MAGIC_SYSRQ=y | 222 | CONFIG_MAGIC_SYSRQ=y |
| 223 | CONFIG_DEBUG_KERNEL=y | 223 | CONFIG_DEBUG_KERNEL=y |
| 224 | CONFIG_DETECT_HUNG_TASK=y | 224 | CONFIG_DETECT_HUNG_TASK=y |
| 225 | CONFIG_TIMER_STATS=y | 225 | CONFIG_TIMER_STATS=y |
| 226 | CONFIG_DEBUG_MEMORY_INIT=y | 226 | CONFIG_DEBUG_MEMORY_INIT=y |
| 227 | # CONFIG_RCU_CPU_STALL_VERBOSE is not set | 227 | # CONFIG_RCU_CPU_STALL_VERBOSE is not set |
| 228 | CONFIG_LATENCYTOP=y | 228 | CONFIG_LATENCYTOP=y |
| 229 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 229 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 230 | CONFIG_FUNCTION_TRACER=y | 230 | CONFIG_FUNCTION_TRACER=y |
| 231 | # CONFIG_FUNCTION_GRAPH_TRACER is not set | 231 | # CONFIG_FUNCTION_GRAPH_TRACER is not set |
| 232 | CONFIG_DMA_API_DEBUG=y | 232 | CONFIG_DMA_API_DEBUG=y |
| 233 | CONFIG_DEBUG_STACK_USAGE=y | 233 | CONFIG_DEBUG_STACK_USAGE=y |
| 234 | CONFIG_DWARF_UNWINDER=y | 234 | CONFIG_DWARF_UNWINDER=y |
| 235 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 235 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 236 | 236 |
drivers/spi/spi-img-spfi.c
| 1 | /* | 1 | /* |
| 2 | * IMG SPFI controller driver | 2 | * IMG SPFI controller driver |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd. | 4 | * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd. |
| 5 | * Copyright (C) 2014 Google, Inc. | 5 | * Copyright (C) 2014 Google, Inc. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, | 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2, as published by the Free Software Foundation. | 9 | * version 2, as published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/clk.h> | 12 | #include <linux/clk.h> |
| 13 | #include <linux/delay.h> | 13 | #include <linux/delay.h> |
| 14 | #include <linux/dmaengine.h> | 14 | #include <linux/dmaengine.h> |
| 15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
| 18 | #include <linux/module.h> | 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> | 19 | #include <linux/of.h> |
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/pm_runtime.h> | 21 | #include <linux/pm_runtime.h> |
| 22 | #include <linux/scatterlist.h> | 22 | #include <linux/scatterlist.h> |
| 23 | #include <linux/slab.h> | 23 | #include <linux/slab.h> |
| 24 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
| 25 | #include <linux/spinlock.h> | 25 | #include <linux/spinlock.h> |
| 26 | 26 | ||
| 27 | #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x)) | 27 | #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x)) |
| 28 | #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24 | 28 | #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24 |
| 29 | #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff | 29 | #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff |
| 30 | #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16 | 30 | #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16 |
| 31 | #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff | 31 | #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff |
| 32 | #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8 | 32 | #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8 |
| 33 | #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff | 33 | #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff |
| 34 | #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0 | 34 | #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0 |
| 35 | #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff | 35 | #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff |
| 36 | 36 | ||
| 37 | #define SPFI_CONTROL 0x14 | 37 | #define SPFI_CONTROL 0x14 |
| 38 | #define SPFI_CONTROL_CONTINUE BIT(12) | 38 | #define SPFI_CONTROL_CONTINUE BIT(12) |
| 39 | #define SPFI_CONTROL_SOFT_RESET BIT(11) | 39 | #define SPFI_CONTROL_SOFT_RESET BIT(11) |
| 40 | #define SPFI_CONTROL_SEND_DMA BIT(10) | 40 | #define SPFI_CONTROL_SEND_DMA BIT(10) |
| 41 | #define SPFI_CONTROL_GET_DMA BIT(9) | 41 | #define SPFI_CONTROL_GET_DMA BIT(9) |
| 42 | #define SPFI_CONTROL_TMODE_SHIFT 5 | 42 | #define SPFI_CONTROL_TMODE_SHIFT 5 |
| 43 | #define SPFI_CONTROL_TMODE_MASK 0x7 | 43 | #define SPFI_CONTROL_TMODE_MASK 0x7 |
| 44 | #define SPFI_CONTROL_TMODE_SINGLE 0 | 44 | #define SPFI_CONTROL_TMODE_SINGLE 0 |
| 45 | #define SPFI_CONTROL_TMODE_DUAL 1 | 45 | #define SPFI_CONTROL_TMODE_DUAL 1 |
| 46 | #define SPFI_CONTROL_TMODE_QUAD 2 | 46 | #define SPFI_CONTROL_TMODE_QUAD 2 |
| 47 | #define SPFI_CONTROL_SPFI_EN BIT(0) | 47 | #define SPFI_CONTROL_SPFI_EN BIT(0) |
| 48 | 48 | ||
| 49 | #define SPFI_TRANSACTION 0x18 | 49 | #define SPFI_TRANSACTION 0x18 |
| 50 | #define SPFI_TRANSACTION_TSIZE_SHIFT 16 | 50 | #define SPFI_TRANSACTION_TSIZE_SHIFT 16 |
| 51 | #define SPFI_TRANSACTION_TSIZE_MASK 0xffff | 51 | #define SPFI_TRANSACTION_TSIZE_MASK 0xffff |
| 52 | 52 | ||
| 53 | #define SPFI_PORT_STATE 0x1c | 53 | #define SPFI_PORT_STATE 0x1c |
| 54 | #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 | 54 | #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 |
| 55 | #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7 | 55 | #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7 |
| 56 | #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x)) | 56 | #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x)) |
| 57 | #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x)) | 57 | #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x)) |
| 58 | 58 | ||
| 59 | #define SPFI_TX_32BIT_VALID_DATA 0x20 | 59 | #define SPFI_TX_32BIT_VALID_DATA 0x20 |
| 60 | #define SPFI_TX_8BIT_VALID_DATA 0x24 | 60 | #define SPFI_TX_8BIT_VALID_DATA 0x24 |
| 61 | #define SPFI_RX_32BIT_VALID_DATA 0x28 | 61 | #define SPFI_RX_32BIT_VALID_DATA 0x28 |
| 62 | #define SPFI_RX_8BIT_VALID_DATA 0x2c | 62 | #define SPFI_RX_8BIT_VALID_DATA 0x2c |
| 63 | 63 | ||
| 64 | #define SPFI_INTERRUPT_STATUS 0x30 | 64 | #define SPFI_INTERRUPT_STATUS 0x30 |
| 65 | #define SPFI_INTERRUPT_ENABLE 0x34 | 65 | #define SPFI_INTERRUPT_ENABLE 0x34 |
| 66 | #define SPFI_INTERRUPT_CLEAR 0x38 | 66 | #define SPFI_INTERRUPT_CLEAR 0x38 |
| 67 | #define SPFI_INTERRUPT_IACCESS BIT(12) | 67 | #define SPFI_INTERRUPT_IACCESS BIT(12) |
| 68 | #define SPFI_INTERRUPT_GDEX8BIT BIT(11) | 68 | #define SPFI_INTERRUPT_GDEX8BIT BIT(11) |
| 69 | #define SPFI_INTERRUPT_ALLDONETRIG BIT(9) | 69 | #define SPFI_INTERRUPT_ALLDONETRIG BIT(9) |
| 70 | #define SPFI_INTERRUPT_GDFUL BIT(8) | 70 | #define SPFI_INTERRUPT_GDFUL BIT(8) |
| 71 | #define SPFI_INTERRUPT_GDHF BIT(7) | 71 | #define SPFI_INTERRUPT_GDHF BIT(7) |
| 72 | #define SPFI_INTERRUPT_GDEX32BIT BIT(6) | 72 | #define SPFI_INTERRUPT_GDEX32BIT BIT(6) |
| 73 | #define SPFI_INTERRUPT_GDTRIG BIT(5) | 73 | #define SPFI_INTERRUPT_GDTRIG BIT(5) |
| 74 | #define SPFI_INTERRUPT_SDFUL BIT(3) | 74 | #define SPFI_INTERRUPT_SDFUL BIT(3) |
| 75 | #define SPFI_INTERRUPT_SDHF BIT(2) | 75 | #define SPFI_INTERRUPT_SDHF BIT(2) |
| 76 | #define SPFI_INTERRUPT_SDE BIT(1) | 76 | #define SPFI_INTERRUPT_SDE BIT(1) |
| 77 | #define SPFI_INTERRUPT_SDTRIG BIT(0) | 77 | #define SPFI_INTERRUPT_SDTRIG BIT(0) |
| 78 | 78 | ||
| 79 | /* | 79 | /* |
| 80 | * There are four parallel FIFOs of 16 bytes each. The word buffer | 80 | * There are four parallel FIFOs of 16 bytes each. The word buffer |
| 81 | * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an | 81 | * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an |
| 82 | * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA) | 82 | * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA) |
| 83 | * accesses only a single FIFO, resulting in an effective FIFO size of | 83 | * accesses only a single FIFO, resulting in an effective FIFO size of |
| 84 | * 16 bytes. | 84 | * 16 bytes. |
| 85 | */ | 85 | */ |
| 86 | #define SPFI_32BIT_FIFO_SIZE 64 | 86 | #define SPFI_32BIT_FIFO_SIZE 64 |
| 87 | #define SPFI_8BIT_FIFO_SIZE 16 | 87 | #define SPFI_8BIT_FIFO_SIZE 16 |
| 88 | 88 | ||
| 89 | struct img_spfi { | 89 | struct img_spfi { |
| 90 | struct device *dev; | 90 | struct device *dev; |
| 91 | struct spi_master *master; | 91 | struct spi_master *master; |
| 92 | spinlock_t lock; | 92 | spinlock_t lock; |
| 93 | 93 | ||
| 94 | void __iomem *regs; | 94 | void __iomem *regs; |
| 95 | phys_addr_t phys; | 95 | phys_addr_t phys; |
| 96 | int irq; | 96 | int irq; |
| 97 | struct clk *spfi_clk; | 97 | struct clk *spfi_clk; |
| 98 | struct clk *sys_clk; | 98 | struct clk *sys_clk; |
| 99 | 99 | ||
| 100 | struct dma_chan *rx_ch; | 100 | struct dma_chan *rx_ch; |
| 101 | struct dma_chan *tx_ch; | 101 | struct dma_chan *tx_ch; |
| 102 | bool tx_dma_busy; | 102 | bool tx_dma_busy; |
| 103 | bool rx_dma_busy; | 103 | bool rx_dma_busy; |
| 104 | }; | 104 | }; |
| 105 | 105 | ||
| 106 | static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg) | 106 | static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg) |
| 107 | { | 107 | { |
| 108 | return readl(spfi->regs + reg); | 108 | return readl(spfi->regs + reg); |
| 109 | } | 109 | } |
| 110 | 110 | ||
| 111 | static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg) | 111 | static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg) |
| 112 | { | 112 | { |
| 113 | writel(val, spfi->regs + reg); | 113 | writel(val, spfi->regs + reg); |
| 114 | } | 114 | } |
| 115 | 115 | ||
| 116 | static inline void spfi_start(struct img_spfi *spfi) | 116 | static inline void spfi_start(struct img_spfi *spfi) |
| 117 | { | 117 | { |
| 118 | u32 val; | 118 | u32 val; |
| 119 | 119 | ||
| 120 | val = spfi_readl(spfi, SPFI_CONTROL); | 120 | val = spfi_readl(spfi, SPFI_CONTROL); |
| 121 | val |= SPFI_CONTROL_SPFI_EN; | 121 | val |= SPFI_CONTROL_SPFI_EN; |
| 122 | spfi_writel(spfi, val, SPFI_CONTROL); | 122 | spfi_writel(spfi, val, SPFI_CONTROL); |
| 123 | } | 123 | } |
| 124 | 124 | ||
| 125 | static inline void spfi_stop(struct img_spfi *spfi) | 125 | static inline void spfi_stop(struct img_spfi *spfi) |
| 126 | { | 126 | { |
| 127 | u32 val; | 127 | u32 val; |
| 128 | 128 | ||
| 129 | val = spfi_readl(spfi, SPFI_CONTROL); | 129 | val = spfi_readl(spfi, SPFI_CONTROL); |
| 130 | val &= ~SPFI_CONTROL_SPFI_EN; | 130 | val &= ~SPFI_CONTROL_SPFI_EN; |
| 131 | spfi_writel(spfi, val, SPFI_CONTROL); | 131 | spfi_writel(spfi, val, SPFI_CONTROL); |
| 132 | } | 132 | } |
| 133 | 133 | ||
| 134 | static inline void spfi_reset(struct img_spfi *spfi) | 134 | static inline void spfi_reset(struct img_spfi *spfi) |
| 135 | { | 135 | { |
| 136 | spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL); | 136 | spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL); |
| 137 | udelay(1); | 137 | udelay(1); |
| 138 | spfi_writel(spfi, 0, SPFI_CONTROL); | 138 | spfi_writel(spfi, 0, SPFI_CONTROL); |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | static void spfi_flush_tx_fifo(struct img_spfi *spfi) | 141 | static void spfi_flush_tx_fifo(struct img_spfi *spfi) |
| 142 | { | 142 | { |
| 143 | unsigned long timeout = jiffies + msecs_to_jiffies(10); | 143 | unsigned long timeout = jiffies + msecs_to_jiffies(10); |
| 144 | 144 | ||
| 145 | spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR); | 145 | spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR); |
| 146 | while (time_before(jiffies, timeout)) { | 146 | while (time_before(jiffies, timeout)) { |
| 147 | if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & | 147 | if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & |
| 148 | SPFI_INTERRUPT_SDE) | 148 | SPFI_INTERRUPT_SDE) |
| 149 | return; | 149 | return; |
| 150 | cpu_relax(); | 150 | cpu_relax(); |
| 151 | } | 151 | } |
| 152 | 152 | ||
| 153 | dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n"); | 153 | dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n"); |
| 154 | spfi_reset(spfi); | 154 | spfi_reset(spfi); |
| 155 | } | 155 | } |
| 156 | 156 | ||
| 157 | static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf, | 157 | static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf, |
| 158 | unsigned int max) | 158 | unsigned int max) |
| 159 | { | 159 | { |
| 160 | unsigned int count = 0; | 160 | unsigned int count = 0; |
| 161 | u32 status; | 161 | u32 status; |
| 162 | 162 | ||
| 163 | while (count < max) { | 163 | while (count < max) { |
| 164 | spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); | 164 | spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); |
| 165 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | 165 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); |
| 166 | if (status & SPFI_INTERRUPT_SDFUL) | 166 | if (status & SPFI_INTERRUPT_SDFUL) |
| 167 | break; | 167 | break; |
| 168 | spfi_writel(spfi, buf[count / 4], SPFI_TX_32BIT_VALID_DATA); | 168 | spfi_writel(spfi, buf[count / 4], SPFI_TX_32BIT_VALID_DATA); |
| 169 | count += 4; | 169 | count += 4; |
| 170 | } | 170 | } |
| 171 | 171 | ||
| 172 | return count; | 172 | return count; |
| 173 | } | 173 | } |
| 174 | 174 | ||
| 175 | static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf, | 175 | static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf, |
| 176 | unsigned int max) | 176 | unsigned int max) |
| 177 | { | 177 | { |
| 178 | unsigned int count = 0; | 178 | unsigned int count = 0; |
| 179 | u32 status; | 179 | u32 status; |
| 180 | 180 | ||
| 181 | while (count < max) { | 181 | while (count < max) { |
| 182 | spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); | 182 | spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); |
| 183 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | 183 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); |
| 184 | if (status & SPFI_INTERRUPT_SDFUL) | 184 | if (status & SPFI_INTERRUPT_SDFUL) |
| 185 | break; | 185 | break; |
| 186 | spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA); | 186 | spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA); |
| 187 | count++; | 187 | count++; |
| 188 | } | 188 | } |
| 189 | 189 | ||
| 190 | return count; | 190 | return count; |
| 191 | } | 191 | } |
| 192 | 192 | ||
| 193 | static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf, | 193 | static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf, |
| 194 | unsigned int max) | 194 | unsigned int max) |
| 195 | { | 195 | { |
| 196 | unsigned int count = 0; | 196 | unsigned int count = 0; |
| 197 | u32 status; | 197 | u32 status; |
| 198 | 198 | ||
| 199 | while (count < max) { | 199 | while (count < max) { |
| 200 | spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT, | 200 | spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT, |
| 201 | SPFI_INTERRUPT_CLEAR); | 201 | SPFI_INTERRUPT_CLEAR); |
| 202 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | 202 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); |
| 203 | if (!(status & SPFI_INTERRUPT_GDEX32BIT)) | 203 | if (!(status & SPFI_INTERRUPT_GDEX32BIT)) |
| 204 | break; | 204 | break; |
| 205 | buf[count / 4] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA); | 205 | buf[count / 4] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA); |
| 206 | count += 4; | 206 | count += 4; |
| 207 | } | 207 | } |
| 208 | 208 | ||
| 209 | return count; | 209 | return count; |
| 210 | } | 210 | } |
| 211 | 211 | ||
| 212 | static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf, | 212 | static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf, |
| 213 | unsigned int max) | 213 | unsigned int max) |
| 214 | { | 214 | { |
| 215 | unsigned int count = 0; | 215 | unsigned int count = 0; |
| 216 | u32 status; | 216 | u32 status; |
| 217 | 217 | ||
| 218 | while (count < max) { | 218 | while (count < max) { |
| 219 | spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT, | 219 | spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT, |
| 220 | SPFI_INTERRUPT_CLEAR); | 220 | SPFI_INTERRUPT_CLEAR); |
| 221 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | 221 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); |
| 222 | if (!(status & SPFI_INTERRUPT_GDEX8BIT)) | 222 | if (!(status & SPFI_INTERRUPT_GDEX8BIT)) |
| 223 | break; | 223 | break; |
| 224 | buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA); | 224 | buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA); |
| 225 | count++; | 225 | count++; |
| 226 | } | 226 | } |
| 227 | 227 | ||
| 228 | return count; | 228 | return count; |
| 229 | } | 229 | } |
| 230 | 230 | ||
| 231 | static int img_spfi_start_pio(struct spi_master *master, | 231 | static int img_spfi_start_pio(struct spi_master *master, |
| 232 | struct spi_device *spi, | 232 | struct spi_device *spi, |
| 233 | struct spi_transfer *xfer) | 233 | struct spi_transfer *xfer) |
| 234 | { | 234 | { |
| 235 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | 235 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); |
| 236 | unsigned int tx_bytes = 0, rx_bytes = 0; | 236 | unsigned int tx_bytes = 0, rx_bytes = 0; |
| 237 | const void *tx_buf = xfer->tx_buf; | 237 | const void *tx_buf = xfer->tx_buf; |
| 238 | void *rx_buf = xfer->rx_buf; | 238 | void *rx_buf = xfer->rx_buf; |
| 239 | unsigned long timeout; | 239 | unsigned long timeout; |
| 240 | 240 | ||
| 241 | if (tx_buf) | 241 | if (tx_buf) |
| 242 | tx_bytes = xfer->len; | 242 | tx_bytes = xfer->len; |
| 243 | if (rx_buf) | 243 | if (rx_buf) |
| 244 | rx_bytes = xfer->len; | 244 | rx_bytes = xfer->len; |
| 245 | 245 | ||
| 246 | spfi_start(spfi); | 246 | spfi_start(spfi); |
| 247 | 247 | ||
| 248 | timeout = jiffies + | 248 | timeout = jiffies + |
| 249 | msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100); | 249 | msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100); |
| 250 | while ((tx_bytes > 0 || rx_bytes > 0) && | 250 | while ((tx_bytes > 0 || rx_bytes > 0) && |
| 251 | time_before(jiffies, timeout)) { | 251 | time_before(jiffies, timeout)) { |
| 252 | unsigned int tx_count, rx_count; | 252 | unsigned int tx_count, rx_count; |
| 253 | 253 | ||
| 254 | switch (xfer->bits_per_word) { | 254 | switch (xfer->bits_per_word) { |
| 255 | case 32: | 255 | case 32: |
| 256 | tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes); | 256 | tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes); |
| 257 | rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes); | 257 | rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes); |
| 258 | break; | 258 | break; |
| 259 | case 8: | 259 | case 8: |
| 260 | default: | 260 | default: |
| 261 | tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes); | 261 | tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes); |
| 262 | rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes); | 262 | rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes); |
| 263 | break; | 263 | break; |
| 264 | } | 264 | } |
| 265 | 265 | ||
| 266 | tx_buf += tx_count; | 266 | tx_buf += tx_count; |
| 267 | rx_buf += rx_count; | 267 | rx_buf += rx_count; |
| 268 | tx_bytes -= tx_count; | 268 | tx_bytes -= tx_count; |
| 269 | rx_bytes -= rx_count; | 269 | rx_bytes -= rx_count; |
| 270 | 270 | ||
| 271 | cpu_relax(); | 271 | cpu_relax(); |
| 272 | } | 272 | } |
| 273 | 273 | ||
| 274 | if (rx_bytes > 0 || tx_bytes > 0) { | 274 | if (rx_bytes > 0 || tx_bytes > 0) { |
| 275 | dev_err(spfi->dev, "PIO transfer timed out\n"); | 275 | dev_err(spfi->dev, "PIO transfer timed out\n"); |
| 276 | spfi_reset(spfi); | 276 | spfi_reset(spfi); |
| 277 | return -ETIMEDOUT; | 277 | return -ETIMEDOUT; |
| 278 | } | 278 | } |
| 279 | 279 | ||
| 280 | if (tx_buf) | 280 | if (tx_buf) |
| 281 | spfi_flush_tx_fifo(spfi); | 281 | spfi_flush_tx_fifo(spfi); |
| 282 | spfi_stop(spfi); | 282 | spfi_stop(spfi); |
| 283 | 283 | ||
| 284 | return 0; | 284 | return 0; |
| 285 | } | 285 | } |
| 286 | 286 | ||
| 287 | static void img_spfi_dma_rx_cb(void *data) | 287 | static void img_spfi_dma_rx_cb(void *data) |
| 288 | { | 288 | { |
| 289 | struct img_spfi *spfi = data; | 289 | struct img_spfi *spfi = data; |
| 290 | unsigned long flags; | 290 | unsigned long flags; |
| 291 | 291 | ||
| 292 | spin_lock_irqsave(&spfi->lock, flags); | 292 | spin_lock_irqsave(&spfi->lock, flags); |
| 293 | 293 | ||
| 294 | spfi->rx_dma_busy = false; | 294 | spfi->rx_dma_busy = false; |
| 295 | if (!spfi->tx_dma_busy) { | 295 | if (!spfi->tx_dma_busy) { |
| 296 | spfi_stop(spfi); | 296 | spfi_stop(spfi); |
| 297 | spi_finalize_current_transfer(spfi->master); | 297 | spi_finalize_current_transfer(spfi->master); |
| 298 | } | 298 | } |
| 299 | 299 | ||
| 300 | spin_unlock_irqrestore(&spfi->lock, flags); | 300 | spin_unlock_irqrestore(&spfi->lock, flags); |
| 301 | } | 301 | } |
| 302 | 302 | ||
| 303 | static void img_spfi_dma_tx_cb(void *data) | 303 | static void img_spfi_dma_tx_cb(void *data) |
| 304 | { | 304 | { |
| 305 | struct img_spfi *spfi = data; | 305 | struct img_spfi *spfi = data; |
| 306 | unsigned long flags; | 306 | unsigned long flags; |
| 307 | 307 | ||
| 308 | spfi_flush_tx_fifo(spfi); | 308 | spfi_flush_tx_fifo(spfi); |
| 309 | 309 | ||
| 310 | spin_lock_irqsave(&spfi->lock, flags); | 310 | spin_lock_irqsave(&spfi->lock, flags); |
| 311 | 311 | ||
| 312 | spfi->tx_dma_busy = false; | 312 | spfi->tx_dma_busy = false; |
| 313 | if (!spfi->rx_dma_busy) { | 313 | if (!spfi->rx_dma_busy) { |
| 314 | spfi_stop(spfi); | 314 | spfi_stop(spfi); |
| 315 | spi_finalize_current_transfer(spfi->master); | 315 | spi_finalize_current_transfer(spfi->master); |
| 316 | } | 316 | } |
| 317 | 317 | ||
| 318 | spin_unlock_irqrestore(&spfi->lock, flags); | 318 | spin_unlock_irqrestore(&spfi->lock, flags); |
| 319 | } | 319 | } |
| 320 | 320 | ||
| 321 | static int img_spfi_start_dma(struct spi_master *master, | 321 | static int img_spfi_start_dma(struct spi_master *master, |
| 322 | struct spi_device *spi, | 322 | struct spi_device *spi, |
| 323 | struct spi_transfer *xfer) | 323 | struct spi_transfer *xfer) |
| 324 | { | 324 | { |
| 325 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | 325 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); |
| 326 | struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL; | 326 | struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL; |
| 327 | struct dma_slave_config rxconf, txconf; | 327 | struct dma_slave_config rxconf, txconf; |
| 328 | 328 | ||
| 329 | spfi->rx_dma_busy = false; | 329 | spfi->rx_dma_busy = false; |
| 330 | spfi->tx_dma_busy = false; | 330 | spfi->tx_dma_busy = false; |
| 331 | 331 | ||
| 332 | if (xfer->rx_buf) { | 332 | if (xfer->rx_buf) { |
| 333 | rxconf.direction = DMA_DEV_TO_MEM; | 333 | rxconf.direction = DMA_DEV_TO_MEM; |
| 334 | switch (xfer->bits_per_word) { | 334 | switch (xfer->bits_per_word) { |
| 335 | case 32: | 335 | case 32: |
| 336 | rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; | 336 | rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; |
| 337 | rxconf.src_addr_width = 4; | 337 | rxconf.src_addr_width = 4; |
| 338 | rxconf.src_maxburst = 4; | 338 | rxconf.src_maxburst = 4; |
| 339 | break; | 339 | break; |
| 340 | case 8: | 340 | case 8: |
| 341 | default: | 341 | default: |
| 342 | rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; | 342 | rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; |
| 343 | rxconf.src_addr_width = 1; | 343 | rxconf.src_addr_width = 1; |
| 344 | rxconf.src_maxburst = 1; | 344 | rxconf.src_maxburst = 1; |
| 345 | } | 345 | } |
| 346 | dmaengine_slave_config(spfi->rx_ch, &rxconf); | 346 | dmaengine_slave_config(spfi->rx_ch, &rxconf); |
| 347 | 347 | ||
| 348 | rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, | 348 | rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, |
| 349 | xfer->rx_sg.nents, | 349 | xfer->rx_sg.nents, |
| 350 | DMA_DEV_TO_MEM, | 350 | DMA_DEV_TO_MEM, |
| 351 | DMA_PREP_INTERRUPT); | 351 | DMA_PREP_INTERRUPT); |
| 352 | if (!rxdesc) | 352 | if (!rxdesc) |
| 353 | goto stop_dma; | 353 | goto stop_dma; |
| 354 | 354 | ||
| 355 | rxdesc->callback = img_spfi_dma_rx_cb; | 355 | rxdesc->callback = img_spfi_dma_rx_cb; |
| 356 | rxdesc->callback_param = spfi; | 356 | rxdesc->callback_param = spfi; |
| 357 | } | 357 | } |
| 358 | 358 | ||
| 359 | if (xfer->tx_buf) { | 359 | if (xfer->tx_buf) { |
| 360 | txconf.direction = DMA_MEM_TO_DEV; | 360 | txconf.direction = DMA_MEM_TO_DEV; |
| 361 | switch (xfer->bits_per_word) { | 361 | switch (xfer->bits_per_word) { |
| 362 | case 32: | 362 | case 32: |
| 363 | txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; | 363 | txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; |
| 364 | txconf.dst_addr_width = 4; | 364 | txconf.dst_addr_width = 4; |
| 365 | txconf.dst_maxburst = 4; | 365 | txconf.dst_maxburst = 4; |
| 366 | break; | 366 | break; |
| 367 | case 8: | 367 | case 8: |
| 368 | default: | 368 | default: |
| 369 | txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; | 369 | txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; |
| 370 | txconf.dst_addr_width = 1; | 370 | txconf.dst_addr_width = 1; |
| 371 | txconf.dst_maxburst = 1; | 371 | txconf.dst_maxburst = 1; |
| 372 | break; | 372 | break; |
| 373 | } | 373 | } |
| 374 | dmaengine_slave_config(spfi->tx_ch, &txconf); | 374 | dmaengine_slave_config(spfi->tx_ch, &txconf); |
| 375 | 375 | ||
| 376 | txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, | 376 | txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, |
| 377 | xfer->tx_sg.nents, | 377 | xfer->tx_sg.nents, |
| 378 | DMA_MEM_TO_DEV, | 378 | DMA_MEM_TO_DEV, |
| 379 | DMA_PREP_INTERRUPT); | 379 | DMA_PREP_INTERRUPT); |
| 380 | if (!txdesc) | 380 | if (!txdesc) |
| 381 | goto stop_dma; | 381 | goto stop_dma; |
| 382 | 382 | ||
| 383 | txdesc->callback = img_spfi_dma_tx_cb; | 383 | txdesc->callback = img_spfi_dma_tx_cb; |
| 384 | txdesc->callback_param = spfi; | 384 | txdesc->callback_param = spfi; |
| 385 | } | 385 | } |
| 386 | 386 | ||
| 387 | if (xfer->rx_buf) { | 387 | if (xfer->rx_buf) { |
| 388 | spfi->rx_dma_busy = true; | 388 | spfi->rx_dma_busy = true; |
| 389 | dmaengine_submit(rxdesc); | 389 | dmaengine_submit(rxdesc); |
| 390 | dma_async_issue_pending(spfi->rx_ch); | 390 | dma_async_issue_pending(spfi->rx_ch); |
| 391 | } | 391 | } |
| 392 | 392 | ||
| 393 | if (xfer->tx_buf) { | 393 | if (xfer->tx_buf) { |
| 394 | spfi->tx_dma_busy = true; | 394 | spfi->tx_dma_busy = true; |
| 395 | dmaengine_submit(txdesc); | 395 | dmaengine_submit(txdesc); |
| 396 | dma_async_issue_pending(spfi->tx_ch); | 396 | dma_async_issue_pending(spfi->tx_ch); |
| 397 | } | 397 | } |
| 398 | 398 | ||
| 399 | spfi_start(spfi); | 399 | spfi_start(spfi); |
| 400 | 400 | ||
| 401 | return 1; | 401 | return 1; |
| 402 | 402 | ||
| 403 | stop_dma: | 403 | stop_dma: |
| 404 | dmaengine_terminate_all(spfi->rx_ch); | 404 | dmaengine_terminate_all(spfi->rx_ch); |
| 405 | dmaengine_terminate_all(spfi->tx_ch); | 405 | dmaengine_terminate_all(spfi->tx_ch); |
| 406 | return -EIO; | 406 | return -EIO; |
| 407 | } | 407 | } |
| 408 | 408 | ||
| 409 | static void img_spfi_config(struct spi_master *master, struct spi_device *spi, | 409 | static void img_spfi_config(struct spi_master *master, struct spi_device *spi, |
| 410 | struct spi_transfer *xfer) | 410 | struct spi_transfer *xfer) |
| 411 | { | 411 | { |
| 412 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | 412 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); |
| 413 | u32 val, div; | 413 | u32 val, div; |
| 414 | 414 | ||
| 415 | /* | 415 | /* |
| 416 | * output = spfi_clk * (BITCLK / 512), where BITCLK must be a | 416 | * output = spfi_clk * (BITCLK / 512), where BITCLK must be a |
| 417 | * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits) | 417 | * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits) |
| 418 | */ | 418 | */ |
| 419 | div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz); | 419 | div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz); |
| 420 | div = clamp(512 / (1 << get_count_order(div)), 1, 255); | 420 | div = clamp(512 / (1 << get_count_order(div)), 1, 255); |
| 421 | 421 | ||
| 422 | val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); | 422 | val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); |
| 423 | val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << | 423 | val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << |
| 424 | SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); | 424 | SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); |
| 425 | val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; | 425 | val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; |
| 426 | spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); | 426 | spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); |
| 427 | 427 | ||
| 428 | val = spfi_readl(spfi, SPFI_CONTROL); | 428 | val = spfi_readl(spfi, SPFI_CONTROL); |
| 429 | val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); | 429 | val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); |
| 430 | if (xfer->tx_buf) | 430 | if (xfer->tx_buf) |
| 431 | val |= SPFI_CONTROL_SEND_DMA; | 431 | val |= SPFI_CONTROL_SEND_DMA; |
| 432 | if (xfer->rx_buf) | 432 | if (xfer->rx_buf) |
| 433 | val |= SPFI_CONTROL_GET_DMA; | 433 | val |= SPFI_CONTROL_GET_DMA; |
| 434 | val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); | 434 | val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); |
| 435 | if (xfer->tx_nbits == SPI_NBITS_DUAL && | 435 | if (xfer->tx_nbits == SPI_NBITS_DUAL && |
| 436 | xfer->rx_nbits == SPI_NBITS_DUAL) | 436 | xfer->rx_nbits == SPI_NBITS_DUAL) |
| 437 | val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; | 437 | val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; |
| 438 | else if (xfer->tx_nbits == SPI_NBITS_QUAD && | 438 | else if (xfer->tx_nbits == SPI_NBITS_QUAD && |
| 439 | xfer->rx_nbits == SPI_NBITS_QUAD) | 439 | xfer->rx_nbits == SPI_NBITS_QUAD) |
| 440 | val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; | 440 | val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; |
| 441 | val &= ~SPFI_CONTROL_CONTINUE; | 441 | val &= ~SPFI_CONTROL_CONTINUE; |
| 442 | if (!xfer->cs_change && !list_is_last(&xfer->transfer_list, | 442 | if (!xfer->cs_change && !list_is_last(&xfer->transfer_list, |
| 443 | &master->cur_msg->transfers)) | 443 | &master->cur_msg->transfers)) |
| 444 | val |= SPFI_CONTROL_CONTINUE; | 444 | val |= SPFI_CONTROL_CONTINUE; |
| 445 | spfi_writel(spfi, val, SPFI_CONTROL); | 445 | spfi_writel(spfi, val, SPFI_CONTROL); |
| 446 | 446 | ||
| 447 | val = spfi_readl(spfi, SPFI_PORT_STATE); | 447 | val = spfi_readl(spfi, SPFI_PORT_STATE); |
| 448 | if (spi->mode & SPI_CPHA) | 448 | if (spi->mode & SPI_CPHA) |
| 449 | val |= SPFI_PORT_STATE_CK_PHASE(spi->chip_select); | 449 | val |= SPFI_PORT_STATE_CK_PHASE(spi->chip_select); |
| 450 | else | 450 | else |
| 451 | val &= ~SPFI_PORT_STATE_CK_PHASE(spi->chip_select); | 451 | val &= ~SPFI_PORT_STATE_CK_PHASE(spi->chip_select); |
| 452 | if (spi->mode & SPI_CPOL) | 452 | if (spi->mode & SPI_CPOL) |
| 453 | val |= SPFI_PORT_STATE_CK_POL(spi->chip_select); | 453 | val |= SPFI_PORT_STATE_CK_POL(spi->chip_select); |
| 454 | else | 454 | else |
| 455 | val &= ~SPFI_PORT_STATE_CK_POL(spi->chip_select); | 455 | val &= ~SPFI_PORT_STATE_CK_POL(spi->chip_select); |
| 456 | spfi_writel(spfi, val, SPFI_PORT_STATE); | 456 | spfi_writel(spfi, val, SPFI_PORT_STATE); |
| 457 | 457 | ||
| 458 | spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, | 458 | spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, |
| 459 | SPFI_TRANSACTION); | 459 | SPFI_TRANSACTION); |
| 460 | } | 460 | } |
| 461 | 461 | ||
| 462 | static int img_spfi_transfer_one(struct spi_master *master, | 462 | static int img_spfi_transfer_one(struct spi_master *master, |
| 463 | struct spi_device *spi, | 463 | struct spi_device *spi, |
| 464 | struct spi_transfer *xfer) | 464 | struct spi_transfer *xfer) |
| 465 | { | 465 | { |
| 466 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | 466 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); |
| 467 | bool dma_reset = false; | 467 | bool dma_reset = false; |
| 468 | unsigned long flags; | 468 | unsigned long flags; |
| 469 | int ret; | 469 | int ret; |
| 470 | 470 | ||
| 471 | /* | 471 | /* |
| 472 | * Stop all DMA and reset the controller if the previous transaction | 472 | * Stop all DMA and reset the controller if the previous transaction |
| 473 | * timed-out and never completed it's DMA. | 473 | * timed-out and never completed it's DMA. |
| 474 | */ | 474 | */ |
| 475 | spin_lock_irqsave(&spfi->lock, flags); | 475 | spin_lock_irqsave(&spfi->lock, flags); |
| 476 | if (spfi->tx_dma_busy || spfi->rx_dma_busy) { | 476 | if (spfi->tx_dma_busy || spfi->rx_dma_busy) { |
| 477 | dev_err(spfi->dev, "SPI DMA still busy\n"); | 477 | dev_err(spfi->dev, "SPI DMA still busy\n"); |
| 478 | dma_reset = true; | 478 | dma_reset = true; |
| 479 | } | 479 | } |
| 480 | spin_unlock_irqrestore(&spfi->lock, flags); | 480 | spin_unlock_irqrestore(&spfi->lock, flags); |
| 481 | 481 | ||
| 482 | if (dma_reset) { | 482 | if (dma_reset) { |
| 483 | dmaengine_terminate_all(spfi->tx_ch); | 483 | dmaengine_terminate_all(spfi->tx_ch); |
| 484 | dmaengine_terminate_all(spfi->rx_ch); | 484 | dmaengine_terminate_all(spfi->rx_ch); |
| 485 | spfi_reset(spfi); | 485 | spfi_reset(spfi); |
| 486 | } | 486 | } |
| 487 | 487 | ||
| 488 | img_spfi_config(master, spi, xfer); | 488 | img_spfi_config(master, spi, xfer); |
| 489 | if (master->can_dma && master->can_dma(master, spi, xfer)) | 489 | if (master->can_dma && master->can_dma(master, spi, xfer)) |
| 490 | ret = img_spfi_start_dma(master, spi, xfer); | 490 | ret = img_spfi_start_dma(master, spi, xfer); |
| 491 | else | 491 | else |
| 492 | ret = img_spfi_start_pio(master, spi, xfer); | 492 | ret = img_spfi_start_pio(master, spi, xfer); |
| 493 | 493 | ||
| 494 | return ret; | 494 | return ret; |
| 495 | } | 495 | } |
| 496 | 496 | ||
| 497 | static void img_spfi_set_cs(struct spi_device *spi, bool enable) | 497 | static void img_spfi_set_cs(struct spi_device *spi, bool enable) |
| 498 | { | 498 | { |
| 499 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | 499 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); |
| 500 | u32 val; | 500 | u32 val; |
| 501 | 501 | ||
| 502 | val = spfi_readl(spfi, SPFI_PORT_STATE); | 502 | val = spfi_readl(spfi, SPFI_PORT_STATE); |
| 503 | val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT); | 503 | val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT); |
| 504 | val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; | 504 | val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; |
| 505 | spfi_writel(spfi, val, SPFI_PORT_STATE); | 505 | spfi_writel(spfi, val, SPFI_PORT_STATE); |
| 506 | } | 506 | } |
| 507 | 507 | ||
| 508 | static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi, | 508 | static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi, |
| 509 | struct spi_transfer *xfer) | 509 | struct spi_transfer *xfer) |
| 510 | { | 510 | { |
| 511 | if (xfer->bits_per_word == 8 && xfer->len > SPFI_8BIT_FIFO_SIZE) | 511 | if (xfer->bits_per_word == 8 && xfer->len > SPFI_8BIT_FIFO_SIZE) |
| 512 | return true; | 512 | return true; |
| 513 | if (xfer->bits_per_word == 32 && xfer->len > SPFI_32BIT_FIFO_SIZE) | 513 | if (xfer->bits_per_word == 32 && xfer->len > SPFI_32BIT_FIFO_SIZE) |
| 514 | return true; | 514 | return true; |
| 515 | return false; | 515 | return false; |
| 516 | } | 516 | } |
| 517 | 517 | ||
| 518 | static irqreturn_t img_spfi_irq(int irq, void *dev_id) | 518 | static irqreturn_t img_spfi_irq(int irq, void *dev_id) |
| 519 | { | 519 | { |
| 520 | struct img_spfi *spfi = (struct img_spfi *)dev_id; | 520 | struct img_spfi *spfi = (struct img_spfi *)dev_id; |
| 521 | u32 status; | 521 | u32 status; |
| 522 | 522 | ||
| 523 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | 523 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); |
| 524 | if (status & SPFI_INTERRUPT_IACCESS) { | 524 | if (status & SPFI_INTERRUPT_IACCESS) { |
| 525 | spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR); | 525 | spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR); |
| 526 | dev_err(spfi->dev, "Illegal access interrupt"); | 526 | dev_err(spfi->dev, "Illegal access interrupt"); |
| 527 | return IRQ_HANDLED; | 527 | return IRQ_HANDLED; |
| 528 | } | 528 | } |
| 529 | 529 | ||
| 530 | return IRQ_NONE; | 530 | return IRQ_NONE; |
| 531 | } | 531 | } |
| 532 | 532 | ||
| 533 | static int img_spfi_probe(struct platform_device *pdev) | 533 | static int img_spfi_probe(struct platform_device *pdev) |
| 534 | { | 534 | { |
| 535 | struct spi_master *master; | 535 | struct spi_master *master; |
| 536 | struct img_spfi *spfi; | 536 | struct img_spfi *spfi; |
| 537 | struct resource *res; | 537 | struct resource *res; |
| 538 | int ret; | 538 | int ret; |
| 539 | 539 | ||
| 540 | master = spi_alloc_master(&pdev->dev, sizeof(*spfi)); | 540 | master = spi_alloc_master(&pdev->dev, sizeof(*spfi)); |
| 541 | if (!master) | 541 | if (!master) |
| 542 | return -ENOMEM; | 542 | return -ENOMEM; |
| 543 | platform_set_drvdata(pdev, master); | 543 | platform_set_drvdata(pdev, master); |
| 544 | 544 | ||
| 545 | spfi = spi_master_get_devdata(master); | 545 | spfi = spi_master_get_devdata(master); |
| 546 | spfi->dev = &pdev->dev; | 546 | spfi->dev = &pdev->dev; |
| 547 | spfi->master = master; | 547 | spfi->master = master; |
| 548 | spin_lock_init(&spfi->lock); | 548 | spin_lock_init(&spfi->lock); |
| 549 | 549 | ||
| 550 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 550 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 551 | spfi->regs = devm_ioremap_resource(spfi->dev, res); | 551 | spfi->regs = devm_ioremap_resource(spfi->dev, res); |
| 552 | if (IS_ERR(spfi->regs)) { | 552 | if (IS_ERR(spfi->regs)) { |
| 553 | ret = PTR_ERR(spfi->regs); | 553 | ret = PTR_ERR(spfi->regs); |
| 554 | goto put_spi; | 554 | goto put_spi; |
| 555 | } | 555 | } |
| 556 | spfi->phys = res->start; | 556 | spfi->phys = res->start; |
| 557 | 557 | ||
| 558 | spfi->irq = platform_get_irq(pdev, 0); | 558 | spfi->irq = platform_get_irq(pdev, 0); |
| 559 | if (spfi->irq < 0) { | 559 | if (spfi->irq < 0) { |
| 560 | ret = spfi->irq; | 560 | ret = spfi->irq; |
| 561 | goto put_spi; | 561 | goto put_spi; |
| 562 | } | 562 | } |
| 563 | ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq, | 563 | ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq, |
| 564 | IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi); | 564 | IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi); |
| 565 | if (ret) | 565 | if (ret) |
| 566 | goto put_spi; | 566 | goto put_spi; |
| 567 | 567 | ||
| 568 | spfi->sys_clk = devm_clk_get(spfi->dev, "sys"); | 568 | spfi->sys_clk = devm_clk_get(spfi->dev, "sys"); |
| 569 | if (IS_ERR(spfi->sys_clk)) { | 569 | if (IS_ERR(spfi->sys_clk)) { |
| 570 | ret = PTR_ERR(spfi->sys_clk); | 570 | ret = PTR_ERR(spfi->sys_clk); |
| 571 | goto put_spi; | 571 | goto put_spi; |
| 572 | } | 572 | } |
| 573 | spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi"); | 573 | spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi"); |
| 574 | if (IS_ERR(spfi->spfi_clk)) { | 574 | if (IS_ERR(spfi->spfi_clk)) { |
| 575 | ret = PTR_ERR(spfi->spfi_clk); | 575 | ret = PTR_ERR(spfi->spfi_clk); |
| 576 | goto put_spi; | 576 | goto put_spi; |
| 577 | } | 577 | } |
| 578 | 578 | ||
| 579 | ret = clk_prepare_enable(spfi->sys_clk); | 579 | ret = clk_prepare_enable(spfi->sys_clk); |
| 580 | if (ret) | 580 | if (ret) |
| 581 | goto put_spi; | 581 | goto put_spi; |
| 582 | ret = clk_prepare_enable(spfi->spfi_clk); | 582 | ret = clk_prepare_enable(spfi->spfi_clk); |
| 583 | if (ret) | 583 | if (ret) |
| 584 | goto disable_pclk; | 584 | goto disable_pclk; |
| 585 | 585 | ||
| 586 | spfi_reset(spfi); | 586 | spfi_reset(spfi); |
| 587 | /* | 587 | /* |
| 588 | * Only enable the error (IACCESS) interrupt. In PIO mode we'll | 588 | * Only enable the error (IACCESS) interrupt. In PIO mode we'll |
| 589 | * poll the status of the FIFOs. | 589 | * poll the status of the FIFOs. |
| 590 | */ | 590 | */ |
| 591 | spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE); | 591 | spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE); |
| 592 | 592 | ||
| 593 | master->auto_runtime_pm = true; | 593 | master->auto_runtime_pm = true; |
| 594 | master->bus_num = pdev->id; | 594 | master->bus_num = pdev->id; |
| 595 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL; | 595 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL; |
| 596 | if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode")) | 596 | if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode")) |
| 597 | master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD; | 597 | master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD; |
| 598 | master->num_chipselect = 5; | 598 | master->num_chipselect = 5; |
| 599 | master->dev.of_node = pdev->dev.of_node; | 599 | master->dev.of_node = pdev->dev.of_node; |
| 600 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); | 600 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); |
| 601 | master->max_speed_hz = clk_get_rate(spfi->spfi_clk); | 601 | master->max_speed_hz = clk_get_rate(spfi->spfi_clk); |
| 602 | master->min_speed_hz = master->max_speed_hz / 512; | 602 | master->min_speed_hz = master->max_speed_hz / 512; |
| 603 | 603 | ||
| 604 | master->set_cs = img_spfi_set_cs; | 604 | master->set_cs = img_spfi_set_cs; |
| 605 | master->transfer_one = img_spfi_transfer_one; | 605 | master->transfer_one = img_spfi_transfer_one; |
| 606 | 606 | ||
| 607 | spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx"); | 607 | spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx"); |
| 608 | spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx"); | 608 | spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx"); |
| 609 | if (!spfi->tx_ch || !spfi->rx_ch) { | 609 | if (!spfi->tx_ch || !spfi->rx_ch) { |
| 610 | if (spfi->tx_ch) | 610 | if (spfi->tx_ch) |
| 611 | dma_release_channel(spfi->tx_ch); | 611 | dma_release_channel(spfi->tx_ch); |
| 612 | if (spfi->rx_ch) | 612 | if (spfi->rx_ch) |
| 613 | dma_release_channel(spfi->rx_ch); | 613 | dma_release_channel(spfi->rx_ch); |
| 614 | dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n"); | 614 | dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n"); |
| 615 | } else { | 615 | } else { |
| 616 | master->dma_tx = spfi->tx_ch; | 616 | master->dma_tx = spfi->tx_ch; |
| 617 | master->dma_rx = spfi->rx_ch; | 617 | master->dma_rx = spfi->rx_ch; |
| 618 | master->can_dma = img_spfi_can_dma; | 618 | master->can_dma = img_spfi_can_dma; |
| 619 | } | 619 | } |
| 620 | 620 | ||
| 621 | pm_runtime_set_active(spfi->dev); | 621 | pm_runtime_set_active(spfi->dev); |
| 622 | pm_runtime_enable(spfi->dev); | 622 | pm_runtime_enable(spfi->dev); |
| 623 | 623 | ||
| 624 | ret = devm_spi_register_master(spfi->dev, master); | 624 | ret = devm_spi_register_master(spfi->dev, master); |
| 625 | if (ret) | 625 | if (ret) |
| 626 | goto disable_pm; | 626 | goto disable_pm; |
| 627 | 627 | ||
| 628 | return 0; | 628 | return 0; |
| 629 | 629 | ||
| 630 | disable_pm: | 630 | disable_pm: |
| 631 | pm_runtime_disable(spfi->dev); | 631 | pm_runtime_disable(spfi->dev); |
| 632 | if (spfi->rx_ch) | 632 | if (spfi->rx_ch) |
| 633 | dma_release_channel(spfi->rx_ch); | 633 | dma_release_channel(spfi->rx_ch); |
| 634 | if (spfi->tx_ch) | 634 | if (spfi->tx_ch) |
| 635 | dma_release_channel(spfi->tx_ch); | 635 | dma_release_channel(spfi->tx_ch); |
| 636 | clk_disable_unprepare(spfi->spfi_clk); | 636 | clk_disable_unprepare(spfi->spfi_clk); |
| 637 | disable_pclk: | 637 | disable_pclk: |
| 638 | clk_disable_unprepare(spfi->sys_clk); | 638 | clk_disable_unprepare(spfi->sys_clk); |
| 639 | put_spi: | 639 | put_spi: |
| 640 | spi_master_put(master); | 640 | spi_master_put(master); |
| 641 | 641 | ||
| 642 | return ret; | 642 | return ret; |
| 643 | } | 643 | } |
| 644 | 644 | ||
| 645 | static int img_spfi_remove(struct platform_device *pdev) | 645 | static int img_spfi_remove(struct platform_device *pdev) |
| 646 | { | 646 | { |
| 647 | struct spi_master *master = platform_get_drvdata(pdev); | 647 | struct spi_master *master = platform_get_drvdata(pdev); |
| 648 | struct img_spfi *spfi = spi_master_get_devdata(master); | 648 | struct img_spfi *spfi = spi_master_get_devdata(master); |
| 649 | 649 | ||
| 650 | if (spfi->tx_ch) | 650 | if (spfi->tx_ch) |
| 651 | dma_release_channel(spfi->tx_ch); | 651 | dma_release_channel(spfi->tx_ch); |
| 652 | if (spfi->rx_ch) | 652 | if (spfi->rx_ch) |
| 653 | dma_release_channel(spfi->rx_ch); | 653 | dma_release_channel(spfi->rx_ch); |
| 654 | 654 | ||
| 655 | pm_runtime_disable(spfi->dev); | 655 | pm_runtime_disable(spfi->dev); |
| 656 | if (!pm_runtime_status_suspended(spfi->dev)) { | 656 | if (!pm_runtime_status_suspended(spfi->dev)) { |
| 657 | clk_disable_unprepare(spfi->spfi_clk); | 657 | clk_disable_unprepare(spfi->spfi_clk); |
| 658 | clk_disable_unprepare(spfi->sys_clk); | 658 | clk_disable_unprepare(spfi->sys_clk); |
| 659 | } | 659 | } |
| 660 | 660 | ||
| 661 | spi_master_put(master); | 661 | spi_master_put(master); |
| 662 | 662 | ||
| 663 | return 0; | 663 | return 0; |
| 664 | } | 664 | } |
| 665 | 665 | ||
| 666 | #ifdef CONFIG_PM_RUNTIME | 666 | #ifdef CONFIG_PM |
| 667 | static int img_spfi_runtime_suspend(struct device *dev) | 667 | static int img_spfi_runtime_suspend(struct device *dev) |
| 668 | { | 668 | { |
| 669 | struct spi_master *master = dev_get_drvdata(dev); | 669 | struct spi_master *master = dev_get_drvdata(dev); |
| 670 | struct img_spfi *spfi = spi_master_get_devdata(master); | 670 | struct img_spfi *spfi = spi_master_get_devdata(master); |
| 671 | 671 | ||
| 672 | clk_disable_unprepare(spfi->spfi_clk); | 672 | clk_disable_unprepare(spfi->spfi_clk); |
| 673 | clk_disable_unprepare(spfi->sys_clk); | 673 | clk_disable_unprepare(spfi->sys_clk); |
| 674 | 674 | ||
| 675 | return 0; | 675 | return 0; |
| 676 | } | 676 | } |
| 677 | 677 | ||
| 678 | static int img_spfi_runtime_resume(struct device *dev) | 678 | static int img_spfi_runtime_resume(struct device *dev) |
| 679 | { | 679 | { |
| 680 | struct spi_master *master = dev_get_drvdata(dev); | 680 | struct spi_master *master = dev_get_drvdata(dev); |
| 681 | struct img_spfi *spfi = spi_master_get_devdata(master); | 681 | struct img_spfi *spfi = spi_master_get_devdata(master); |
| 682 | int ret; | 682 | int ret; |
| 683 | 683 | ||
| 684 | ret = clk_prepare_enable(spfi->sys_clk); | 684 | ret = clk_prepare_enable(spfi->sys_clk); |
| 685 | if (ret) | 685 | if (ret) |
| 686 | return ret; | 686 | return ret; |
| 687 | ret = clk_prepare_enable(spfi->spfi_clk); | 687 | ret = clk_prepare_enable(spfi->spfi_clk); |
| 688 | if (ret) { | 688 | if (ret) { |
| 689 | clk_disable_unprepare(spfi->sys_clk); | 689 | clk_disable_unprepare(spfi->sys_clk); |
| 690 | return ret; | 690 | return ret; |
| 691 | } | 691 | } |
| 692 | 692 | ||
| 693 | return 0; | 693 | return 0; |
| 694 | } | 694 | } |
| 695 | #endif /* CONFIG_PM_RUNTIME */ | 695 | #endif /* CONFIG_PM */ |
| 696 | 696 | ||
| 697 | #ifdef CONFIG_PM_SLEEP | 697 | #ifdef CONFIG_PM_SLEEP |
| 698 | static int img_spfi_suspend(struct device *dev) | 698 | static int img_spfi_suspend(struct device *dev) |
| 699 | { | 699 | { |
| 700 | struct spi_master *master = dev_get_drvdata(dev); | 700 | struct spi_master *master = dev_get_drvdata(dev); |
| 701 | 701 | ||
| 702 | return spi_master_suspend(master); | 702 | return spi_master_suspend(master); |
| 703 | } | 703 | } |
| 704 | 704 | ||
| 705 | static int img_spfi_resume(struct device *dev) | 705 | static int img_spfi_resume(struct device *dev) |
| 706 | { | 706 | { |
| 707 | struct spi_master *master = dev_get_drvdata(dev); | 707 | struct spi_master *master = dev_get_drvdata(dev); |
| 708 | struct img_spfi *spfi = spi_master_get_devdata(master); | 708 | struct img_spfi *spfi = spi_master_get_devdata(master); |
| 709 | int ret; | 709 | int ret; |
| 710 | 710 | ||
| 711 | ret = pm_runtime_get_sync(dev); | 711 | ret = pm_runtime_get_sync(dev); |
| 712 | if (ret) | 712 | if (ret) |
| 713 | return ret; | 713 | return ret; |
| 714 | spfi_reset(spfi); | 714 | spfi_reset(spfi); |
| 715 | pm_runtime_put(dev); | 715 | pm_runtime_put(dev); |
| 716 | 716 | ||
| 717 | return spi_master_resume(master); | 717 | return spi_master_resume(master); |
| 718 | } | 718 | } |
| 719 | #endif /* CONFIG_PM_SLEEP */ | 719 | #endif /* CONFIG_PM_SLEEP */ |
| 720 | 720 | ||
| 721 | static const struct dev_pm_ops img_spfi_pm_ops = { | 721 | static const struct dev_pm_ops img_spfi_pm_ops = { |
| 722 | SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume, | 722 | SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume, |
| 723 | NULL) | 723 | NULL) |
| 724 | SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume) | 724 | SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume) |
| 725 | }; | 725 | }; |
| 726 | 726 | ||
| 727 | static const struct of_device_id img_spfi_of_match[] = { | 727 | static const struct of_device_id img_spfi_of_match[] = { |
| 728 | { .compatible = "img,spfi", }, | 728 | { .compatible = "img,spfi", }, |
| 729 | { }, | 729 | { }, |
| 730 | }; | 730 | }; |
| 731 | MODULE_DEVICE_TABLE(of, img_spfi_of_match); | 731 | MODULE_DEVICE_TABLE(of, img_spfi_of_match); |
| 732 | 732 | ||
| 733 | static struct platform_driver img_spfi_driver = { | 733 | static struct platform_driver img_spfi_driver = { |
| 734 | .driver = { | 734 | .driver = { |
| 735 | .name = "img-spfi", | 735 | .name = "img-spfi", |
| 736 | .pm = &img_spfi_pm_ops, | 736 | .pm = &img_spfi_pm_ops, |
| 737 | .of_match_table = of_match_ptr(img_spfi_of_match), | 737 | .of_match_table = of_match_ptr(img_spfi_of_match), |
| 738 | }, | 738 | }, |
| 739 | .probe = img_spfi_probe, | 739 | .probe = img_spfi_probe, |
| 740 | .remove = img_spfi_remove, | 740 | .remove = img_spfi_remove, |
| 741 | }; | 741 | }; |
| 742 | module_platform_driver(img_spfi_driver); | 742 | module_platform_driver(img_spfi_driver); |
| 743 | 743 | ||
| 744 | MODULE_DESCRIPTION("IMG SPFI controller driver"); | 744 | MODULE_DESCRIPTION("IMG SPFI controller driver"); |
| 745 | MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); | 745 | MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); |
| 746 | MODULE_LICENSE("GPL v2"); | 746 | MODULE_LICENSE("GPL v2"); |
| 747 | 747 |
drivers/spi/spi-meson-spifc.c
| 1 | /* | 1 | /* |
| 2 | * Driver for Amlogic Meson SPI flash controller (SPIFC) | 2 | * Driver for Amlogic Meson SPI flash controller (SPIFC) |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | 4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
| 8 | * version 2 as published by the Free Software Foundation. | 8 | * version 2 as published by the Free Software Foundation. |
| 9 | * | 9 | * |
| 10 | * You should have received a copy of the GNU General Public License | 10 | * You should have received a copy of the GNU General Public License |
| 11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/clk.h> | 14 | #include <linux/clk.h> |
| 15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
| 16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> | 20 | #include <linux/of.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/pm_runtime.h> | 22 | #include <linux/pm_runtime.h> |
| 23 | #include <linux/regmap.h> | 23 | #include <linux/regmap.h> |
| 24 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
| 25 | #include <linux/types.h> | 25 | #include <linux/types.h> |
| 26 | 26 | ||
| 27 | /* register map */ | 27 | /* register map */ |
| 28 | #define REG_CMD 0x00 | 28 | #define REG_CMD 0x00 |
| 29 | #define REG_ADDR 0x04 | 29 | #define REG_ADDR 0x04 |
| 30 | #define REG_CTRL 0x08 | 30 | #define REG_CTRL 0x08 |
| 31 | #define REG_CTRL1 0x0c | 31 | #define REG_CTRL1 0x0c |
| 32 | #define REG_STATUS 0x10 | 32 | #define REG_STATUS 0x10 |
| 33 | #define REG_CTRL2 0x14 | 33 | #define REG_CTRL2 0x14 |
| 34 | #define REG_CLOCK 0x18 | 34 | #define REG_CLOCK 0x18 |
| 35 | #define REG_USER 0x1c | 35 | #define REG_USER 0x1c |
| 36 | #define REG_USER1 0x20 | 36 | #define REG_USER1 0x20 |
| 37 | #define REG_USER2 0x24 | 37 | #define REG_USER2 0x24 |
| 38 | #define REG_USER3 0x28 | 38 | #define REG_USER3 0x28 |
| 39 | #define REG_USER4 0x2c | 39 | #define REG_USER4 0x2c |
| 40 | #define REG_SLAVE 0x30 | 40 | #define REG_SLAVE 0x30 |
| 41 | #define REG_SLAVE1 0x34 | 41 | #define REG_SLAVE1 0x34 |
| 42 | #define REG_SLAVE2 0x38 | 42 | #define REG_SLAVE2 0x38 |
| 43 | #define REG_SLAVE3 0x3c | 43 | #define REG_SLAVE3 0x3c |
| 44 | #define REG_C0 0x40 | 44 | #define REG_C0 0x40 |
| 45 | #define REG_B8 0x60 | 45 | #define REG_B8 0x60 |
| 46 | #define REG_MAX 0x7c | 46 | #define REG_MAX 0x7c |
| 47 | 47 | ||
| 48 | /* register fields */ | 48 | /* register fields */ |
| 49 | #define CMD_USER BIT(18) | 49 | #define CMD_USER BIT(18) |
| 50 | #define CTRL_ENABLE_AHB BIT(17) | 50 | #define CTRL_ENABLE_AHB BIT(17) |
| 51 | #define CLOCK_SOURCE BIT(31) | 51 | #define CLOCK_SOURCE BIT(31) |
| 52 | #define CLOCK_DIV_SHIFT 12 | 52 | #define CLOCK_DIV_SHIFT 12 |
| 53 | #define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT) | 53 | #define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT) |
| 54 | #define CLOCK_CNT_HIGH_SHIFT 6 | 54 | #define CLOCK_CNT_HIGH_SHIFT 6 |
| 55 | #define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT) | 55 | #define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT) |
| 56 | #define CLOCK_CNT_LOW_SHIFT 0 | 56 | #define CLOCK_CNT_LOW_SHIFT 0 |
| 57 | #define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT) | 57 | #define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT) |
| 58 | #define USER_DIN_EN_MS BIT(0) | 58 | #define USER_DIN_EN_MS BIT(0) |
| 59 | #define USER_CMP_MODE BIT(2) | 59 | #define USER_CMP_MODE BIT(2) |
| 60 | #define USER_UC_DOUT_SEL BIT(27) | 60 | #define USER_UC_DOUT_SEL BIT(27) |
| 61 | #define USER_UC_DIN_SEL BIT(28) | 61 | #define USER_UC_DIN_SEL BIT(28) |
| 62 | #define USER_UC_MASK ((BIT(5) - 1) << 27) | 62 | #define USER_UC_MASK ((BIT(5) - 1) << 27) |
| 63 | #define USER1_BN_UC_DOUT_SHIFT 17 | 63 | #define USER1_BN_UC_DOUT_SHIFT 17 |
| 64 | #define USER1_BN_UC_DOUT_MASK (0xff << 16) | 64 | #define USER1_BN_UC_DOUT_MASK (0xff << 16) |
| 65 | #define USER1_BN_UC_DIN_SHIFT 8 | 65 | #define USER1_BN_UC_DIN_SHIFT 8 |
| 66 | #define USER1_BN_UC_DIN_MASK (0xff << 8) | 66 | #define USER1_BN_UC_DIN_MASK (0xff << 8) |
| 67 | #define USER4_CS_ACT BIT(30) | 67 | #define USER4_CS_ACT BIT(30) |
| 68 | #define SLAVE_TRST_DONE BIT(4) | 68 | #define SLAVE_TRST_DONE BIT(4) |
| 69 | #define SLAVE_OP_MODE BIT(30) | 69 | #define SLAVE_OP_MODE BIT(30) |
| 70 | #define SLAVE_SW_RST BIT(31) | 70 | #define SLAVE_SW_RST BIT(31) |
| 71 | 71 | ||
| 72 | #define SPIFC_BUFFER_SIZE 64 | 72 | #define SPIFC_BUFFER_SIZE 64 |
| 73 | 73 | ||
| 74 | /** | 74 | /** |
| 75 | * struct meson_spifc | 75 | * struct meson_spifc |
| 76 | * @master: the SPI master | 76 | * @master: the SPI master |
| 77 | * @regmap: regmap for device registers | 77 | * @regmap: regmap for device registers |
| 78 | * @clk: input clock of the built-in baud rate generator | 78 | * @clk: input clock of the built-in baud rate generator |
| 79 | * @device: the device structure | 79 | * @device: the device structure |
| 80 | */ | 80 | */ |
| 81 | struct meson_spifc { | 81 | struct meson_spifc { |
| 82 | struct spi_master *master; | 82 | struct spi_master *master; |
| 83 | struct regmap *regmap; | 83 | struct regmap *regmap; |
| 84 | struct clk *clk; | 84 | struct clk *clk; |
| 85 | struct device *dev; | 85 | struct device *dev; |
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | static struct regmap_config spifc_regmap_config = { | 88 | static struct regmap_config spifc_regmap_config = { |
| 89 | .reg_bits = 32, | 89 | .reg_bits = 32, |
| 90 | .val_bits = 32, | 90 | .val_bits = 32, |
| 91 | .reg_stride = 4, | 91 | .reg_stride = 4, |
| 92 | .max_register = REG_MAX, | 92 | .max_register = REG_MAX, |
| 93 | }; | 93 | }; |
| 94 | 94 | ||
| 95 | /** | 95 | /** |
| 96 | * meson_spifc_wait_ready() - wait for the current operation to terminate | 96 | * meson_spifc_wait_ready() - wait for the current operation to terminate |
| 97 | * @spifc: the Meson SPI device | 97 | * @spifc: the Meson SPI device |
| 98 | * Return: 0 on success, a negative value on error | 98 | * Return: 0 on success, a negative value on error |
| 99 | */ | 99 | */ |
| 100 | static int meson_spifc_wait_ready(struct meson_spifc *spifc) | 100 | static int meson_spifc_wait_ready(struct meson_spifc *spifc) |
| 101 | { | 101 | { |
| 102 | unsigned long deadline = jiffies + msecs_to_jiffies(5); | 102 | unsigned long deadline = jiffies + msecs_to_jiffies(5); |
| 103 | u32 data; | 103 | u32 data; |
| 104 | 104 | ||
| 105 | do { | 105 | do { |
| 106 | regmap_read(spifc->regmap, REG_SLAVE, &data); | 106 | regmap_read(spifc->regmap, REG_SLAVE, &data); |
| 107 | if (data & SLAVE_TRST_DONE) | 107 | if (data & SLAVE_TRST_DONE) |
| 108 | return 0; | 108 | return 0; |
| 109 | cond_resched(); | 109 | cond_resched(); |
| 110 | } while (!time_after(jiffies, deadline)); | 110 | } while (!time_after(jiffies, deadline)); |
| 111 | 111 | ||
| 112 | return -ETIMEDOUT; | 112 | return -ETIMEDOUT; |
| 113 | } | 113 | } |
| 114 | 114 | ||
| 115 | /** | 115 | /** |
| 116 | * meson_spifc_drain_buffer() - copy data from device buffer to memory | 116 | * meson_spifc_drain_buffer() - copy data from device buffer to memory |
| 117 | * @spifc: the Meson SPI device | 117 | * @spifc: the Meson SPI device |
| 118 | * @buf: the destination buffer | 118 | * @buf: the destination buffer |
| 119 | * @len: number of bytes to copy | 119 | * @len: number of bytes to copy |
| 120 | */ | 120 | */ |
| 121 | static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf, | 121 | static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf, |
| 122 | int len) | 122 | int len) |
| 123 | { | 123 | { |
| 124 | u32 data; | 124 | u32 data; |
| 125 | int i = 0; | 125 | int i = 0; |
| 126 | 126 | ||
| 127 | while (i < len) { | 127 | while (i < len) { |
| 128 | regmap_read(spifc->regmap, REG_C0 + i, &data); | 128 | regmap_read(spifc->regmap, REG_C0 + i, &data); |
| 129 | 129 | ||
| 130 | if (len - i >= 4) { | 130 | if (len - i >= 4) { |
| 131 | *((u32 *)buf) = data; | 131 | *((u32 *)buf) = data; |
| 132 | buf += 4; | 132 | buf += 4; |
| 133 | } else { | 133 | } else { |
| 134 | memcpy(buf, &data, len - i); | 134 | memcpy(buf, &data, len - i); |
| 135 | break; | 135 | break; |
| 136 | } | 136 | } |
| 137 | i += 4; | 137 | i += 4; |
| 138 | } | 138 | } |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | /** | 141 | /** |
| 142 | * meson_spifc_fill_buffer() - copy data from memory to device buffer | 142 | * meson_spifc_fill_buffer() - copy data from memory to device buffer |
| 143 | * @spifc: the Meson SPI device | 143 | * @spifc: the Meson SPI device |
| 144 | * @buf: the source buffer | 144 | * @buf: the source buffer |
| 145 | * @len: number of bytes to copy | 145 | * @len: number of bytes to copy |
| 146 | */ | 146 | */ |
| 147 | static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf, | 147 | static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf, |
| 148 | int len) | 148 | int len) |
| 149 | { | 149 | { |
| 150 | u32 data; | 150 | u32 data; |
| 151 | int i = 0; | 151 | int i = 0; |
| 152 | 152 | ||
| 153 | while (i < len) { | 153 | while (i < len) { |
| 154 | if (len - i >= 4) | 154 | if (len - i >= 4) |
| 155 | data = *(u32 *)buf; | 155 | data = *(u32 *)buf; |
| 156 | else | 156 | else |
| 157 | memcpy(&data, buf, len - i); | 157 | memcpy(&data, buf, len - i); |
| 158 | 158 | ||
| 159 | regmap_write(spifc->regmap, REG_C0 + i, data); | 159 | regmap_write(spifc->regmap, REG_C0 + i, data); |
| 160 | 160 | ||
| 161 | buf += 4; | 161 | buf += 4; |
| 162 | i += 4; | 162 | i += 4; |
| 163 | } | 163 | } |
| 164 | } | 164 | } |
| 165 | 165 | ||
| 166 | /** | 166 | /** |
| 167 | * meson_spifc_setup_speed() - program the clock divider | 167 | * meson_spifc_setup_speed() - program the clock divider |
| 168 | * @spifc: the Meson SPI device | 168 | * @spifc: the Meson SPI device |
| 169 | * @speed: desired speed in Hz | 169 | * @speed: desired speed in Hz |
| 170 | */ | 170 | */ |
| 171 | static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed) | 171 | static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed) |
| 172 | { | 172 | { |
| 173 | unsigned long parent, value; | 173 | unsigned long parent, value; |
| 174 | int n; | 174 | int n; |
| 175 | 175 | ||
| 176 | parent = clk_get_rate(spifc->clk); | 176 | parent = clk_get_rate(spifc->clk); |
| 177 | n = max_t(int, parent / speed - 1, 1); | 177 | n = max_t(int, parent / speed - 1, 1); |
| 178 | 178 | ||
| 179 | dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent, | 179 | dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent, |
| 180 | speed, n); | 180 | speed, n); |
| 181 | 181 | ||
| 182 | value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK; | 182 | value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK; |
| 183 | value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK; | 183 | value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK; |
| 184 | value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) & | 184 | value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) & |
| 185 | CLOCK_CNT_HIGH_MASK; | 185 | CLOCK_CNT_HIGH_MASK; |
| 186 | 186 | ||
| 187 | regmap_write(spifc->regmap, REG_CLOCK, value); | 187 | regmap_write(spifc->regmap, REG_CLOCK, value); |
| 188 | } | 188 | } |
| 189 | 189 | ||
| 190 | /** | 190 | /** |
| 191 | * meson_spifc_txrx() - transfer a chunk of data | 191 | * meson_spifc_txrx() - transfer a chunk of data |
| 192 | * @spifc: the Meson SPI device | 192 | * @spifc: the Meson SPI device |
| 193 | * @xfer: the current SPI transfer | 193 | * @xfer: the current SPI transfer |
| 194 | * @offset: offset of the data to transfer | 194 | * @offset: offset of the data to transfer |
| 195 | * @len: length of the data to transfer | 195 | * @len: length of the data to transfer |
| 196 | * @last_xfer: whether this is the last transfer of the message | 196 | * @last_xfer: whether this is the last transfer of the message |
| 197 | * @last_chunk: whether this is the last chunk of the transfer | 197 | * @last_chunk: whether this is the last chunk of the transfer |
| 198 | * Return: 0 on success, a negative value on error | 198 | * Return: 0 on success, a negative value on error |
| 199 | */ | 199 | */ |
| 200 | static int meson_spifc_txrx(struct meson_spifc *spifc, | 200 | static int meson_spifc_txrx(struct meson_spifc *spifc, |
| 201 | struct spi_transfer *xfer, | 201 | struct spi_transfer *xfer, |
| 202 | int offset, int len, bool last_xfer, | 202 | int offset, int len, bool last_xfer, |
| 203 | bool last_chunk) | 203 | bool last_chunk) |
| 204 | { | 204 | { |
| 205 | bool keep_cs = true; | 205 | bool keep_cs = true; |
| 206 | int ret; | 206 | int ret; |
| 207 | 207 | ||
| 208 | if (xfer->tx_buf) | 208 | if (xfer->tx_buf) |
| 209 | meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len); | 209 | meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len); |
| 210 | 210 | ||
| 211 | /* enable DOUT stage */ | 211 | /* enable DOUT stage */ |
| 212 | regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK, | 212 | regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK, |
| 213 | USER_UC_DOUT_SEL); | 213 | USER_UC_DOUT_SEL); |
| 214 | regmap_write(spifc->regmap, REG_USER1, | 214 | regmap_write(spifc->regmap, REG_USER1, |
| 215 | (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT); | 215 | (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT); |
| 216 | 216 | ||
| 217 | /* enable data input during DOUT */ | 217 | /* enable data input during DOUT */ |
| 218 | regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS, | 218 | regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS, |
| 219 | USER_DIN_EN_MS); | 219 | USER_DIN_EN_MS); |
| 220 | 220 | ||
| 221 | if (last_chunk) { | 221 | if (last_chunk) { |
| 222 | if (last_xfer) | 222 | if (last_xfer) |
| 223 | keep_cs = xfer->cs_change; | 223 | keep_cs = xfer->cs_change; |
| 224 | else | 224 | else |
| 225 | keep_cs = !xfer->cs_change; | 225 | keep_cs = !xfer->cs_change; |
| 226 | } | 226 | } |
| 227 | 227 | ||
| 228 | regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT, | 228 | regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT, |
| 229 | keep_cs ? USER4_CS_ACT : 0); | 229 | keep_cs ? USER4_CS_ACT : 0); |
| 230 | 230 | ||
| 231 | /* clear transition done bit */ | 231 | /* clear transition done bit */ |
| 232 | regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0); | 232 | regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0); |
| 233 | /* start transfer */ | 233 | /* start transfer */ |
| 234 | regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER); | 234 | regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER); |
| 235 | 235 | ||
| 236 | ret = meson_spifc_wait_ready(spifc); | 236 | ret = meson_spifc_wait_ready(spifc); |
| 237 | 237 | ||
| 238 | if (!ret && xfer->rx_buf) | 238 | if (!ret && xfer->rx_buf) |
| 239 | meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len); | 239 | meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len); |
| 240 | 240 | ||
| 241 | return ret; | 241 | return ret; |
| 242 | } | 242 | } |
| 243 | 243 | ||
| 244 | /** | 244 | /** |
| 245 | * meson_spifc_transfer_one() - perform a single transfer | 245 | * meson_spifc_transfer_one() - perform a single transfer |
| 246 | * @master: the SPI master | 246 | * @master: the SPI master |
| 247 | * @spi: the SPI device | 247 | * @spi: the SPI device |
| 248 | * @xfer: the current SPI transfer | 248 | * @xfer: the current SPI transfer |
| 249 | * Return: 0 on success, a negative value on error | 249 | * Return: 0 on success, a negative value on error |
| 250 | */ | 250 | */ |
| 251 | static int meson_spifc_transfer_one(struct spi_master *master, | 251 | static int meson_spifc_transfer_one(struct spi_master *master, |
| 252 | struct spi_device *spi, | 252 | struct spi_device *spi, |
| 253 | struct spi_transfer *xfer) | 253 | struct spi_transfer *xfer) |
| 254 | { | 254 | { |
| 255 | struct meson_spifc *spifc = spi_master_get_devdata(master); | 255 | struct meson_spifc *spifc = spi_master_get_devdata(master); |
| 256 | int len, done = 0, ret = 0; | 256 | int len, done = 0, ret = 0; |
| 257 | 257 | ||
| 258 | meson_spifc_setup_speed(spifc, xfer->speed_hz); | 258 | meson_spifc_setup_speed(spifc, xfer->speed_hz); |
| 259 | 259 | ||
| 260 | regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0); | 260 | regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0); |
| 261 | 261 | ||
| 262 | while (done < xfer->len && !ret) { | 262 | while (done < xfer->len && !ret) { |
| 263 | len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE); | 263 | len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE); |
| 264 | ret = meson_spifc_txrx(spifc, xfer, done, len, | 264 | ret = meson_spifc_txrx(spifc, xfer, done, len, |
| 265 | spi_transfer_is_last(master, xfer), | 265 | spi_transfer_is_last(master, xfer), |
| 266 | done + len >= xfer->len); | 266 | done + len >= xfer->len); |
| 267 | done += len; | 267 | done += len; |
| 268 | } | 268 | } |
| 269 | 269 | ||
| 270 | regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, | 270 | regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, |
| 271 | CTRL_ENABLE_AHB); | 271 | CTRL_ENABLE_AHB); |
| 272 | 272 | ||
| 273 | return ret; | 273 | return ret; |
| 274 | } | 274 | } |
| 275 | 275 | ||
| 276 | /** | 276 | /** |
| 277 | * meson_spifc_hw_init() - reset and initialize the SPI controller | 277 | * meson_spifc_hw_init() - reset and initialize the SPI controller |
| 278 | * @spifc: the Meson SPI device | 278 | * @spifc: the Meson SPI device |
| 279 | */ | 279 | */ |
| 280 | static void meson_spifc_hw_init(struct meson_spifc *spifc) | 280 | static void meson_spifc_hw_init(struct meson_spifc *spifc) |
| 281 | { | 281 | { |
| 282 | /* reset device */ | 282 | /* reset device */ |
| 283 | regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST, | 283 | regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST, |
| 284 | SLAVE_SW_RST); | 284 | SLAVE_SW_RST); |
| 285 | /* disable compatible mode */ | 285 | /* disable compatible mode */ |
| 286 | regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0); | 286 | regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0); |
| 287 | /* set master mode */ | 287 | /* set master mode */ |
| 288 | regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0); | 288 | regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0); |
| 289 | } | 289 | } |
| 290 | 290 | ||
| 291 | static int meson_spifc_probe(struct platform_device *pdev) | 291 | static int meson_spifc_probe(struct platform_device *pdev) |
| 292 | { | 292 | { |
| 293 | struct spi_master *master; | 293 | struct spi_master *master; |
| 294 | struct meson_spifc *spifc; | 294 | struct meson_spifc *spifc; |
| 295 | struct resource *res; | 295 | struct resource *res; |
| 296 | void __iomem *base; | 296 | void __iomem *base; |
| 297 | unsigned int rate; | 297 | unsigned int rate; |
| 298 | int ret = 0; | 298 | int ret = 0; |
| 299 | 299 | ||
| 300 | master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc)); | 300 | master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc)); |
| 301 | if (!master) | 301 | if (!master) |
| 302 | return -ENOMEM; | 302 | return -ENOMEM; |
| 303 | 303 | ||
| 304 | platform_set_drvdata(pdev, master); | 304 | platform_set_drvdata(pdev, master); |
| 305 | 305 | ||
| 306 | spifc = spi_master_get_devdata(master); | 306 | spifc = spi_master_get_devdata(master); |
| 307 | spifc->dev = &pdev->dev; | 307 | spifc->dev = &pdev->dev; |
| 308 | 308 | ||
| 309 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 309 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 310 | base = devm_ioremap_resource(spifc->dev, res); | 310 | base = devm_ioremap_resource(spifc->dev, res); |
| 311 | if (IS_ERR(base)) { | 311 | if (IS_ERR(base)) { |
| 312 | ret = PTR_ERR(base); | 312 | ret = PTR_ERR(base); |
| 313 | goto out_err; | 313 | goto out_err; |
| 314 | } | 314 | } |
| 315 | 315 | ||
| 316 | spifc->regmap = devm_regmap_init_mmio(spifc->dev, base, | 316 | spifc->regmap = devm_regmap_init_mmio(spifc->dev, base, |
| 317 | &spifc_regmap_config); | 317 | &spifc_regmap_config); |
| 318 | if (IS_ERR(spifc->regmap)) { | 318 | if (IS_ERR(spifc->regmap)) { |
| 319 | ret = PTR_ERR(spifc->regmap); | 319 | ret = PTR_ERR(spifc->regmap); |
| 320 | goto out_err; | 320 | goto out_err; |
| 321 | } | 321 | } |
| 322 | 322 | ||
| 323 | spifc->clk = devm_clk_get(spifc->dev, NULL); | 323 | spifc->clk = devm_clk_get(spifc->dev, NULL); |
| 324 | if (IS_ERR(spifc->clk)) { | 324 | if (IS_ERR(spifc->clk)) { |
| 325 | dev_err(spifc->dev, "missing clock\n"); | 325 | dev_err(spifc->dev, "missing clock\n"); |
| 326 | ret = PTR_ERR(spifc->clk); | 326 | ret = PTR_ERR(spifc->clk); |
| 327 | goto out_err; | 327 | goto out_err; |
| 328 | } | 328 | } |
| 329 | 329 | ||
| 330 | ret = clk_prepare_enable(spifc->clk); | 330 | ret = clk_prepare_enable(spifc->clk); |
| 331 | if (ret) { | 331 | if (ret) { |
| 332 | dev_err(spifc->dev, "can't prepare clock\n"); | 332 | dev_err(spifc->dev, "can't prepare clock\n"); |
| 333 | goto out_err; | 333 | goto out_err; |
| 334 | } | 334 | } |
| 335 | 335 | ||
| 336 | rate = clk_get_rate(spifc->clk); | 336 | rate = clk_get_rate(spifc->clk); |
| 337 | 337 | ||
| 338 | master->num_chipselect = 1; | 338 | master->num_chipselect = 1; |
| 339 | master->dev.of_node = pdev->dev.of_node; | 339 | master->dev.of_node = pdev->dev.of_node; |
| 340 | master->bits_per_word_mask = SPI_BPW_MASK(8); | 340 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
| 341 | master->auto_runtime_pm = true; | 341 | master->auto_runtime_pm = true; |
| 342 | master->transfer_one = meson_spifc_transfer_one; | 342 | master->transfer_one = meson_spifc_transfer_one; |
| 343 | master->min_speed_hz = rate >> 6; | 343 | master->min_speed_hz = rate >> 6; |
| 344 | master->max_speed_hz = rate >> 1; | 344 | master->max_speed_hz = rate >> 1; |
| 345 | 345 | ||
| 346 | meson_spifc_hw_init(spifc); | 346 | meson_spifc_hw_init(spifc); |
| 347 | 347 | ||
| 348 | pm_runtime_set_active(spifc->dev); | 348 | pm_runtime_set_active(spifc->dev); |
| 349 | pm_runtime_enable(spifc->dev); | 349 | pm_runtime_enable(spifc->dev); |
| 350 | 350 | ||
| 351 | ret = devm_spi_register_master(spifc->dev, master); | 351 | ret = devm_spi_register_master(spifc->dev, master); |
| 352 | if (ret) { | 352 | if (ret) { |
| 353 | dev_err(spifc->dev, "failed to register spi master\n"); | 353 | dev_err(spifc->dev, "failed to register spi master\n"); |
| 354 | goto out_clk; | 354 | goto out_clk; |
| 355 | } | 355 | } |
| 356 | 356 | ||
| 357 | return 0; | 357 | return 0; |
| 358 | out_clk: | 358 | out_clk: |
| 359 | clk_disable_unprepare(spifc->clk); | 359 | clk_disable_unprepare(spifc->clk); |
| 360 | out_err: | 360 | out_err: |
| 361 | spi_master_put(master); | 361 | spi_master_put(master); |
| 362 | return ret; | 362 | return ret; |
| 363 | } | 363 | } |
| 364 | 364 | ||
| 365 | static int meson_spifc_remove(struct platform_device *pdev) | 365 | static int meson_spifc_remove(struct platform_device *pdev) |
| 366 | { | 366 | { |
| 367 | struct spi_master *master = platform_get_drvdata(pdev); | 367 | struct spi_master *master = platform_get_drvdata(pdev); |
| 368 | struct meson_spifc *spifc = spi_master_get_devdata(master); | 368 | struct meson_spifc *spifc = spi_master_get_devdata(master); |
| 369 | 369 | ||
| 370 | pm_runtime_get_sync(&pdev->dev); | 370 | pm_runtime_get_sync(&pdev->dev); |
| 371 | clk_disable_unprepare(spifc->clk); | 371 | clk_disable_unprepare(spifc->clk); |
| 372 | pm_runtime_disable(&pdev->dev); | 372 | pm_runtime_disable(&pdev->dev); |
| 373 | 373 | ||
| 374 | return 0; | 374 | return 0; |
| 375 | } | 375 | } |
| 376 | 376 | ||
| 377 | #ifdef CONFIG_PM_SLEEP | 377 | #ifdef CONFIG_PM_SLEEP |
| 378 | static int meson_spifc_suspend(struct device *dev) | 378 | static int meson_spifc_suspend(struct device *dev) |
| 379 | { | 379 | { |
| 380 | struct spi_master *master = dev_get_drvdata(dev); | 380 | struct spi_master *master = dev_get_drvdata(dev); |
| 381 | struct meson_spifc *spifc = spi_master_get_devdata(master); | 381 | struct meson_spifc *spifc = spi_master_get_devdata(master); |
| 382 | int ret; | 382 | int ret; |
| 383 | 383 | ||
| 384 | ret = spi_master_suspend(master); | 384 | ret = spi_master_suspend(master); |
| 385 | if (ret) | 385 | if (ret) |
| 386 | return ret; | 386 | return ret; |
| 387 | 387 | ||
| 388 | if (!pm_runtime_suspended(dev)) | 388 | if (!pm_runtime_suspended(dev)) |
| 389 | clk_disable_unprepare(spifc->clk); | 389 | clk_disable_unprepare(spifc->clk); |
| 390 | 390 | ||
| 391 | return 0; | 391 | return 0; |
| 392 | } | 392 | } |
| 393 | 393 | ||
| 394 | static int meson_spifc_resume(struct device *dev) | 394 | static int meson_spifc_resume(struct device *dev) |
| 395 | { | 395 | { |
| 396 | struct spi_master *master = dev_get_drvdata(dev); | 396 | struct spi_master *master = dev_get_drvdata(dev); |
| 397 | struct meson_spifc *spifc = spi_master_get_devdata(master); | 397 | struct meson_spifc *spifc = spi_master_get_devdata(master); |
| 398 | int ret; | 398 | int ret; |
| 399 | 399 | ||
| 400 | if (!pm_runtime_suspended(dev)) { | 400 | if (!pm_runtime_suspended(dev)) { |
| 401 | ret = clk_prepare_enable(spifc->clk); | 401 | ret = clk_prepare_enable(spifc->clk); |
| 402 | if (ret) | 402 | if (ret) |
| 403 | return ret; | 403 | return ret; |
| 404 | } | 404 | } |
| 405 | 405 | ||
| 406 | meson_spifc_hw_init(spifc); | 406 | meson_spifc_hw_init(spifc); |
| 407 | 407 | ||
| 408 | ret = spi_master_resume(master); | 408 | ret = spi_master_resume(master); |
| 409 | if (ret) | 409 | if (ret) |
| 410 | clk_disable_unprepare(spifc->clk); | 410 | clk_disable_unprepare(spifc->clk); |
| 411 | 411 | ||
| 412 | return ret; | 412 | return ret; |
| 413 | } | 413 | } |
| 414 | #endif /* CONFIG_PM_SLEEP */ | 414 | #endif /* CONFIG_PM_SLEEP */ |
| 415 | 415 | ||
| 416 | #ifdef CONFIG_PM_RUNTIME | 416 | #ifdef CONFIG_PM |
| 417 | static int meson_spifc_runtime_suspend(struct device *dev) | 417 | static int meson_spifc_runtime_suspend(struct device *dev) |
| 418 | { | 418 | { |
| 419 | struct spi_master *master = dev_get_drvdata(dev); | 419 | struct spi_master *master = dev_get_drvdata(dev); |
| 420 | struct meson_spifc *spifc = spi_master_get_devdata(master); | 420 | struct meson_spifc *spifc = spi_master_get_devdata(master); |
| 421 | 421 | ||
| 422 | clk_disable_unprepare(spifc->clk); | 422 | clk_disable_unprepare(spifc->clk); |
| 423 | 423 | ||
| 424 | return 0; | 424 | return 0; |
| 425 | } | 425 | } |
| 426 | 426 | ||
| 427 | static int meson_spifc_runtime_resume(struct device *dev) | 427 | static int meson_spifc_runtime_resume(struct device *dev) |
| 428 | { | 428 | { |
| 429 | struct spi_master *master = dev_get_drvdata(dev); | 429 | struct spi_master *master = dev_get_drvdata(dev); |
| 430 | struct meson_spifc *spifc = spi_master_get_devdata(master); | 430 | struct meson_spifc *spifc = spi_master_get_devdata(master); |
| 431 | 431 | ||
| 432 | return clk_prepare_enable(spifc->clk); | 432 | return clk_prepare_enable(spifc->clk); |
| 433 | } | 433 | } |
| 434 | #endif /* CONFIG_PM_RUNTIME */ | 434 | #endif /* CONFIG_PM */ |
| 435 | 435 | ||
| 436 | static const struct dev_pm_ops meson_spifc_pm_ops = { | 436 | static const struct dev_pm_ops meson_spifc_pm_ops = { |
| 437 | SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume) | 437 | SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume) |
| 438 | SET_RUNTIME_PM_OPS(meson_spifc_runtime_suspend, | 438 | SET_RUNTIME_PM_OPS(meson_spifc_runtime_suspend, |
| 439 | meson_spifc_runtime_resume, | 439 | meson_spifc_runtime_resume, |
| 440 | NULL) | 440 | NULL) |
| 441 | }; | 441 | }; |
| 442 | 442 | ||
| 443 | static const struct of_device_id meson_spifc_dt_match[] = { | 443 | static const struct of_device_id meson_spifc_dt_match[] = { |
| 444 | { .compatible = "amlogic,meson6-spifc", }, | 444 | { .compatible = "amlogic,meson6-spifc", }, |
| 445 | { }, | 445 | { }, |
| 446 | }; | 446 | }; |
| 447 | 447 | ||
| 448 | static struct platform_driver meson_spifc_driver = { | 448 | static struct platform_driver meson_spifc_driver = { |
| 449 | .probe = meson_spifc_probe, | 449 | .probe = meson_spifc_probe, |
| 450 | .remove = meson_spifc_remove, | 450 | .remove = meson_spifc_remove, |
| 451 | .driver = { | 451 | .driver = { |
| 452 | .name = "meson-spifc", | 452 | .name = "meson-spifc", |
| 453 | .of_match_table = of_match_ptr(meson_spifc_dt_match), | 453 | .of_match_table = of_match_ptr(meson_spifc_dt_match), |
| 454 | .pm = &meson_spifc_pm_ops, | 454 | .pm = &meson_spifc_pm_ops, |
| 455 | }, | 455 | }, |
| 456 | }; | 456 | }; |
| 457 | 457 | ||
| 458 | module_platform_driver(meson_spifc_driver); | 458 | module_platform_driver(meson_spifc_driver); |
| 459 | 459 | ||
| 460 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); | 460 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); |
| 461 | MODULE_DESCRIPTION("Amlogic Meson SPIFC driver"); | 461 | MODULE_DESCRIPTION("Amlogic Meson SPIFC driver"); |
| 462 | MODULE_LICENSE("GPL v2"); | 462 | MODULE_LICENSE("GPL v2"); |
| 463 | 463 |
drivers/tty/serial/8250/8250_omap.c
| 1 | /* | 1 | /* |
| 2 | * 8250-core based driver for the OMAP internal UART | 2 | * 8250-core based driver for the OMAP internal UART |
| 3 | * | 3 | * |
| 4 | * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. | 4 | * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2014 Sebastian Andrzej Siewior | 6 | * Copyright (C) 2014 Sebastian Andrzej Siewior |
| 7 | * | 7 | * |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include <linux/device.h> | 10 | #include <linux/device.h> |
| 11 | #include <linux/io.h> | 11 | #include <linux/io.h> |
| 12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
| 13 | #include <linux/serial_8250.h> | 13 | #include <linux/serial_8250.h> |
| 14 | #include <linux/serial_core.h> | 14 | #include <linux/serial_core.h> |
| 15 | #include <linux/serial_reg.h> | 15 | #include <linux/serial_reg.h> |
| 16 | #include <linux/tty_flip.h> | 16 | #include <linux/tty_flip.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/slab.h> | 18 | #include <linux/slab.h> |
| 19 | #include <linux/of.h> | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_gpio.h> | 20 | #include <linux/of_gpio.h> |
| 21 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/pm_runtime.h> | 23 | #include <linux/pm_runtime.h> |
| 24 | #include <linux/console.h> | 24 | #include <linux/console.h> |
| 25 | #include <linux/pm_qos.h> | 25 | #include <linux/pm_qos.h> |
| 26 | #include <linux/dma-mapping.h> | 26 | #include <linux/dma-mapping.h> |
| 27 | 27 | ||
| 28 | #include "8250.h" | 28 | #include "8250.h" |
| 29 | 29 | ||
| 30 | #define DEFAULT_CLK_SPEED 48000000 | 30 | #define DEFAULT_CLK_SPEED 48000000 |
| 31 | 31 | ||
| 32 | #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) | 32 | #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) |
| 33 | #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) | 33 | #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) |
| 34 | #define OMAP_DMA_TX_KICK (1 << 2) | 34 | #define OMAP_DMA_TX_KICK (1 << 2) |
| 35 | 35 | ||
| 36 | #define OMAP_UART_FCR_RX_TRIG 6 | 36 | #define OMAP_UART_FCR_RX_TRIG 6 |
| 37 | #define OMAP_UART_FCR_TX_TRIG 4 | 37 | #define OMAP_UART_FCR_TX_TRIG 4 |
| 38 | 38 | ||
| 39 | /* SCR register bitmasks */ | 39 | /* SCR register bitmasks */ |
| 40 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | 40 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) |
| 41 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) | 41 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) |
| 42 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) | 42 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) |
| 43 | #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) | 43 | #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) |
| 44 | #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) | 44 | #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) |
| 45 | #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) | 45 | #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) |
| 46 | 46 | ||
| 47 | /* MVR register bitmasks */ | 47 | /* MVR register bitmasks */ |
| 48 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | 48 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 |
| 49 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | 49 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 |
| 50 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | 50 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 |
| 51 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | 51 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f |
| 52 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | 52 | #define OMAP_UART_MVR_MAJ_MASK 0x700 |
| 53 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | 53 | #define OMAP_UART_MVR_MAJ_SHIFT 8 |
| 54 | #define OMAP_UART_MVR_MIN_MASK 0x3f | 54 | #define OMAP_UART_MVR_MIN_MASK 0x3f |
| 55 | 55 | ||
| 56 | #define UART_TI752_TLR_TX 0 | 56 | #define UART_TI752_TLR_TX 0 |
| 57 | #define UART_TI752_TLR_RX 4 | 57 | #define UART_TI752_TLR_RX 4 |
| 58 | 58 | ||
| 59 | #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) | 59 | #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) |
| 60 | #define TRIGGER_FCR_MASK(x) (x & 3) | 60 | #define TRIGGER_FCR_MASK(x) (x & 3) |
| 61 | 61 | ||
| 62 | /* Enable XON/XOFF flow control on output */ | 62 | /* Enable XON/XOFF flow control on output */ |
| 63 | #define OMAP_UART_SW_TX 0x08 | 63 | #define OMAP_UART_SW_TX 0x08 |
| 64 | /* Enable XON/XOFF flow control on input */ | 64 | /* Enable XON/XOFF flow control on input */ |
| 65 | #define OMAP_UART_SW_RX 0x02 | 65 | #define OMAP_UART_SW_RX 0x02 |
| 66 | 66 | ||
| 67 | #define OMAP_UART_WER_MOD_WKUP 0x7f | 67 | #define OMAP_UART_WER_MOD_WKUP 0x7f |
| 68 | #define OMAP_UART_TX_WAKEUP_EN (1 << 7) | 68 | #define OMAP_UART_TX_WAKEUP_EN (1 << 7) |
| 69 | 69 | ||
| 70 | #define TX_TRIGGER 1 | 70 | #define TX_TRIGGER 1 |
| 71 | #define RX_TRIGGER 48 | 71 | #define RX_TRIGGER 48 |
| 72 | 72 | ||
| 73 | #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) | 73 | #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) |
| 74 | #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) | 74 | #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) |
| 75 | 75 | ||
| 76 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) | 76 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) |
| 77 | 77 | ||
| 78 | #define OMAP_UART_REV_46 0x0406 | 78 | #define OMAP_UART_REV_46 0x0406 |
| 79 | #define OMAP_UART_REV_52 0x0502 | 79 | #define OMAP_UART_REV_52 0x0502 |
| 80 | #define OMAP_UART_REV_63 0x0603 | 80 | #define OMAP_UART_REV_63 0x0603 |
| 81 | 81 | ||
| 82 | struct omap8250_priv { | 82 | struct omap8250_priv { |
| 83 | int line; | 83 | int line; |
| 84 | u8 habit; | 84 | u8 habit; |
| 85 | u8 mdr1; | 85 | u8 mdr1; |
| 86 | u8 efr; | 86 | u8 efr; |
| 87 | u8 scr; | 87 | u8 scr; |
| 88 | u8 wer; | 88 | u8 wer; |
| 89 | u8 xon; | 89 | u8 xon; |
| 90 | u8 xoff; | 90 | u8 xoff; |
| 91 | u8 delayed_restore; | 91 | u8 delayed_restore; |
| 92 | u16 quot; | 92 | u16 quot; |
| 93 | 93 | ||
| 94 | bool is_suspending; | 94 | bool is_suspending; |
| 95 | int wakeirq; | 95 | int wakeirq; |
| 96 | int wakeups_enabled; | 96 | int wakeups_enabled; |
| 97 | u32 latency; | 97 | u32 latency; |
| 98 | u32 calc_latency; | 98 | u32 calc_latency; |
| 99 | struct pm_qos_request pm_qos_request; | 99 | struct pm_qos_request pm_qos_request; |
| 100 | struct work_struct qos_work; | 100 | struct work_struct qos_work; |
| 101 | struct uart_8250_dma omap8250_dma; | 101 | struct uart_8250_dma omap8250_dma; |
| 102 | }; | 102 | }; |
| 103 | 103 | ||
| 104 | static u32 uart_read(struct uart_8250_port *up, u32 reg) | 104 | static u32 uart_read(struct uart_8250_port *up, u32 reg) |
| 105 | { | 105 | { |
| 106 | return readl(up->port.membase + (reg << up->port.regshift)); | 106 | return readl(up->port.membase + (reg << up->port.regshift)); |
| 107 | } | 107 | } |
| 108 | 108 | ||
| 109 | /* | 109 | /* |
| 110 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | 110 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) |
| 111 | * The access to uart register after MDR1 Access | 111 | * The access to uart register after MDR1 Access |
| 112 | * causes UART to corrupt data. | 112 | * causes UART to corrupt data. |
| 113 | * | 113 | * |
| 114 | * Need a delay = | 114 | * Need a delay = |
| 115 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | 115 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) |
| 116 | * give 10 times as much | 116 | * give 10 times as much |
| 117 | */ | 117 | */ |
| 118 | static void omap_8250_mdr1_errataset(struct uart_8250_port *up, | 118 | static void omap_8250_mdr1_errataset(struct uart_8250_port *up, |
| 119 | struct omap8250_priv *priv) | 119 | struct omap8250_priv *priv) |
| 120 | { | 120 | { |
| 121 | u8 timeout = 255; | 121 | u8 timeout = 255; |
| 122 | u8 old_mdr1; | 122 | u8 old_mdr1; |
| 123 | 123 | ||
| 124 | old_mdr1 = serial_in(up, UART_OMAP_MDR1); | 124 | old_mdr1 = serial_in(up, UART_OMAP_MDR1); |
| 125 | if (old_mdr1 == priv->mdr1) | 125 | if (old_mdr1 == priv->mdr1) |
| 126 | return; | 126 | return; |
| 127 | 127 | ||
| 128 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); | 128 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); |
| 129 | udelay(2); | 129 | udelay(2); |
| 130 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | 130 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | |
| 131 | UART_FCR_CLEAR_RCVR); | 131 | UART_FCR_CLEAR_RCVR); |
| 132 | /* | 132 | /* |
| 133 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | 133 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and |
| 134 | * TX_FIFO_E bit is 1. | 134 | * TX_FIFO_E bit is 1. |
| 135 | */ | 135 | */ |
| 136 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & | 136 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & |
| 137 | (UART_LSR_THRE | UART_LSR_DR))) { | 137 | (UART_LSR_THRE | UART_LSR_DR))) { |
| 138 | timeout--; | 138 | timeout--; |
| 139 | if (!timeout) { | 139 | if (!timeout) { |
| 140 | /* Should *never* happen. we warn and carry on */ | 140 | /* Should *never* happen. we warn and carry on */ |
| 141 | dev_crit(up->port.dev, "Errata i202: timedout %x\n", | 141 | dev_crit(up->port.dev, "Errata i202: timedout %x\n", |
| 142 | serial_in(up, UART_LSR)); | 142 | serial_in(up, UART_LSR)); |
| 143 | break; | 143 | break; |
| 144 | } | 144 | } |
| 145 | udelay(1); | 145 | udelay(1); |
| 146 | } | 146 | } |
| 147 | } | 147 | } |
| 148 | 148 | ||
| 149 | static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, | 149 | static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, |
| 150 | struct omap8250_priv *priv) | 150 | struct omap8250_priv *priv) |
| 151 | { | 151 | { |
| 152 | unsigned int uartclk = port->uartclk; | 152 | unsigned int uartclk = port->uartclk; |
| 153 | unsigned int div_13, div_16; | 153 | unsigned int div_13, div_16; |
| 154 | unsigned int abs_d13, abs_d16; | 154 | unsigned int abs_d13, abs_d16; |
| 155 | 155 | ||
| 156 | /* | 156 | /* |
| 157 | * Old custom speed handling. | 157 | * Old custom speed handling. |
| 158 | */ | 158 | */ |
| 159 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { | 159 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { |
| 160 | priv->quot = port->custom_divisor & 0xffff; | 160 | priv->quot = port->custom_divisor & 0xffff; |
| 161 | /* | 161 | /* |
| 162 | * I assume that nobody is using this. But hey, if somebody | 162 | * I assume that nobody is using this. But hey, if somebody |
| 163 | * would like to specify the divisor _and_ the mode then the | 163 | * would like to specify the divisor _and_ the mode then the |
| 164 | * driver is ready and waiting for it. | 164 | * driver is ready and waiting for it. |
| 165 | */ | 165 | */ |
| 166 | if (port->custom_divisor & (1 << 16)) | 166 | if (port->custom_divisor & (1 << 16)) |
| 167 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; | 167 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; |
| 168 | else | 168 | else |
| 169 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; | 169 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; |
| 170 | return; | 170 | return; |
| 171 | } | 171 | } |
| 172 | div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); | 172 | div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); |
| 173 | div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); | 173 | div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); |
| 174 | 174 | ||
| 175 | if (!div_13) | 175 | if (!div_13) |
| 176 | div_13 = 1; | 176 | div_13 = 1; |
| 177 | if (!div_16) | 177 | if (!div_16) |
| 178 | div_16 = 1; | 178 | div_16 = 1; |
| 179 | 179 | ||
| 180 | abs_d13 = abs(baud - uartclk / 13 / div_13); | 180 | abs_d13 = abs(baud - uartclk / 13 / div_13); |
| 181 | abs_d16 = abs(baud - uartclk / 16 / div_16); | 181 | abs_d16 = abs(baud - uartclk / 16 / div_16); |
| 182 | 182 | ||
| 183 | if (abs_d13 >= abs_d16) { | 183 | if (abs_d13 >= abs_d16) { |
| 184 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; | 184 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; |
| 185 | priv->quot = div_16; | 185 | priv->quot = div_16; |
| 186 | } else { | 186 | } else { |
| 187 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; | 187 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; |
| 188 | priv->quot = div_13; | 188 | priv->quot = div_13; |
| 189 | } | 189 | } |
| 190 | } | 190 | } |
| 191 | 191 | ||
| 192 | static void omap8250_update_scr(struct uart_8250_port *up, | 192 | static void omap8250_update_scr(struct uart_8250_port *up, |
| 193 | struct omap8250_priv *priv) | 193 | struct omap8250_priv *priv) |
| 194 | { | 194 | { |
| 195 | u8 old_scr; | 195 | u8 old_scr; |
| 196 | 196 | ||
| 197 | old_scr = serial_in(up, UART_OMAP_SCR); | 197 | old_scr = serial_in(up, UART_OMAP_SCR); |
| 198 | if (old_scr == priv->scr) | 198 | if (old_scr == priv->scr) |
| 199 | return; | 199 | return; |
| 200 | 200 | ||
| 201 | /* | 201 | /* |
| 202 | * The manual recommends not to enable the DMA mode selector in the SCR | 202 | * The manual recommends not to enable the DMA mode selector in the SCR |
| 203 | * (instead of the FCR) register _and_ selecting the DMA mode as one | 203 | * (instead of the FCR) register _and_ selecting the DMA mode as one |
| 204 | * register write because this may lead to malfunction. | 204 | * register write because this may lead to malfunction. |
| 205 | */ | 205 | */ |
| 206 | if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) | 206 | if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) |
| 207 | serial_out(up, UART_OMAP_SCR, | 207 | serial_out(up, UART_OMAP_SCR, |
| 208 | priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); | 208 | priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); |
| 209 | serial_out(up, UART_OMAP_SCR, priv->scr); | 209 | serial_out(up, UART_OMAP_SCR, priv->scr); |
| 210 | } | 210 | } |
| 211 | 211 | ||
| 212 | static void omap8250_restore_regs(struct uart_8250_port *up) | 212 | static void omap8250_restore_regs(struct uart_8250_port *up) |
| 213 | { | 213 | { |
| 214 | struct omap8250_priv *priv = up->port.private_data; | 214 | struct omap8250_priv *priv = up->port.private_data; |
| 215 | struct uart_8250_dma *dma = up->dma; | 215 | struct uart_8250_dma *dma = up->dma; |
| 216 | 216 | ||
| 217 | if (dma && dma->tx_running) { | 217 | if (dma && dma->tx_running) { |
| 218 | /* | 218 | /* |
| 219 | * TCSANOW requests the change to occur immediately however if | 219 | * TCSANOW requests the change to occur immediately however if |
| 220 | * we have a TX-DMA operation in progress then it has been | 220 | * we have a TX-DMA operation in progress then it has been |
| 221 | * observed that it might stall and never complete. Therefore we | 221 | * observed that it might stall and never complete. Therefore we |
| 222 | * delay DMA completes to prevent this hang from happen. | 222 | * delay DMA completes to prevent this hang from happen. |
| 223 | */ | 223 | */ |
| 224 | priv->delayed_restore = 1; | 224 | priv->delayed_restore = 1; |
| 225 | return; | 225 | return; |
| 226 | } | 226 | } |
| 227 | 227 | ||
| 228 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | 228 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 229 | serial_out(up, UART_EFR, UART_EFR_ECB); | 229 | serial_out(up, UART_EFR, UART_EFR_ECB); |
| 230 | 230 | ||
| 231 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | 231 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
| 232 | serial_out(up, UART_MCR, UART_MCR_TCRTLR); | 232 | serial_out(up, UART_MCR, UART_MCR_TCRTLR); |
| 233 | serial_out(up, UART_FCR, up->fcr); | 233 | serial_out(up, UART_FCR, up->fcr); |
| 234 | 234 | ||
| 235 | omap8250_update_scr(up, priv); | 235 | omap8250_update_scr(up, priv); |
| 236 | 236 | ||
| 237 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | 237 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 238 | 238 | ||
| 239 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | | 239 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | |
| 240 | OMAP_UART_TCR_HALT(52)); | 240 | OMAP_UART_TCR_HALT(52)); |
| 241 | serial_out(up, UART_TI752_TLR, | 241 | serial_out(up, UART_TI752_TLR, |
| 242 | TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | | 242 | TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | |
| 243 | TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); | 243 | TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); |
| 244 | 244 | ||
| 245 | serial_out(up, UART_LCR, 0); | 245 | serial_out(up, UART_LCR, 0); |
| 246 | 246 | ||
| 247 | /* drop TCR + TLR access, we setup XON/XOFF later */ | 247 | /* drop TCR + TLR access, we setup XON/XOFF later */ |
| 248 | serial_out(up, UART_MCR, up->mcr); | 248 | serial_out(up, UART_MCR, up->mcr); |
| 249 | serial_out(up, UART_IER, up->ier); | 249 | serial_out(up, UART_IER, up->ier); |
| 250 | 250 | ||
| 251 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | 251 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 252 | serial_dl_write(up, priv->quot); | 252 | serial_dl_write(up, priv->quot); |
| 253 | 253 | ||
| 254 | serial_out(up, UART_EFR, priv->efr); | 254 | serial_out(up, UART_EFR, priv->efr); |
| 255 | 255 | ||
| 256 | /* Configure flow control */ | 256 | /* Configure flow control */ |
| 257 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | 257 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 258 | serial_out(up, UART_XON1, priv->xon); | 258 | serial_out(up, UART_XON1, priv->xon); |
| 259 | serial_out(up, UART_XOFF1, priv->xoff); | 259 | serial_out(up, UART_XOFF1, priv->xoff); |
| 260 | 260 | ||
| 261 | serial_out(up, UART_LCR, up->lcr); | 261 | serial_out(up, UART_LCR, up->lcr); |
| 262 | /* need mode A for FCR */ | 262 | /* need mode A for FCR */ |
| 263 | if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) | 263 | if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) |
| 264 | omap_8250_mdr1_errataset(up, priv); | 264 | omap_8250_mdr1_errataset(up, priv); |
| 265 | else | 265 | else |
| 266 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); | 266 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); |
| 267 | up->port.ops->set_mctrl(&up->port, up->port.mctrl); | 267 | up->port.ops->set_mctrl(&up->port, up->port.mctrl); |
| 268 | } | 268 | } |
| 269 | 269 | ||
| 270 | /* | 270 | /* |
| 271 | * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have | 271 | * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have |
| 272 | * some differences in how we want to handle flow control. | 272 | * some differences in how we want to handle flow control. |
| 273 | */ | 273 | */ |
| 274 | static void omap_8250_set_termios(struct uart_port *port, | 274 | static void omap_8250_set_termios(struct uart_port *port, |
| 275 | struct ktermios *termios, | 275 | struct ktermios *termios, |
| 276 | struct ktermios *old) | 276 | struct ktermios *old) |
| 277 | { | 277 | { |
| 278 | struct uart_8250_port *up = | 278 | struct uart_8250_port *up = |
| 279 | container_of(port, struct uart_8250_port, port); | 279 | container_of(port, struct uart_8250_port, port); |
| 280 | struct omap8250_priv *priv = up->port.private_data; | 280 | struct omap8250_priv *priv = up->port.private_data; |
| 281 | unsigned char cval = 0; | 281 | unsigned char cval = 0; |
| 282 | unsigned int baud; | 282 | unsigned int baud; |
| 283 | 283 | ||
| 284 | switch (termios->c_cflag & CSIZE) { | 284 | switch (termios->c_cflag & CSIZE) { |
| 285 | case CS5: | 285 | case CS5: |
| 286 | cval = UART_LCR_WLEN5; | 286 | cval = UART_LCR_WLEN5; |
| 287 | break; | 287 | break; |
| 288 | case CS6: | 288 | case CS6: |
| 289 | cval = UART_LCR_WLEN6; | 289 | cval = UART_LCR_WLEN6; |
| 290 | break; | 290 | break; |
| 291 | case CS7: | 291 | case CS7: |
| 292 | cval = UART_LCR_WLEN7; | 292 | cval = UART_LCR_WLEN7; |
| 293 | break; | 293 | break; |
| 294 | default: | 294 | default: |
| 295 | case CS8: | 295 | case CS8: |
| 296 | cval = UART_LCR_WLEN8; | 296 | cval = UART_LCR_WLEN8; |
| 297 | break; | 297 | break; |
| 298 | } | 298 | } |
| 299 | 299 | ||
| 300 | if (termios->c_cflag & CSTOPB) | 300 | if (termios->c_cflag & CSTOPB) |
| 301 | cval |= UART_LCR_STOP; | 301 | cval |= UART_LCR_STOP; |
| 302 | if (termios->c_cflag & PARENB) | 302 | if (termios->c_cflag & PARENB) |
| 303 | cval |= UART_LCR_PARITY; | 303 | cval |= UART_LCR_PARITY; |
| 304 | if (!(termios->c_cflag & PARODD)) | 304 | if (!(termios->c_cflag & PARODD)) |
| 305 | cval |= UART_LCR_EPAR; | 305 | cval |= UART_LCR_EPAR; |
| 306 | if (termios->c_cflag & CMSPAR) | 306 | if (termios->c_cflag & CMSPAR) |
| 307 | cval |= UART_LCR_SPAR; | 307 | cval |= UART_LCR_SPAR; |
| 308 | 308 | ||
| 309 | /* | 309 | /* |
| 310 | * Ask the core to calculate the divisor for us. | 310 | * Ask the core to calculate the divisor for us. |
| 311 | */ | 311 | */ |
| 312 | baud = uart_get_baud_rate(port, termios, old, | 312 | baud = uart_get_baud_rate(port, termios, old, |
| 313 | port->uartclk / 16 / 0xffff, | 313 | port->uartclk / 16 / 0xffff, |
| 314 | port->uartclk / 13); | 314 | port->uartclk / 13); |
| 315 | omap_8250_get_divisor(port, baud, priv); | 315 | omap_8250_get_divisor(port, baud, priv); |
| 316 | 316 | ||
| 317 | /* | 317 | /* |
| 318 | * Ok, we're now changing the port state. Do it with | 318 | * Ok, we're now changing the port state. Do it with |
| 319 | * interrupts disabled. | 319 | * interrupts disabled. |
| 320 | */ | 320 | */ |
| 321 | pm_runtime_get_sync(port->dev); | 321 | pm_runtime_get_sync(port->dev); |
| 322 | spin_lock_irq(&port->lock); | 322 | spin_lock_irq(&port->lock); |
| 323 | 323 | ||
| 324 | /* | 324 | /* |
| 325 | * Update the per-port timeout. | 325 | * Update the per-port timeout. |
| 326 | */ | 326 | */ |
| 327 | uart_update_timeout(port, termios->c_cflag, baud); | 327 | uart_update_timeout(port, termios->c_cflag, baud); |
| 328 | 328 | ||
| 329 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | 329 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
| 330 | if (termios->c_iflag & INPCK) | 330 | if (termios->c_iflag & INPCK) |
| 331 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | 331 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
| 332 | if (termios->c_iflag & (IGNBRK | PARMRK)) | 332 | if (termios->c_iflag & (IGNBRK | PARMRK)) |
| 333 | up->port.read_status_mask |= UART_LSR_BI; | 333 | up->port.read_status_mask |= UART_LSR_BI; |
| 334 | 334 | ||
| 335 | /* | 335 | /* |
| 336 | * Characters to ignore | 336 | * Characters to ignore |
| 337 | */ | 337 | */ |
| 338 | up->port.ignore_status_mask = 0; | 338 | up->port.ignore_status_mask = 0; |
| 339 | if (termios->c_iflag & IGNPAR) | 339 | if (termios->c_iflag & IGNPAR) |
| 340 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | 340 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
| 341 | if (termios->c_iflag & IGNBRK) { | 341 | if (termios->c_iflag & IGNBRK) { |
| 342 | up->port.ignore_status_mask |= UART_LSR_BI; | 342 | up->port.ignore_status_mask |= UART_LSR_BI; |
| 343 | /* | 343 | /* |
| 344 | * If we're ignoring parity and break indicators, | 344 | * If we're ignoring parity and break indicators, |
| 345 | * ignore overruns too (for real raw support). | 345 | * ignore overruns too (for real raw support). |
| 346 | */ | 346 | */ |
| 347 | if (termios->c_iflag & IGNPAR) | 347 | if (termios->c_iflag & IGNPAR) |
| 348 | up->port.ignore_status_mask |= UART_LSR_OE; | 348 | up->port.ignore_status_mask |= UART_LSR_OE; |
| 349 | } | 349 | } |
| 350 | 350 | ||
| 351 | /* | 351 | /* |
| 352 | * ignore all characters if CREAD is not set | 352 | * ignore all characters if CREAD is not set |
| 353 | */ | 353 | */ |
| 354 | if ((termios->c_cflag & CREAD) == 0) | 354 | if ((termios->c_cflag & CREAD) == 0) |
| 355 | up->port.ignore_status_mask |= UART_LSR_DR; | 355 | up->port.ignore_status_mask |= UART_LSR_DR; |
| 356 | 356 | ||
| 357 | /* | 357 | /* |
| 358 | * Modem status interrupts | 358 | * Modem status interrupts |
| 359 | */ | 359 | */ |
| 360 | up->ier &= ~UART_IER_MSI; | 360 | up->ier &= ~UART_IER_MSI; |
| 361 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | 361 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) |
| 362 | up->ier |= UART_IER_MSI; | 362 | up->ier |= UART_IER_MSI; |
| 363 | 363 | ||
| 364 | up->lcr = cval; | 364 | up->lcr = cval; |
| 365 | /* Up to here it was mostly serial8250_do_set_termios() */ | 365 | /* Up to here it was mostly serial8250_do_set_termios() */ |
| 366 | 366 | ||
| 367 | /* | 367 | /* |
| 368 | * We enable TRIG_GRANU for RX and TX and additionaly we set | 368 | * We enable TRIG_GRANU for RX and TX and additionaly we set |
| 369 | * SCR_TX_EMPTY bit. The result is the following: | 369 | * SCR_TX_EMPTY bit. The result is the following: |
| 370 | * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. | 370 | * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. |
| 371 | * - less than RX_TRIGGER number of bytes will also cause an interrupt | 371 | * - less than RX_TRIGGER number of bytes will also cause an interrupt |
| 372 | * once the UART decides that there no new bytes arriving. | 372 | * once the UART decides that there no new bytes arriving. |
| 373 | * - Once THRE is enabled, the interrupt will be fired once the FIFO is | 373 | * - Once THRE is enabled, the interrupt will be fired once the FIFO is |
| 374 | * empty - the trigger level is ignored here. | 374 | * empty - the trigger level is ignored here. |
| 375 | * | 375 | * |
| 376 | * Once DMA is enabled: | 376 | * Once DMA is enabled: |
| 377 | * - UART will assert the TX DMA line once there is room for TX_TRIGGER | 377 | * - UART will assert the TX DMA line once there is room for TX_TRIGGER |
| 378 | * bytes in the TX FIFO. On each assert the DMA engine will move | 378 | * bytes in the TX FIFO. On each assert the DMA engine will move |
| 379 | * TX_TRIGGER bytes into the FIFO. | 379 | * TX_TRIGGER bytes into the FIFO. |
| 380 | * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in | 380 | * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in |
| 381 | * the FIFO and move RX_TRIGGER bytes. | 381 | * the FIFO and move RX_TRIGGER bytes. |
| 382 | * This is because threshold and trigger values are the same. | 382 | * This is because threshold and trigger values are the same. |
| 383 | */ | 383 | */ |
| 384 | up->fcr = UART_FCR_ENABLE_FIFO; | 384 | up->fcr = UART_FCR_ENABLE_FIFO; |
| 385 | up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; | 385 | up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; |
| 386 | up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; | 386 | up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; |
| 387 | 387 | ||
| 388 | priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | | 388 | priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | |
| 389 | OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; | 389 | OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; |
| 390 | 390 | ||
| 391 | if (up->dma) | 391 | if (up->dma) |
| 392 | priv->scr |= OMAP_UART_SCR_DMAMODE_1 | | 392 | priv->scr |= OMAP_UART_SCR_DMAMODE_1 | |
| 393 | OMAP_UART_SCR_DMAMODE_CTL; | 393 | OMAP_UART_SCR_DMAMODE_CTL; |
| 394 | 394 | ||
| 395 | priv->xon = termios->c_cc[VSTART]; | 395 | priv->xon = termios->c_cc[VSTART]; |
| 396 | priv->xoff = termios->c_cc[VSTOP]; | 396 | priv->xoff = termios->c_cc[VSTOP]; |
| 397 | 397 | ||
| 398 | priv->efr = 0; | 398 | priv->efr = 0; |
| 399 | up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); | 399 | up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); |
| 400 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { | 400 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { |
| 401 | /* Enable AUTORTS and AUTOCTS */ | 401 | /* Enable AUTORTS and AUTOCTS */ |
| 402 | priv->efr |= UART_EFR_CTS | UART_EFR_RTS; | 402 | priv->efr |= UART_EFR_CTS | UART_EFR_RTS; |
| 403 | 403 | ||
| 404 | /* Ensure MCR RTS is asserted */ | 404 | /* Ensure MCR RTS is asserted */ |
| 405 | up->mcr |= UART_MCR_RTS; | 405 | up->mcr |= UART_MCR_RTS; |
| 406 | } else if (up->port.flags & UPF_SOFT_FLOW) { | 406 | } else if (up->port.flags & UPF_SOFT_FLOW) { |
| 407 | /* | 407 | /* |
| 408 | * IXON Flag: | 408 | * IXON Flag: |
| 409 | * Enable XON/XOFF flow control on input. | 409 | * Enable XON/XOFF flow control on input. |
| 410 | * Receiver compares XON1, XOFF1. | 410 | * Receiver compares XON1, XOFF1. |
| 411 | */ | 411 | */ |
| 412 | if (termios->c_iflag & IXON) | 412 | if (termios->c_iflag & IXON) |
| 413 | priv->efr |= OMAP_UART_SW_RX; | 413 | priv->efr |= OMAP_UART_SW_RX; |
| 414 | 414 | ||
| 415 | /* | 415 | /* |
| 416 | * IXOFF Flag: | 416 | * IXOFF Flag: |
| 417 | * Enable XON/XOFF flow control on output. | 417 | * Enable XON/XOFF flow control on output. |
| 418 | * Transmit XON1, XOFF1 | 418 | * Transmit XON1, XOFF1 |
| 419 | */ | 419 | */ |
| 420 | if (termios->c_iflag & IXOFF) | 420 | if (termios->c_iflag & IXOFF) |
| 421 | priv->efr |= OMAP_UART_SW_TX; | 421 | priv->efr |= OMAP_UART_SW_TX; |
| 422 | 422 | ||
| 423 | /* | 423 | /* |
| 424 | * IXANY Flag: | 424 | * IXANY Flag: |
| 425 | * Enable any character to restart output. | 425 | * Enable any character to restart output. |
| 426 | * Operation resumes after receiving any | 426 | * Operation resumes after receiving any |
| 427 | * character after recognition of the XOFF character | 427 | * character after recognition of the XOFF character |
| 428 | */ | 428 | */ |
| 429 | if (termios->c_iflag & IXANY) | 429 | if (termios->c_iflag & IXANY) |
| 430 | up->mcr |= UART_MCR_XONANY; | 430 | up->mcr |= UART_MCR_XONANY; |
| 431 | } | 431 | } |
| 432 | omap8250_restore_regs(up); | 432 | omap8250_restore_regs(up); |
| 433 | 433 | ||
| 434 | spin_unlock_irq(&up->port.lock); | 434 | spin_unlock_irq(&up->port.lock); |
| 435 | pm_runtime_mark_last_busy(port->dev); | 435 | pm_runtime_mark_last_busy(port->dev); |
| 436 | pm_runtime_put_autosuspend(port->dev); | 436 | pm_runtime_put_autosuspend(port->dev); |
| 437 | 437 | ||
| 438 | /* calculate wakeup latency constraint */ | 438 | /* calculate wakeup latency constraint */ |
| 439 | priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; | 439 | priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; |
| 440 | priv->latency = priv->calc_latency; | 440 | priv->latency = priv->calc_latency; |
| 441 | 441 | ||
| 442 | schedule_work(&priv->qos_work); | 442 | schedule_work(&priv->qos_work); |
| 443 | 443 | ||
| 444 | /* Don't rewrite B0 */ | 444 | /* Don't rewrite B0 */ |
| 445 | if (tty_termios_baud_rate(termios)) | 445 | if (tty_termios_baud_rate(termios)) |
| 446 | tty_termios_encode_baud_rate(termios, baud, baud); | 446 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 447 | } | 447 | } |
| 448 | 448 | ||
| 449 | /* same as 8250 except that we may have extra flow bits set in EFR */ | 449 | /* same as 8250 except that we may have extra flow bits set in EFR */ |
| 450 | static void omap_8250_pm(struct uart_port *port, unsigned int state, | 450 | static void omap_8250_pm(struct uart_port *port, unsigned int state, |
| 451 | unsigned int oldstate) | 451 | unsigned int oldstate) |
| 452 | { | 452 | { |
| 453 | struct uart_8250_port *up = | 453 | struct uart_8250_port *up = |
| 454 | container_of(port, struct uart_8250_port, port); | 454 | container_of(port, struct uart_8250_port, port); |
| 455 | struct omap8250_priv *priv = up->port.private_data; | 455 | struct omap8250_priv *priv = up->port.private_data; |
| 456 | 456 | ||
| 457 | pm_runtime_get_sync(port->dev); | 457 | pm_runtime_get_sync(port->dev); |
| 458 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | 458 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 459 | serial_out(up, UART_EFR, priv->efr | UART_EFR_ECB); | 459 | serial_out(up, UART_EFR, priv->efr | UART_EFR_ECB); |
| 460 | serial_out(up, UART_LCR, 0); | 460 | serial_out(up, UART_LCR, 0); |
| 461 | 461 | ||
| 462 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | 462 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); |
| 463 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | 463 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
| 464 | serial_out(up, UART_EFR, priv->efr); | 464 | serial_out(up, UART_EFR, priv->efr); |
| 465 | serial_out(up, UART_LCR, 0); | 465 | serial_out(up, UART_LCR, 0); |
| 466 | 466 | ||
| 467 | pm_runtime_mark_last_busy(port->dev); | 467 | pm_runtime_mark_last_busy(port->dev); |
| 468 | pm_runtime_put_autosuspend(port->dev); | 468 | pm_runtime_put_autosuspend(port->dev); |
| 469 | } | 469 | } |
| 470 | 470 | ||
| 471 | static void omap_serial_fill_features_erratas(struct uart_8250_port *up, | 471 | static void omap_serial_fill_features_erratas(struct uart_8250_port *up, |
| 472 | struct omap8250_priv *priv) | 472 | struct omap8250_priv *priv) |
| 473 | { | 473 | { |
| 474 | u32 mvr, scheme; | 474 | u32 mvr, scheme; |
| 475 | u16 revision, major, minor; | 475 | u16 revision, major, minor; |
| 476 | 476 | ||
| 477 | mvr = uart_read(up, UART_OMAP_MVER); | 477 | mvr = uart_read(up, UART_OMAP_MVER); |
| 478 | 478 | ||
| 479 | /* Check revision register scheme */ | 479 | /* Check revision register scheme */ |
| 480 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | 480 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; |
| 481 | 481 | ||
| 482 | switch (scheme) { | 482 | switch (scheme) { |
| 483 | case 0: /* Legacy Scheme: OMAP2/3 */ | 483 | case 0: /* Legacy Scheme: OMAP2/3 */ |
| 484 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | 484 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ |
| 485 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | 485 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> |
| 486 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | 486 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; |
| 487 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | 487 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); |
| 488 | break; | 488 | break; |
| 489 | case 1: | 489 | case 1: |
| 490 | /* New Scheme: OMAP4+ */ | 490 | /* New Scheme: OMAP4+ */ |
| 491 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | 491 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ |
| 492 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | 492 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> |
| 493 | OMAP_UART_MVR_MAJ_SHIFT; | 493 | OMAP_UART_MVR_MAJ_SHIFT; |
| 494 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | 494 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); |
| 495 | break; | 495 | break; |
| 496 | default: | 496 | default: |
| 497 | dev_warn(up->port.dev, | 497 | dev_warn(up->port.dev, |
| 498 | "Unknown revision, defaulting to highest\n"); | 498 | "Unknown revision, defaulting to highest\n"); |
| 499 | /* highest possible revision */ | 499 | /* highest possible revision */ |
| 500 | major = 0xff; | 500 | major = 0xff; |
| 501 | minor = 0xff; | 501 | minor = 0xff; |
| 502 | } | 502 | } |
| 503 | /* normalize revision for the driver */ | 503 | /* normalize revision for the driver */ |
| 504 | revision = UART_BUILD_REVISION(major, minor); | 504 | revision = UART_BUILD_REVISION(major, minor); |
| 505 | 505 | ||
| 506 | switch (revision) { | 506 | switch (revision) { |
| 507 | case OMAP_UART_REV_46: | 507 | case OMAP_UART_REV_46: |
| 508 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS; | 508 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS; |
| 509 | break; | 509 | break; |
| 510 | case OMAP_UART_REV_52: | 510 | case OMAP_UART_REV_52: |
| 511 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS | | 511 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS | |
| 512 | OMAP_UART_WER_HAS_TX_WAKEUP; | 512 | OMAP_UART_WER_HAS_TX_WAKEUP; |
| 513 | break; | 513 | break; |
| 514 | case OMAP_UART_REV_63: | 514 | case OMAP_UART_REV_63: |
| 515 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS | | 515 | priv->habit = UART_ERRATA_i202_MDR1_ACCESS | |
| 516 | OMAP_UART_WER_HAS_TX_WAKEUP; | 516 | OMAP_UART_WER_HAS_TX_WAKEUP; |
| 517 | break; | 517 | break; |
| 518 | default: | 518 | default: |
| 519 | break; | 519 | break; |
| 520 | } | 520 | } |
| 521 | } | 521 | } |
| 522 | 522 | ||
| 523 | static void omap8250_uart_qos_work(struct work_struct *work) | 523 | static void omap8250_uart_qos_work(struct work_struct *work) |
| 524 | { | 524 | { |
| 525 | struct omap8250_priv *priv; | 525 | struct omap8250_priv *priv; |
| 526 | 526 | ||
| 527 | priv = container_of(work, struct omap8250_priv, qos_work); | 527 | priv = container_of(work, struct omap8250_priv, qos_work); |
| 528 | pm_qos_update_request(&priv->pm_qos_request, priv->latency); | 528 | pm_qos_update_request(&priv->pm_qos_request, priv->latency); |
| 529 | } | 529 | } |
| 530 | 530 | ||
| 531 | static irqreturn_t omap_wake_irq(int irq, void *dev_id) | 531 | static irqreturn_t omap_wake_irq(int irq, void *dev_id) |
| 532 | { | 532 | { |
| 533 | struct uart_port *port = dev_id; | 533 | struct uart_port *port = dev_id; |
| 534 | int ret; | 534 | int ret; |
| 535 | 535 | ||
| 536 | ret = port->handle_irq(port); | 536 | ret = port->handle_irq(port); |
| 537 | if (ret) | 537 | if (ret) |
| 538 | return IRQ_HANDLED; | 538 | return IRQ_HANDLED; |
| 539 | return IRQ_NONE; | 539 | return IRQ_NONE; |
| 540 | } | 540 | } |
| 541 | 541 | ||
| 542 | static int omap_8250_startup(struct uart_port *port) | 542 | static int omap_8250_startup(struct uart_port *port) |
| 543 | { | 543 | { |
| 544 | struct uart_8250_port *up = | 544 | struct uart_8250_port *up = |
| 545 | container_of(port, struct uart_8250_port, port); | 545 | container_of(port, struct uart_8250_port, port); |
| 546 | struct omap8250_priv *priv = port->private_data; | 546 | struct omap8250_priv *priv = port->private_data; |
| 547 | 547 | ||
| 548 | int ret; | 548 | int ret; |
| 549 | 549 | ||
| 550 | if (priv->wakeirq) { | 550 | if (priv->wakeirq) { |
| 551 | ret = request_irq(priv->wakeirq, omap_wake_irq, | 551 | ret = request_irq(priv->wakeirq, omap_wake_irq, |
| 552 | port->irqflags, "uart wakeup irq", port); | 552 | port->irqflags, "uart wakeup irq", port); |
| 553 | if (ret) | 553 | if (ret) |
| 554 | return ret; | 554 | return ret; |
| 555 | disable_irq(priv->wakeirq); | 555 | disable_irq(priv->wakeirq); |
| 556 | } | 556 | } |
| 557 | 557 | ||
| 558 | pm_runtime_get_sync(port->dev); | 558 | pm_runtime_get_sync(port->dev); |
| 559 | 559 | ||
| 560 | ret = serial8250_do_startup(port); | 560 | ret = serial8250_do_startup(port); |
| 561 | if (ret) | 561 | if (ret) |
| 562 | goto err; | 562 | goto err; |
| 563 | 563 | ||
| 564 | #ifdef CONFIG_PM_RUNTIME | 564 | #ifdef CONFIG_PM |
| 565 | up->capabilities |= UART_CAP_RPM; | 565 | up->capabilities |= UART_CAP_RPM; |
| 566 | #endif | 566 | #endif |
| 567 | 567 | ||
| 568 | /* Enable module level wake up */ | 568 | /* Enable module level wake up */ |
| 569 | priv->wer = OMAP_UART_WER_MOD_WKUP; | 569 | priv->wer = OMAP_UART_WER_MOD_WKUP; |
| 570 | if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) | 570 | if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) |
| 571 | priv->wer |= OMAP_UART_TX_WAKEUP_EN; | 571 | priv->wer |= OMAP_UART_TX_WAKEUP_EN; |
| 572 | serial_out(up, UART_OMAP_WER, priv->wer); | 572 | serial_out(up, UART_OMAP_WER, priv->wer); |
| 573 | 573 | ||
| 574 | if (up->dma) | 574 | if (up->dma) |
| 575 | up->dma->rx_dma(up, 0); | 575 | up->dma->rx_dma(up, 0); |
| 576 | 576 | ||
| 577 | pm_runtime_mark_last_busy(port->dev); | 577 | pm_runtime_mark_last_busy(port->dev); |
| 578 | pm_runtime_put_autosuspend(port->dev); | 578 | pm_runtime_put_autosuspend(port->dev); |
| 579 | return 0; | 579 | return 0; |
| 580 | err: | 580 | err: |
| 581 | pm_runtime_mark_last_busy(port->dev); | 581 | pm_runtime_mark_last_busy(port->dev); |
| 582 | pm_runtime_put_autosuspend(port->dev); | 582 | pm_runtime_put_autosuspend(port->dev); |
| 583 | if (priv->wakeirq) | 583 | if (priv->wakeirq) |
| 584 | free_irq(priv->wakeirq, port); | 584 | free_irq(priv->wakeirq, port); |
| 585 | return ret; | 585 | return ret; |
| 586 | } | 586 | } |
| 587 | 587 | ||
| 588 | static void omap_8250_shutdown(struct uart_port *port) | 588 | static void omap_8250_shutdown(struct uart_port *port) |
| 589 | { | 589 | { |
| 590 | struct uart_8250_port *up = | 590 | struct uart_8250_port *up = |
| 591 | container_of(port, struct uart_8250_port, port); | 591 | container_of(port, struct uart_8250_port, port); |
| 592 | struct omap8250_priv *priv = port->private_data; | 592 | struct omap8250_priv *priv = port->private_data; |
| 593 | 593 | ||
| 594 | flush_work(&priv->qos_work); | 594 | flush_work(&priv->qos_work); |
| 595 | if (up->dma) | 595 | if (up->dma) |
| 596 | up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); | 596 | up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); |
| 597 | 597 | ||
| 598 | pm_runtime_get_sync(port->dev); | 598 | pm_runtime_get_sync(port->dev); |
| 599 | 599 | ||
| 600 | serial_out(up, UART_OMAP_WER, 0); | 600 | serial_out(up, UART_OMAP_WER, 0); |
| 601 | serial8250_do_shutdown(port); | 601 | serial8250_do_shutdown(port); |
| 602 | 602 | ||
| 603 | pm_runtime_mark_last_busy(port->dev); | 603 | pm_runtime_mark_last_busy(port->dev); |
| 604 | pm_runtime_put_autosuspend(port->dev); | 604 | pm_runtime_put_autosuspend(port->dev); |
| 605 | 605 | ||
| 606 | if (priv->wakeirq) | 606 | if (priv->wakeirq) |
| 607 | free_irq(priv->wakeirq, port); | 607 | free_irq(priv->wakeirq, port); |
| 608 | } | 608 | } |
| 609 | 609 | ||
| 610 | static void omap_8250_throttle(struct uart_port *port) | 610 | static void omap_8250_throttle(struct uart_port *port) |
| 611 | { | 611 | { |
| 612 | unsigned long flags; | 612 | unsigned long flags; |
| 613 | struct uart_8250_port *up = | 613 | struct uart_8250_port *up = |
| 614 | container_of(port, struct uart_8250_port, port); | 614 | container_of(port, struct uart_8250_port, port); |
| 615 | 615 | ||
| 616 | pm_runtime_get_sync(port->dev); | 616 | pm_runtime_get_sync(port->dev); |
| 617 | 617 | ||
| 618 | spin_lock_irqsave(&port->lock, flags); | 618 | spin_lock_irqsave(&port->lock, flags); |
| 619 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | 619 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); |
| 620 | serial_out(up, UART_IER, up->ier); | 620 | serial_out(up, UART_IER, up->ier); |
| 621 | spin_unlock_irqrestore(&port->lock, flags); | 621 | spin_unlock_irqrestore(&port->lock, flags); |
| 622 | 622 | ||
| 623 | pm_runtime_mark_last_busy(port->dev); | 623 | pm_runtime_mark_last_busy(port->dev); |
| 624 | pm_runtime_put_autosuspend(port->dev); | 624 | pm_runtime_put_autosuspend(port->dev); |
| 625 | } | 625 | } |
| 626 | 626 | ||
| 627 | static void omap_8250_unthrottle(struct uart_port *port) | 627 | static void omap_8250_unthrottle(struct uart_port *port) |
| 628 | { | 628 | { |
| 629 | unsigned long flags; | 629 | unsigned long flags; |
| 630 | struct uart_8250_port *up = | 630 | struct uart_8250_port *up = |
| 631 | container_of(port, struct uart_8250_port, port); | 631 | container_of(port, struct uart_8250_port, port); |
| 632 | 632 | ||
| 633 | pm_runtime_get_sync(port->dev); | 633 | pm_runtime_get_sync(port->dev); |
| 634 | 634 | ||
| 635 | spin_lock_irqsave(&port->lock, flags); | 635 | spin_lock_irqsave(&port->lock, flags); |
| 636 | up->ier |= UART_IER_RLSI | UART_IER_RDI; | 636 | up->ier |= UART_IER_RLSI | UART_IER_RDI; |
| 637 | serial_out(up, UART_IER, up->ier); | 637 | serial_out(up, UART_IER, up->ier); |
| 638 | spin_unlock_irqrestore(&port->lock, flags); | 638 | spin_unlock_irqrestore(&port->lock, flags); |
| 639 | 639 | ||
| 640 | pm_runtime_mark_last_busy(port->dev); | 640 | pm_runtime_mark_last_busy(port->dev); |
| 641 | pm_runtime_put_autosuspend(port->dev); | 641 | pm_runtime_put_autosuspend(port->dev); |
| 642 | } | 642 | } |
| 643 | 643 | ||
| 644 | #ifdef CONFIG_SERIAL_8250_DMA | 644 | #ifdef CONFIG_SERIAL_8250_DMA |
| 645 | static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); | 645 | static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); |
| 646 | 646 | ||
| 647 | static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) | 647 | static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) |
| 648 | { | 648 | { |
| 649 | struct uart_8250_dma *dma = p->dma; | 649 | struct uart_8250_dma *dma = p->dma; |
| 650 | struct tty_port *tty_port = &p->port.state->port; | 650 | struct tty_port *tty_port = &p->port.state->port; |
| 651 | struct dma_tx_state state; | 651 | struct dma_tx_state state; |
| 652 | int count; | 652 | int count; |
| 653 | 653 | ||
| 654 | dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, | 654 | dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, |
| 655 | dma->rx_size, DMA_FROM_DEVICE); | 655 | dma->rx_size, DMA_FROM_DEVICE); |
| 656 | 656 | ||
| 657 | dma->rx_running = 0; | 657 | dma->rx_running = 0; |
| 658 | dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); | 658 | dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); |
| 659 | dmaengine_terminate_all(dma->rxchan); | 659 | dmaengine_terminate_all(dma->rxchan); |
| 660 | 660 | ||
| 661 | count = dma->rx_size - state.residue; | 661 | count = dma->rx_size - state.residue; |
| 662 | 662 | ||
| 663 | tty_insert_flip_string(tty_port, dma->rx_buf, count); | 663 | tty_insert_flip_string(tty_port, dma->rx_buf, count); |
| 664 | p->port.icount.rx += count; | 664 | p->port.icount.rx += count; |
| 665 | if (!error) | 665 | if (!error) |
| 666 | omap_8250_rx_dma(p, 0); | 666 | omap_8250_rx_dma(p, 0); |
| 667 | 667 | ||
| 668 | tty_flip_buffer_push(tty_port); | 668 | tty_flip_buffer_push(tty_port); |
| 669 | } | 669 | } |
| 670 | 670 | ||
| 671 | static void __dma_rx_complete(void *param) | 671 | static void __dma_rx_complete(void *param) |
| 672 | { | 672 | { |
| 673 | __dma_rx_do_complete(param, false); | 673 | __dma_rx_do_complete(param, false); |
| 674 | } | 674 | } |
| 675 | 675 | ||
| 676 | static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) | 676 | static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) |
| 677 | { | 677 | { |
| 678 | struct uart_8250_dma *dma = p->dma; | 678 | struct uart_8250_dma *dma = p->dma; |
| 679 | struct dma_async_tx_descriptor *desc; | 679 | struct dma_async_tx_descriptor *desc; |
| 680 | 680 | ||
| 681 | switch (iir & 0x3f) { | 681 | switch (iir & 0x3f) { |
| 682 | case UART_IIR_RLSI: | 682 | case UART_IIR_RLSI: |
| 683 | /* 8250_core handles errors and break interrupts */ | 683 | /* 8250_core handles errors and break interrupts */ |
| 684 | if (dma->rx_running) { | 684 | if (dma->rx_running) { |
| 685 | dmaengine_pause(dma->rxchan); | 685 | dmaengine_pause(dma->rxchan); |
| 686 | __dma_rx_do_complete(p, true); | 686 | __dma_rx_do_complete(p, true); |
| 687 | } | 687 | } |
| 688 | return -EIO; | 688 | return -EIO; |
| 689 | case UART_IIR_RX_TIMEOUT: | 689 | case UART_IIR_RX_TIMEOUT: |
| 690 | /* | 690 | /* |
| 691 | * If RCVR FIFO trigger level was not reached, complete the | 691 | * If RCVR FIFO trigger level was not reached, complete the |
| 692 | * transfer and let 8250_core copy the remaining data. | 692 | * transfer and let 8250_core copy the remaining data. |
| 693 | */ | 693 | */ |
| 694 | if (dma->rx_running) { | 694 | if (dma->rx_running) { |
| 695 | dmaengine_pause(dma->rxchan); | 695 | dmaengine_pause(dma->rxchan); |
| 696 | __dma_rx_do_complete(p, true); | 696 | __dma_rx_do_complete(p, true); |
| 697 | } | 697 | } |
| 698 | return -ETIMEDOUT; | 698 | return -ETIMEDOUT; |
| 699 | case UART_IIR_RDI: | 699 | case UART_IIR_RDI: |
| 700 | /* | 700 | /* |
| 701 | * The OMAP UART is a special BEAST. If we receive RDI we _have_ | 701 | * The OMAP UART is a special BEAST. If we receive RDI we _have_ |
| 702 | * a DMA transfer programmed but it didn't work. One reason is | 702 | * a DMA transfer programmed but it didn't work. One reason is |
| 703 | * that we were too slow and there were too many bytes in the | 703 | * that we were too slow and there were too many bytes in the |
| 704 | * FIFO, the UART counted wrong and never kicked the DMA engine | 704 | * FIFO, the UART counted wrong and never kicked the DMA engine |
| 705 | * to do anything. That means once we receive RDI on OMAP then | 705 | * to do anything. That means once we receive RDI on OMAP then |
| 706 | * the DMA won't do anything soon so we have to cancel the DMA | 706 | * the DMA won't do anything soon so we have to cancel the DMA |
| 707 | * transfer and purge the FIFO manually. | 707 | * transfer and purge the FIFO manually. |
| 708 | */ | 708 | */ |
| 709 | if (dma->rx_running) { | 709 | if (dma->rx_running) { |
| 710 | dmaengine_pause(dma->rxchan); | 710 | dmaengine_pause(dma->rxchan); |
| 711 | __dma_rx_do_complete(p, true); | 711 | __dma_rx_do_complete(p, true); |
| 712 | } | 712 | } |
| 713 | return -ETIMEDOUT; | 713 | return -ETIMEDOUT; |
| 714 | 714 | ||
| 715 | default: | 715 | default: |
| 716 | break; | 716 | break; |
| 717 | } | 717 | } |
| 718 | 718 | ||
| 719 | if (dma->rx_running) | 719 | if (dma->rx_running) |
| 720 | return 0; | 720 | return 0; |
| 721 | 721 | ||
| 722 | desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, | 722 | desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, |
| 723 | dma->rx_size, DMA_DEV_TO_MEM, | 723 | dma->rx_size, DMA_DEV_TO_MEM, |
| 724 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 724 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 725 | if (!desc) | 725 | if (!desc) |
| 726 | return -EBUSY; | 726 | return -EBUSY; |
| 727 | 727 | ||
| 728 | dma->rx_running = 1; | 728 | dma->rx_running = 1; |
| 729 | desc->callback = __dma_rx_complete; | 729 | desc->callback = __dma_rx_complete; |
| 730 | desc->callback_param = p; | 730 | desc->callback_param = p; |
| 731 | 731 | ||
| 732 | dma->rx_cookie = dmaengine_submit(desc); | 732 | dma->rx_cookie = dmaengine_submit(desc); |
| 733 | 733 | ||
| 734 | dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, | 734 | dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, |
| 735 | dma->rx_size, DMA_FROM_DEVICE); | 735 | dma->rx_size, DMA_FROM_DEVICE); |
| 736 | 736 | ||
| 737 | dma_async_issue_pending(dma->rxchan); | 737 | dma_async_issue_pending(dma->rxchan); |
| 738 | return 0; | 738 | return 0; |
| 739 | } | 739 | } |
| 740 | 740 | ||
| 741 | static int omap_8250_tx_dma(struct uart_8250_port *p); | 741 | static int omap_8250_tx_dma(struct uart_8250_port *p); |
| 742 | 742 | ||
| 743 | static void omap_8250_dma_tx_complete(void *param) | 743 | static void omap_8250_dma_tx_complete(void *param) |
| 744 | { | 744 | { |
| 745 | struct uart_8250_port *p = param; | 745 | struct uart_8250_port *p = param; |
| 746 | struct uart_8250_dma *dma = p->dma; | 746 | struct uart_8250_dma *dma = p->dma; |
| 747 | struct circ_buf *xmit = &p->port.state->xmit; | 747 | struct circ_buf *xmit = &p->port.state->xmit; |
| 748 | unsigned long flags; | 748 | unsigned long flags; |
| 749 | bool en_thri = false; | 749 | bool en_thri = false; |
| 750 | struct omap8250_priv *priv = p->port.private_data; | 750 | struct omap8250_priv *priv = p->port.private_data; |
| 751 | 751 | ||
| 752 | dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, | 752 | dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, |
| 753 | UART_XMIT_SIZE, DMA_TO_DEVICE); | 753 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
| 754 | 754 | ||
| 755 | spin_lock_irqsave(&p->port.lock, flags); | 755 | spin_lock_irqsave(&p->port.lock, flags); |
| 756 | 756 | ||
| 757 | dma->tx_running = 0; | 757 | dma->tx_running = 0; |
| 758 | 758 | ||
| 759 | xmit->tail += dma->tx_size; | 759 | xmit->tail += dma->tx_size; |
| 760 | xmit->tail &= UART_XMIT_SIZE - 1; | 760 | xmit->tail &= UART_XMIT_SIZE - 1; |
| 761 | p->port.icount.tx += dma->tx_size; | 761 | p->port.icount.tx += dma->tx_size; |
| 762 | 762 | ||
| 763 | if (priv->delayed_restore) { | 763 | if (priv->delayed_restore) { |
| 764 | priv->delayed_restore = 0; | 764 | priv->delayed_restore = 0; |
| 765 | omap8250_restore_regs(p); | 765 | omap8250_restore_regs(p); |
| 766 | } | 766 | } |
| 767 | 767 | ||
| 768 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | 768 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 769 | uart_write_wakeup(&p->port); | 769 | uart_write_wakeup(&p->port); |
| 770 | 770 | ||
| 771 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { | 771 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { |
| 772 | int ret; | 772 | int ret; |
| 773 | 773 | ||
| 774 | ret = omap_8250_tx_dma(p); | 774 | ret = omap_8250_tx_dma(p); |
| 775 | if (ret) | 775 | if (ret) |
| 776 | en_thri = true; | 776 | en_thri = true; |
| 777 | 777 | ||
| 778 | } else if (p->capabilities & UART_CAP_RPM) { | 778 | } else if (p->capabilities & UART_CAP_RPM) { |
| 779 | en_thri = true; | 779 | en_thri = true; |
| 780 | } | 780 | } |
| 781 | 781 | ||
| 782 | if (en_thri) { | 782 | if (en_thri) { |
| 783 | dma->tx_err = 1; | 783 | dma->tx_err = 1; |
| 784 | p->ier |= UART_IER_THRI; | 784 | p->ier |= UART_IER_THRI; |
| 785 | serial_port_out(&p->port, UART_IER, p->ier); | 785 | serial_port_out(&p->port, UART_IER, p->ier); |
| 786 | } | 786 | } |
| 787 | 787 | ||
| 788 | spin_unlock_irqrestore(&p->port.lock, flags); | 788 | spin_unlock_irqrestore(&p->port.lock, flags); |
| 789 | } | 789 | } |
| 790 | 790 | ||
| 791 | static int omap_8250_tx_dma(struct uart_8250_port *p) | 791 | static int omap_8250_tx_dma(struct uart_8250_port *p) |
| 792 | { | 792 | { |
| 793 | struct uart_8250_dma *dma = p->dma; | 793 | struct uart_8250_dma *dma = p->dma; |
| 794 | struct omap8250_priv *priv = p->port.private_data; | 794 | struct omap8250_priv *priv = p->port.private_data; |
| 795 | struct circ_buf *xmit = &p->port.state->xmit; | 795 | struct circ_buf *xmit = &p->port.state->xmit; |
| 796 | struct dma_async_tx_descriptor *desc; | 796 | struct dma_async_tx_descriptor *desc; |
| 797 | unsigned int skip_byte = 0; | 797 | unsigned int skip_byte = 0; |
| 798 | int ret; | 798 | int ret; |
| 799 | 799 | ||
| 800 | if (dma->tx_running) | 800 | if (dma->tx_running) |
| 801 | return 0; | 801 | return 0; |
| 802 | if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { | 802 | if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { |
| 803 | 803 | ||
| 804 | /* | 804 | /* |
| 805 | * Even if no data, we need to return an error for the two cases | 805 | * Even if no data, we need to return an error for the two cases |
| 806 | * below so serial8250_tx_chars() is invoked and properly clears | 806 | * below so serial8250_tx_chars() is invoked and properly clears |
| 807 | * THRI and/or runtime suspend. | 807 | * THRI and/or runtime suspend. |
| 808 | */ | 808 | */ |
| 809 | if (dma->tx_err || p->capabilities & UART_CAP_RPM) { | 809 | if (dma->tx_err || p->capabilities & UART_CAP_RPM) { |
| 810 | ret = -EBUSY; | 810 | ret = -EBUSY; |
| 811 | goto err; | 811 | goto err; |
| 812 | } | 812 | } |
| 813 | if (p->ier & UART_IER_THRI) { | 813 | if (p->ier & UART_IER_THRI) { |
| 814 | p->ier &= ~UART_IER_THRI; | 814 | p->ier &= ~UART_IER_THRI; |
| 815 | serial_out(p, UART_IER, p->ier); | 815 | serial_out(p, UART_IER, p->ier); |
| 816 | } | 816 | } |
| 817 | return 0; | 817 | return 0; |
| 818 | } | 818 | } |
| 819 | 819 | ||
| 820 | dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | 820 | dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
| 821 | if (priv->habit & OMAP_DMA_TX_KICK) { | 821 | if (priv->habit & OMAP_DMA_TX_KICK) { |
| 822 | u8 tx_lvl; | 822 | u8 tx_lvl; |
| 823 | 823 | ||
| 824 | /* | 824 | /* |
| 825 | * We need to put the first byte into the FIFO in order to start | 825 | * We need to put the first byte into the FIFO in order to start |
| 826 | * the DMA transfer. For transfers smaller than four bytes we | 826 | * the DMA transfer. For transfers smaller than four bytes we |
| 827 | * don't bother doing DMA at all. It seem not matter if there | 827 | * don't bother doing DMA at all. It seem not matter if there |
| 828 | * are still bytes in the FIFO from the last transfer (in case | 828 | * are still bytes in the FIFO from the last transfer (in case |
| 829 | * we got here directly from omap_8250_dma_tx_complete()). Bytes | 829 | * we got here directly from omap_8250_dma_tx_complete()). Bytes |
| 830 | * leaving the FIFO seem not to trigger the DMA transfer. It is | 830 | * leaving the FIFO seem not to trigger the DMA transfer. It is |
| 831 | * really the byte that we put into the FIFO. | 831 | * really the byte that we put into the FIFO. |
| 832 | * If the FIFO is already full then we most likely got here from | 832 | * If the FIFO is already full then we most likely got here from |
| 833 | * omap_8250_dma_tx_complete(). And this means the DMA engine | 833 | * omap_8250_dma_tx_complete(). And this means the DMA engine |
| 834 | * just completed its work. We don't have to wait the complete | 834 | * just completed its work. We don't have to wait the complete |
| 835 | * 86us at 115200,8n1 but around 60us (not to mention lower | 835 | * 86us at 115200,8n1 but around 60us (not to mention lower |
| 836 | * baudrates). So in that case we take the interrupt and try | 836 | * baudrates). So in that case we take the interrupt and try |
| 837 | * again with an empty FIFO. | 837 | * again with an empty FIFO. |
| 838 | */ | 838 | */ |
| 839 | tx_lvl = serial_in(p, UART_OMAP_TX_LVL); | 839 | tx_lvl = serial_in(p, UART_OMAP_TX_LVL); |
| 840 | if (tx_lvl == p->tx_loadsz) { | 840 | if (tx_lvl == p->tx_loadsz) { |
| 841 | ret = -EBUSY; | 841 | ret = -EBUSY; |
| 842 | goto err; | 842 | goto err; |
| 843 | } | 843 | } |
| 844 | if (dma->tx_size < 4) { | 844 | if (dma->tx_size < 4) { |
| 845 | ret = -EINVAL; | 845 | ret = -EINVAL; |
| 846 | goto err; | 846 | goto err; |
| 847 | } | 847 | } |
| 848 | skip_byte = 1; | 848 | skip_byte = 1; |
| 849 | } | 849 | } |
| 850 | 850 | ||
| 851 | desc = dmaengine_prep_slave_single(dma->txchan, | 851 | desc = dmaengine_prep_slave_single(dma->txchan, |
| 852 | dma->tx_addr + xmit->tail + skip_byte, | 852 | dma->tx_addr + xmit->tail + skip_byte, |
| 853 | dma->tx_size - skip_byte, DMA_MEM_TO_DEV, | 853 | dma->tx_size - skip_byte, DMA_MEM_TO_DEV, |
| 854 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 854 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 855 | if (!desc) { | 855 | if (!desc) { |
| 856 | ret = -EBUSY; | 856 | ret = -EBUSY; |
| 857 | goto err; | 857 | goto err; |
| 858 | } | 858 | } |
| 859 | 859 | ||
| 860 | dma->tx_running = 1; | 860 | dma->tx_running = 1; |
| 861 | 861 | ||
| 862 | desc->callback = omap_8250_dma_tx_complete; | 862 | desc->callback = omap_8250_dma_tx_complete; |
| 863 | desc->callback_param = p; | 863 | desc->callback_param = p; |
| 864 | 864 | ||
| 865 | dma->tx_cookie = dmaengine_submit(desc); | 865 | dma->tx_cookie = dmaengine_submit(desc); |
| 866 | 866 | ||
| 867 | dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, | 867 | dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, |
| 868 | UART_XMIT_SIZE, DMA_TO_DEVICE); | 868 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
| 869 | 869 | ||
| 870 | dma_async_issue_pending(dma->txchan); | 870 | dma_async_issue_pending(dma->txchan); |
| 871 | if (dma->tx_err) | 871 | if (dma->tx_err) |
| 872 | dma->tx_err = 0; | 872 | dma->tx_err = 0; |
| 873 | 873 | ||
| 874 | if (p->ier & UART_IER_THRI) { | 874 | if (p->ier & UART_IER_THRI) { |
| 875 | p->ier &= ~UART_IER_THRI; | 875 | p->ier &= ~UART_IER_THRI; |
| 876 | serial_out(p, UART_IER, p->ier); | 876 | serial_out(p, UART_IER, p->ier); |
| 877 | } | 877 | } |
| 878 | if (skip_byte) | 878 | if (skip_byte) |
| 879 | serial_out(p, UART_TX, xmit->buf[xmit->tail]); | 879 | serial_out(p, UART_TX, xmit->buf[xmit->tail]); |
| 880 | return 0; | 880 | return 0; |
| 881 | err: | 881 | err: |
| 882 | dma->tx_err = 1; | 882 | dma->tx_err = 1; |
| 883 | return ret; | 883 | return ret; |
| 884 | } | 884 | } |
| 885 | 885 | ||
| 886 | /* | 886 | /* |
| 887 | * This is mostly serial8250_handle_irq(). We have a slightly different DMA | 887 | * This is mostly serial8250_handle_irq(). We have a slightly different DMA |
| 888 | * hoook for RX/TX and need different logic for them in the ISR. Therefore we | 888 | * hoook for RX/TX and need different logic for them in the ISR. Therefore we |
| 889 | * use the default routine in the non-DMA case and this one for with DMA. | 889 | * use the default routine in the non-DMA case and this one for with DMA. |
| 890 | */ | 890 | */ |
| 891 | static int omap_8250_dma_handle_irq(struct uart_port *port) | 891 | static int omap_8250_dma_handle_irq(struct uart_port *port) |
| 892 | { | 892 | { |
| 893 | struct uart_8250_port *up = up_to_u8250p(port); | 893 | struct uart_8250_port *up = up_to_u8250p(port); |
| 894 | unsigned char status; | 894 | unsigned char status; |
| 895 | unsigned long flags; | 895 | unsigned long flags; |
| 896 | u8 iir; | 896 | u8 iir; |
| 897 | int dma_err = 0; | 897 | int dma_err = 0; |
| 898 | 898 | ||
| 899 | serial8250_rpm_get(up); | 899 | serial8250_rpm_get(up); |
| 900 | 900 | ||
| 901 | iir = serial_port_in(port, UART_IIR); | 901 | iir = serial_port_in(port, UART_IIR); |
| 902 | if (iir & UART_IIR_NO_INT) { | 902 | if (iir & UART_IIR_NO_INT) { |
| 903 | serial8250_rpm_put(up); | 903 | serial8250_rpm_put(up); |
| 904 | return 0; | 904 | return 0; |
| 905 | } | 905 | } |
| 906 | 906 | ||
| 907 | spin_lock_irqsave(&port->lock, flags); | 907 | spin_lock_irqsave(&port->lock, flags); |
| 908 | 908 | ||
| 909 | status = serial_port_in(port, UART_LSR); | 909 | status = serial_port_in(port, UART_LSR); |
| 910 | 910 | ||
| 911 | if (status & (UART_LSR_DR | UART_LSR_BI)) { | 911 | if (status & (UART_LSR_DR | UART_LSR_BI)) { |
| 912 | 912 | ||
| 913 | dma_err = omap_8250_rx_dma(up, iir); | 913 | dma_err = omap_8250_rx_dma(up, iir); |
| 914 | if (dma_err) { | 914 | if (dma_err) { |
| 915 | status = serial8250_rx_chars(up, status); | 915 | status = serial8250_rx_chars(up, status); |
| 916 | omap_8250_rx_dma(up, 0); | 916 | omap_8250_rx_dma(up, 0); |
| 917 | } | 917 | } |
| 918 | } | 918 | } |
| 919 | serial8250_modem_status(up); | 919 | serial8250_modem_status(up); |
| 920 | if (status & UART_LSR_THRE && up->dma->tx_err) { | 920 | if (status & UART_LSR_THRE && up->dma->tx_err) { |
| 921 | if (uart_tx_stopped(&up->port) || | 921 | if (uart_tx_stopped(&up->port) || |
| 922 | uart_circ_empty(&up->port.state->xmit)) { | 922 | uart_circ_empty(&up->port.state->xmit)) { |
| 923 | up->dma->tx_err = 0; | 923 | up->dma->tx_err = 0; |
| 924 | serial8250_tx_chars(up); | 924 | serial8250_tx_chars(up); |
| 925 | } else { | 925 | } else { |
| 926 | /* | 926 | /* |
| 927 | * try again due to an earlier failer which | 927 | * try again due to an earlier failer which |
| 928 | * might have been resolved by now. | 928 | * might have been resolved by now. |
| 929 | */ | 929 | */ |
| 930 | dma_err = omap_8250_tx_dma(up); | 930 | dma_err = omap_8250_tx_dma(up); |
| 931 | if (dma_err) | 931 | if (dma_err) |
| 932 | serial8250_tx_chars(up); | 932 | serial8250_tx_chars(up); |
| 933 | } | 933 | } |
| 934 | } | 934 | } |
| 935 | 935 | ||
| 936 | spin_unlock_irqrestore(&port->lock, flags); | 936 | spin_unlock_irqrestore(&port->lock, flags); |
| 937 | serial8250_rpm_put(up); | 937 | serial8250_rpm_put(up); |
| 938 | return 1; | 938 | return 1; |
| 939 | } | 939 | } |
| 940 | 940 | ||
| 941 | static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) | 941 | static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) |
| 942 | { | 942 | { |
| 943 | return false; | 943 | return false; |
| 944 | } | 944 | } |
| 945 | 945 | ||
| 946 | #else | 946 | #else |
| 947 | 947 | ||
| 948 | static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) | 948 | static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) |
| 949 | { | 949 | { |
| 950 | return -EINVAL; | 950 | return -EINVAL; |
| 951 | } | 951 | } |
| 952 | #endif | 952 | #endif |
| 953 | 953 | ||
| 954 | static int omap8250_probe(struct platform_device *pdev) | 954 | static int omap8250_probe(struct platform_device *pdev) |
| 955 | { | 955 | { |
| 956 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 956 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 957 | struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 957 | struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 958 | struct omap8250_priv *priv; | 958 | struct omap8250_priv *priv; |
| 959 | struct uart_8250_port up; | 959 | struct uart_8250_port up; |
| 960 | int ret; | 960 | int ret; |
| 961 | void __iomem *membase; | 961 | void __iomem *membase; |
| 962 | 962 | ||
| 963 | if (!regs || !irq) { | 963 | if (!regs || !irq) { |
| 964 | dev_err(&pdev->dev, "missing registers or irq\n"); | 964 | dev_err(&pdev->dev, "missing registers or irq\n"); |
| 965 | return -EINVAL; | 965 | return -EINVAL; |
| 966 | } | 966 | } |
| 967 | 967 | ||
| 968 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | 968 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 969 | if (!priv) | 969 | if (!priv) |
| 970 | return -ENOMEM; | 970 | return -ENOMEM; |
| 971 | 971 | ||
| 972 | membase = devm_ioremap_nocache(&pdev->dev, regs->start, | 972 | membase = devm_ioremap_nocache(&pdev->dev, regs->start, |
| 973 | resource_size(regs)); | 973 | resource_size(regs)); |
| 974 | if (!membase) | 974 | if (!membase) |
| 975 | return -ENODEV; | 975 | return -ENODEV; |
| 976 | 976 | ||
| 977 | memset(&up, 0, sizeof(up)); | 977 | memset(&up, 0, sizeof(up)); |
| 978 | up.port.dev = &pdev->dev; | 978 | up.port.dev = &pdev->dev; |
| 979 | up.port.mapbase = regs->start; | 979 | up.port.mapbase = regs->start; |
| 980 | up.port.membase = membase; | 980 | up.port.membase = membase; |
| 981 | up.port.irq = irq->start; | 981 | up.port.irq = irq->start; |
| 982 | /* | 982 | /* |
| 983 | * It claims to be 16C750 compatible however it is a little different. | 983 | * It claims to be 16C750 compatible however it is a little different. |
| 984 | * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to | 984 | * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to |
| 985 | * have) is enabled via EFR instead of MCR. The type is set here 8250 | 985 | * have) is enabled via EFR instead of MCR. The type is set here 8250 |
| 986 | * just to get things going. UNKNOWN does not work for a few reasons and | 986 | * just to get things going. UNKNOWN does not work for a few reasons and |
| 987 | * we don't need our own type since we don't use 8250's set_termios() | 987 | * we don't need our own type since we don't use 8250's set_termios() |
| 988 | * or pm callback. | 988 | * or pm callback. |
| 989 | */ | 989 | */ |
| 990 | up.port.type = PORT_8250; | 990 | up.port.type = PORT_8250; |
| 991 | up.port.iotype = UPIO_MEM; | 991 | up.port.iotype = UPIO_MEM; |
| 992 | up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | | 992 | up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | |
| 993 | UPF_HARD_FLOW; | 993 | UPF_HARD_FLOW; |
| 994 | up.port.private_data = priv; | 994 | up.port.private_data = priv; |
| 995 | 995 | ||
| 996 | up.port.regshift = 2; | 996 | up.port.regshift = 2; |
| 997 | up.port.fifosize = 64; | 997 | up.port.fifosize = 64; |
| 998 | up.tx_loadsz = 64; | 998 | up.tx_loadsz = 64; |
| 999 | up.capabilities = UART_CAP_FIFO; | 999 | up.capabilities = UART_CAP_FIFO; |
| 1000 | #ifdef CONFIG_PM_RUNTIME | 1000 | #ifdef CONFIG_PM |
| 1001 | /* | 1001 | /* |
| 1002 | * PM_RUNTIME is mostly transparent. However to do it right we need to a | 1002 | * Runtime PM is mostly transparent. However to do it right we need to a |
| 1003 | * TX empty interrupt before we can put the device to auto idle. So if | 1003 | * TX empty interrupt before we can put the device to auto idle. So if |
| 1004 | * PM_RUNTIME is not enabled we don't add that flag and can spare that | 1004 | * PM is not enabled we don't add that flag and can spare that one extra |
| 1005 | * one extra interrupt in the TX path. | 1005 | * interrupt in the TX path. |
| 1006 | */ | 1006 | */ |
| 1007 | up.capabilities |= UART_CAP_RPM; | 1007 | up.capabilities |= UART_CAP_RPM; |
| 1008 | #endif | 1008 | #endif |
| 1009 | up.port.set_termios = omap_8250_set_termios; | 1009 | up.port.set_termios = omap_8250_set_termios; |
| 1010 | up.port.pm = omap_8250_pm; | 1010 | up.port.pm = omap_8250_pm; |
| 1011 | up.port.startup = omap_8250_startup; | 1011 | up.port.startup = omap_8250_startup; |
| 1012 | up.port.shutdown = omap_8250_shutdown; | 1012 | up.port.shutdown = omap_8250_shutdown; |
| 1013 | up.port.throttle = omap_8250_throttle; | 1013 | up.port.throttle = omap_8250_throttle; |
| 1014 | up.port.unthrottle = omap_8250_unthrottle; | 1014 | up.port.unthrottle = omap_8250_unthrottle; |
| 1015 | 1015 | ||
| 1016 | if (pdev->dev.of_node) { | 1016 | if (pdev->dev.of_node) { |
| 1017 | ret = of_alias_get_id(pdev->dev.of_node, "serial"); | 1017 | ret = of_alias_get_id(pdev->dev.of_node, "serial"); |
| 1018 | 1018 | ||
| 1019 | of_property_read_u32(pdev->dev.of_node, "clock-frequency", | 1019 | of_property_read_u32(pdev->dev.of_node, "clock-frequency", |
| 1020 | &up.port.uartclk); | 1020 | &up.port.uartclk); |
| 1021 | priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); | 1021 | priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); |
| 1022 | } else { | 1022 | } else { |
| 1023 | ret = pdev->id; | 1023 | ret = pdev->id; |
| 1024 | } | 1024 | } |
| 1025 | if (ret < 0) { | 1025 | if (ret < 0) { |
| 1026 | dev_err(&pdev->dev, "failed to get alias/pdev id\n"); | 1026 | dev_err(&pdev->dev, "failed to get alias/pdev id\n"); |
| 1027 | return ret; | 1027 | return ret; |
| 1028 | } | 1028 | } |
| 1029 | up.port.line = ret; | 1029 | up.port.line = ret; |
| 1030 | 1030 | ||
| 1031 | if (!up.port.uartclk) { | 1031 | if (!up.port.uartclk) { |
| 1032 | up.port.uartclk = DEFAULT_CLK_SPEED; | 1032 | up.port.uartclk = DEFAULT_CLK_SPEED; |
| 1033 | dev_warn(&pdev->dev, | 1033 | dev_warn(&pdev->dev, |
| 1034 | "No clock speed specified: using default: %d\n", | 1034 | "No clock speed specified: using default: %d\n", |
| 1035 | DEFAULT_CLK_SPEED); | 1035 | DEFAULT_CLK_SPEED); |
| 1036 | } | 1036 | } |
| 1037 | 1037 | ||
| 1038 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | 1038 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
| 1039 | priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | 1039 | priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
| 1040 | pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, | 1040 | pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, |
| 1041 | priv->latency); | 1041 | priv->latency); |
| 1042 | INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); | 1042 | INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); |
| 1043 | 1043 | ||
| 1044 | device_init_wakeup(&pdev->dev, true); | 1044 | device_init_wakeup(&pdev->dev, true); |
| 1045 | pm_runtime_use_autosuspend(&pdev->dev); | 1045 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1046 | pm_runtime_set_autosuspend_delay(&pdev->dev, -1); | 1046 | pm_runtime_set_autosuspend_delay(&pdev->dev, -1); |
| 1047 | 1047 | ||
| 1048 | pm_runtime_irq_safe(&pdev->dev); | 1048 | pm_runtime_irq_safe(&pdev->dev); |
| 1049 | pm_runtime_enable(&pdev->dev); | 1049 | pm_runtime_enable(&pdev->dev); |
| 1050 | 1050 | ||
| 1051 | pm_runtime_get_sync(&pdev->dev); | 1051 | pm_runtime_get_sync(&pdev->dev); |
| 1052 | 1052 | ||
| 1053 | omap_serial_fill_features_erratas(&up, priv); | 1053 | omap_serial_fill_features_erratas(&up, priv); |
| 1054 | #ifdef CONFIG_SERIAL_8250_DMA | 1054 | #ifdef CONFIG_SERIAL_8250_DMA |
| 1055 | if (pdev->dev.of_node) { | 1055 | if (pdev->dev.of_node) { |
| 1056 | /* | 1056 | /* |
| 1057 | * Oh DMA support. If there are no DMA properties in the DT then | 1057 | * Oh DMA support. If there are no DMA properties in the DT then |
| 1058 | * we will fall back to a generic DMA channel which does not | 1058 | * we will fall back to a generic DMA channel which does not |
| 1059 | * really work here. To ensure that we do not get a generic DMA | 1059 | * really work here. To ensure that we do not get a generic DMA |
| 1060 | * channel assigned, we have the the_no_dma_filter_fn() here. | 1060 | * channel assigned, we have the the_no_dma_filter_fn() here. |
| 1061 | * To avoid "failed to request DMA" messages we check for DMA | 1061 | * To avoid "failed to request DMA" messages we check for DMA |
| 1062 | * properties in DT. | 1062 | * properties in DT. |
| 1063 | */ | 1063 | */ |
| 1064 | ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); | 1064 | ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); |
| 1065 | if (ret == 2) { | 1065 | if (ret == 2) { |
| 1066 | up.dma = &priv->omap8250_dma; | 1066 | up.dma = &priv->omap8250_dma; |
| 1067 | up.port.handle_irq = omap_8250_dma_handle_irq; | 1067 | up.port.handle_irq = omap_8250_dma_handle_irq; |
| 1068 | priv->omap8250_dma.fn = the_no_dma_filter_fn; | 1068 | priv->omap8250_dma.fn = the_no_dma_filter_fn; |
| 1069 | priv->omap8250_dma.tx_dma = omap_8250_tx_dma; | 1069 | priv->omap8250_dma.tx_dma = omap_8250_tx_dma; |
| 1070 | priv->omap8250_dma.rx_dma = omap_8250_rx_dma; | 1070 | priv->omap8250_dma.rx_dma = omap_8250_rx_dma; |
| 1071 | priv->omap8250_dma.rx_size = RX_TRIGGER; | 1071 | priv->omap8250_dma.rx_size = RX_TRIGGER; |
| 1072 | priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; | 1072 | priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; |
| 1073 | priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; | 1073 | priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; |
| 1074 | 1074 | ||
| 1075 | if (of_machine_is_compatible("ti,am33xx")) | 1075 | if (of_machine_is_compatible("ti,am33xx")) |
| 1076 | priv->habit |= OMAP_DMA_TX_KICK; | 1076 | priv->habit |= OMAP_DMA_TX_KICK; |
| 1077 | } | 1077 | } |
| 1078 | } | 1078 | } |
| 1079 | #endif | 1079 | #endif |
| 1080 | ret = serial8250_register_8250_port(&up); | 1080 | ret = serial8250_register_8250_port(&up); |
| 1081 | if (ret < 0) { | 1081 | if (ret < 0) { |
| 1082 | dev_err(&pdev->dev, "unable to register 8250 port\n"); | 1082 | dev_err(&pdev->dev, "unable to register 8250 port\n"); |
| 1083 | goto err; | 1083 | goto err; |
| 1084 | } | 1084 | } |
| 1085 | priv->line = ret; | 1085 | priv->line = ret; |
| 1086 | platform_set_drvdata(pdev, priv); | 1086 | platform_set_drvdata(pdev, priv); |
| 1087 | pm_runtime_mark_last_busy(&pdev->dev); | 1087 | pm_runtime_mark_last_busy(&pdev->dev); |
| 1088 | pm_runtime_put_autosuspend(&pdev->dev); | 1088 | pm_runtime_put_autosuspend(&pdev->dev); |
| 1089 | return 0; | 1089 | return 0; |
| 1090 | err: | 1090 | err: |
| 1091 | pm_runtime_put(&pdev->dev); | 1091 | pm_runtime_put(&pdev->dev); |
| 1092 | pm_runtime_disable(&pdev->dev); | 1092 | pm_runtime_disable(&pdev->dev); |
| 1093 | return ret; | 1093 | return ret; |
| 1094 | } | 1094 | } |
| 1095 | 1095 | ||
| 1096 | static int omap8250_remove(struct platform_device *pdev) | 1096 | static int omap8250_remove(struct platform_device *pdev) |
| 1097 | { | 1097 | { |
| 1098 | struct omap8250_priv *priv = platform_get_drvdata(pdev); | 1098 | struct omap8250_priv *priv = platform_get_drvdata(pdev); |
| 1099 | 1099 | ||
| 1100 | pm_runtime_put_sync(&pdev->dev); | 1100 | pm_runtime_put_sync(&pdev->dev); |
| 1101 | pm_runtime_disable(&pdev->dev); | 1101 | pm_runtime_disable(&pdev->dev); |
| 1102 | serial8250_unregister_port(priv->line); | 1102 | serial8250_unregister_port(priv->line); |
| 1103 | pm_qos_remove_request(&priv->pm_qos_request); | 1103 | pm_qos_remove_request(&priv->pm_qos_request); |
| 1104 | device_init_wakeup(&pdev->dev, false); | 1104 | device_init_wakeup(&pdev->dev, false); |
| 1105 | return 0; | 1105 | return 0; |
| 1106 | } | 1106 | } |
| 1107 | 1107 | ||
| 1108 | #if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM_RUNTIME) | 1108 | #ifdef CONFIG_PM |
| 1109 | 1109 | ||
| 1110 | static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv, | 1110 | static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv, |
| 1111 | bool enable) | 1111 | bool enable) |
| 1112 | { | 1112 | { |
| 1113 | if (!priv->wakeirq) | 1113 | if (!priv->wakeirq) |
| 1114 | return; | 1114 | return; |
| 1115 | 1115 | ||
| 1116 | if (enable) | 1116 | if (enable) |
| 1117 | enable_irq(priv->wakeirq); | 1117 | enable_irq(priv->wakeirq); |
| 1118 | else | 1118 | else |
| 1119 | disable_irq_nosync(priv->wakeirq); | 1119 | disable_irq_nosync(priv->wakeirq); |
| 1120 | } | 1120 | } |
| 1121 | 1121 | ||
| 1122 | static void omap8250_enable_wakeup(struct omap8250_priv *priv, | 1122 | static void omap8250_enable_wakeup(struct omap8250_priv *priv, |
| 1123 | bool enable) | 1123 | bool enable) |
| 1124 | { | 1124 | { |
| 1125 | if (enable == priv->wakeups_enabled) | 1125 | if (enable == priv->wakeups_enabled) |
| 1126 | return; | 1126 | return; |
| 1127 | 1127 | ||
| 1128 | omap8250_enable_wakeirq(priv, enable); | 1128 | omap8250_enable_wakeirq(priv, enable); |
| 1129 | priv->wakeups_enabled = enable; | 1129 | priv->wakeups_enabled = enable; |
| 1130 | } | 1130 | } |
| 1131 | #endif | 1131 | #endif |
| 1132 | 1132 | ||
| 1133 | #ifdef CONFIG_PM_SLEEP | 1133 | #ifdef CONFIG_PM_SLEEP |
| 1134 | static int omap8250_prepare(struct device *dev) | 1134 | static int omap8250_prepare(struct device *dev) |
| 1135 | { | 1135 | { |
| 1136 | struct omap8250_priv *priv = dev_get_drvdata(dev); | 1136 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1137 | 1137 | ||
| 1138 | if (!priv) | 1138 | if (!priv) |
| 1139 | return 0; | 1139 | return 0; |
| 1140 | priv->is_suspending = true; | 1140 | priv->is_suspending = true; |
| 1141 | return 0; | 1141 | return 0; |
| 1142 | } | 1142 | } |
| 1143 | 1143 | ||
| 1144 | static void omap8250_complete(struct device *dev) | 1144 | static void omap8250_complete(struct device *dev) |
| 1145 | { | 1145 | { |
| 1146 | struct omap8250_priv *priv = dev_get_drvdata(dev); | 1146 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1147 | 1147 | ||
| 1148 | if (!priv) | 1148 | if (!priv) |
| 1149 | return; | 1149 | return; |
| 1150 | priv->is_suspending = false; | 1150 | priv->is_suspending = false; |
| 1151 | } | 1151 | } |
| 1152 | 1152 | ||
| 1153 | static int omap8250_suspend(struct device *dev) | 1153 | static int omap8250_suspend(struct device *dev) |
| 1154 | { | 1154 | { |
| 1155 | struct omap8250_priv *priv = dev_get_drvdata(dev); | 1155 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1156 | 1156 | ||
| 1157 | serial8250_suspend_port(priv->line); | 1157 | serial8250_suspend_port(priv->line); |
| 1158 | flush_work(&priv->qos_work); | 1158 | flush_work(&priv->qos_work); |
| 1159 | 1159 | ||
| 1160 | if (device_may_wakeup(dev)) | 1160 | if (device_may_wakeup(dev)) |
| 1161 | omap8250_enable_wakeup(priv, true); | 1161 | omap8250_enable_wakeup(priv, true); |
| 1162 | else | 1162 | else |
| 1163 | omap8250_enable_wakeup(priv, false); | 1163 | omap8250_enable_wakeup(priv, false); |
| 1164 | return 0; | 1164 | return 0; |
| 1165 | } | 1165 | } |
| 1166 | 1166 | ||
| 1167 | static int omap8250_resume(struct device *dev) | 1167 | static int omap8250_resume(struct device *dev) |
| 1168 | { | 1168 | { |
| 1169 | struct omap8250_priv *priv = dev_get_drvdata(dev); | 1169 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1170 | 1170 | ||
| 1171 | if (device_may_wakeup(dev)) | 1171 | if (device_may_wakeup(dev)) |
| 1172 | omap8250_enable_wakeup(priv, false); | 1172 | omap8250_enable_wakeup(priv, false); |
| 1173 | 1173 | ||
| 1174 | serial8250_resume_port(priv->line); | 1174 | serial8250_resume_port(priv->line); |
| 1175 | return 0; | 1175 | return 0; |
| 1176 | } | 1176 | } |
| 1177 | #else | 1177 | #else |
| 1178 | #define omap8250_prepare NULL | 1178 | #define omap8250_prepare NULL |
| 1179 | #define omap8250_complete NULL | 1179 | #define omap8250_complete NULL |
| 1180 | #endif | 1180 | #endif |
| 1181 | 1181 | ||
| 1182 | #ifdef CONFIG_PM_RUNTIME | 1182 | #ifdef CONFIG_PM |
| 1183 | static int omap8250_lost_context(struct uart_8250_port *up) | 1183 | static int omap8250_lost_context(struct uart_8250_port *up) |
| 1184 | { | 1184 | { |
| 1185 | u32 val; | 1185 | u32 val; |
| 1186 | 1186 | ||
| 1187 | val = serial_in(up, UART_OMAP_MDR1); | 1187 | val = serial_in(up, UART_OMAP_MDR1); |
| 1188 | /* | 1188 | /* |
| 1189 | * If we lose context, then MDR1 is set to its reset value which is | 1189 | * If we lose context, then MDR1 is set to its reset value which is |
| 1190 | * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x | 1190 | * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x |
| 1191 | * or 16x but never to disable again. | 1191 | * or 16x but never to disable again. |
| 1192 | */ | 1192 | */ |
| 1193 | if (val == UART_OMAP_MDR1_DISABLE) | 1193 | if (val == UART_OMAP_MDR1_DISABLE) |
| 1194 | return 1; | 1194 | return 1; |
| 1195 | return 0; | 1195 | return 0; |
| 1196 | } | 1196 | } |
| 1197 | 1197 | ||
| 1198 | static int omap8250_runtime_suspend(struct device *dev) | 1198 | static int omap8250_runtime_suspend(struct device *dev) |
| 1199 | { | 1199 | { |
| 1200 | struct omap8250_priv *priv = dev_get_drvdata(dev); | 1200 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1201 | struct uart_8250_port *up; | 1201 | struct uart_8250_port *up; |
| 1202 | 1202 | ||
| 1203 | up = serial8250_get_port(priv->line); | 1203 | up = serial8250_get_port(priv->line); |
| 1204 | /* | 1204 | /* |
| 1205 | * When using 'no_console_suspend', the console UART must not be | 1205 | * When using 'no_console_suspend', the console UART must not be |
| 1206 | * suspended. Since driver suspend is managed by runtime suspend, | 1206 | * suspended. Since driver suspend is managed by runtime suspend, |
| 1207 | * preventing runtime suspend (by returning error) will keep device | 1207 | * preventing runtime suspend (by returning error) will keep device |
| 1208 | * active during suspend. | 1208 | * active during suspend. |
| 1209 | */ | 1209 | */ |
| 1210 | if (priv->is_suspending && !console_suspend_enabled) { | 1210 | if (priv->is_suspending && !console_suspend_enabled) { |
| 1211 | if (uart_console(&up->port)) | 1211 | if (uart_console(&up->port)) |
| 1212 | return -EBUSY; | 1212 | return -EBUSY; |
| 1213 | } | 1213 | } |
| 1214 | 1214 | ||
| 1215 | omap8250_enable_wakeup(priv, true); | 1215 | omap8250_enable_wakeup(priv, true); |
| 1216 | if (up->dma) | 1216 | if (up->dma) |
| 1217 | omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); | 1217 | omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); |
| 1218 | 1218 | ||
| 1219 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | 1219 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
| 1220 | schedule_work(&priv->qos_work); | 1220 | schedule_work(&priv->qos_work); |
| 1221 | 1221 | ||
| 1222 | return 0; | 1222 | return 0; |
| 1223 | } | 1223 | } |
| 1224 | 1224 | ||
| 1225 | static int omap8250_runtime_resume(struct device *dev) | 1225 | static int omap8250_runtime_resume(struct device *dev) |
| 1226 | { | 1226 | { |
| 1227 | struct omap8250_priv *priv = dev_get_drvdata(dev); | 1227 | struct omap8250_priv *priv = dev_get_drvdata(dev); |
| 1228 | struct uart_8250_port *up; | 1228 | struct uart_8250_port *up; |
| 1229 | int loss_cntx; | 1229 | int loss_cntx; |
| 1230 | 1230 | ||
| 1231 | /* In case runtime-pm tries this before we are setup */ | 1231 | /* In case runtime-pm tries this before we are setup */ |
| 1232 | if (!priv) | 1232 | if (!priv) |
| 1233 | return 0; | 1233 | return 0; |
| 1234 | 1234 | ||
| 1235 | up = serial8250_get_port(priv->line); | 1235 | up = serial8250_get_port(priv->line); |
| 1236 | omap8250_enable_wakeup(priv, false); | 1236 | omap8250_enable_wakeup(priv, false); |
| 1237 | loss_cntx = omap8250_lost_context(up); | 1237 | loss_cntx = omap8250_lost_context(up); |
| 1238 | 1238 | ||
| 1239 | if (loss_cntx) | 1239 | if (loss_cntx) |
| 1240 | omap8250_restore_regs(up); | 1240 | omap8250_restore_regs(up); |
| 1241 | 1241 | ||
| 1242 | if (up->dma) | 1242 | if (up->dma) |
| 1243 | omap_8250_rx_dma(up, 0); | 1243 | omap_8250_rx_dma(up, 0); |
| 1244 | 1244 | ||
| 1245 | priv->latency = priv->calc_latency; | 1245 | priv->latency = priv->calc_latency; |
| 1246 | schedule_work(&priv->qos_work); | 1246 | schedule_work(&priv->qos_work); |
| 1247 | return 0; | 1247 | return 0; |
| 1248 | } | 1248 | } |
| 1249 | #endif | 1249 | #endif |
| 1250 | 1250 | ||
| 1251 | static const struct dev_pm_ops omap8250_dev_pm_ops = { | 1251 | static const struct dev_pm_ops omap8250_dev_pm_ops = { |
| 1252 | SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) | 1252 | SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) |
| 1253 | SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, | 1253 | SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, |
| 1254 | omap8250_runtime_resume, NULL) | 1254 | omap8250_runtime_resume, NULL) |
| 1255 | .prepare = omap8250_prepare, | 1255 | .prepare = omap8250_prepare, |
| 1256 | .complete = omap8250_complete, | 1256 | .complete = omap8250_complete, |
| 1257 | }; | 1257 | }; |
| 1258 | 1258 | ||
| 1259 | static const struct of_device_id omap8250_dt_ids[] = { | 1259 | static const struct of_device_id omap8250_dt_ids[] = { |
| 1260 | { .compatible = "ti,omap2-uart" }, | 1260 | { .compatible = "ti,omap2-uart" }, |
| 1261 | { .compatible = "ti,omap3-uart" }, | 1261 | { .compatible = "ti,omap3-uart" }, |
| 1262 | { .compatible = "ti,omap4-uart" }, | 1262 | { .compatible = "ti,omap4-uart" }, |
| 1263 | {}, | 1263 | {}, |
| 1264 | }; | 1264 | }; |
| 1265 | MODULE_DEVICE_TABLE(of, omap8250_dt_ids); | 1265 | MODULE_DEVICE_TABLE(of, omap8250_dt_ids); |
| 1266 | 1266 | ||
| 1267 | static struct platform_driver omap8250_platform_driver = { | 1267 | static struct platform_driver omap8250_platform_driver = { |
| 1268 | .driver = { | 1268 | .driver = { |
| 1269 | .name = "omap8250", | 1269 | .name = "omap8250", |
| 1270 | .pm = &omap8250_dev_pm_ops, | 1270 | .pm = &omap8250_dev_pm_ops, |
| 1271 | .of_match_table = omap8250_dt_ids, | 1271 | .of_match_table = omap8250_dt_ids, |
| 1272 | .owner = THIS_MODULE, | 1272 | .owner = THIS_MODULE, |
| 1273 | }, | 1273 | }, |
| 1274 | .probe = omap8250_probe, | 1274 | .probe = omap8250_probe, |
| 1275 | .remove = omap8250_remove, | 1275 | .remove = omap8250_remove, |
| 1276 | }; | 1276 | }; |
| 1277 | module_platform_driver(omap8250_platform_driver); | 1277 | module_platform_driver(omap8250_platform_driver); |
| 1278 | 1278 | ||
| 1279 | MODULE_AUTHOR("Sebastian Andrzej Siewior"); | 1279 | MODULE_AUTHOR("Sebastian Andrzej Siewior"); |
| 1280 | MODULE_DESCRIPTION("OMAP 8250 Driver"); | 1280 | MODULE_DESCRIPTION("OMAP 8250 Driver"); |
| 1281 | MODULE_LICENSE("GPL v2"); | 1281 | MODULE_LICENSE("GPL v2"); |
| 1282 | 1282 |
drivers/usb/host/isp1760-hcd.c
| 1 | /* | 1 | /* |
| 2 | * Driver for the NXP ISP1760 chip | 2 | * Driver for the NXP ISP1760 chip |
| 3 | * | 3 | * |
| 4 | * However, the code might contain some bugs. What doesn't work for sure is: | 4 | * However, the code might contain some bugs. What doesn't work for sure is: |
| 5 | * - ISO | 5 | * - ISO |
| 6 | * - OTG | 6 | * - OTG |
| 7 | e The interrupt line is configured as active low, level. | 7 | e The interrupt line is configured as active low, level. |
| 8 | * | 8 | * |
| 9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | 9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> |
| 10 | * | 10 | * |
| 11 | * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> | 11 | * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> |
| 12 | * | 12 | * |
| 13 | */ | 13 | */ |
| 14 | #include <linux/module.h> | 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/slab.h> | 16 | #include <linux/slab.h> |
| 17 | #include <linux/list.h> | 17 | #include <linux/list.h> |
| 18 | #include <linux/usb.h> | 18 | #include <linux/usb.h> |
| 19 | #include <linux/usb/hcd.h> | 19 | #include <linux/usb/hcd.h> |
| 20 | #include <linux/debugfs.h> | 20 | #include <linux/debugfs.h> |
| 21 | #include <linux/uaccess.h> | 21 | #include <linux/uaccess.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/mm.h> | 23 | #include <linux/mm.h> |
| 24 | #include <linux/timer.h> | 24 | #include <linux/timer.h> |
| 25 | #include <asm/unaligned.h> | 25 | #include <asm/unaligned.h> |
| 26 | #include <asm/cacheflush.h> | 26 | #include <asm/cacheflush.h> |
| 27 | #include <linux/gpio.h> | 27 | #include <linux/gpio.h> |
| 28 | 28 | ||
| 29 | #include "isp1760-hcd.h" | 29 | #include "isp1760-hcd.h" |
| 30 | 30 | ||
| 31 | static struct kmem_cache *qtd_cachep; | 31 | static struct kmem_cache *qtd_cachep; |
| 32 | static struct kmem_cache *qh_cachep; | 32 | static struct kmem_cache *qh_cachep; |
| 33 | static struct kmem_cache *urb_listitem_cachep; | 33 | static struct kmem_cache *urb_listitem_cachep; |
| 34 | 34 | ||
| 35 | enum queue_head_types { | 35 | enum queue_head_types { |
| 36 | QH_CONTROL, | 36 | QH_CONTROL, |
| 37 | QH_BULK, | 37 | QH_BULK, |
| 38 | QH_INTERRUPT, | 38 | QH_INTERRUPT, |
| 39 | QH_END | 39 | QH_END |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | struct isp1760_hcd { | 42 | struct isp1760_hcd { |
| 43 | u32 hcs_params; | 43 | u32 hcs_params; |
| 44 | spinlock_t lock; | 44 | spinlock_t lock; |
| 45 | struct slotinfo atl_slots[32]; | 45 | struct slotinfo atl_slots[32]; |
| 46 | int atl_done_map; | 46 | int atl_done_map; |
| 47 | struct slotinfo int_slots[32]; | 47 | struct slotinfo int_slots[32]; |
| 48 | int int_done_map; | 48 | int int_done_map; |
| 49 | struct memory_chunk memory_pool[BLOCKS]; | 49 | struct memory_chunk memory_pool[BLOCKS]; |
| 50 | struct list_head qh_list[QH_END]; | 50 | struct list_head qh_list[QH_END]; |
| 51 | 51 | ||
| 52 | /* periodic schedule support */ | 52 | /* periodic schedule support */ |
| 53 | #define DEFAULT_I_TDPS 1024 | 53 | #define DEFAULT_I_TDPS 1024 |
| 54 | unsigned periodic_size; | 54 | unsigned periodic_size; |
| 55 | unsigned i_thresh; | 55 | unsigned i_thresh; |
| 56 | unsigned long reset_done; | 56 | unsigned long reset_done; |
| 57 | unsigned long next_statechange; | 57 | unsigned long next_statechange; |
| 58 | unsigned int devflags; | 58 | unsigned int devflags; |
| 59 | 59 | ||
| 60 | int rst_gpio; | 60 | int rst_gpio; |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | 63 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) |
| 64 | { | 64 | { |
| 65 | return (struct isp1760_hcd *) (hcd->hcd_priv); | 65 | return (struct isp1760_hcd *) (hcd->hcd_priv); |
| 66 | } | 66 | } |
| 67 | 67 | ||
| 68 | /* Section 2.2 Host Controller Capability Registers */ | 68 | /* Section 2.2 Host Controller Capability Registers */ |
| 69 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ | 69 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
| 70 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ | 70 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ |
| 71 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ | 71 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ |
| 72 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ | 72 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ |
| 73 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ | 73 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
| 74 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ | 74 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ |
| 75 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ | 75 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ |
| 76 | 76 | ||
| 77 | /* Section 2.3 Host Controller Operational Registers */ | 77 | /* Section 2.3 Host Controller Operational Registers */ |
| 78 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ | 78 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ |
| 79 | #define CMD_RESET (1<<1) /* reset HC not bus */ | 79 | #define CMD_RESET (1<<1) /* reset HC not bus */ |
| 80 | #define CMD_RUN (1<<0) /* start/stop HC */ | 80 | #define CMD_RUN (1<<0) /* start/stop HC */ |
| 81 | #define STS_PCD (1<<2) /* port change detect */ | 81 | #define STS_PCD (1<<2) /* port change detect */ |
| 82 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ | 82 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ |
| 83 | 83 | ||
| 84 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ | 84 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ |
| 85 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ | 85 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ |
| 86 | #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ | 86 | #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ |
| 87 | #define PORT_RESET (1<<8) /* reset port */ | 87 | #define PORT_RESET (1<<8) /* reset port */ |
| 88 | #define PORT_SUSPEND (1<<7) /* suspend port */ | 88 | #define PORT_SUSPEND (1<<7) /* suspend port */ |
| 89 | #define PORT_RESUME (1<<6) /* resume it */ | 89 | #define PORT_RESUME (1<<6) /* resume it */ |
| 90 | #define PORT_PE (1<<2) /* port enable */ | 90 | #define PORT_PE (1<<2) /* port enable */ |
| 91 | #define PORT_CSC (1<<1) /* connect status change */ | 91 | #define PORT_CSC (1<<1) /* connect status change */ |
| 92 | #define PORT_CONNECT (1<<0) /* device connected */ | 92 | #define PORT_CONNECT (1<<0) /* device connected */ |
| 93 | #define PORT_RWC_BITS (PORT_CSC) | 93 | #define PORT_RWC_BITS (PORT_CSC) |
| 94 | 94 | ||
| 95 | struct isp1760_qtd { | 95 | struct isp1760_qtd { |
| 96 | u8 packet_type; | 96 | u8 packet_type; |
| 97 | void *data_buffer; | 97 | void *data_buffer; |
| 98 | u32 payload_addr; | 98 | u32 payload_addr; |
| 99 | 99 | ||
| 100 | /* the rest is HCD-private */ | 100 | /* the rest is HCD-private */ |
| 101 | struct list_head qtd_list; | 101 | struct list_head qtd_list; |
| 102 | struct urb *urb; | 102 | struct urb *urb; |
| 103 | size_t length; | 103 | size_t length; |
| 104 | size_t actual_length; | 104 | size_t actual_length; |
| 105 | 105 | ||
| 106 | /* QTD_ENQUEUED: waiting for transfer (inactive) */ | 106 | /* QTD_ENQUEUED: waiting for transfer (inactive) */ |
| 107 | /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ | 107 | /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ |
| 108 | /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only | 108 | /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only |
| 109 | interrupt handler may touch this qtd! */ | 109 | interrupt handler may touch this qtd! */ |
| 110 | /* QTD_XFER_COMPLETE: payload has been transferred successfully */ | 110 | /* QTD_XFER_COMPLETE: payload has been transferred successfully */ |
| 111 | /* QTD_RETIRE: transfer error/abort qtd */ | 111 | /* QTD_RETIRE: transfer error/abort qtd */ |
| 112 | #define QTD_ENQUEUED 0 | 112 | #define QTD_ENQUEUED 0 |
| 113 | #define QTD_PAYLOAD_ALLOC 1 | 113 | #define QTD_PAYLOAD_ALLOC 1 |
| 114 | #define QTD_XFER_STARTED 2 | 114 | #define QTD_XFER_STARTED 2 |
| 115 | #define QTD_XFER_COMPLETE 3 | 115 | #define QTD_XFER_COMPLETE 3 |
| 116 | #define QTD_RETIRE 4 | 116 | #define QTD_RETIRE 4 |
| 117 | u32 status; | 117 | u32 status; |
| 118 | }; | 118 | }; |
| 119 | 119 | ||
| 120 | /* Queue head, one for each active endpoint */ | 120 | /* Queue head, one for each active endpoint */ |
| 121 | struct isp1760_qh { | 121 | struct isp1760_qh { |
| 122 | struct list_head qh_list; | 122 | struct list_head qh_list; |
| 123 | struct list_head qtd_list; | 123 | struct list_head qtd_list; |
| 124 | u32 toggle; | 124 | u32 toggle; |
| 125 | u32 ping; | 125 | u32 ping; |
| 126 | int slot; | 126 | int slot; |
| 127 | int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ | 127 | int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ |
| 128 | }; | 128 | }; |
| 129 | 129 | ||
| 130 | struct urb_listitem { | 130 | struct urb_listitem { |
| 131 | struct list_head urb_list; | 131 | struct list_head urb_list; |
| 132 | struct urb *urb; | 132 | struct urb *urb; |
| 133 | }; | 133 | }; |
| 134 | 134 | ||
| 135 | /* | 135 | /* |
| 136 | * Access functions for isp176x registers (addresses 0..0x03FF). | 136 | * Access functions for isp176x registers (addresses 0..0x03FF). |
| 137 | */ | 137 | */ |
| 138 | static u32 reg_read32(void __iomem *base, u32 reg) | 138 | static u32 reg_read32(void __iomem *base, u32 reg) |
| 139 | { | 139 | { |
| 140 | return readl(base + reg); | 140 | return readl(base + reg); |
| 141 | } | 141 | } |
| 142 | 142 | ||
| 143 | static void reg_write32(void __iomem *base, u32 reg, u32 val) | 143 | static void reg_write32(void __iomem *base, u32 reg, u32 val) |
| 144 | { | 144 | { |
| 145 | writel(val, base + reg); | 145 | writel(val, base + reg); |
| 146 | } | 146 | } |
| 147 | 147 | ||
| 148 | /* | 148 | /* |
| 149 | * Access functions for isp176x memory (offset >= 0x0400). | 149 | * Access functions for isp176x memory (offset >= 0x0400). |
| 150 | * | 150 | * |
| 151 | * bank_reads8() reads memory locations prefetched by an earlier write to | 151 | * bank_reads8() reads memory locations prefetched by an earlier write to |
| 152 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- | 152 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- |
| 153 | * bank optimizations, you should use the more generic mem_reads8() below. | 153 | * bank optimizations, you should use the more generic mem_reads8() below. |
| 154 | * | 154 | * |
| 155 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() | 155 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() |
| 156 | * below. | 156 | * below. |
| 157 | * | 157 | * |
| 158 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() | 158 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() |
| 159 | * doesn't quite work because some people have to enforce 32-bit access | 159 | * doesn't quite work because some people have to enforce 32-bit access |
| 160 | */ | 160 | */ |
| 161 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, | 161 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
| 162 | __u32 *dst, u32 bytes) | 162 | __u32 *dst, u32 bytes) |
| 163 | { | 163 | { |
| 164 | __u32 __iomem *src; | 164 | __u32 __iomem *src; |
| 165 | u32 val; | 165 | u32 val; |
| 166 | __u8 *src_byteptr; | 166 | __u8 *src_byteptr; |
| 167 | __u8 *dst_byteptr; | 167 | __u8 *dst_byteptr; |
| 168 | 168 | ||
| 169 | src = src_base + (bank_addr | src_offset); | 169 | src = src_base + (bank_addr | src_offset); |
| 170 | 170 | ||
| 171 | if (src_offset < PAYLOAD_OFFSET) { | 171 | if (src_offset < PAYLOAD_OFFSET) { |
| 172 | while (bytes >= 4) { | 172 | while (bytes >= 4) { |
| 173 | *dst = le32_to_cpu(__raw_readl(src)); | 173 | *dst = le32_to_cpu(__raw_readl(src)); |
| 174 | bytes -= 4; | 174 | bytes -= 4; |
| 175 | src++; | 175 | src++; |
| 176 | dst++; | 176 | dst++; |
| 177 | } | 177 | } |
| 178 | } else { | 178 | } else { |
| 179 | while (bytes >= 4) { | 179 | while (bytes >= 4) { |
| 180 | *dst = __raw_readl(src); | 180 | *dst = __raw_readl(src); |
| 181 | bytes -= 4; | 181 | bytes -= 4; |
| 182 | src++; | 182 | src++; |
| 183 | dst++; | 183 | dst++; |
| 184 | } | 184 | } |
| 185 | } | 185 | } |
| 186 | 186 | ||
| 187 | if (!bytes) | 187 | if (!bytes) |
| 188 | return; | 188 | return; |
| 189 | 189 | ||
| 190 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | 190 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully |
| 191 | * allocated. | 191 | * allocated. |
| 192 | */ | 192 | */ |
| 193 | if (src_offset < PAYLOAD_OFFSET) | 193 | if (src_offset < PAYLOAD_OFFSET) |
| 194 | val = le32_to_cpu(__raw_readl(src)); | 194 | val = le32_to_cpu(__raw_readl(src)); |
| 195 | else | 195 | else |
| 196 | val = __raw_readl(src); | 196 | val = __raw_readl(src); |
| 197 | 197 | ||
| 198 | dst_byteptr = (void *) dst; | 198 | dst_byteptr = (void *) dst; |
| 199 | src_byteptr = (void *) &val; | 199 | src_byteptr = (void *) &val; |
| 200 | while (bytes > 0) { | 200 | while (bytes > 0) { |
| 201 | *dst_byteptr = *src_byteptr; | 201 | *dst_byteptr = *src_byteptr; |
| 202 | dst_byteptr++; | 202 | dst_byteptr++; |
| 203 | src_byteptr++; | 203 | src_byteptr++; |
| 204 | bytes--; | 204 | bytes--; |
| 205 | } | 205 | } |
| 206 | } | 206 | } |
| 207 | 207 | ||
| 208 | static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, | 208 | static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, |
| 209 | u32 bytes) | 209 | u32 bytes) |
| 210 | { | 210 | { |
| 211 | reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); | 211 | reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); |
| 212 | ndelay(90); | 212 | ndelay(90); |
| 213 | bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); | 213 | bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); |
| 214 | } | 214 | } |
| 215 | 215 | ||
| 216 | static void mem_writes8(void __iomem *dst_base, u32 dst_offset, | 216 | static void mem_writes8(void __iomem *dst_base, u32 dst_offset, |
| 217 | __u32 const *src, u32 bytes) | 217 | __u32 const *src, u32 bytes) |
| 218 | { | 218 | { |
| 219 | __u32 __iomem *dst; | 219 | __u32 __iomem *dst; |
| 220 | 220 | ||
| 221 | dst = dst_base + dst_offset; | 221 | dst = dst_base + dst_offset; |
| 222 | 222 | ||
| 223 | if (dst_offset < PAYLOAD_OFFSET) { | 223 | if (dst_offset < PAYLOAD_OFFSET) { |
| 224 | while (bytes >= 4) { | 224 | while (bytes >= 4) { |
| 225 | __raw_writel(cpu_to_le32(*src), dst); | 225 | __raw_writel(cpu_to_le32(*src), dst); |
| 226 | bytes -= 4; | 226 | bytes -= 4; |
| 227 | src++; | 227 | src++; |
| 228 | dst++; | 228 | dst++; |
| 229 | } | 229 | } |
| 230 | } else { | 230 | } else { |
| 231 | while (bytes >= 4) { | 231 | while (bytes >= 4) { |
| 232 | __raw_writel(*src, dst); | 232 | __raw_writel(*src, dst); |
| 233 | bytes -= 4; | 233 | bytes -= 4; |
| 234 | src++; | 234 | src++; |
| 235 | dst++; | 235 | dst++; |
| 236 | } | 236 | } |
| 237 | } | 237 | } |
| 238 | 238 | ||
| 239 | if (!bytes) | 239 | if (!bytes) |
| 240 | return; | 240 | return; |
| 241 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the | 241 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
| 242 | * extra bytes should not be read by the HW. | 242 | * extra bytes should not be read by the HW. |
| 243 | */ | 243 | */ |
| 244 | 244 | ||
| 245 | if (dst_offset < PAYLOAD_OFFSET) | 245 | if (dst_offset < PAYLOAD_OFFSET) |
| 246 | __raw_writel(cpu_to_le32(*src), dst); | 246 | __raw_writel(cpu_to_le32(*src), dst); |
| 247 | else | 247 | else |
| 248 | __raw_writel(*src, dst); | 248 | __raw_writel(*src, dst); |
| 249 | } | 249 | } |
| 250 | 250 | ||
| 251 | /* | 251 | /* |
| 252 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, | 252 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, |
| 253 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. | 253 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. |
| 254 | */ | 254 | */ |
| 255 | static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, | 255 | static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, |
| 256 | struct ptd *ptd) | 256 | struct ptd *ptd) |
| 257 | { | 257 | { |
| 258 | reg_write32(base, HC_MEMORY_REG, | 258 | reg_write32(base, HC_MEMORY_REG, |
| 259 | ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); | 259 | ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); |
| 260 | ndelay(90); | 260 | ndelay(90); |
| 261 | bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), | 261 | bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), |
| 262 | (void *) ptd, sizeof(*ptd)); | 262 | (void *) ptd, sizeof(*ptd)); |
| 263 | } | 263 | } |
| 264 | 264 | ||
| 265 | static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, | 265 | static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, |
| 266 | struct ptd *ptd) | 266 | struct ptd *ptd) |
| 267 | { | 267 | { |
| 268 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), | 268 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), |
| 269 | &ptd->dw1, 7*sizeof(ptd->dw1)); | 269 | &ptd->dw1, 7*sizeof(ptd->dw1)); |
| 270 | /* Make sure dw0 gets written last (after other dw's and after payload) | 270 | /* Make sure dw0 gets written last (after other dw's and after payload) |
| 271 | since it contains the enable bit */ | 271 | since it contains the enable bit */ |
| 272 | wmb(); | 272 | wmb(); |
| 273 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, | 273 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, |
| 274 | sizeof(ptd->dw0)); | 274 | sizeof(ptd->dw0)); |
| 275 | } | 275 | } |
| 276 | 276 | ||
| 277 | 277 | ||
| 278 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ | 278 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
| 279 | static void init_memory(struct isp1760_hcd *priv) | 279 | static void init_memory(struct isp1760_hcd *priv) |
| 280 | { | 280 | { |
| 281 | int i, curr; | 281 | int i, curr; |
| 282 | u32 payload_addr; | 282 | u32 payload_addr; |
| 283 | 283 | ||
| 284 | payload_addr = PAYLOAD_OFFSET; | 284 | payload_addr = PAYLOAD_OFFSET; |
| 285 | for (i = 0; i < BLOCK_1_NUM; i++) { | 285 | for (i = 0; i < BLOCK_1_NUM; i++) { |
| 286 | priv->memory_pool[i].start = payload_addr; | 286 | priv->memory_pool[i].start = payload_addr; |
| 287 | priv->memory_pool[i].size = BLOCK_1_SIZE; | 287 | priv->memory_pool[i].size = BLOCK_1_SIZE; |
| 288 | priv->memory_pool[i].free = 1; | 288 | priv->memory_pool[i].free = 1; |
| 289 | payload_addr += priv->memory_pool[i].size; | 289 | payload_addr += priv->memory_pool[i].size; |
| 290 | } | 290 | } |
| 291 | 291 | ||
| 292 | curr = i; | 292 | curr = i; |
| 293 | for (i = 0; i < BLOCK_2_NUM; i++) { | 293 | for (i = 0; i < BLOCK_2_NUM; i++) { |
| 294 | priv->memory_pool[curr + i].start = payload_addr; | 294 | priv->memory_pool[curr + i].start = payload_addr; |
| 295 | priv->memory_pool[curr + i].size = BLOCK_2_SIZE; | 295 | priv->memory_pool[curr + i].size = BLOCK_2_SIZE; |
| 296 | priv->memory_pool[curr + i].free = 1; | 296 | priv->memory_pool[curr + i].free = 1; |
| 297 | payload_addr += priv->memory_pool[curr + i].size; | 297 | payload_addr += priv->memory_pool[curr + i].size; |
| 298 | } | 298 | } |
| 299 | 299 | ||
| 300 | curr = i; | 300 | curr = i; |
| 301 | for (i = 0; i < BLOCK_3_NUM; i++) { | 301 | for (i = 0; i < BLOCK_3_NUM; i++) { |
| 302 | priv->memory_pool[curr + i].start = payload_addr; | 302 | priv->memory_pool[curr + i].start = payload_addr; |
| 303 | priv->memory_pool[curr + i].size = BLOCK_3_SIZE; | 303 | priv->memory_pool[curr + i].size = BLOCK_3_SIZE; |
| 304 | priv->memory_pool[curr + i].free = 1; | 304 | priv->memory_pool[curr + i].free = 1; |
| 305 | payload_addr += priv->memory_pool[curr + i].size; | 305 | payload_addr += priv->memory_pool[curr + i].size; |
| 306 | } | 306 | } |
| 307 | 307 | ||
| 308 | WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); | 308 | WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); |
| 309 | } | 309 | } |
| 310 | 310 | ||
| 311 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) | 311 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
| 312 | { | 312 | { |
| 313 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 313 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 314 | int i; | 314 | int i; |
| 315 | 315 | ||
| 316 | WARN_ON(qtd->payload_addr); | 316 | WARN_ON(qtd->payload_addr); |
| 317 | 317 | ||
| 318 | if (!qtd->length) | 318 | if (!qtd->length) |
| 319 | return; | 319 | return; |
| 320 | 320 | ||
| 321 | for (i = 0; i < BLOCKS; i++) { | 321 | for (i = 0; i < BLOCKS; i++) { |
| 322 | if (priv->memory_pool[i].size >= qtd->length && | 322 | if (priv->memory_pool[i].size >= qtd->length && |
| 323 | priv->memory_pool[i].free) { | 323 | priv->memory_pool[i].free) { |
| 324 | priv->memory_pool[i].free = 0; | 324 | priv->memory_pool[i].free = 0; |
| 325 | qtd->payload_addr = priv->memory_pool[i].start; | 325 | qtd->payload_addr = priv->memory_pool[i].start; |
| 326 | return; | 326 | return; |
| 327 | } | 327 | } |
| 328 | } | 328 | } |
| 329 | } | 329 | } |
| 330 | 330 | ||
| 331 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) | 331 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
| 332 | { | 332 | { |
| 333 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 333 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 334 | int i; | 334 | int i; |
| 335 | 335 | ||
| 336 | if (!qtd->payload_addr) | 336 | if (!qtd->payload_addr) |
| 337 | return; | 337 | return; |
| 338 | 338 | ||
| 339 | for (i = 0; i < BLOCKS; i++) { | 339 | for (i = 0; i < BLOCKS; i++) { |
| 340 | if (priv->memory_pool[i].start == qtd->payload_addr) { | 340 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
| 341 | WARN_ON(priv->memory_pool[i].free); | 341 | WARN_ON(priv->memory_pool[i].free); |
| 342 | priv->memory_pool[i].free = 1; | 342 | priv->memory_pool[i].free = 1; |
| 343 | qtd->payload_addr = 0; | 343 | qtd->payload_addr = 0; |
| 344 | return; | 344 | return; |
| 345 | } | 345 | } |
| 346 | } | 346 | } |
| 347 | 347 | ||
| 348 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", | 348 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", |
| 349 | __func__, qtd->payload_addr); | 349 | __func__, qtd->payload_addr); |
| 350 | WARN_ON(1); | 350 | WARN_ON(1); |
| 351 | qtd->payload_addr = 0; | 351 | qtd->payload_addr = 0; |
| 352 | } | 352 | } |
| 353 | 353 | ||
| 354 | static int handshake(struct usb_hcd *hcd, u32 reg, | 354 | static int handshake(struct usb_hcd *hcd, u32 reg, |
| 355 | u32 mask, u32 done, int usec) | 355 | u32 mask, u32 done, int usec) |
| 356 | { | 356 | { |
| 357 | u32 result; | 357 | u32 result; |
| 358 | 358 | ||
| 359 | do { | 359 | do { |
| 360 | result = reg_read32(hcd->regs, reg); | 360 | result = reg_read32(hcd->regs, reg); |
| 361 | if (result == ~0) | 361 | if (result == ~0) |
| 362 | return -ENODEV; | 362 | return -ENODEV; |
| 363 | result &= mask; | 363 | result &= mask; |
| 364 | if (result == done) | 364 | if (result == done) |
| 365 | return 0; | 365 | return 0; |
| 366 | udelay(1); | 366 | udelay(1); |
| 367 | usec--; | 367 | usec--; |
| 368 | } while (usec > 0); | 368 | } while (usec > 0); |
| 369 | return -ETIMEDOUT; | 369 | return -ETIMEDOUT; |
| 370 | } | 370 | } |
| 371 | 371 | ||
| 372 | /* reset a non-running (STS_HALT == 1) controller */ | 372 | /* reset a non-running (STS_HALT == 1) controller */ |
| 373 | static int ehci_reset(struct usb_hcd *hcd) | 373 | static int ehci_reset(struct usb_hcd *hcd) |
| 374 | { | 374 | { |
| 375 | int retval; | 375 | int retval; |
| 376 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 376 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 377 | 377 | ||
| 378 | u32 command = reg_read32(hcd->regs, HC_USBCMD); | 378 | u32 command = reg_read32(hcd->regs, HC_USBCMD); |
| 379 | 379 | ||
| 380 | command |= CMD_RESET; | 380 | command |= CMD_RESET; |
| 381 | reg_write32(hcd->regs, HC_USBCMD, command); | 381 | reg_write32(hcd->regs, HC_USBCMD, command); |
| 382 | hcd->state = HC_STATE_HALT; | 382 | hcd->state = HC_STATE_HALT; |
| 383 | priv->next_statechange = jiffies; | 383 | priv->next_statechange = jiffies; |
| 384 | retval = handshake(hcd, HC_USBCMD, | 384 | retval = handshake(hcd, HC_USBCMD, |
| 385 | CMD_RESET, 0, 250 * 1000); | 385 | CMD_RESET, 0, 250 * 1000); |
| 386 | return retval; | 386 | return retval; |
| 387 | } | 387 | } |
| 388 | 388 | ||
| 389 | static struct isp1760_qh *qh_alloc(gfp_t flags) | 389 | static struct isp1760_qh *qh_alloc(gfp_t flags) |
| 390 | { | 390 | { |
| 391 | struct isp1760_qh *qh; | 391 | struct isp1760_qh *qh; |
| 392 | 392 | ||
| 393 | qh = kmem_cache_zalloc(qh_cachep, flags); | 393 | qh = kmem_cache_zalloc(qh_cachep, flags); |
| 394 | if (!qh) | 394 | if (!qh) |
| 395 | return NULL; | 395 | return NULL; |
| 396 | 396 | ||
| 397 | INIT_LIST_HEAD(&qh->qh_list); | 397 | INIT_LIST_HEAD(&qh->qh_list); |
| 398 | INIT_LIST_HEAD(&qh->qtd_list); | 398 | INIT_LIST_HEAD(&qh->qtd_list); |
| 399 | qh->slot = -1; | 399 | qh->slot = -1; |
| 400 | 400 | ||
| 401 | return qh; | 401 | return qh; |
| 402 | } | 402 | } |
| 403 | 403 | ||
| 404 | static void qh_free(struct isp1760_qh *qh) | 404 | static void qh_free(struct isp1760_qh *qh) |
| 405 | { | 405 | { |
| 406 | WARN_ON(!list_empty(&qh->qtd_list)); | 406 | WARN_ON(!list_empty(&qh->qtd_list)); |
| 407 | WARN_ON(qh->slot > -1); | 407 | WARN_ON(qh->slot > -1); |
| 408 | kmem_cache_free(qh_cachep, qh); | 408 | kmem_cache_free(qh_cachep, qh); |
| 409 | } | 409 | } |
| 410 | 410 | ||
| 411 | /* one-time init, only for memory state */ | 411 | /* one-time init, only for memory state */ |
| 412 | static int priv_init(struct usb_hcd *hcd) | 412 | static int priv_init(struct usb_hcd *hcd) |
| 413 | { | 413 | { |
| 414 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 414 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 415 | u32 hcc_params; | 415 | u32 hcc_params; |
| 416 | int i; | 416 | int i; |
| 417 | 417 | ||
| 418 | spin_lock_init(&priv->lock); | 418 | spin_lock_init(&priv->lock); |
| 419 | 419 | ||
| 420 | for (i = 0; i < QH_END; i++) | 420 | for (i = 0; i < QH_END; i++) |
| 421 | INIT_LIST_HEAD(&priv->qh_list[i]); | 421 | INIT_LIST_HEAD(&priv->qh_list[i]); |
| 422 | 422 | ||
| 423 | /* | 423 | /* |
| 424 | * hw default: 1K periodic list heads, one per frame. | 424 | * hw default: 1K periodic list heads, one per frame. |
| 425 | * periodic_size can shrink by USBCMD update if hcc_params allows. | 425 | * periodic_size can shrink by USBCMD update if hcc_params allows. |
| 426 | */ | 426 | */ |
| 427 | priv->periodic_size = DEFAULT_I_TDPS; | 427 | priv->periodic_size = DEFAULT_I_TDPS; |
| 428 | 428 | ||
| 429 | /* controllers may cache some of the periodic schedule ... */ | 429 | /* controllers may cache some of the periodic schedule ... */ |
| 430 | hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); | 430 | hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); |
| 431 | /* full frame cache */ | 431 | /* full frame cache */ |
| 432 | if (HCC_ISOC_CACHE(hcc_params)) | 432 | if (HCC_ISOC_CACHE(hcc_params)) |
| 433 | priv->i_thresh = 8; | 433 | priv->i_thresh = 8; |
| 434 | else /* N microframes cached */ | 434 | else /* N microframes cached */ |
| 435 | priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); | 435 | priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
| 436 | 436 | ||
| 437 | return 0; | 437 | return 0; |
| 438 | } | 438 | } |
| 439 | 439 | ||
| 440 | static int isp1760_hc_setup(struct usb_hcd *hcd) | 440 | static int isp1760_hc_setup(struct usb_hcd *hcd) |
| 441 | { | 441 | { |
| 442 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 442 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 443 | int result; | 443 | int result; |
| 444 | u32 scratch, hwmode; | 444 | u32 scratch, hwmode; |
| 445 | 445 | ||
| 446 | /* low-level chip reset */ | 446 | /* low-level chip reset */ |
| 447 | if (gpio_is_valid(priv->rst_gpio)) { | 447 | if (gpio_is_valid(priv->rst_gpio)) { |
| 448 | unsigned int rst_lvl; | 448 | unsigned int rst_lvl; |
| 449 | 449 | ||
| 450 | rst_lvl = (priv->devflags & | 450 | rst_lvl = (priv->devflags & |
| 451 | ISP1760_FLAG_RESET_ACTIVE_HIGH) ? 1 : 0; | 451 | ISP1760_FLAG_RESET_ACTIVE_HIGH) ? 1 : 0; |
| 452 | 452 | ||
| 453 | gpio_set_value(priv->rst_gpio, rst_lvl); | 453 | gpio_set_value(priv->rst_gpio, rst_lvl); |
| 454 | mdelay(50); | 454 | mdelay(50); |
| 455 | gpio_set_value(priv->rst_gpio, !rst_lvl); | 455 | gpio_set_value(priv->rst_gpio, !rst_lvl); |
| 456 | } | 456 | } |
| 457 | 457 | ||
| 458 | /* Setup HW Mode Control: This assumes a level active-low interrupt */ | 458 | /* Setup HW Mode Control: This assumes a level active-low interrupt */ |
| 459 | hwmode = HW_DATA_BUS_32BIT; | 459 | hwmode = HW_DATA_BUS_32BIT; |
| 460 | 460 | ||
| 461 | if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) | 461 | if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) |
| 462 | hwmode &= ~HW_DATA_BUS_32BIT; | 462 | hwmode &= ~HW_DATA_BUS_32BIT; |
| 463 | if (priv->devflags & ISP1760_FLAG_ANALOG_OC) | 463 | if (priv->devflags & ISP1760_FLAG_ANALOG_OC) |
| 464 | hwmode |= HW_ANA_DIGI_OC; | 464 | hwmode |= HW_ANA_DIGI_OC; |
| 465 | if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) | 465 | if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) |
| 466 | hwmode |= HW_DACK_POL_HIGH; | 466 | hwmode |= HW_DACK_POL_HIGH; |
| 467 | if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) | 467 | if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) |
| 468 | hwmode |= HW_DREQ_POL_HIGH; | 468 | hwmode |= HW_DREQ_POL_HIGH; |
| 469 | if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) | 469 | if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) |
| 470 | hwmode |= HW_INTR_HIGH_ACT; | 470 | hwmode |= HW_INTR_HIGH_ACT; |
| 471 | if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) | 471 | if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) |
| 472 | hwmode |= HW_INTR_EDGE_TRIG; | 472 | hwmode |= HW_INTR_EDGE_TRIG; |
| 473 | 473 | ||
| 474 | /* | 474 | /* |
| 475 | * We have to set this first in case we're in 16-bit mode. | 475 | * We have to set this first in case we're in 16-bit mode. |
| 476 | * Write it twice to ensure correct upper bits if switching | 476 | * Write it twice to ensure correct upper bits if switching |
| 477 | * to 16-bit mode. | 477 | * to 16-bit mode. |
| 478 | */ | 478 | */ |
| 479 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); | 479 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
| 480 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); | 480 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
| 481 | 481 | ||
| 482 | reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); | 482 | reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); |
| 483 | /* Change bus pattern */ | 483 | /* Change bus pattern */ |
| 484 | scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); | 484 | scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
| 485 | scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); | 485 | scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); |
| 486 | if (scratch != 0xdeadbabe) { | 486 | if (scratch != 0xdeadbabe) { |
| 487 | dev_err(hcd->self.controller, "Scratch test failed.\n"); | 487 | dev_err(hcd->self.controller, "Scratch test failed.\n"); |
| 488 | return -ENODEV; | 488 | return -ENODEV; |
| 489 | } | 489 | } |
| 490 | 490 | ||
| 491 | /* pre reset */ | 491 | /* pre reset */ |
| 492 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); | 492 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); |
| 493 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | 493 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); |
| 494 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | 494 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); |
| 495 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | 495 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); |
| 496 | 496 | ||
| 497 | /* reset */ | 497 | /* reset */ |
| 498 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); | 498 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); |
| 499 | mdelay(100); | 499 | mdelay(100); |
| 500 | 500 | ||
| 501 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); | 501 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); |
| 502 | mdelay(100); | 502 | mdelay(100); |
| 503 | 503 | ||
| 504 | result = ehci_reset(hcd); | 504 | result = ehci_reset(hcd); |
| 505 | if (result) | 505 | if (result) |
| 506 | return result; | 506 | return result; |
| 507 | 507 | ||
| 508 | /* Step 11 passed */ | 508 | /* Step 11 passed */ |
| 509 | 509 | ||
| 510 | dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", | 510 | dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", |
| 511 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? | 511 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? |
| 512 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? | 512 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? |
| 513 | "analog" : "digital"); | 513 | "analog" : "digital"); |
| 514 | 514 | ||
| 515 | /* ATL reset */ | 515 | /* ATL reset */ |
| 516 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); | 516 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); |
| 517 | mdelay(10); | 517 | mdelay(10); |
| 518 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); | 518 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
| 519 | 519 | ||
| 520 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); | 520 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); |
| 521 | 521 | ||
| 522 | /* | 522 | /* |
| 523 | * PORT 1 Control register of the ISP1760 is the OTG control | 523 | * PORT 1 Control register of the ISP1760 is the OTG control |
| 524 | * register on ISP1761. Since there is no OTG or device controller | 524 | * register on ISP1761. Since there is no OTG or device controller |
| 525 | * support in this driver, we use port 1 as a "normal" USB host port on | 525 | * support in this driver, we use port 1 as a "normal" USB host port on |
| 526 | * both chips. | 526 | * both chips. |
| 527 | */ | 527 | */ |
| 528 | reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); | 528 | reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); |
| 529 | mdelay(10); | 529 | mdelay(10); |
| 530 | 530 | ||
| 531 | priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); | 531 | priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); |
| 532 | 532 | ||
| 533 | return priv_init(hcd); | 533 | return priv_init(hcd); |
| 534 | } | 534 | } |
| 535 | 535 | ||
| 536 | static u32 base_to_chip(u32 base) | 536 | static u32 base_to_chip(u32 base) |
| 537 | { | 537 | { |
| 538 | return ((base - 0x400) >> 3); | 538 | return ((base - 0x400) >> 3); |
| 539 | } | 539 | } |
| 540 | 540 | ||
| 541 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) | 541 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
| 542 | { | 542 | { |
| 543 | struct urb *urb; | 543 | struct urb *urb; |
| 544 | 544 | ||
| 545 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) | 545 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) |
| 546 | return 1; | 546 | return 1; |
| 547 | 547 | ||
| 548 | urb = qtd->urb; | 548 | urb = qtd->urb; |
| 549 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); | 549 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); |
| 550 | return (qtd->urb != urb); | 550 | return (qtd->urb != urb); |
| 551 | } | 551 | } |
| 552 | 552 | ||
| 553 | /* magic numbers that can affect system performance */ | 553 | /* magic numbers that can affect system performance */ |
| 554 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | 554 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ |
| 555 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | 555 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ |
| 556 | #define EHCI_TUNE_RL_TT 0 | 556 | #define EHCI_TUNE_RL_TT 0 |
| 557 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | 557 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ |
| 558 | #define EHCI_TUNE_MULT_TT 1 | 558 | #define EHCI_TUNE_MULT_TT 1 |
| 559 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | 559 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ |
| 560 | 560 | ||
| 561 | static void create_ptd_atl(struct isp1760_qh *qh, | 561 | static void create_ptd_atl(struct isp1760_qh *qh, |
| 562 | struct isp1760_qtd *qtd, struct ptd *ptd) | 562 | struct isp1760_qtd *qtd, struct ptd *ptd) |
| 563 | { | 563 | { |
| 564 | u32 maxpacket; | 564 | u32 maxpacket; |
| 565 | u32 multi; | 565 | u32 multi; |
| 566 | u32 rl = RL_COUNTER; | 566 | u32 rl = RL_COUNTER; |
| 567 | u32 nak = NAK_COUNTER; | 567 | u32 nak = NAK_COUNTER; |
| 568 | 568 | ||
| 569 | memset(ptd, 0, sizeof(*ptd)); | 569 | memset(ptd, 0, sizeof(*ptd)); |
| 570 | 570 | ||
| 571 | /* according to 3.6.2, max packet len can not be > 0x400 */ | 571 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
| 572 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, | 572 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, |
| 573 | usb_pipeout(qtd->urb->pipe)); | 573 | usb_pipeout(qtd->urb->pipe)); |
| 574 | multi = 1 + ((maxpacket >> 11) & 0x3); | 574 | multi = 1 + ((maxpacket >> 11) & 0x3); |
| 575 | maxpacket &= 0x7ff; | 575 | maxpacket &= 0x7ff; |
| 576 | 576 | ||
| 577 | /* DW0 */ | 577 | /* DW0 */ |
| 578 | ptd->dw0 = DW0_VALID_BIT; | 578 | ptd->dw0 = DW0_VALID_BIT; |
| 579 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); | 579 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); |
| 580 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); | 580 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); |
| 581 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); | 581 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); |
| 582 | 582 | ||
| 583 | /* DW1 */ | 583 | /* DW1 */ |
| 584 | ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; | 584 | ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; |
| 585 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); | 585 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); |
| 586 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); | 586 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); |
| 587 | 587 | ||
| 588 | if (usb_pipebulk(qtd->urb->pipe)) | 588 | if (usb_pipebulk(qtd->urb->pipe)) |
| 589 | ptd->dw1 |= DW1_TRANS_BULK; | 589 | ptd->dw1 |= DW1_TRANS_BULK; |
| 590 | else if (usb_pipeint(qtd->urb->pipe)) | 590 | else if (usb_pipeint(qtd->urb->pipe)) |
| 591 | ptd->dw1 |= DW1_TRANS_INT; | 591 | ptd->dw1 |= DW1_TRANS_INT; |
| 592 | 592 | ||
| 593 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { | 593 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
| 594 | /* split transaction */ | 594 | /* split transaction */ |
| 595 | 595 | ||
| 596 | ptd->dw1 |= DW1_TRANS_SPLIT; | 596 | ptd->dw1 |= DW1_TRANS_SPLIT; |
| 597 | if (qtd->urb->dev->speed == USB_SPEED_LOW) | 597 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
| 598 | ptd->dw1 |= DW1_SE_USB_LOSPEED; | 598 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
| 599 | 599 | ||
| 600 | ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); | 600 | ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); |
| 601 | ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); | 601 | ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); |
| 602 | 602 | ||
| 603 | /* SE bit for Split INT transfers */ | 603 | /* SE bit for Split INT transfers */ |
| 604 | if (usb_pipeint(qtd->urb->pipe) && | 604 | if (usb_pipeint(qtd->urb->pipe) && |
| 605 | (qtd->urb->dev->speed == USB_SPEED_LOW)) | 605 | (qtd->urb->dev->speed == USB_SPEED_LOW)) |
| 606 | ptd->dw1 |= 2 << 16; | 606 | ptd->dw1 |= 2 << 16; |
| 607 | 607 | ||
| 608 | rl = 0; | 608 | rl = 0; |
| 609 | nak = 0; | 609 | nak = 0; |
| 610 | } else { | 610 | } else { |
| 611 | ptd->dw0 |= TO_DW0_MULTI(multi); | 611 | ptd->dw0 |= TO_DW0_MULTI(multi); |
| 612 | if (usb_pipecontrol(qtd->urb->pipe) || | 612 | if (usb_pipecontrol(qtd->urb->pipe) || |
| 613 | usb_pipebulk(qtd->urb->pipe)) | 613 | usb_pipebulk(qtd->urb->pipe)) |
| 614 | ptd->dw3 |= TO_DW3_PING(qh->ping); | 614 | ptd->dw3 |= TO_DW3_PING(qh->ping); |
| 615 | } | 615 | } |
| 616 | /* DW2 */ | 616 | /* DW2 */ |
| 617 | ptd->dw2 = 0; | 617 | ptd->dw2 = 0; |
| 618 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); | 618 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
| 619 | ptd->dw2 |= TO_DW2_RL(rl); | 619 | ptd->dw2 |= TO_DW2_RL(rl); |
| 620 | 620 | ||
| 621 | /* DW3 */ | 621 | /* DW3 */ |
| 622 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); | 622 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
| 623 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); | 623 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); |
| 624 | if (usb_pipecontrol(qtd->urb->pipe)) { | 624 | if (usb_pipecontrol(qtd->urb->pipe)) { |
| 625 | if (qtd->data_buffer == qtd->urb->setup_packet) | 625 | if (qtd->data_buffer == qtd->urb->setup_packet) |
| 626 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); | 626 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); |
| 627 | else if (last_qtd_of_urb(qtd, qh)) | 627 | else if (last_qtd_of_urb(qtd, qh)) |
| 628 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); | 628 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); |
| 629 | } | 629 | } |
| 630 | 630 | ||
| 631 | ptd->dw3 |= DW3_ACTIVE_BIT; | 631 | ptd->dw3 |= DW3_ACTIVE_BIT; |
| 632 | /* Cerr */ | 632 | /* Cerr */ |
| 633 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); | 633 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
| 634 | } | 634 | } |
| 635 | 635 | ||
| 636 | static void transform_add_int(struct isp1760_qh *qh, | 636 | static void transform_add_int(struct isp1760_qh *qh, |
| 637 | struct isp1760_qtd *qtd, struct ptd *ptd) | 637 | struct isp1760_qtd *qtd, struct ptd *ptd) |
| 638 | { | 638 | { |
| 639 | u32 usof; | 639 | u32 usof; |
| 640 | u32 period; | 640 | u32 period; |
| 641 | 641 | ||
| 642 | /* | 642 | /* |
| 643 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and | 643 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and |
| 644 | * the algorithm from the original Philips driver code, which was | 644 | * the algorithm from the original Philips driver code, which was |
| 645 | * pretty much used in this driver before as well, is quite horrendous | 645 | * pretty much used in this driver before as well, is quite horrendous |
| 646 | * and, i believe, incorrect. The code below follows the datasheet and | 646 | * and, i believe, incorrect. The code below follows the datasheet and |
| 647 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much | 647 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much |
| 648 | * more reliable this way (fingers crossed...). | 648 | * more reliable this way (fingers crossed...). |
| 649 | */ | 649 | */ |
| 650 | 650 | ||
| 651 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { | 651 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
| 652 | /* urb->interval is in units of microframes (1/8 ms) */ | 652 | /* urb->interval is in units of microframes (1/8 ms) */ |
| 653 | period = qtd->urb->interval >> 3; | 653 | period = qtd->urb->interval >> 3; |
| 654 | 654 | ||
| 655 | if (qtd->urb->interval > 4) | 655 | if (qtd->urb->interval > 4) |
| 656 | usof = 0x01; /* One bit set => | 656 | usof = 0x01; /* One bit set => |
| 657 | interval 1 ms * uFrame-match */ | 657 | interval 1 ms * uFrame-match */ |
| 658 | else if (qtd->urb->interval > 2) | 658 | else if (qtd->urb->interval > 2) |
| 659 | usof = 0x22; /* Two bits set => interval 1/2 ms */ | 659 | usof = 0x22; /* Two bits set => interval 1/2 ms */ |
| 660 | else if (qtd->urb->interval > 1) | 660 | else if (qtd->urb->interval > 1) |
| 661 | usof = 0x55; /* Four bits set => interval 1/4 ms */ | 661 | usof = 0x55; /* Four bits set => interval 1/4 ms */ |
| 662 | else | 662 | else |
| 663 | usof = 0xff; /* All bits set => interval 1/8 ms */ | 663 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
| 664 | } else { | 664 | } else { |
| 665 | /* urb->interval is in units of frames (1 ms) */ | 665 | /* urb->interval is in units of frames (1 ms) */ |
| 666 | period = qtd->urb->interval; | 666 | period = qtd->urb->interval; |
| 667 | usof = 0x0f; /* Execute Start Split on any of the | 667 | usof = 0x0f; /* Execute Start Split on any of the |
| 668 | four first uFrames */ | 668 | four first uFrames */ |
| 669 | 669 | ||
| 670 | /* | 670 | /* |
| 671 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the | 671 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the |
| 672 | * complete split needs to be sent. Valid only for IN." Also, | 672 | * complete split needs to be sent. Valid only for IN." Also, |
| 673 | * "All bits can be set to one for every transfer." (p 82, | 673 | * "All bits can be set to one for every transfer." (p 82, |
| 674 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did | 674 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did |
| 675 | * that number come from? 0xff seems to work fine... | 675 | * that number come from? 0xff seems to work fine... |
| 676 | */ | 676 | */ |
| 677 | /* ptd->dw5 = 0x1c; */ | 677 | /* ptd->dw5 = 0x1c; */ |
| 678 | ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ | 678 | ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ |
| 679 | } | 679 | } |
| 680 | 680 | ||
| 681 | period = period >> 1;/* Ensure equal or shorter period than requested */ | 681 | period = period >> 1;/* Ensure equal or shorter period than requested */ |
| 682 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ | 682 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ |
| 683 | 683 | ||
| 684 | ptd->dw2 |= period; | 684 | ptd->dw2 |= period; |
| 685 | ptd->dw4 = usof; | 685 | ptd->dw4 = usof; |
| 686 | } | 686 | } |
| 687 | 687 | ||
| 688 | static void create_ptd_int(struct isp1760_qh *qh, | 688 | static void create_ptd_int(struct isp1760_qh *qh, |
| 689 | struct isp1760_qtd *qtd, struct ptd *ptd) | 689 | struct isp1760_qtd *qtd, struct ptd *ptd) |
| 690 | { | 690 | { |
| 691 | create_ptd_atl(qh, qtd, ptd); | 691 | create_ptd_atl(qh, qtd, ptd); |
| 692 | transform_add_int(qh, qtd, ptd); | 692 | transform_add_int(qh, qtd, ptd); |
| 693 | } | 693 | } |
| 694 | 694 | ||
| 695 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) | 695 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
| 696 | __releases(priv->lock) | 696 | __releases(priv->lock) |
| 697 | __acquires(priv->lock) | 697 | __acquires(priv->lock) |
| 698 | { | 698 | { |
| 699 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 699 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 700 | 700 | ||
| 701 | if (!urb->unlinked) { | 701 | if (!urb->unlinked) { |
| 702 | if (urb->status == -EINPROGRESS) | 702 | if (urb->status == -EINPROGRESS) |
| 703 | urb->status = 0; | 703 | urb->status = 0; |
| 704 | } | 704 | } |
| 705 | 705 | ||
| 706 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { | 706 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
| 707 | void *ptr; | 707 | void *ptr; |
| 708 | for (ptr = urb->transfer_buffer; | 708 | for (ptr = urb->transfer_buffer; |
| 709 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; | 709 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; |
| 710 | ptr += PAGE_SIZE) | 710 | ptr += PAGE_SIZE) |
| 711 | flush_dcache_page(virt_to_page(ptr)); | 711 | flush_dcache_page(virt_to_page(ptr)); |
| 712 | } | 712 | } |
| 713 | 713 | ||
| 714 | /* complete() can reenter this HCD */ | 714 | /* complete() can reenter this HCD */ |
| 715 | usb_hcd_unlink_urb_from_ep(hcd, urb); | 715 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 716 | spin_unlock(&priv->lock); | 716 | spin_unlock(&priv->lock); |
| 717 | usb_hcd_giveback_urb(hcd, urb, urb->status); | 717 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
| 718 | spin_lock(&priv->lock); | 718 | spin_lock(&priv->lock); |
| 719 | } | 719 | } |
| 720 | 720 | ||
| 721 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, | 721 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
| 722 | u8 packet_type) | 722 | u8 packet_type) |
| 723 | { | 723 | { |
| 724 | struct isp1760_qtd *qtd; | 724 | struct isp1760_qtd *qtd; |
| 725 | 725 | ||
| 726 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | 726 | qtd = kmem_cache_zalloc(qtd_cachep, flags); |
| 727 | if (!qtd) | 727 | if (!qtd) |
| 728 | return NULL; | 728 | return NULL; |
| 729 | 729 | ||
| 730 | INIT_LIST_HEAD(&qtd->qtd_list); | 730 | INIT_LIST_HEAD(&qtd->qtd_list); |
| 731 | qtd->urb = urb; | 731 | qtd->urb = urb; |
| 732 | qtd->packet_type = packet_type; | 732 | qtd->packet_type = packet_type; |
| 733 | qtd->status = QTD_ENQUEUED; | 733 | qtd->status = QTD_ENQUEUED; |
| 734 | qtd->actual_length = 0; | 734 | qtd->actual_length = 0; |
| 735 | 735 | ||
| 736 | return qtd; | 736 | return qtd; |
| 737 | } | 737 | } |
| 738 | 738 | ||
| 739 | static void qtd_free(struct isp1760_qtd *qtd) | 739 | static void qtd_free(struct isp1760_qtd *qtd) |
| 740 | { | 740 | { |
| 741 | WARN_ON(qtd->payload_addr); | 741 | WARN_ON(qtd->payload_addr); |
| 742 | kmem_cache_free(qtd_cachep, qtd); | 742 | kmem_cache_free(qtd_cachep, qtd); |
| 743 | } | 743 | } |
| 744 | 744 | ||
| 745 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, | 745 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
| 746 | struct slotinfo *slots, struct isp1760_qtd *qtd, | 746 | struct slotinfo *slots, struct isp1760_qtd *qtd, |
| 747 | struct isp1760_qh *qh, struct ptd *ptd) | 747 | struct isp1760_qh *qh, struct ptd *ptd) |
| 748 | { | 748 | { |
| 749 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 749 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 750 | int skip_map; | 750 | int skip_map; |
| 751 | 751 | ||
| 752 | WARN_ON((slot < 0) || (slot > 31)); | 752 | WARN_ON((slot < 0) || (slot > 31)); |
| 753 | WARN_ON(qtd->length && !qtd->payload_addr); | 753 | WARN_ON(qtd->length && !qtd->payload_addr); |
| 754 | WARN_ON(slots[slot].qtd); | 754 | WARN_ON(slots[slot].qtd); |
| 755 | WARN_ON(slots[slot].qh); | 755 | WARN_ON(slots[slot].qh); |
| 756 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); | 756 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); |
| 757 | 757 | ||
| 758 | /* Make sure done map has not triggered from some unlinked transfer */ | 758 | /* Make sure done map has not triggered from some unlinked transfer */ |
| 759 | if (ptd_offset == ATL_PTD_OFFSET) { | 759 | if (ptd_offset == ATL_PTD_OFFSET) { |
| 760 | priv->atl_done_map |= reg_read32(hcd->regs, | 760 | priv->atl_done_map |= reg_read32(hcd->regs, |
| 761 | HC_ATL_PTD_DONEMAP_REG); | 761 | HC_ATL_PTD_DONEMAP_REG); |
| 762 | priv->atl_done_map &= ~(1 << slot); | 762 | priv->atl_done_map &= ~(1 << slot); |
| 763 | } else { | 763 | } else { |
| 764 | priv->int_done_map |= reg_read32(hcd->regs, | 764 | priv->int_done_map |= reg_read32(hcd->regs, |
| 765 | HC_INT_PTD_DONEMAP_REG); | 765 | HC_INT_PTD_DONEMAP_REG); |
| 766 | priv->int_done_map &= ~(1 << slot); | 766 | priv->int_done_map &= ~(1 << slot); |
| 767 | } | 767 | } |
| 768 | 768 | ||
| 769 | qh->slot = slot; | 769 | qh->slot = slot; |
| 770 | qtd->status = QTD_XFER_STARTED; | 770 | qtd->status = QTD_XFER_STARTED; |
| 771 | slots[slot].timestamp = jiffies; | 771 | slots[slot].timestamp = jiffies; |
| 772 | slots[slot].qtd = qtd; | 772 | slots[slot].qtd = qtd; |
| 773 | slots[slot].qh = qh; | 773 | slots[slot].qh = qh; |
| 774 | ptd_write(hcd->regs, ptd_offset, slot, ptd); | 774 | ptd_write(hcd->regs, ptd_offset, slot, ptd); |
| 775 | 775 | ||
| 776 | if (ptd_offset == ATL_PTD_OFFSET) { | 776 | if (ptd_offset == ATL_PTD_OFFSET) { |
| 777 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | 777 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
| 778 | skip_map &= ~(1 << qh->slot); | 778 | skip_map &= ~(1 << qh->slot); |
| 779 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | 779 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); |
| 780 | } else { | 780 | } else { |
| 781 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | 781 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
| 782 | skip_map &= ~(1 << qh->slot); | 782 | skip_map &= ~(1 << qh->slot); |
| 783 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); | 783 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); |
| 784 | } | 784 | } |
| 785 | } | 785 | } |
| 786 | 786 | ||
| 787 | static int is_short_bulk(struct isp1760_qtd *qtd) | 787 | static int is_short_bulk(struct isp1760_qtd *qtd) |
| 788 | { | 788 | { |
| 789 | return (usb_pipebulk(qtd->urb->pipe) && | 789 | return (usb_pipebulk(qtd->urb->pipe) && |
| 790 | (qtd->actual_length < qtd->length)); | 790 | (qtd->actual_length < qtd->length)); |
| 791 | } | 791 | } |
| 792 | 792 | ||
| 793 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, | 793 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 794 | struct list_head *urb_list) | 794 | struct list_head *urb_list) |
| 795 | { | 795 | { |
| 796 | int last_qtd; | 796 | int last_qtd; |
| 797 | struct isp1760_qtd *qtd, *qtd_next; | 797 | struct isp1760_qtd *qtd, *qtd_next; |
| 798 | struct urb_listitem *urb_listitem; | 798 | struct urb_listitem *urb_listitem; |
| 799 | 799 | ||
| 800 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { | 800 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
| 801 | if (qtd->status < QTD_XFER_COMPLETE) | 801 | if (qtd->status < QTD_XFER_COMPLETE) |
| 802 | break; | 802 | break; |
| 803 | 803 | ||
| 804 | last_qtd = last_qtd_of_urb(qtd, qh); | 804 | last_qtd = last_qtd_of_urb(qtd, qh); |
| 805 | 805 | ||
| 806 | if ((!last_qtd) && (qtd->status == QTD_RETIRE)) | 806 | if ((!last_qtd) && (qtd->status == QTD_RETIRE)) |
| 807 | qtd_next->status = QTD_RETIRE; | 807 | qtd_next->status = QTD_RETIRE; |
| 808 | 808 | ||
| 809 | if (qtd->status == QTD_XFER_COMPLETE) { | 809 | if (qtd->status == QTD_XFER_COMPLETE) { |
| 810 | if (qtd->actual_length) { | 810 | if (qtd->actual_length) { |
| 811 | switch (qtd->packet_type) { | 811 | switch (qtd->packet_type) { |
| 812 | case IN_PID: | 812 | case IN_PID: |
| 813 | mem_reads8(hcd->regs, qtd->payload_addr, | 813 | mem_reads8(hcd->regs, qtd->payload_addr, |
| 814 | qtd->data_buffer, | 814 | qtd->data_buffer, |
| 815 | qtd->actual_length); | 815 | qtd->actual_length); |
| 816 | /* Fall through (?) */ | 816 | /* Fall through (?) */ |
| 817 | case OUT_PID: | 817 | case OUT_PID: |
| 818 | qtd->urb->actual_length += | 818 | qtd->urb->actual_length += |
| 819 | qtd->actual_length; | 819 | qtd->actual_length; |
| 820 | /* Fall through ... */ | 820 | /* Fall through ... */ |
| 821 | case SETUP_PID: | 821 | case SETUP_PID: |
| 822 | break; | 822 | break; |
| 823 | } | 823 | } |
| 824 | } | 824 | } |
| 825 | 825 | ||
| 826 | if (is_short_bulk(qtd)) { | 826 | if (is_short_bulk(qtd)) { |
| 827 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) | 827 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 828 | qtd->urb->status = -EREMOTEIO; | 828 | qtd->urb->status = -EREMOTEIO; |
| 829 | if (!last_qtd) | 829 | if (!last_qtd) |
| 830 | qtd_next->status = QTD_RETIRE; | 830 | qtd_next->status = QTD_RETIRE; |
| 831 | } | 831 | } |
| 832 | } | 832 | } |
| 833 | 833 | ||
| 834 | if (qtd->payload_addr) | 834 | if (qtd->payload_addr) |
| 835 | free_mem(hcd, qtd); | 835 | free_mem(hcd, qtd); |
| 836 | 836 | ||
| 837 | if (last_qtd) { | 837 | if (last_qtd) { |
| 838 | if ((qtd->status == QTD_RETIRE) && | 838 | if ((qtd->status == QTD_RETIRE) && |
| 839 | (qtd->urb->status == -EINPROGRESS)) | 839 | (qtd->urb->status == -EINPROGRESS)) |
| 840 | qtd->urb->status = -EPIPE; | 840 | qtd->urb->status = -EPIPE; |
| 841 | /* Defer calling of urb_done() since it releases lock */ | 841 | /* Defer calling of urb_done() since it releases lock */ |
| 842 | urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, | 842 | urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, |
| 843 | GFP_ATOMIC); | 843 | GFP_ATOMIC); |
| 844 | if (unlikely(!urb_listitem)) | 844 | if (unlikely(!urb_listitem)) |
| 845 | break; /* Try again on next call */ | 845 | break; /* Try again on next call */ |
| 846 | urb_listitem->urb = qtd->urb; | 846 | urb_listitem->urb = qtd->urb; |
| 847 | list_add_tail(&urb_listitem->urb_list, urb_list); | 847 | list_add_tail(&urb_listitem->urb_list, urb_list); |
| 848 | } | 848 | } |
| 849 | 849 | ||
| 850 | list_del(&qtd->qtd_list); | 850 | list_del(&qtd->qtd_list); |
| 851 | qtd_free(qtd); | 851 | qtd_free(qtd); |
| 852 | } | 852 | } |
| 853 | } | 853 | } |
| 854 | 854 | ||
| 855 | #define ENQUEUE_DEPTH 2 | 855 | #define ENQUEUE_DEPTH 2 |
| 856 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) | 856 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) |
| 857 | { | 857 | { |
| 858 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 858 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 859 | int ptd_offset; | 859 | int ptd_offset; |
| 860 | struct slotinfo *slots; | 860 | struct slotinfo *slots; |
| 861 | int curr_slot, free_slot; | 861 | int curr_slot, free_slot; |
| 862 | int n; | 862 | int n; |
| 863 | struct ptd ptd; | 863 | struct ptd ptd; |
| 864 | struct isp1760_qtd *qtd; | 864 | struct isp1760_qtd *qtd; |
| 865 | 865 | ||
| 866 | if (unlikely(list_empty(&qh->qtd_list))) { | 866 | if (unlikely(list_empty(&qh->qtd_list))) { |
| 867 | WARN_ON(1); | 867 | WARN_ON(1); |
| 868 | return; | 868 | return; |
| 869 | } | 869 | } |
| 870 | 870 | ||
| 871 | /* Make sure this endpoint's TT buffer is clean before queueing ptds */ | 871 | /* Make sure this endpoint's TT buffer is clean before queueing ptds */ |
| 872 | if (qh->tt_buffer_dirty) | 872 | if (qh->tt_buffer_dirty) |
| 873 | return; | 873 | return; |
| 874 | 874 | ||
| 875 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, | 875 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
| 876 | qtd_list)->urb->pipe)) { | 876 | qtd_list)->urb->pipe)) { |
| 877 | ptd_offset = INT_PTD_OFFSET; | 877 | ptd_offset = INT_PTD_OFFSET; |
| 878 | slots = priv->int_slots; | 878 | slots = priv->int_slots; |
| 879 | } else { | 879 | } else { |
| 880 | ptd_offset = ATL_PTD_OFFSET; | 880 | ptd_offset = ATL_PTD_OFFSET; |
| 881 | slots = priv->atl_slots; | 881 | slots = priv->atl_slots; |
| 882 | } | 882 | } |
| 883 | 883 | ||
| 884 | free_slot = -1; | 884 | free_slot = -1; |
| 885 | for (curr_slot = 0; curr_slot < 32; curr_slot++) { | 885 | for (curr_slot = 0; curr_slot < 32; curr_slot++) { |
| 886 | if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) | 886 | if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) |
| 887 | free_slot = curr_slot; | 887 | free_slot = curr_slot; |
| 888 | if (slots[curr_slot].qh == qh) | 888 | if (slots[curr_slot].qh == qh) |
| 889 | break; | 889 | break; |
| 890 | } | 890 | } |
| 891 | 891 | ||
| 892 | n = 0; | 892 | n = 0; |
| 893 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { | 893 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
| 894 | if (qtd->status == QTD_ENQUEUED) { | 894 | if (qtd->status == QTD_ENQUEUED) { |
| 895 | WARN_ON(qtd->payload_addr); | 895 | WARN_ON(qtd->payload_addr); |
| 896 | alloc_mem(hcd, qtd); | 896 | alloc_mem(hcd, qtd); |
| 897 | if ((qtd->length) && (!qtd->payload_addr)) | 897 | if ((qtd->length) && (!qtd->payload_addr)) |
| 898 | break; | 898 | break; |
| 899 | 899 | ||
| 900 | if ((qtd->length) && | 900 | if ((qtd->length) && |
| 901 | ((qtd->packet_type == SETUP_PID) || | 901 | ((qtd->packet_type == SETUP_PID) || |
| 902 | (qtd->packet_type == OUT_PID))) { | 902 | (qtd->packet_type == OUT_PID))) { |
| 903 | mem_writes8(hcd->regs, qtd->payload_addr, | 903 | mem_writes8(hcd->regs, qtd->payload_addr, |
| 904 | qtd->data_buffer, qtd->length); | 904 | qtd->data_buffer, qtd->length); |
| 905 | } | 905 | } |
| 906 | 906 | ||
| 907 | qtd->status = QTD_PAYLOAD_ALLOC; | 907 | qtd->status = QTD_PAYLOAD_ALLOC; |
| 908 | } | 908 | } |
| 909 | 909 | ||
| 910 | if (qtd->status == QTD_PAYLOAD_ALLOC) { | 910 | if (qtd->status == QTD_PAYLOAD_ALLOC) { |
| 911 | /* | 911 | /* |
| 912 | if ((curr_slot > 31) && (free_slot == -1)) | 912 | if ((curr_slot > 31) && (free_slot == -1)) |
| 913 | dev_dbg(hcd->self.controller, "%s: No slot " | 913 | dev_dbg(hcd->self.controller, "%s: No slot " |
| 914 | "available for transfer\n", __func__); | 914 | "available for transfer\n", __func__); |
| 915 | */ | 915 | */ |
| 916 | /* Start xfer for this endpoint if not already done */ | 916 | /* Start xfer for this endpoint if not already done */ |
| 917 | if ((curr_slot > 31) && (free_slot > -1)) { | 917 | if ((curr_slot > 31) && (free_slot > -1)) { |
| 918 | if (usb_pipeint(qtd->urb->pipe)) | 918 | if (usb_pipeint(qtd->urb->pipe)) |
| 919 | create_ptd_int(qh, qtd, &ptd); | 919 | create_ptd_int(qh, qtd, &ptd); |
| 920 | else | 920 | else |
| 921 | create_ptd_atl(qh, qtd, &ptd); | 921 | create_ptd_atl(qh, qtd, &ptd); |
| 922 | 922 | ||
| 923 | start_bus_transfer(hcd, ptd_offset, free_slot, | 923 | start_bus_transfer(hcd, ptd_offset, free_slot, |
| 924 | slots, qtd, qh, &ptd); | 924 | slots, qtd, qh, &ptd); |
| 925 | curr_slot = free_slot; | 925 | curr_slot = free_slot; |
| 926 | } | 926 | } |
| 927 | 927 | ||
| 928 | n++; | 928 | n++; |
| 929 | if (n >= ENQUEUE_DEPTH) | 929 | if (n >= ENQUEUE_DEPTH) |
| 930 | break; | 930 | break; |
| 931 | } | 931 | } |
| 932 | } | 932 | } |
| 933 | } | 933 | } |
| 934 | 934 | ||
| 935 | static void schedule_ptds(struct usb_hcd *hcd) | 935 | static void schedule_ptds(struct usb_hcd *hcd) |
| 936 | { | 936 | { |
| 937 | struct isp1760_hcd *priv; | 937 | struct isp1760_hcd *priv; |
| 938 | struct isp1760_qh *qh, *qh_next; | 938 | struct isp1760_qh *qh, *qh_next; |
| 939 | struct list_head *ep_queue; | 939 | struct list_head *ep_queue; |
| 940 | LIST_HEAD(urb_list); | 940 | LIST_HEAD(urb_list); |
| 941 | struct urb_listitem *urb_listitem, *urb_listitem_next; | 941 | struct urb_listitem *urb_listitem, *urb_listitem_next; |
| 942 | int i; | 942 | int i; |
| 943 | 943 | ||
| 944 | if (!hcd) { | 944 | if (!hcd) { |
| 945 | WARN_ON(1); | 945 | WARN_ON(1); |
| 946 | return; | 946 | return; |
| 947 | } | 947 | } |
| 948 | 948 | ||
| 949 | priv = hcd_to_priv(hcd); | 949 | priv = hcd_to_priv(hcd); |
| 950 | 950 | ||
| 951 | /* | 951 | /* |
| 952 | * check finished/retired xfers, transfer payloads, call urb_done() | 952 | * check finished/retired xfers, transfer payloads, call urb_done() |
| 953 | */ | 953 | */ |
| 954 | for (i = 0; i < QH_END; i++) { | 954 | for (i = 0; i < QH_END; i++) { |
| 955 | ep_queue = &priv->qh_list[i]; | 955 | ep_queue = &priv->qh_list[i]; |
| 956 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { | 956 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { |
| 957 | collect_qtds(hcd, qh, &urb_list); | 957 | collect_qtds(hcd, qh, &urb_list); |
| 958 | if (list_empty(&qh->qtd_list)) | 958 | if (list_empty(&qh->qtd_list)) |
| 959 | list_del(&qh->qh_list); | 959 | list_del(&qh->qh_list); |
| 960 | } | 960 | } |
| 961 | } | 961 | } |
| 962 | 962 | ||
| 963 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, | 963 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
| 964 | urb_list) { | 964 | urb_list) { |
| 965 | isp1760_urb_done(hcd, urb_listitem->urb); | 965 | isp1760_urb_done(hcd, urb_listitem->urb); |
| 966 | kmem_cache_free(urb_listitem_cachep, urb_listitem); | 966 | kmem_cache_free(urb_listitem_cachep, urb_listitem); |
| 967 | } | 967 | } |
| 968 | 968 | ||
| 969 | /* | 969 | /* |
| 970 | * Schedule packets for transfer. | 970 | * Schedule packets for transfer. |
| 971 | * | 971 | * |
| 972 | * According to USB2.0 specification: | 972 | * According to USB2.0 specification: |
| 973 | * | 973 | * |
| 974 | * 1st prio: interrupt xfers, up to 80 % of bandwidth | 974 | * 1st prio: interrupt xfers, up to 80 % of bandwidth |
| 975 | * 2nd prio: control xfers | 975 | * 2nd prio: control xfers |
| 976 | * 3rd prio: bulk xfers | 976 | * 3rd prio: bulk xfers |
| 977 | * | 977 | * |
| 978 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc | 978 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc |
| 979 | * is very unclear on how to prioritize traffic): | 979 | * is very unclear on how to prioritize traffic): |
| 980 | * | 980 | * |
| 981 | * 1) Enqueue any queued control transfers, as long as payload chip mem | 981 | * 1) Enqueue any queued control transfers, as long as payload chip mem |
| 982 | * and PTD ATL slots are available. | 982 | * and PTD ATL slots are available. |
| 983 | * 2) Enqueue any queued INT transfers, as long as payload chip mem | 983 | * 2) Enqueue any queued INT transfers, as long as payload chip mem |
| 984 | * and PTD INT slots are available. | 984 | * and PTD INT slots are available. |
| 985 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem | 985 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem |
| 986 | * and PTD ATL slots are available. | 986 | * and PTD ATL slots are available. |
| 987 | * | 987 | * |
| 988 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between | 988 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between |
| 989 | * conservation of chip mem and performance. | 989 | * conservation of chip mem and performance. |
| 990 | * | 990 | * |
| 991 | * I'm sure this scheme could be improved upon! | 991 | * I'm sure this scheme could be improved upon! |
| 992 | */ | 992 | */ |
| 993 | for (i = 0; i < QH_END; i++) { | 993 | for (i = 0; i < QH_END; i++) { |
| 994 | ep_queue = &priv->qh_list[i]; | 994 | ep_queue = &priv->qh_list[i]; |
| 995 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) | 995 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) |
| 996 | enqueue_qtds(hcd, qh); | 996 | enqueue_qtds(hcd, qh); |
| 997 | } | 997 | } |
| 998 | } | 998 | } |
| 999 | 999 | ||
| 1000 | #define PTD_STATE_QTD_DONE 1 | 1000 | #define PTD_STATE_QTD_DONE 1 |
| 1001 | #define PTD_STATE_QTD_RELOAD 2 | 1001 | #define PTD_STATE_QTD_RELOAD 2 |
| 1002 | #define PTD_STATE_URB_RETIRE 3 | 1002 | #define PTD_STATE_URB_RETIRE 3 |
| 1003 | 1003 | ||
| 1004 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, | 1004 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
| 1005 | struct urb *urb) | 1005 | struct urb *urb) |
| 1006 | { | 1006 | { |
| 1007 | __dw dw4; | 1007 | __dw dw4; |
| 1008 | int i; | 1008 | int i; |
| 1009 | 1009 | ||
| 1010 | dw4 = ptd->dw4; | 1010 | dw4 = ptd->dw4; |
| 1011 | dw4 >>= 8; | 1011 | dw4 >>= 8; |
| 1012 | 1012 | ||
| 1013 | /* FIXME: ISP1761 datasheet does not say what to do with these. Do we | 1013 | /* FIXME: ISP1761 datasheet does not say what to do with these. Do we |
| 1014 | need to handle these errors? Is it done in hardware? */ | 1014 | need to handle these errors? Is it done in hardware? */ |
| 1015 | 1015 | ||
| 1016 | if (ptd->dw3 & DW3_HALT_BIT) { | 1016 | if (ptd->dw3 & DW3_HALT_BIT) { |
| 1017 | 1017 | ||
| 1018 | urb->status = -EPROTO; /* Default unknown error */ | 1018 | urb->status = -EPROTO; /* Default unknown error */ |
| 1019 | 1019 | ||
| 1020 | for (i = 0; i < 8; i++) { | 1020 | for (i = 0; i < 8; i++) { |
| 1021 | switch (dw4 & 0x7) { | 1021 | switch (dw4 & 0x7) { |
| 1022 | case INT_UNDERRUN: | 1022 | case INT_UNDERRUN: |
| 1023 | dev_dbg(hcd->self.controller, "%s: underrun " | 1023 | dev_dbg(hcd->self.controller, "%s: underrun " |
| 1024 | "during uFrame %d\n", | 1024 | "during uFrame %d\n", |
| 1025 | __func__, i); | 1025 | __func__, i); |
| 1026 | urb->status = -ECOMM; /* Could not write data */ | 1026 | urb->status = -ECOMM; /* Could not write data */ |
| 1027 | break; | 1027 | break; |
| 1028 | case INT_EXACT: | 1028 | case INT_EXACT: |
| 1029 | dev_dbg(hcd->self.controller, "%s: transaction " | 1029 | dev_dbg(hcd->self.controller, "%s: transaction " |
| 1030 | "error during uFrame %d\n", | 1030 | "error during uFrame %d\n", |
| 1031 | __func__, i); | 1031 | __func__, i); |
| 1032 | urb->status = -EPROTO; /* timeout, bad CRC, PID | 1032 | urb->status = -EPROTO; /* timeout, bad CRC, PID |
| 1033 | error etc. */ | 1033 | error etc. */ |
| 1034 | break; | 1034 | break; |
| 1035 | case INT_BABBLE: | 1035 | case INT_BABBLE: |
| 1036 | dev_dbg(hcd->self.controller, "%s: babble " | 1036 | dev_dbg(hcd->self.controller, "%s: babble " |
| 1037 | "error during uFrame %d\n", | 1037 | "error during uFrame %d\n", |
| 1038 | __func__, i); | 1038 | __func__, i); |
| 1039 | urb->status = -EOVERFLOW; | 1039 | urb->status = -EOVERFLOW; |
| 1040 | break; | 1040 | break; |
| 1041 | } | 1041 | } |
| 1042 | dw4 >>= 3; | 1042 | dw4 >>= 3; |
| 1043 | } | 1043 | } |
| 1044 | 1044 | ||
| 1045 | return PTD_STATE_URB_RETIRE; | 1045 | return PTD_STATE_URB_RETIRE; |
| 1046 | } | 1046 | } |
| 1047 | 1047 | ||
| 1048 | return PTD_STATE_QTD_DONE; | 1048 | return PTD_STATE_QTD_DONE; |
| 1049 | } | 1049 | } |
| 1050 | 1050 | ||
| 1051 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, | 1051 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
| 1052 | struct urb *urb) | 1052 | struct urb *urb) |
| 1053 | { | 1053 | { |
| 1054 | WARN_ON(!ptd); | 1054 | WARN_ON(!ptd); |
| 1055 | if (ptd->dw3 & DW3_HALT_BIT) { | 1055 | if (ptd->dw3 & DW3_HALT_BIT) { |
| 1056 | if (ptd->dw3 & DW3_BABBLE_BIT) | 1056 | if (ptd->dw3 & DW3_BABBLE_BIT) |
| 1057 | urb->status = -EOVERFLOW; | 1057 | urb->status = -EOVERFLOW; |
| 1058 | else if (FROM_DW3_CERR(ptd->dw3)) | 1058 | else if (FROM_DW3_CERR(ptd->dw3)) |
| 1059 | urb->status = -EPIPE; /* Stall */ | 1059 | urb->status = -EPIPE; /* Stall */ |
| 1060 | else if (ptd->dw3 & DW3_ERROR_BIT) | 1060 | else if (ptd->dw3 & DW3_ERROR_BIT) |
| 1061 | urb->status = -EPROTO; /* XactErr */ | 1061 | urb->status = -EPROTO; /* XactErr */ |
| 1062 | else | 1062 | else |
| 1063 | urb->status = -EPROTO; /* Unknown */ | 1063 | urb->status = -EPROTO; /* Unknown */ |
| 1064 | /* | 1064 | /* |
| 1065 | dev_dbg(hcd->self.controller, "%s: ptd error:\n" | 1065 | dev_dbg(hcd->self.controller, "%s: ptd error:\n" |
| 1066 | " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" | 1066 | " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" |
| 1067 | " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", | 1067 | " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", |
| 1068 | __func__, | 1068 | __func__, |
| 1069 | ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, | 1069 | ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, |
| 1070 | ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); | 1070 | ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); |
| 1071 | */ | 1071 | */ |
| 1072 | return PTD_STATE_URB_RETIRE; | 1072 | return PTD_STATE_URB_RETIRE; |
| 1073 | } | 1073 | } |
| 1074 | 1074 | ||
| 1075 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { | 1075 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
| 1076 | /* Transfer Error, *but* active and no HALT -> reload */ | 1076 | /* Transfer Error, *but* active and no HALT -> reload */ |
| 1077 | dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); | 1077 | dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); |
| 1078 | return PTD_STATE_QTD_RELOAD; | 1078 | return PTD_STATE_QTD_RELOAD; |
| 1079 | } | 1079 | } |
| 1080 | 1080 | ||
| 1081 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { | 1081 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
| 1082 | /* | 1082 | /* |
| 1083 | * NAKs are handled in HW by the chip. Usually if the | 1083 | * NAKs are handled in HW by the chip. Usually if the |
| 1084 | * device is not able to send data fast enough. | 1084 | * device is not able to send data fast enough. |
| 1085 | * This happens mostly on slower hardware. | 1085 | * This happens mostly on slower hardware. |
| 1086 | */ | 1086 | */ |
| 1087 | return PTD_STATE_QTD_RELOAD; | 1087 | return PTD_STATE_QTD_RELOAD; |
| 1088 | } | 1088 | } |
| 1089 | 1089 | ||
| 1090 | return PTD_STATE_QTD_DONE; | 1090 | return PTD_STATE_QTD_DONE; |
| 1091 | } | 1091 | } |
| 1092 | 1092 | ||
| 1093 | static void handle_done_ptds(struct usb_hcd *hcd) | 1093 | static void handle_done_ptds(struct usb_hcd *hcd) |
| 1094 | { | 1094 | { |
| 1095 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1095 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1096 | struct ptd ptd; | 1096 | struct ptd ptd; |
| 1097 | struct isp1760_qh *qh; | 1097 | struct isp1760_qh *qh; |
| 1098 | int slot; | 1098 | int slot; |
| 1099 | int state; | 1099 | int state; |
| 1100 | struct slotinfo *slots; | 1100 | struct slotinfo *slots; |
| 1101 | u32 ptd_offset; | 1101 | u32 ptd_offset; |
| 1102 | struct isp1760_qtd *qtd; | 1102 | struct isp1760_qtd *qtd; |
| 1103 | int modified; | 1103 | int modified; |
| 1104 | int skip_map; | 1104 | int skip_map; |
| 1105 | 1105 | ||
| 1106 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | 1106 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
| 1107 | priv->int_done_map &= ~skip_map; | 1107 | priv->int_done_map &= ~skip_map; |
| 1108 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | 1108 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
| 1109 | priv->atl_done_map &= ~skip_map; | 1109 | priv->atl_done_map &= ~skip_map; |
| 1110 | 1110 | ||
| 1111 | modified = priv->int_done_map || priv->atl_done_map; | 1111 | modified = priv->int_done_map || priv->atl_done_map; |
| 1112 | 1112 | ||
| 1113 | while (priv->int_done_map || priv->atl_done_map) { | 1113 | while (priv->int_done_map || priv->atl_done_map) { |
| 1114 | if (priv->int_done_map) { | 1114 | if (priv->int_done_map) { |
| 1115 | /* INT ptd */ | 1115 | /* INT ptd */ |
| 1116 | slot = __ffs(priv->int_done_map); | 1116 | slot = __ffs(priv->int_done_map); |
| 1117 | priv->int_done_map &= ~(1 << slot); | 1117 | priv->int_done_map &= ~(1 << slot); |
| 1118 | slots = priv->int_slots; | 1118 | slots = priv->int_slots; |
| 1119 | /* This should not trigger, and could be removed if | 1119 | /* This should not trigger, and could be removed if |
| 1120 | noone have any problems with it triggering: */ | 1120 | noone have any problems with it triggering: */ |
| 1121 | if (!slots[slot].qh) { | 1121 | if (!slots[slot].qh) { |
| 1122 | WARN_ON(1); | 1122 | WARN_ON(1); |
| 1123 | continue; | 1123 | continue; |
| 1124 | } | 1124 | } |
| 1125 | ptd_offset = INT_PTD_OFFSET; | 1125 | ptd_offset = INT_PTD_OFFSET; |
| 1126 | ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); | 1126 | ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); |
| 1127 | state = check_int_transfer(hcd, &ptd, | 1127 | state = check_int_transfer(hcd, &ptd, |
| 1128 | slots[slot].qtd->urb); | 1128 | slots[slot].qtd->urb); |
| 1129 | } else { | 1129 | } else { |
| 1130 | /* ATL ptd */ | 1130 | /* ATL ptd */ |
| 1131 | slot = __ffs(priv->atl_done_map); | 1131 | slot = __ffs(priv->atl_done_map); |
| 1132 | priv->atl_done_map &= ~(1 << slot); | 1132 | priv->atl_done_map &= ~(1 << slot); |
| 1133 | slots = priv->atl_slots; | 1133 | slots = priv->atl_slots; |
| 1134 | /* This should not trigger, and could be removed if | 1134 | /* This should not trigger, and could be removed if |
| 1135 | noone have any problems with it triggering: */ | 1135 | noone have any problems with it triggering: */ |
| 1136 | if (!slots[slot].qh) { | 1136 | if (!slots[slot].qh) { |
| 1137 | WARN_ON(1); | 1137 | WARN_ON(1); |
| 1138 | continue; | 1138 | continue; |
| 1139 | } | 1139 | } |
| 1140 | ptd_offset = ATL_PTD_OFFSET; | 1140 | ptd_offset = ATL_PTD_OFFSET; |
| 1141 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); | 1141 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); |
| 1142 | state = check_atl_transfer(hcd, &ptd, | 1142 | state = check_atl_transfer(hcd, &ptd, |
| 1143 | slots[slot].qtd->urb); | 1143 | slots[slot].qtd->urb); |
| 1144 | } | 1144 | } |
| 1145 | 1145 | ||
| 1146 | qtd = slots[slot].qtd; | 1146 | qtd = slots[slot].qtd; |
| 1147 | slots[slot].qtd = NULL; | 1147 | slots[slot].qtd = NULL; |
| 1148 | qh = slots[slot].qh; | 1148 | qh = slots[slot].qh; |
| 1149 | slots[slot].qh = NULL; | 1149 | slots[slot].qh = NULL; |
| 1150 | qh->slot = -1; | 1150 | qh->slot = -1; |
| 1151 | 1151 | ||
| 1152 | WARN_ON(qtd->status != QTD_XFER_STARTED); | 1152 | WARN_ON(qtd->status != QTD_XFER_STARTED); |
| 1153 | 1153 | ||
| 1154 | switch (state) { | 1154 | switch (state) { |
| 1155 | case PTD_STATE_QTD_DONE: | 1155 | case PTD_STATE_QTD_DONE: |
| 1156 | if ((usb_pipeint(qtd->urb->pipe)) && | 1156 | if ((usb_pipeint(qtd->urb->pipe)) && |
| 1157 | (qtd->urb->dev->speed != USB_SPEED_HIGH)) | 1157 | (qtd->urb->dev->speed != USB_SPEED_HIGH)) |
| 1158 | qtd->actual_length = | 1158 | qtd->actual_length = |
| 1159 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); | 1159 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); |
| 1160 | else | 1160 | else |
| 1161 | qtd->actual_length = | 1161 | qtd->actual_length = |
| 1162 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); | 1162 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); |
| 1163 | 1163 | ||
| 1164 | qtd->status = QTD_XFER_COMPLETE; | 1164 | qtd->status = QTD_XFER_COMPLETE; |
| 1165 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || | 1165 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || |
| 1166 | is_short_bulk(qtd)) | 1166 | is_short_bulk(qtd)) |
| 1167 | qtd = NULL; | 1167 | qtd = NULL; |
| 1168 | else | 1168 | else |
| 1169 | qtd = list_entry(qtd->qtd_list.next, | 1169 | qtd = list_entry(qtd->qtd_list.next, |
| 1170 | typeof(*qtd), qtd_list); | 1170 | typeof(*qtd), qtd_list); |
| 1171 | 1171 | ||
| 1172 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | 1172 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
| 1173 | qh->ping = FROM_DW3_PING(ptd.dw3); | 1173 | qh->ping = FROM_DW3_PING(ptd.dw3); |
| 1174 | break; | 1174 | break; |
| 1175 | 1175 | ||
| 1176 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ | 1176 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
| 1177 | qtd->status = QTD_PAYLOAD_ALLOC; | 1177 | qtd->status = QTD_PAYLOAD_ALLOC; |
| 1178 | ptd.dw0 |= DW0_VALID_BIT; | 1178 | ptd.dw0 |= DW0_VALID_BIT; |
| 1179 | /* RL counter = ERR counter */ | 1179 | /* RL counter = ERR counter */ |
| 1180 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); | 1180 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); |
| 1181 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); | 1181 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); |
| 1182 | ptd.dw3 &= ~TO_DW3_CERR(3); | 1182 | ptd.dw3 &= ~TO_DW3_CERR(3); |
| 1183 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); | 1183 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); |
| 1184 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | 1184 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
| 1185 | qh->ping = FROM_DW3_PING(ptd.dw3); | 1185 | qh->ping = FROM_DW3_PING(ptd.dw3); |
| 1186 | break; | 1186 | break; |
| 1187 | 1187 | ||
| 1188 | case PTD_STATE_URB_RETIRE: | 1188 | case PTD_STATE_URB_RETIRE: |
| 1189 | qtd->status = QTD_RETIRE; | 1189 | qtd->status = QTD_RETIRE; |
| 1190 | if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && | 1190 | if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && |
| 1191 | (qtd->urb->status != -EPIPE) && | 1191 | (qtd->urb->status != -EPIPE) && |
| 1192 | (qtd->urb->status != -EREMOTEIO)) { | 1192 | (qtd->urb->status != -EREMOTEIO)) { |
| 1193 | qh->tt_buffer_dirty = 1; | 1193 | qh->tt_buffer_dirty = 1; |
| 1194 | if (usb_hub_clear_tt_buffer(qtd->urb)) | 1194 | if (usb_hub_clear_tt_buffer(qtd->urb)) |
| 1195 | /* Clear failed; let's hope things work | 1195 | /* Clear failed; let's hope things work |
| 1196 | anyway */ | 1196 | anyway */ |
| 1197 | qh->tt_buffer_dirty = 0; | 1197 | qh->tt_buffer_dirty = 0; |
| 1198 | } | 1198 | } |
| 1199 | qtd = NULL; | 1199 | qtd = NULL; |
| 1200 | qh->toggle = 0; | 1200 | qh->toggle = 0; |
| 1201 | qh->ping = 0; | 1201 | qh->ping = 0; |
| 1202 | break; | 1202 | break; |
| 1203 | 1203 | ||
| 1204 | default: | 1204 | default: |
| 1205 | WARN_ON(1); | 1205 | WARN_ON(1); |
| 1206 | continue; | 1206 | continue; |
| 1207 | } | 1207 | } |
| 1208 | 1208 | ||
| 1209 | if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { | 1209 | if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { |
| 1210 | if (slots == priv->int_slots) { | 1210 | if (slots == priv->int_slots) { |
| 1211 | if (state == PTD_STATE_QTD_RELOAD) | 1211 | if (state == PTD_STATE_QTD_RELOAD) |
| 1212 | dev_err(hcd->self.controller, | 1212 | dev_err(hcd->self.controller, |
| 1213 | "%s: PTD_STATE_QTD_RELOAD on " | 1213 | "%s: PTD_STATE_QTD_RELOAD on " |
| 1214 | "interrupt packet\n", __func__); | 1214 | "interrupt packet\n", __func__); |
| 1215 | if (state != PTD_STATE_QTD_RELOAD) | 1215 | if (state != PTD_STATE_QTD_RELOAD) |
| 1216 | create_ptd_int(qh, qtd, &ptd); | 1216 | create_ptd_int(qh, qtd, &ptd); |
| 1217 | } else { | 1217 | } else { |
| 1218 | if (state != PTD_STATE_QTD_RELOAD) | 1218 | if (state != PTD_STATE_QTD_RELOAD) |
| 1219 | create_ptd_atl(qh, qtd, &ptd); | 1219 | create_ptd_atl(qh, qtd, &ptd); |
| 1220 | } | 1220 | } |
| 1221 | 1221 | ||
| 1222 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, | 1222 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
| 1223 | qh, &ptd); | 1223 | qh, &ptd); |
| 1224 | } | 1224 | } |
| 1225 | } | 1225 | } |
| 1226 | 1226 | ||
| 1227 | if (modified) | 1227 | if (modified) |
| 1228 | schedule_ptds(hcd); | 1228 | schedule_ptds(hcd); |
| 1229 | } | 1229 | } |
| 1230 | 1230 | ||
| 1231 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) | 1231 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) |
| 1232 | { | 1232 | { |
| 1233 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1233 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1234 | u32 imask; | 1234 | u32 imask; |
| 1235 | irqreturn_t irqret = IRQ_NONE; | 1235 | irqreturn_t irqret = IRQ_NONE; |
| 1236 | 1236 | ||
| 1237 | spin_lock(&priv->lock); | 1237 | spin_lock(&priv->lock); |
| 1238 | 1238 | ||
| 1239 | if (!(hcd->state & HC_STATE_RUNNING)) | 1239 | if (!(hcd->state & HC_STATE_RUNNING)) |
| 1240 | goto leave; | 1240 | goto leave; |
| 1241 | 1241 | ||
| 1242 | imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); | 1242 | imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); |
| 1243 | if (unlikely(!imask)) | 1243 | if (unlikely(!imask)) |
| 1244 | goto leave; | 1244 | goto leave; |
| 1245 | reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ | 1245 | reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ |
| 1246 | 1246 | ||
| 1247 | priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); | 1247 | priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); |
| 1248 | priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); | 1248 | priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); |
| 1249 | 1249 | ||
| 1250 | handle_done_ptds(hcd); | 1250 | handle_done_ptds(hcd); |
| 1251 | 1251 | ||
| 1252 | irqret = IRQ_HANDLED; | 1252 | irqret = IRQ_HANDLED; |
| 1253 | leave: | 1253 | leave: |
| 1254 | spin_unlock(&priv->lock); | 1254 | spin_unlock(&priv->lock); |
| 1255 | 1255 | ||
| 1256 | return irqret; | 1256 | return irqret; |
| 1257 | } | 1257 | } |
| 1258 | 1258 | ||
| 1259 | /* | 1259 | /* |
| 1260 | * Workaround for problem described in chip errata 2: | 1260 | * Workaround for problem described in chip errata 2: |
| 1261 | * | 1261 | * |
| 1262 | * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. | 1262 | * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. |
| 1263 | * One solution suggested in the errata is to use SOF interrupts _instead_of_ | 1263 | * One solution suggested in the errata is to use SOF interrupts _instead_of_ |
| 1264 | * ATL done interrupts (the "instead of" might be important since it seems | 1264 | * ATL done interrupts (the "instead of" might be important since it seems |
| 1265 | * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" | 1265 | * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" |
| 1266 | * to set the PTD's done bit in addition to not generating an interrupt!). | 1266 | * to set the PTD's done bit in addition to not generating an interrupt!). |
| 1267 | * | 1267 | * |
| 1268 | * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their | 1268 | * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their |
| 1269 | * done bit is not being set. This is bad - it blocks the endpoint until reboot. | 1269 | * done bit is not being set. This is bad - it blocks the endpoint until reboot. |
| 1270 | * | 1270 | * |
| 1271 | * If we use SOF interrupts only, we get latency between ptd completion and the | 1271 | * If we use SOF interrupts only, we get latency between ptd completion and the |
| 1272 | * actual handling. This is very noticeable in testusb runs which takes several | 1272 | * actual handling. This is very noticeable in testusb runs which takes several |
| 1273 | * minutes longer without ATL interrupts. | 1273 | * minutes longer without ATL interrupts. |
| 1274 | * | 1274 | * |
| 1275 | * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it | 1275 | * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it |
| 1276 | * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the | 1276 | * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the |
| 1277 | * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered | 1277 | * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered |
| 1278 | * completed and its done map bit is set. | 1278 | * completed and its done map bit is set. |
| 1279 | * | 1279 | * |
| 1280 | * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen | 1280 | * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen |
| 1281 | * not to cause too much lag when this HW bug occurs, while still hopefully | 1281 | * not to cause too much lag when this HW bug occurs, while still hopefully |
| 1282 | * ensuring that the check does not falsely trigger. | 1282 | * ensuring that the check does not falsely trigger. |
| 1283 | */ | 1283 | */ |
| 1284 | #define SLOT_TIMEOUT 300 | 1284 | #define SLOT_TIMEOUT 300 |
| 1285 | #define SLOT_CHECK_PERIOD 200 | 1285 | #define SLOT_CHECK_PERIOD 200 |
| 1286 | static struct timer_list errata2_timer; | 1286 | static struct timer_list errata2_timer; |
| 1287 | 1287 | ||
| 1288 | static void errata2_function(unsigned long data) | 1288 | static void errata2_function(unsigned long data) |
| 1289 | { | 1289 | { |
| 1290 | struct usb_hcd *hcd = (struct usb_hcd *) data; | 1290 | struct usb_hcd *hcd = (struct usb_hcd *) data; |
| 1291 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1291 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1292 | int slot; | 1292 | int slot; |
| 1293 | struct ptd ptd; | 1293 | struct ptd ptd; |
| 1294 | unsigned long spinflags; | 1294 | unsigned long spinflags; |
| 1295 | 1295 | ||
| 1296 | spin_lock_irqsave(&priv->lock, spinflags); | 1296 | spin_lock_irqsave(&priv->lock, spinflags); |
| 1297 | 1297 | ||
| 1298 | for (slot = 0; slot < 32; slot++) | 1298 | for (slot = 0; slot < 32; slot++) |
| 1299 | if (priv->atl_slots[slot].qh && time_after(jiffies, | 1299 | if (priv->atl_slots[slot].qh && time_after(jiffies, |
| 1300 | priv->atl_slots[slot].timestamp + | 1300 | priv->atl_slots[slot].timestamp + |
| 1301 | SLOT_TIMEOUT * HZ / 1000)) { | 1301 | SLOT_TIMEOUT * HZ / 1000)) { |
| 1302 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); | 1302 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); |
| 1303 | if (!FROM_DW0_VALID(ptd.dw0) && | 1303 | if (!FROM_DW0_VALID(ptd.dw0) && |
| 1304 | !FROM_DW3_ACTIVE(ptd.dw3)) | 1304 | !FROM_DW3_ACTIVE(ptd.dw3)) |
| 1305 | priv->atl_done_map |= 1 << slot; | 1305 | priv->atl_done_map |= 1 << slot; |
| 1306 | } | 1306 | } |
| 1307 | 1307 | ||
| 1308 | if (priv->atl_done_map) | 1308 | if (priv->atl_done_map) |
| 1309 | handle_done_ptds(hcd); | 1309 | handle_done_ptds(hcd); |
| 1310 | 1310 | ||
| 1311 | spin_unlock_irqrestore(&priv->lock, spinflags); | 1311 | spin_unlock_irqrestore(&priv->lock, spinflags); |
| 1312 | 1312 | ||
| 1313 | errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; | 1313 | errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; |
| 1314 | add_timer(&errata2_timer); | 1314 | add_timer(&errata2_timer); |
| 1315 | } | 1315 | } |
| 1316 | 1316 | ||
| 1317 | static int isp1760_run(struct usb_hcd *hcd) | 1317 | static int isp1760_run(struct usb_hcd *hcd) |
| 1318 | { | 1318 | { |
| 1319 | int retval; | 1319 | int retval; |
| 1320 | u32 temp; | 1320 | u32 temp; |
| 1321 | u32 command; | 1321 | u32 command; |
| 1322 | u32 chipid; | 1322 | u32 chipid; |
| 1323 | 1323 | ||
| 1324 | hcd->uses_new_polling = 1; | 1324 | hcd->uses_new_polling = 1; |
| 1325 | 1325 | ||
| 1326 | hcd->state = HC_STATE_RUNNING; | 1326 | hcd->state = HC_STATE_RUNNING; |
| 1327 | 1327 | ||
| 1328 | /* Set PTD interrupt AND & OR maps */ | 1328 | /* Set PTD interrupt AND & OR maps */ |
| 1329 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); | 1329 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); |
| 1330 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); | 1330 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); |
| 1331 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); | 1331 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); |
| 1332 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); | 1332 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); |
| 1333 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); | 1333 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); |
| 1334 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); | 1334 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); |
| 1335 | /* step 23 passed */ | 1335 | /* step 23 passed */ |
| 1336 | 1336 | ||
| 1337 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); | 1337 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
| 1338 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); | 1338 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); |
| 1339 | 1339 | ||
| 1340 | command = reg_read32(hcd->regs, HC_USBCMD); | 1340 | command = reg_read32(hcd->regs, HC_USBCMD); |
| 1341 | command &= ~(CMD_LRESET|CMD_RESET); | 1341 | command &= ~(CMD_LRESET|CMD_RESET); |
| 1342 | command |= CMD_RUN; | 1342 | command |= CMD_RUN; |
| 1343 | reg_write32(hcd->regs, HC_USBCMD, command); | 1343 | reg_write32(hcd->regs, HC_USBCMD, command); |
| 1344 | 1344 | ||
| 1345 | retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); | 1345 | retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); |
| 1346 | if (retval) | 1346 | if (retval) |
| 1347 | return retval; | 1347 | return retval; |
| 1348 | 1348 | ||
| 1349 | /* | 1349 | /* |
| 1350 | * XXX | 1350 | * XXX |
| 1351 | * Spec says to write FLAG_CF as last config action, priv code grabs | 1351 | * Spec says to write FLAG_CF as last config action, priv code grabs |
| 1352 | * the semaphore while doing so. | 1352 | * the semaphore while doing so. |
| 1353 | */ | 1353 | */ |
| 1354 | down_write(&ehci_cf_port_reset_rwsem); | 1354 | down_write(&ehci_cf_port_reset_rwsem); |
| 1355 | reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); | 1355 | reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); |
| 1356 | 1356 | ||
| 1357 | retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); | 1357 | retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); |
| 1358 | up_write(&ehci_cf_port_reset_rwsem); | 1358 | up_write(&ehci_cf_port_reset_rwsem); |
| 1359 | if (retval) | 1359 | if (retval) |
| 1360 | return retval; | 1360 | return retval; |
| 1361 | 1361 | ||
| 1362 | init_timer(&errata2_timer); | 1362 | init_timer(&errata2_timer); |
| 1363 | errata2_timer.function = errata2_function; | 1363 | errata2_timer.function = errata2_function; |
| 1364 | errata2_timer.data = (unsigned long) hcd; | 1364 | errata2_timer.data = (unsigned long) hcd; |
| 1365 | errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; | 1365 | errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; |
| 1366 | add_timer(&errata2_timer); | 1366 | add_timer(&errata2_timer); |
| 1367 | 1367 | ||
| 1368 | chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); | 1368 | chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
| 1369 | dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", | 1369 | dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", |
| 1370 | chipid & 0xffff, chipid >> 16); | 1370 | chipid & 0xffff, chipid >> 16); |
| 1371 | 1371 | ||
| 1372 | /* PTD Register Init Part 2, Step 28 */ | 1372 | /* PTD Register Init Part 2, Step 28 */ |
| 1373 | 1373 | ||
| 1374 | /* Setup registers controlling PTD checking */ | 1374 | /* Setup registers controlling PTD checking */ |
| 1375 | reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); | 1375 | reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); |
| 1376 | reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); | 1376 | reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); |
| 1377 | reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); | 1377 | reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); |
| 1378 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); | 1378 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); |
| 1379 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); | 1379 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); |
| 1380 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); | 1380 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); |
| 1381 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, | 1381 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, |
| 1382 | ATL_BUF_FILL | INT_BUF_FILL); | 1382 | ATL_BUF_FILL | INT_BUF_FILL); |
| 1383 | 1383 | ||
| 1384 | /* GRR this is run-once init(), being done every time the HC starts. | 1384 | /* GRR this is run-once init(), being done every time the HC starts. |
| 1385 | * So long as they're part of class devices, we can't do it init() | 1385 | * So long as they're part of class devices, we can't do it init() |
| 1386 | * since the class device isn't created that early. | 1386 | * since the class device isn't created that early. |
| 1387 | */ | 1387 | */ |
| 1388 | return 0; | 1388 | return 0; |
| 1389 | } | 1389 | } |
| 1390 | 1390 | ||
| 1391 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) | 1391 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
| 1392 | { | 1392 | { |
| 1393 | qtd->data_buffer = databuffer; | 1393 | qtd->data_buffer = databuffer; |
| 1394 | 1394 | ||
| 1395 | if (len > MAX_PAYLOAD_SIZE) | 1395 | if (len > MAX_PAYLOAD_SIZE) |
| 1396 | len = MAX_PAYLOAD_SIZE; | 1396 | len = MAX_PAYLOAD_SIZE; |
| 1397 | qtd->length = len; | 1397 | qtd->length = len; |
| 1398 | 1398 | ||
| 1399 | return qtd->length; | 1399 | return qtd->length; |
| 1400 | } | 1400 | } |
| 1401 | 1401 | ||
| 1402 | static void qtd_list_free(struct list_head *qtd_list) | 1402 | static void qtd_list_free(struct list_head *qtd_list) |
| 1403 | { | 1403 | { |
| 1404 | struct isp1760_qtd *qtd, *qtd_next; | 1404 | struct isp1760_qtd *qtd, *qtd_next; |
| 1405 | 1405 | ||
| 1406 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { | 1406 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
| 1407 | list_del(&qtd->qtd_list); | 1407 | list_del(&qtd->qtd_list); |
| 1408 | qtd_free(qtd); | 1408 | qtd_free(qtd); |
| 1409 | } | 1409 | } |
| 1410 | } | 1410 | } |
| 1411 | 1411 | ||
| 1412 | /* | 1412 | /* |
| 1413 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. | 1413 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
| 1414 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. | 1414 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. |
| 1415 | */ | 1415 | */ |
| 1416 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | 1416 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
| 1417 | static void packetize_urb(struct usb_hcd *hcd, | 1417 | static void packetize_urb(struct usb_hcd *hcd, |
| 1418 | struct urb *urb, struct list_head *head, gfp_t flags) | 1418 | struct urb *urb, struct list_head *head, gfp_t flags) |
| 1419 | { | 1419 | { |
| 1420 | struct isp1760_qtd *qtd; | 1420 | struct isp1760_qtd *qtd; |
| 1421 | void *buf; | 1421 | void *buf; |
| 1422 | int len, maxpacketsize; | 1422 | int len, maxpacketsize; |
| 1423 | u8 packet_type; | 1423 | u8 packet_type; |
| 1424 | 1424 | ||
| 1425 | /* | 1425 | /* |
| 1426 | * URBs map to sequences of QTDs: one logical transaction | 1426 | * URBs map to sequences of QTDs: one logical transaction |
| 1427 | */ | 1427 | */ |
| 1428 | 1428 | ||
| 1429 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { | 1429 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
| 1430 | /* XXX This looks like usb storage / SCSI bug */ | 1430 | /* XXX This looks like usb storage / SCSI bug */ |
| 1431 | dev_err(hcd->self.controller, | 1431 | dev_err(hcd->self.controller, |
| 1432 | "buf is null, dma is %08lx len is %d\n", | 1432 | "buf is null, dma is %08lx len is %d\n", |
| 1433 | (long unsigned)urb->transfer_dma, | 1433 | (long unsigned)urb->transfer_dma, |
| 1434 | urb->transfer_buffer_length); | 1434 | urb->transfer_buffer_length); |
| 1435 | WARN_ON(1); | 1435 | WARN_ON(1); |
| 1436 | } | 1436 | } |
| 1437 | 1437 | ||
| 1438 | if (usb_pipein(urb->pipe)) | 1438 | if (usb_pipein(urb->pipe)) |
| 1439 | packet_type = IN_PID; | 1439 | packet_type = IN_PID; |
| 1440 | else | 1440 | else |
| 1441 | packet_type = OUT_PID; | 1441 | packet_type = OUT_PID; |
| 1442 | 1442 | ||
| 1443 | if (usb_pipecontrol(urb->pipe)) { | 1443 | if (usb_pipecontrol(urb->pipe)) { |
| 1444 | qtd = qtd_alloc(flags, urb, SETUP_PID); | 1444 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
| 1445 | if (!qtd) | 1445 | if (!qtd) |
| 1446 | goto cleanup; | 1446 | goto cleanup; |
| 1447 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); | 1447 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
| 1448 | list_add_tail(&qtd->qtd_list, head); | 1448 | list_add_tail(&qtd->qtd_list, head); |
| 1449 | 1449 | ||
| 1450 | /* for zero length DATA stages, STATUS is always IN */ | 1450 | /* for zero length DATA stages, STATUS is always IN */ |
| 1451 | if (urb->transfer_buffer_length == 0) | 1451 | if (urb->transfer_buffer_length == 0) |
| 1452 | packet_type = IN_PID; | 1452 | packet_type = IN_PID; |
| 1453 | } | 1453 | } |
| 1454 | 1454 | ||
| 1455 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, | 1455 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, |
| 1456 | usb_pipeout(urb->pipe))); | 1456 | usb_pipeout(urb->pipe))); |
| 1457 | 1457 | ||
| 1458 | /* | 1458 | /* |
| 1459 | * buffer gets wrapped in one or more qtds; | 1459 | * buffer gets wrapped in one or more qtds; |
| 1460 | * last one may be "short" (including zero len) | 1460 | * last one may be "short" (including zero len) |
| 1461 | * and may serve as a control status ack | 1461 | * and may serve as a control status ack |
| 1462 | */ | 1462 | */ |
| 1463 | buf = urb->transfer_buffer; | 1463 | buf = urb->transfer_buffer; |
| 1464 | len = urb->transfer_buffer_length; | 1464 | len = urb->transfer_buffer_length; |
| 1465 | 1465 | ||
| 1466 | for (;;) { | 1466 | for (;;) { |
| 1467 | int this_qtd_len; | 1467 | int this_qtd_len; |
| 1468 | 1468 | ||
| 1469 | qtd = qtd_alloc(flags, urb, packet_type); | 1469 | qtd = qtd_alloc(flags, urb, packet_type); |
| 1470 | if (!qtd) | 1470 | if (!qtd) |
| 1471 | goto cleanup; | 1471 | goto cleanup; |
| 1472 | this_qtd_len = qtd_fill(qtd, buf, len); | 1472 | this_qtd_len = qtd_fill(qtd, buf, len); |
| 1473 | list_add_tail(&qtd->qtd_list, head); | 1473 | list_add_tail(&qtd->qtd_list, head); |
| 1474 | 1474 | ||
| 1475 | len -= this_qtd_len; | 1475 | len -= this_qtd_len; |
| 1476 | buf += this_qtd_len; | 1476 | buf += this_qtd_len; |
| 1477 | 1477 | ||
| 1478 | if (len <= 0) | 1478 | if (len <= 0) |
| 1479 | break; | 1479 | break; |
| 1480 | } | 1480 | } |
| 1481 | 1481 | ||
| 1482 | /* | 1482 | /* |
| 1483 | * control requests may need a terminating data "status" ack; | 1483 | * control requests may need a terminating data "status" ack; |
| 1484 | * bulk ones may need a terminating short packet (zero length). | 1484 | * bulk ones may need a terminating short packet (zero length). |
| 1485 | */ | 1485 | */ |
| 1486 | if (urb->transfer_buffer_length != 0) { | 1486 | if (urb->transfer_buffer_length != 0) { |
| 1487 | int one_more = 0; | 1487 | int one_more = 0; |
| 1488 | 1488 | ||
| 1489 | if (usb_pipecontrol(urb->pipe)) { | 1489 | if (usb_pipecontrol(urb->pipe)) { |
| 1490 | one_more = 1; | 1490 | one_more = 1; |
| 1491 | if (packet_type == IN_PID) | 1491 | if (packet_type == IN_PID) |
| 1492 | packet_type = OUT_PID; | 1492 | packet_type = OUT_PID; |
| 1493 | else | 1493 | else |
| 1494 | packet_type = IN_PID; | 1494 | packet_type = IN_PID; |
| 1495 | } else if (usb_pipebulk(urb->pipe) | 1495 | } else if (usb_pipebulk(urb->pipe) |
| 1496 | && (urb->transfer_flags & URB_ZERO_PACKET) | 1496 | && (urb->transfer_flags & URB_ZERO_PACKET) |
| 1497 | && !(urb->transfer_buffer_length % | 1497 | && !(urb->transfer_buffer_length % |
| 1498 | maxpacketsize)) { | 1498 | maxpacketsize)) { |
| 1499 | one_more = 1; | 1499 | one_more = 1; |
| 1500 | } | 1500 | } |
| 1501 | if (one_more) { | 1501 | if (one_more) { |
| 1502 | qtd = qtd_alloc(flags, urb, packet_type); | 1502 | qtd = qtd_alloc(flags, urb, packet_type); |
| 1503 | if (!qtd) | 1503 | if (!qtd) |
| 1504 | goto cleanup; | 1504 | goto cleanup; |
| 1505 | 1505 | ||
| 1506 | /* never any data in such packets */ | 1506 | /* never any data in such packets */ |
| 1507 | qtd_fill(qtd, NULL, 0); | 1507 | qtd_fill(qtd, NULL, 0); |
| 1508 | list_add_tail(&qtd->qtd_list, head); | 1508 | list_add_tail(&qtd->qtd_list, head); |
| 1509 | } | 1509 | } |
| 1510 | } | 1510 | } |
| 1511 | 1511 | ||
| 1512 | return; | 1512 | return; |
| 1513 | 1513 | ||
| 1514 | cleanup: | 1514 | cleanup: |
| 1515 | qtd_list_free(head); | 1515 | qtd_list_free(head); |
| 1516 | } | 1516 | } |
| 1517 | 1517 | ||
| 1518 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | 1518 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
| 1519 | gfp_t mem_flags) | 1519 | gfp_t mem_flags) |
| 1520 | { | 1520 | { |
| 1521 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1521 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1522 | struct list_head *ep_queue; | 1522 | struct list_head *ep_queue; |
| 1523 | struct isp1760_qh *qh, *qhit; | 1523 | struct isp1760_qh *qh, *qhit; |
| 1524 | unsigned long spinflags; | 1524 | unsigned long spinflags; |
| 1525 | LIST_HEAD(new_qtds); | 1525 | LIST_HEAD(new_qtds); |
| 1526 | int retval; | 1526 | int retval; |
| 1527 | int qh_in_queue; | 1527 | int qh_in_queue; |
| 1528 | 1528 | ||
| 1529 | switch (usb_pipetype(urb->pipe)) { | 1529 | switch (usb_pipetype(urb->pipe)) { |
| 1530 | case PIPE_CONTROL: | 1530 | case PIPE_CONTROL: |
| 1531 | ep_queue = &priv->qh_list[QH_CONTROL]; | 1531 | ep_queue = &priv->qh_list[QH_CONTROL]; |
| 1532 | break; | 1532 | break; |
| 1533 | case PIPE_BULK: | 1533 | case PIPE_BULK: |
| 1534 | ep_queue = &priv->qh_list[QH_BULK]; | 1534 | ep_queue = &priv->qh_list[QH_BULK]; |
| 1535 | break; | 1535 | break; |
| 1536 | case PIPE_INTERRUPT: | 1536 | case PIPE_INTERRUPT: |
| 1537 | if (urb->interval < 0) | 1537 | if (urb->interval < 0) |
| 1538 | return -EINVAL; | 1538 | return -EINVAL; |
| 1539 | /* FIXME: Check bandwidth */ | 1539 | /* FIXME: Check bandwidth */ |
| 1540 | ep_queue = &priv->qh_list[QH_INTERRUPT]; | 1540 | ep_queue = &priv->qh_list[QH_INTERRUPT]; |
| 1541 | break; | 1541 | break; |
| 1542 | case PIPE_ISOCHRONOUS: | 1542 | case PIPE_ISOCHRONOUS: |
| 1543 | dev_err(hcd->self.controller, "%s: isochronous USB packets " | 1543 | dev_err(hcd->self.controller, "%s: isochronous USB packets " |
| 1544 | "not yet supported\n", | 1544 | "not yet supported\n", |
| 1545 | __func__); | 1545 | __func__); |
| 1546 | return -EPIPE; | 1546 | return -EPIPE; |
| 1547 | default: | 1547 | default: |
| 1548 | dev_err(hcd->self.controller, "%s: unknown pipe type\n", | 1548 | dev_err(hcd->self.controller, "%s: unknown pipe type\n", |
| 1549 | __func__); | 1549 | __func__); |
| 1550 | return -EPIPE; | 1550 | return -EPIPE; |
| 1551 | } | 1551 | } |
| 1552 | 1552 | ||
| 1553 | if (usb_pipein(urb->pipe)) | 1553 | if (usb_pipein(urb->pipe)) |
| 1554 | urb->actual_length = 0; | 1554 | urb->actual_length = 0; |
| 1555 | 1555 | ||
| 1556 | packetize_urb(hcd, urb, &new_qtds, mem_flags); | 1556 | packetize_urb(hcd, urb, &new_qtds, mem_flags); |
| 1557 | if (list_empty(&new_qtds)) | 1557 | if (list_empty(&new_qtds)) |
| 1558 | return -ENOMEM; | 1558 | return -ENOMEM; |
| 1559 | 1559 | ||
| 1560 | retval = 0; | 1560 | retval = 0; |
| 1561 | spin_lock_irqsave(&priv->lock, spinflags); | 1561 | spin_lock_irqsave(&priv->lock, spinflags); |
| 1562 | 1562 | ||
| 1563 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { | 1563 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
| 1564 | retval = -ESHUTDOWN; | 1564 | retval = -ESHUTDOWN; |
| 1565 | qtd_list_free(&new_qtds); | 1565 | qtd_list_free(&new_qtds); |
| 1566 | goto out; | 1566 | goto out; |
| 1567 | } | 1567 | } |
| 1568 | retval = usb_hcd_link_urb_to_ep(hcd, urb); | 1568 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
| 1569 | if (retval) { | 1569 | if (retval) { |
| 1570 | qtd_list_free(&new_qtds); | 1570 | qtd_list_free(&new_qtds); |
| 1571 | goto out; | 1571 | goto out; |
| 1572 | } | 1572 | } |
| 1573 | 1573 | ||
| 1574 | qh = urb->ep->hcpriv; | 1574 | qh = urb->ep->hcpriv; |
| 1575 | if (qh) { | 1575 | if (qh) { |
| 1576 | qh_in_queue = 0; | 1576 | qh_in_queue = 0; |
| 1577 | list_for_each_entry(qhit, ep_queue, qh_list) { | 1577 | list_for_each_entry(qhit, ep_queue, qh_list) { |
| 1578 | if (qhit == qh) { | 1578 | if (qhit == qh) { |
| 1579 | qh_in_queue = 1; | 1579 | qh_in_queue = 1; |
| 1580 | break; | 1580 | break; |
| 1581 | } | 1581 | } |
| 1582 | } | 1582 | } |
| 1583 | if (!qh_in_queue) | 1583 | if (!qh_in_queue) |
| 1584 | list_add_tail(&qh->qh_list, ep_queue); | 1584 | list_add_tail(&qh->qh_list, ep_queue); |
| 1585 | } else { | 1585 | } else { |
| 1586 | qh = qh_alloc(GFP_ATOMIC); | 1586 | qh = qh_alloc(GFP_ATOMIC); |
| 1587 | if (!qh) { | 1587 | if (!qh) { |
| 1588 | retval = -ENOMEM; | 1588 | retval = -ENOMEM; |
| 1589 | usb_hcd_unlink_urb_from_ep(hcd, urb); | 1589 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 1590 | qtd_list_free(&new_qtds); | 1590 | qtd_list_free(&new_qtds); |
| 1591 | goto out; | 1591 | goto out; |
| 1592 | } | 1592 | } |
| 1593 | list_add_tail(&qh->qh_list, ep_queue); | 1593 | list_add_tail(&qh->qh_list, ep_queue); |
| 1594 | urb->ep->hcpriv = qh; | 1594 | urb->ep->hcpriv = qh; |
| 1595 | } | 1595 | } |
| 1596 | 1596 | ||
| 1597 | list_splice_tail(&new_qtds, &qh->qtd_list); | 1597 | list_splice_tail(&new_qtds, &qh->qtd_list); |
| 1598 | schedule_ptds(hcd); | 1598 | schedule_ptds(hcd); |
| 1599 | 1599 | ||
| 1600 | out: | 1600 | out: |
| 1601 | spin_unlock_irqrestore(&priv->lock, spinflags); | 1601 | spin_unlock_irqrestore(&priv->lock, spinflags); |
| 1602 | return retval; | 1602 | return retval; |
| 1603 | } | 1603 | } |
| 1604 | 1604 | ||
| 1605 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, | 1605 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, |
| 1606 | struct isp1760_qh *qh) | 1606 | struct isp1760_qh *qh) |
| 1607 | { | 1607 | { |
| 1608 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1608 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1609 | int skip_map; | 1609 | int skip_map; |
| 1610 | 1610 | ||
| 1611 | WARN_ON(qh->slot == -1); | 1611 | WARN_ON(qh->slot == -1); |
| 1612 | 1612 | ||
| 1613 | /* We need to forcefully reclaim the slot since some transfers never | 1613 | /* We need to forcefully reclaim the slot since some transfers never |
| 1614 | return, e.g. interrupt transfers and NAKed bulk transfers. */ | 1614 | return, e.g. interrupt transfers and NAKed bulk transfers. */ |
| 1615 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { | 1615 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { |
| 1616 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | 1616 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
| 1617 | skip_map |= (1 << qh->slot); | 1617 | skip_map |= (1 << qh->slot); |
| 1618 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | 1618 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); |
| 1619 | priv->atl_slots[qh->slot].qh = NULL; | 1619 | priv->atl_slots[qh->slot].qh = NULL; |
| 1620 | priv->atl_slots[qh->slot].qtd = NULL; | 1620 | priv->atl_slots[qh->slot].qtd = NULL; |
| 1621 | } else { | 1621 | } else { |
| 1622 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | 1622 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
| 1623 | skip_map |= (1 << qh->slot); | 1623 | skip_map |= (1 << qh->slot); |
| 1624 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); | 1624 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); |
| 1625 | priv->int_slots[qh->slot].qh = NULL; | 1625 | priv->int_slots[qh->slot].qh = NULL; |
| 1626 | priv->int_slots[qh->slot].qtd = NULL; | 1626 | priv->int_slots[qh->slot].qtd = NULL; |
| 1627 | } | 1627 | } |
| 1628 | 1628 | ||
| 1629 | qh->slot = -1; | 1629 | qh->slot = -1; |
| 1630 | } | 1630 | } |
| 1631 | 1631 | ||
| 1632 | /* | 1632 | /* |
| 1633 | * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing | 1633 | * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing |
| 1634 | * any active transfer belonging to the urb in the process. | 1634 | * any active transfer belonging to the urb in the process. |
| 1635 | */ | 1635 | */ |
| 1636 | static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, | 1636 | static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 1637 | struct isp1760_qtd *qtd) | 1637 | struct isp1760_qtd *qtd) |
| 1638 | { | 1638 | { |
| 1639 | struct urb *urb; | 1639 | struct urb *urb; |
| 1640 | int urb_was_running; | 1640 | int urb_was_running; |
| 1641 | 1641 | ||
| 1642 | urb = qtd->urb; | 1642 | urb = qtd->urb; |
| 1643 | urb_was_running = 0; | 1643 | urb_was_running = 0; |
| 1644 | list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { | 1644 | list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { |
| 1645 | if (qtd->urb != urb) | 1645 | if (qtd->urb != urb) |
| 1646 | break; | 1646 | break; |
| 1647 | 1647 | ||
| 1648 | if (qtd->status >= QTD_XFER_STARTED) | 1648 | if (qtd->status >= QTD_XFER_STARTED) |
| 1649 | urb_was_running = 1; | 1649 | urb_was_running = 1; |
| 1650 | if (last_qtd_of_urb(qtd, qh) && | 1650 | if (last_qtd_of_urb(qtd, qh) && |
| 1651 | (qtd->status >= QTD_XFER_COMPLETE)) | 1651 | (qtd->status >= QTD_XFER_COMPLETE)) |
| 1652 | urb_was_running = 0; | 1652 | urb_was_running = 0; |
| 1653 | 1653 | ||
| 1654 | if (qtd->status == QTD_XFER_STARTED) | 1654 | if (qtd->status == QTD_XFER_STARTED) |
| 1655 | kill_transfer(hcd, urb, qh); | 1655 | kill_transfer(hcd, urb, qh); |
| 1656 | qtd->status = QTD_RETIRE; | 1656 | qtd->status = QTD_RETIRE; |
| 1657 | } | 1657 | } |
| 1658 | 1658 | ||
| 1659 | if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { | 1659 | if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { |
| 1660 | qh->tt_buffer_dirty = 1; | 1660 | qh->tt_buffer_dirty = 1; |
| 1661 | if (usb_hub_clear_tt_buffer(urb)) | 1661 | if (usb_hub_clear_tt_buffer(urb)) |
| 1662 | /* Clear failed; let's hope things work anyway */ | 1662 | /* Clear failed; let's hope things work anyway */ |
| 1663 | qh->tt_buffer_dirty = 0; | 1663 | qh->tt_buffer_dirty = 0; |
| 1664 | } | 1664 | } |
| 1665 | } | 1665 | } |
| 1666 | 1666 | ||
| 1667 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, | 1667 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, |
| 1668 | int status) | 1668 | int status) |
| 1669 | { | 1669 | { |
| 1670 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1670 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1671 | unsigned long spinflags; | 1671 | unsigned long spinflags; |
| 1672 | struct isp1760_qh *qh; | 1672 | struct isp1760_qh *qh; |
| 1673 | struct isp1760_qtd *qtd; | 1673 | struct isp1760_qtd *qtd; |
| 1674 | int retval = 0; | 1674 | int retval = 0; |
| 1675 | 1675 | ||
| 1676 | spin_lock_irqsave(&priv->lock, spinflags); | 1676 | spin_lock_irqsave(&priv->lock, spinflags); |
| 1677 | retval = usb_hcd_check_unlink_urb(hcd, urb, status); | 1677 | retval = usb_hcd_check_unlink_urb(hcd, urb, status); |
| 1678 | if (retval) | 1678 | if (retval) |
| 1679 | goto out; | 1679 | goto out; |
| 1680 | 1680 | ||
| 1681 | qh = urb->ep->hcpriv; | 1681 | qh = urb->ep->hcpriv; |
| 1682 | if (!qh) { | 1682 | if (!qh) { |
| 1683 | retval = -EINVAL; | 1683 | retval = -EINVAL; |
| 1684 | goto out; | 1684 | goto out; |
| 1685 | } | 1685 | } |
| 1686 | 1686 | ||
| 1687 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) | 1687 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
| 1688 | if (qtd->urb == urb) { | 1688 | if (qtd->urb == urb) { |
| 1689 | dequeue_urb_from_qtd(hcd, qh, qtd); | 1689 | dequeue_urb_from_qtd(hcd, qh, qtd); |
| 1690 | list_move(&qtd->qtd_list, &qh->qtd_list); | 1690 | list_move(&qtd->qtd_list, &qh->qtd_list); |
| 1691 | break; | 1691 | break; |
| 1692 | } | 1692 | } |
| 1693 | 1693 | ||
| 1694 | urb->status = status; | 1694 | urb->status = status; |
| 1695 | schedule_ptds(hcd); | 1695 | schedule_ptds(hcd); |
| 1696 | 1696 | ||
| 1697 | out: | 1697 | out: |
| 1698 | spin_unlock_irqrestore(&priv->lock, spinflags); | 1698 | spin_unlock_irqrestore(&priv->lock, spinflags); |
| 1699 | return retval; | 1699 | return retval; |
| 1700 | } | 1700 | } |
| 1701 | 1701 | ||
| 1702 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, | 1702 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
| 1703 | struct usb_host_endpoint *ep) | 1703 | struct usb_host_endpoint *ep) |
| 1704 | { | 1704 | { |
| 1705 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1705 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1706 | unsigned long spinflags; | 1706 | unsigned long spinflags; |
| 1707 | struct isp1760_qh *qh, *qh_iter; | 1707 | struct isp1760_qh *qh, *qh_iter; |
| 1708 | int i; | 1708 | int i; |
| 1709 | 1709 | ||
| 1710 | spin_lock_irqsave(&priv->lock, spinflags); | 1710 | spin_lock_irqsave(&priv->lock, spinflags); |
| 1711 | 1711 | ||
| 1712 | qh = ep->hcpriv; | 1712 | qh = ep->hcpriv; |
| 1713 | if (!qh) | 1713 | if (!qh) |
| 1714 | goto out; | 1714 | goto out; |
| 1715 | 1715 | ||
| 1716 | WARN_ON(!list_empty(&qh->qtd_list)); | 1716 | WARN_ON(!list_empty(&qh->qtd_list)); |
| 1717 | 1717 | ||
| 1718 | for (i = 0; i < QH_END; i++) | 1718 | for (i = 0; i < QH_END; i++) |
| 1719 | list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) | 1719 | list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) |
| 1720 | if (qh_iter == qh) { | 1720 | if (qh_iter == qh) { |
| 1721 | list_del(&qh_iter->qh_list); | 1721 | list_del(&qh_iter->qh_list); |
| 1722 | i = QH_END; | 1722 | i = QH_END; |
| 1723 | break; | 1723 | break; |
| 1724 | } | 1724 | } |
| 1725 | qh_free(qh); | 1725 | qh_free(qh); |
| 1726 | ep->hcpriv = NULL; | 1726 | ep->hcpriv = NULL; |
| 1727 | 1727 | ||
| 1728 | schedule_ptds(hcd); | 1728 | schedule_ptds(hcd); |
| 1729 | 1729 | ||
| 1730 | out: | 1730 | out: |
| 1731 | spin_unlock_irqrestore(&priv->lock, spinflags); | 1731 | spin_unlock_irqrestore(&priv->lock, spinflags); |
| 1732 | } | 1732 | } |
| 1733 | 1733 | ||
| 1734 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | 1734 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) |
| 1735 | { | 1735 | { |
| 1736 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1736 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1737 | u32 temp, status = 0; | 1737 | u32 temp, status = 0; |
| 1738 | u32 mask; | 1738 | u32 mask; |
| 1739 | int retval = 1; | 1739 | int retval = 1; |
| 1740 | unsigned long flags; | 1740 | unsigned long flags; |
| 1741 | 1741 | ||
| 1742 | /* if !PM_RUNTIME, root hub timers won't get shut down ... */ | 1742 | /* if !PM, root hub timers won't get shut down ... */ |
| 1743 | if (!HC_IS_RUNNING(hcd->state)) | 1743 | if (!HC_IS_RUNNING(hcd->state)) |
| 1744 | return 0; | 1744 | return 0; |
| 1745 | 1745 | ||
| 1746 | /* init status to no-changes */ | 1746 | /* init status to no-changes */ |
| 1747 | buf[0] = 0; | 1747 | buf[0] = 0; |
| 1748 | mask = PORT_CSC; | 1748 | mask = PORT_CSC; |
| 1749 | 1749 | ||
| 1750 | spin_lock_irqsave(&priv->lock, flags); | 1750 | spin_lock_irqsave(&priv->lock, flags); |
| 1751 | temp = reg_read32(hcd->regs, HC_PORTSC1); | 1751 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
| 1752 | 1752 | ||
| 1753 | if (temp & PORT_OWNER) { | 1753 | if (temp & PORT_OWNER) { |
| 1754 | if (temp & PORT_CSC) { | 1754 | if (temp & PORT_CSC) { |
| 1755 | temp &= ~PORT_CSC; | 1755 | temp &= ~PORT_CSC; |
| 1756 | reg_write32(hcd->regs, HC_PORTSC1, temp); | 1756 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
| 1757 | goto done; | 1757 | goto done; |
| 1758 | } | 1758 | } |
| 1759 | } | 1759 | } |
| 1760 | 1760 | ||
| 1761 | /* | 1761 | /* |
| 1762 | * Return status information even for ports with OWNER set. | 1762 | * Return status information even for ports with OWNER set. |
| 1763 | * Otherwise hub_wq wouldn't see the disconnect event when a | 1763 | * Otherwise hub_wq wouldn't see the disconnect event when a |
| 1764 | * high-speed device is switched over to the companion | 1764 | * high-speed device is switched over to the companion |
| 1765 | * controller by the user. | 1765 | * controller by the user. |
| 1766 | */ | 1766 | */ |
| 1767 | 1767 | ||
| 1768 | if ((temp & mask) != 0 | 1768 | if ((temp & mask) != 0 |
| 1769 | || ((temp & PORT_RESUME) != 0 | 1769 | || ((temp & PORT_RESUME) != 0 |
| 1770 | && time_after_eq(jiffies, | 1770 | && time_after_eq(jiffies, |
| 1771 | priv->reset_done))) { | 1771 | priv->reset_done))) { |
| 1772 | buf [0] |= 1 << (0 + 1); | 1772 | buf [0] |= 1 << (0 + 1); |
| 1773 | status = STS_PCD; | 1773 | status = STS_PCD; |
| 1774 | } | 1774 | } |
| 1775 | /* FIXME autosuspend idle root hubs */ | 1775 | /* FIXME autosuspend idle root hubs */ |
| 1776 | done: | 1776 | done: |
| 1777 | spin_unlock_irqrestore(&priv->lock, flags); | 1777 | spin_unlock_irqrestore(&priv->lock, flags); |
| 1778 | return status ? retval : 0; | 1778 | return status ? retval : 0; |
| 1779 | } | 1779 | } |
| 1780 | 1780 | ||
| 1781 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | 1781 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, |
| 1782 | struct usb_hub_descriptor *desc) | 1782 | struct usb_hub_descriptor *desc) |
| 1783 | { | 1783 | { |
| 1784 | int ports = HCS_N_PORTS(priv->hcs_params); | 1784 | int ports = HCS_N_PORTS(priv->hcs_params); |
| 1785 | u16 temp; | 1785 | u16 temp; |
| 1786 | 1786 | ||
| 1787 | desc->bDescriptorType = 0x29; | 1787 | desc->bDescriptorType = 0x29; |
| 1788 | /* priv 1.0, 2.3.9 says 20ms max */ | 1788 | /* priv 1.0, 2.3.9 says 20ms max */ |
| 1789 | desc->bPwrOn2PwrGood = 10; | 1789 | desc->bPwrOn2PwrGood = 10; |
| 1790 | desc->bHubContrCurrent = 0; | 1790 | desc->bHubContrCurrent = 0; |
| 1791 | 1791 | ||
| 1792 | desc->bNbrPorts = ports; | 1792 | desc->bNbrPorts = ports; |
| 1793 | temp = 1 + (ports / 8); | 1793 | temp = 1 + (ports / 8); |
| 1794 | desc->bDescLength = 7 + 2 * temp; | 1794 | desc->bDescLength = 7 + 2 * temp; |
| 1795 | 1795 | ||
| 1796 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 1796 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
| 1797 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); | 1797 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
| 1798 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); | 1798 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
| 1799 | 1799 | ||
| 1800 | /* per-port overcurrent reporting */ | 1800 | /* per-port overcurrent reporting */ |
| 1801 | temp = 0x0008; | 1801 | temp = 0x0008; |
| 1802 | if (HCS_PPC(priv->hcs_params)) | 1802 | if (HCS_PPC(priv->hcs_params)) |
| 1803 | /* per-port power control */ | 1803 | /* per-port power control */ |
| 1804 | temp |= 0x0001; | 1804 | temp |= 0x0001; |
| 1805 | else | 1805 | else |
| 1806 | /* no power switching */ | 1806 | /* no power switching */ |
| 1807 | temp |= 0x0002; | 1807 | temp |= 0x0002; |
| 1808 | desc->wHubCharacteristics = cpu_to_le16(temp); | 1808 | desc->wHubCharacteristics = cpu_to_le16(temp); |
| 1809 | } | 1809 | } |
| 1810 | 1810 | ||
| 1811 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | 1811 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
| 1812 | 1812 | ||
| 1813 | static int check_reset_complete(struct usb_hcd *hcd, int index, | 1813 | static int check_reset_complete(struct usb_hcd *hcd, int index, |
| 1814 | int port_status) | 1814 | int port_status) |
| 1815 | { | 1815 | { |
| 1816 | if (!(port_status & PORT_CONNECT)) | 1816 | if (!(port_status & PORT_CONNECT)) |
| 1817 | return port_status; | 1817 | return port_status; |
| 1818 | 1818 | ||
| 1819 | /* if reset finished and it's still not enabled -- handoff */ | 1819 | /* if reset finished and it's still not enabled -- handoff */ |
| 1820 | if (!(port_status & PORT_PE)) { | 1820 | if (!(port_status & PORT_PE)) { |
| 1821 | 1821 | ||
| 1822 | dev_info(hcd->self.controller, | 1822 | dev_info(hcd->self.controller, |
| 1823 | "port %d full speed --> companion\n", | 1823 | "port %d full speed --> companion\n", |
| 1824 | index + 1); | 1824 | index + 1); |
| 1825 | 1825 | ||
| 1826 | port_status |= PORT_OWNER; | 1826 | port_status |= PORT_OWNER; |
| 1827 | port_status &= ~PORT_RWC_BITS; | 1827 | port_status &= ~PORT_RWC_BITS; |
| 1828 | reg_write32(hcd->regs, HC_PORTSC1, port_status); | 1828 | reg_write32(hcd->regs, HC_PORTSC1, port_status); |
| 1829 | 1829 | ||
| 1830 | } else | 1830 | } else |
| 1831 | dev_info(hcd->self.controller, "port %d high speed\n", | 1831 | dev_info(hcd->self.controller, "port %d high speed\n", |
| 1832 | index + 1); | 1832 | index + 1); |
| 1833 | 1833 | ||
| 1834 | return port_status; | 1834 | return port_status; |
| 1835 | } | 1835 | } |
| 1836 | 1836 | ||
| 1837 | static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | 1837 | static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, |
| 1838 | u16 wValue, u16 wIndex, char *buf, u16 wLength) | 1838 | u16 wValue, u16 wIndex, char *buf, u16 wLength) |
| 1839 | { | 1839 | { |
| 1840 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1840 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1841 | int ports = HCS_N_PORTS(priv->hcs_params); | 1841 | int ports = HCS_N_PORTS(priv->hcs_params); |
| 1842 | u32 temp, status; | 1842 | u32 temp, status; |
| 1843 | unsigned long flags; | 1843 | unsigned long flags; |
| 1844 | int retval = 0; | 1844 | int retval = 0; |
| 1845 | unsigned selector; | 1845 | unsigned selector; |
| 1846 | 1846 | ||
| 1847 | /* | 1847 | /* |
| 1848 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. | 1848 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. |
| 1849 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. | 1849 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. |
| 1850 | * (track current state ourselves) ... blink for diagnostics, | 1850 | * (track current state ourselves) ... blink for diagnostics, |
| 1851 | * power, "this is the one", etc. EHCI spec supports this. | 1851 | * power, "this is the one", etc. EHCI spec supports this. |
| 1852 | */ | 1852 | */ |
| 1853 | 1853 | ||
| 1854 | spin_lock_irqsave(&priv->lock, flags); | 1854 | spin_lock_irqsave(&priv->lock, flags); |
| 1855 | switch (typeReq) { | 1855 | switch (typeReq) { |
| 1856 | case ClearHubFeature: | 1856 | case ClearHubFeature: |
| 1857 | switch (wValue) { | 1857 | switch (wValue) { |
| 1858 | case C_HUB_LOCAL_POWER: | 1858 | case C_HUB_LOCAL_POWER: |
| 1859 | case C_HUB_OVER_CURRENT: | 1859 | case C_HUB_OVER_CURRENT: |
| 1860 | /* no hub-wide feature/status flags */ | 1860 | /* no hub-wide feature/status flags */ |
| 1861 | break; | 1861 | break; |
| 1862 | default: | 1862 | default: |
| 1863 | goto error; | 1863 | goto error; |
| 1864 | } | 1864 | } |
| 1865 | break; | 1865 | break; |
| 1866 | case ClearPortFeature: | 1866 | case ClearPortFeature: |
| 1867 | if (!wIndex || wIndex > ports) | 1867 | if (!wIndex || wIndex > ports) |
| 1868 | goto error; | 1868 | goto error; |
| 1869 | wIndex--; | 1869 | wIndex--; |
| 1870 | temp = reg_read32(hcd->regs, HC_PORTSC1); | 1870 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
| 1871 | 1871 | ||
| 1872 | /* | 1872 | /* |
| 1873 | * Even if OWNER is set, so the port is owned by the | 1873 | * Even if OWNER is set, so the port is owned by the |
| 1874 | * companion controller, hub_wq needs to be able to clear | 1874 | * companion controller, hub_wq needs to be able to clear |
| 1875 | * the port-change status bits (especially | 1875 | * the port-change status bits (especially |
| 1876 | * USB_PORT_STAT_C_CONNECTION). | 1876 | * USB_PORT_STAT_C_CONNECTION). |
| 1877 | */ | 1877 | */ |
| 1878 | 1878 | ||
| 1879 | switch (wValue) { | 1879 | switch (wValue) { |
| 1880 | case USB_PORT_FEAT_ENABLE: | 1880 | case USB_PORT_FEAT_ENABLE: |
| 1881 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); | 1881 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); |
| 1882 | break; | 1882 | break; |
| 1883 | case USB_PORT_FEAT_C_ENABLE: | 1883 | case USB_PORT_FEAT_C_ENABLE: |
| 1884 | /* XXX error? */ | 1884 | /* XXX error? */ |
| 1885 | break; | 1885 | break; |
| 1886 | case USB_PORT_FEAT_SUSPEND: | 1886 | case USB_PORT_FEAT_SUSPEND: |
| 1887 | if (temp & PORT_RESET) | 1887 | if (temp & PORT_RESET) |
| 1888 | goto error; | 1888 | goto error; |
| 1889 | 1889 | ||
| 1890 | if (temp & PORT_SUSPEND) { | 1890 | if (temp & PORT_SUSPEND) { |
| 1891 | if ((temp & PORT_PE) == 0) | 1891 | if ((temp & PORT_PE) == 0) |
| 1892 | goto error; | 1892 | goto error; |
| 1893 | /* resume signaling for 20 msec */ | 1893 | /* resume signaling for 20 msec */ |
| 1894 | temp &= ~(PORT_RWC_BITS); | 1894 | temp &= ~(PORT_RWC_BITS); |
| 1895 | reg_write32(hcd->regs, HC_PORTSC1, | 1895 | reg_write32(hcd->regs, HC_PORTSC1, |
| 1896 | temp | PORT_RESUME); | 1896 | temp | PORT_RESUME); |
| 1897 | priv->reset_done = jiffies + | 1897 | priv->reset_done = jiffies + |
| 1898 | msecs_to_jiffies(20); | 1898 | msecs_to_jiffies(20); |
| 1899 | } | 1899 | } |
| 1900 | break; | 1900 | break; |
| 1901 | case USB_PORT_FEAT_C_SUSPEND: | 1901 | case USB_PORT_FEAT_C_SUSPEND: |
| 1902 | /* we auto-clear this feature */ | 1902 | /* we auto-clear this feature */ |
| 1903 | break; | 1903 | break; |
| 1904 | case USB_PORT_FEAT_POWER: | 1904 | case USB_PORT_FEAT_POWER: |
| 1905 | if (HCS_PPC(priv->hcs_params)) | 1905 | if (HCS_PPC(priv->hcs_params)) |
| 1906 | reg_write32(hcd->regs, HC_PORTSC1, | 1906 | reg_write32(hcd->regs, HC_PORTSC1, |
| 1907 | temp & ~PORT_POWER); | 1907 | temp & ~PORT_POWER); |
| 1908 | break; | 1908 | break; |
| 1909 | case USB_PORT_FEAT_C_CONNECTION: | 1909 | case USB_PORT_FEAT_C_CONNECTION: |
| 1910 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); | 1910 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); |
| 1911 | break; | 1911 | break; |
| 1912 | case USB_PORT_FEAT_C_OVER_CURRENT: | 1912 | case USB_PORT_FEAT_C_OVER_CURRENT: |
| 1913 | /* XXX error ?*/ | 1913 | /* XXX error ?*/ |
| 1914 | break; | 1914 | break; |
| 1915 | case USB_PORT_FEAT_C_RESET: | 1915 | case USB_PORT_FEAT_C_RESET: |
| 1916 | /* GetPortStatus clears reset */ | 1916 | /* GetPortStatus clears reset */ |
| 1917 | break; | 1917 | break; |
| 1918 | default: | 1918 | default: |
| 1919 | goto error; | 1919 | goto error; |
| 1920 | } | 1920 | } |
| 1921 | reg_read32(hcd->regs, HC_USBCMD); | 1921 | reg_read32(hcd->regs, HC_USBCMD); |
| 1922 | break; | 1922 | break; |
| 1923 | case GetHubDescriptor: | 1923 | case GetHubDescriptor: |
| 1924 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | 1924 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) |
| 1925 | buf); | 1925 | buf); |
| 1926 | break; | 1926 | break; |
| 1927 | case GetHubStatus: | 1927 | case GetHubStatus: |
| 1928 | /* no hub-wide feature/status flags */ | 1928 | /* no hub-wide feature/status flags */ |
| 1929 | memset(buf, 0, 4); | 1929 | memset(buf, 0, 4); |
| 1930 | break; | 1930 | break; |
| 1931 | case GetPortStatus: | 1931 | case GetPortStatus: |
| 1932 | if (!wIndex || wIndex > ports) | 1932 | if (!wIndex || wIndex > ports) |
| 1933 | goto error; | 1933 | goto error; |
| 1934 | wIndex--; | 1934 | wIndex--; |
| 1935 | status = 0; | 1935 | status = 0; |
| 1936 | temp = reg_read32(hcd->regs, HC_PORTSC1); | 1936 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
| 1937 | 1937 | ||
| 1938 | /* wPortChange bits */ | 1938 | /* wPortChange bits */ |
| 1939 | if (temp & PORT_CSC) | 1939 | if (temp & PORT_CSC) |
| 1940 | status |= USB_PORT_STAT_C_CONNECTION << 16; | 1940 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
| 1941 | 1941 | ||
| 1942 | 1942 | ||
| 1943 | /* whoever resumes must GetPortStatus to complete it!! */ | 1943 | /* whoever resumes must GetPortStatus to complete it!! */ |
| 1944 | if (temp & PORT_RESUME) { | 1944 | if (temp & PORT_RESUME) { |
| 1945 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); | 1945 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); |
| 1946 | 1946 | ||
| 1947 | /* Remote Wakeup received? */ | 1947 | /* Remote Wakeup received? */ |
| 1948 | if (!priv->reset_done) { | 1948 | if (!priv->reset_done) { |
| 1949 | /* resume signaling for 20 msec */ | 1949 | /* resume signaling for 20 msec */ |
| 1950 | priv->reset_done = jiffies | 1950 | priv->reset_done = jiffies |
| 1951 | + msecs_to_jiffies(20); | 1951 | + msecs_to_jiffies(20); |
| 1952 | /* check the port again */ | 1952 | /* check the port again */ |
| 1953 | mod_timer(&hcd->rh_timer, priv->reset_done); | 1953 | mod_timer(&hcd->rh_timer, priv->reset_done); |
| 1954 | } | 1954 | } |
| 1955 | 1955 | ||
| 1956 | /* resume completed? */ | 1956 | /* resume completed? */ |
| 1957 | else if (time_after_eq(jiffies, | 1957 | else if (time_after_eq(jiffies, |
| 1958 | priv->reset_done)) { | 1958 | priv->reset_done)) { |
| 1959 | status |= USB_PORT_STAT_C_SUSPEND << 16; | 1959 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
| 1960 | priv->reset_done = 0; | 1960 | priv->reset_done = 0; |
| 1961 | 1961 | ||
| 1962 | /* stop resume signaling */ | 1962 | /* stop resume signaling */ |
| 1963 | temp = reg_read32(hcd->regs, HC_PORTSC1); | 1963 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
| 1964 | reg_write32(hcd->regs, HC_PORTSC1, | 1964 | reg_write32(hcd->regs, HC_PORTSC1, |
| 1965 | temp & ~(PORT_RWC_BITS | PORT_RESUME)); | 1965 | temp & ~(PORT_RWC_BITS | PORT_RESUME)); |
| 1966 | retval = handshake(hcd, HC_PORTSC1, | 1966 | retval = handshake(hcd, HC_PORTSC1, |
| 1967 | PORT_RESUME, 0, 2000 /* 2msec */); | 1967 | PORT_RESUME, 0, 2000 /* 2msec */); |
| 1968 | if (retval != 0) { | 1968 | if (retval != 0) { |
| 1969 | dev_err(hcd->self.controller, | 1969 | dev_err(hcd->self.controller, |
| 1970 | "port %d resume error %d\n", | 1970 | "port %d resume error %d\n", |
| 1971 | wIndex + 1, retval); | 1971 | wIndex + 1, retval); |
| 1972 | goto error; | 1972 | goto error; |
| 1973 | } | 1973 | } |
| 1974 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); | 1974 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); |
| 1975 | } | 1975 | } |
| 1976 | } | 1976 | } |
| 1977 | 1977 | ||
| 1978 | /* whoever resets must GetPortStatus to complete it!! */ | 1978 | /* whoever resets must GetPortStatus to complete it!! */ |
| 1979 | if ((temp & PORT_RESET) | 1979 | if ((temp & PORT_RESET) |
| 1980 | && time_after_eq(jiffies, | 1980 | && time_after_eq(jiffies, |
| 1981 | priv->reset_done)) { | 1981 | priv->reset_done)) { |
| 1982 | status |= USB_PORT_STAT_C_RESET << 16; | 1982 | status |= USB_PORT_STAT_C_RESET << 16; |
| 1983 | priv->reset_done = 0; | 1983 | priv->reset_done = 0; |
| 1984 | 1984 | ||
| 1985 | /* force reset to complete */ | 1985 | /* force reset to complete */ |
| 1986 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); | 1986 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); |
| 1987 | /* REVISIT: some hardware needs 550+ usec to clear | 1987 | /* REVISIT: some hardware needs 550+ usec to clear |
| 1988 | * this bit; seems too long to spin routinely... | 1988 | * this bit; seems too long to spin routinely... |
| 1989 | */ | 1989 | */ |
| 1990 | retval = handshake(hcd, HC_PORTSC1, | 1990 | retval = handshake(hcd, HC_PORTSC1, |
| 1991 | PORT_RESET, 0, 750); | 1991 | PORT_RESET, 0, 750); |
| 1992 | if (retval != 0) { | 1992 | if (retval != 0) { |
| 1993 | dev_err(hcd->self.controller, "port %d reset error %d\n", | 1993 | dev_err(hcd->self.controller, "port %d reset error %d\n", |
| 1994 | wIndex + 1, retval); | 1994 | wIndex + 1, retval); |
| 1995 | goto error; | 1995 | goto error; |
| 1996 | } | 1996 | } |
| 1997 | 1997 | ||
| 1998 | /* see what we found out */ | 1998 | /* see what we found out */ |
| 1999 | temp = check_reset_complete(hcd, wIndex, | 1999 | temp = check_reset_complete(hcd, wIndex, |
| 2000 | reg_read32(hcd->regs, HC_PORTSC1)); | 2000 | reg_read32(hcd->regs, HC_PORTSC1)); |
| 2001 | } | 2001 | } |
| 2002 | /* | 2002 | /* |
| 2003 | * Even if OWNER is set, there's no harm letting hub_wq | 2003 | * Even if OWNER is set, there's no harm letting hub_wq |
| 2004 | * see the wPortStatus values (they should all be 0 except | 2004 | * see the wPortStatus values (they should all be 0 except |
| 2005 | * for PORT_POWER anyway). | 2005 | * for PORT_POWER anyway). |
| 2006 | */ | 2006 | */ |
| 2007 | 2007 | ||
| 2008 | if (temp & PORT_OWNER) | 2008 | if (temp & PORT_OWNER) |
| 2009 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); | 2009 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); |
| 2010 | 2010 | ||
| 2011 | if (temp & PORT_CONNECT) { | 2011 | if (temp & PORT_CONNECT) { |
| 2012 | status |= USB_PORT_STAT_CONNECTION; | 2012 | status |= USB_PORT_STAT_CONNECTION; |
| 2013 | /* status may be from integrated TT */ | 2013 | /* status may be from integrated TT */ |
| 2014 | status |= USB_PORT_STAT_HIGH_SPEED; | 2014 | status |= USB_PORT_STAT_HIGH_SPEED; |
| 2015 | } | 2015 | } |
| 2016 | if (temp & PORT_PE) | 2016 | if (temp & PORT_PE) |
| 2017 | status |= USB_PORT_STAT_ENABLE; | 2017 | status |= USB_PORT_STAT_ENABLE; |
| 2018 | if (temp & (PORT_SUSPEND|PORT_RESUME)) | 2018 | if (temp & (PORT_SUSPEND|PORT_RESUME)) |
| 2019 | status |= USB_PORT_STAT_SUSPEND; | 2019 | status |= USB_PORT_STAT_SUSPEND; |
| 2020 | if (temp & PORT_RESET) | 2020 | if (temp & PORT_RESET) |
| 2021 | status |= USB_PORT_STAT_RESET; | 2021 | status |= USB_PORT_STAT_RESET; |
| 2022 | if (temp & PORT_POWER) | 2022 | if (temp & PORT_POWER) |
| 2023 | status |= USB_PORT_STAT_POWER; | 2023 | status |= USB_PORT_STAT_POWER; |
| 2024 | 2024 | ||
| 2025 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | 2025 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
| 2026 | break; | 2026 | break; |
| 2027 | case SetHubFeature: | 2027 | case SetHubFeature: |
| 2028 | switch (wValue) { | 2028 | switch (wValue) { |
| 2029 | case C_HUB_LOCAL_POWER: | 2029 | case C_HUB_LOCAL_POWER: |
| 2030 | case C_HUB_OVER_CURRENT: | 2030 | case C_HUB_OVER_CURRENT: |
| 2031 | /* no hub-wide feature/status flags */ | 2031 | /* no hub-wide feature/status flags */ |
| 2032 | break; | 2032 | break; |
| 2033 | default: | 2033 | default: |
| 2034 | goto error; | 2034 | goto error; |
| 2035 | } | 2035 | } |
| 2036 | break; | 2036 | break; |
| 2037 | case SetPortFeature: | 2037 | case SetPortFeature: |
| 2038 | selector = wIndex >> 8; | 2038 | selector = wIndex >> 8; |
| 2039 | wIndex &= 0xff; | 2039 | wIndex &= 0xff; |
| 2040 | if (!wIndex || wIndex > ports) | 2040 | if (!wIndex || wIndex > ports) |
| 2041 | goto error; | 2041 | goto error; |
| 2042 | wIndex--; | 2042 | wIndex--; |
| 2043 | temp = reg_read32(hcd->regs, HC_PORTSC1); | 2043 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
| 2044 | if (temp & PORT_OWNER) | 2044 | if (temp & PORT_OWNER) |
| 2045 | break; | 2045 | break; |
| 2046 | 2046 | ||
| 2047 | /* temp &= ~PORT_RWC_BITS; */ | 2047 | /* temp &= ~PORT_RWC_BITS; */ |
| 2048 | switch (wValue) { | 2048 | switch (wValue) { |
| 2049 | case USB_PORT_FEAT_ENABLE: | 2049 | case USB_PORT_FEAT_ENABLE: |
| 2050 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); | 2050 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); |
| 2051 | break; | 2051 | break; |
| 2052 | 2052 | ||
| 2053 | case USB_PORT_FEAT_SUSPEND: | 2053 | case USB_PORT_FEAT_SUSPEND: |
| 2054 | if ((temp & PORT_PE) == 0 | 2054 | if ((temp & PORT_PE) == 0 |
| 2055 | || (temp & PORT_RESET) != 0) | 2055 | || (temp & PORT_RESET) != 0) |
| 2056 | goto error; | 2056 | goto error; |
| 2057 | 2057 | ||
| 2058 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); | 2058 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); |
| 2059 | break; | 2059 | break; |
| 2060 | case USB_PORT_FEAT_POWER: | 2060 | case USB_PORT_FEAT_POWER: |
| 2061 | if (HCS_PPC(priv->hcs_params)) | 2061 | if (HCS_PPC(priv->hcs_params)) |
| 2062 | reg_write32(hcd->regs, HC_PORTSC1, | 2062 | reg_write32(hcd->regs, HC_PORTSC1, |
| 2063 | temp | PORT_POWER); | 2063 | temp | PORT_POWER); |
| 2064 | break; | 2064 | break; |
| 2065 | case USB_PORT_FEAT_RESET: | 2065 | case USB_PORT_FEAT_RESET: |
| 2066 | if (temp & PORT_RESUME) | 2066 | if (temp & PORT_RESUME) |
| 2067 | goto error; | 2067 | goto error; |
| 2068 | /* line status bits may report this as low speed, | 2068 | /* line status bits may report this as low speed, |
| 2069 | * which can be fine if this root hub has a | 2069 | * which can be fine if this root hub has a |
| 2070 | * transaction translator built in. | 2070 | * transaction translator built in. |
| 2071 | */ | 2071 | */ |
| 2072 | if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT | 2072 | if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT |
| 2073 | && PORT_USB11(temp)) { | 2073 | && PORT_USB11(temp)) { |
| 2074 | temp |= PORT_OWNER; | 2074 | temp |= PORT_OWNER; |
| 2075 | } else { | 2075 | } else { |
| 2076 | temp |= PORT_RESET; | 2076 | temp |= PORT_RESET; |
| 2077 | temp &= ~PORT_PE; | 2077 | temp &= ~PORT_PE; |
| 2078 | 2078 | ||
| 2079 | /* | 2079 | /* |
| 2080 | * caller must wait, then call GetPortStatus | 2080 | * caller must wait, then call GetPortStatus |
| 2081 | * usb 2.0 spec says 50 ms resets on root | 2081 | * usb 2.0 spec says 50 ms resets on root |
| 2082 | */ | 2082 | */ |
| 2083 | priv->reset_done = jiffies + | 2083 | priv->reset_done = jiffies + |
| 2084 | msecs_to_jiffies(50); | 2084 | msecs_to_jiffies(50); |
| 2085 | } | 2085 | } |
| 2086 | reg_write32(hcd->regs, HC_PORTSC1, temp); | 2086 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
| 2087 | break; | 2087 | break; |
| 2088 | default: | 2088 | default: |
| 2089 | goto error; | 2089 | goto error; |
| 2090 | } | 2090 | } |
| 2091 | reg_read32(hcd->regs, HC_USBCMD); | 2091 | reg_read32(hcd->regs, HC_USBCMD); |
| 2092 | break; | 2092 | break; |
| 2093 | 2093 | ||
| 2094 | default: | 2094 | default: |
| 2095 | error: | 2095 | error: |
| 2096 | /* "stall" on error */ | 2096 | /* "stall" on error */ |
| 2097 | retval = -EPIPE; | 2097 | retval = -EPIPE; |
| 2098 | } | 2098 | } |
| 2099 | spin_unlock_irqrestore(&priv->lock, flags); | 2099 | spin_unlock_irqrestore(&priv->lock, flags); |
| 2100 | return retval; | 2100 | return retval; |
| 2101 | } | 2101 | } |
| 2102 | 2102 | ||
| 2103 | static int isp1760_get_frame(struct usb_hcd *hcd) | 2103 | static int isp1760_get_frame(struct usb_hcd *hcd) |
| 2104 | { | 2104 | { |
| 2105 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 2105 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2106 | u32 fr; | 2106 | u32 fr; |
| 2107 | 2107 | ||
| 2108 | fr = reg_read32(hcd->regs, HC_FRINDEX); | 2108 | fr = reg_read32(hcd->regs, HC_FRINDEX); |
| 2109 | return (fr >> 3) % priv->periodic_size; | 2109 | return (fr >> 3) % priv->periodic_size; |
| 2110 | } | 2110 | } |
| 2111 | 2111 | ||
| 2112 | static void isp1760_stop(struct usb_hcd *hcd) | 2112 | static void isp1760_stop(struct usb_hcd *hcd) |
| 2113 | { | 2113 | { |
| 2114 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 2114 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2115 | u32 temp; | 2115 | u32 temp; |
| 2116 | 2116 | ||
| 2117 | del_timer(&errata2_timer); | 2117 | del_timer(&errata2_timer); |
| 2118 | 2118 | ||
| 2119 | isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, | 2119 | isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, |
| 2120 | NULL, 0); | 2120 | NULL, 0); |
| 2121 | mdelay(20); | 2121 | mdelay(20); |
| 2122 | 2122 | ||
| 2123 | spin_lock_irq(&priv->lock); | 2123 | spin_lock_irq(&priv->lock); |
| 2124 | ehci_reset(hcd); | 2124 | ehci_reset(hcd); |
| 2125 | /* Disable IRQ */ | 2125 | /* Disable IRQ */ |
| 2126 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); | 2126 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
| 2127 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); | 2127 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); |
| 2128 | spin_unlock_irq(&priv->lock); | 2128 | spin_unlock_irq(&priv->lock); |
| 2129 | 2129 | ||
| 2130 | reg_write32(hcd->regs, HC_CONFIGFLAG, 0); | 2130 | reg_write32(hcd->regs, HC_CONFIGFLAG, 0); |
| 2131 | } | 2131 | } |
| 2132 | 2132 | ||
| 2133 | static void isp1760_shutdown(struct usb_hcd *hcd) | 2133 | static void isp1760_shutdown(struct usb_hcd *hcd) |
| 2134 | { | 2134 | { |
| 2135 | u32 command, temp; | 2135 | u32 command, temp; |
| 2136 | 2136 | ||
| 2137 | isp1760_stop(hcd); | 2137 | isp1760_stop(hcd); |
| 2138 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); | 2138 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
| 2139 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); | 2139 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); |
| 2140 | 2140 | ||
| 2141 | command = reg_read32(hcd->regs, HC_USBCMD); | 2141 | command = reg_read32(hcd->regs, HC_USBCMD); |
| 2142 | command &= ~CMD_RUN; | 2142 | command &= ~CMD_RUN; |
| 2143 | reg_write32(hcd->regs, HC_USBCMD, command); | 2143 | reg_write32(hcd->regs, HC_USBCMD, command); |
| 2144 | } | 2144 | } |
| 2145 | 2145 | ||
| 2146 | static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, | 2146 | static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, |
| 2147 | struct usb_host_endpoint *ep) | 2147 | struct usb_host_endpoint *ep) |
| 2148 | { | 2148 | { |
| 2149 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 2149 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2150 | struct isp1760_qh *qh = ep->hcpriv; | 2150 | struct isp1760_qh *qh = ep->hcpriv; |
| 2151 | unsigned long spinflags; | 2151 | unsigned long spinflags; |
| 2152 | 2152 | ||
| 2153 | if (!qh) | 2153 | if (!qh) |
| 2154 | return; | 2154 | return; |
| 2155 | 2155 | ||
| 2156 | spin_lock_irqsave(&priv->lock, spinflags); | 2156 | spin_lock_irqsave(&priv->lock, spinflags); |
| 2157 | qh->tt_buffer_dirty = 0; | 2157 | qh->tt_buffer_dirty = 0; |
| 2158 | schedule_ptds(hcd); | 2158 | schedule_ptds(hcd); |
| 2159 | spin_unlock_irqrestore(&priv->lock, spinflags); | 2159 | spin_unlock_irqrestore(&priv->lock, spinflags); |
| 2160 | } | 2160 | } |
| 2161 | 2161 | ||
| 2162 | 2162 | ||
| 2163 | static const struct hc_driver isp1760_hc_driver = { | 2163 | static const struct hc_driver isp1760_hc_driver = { |
| 2164 | .description = "isp1760-hcd", | 2164 | .description = "isp1760-hcd", |
| 2165 | .product_desc = "NXP ISP1760 USB Host Controller", | 2165 | .product_desc = "NXP ISP1760 USB Host Controller", |
| 2166 | .hcd_priv_size = sizeof(struct isp1760_hcd), | 2166 | .hcd_priv_size = sizeof(struct isp1760_hcd), |
| 2167 | .irq = isp1760_irq, | 2167 | .irq = isp1760_irq, |
| 2168 | .flags = HCD_MEMORY | HCD_USB2, | 2168 | .flags = HCD_MEMORY | HCD_USB2, |
| 2169 | .reset = isp1760_hc_setup, | 2169 | .reset = isp1760_hc_setup, |
| 2170 | .start = isp1760_run, | 2170 | .start = isp1760_run, |
| 2171 | .stop = isp1760_stop, | 2171 | .stop = isp1760_stop, |
| 2172 | .shutdown = isp1760_shutdown, | 2172 | .shutdown = isp1760_shutdown, |
| 2173 | .urb_enqueue = isp1760_urb_enqueue, | 2173 | .urb_enqueue = isp1760_urb_enqueue, |
| 2174 | .urb_dequeue = isp1760_urb_dequeue, | 2174 | .urb_dequeue = isp1760_urb_dequeue, |
| 2175 | .endpoint_disable = isp1760_endpoint_disable, | 2175 | .endpoint_disable = isp1760_endpoint_disable, |
| 2176 | .get_frame_number = isp1760_get_frame, | 2176 | .get_frame_number = isp1760_get_frame, |
| 2177 | .hub_status_data = isp1760_hub_status_data, | 2177 | .hub_status_data = isp1760_hub_status_data, |
| 2178 | .hub_control = isp1760_hub_control, | 2178 | .hub_control = isp1760_hub_control, |
| 2179 | .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, | 2179 | .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, |
| 2180 | }; | 2180 | }; |
| 2181 | 2181 | ||
| 2182 | int __init init_kmem_once(void) | 2182 | int __init init_kmem_once(void) |
| 2183 | { | 2183 | { |
| 2184 | urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", | 2184 | urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", |
| 2185 | sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | | 2185 | sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | |
| 2186 | SLAB_MEM_SPREAD, NULL); | 2186 | SLAB_MEM_SPREAD, NULL); |
| 2187 | 2187 | ||
| 2188 | if (!urb_listitem_cachep) | 2188 | if (!urb_listitem_cachep) |
| 2189 | return -ENOMEM; | 2189 | return -ENOMEM; |
| 2190 | 2190 | ||
| 2191 | qtd_cachep = kmem_cache_create("isp1760_qtd", | 2191 | qtd_cachep = kmem_cache_create("isp1760_qtd", |
| 2192 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | 2192 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | |
| 2193 | SLAB_MEM_SPREAD, NULL); | 2193 | SLAB_MEM_SPREAD, NULL); |
| 2194 | 2194 | ||
| 2195 | if (!qtd_cachep) | 2195 | if (!qtd_cachep) |
| 2196 | return -ENOMEM; | 2196 | return -ENOMEM; |
| 2197 | 2197 | ||
| 2198 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), | 2198 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), |
| 2199 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); | 2199 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); |
| 2200 | 2200 | ||
| 2201 | if (!qh_cachep) { | 2201 | if (!qh_cachep) { |
| 2202 | kmem_cache_destroy(qtd_cachep); | 2202 | kmem_cache_destroy(qtd_cachep); |
| 2203 | return -ENOMEM; | 2203 | return -ENOMEM; |
| 2204 | } | 2204 | } |
| 2205 | 2205 | ||
| 2206 | return 0; | 2206 | return 0; |
| 2207 | } | 2207 | } |
| 2208 | 2208 | ||
| 2209 | void deinit_kmem_cache(void) | 2209 | void deinit_kmem_cache(void) |
| 2210 | { | 2210 | { |
| 2211 | kmem_cache_destroy(qtd_cachep); | 2211 | kmem_cache_destroy(qtd_cachep); |
| 2212 | kmem_cache_destroy(qh_cachep); | 2212 | kmem_cache_destroy(qh_cachep); |
| 2213 | kmem_cache_destroy(urb_listitem_cachep); | 2213 | kmem_cache_destroy(urb_listitem_cachep); |
| 2214 | } | 2214 | } |
| 2215 | 2215 | ||
| 2216 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, | 2216 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, |
| 2217 | int irq, unsigned long irqflags, | 2217 | int irq, unsigned long irqflags, |
| 2218 | int rst_gpio, | 2218 | int rst_gpio, |
| 2219 | struct device *dev, const char *busname, | 2219 | struct device *dev, const char *busname, |
| 2220 | unsigned int devflags) | 2220 | unsigned int devflags) |
| 2221 | { | 2221 | { |
| 2222 | struct usb_hcd *hcd; | 2222 | struct usb_hcd *hcd; |
| 2223 | struct isp1760_hcd *priv; | 2223 | struct isp1760_hcd *priv; |
| 2224 | int ret; | 2224 | int ret; |
| 2225 | 2225 | ||
| 2226 | if (usb_disabled()) | 2226 | if (usb_disabled()) |
| 2227 | return ERR_PTR(-ENODEV); | 2227 | return ERR_PTR(-ENODEV); |
| 2228 | 2228 | ||
| 2229 | /* prevent usb-core allocating DMA pages */ | 2229 | /* prevent usb-core allocating DMA pages */ |
| 2230 | dev->dma_mask = NULL; | 2230 | dev->dma_mask = NULL; |
| 2231 | 2231 | ||
| 2232 | hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); | 2232 | hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); |
| 2233 | if (!hcd) | 2233 | if (!hcd) |
| 2234 | return ERR_PTR(-ENOMEM); | 2234 | return ERR_PTR(-ENOMEM); |
| 2235 | 2235 | ||
| 2236 | priv = hcd_to_priv(hcd); | 2236 | priv = hcd_to_priv(hcd); |
| 2237 | priv->devflags = devflags; | 2237 | priv->devflags = devflags; |
| 2238 | priv->rst_gpio = rst_gpio; | 2238 | priv->rst_gpio = rst_gpio; |
| 2239 | init_memory(priv); | 2239 | init_memory(priv); |
| 2240 | hcd->regs = ioremap(res_start, res_len); | 2240 | hcd->regs = ioremap(res_start, res_len); |
| 2241 | if (!hcd->regs) { | 2241 | if (!hcd->regs) { |
| 2242 | ret = -EIO; | 2242 | ret = -EIO; |
| 2243 | goto err_put; | 2243 | goto err_put; |
| 2244 | } | 2244 | } |
| 2245 | 2245 | ||
| 2246 | hcd->irq = irq; | 2246 | hcd->irq = irq; |
| 2247 | hcd->rsrc_start = res_start; | 2247 | hcd->rsrc_start = res_start; |
| 2248 | hcd->rsrc_len = res_len; | 2248 | hcd->rsrc_len = res_len; |
| 2249 | 2249 | ||
| 2250 | ret = usb_add_hcd(hcd, irq, irqflags); | 2250 | ret = usb_add_hcd(hcd, irq, irqflags); |
| 2251 | if (ret) | 2251 | if (ret) |
| 2252 | goto err_unmap; | 2252 | goto err_unmap; |
| 2253 | device_wakeup_enable(hcd->self.controller); | 2253 | device_wakeup_enable(hcd->self.controller); |
| 2254 | 2254 | ||
| 2255 | return hcd; | 2255 | return hcd; |
| 2256 | 2256 | ||
| 2257 | err_unmap: | 2257 | err_unmap: |
| 2258 | iounmap(hcd->regs); | 2258 | iounmap(hcd->regs); |
| 2259 | 2259 | ||
| 2260 | err_put: | 2260 | err_put: |
| 2261 | usb_put_hcd(hcd); | 2261 | usb_put_hcd(hcd); |
| 2262 | 2262 | ||
| 2263 | return ERR_PTR(ret); | 2263 | return ERR_PTR(ret); |
| 2264 | } | 2264 | } |
| 2265 | 2265 | ||
| 2266 | MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); | 2266 | MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); |
| 2267 | MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); | 2267 | MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); |
| 2268 | MODULE_LICENSE("GPL v2"); | 2268 | MODULE_LICENSE("GPL v2"); |
| 2269 | 2269 |
drivers/usb/host/oxu210hp-hcd.c
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it> | 2 | * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it> |
| 3 | * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it> | 3 | * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it> |
| 4 | * | 4 | * |
| 5 | * This code is *strongly* based on EHCI-HCD code by David Brownell since | 5 | * This code is *strongly* based on EHCI-HCD code by David Brownell since |
| 6 | * the chip is a quasi-EHCI compatible. | 6 | * the chip is a quasi-EHCI compatible. |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the | 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. | 11 | * option) any later version. |
| 12 | * | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but | 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. | 16 | * for more details. |
| 17 | * | 17 | * |
| 18 | * You should have received a copy of the GNU General Public License | 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, | 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ | 21 | */ |
| 22 | 22 | ||
| 23 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 24 | #include <linux/pci.h> | 24 | #include <linux/pci.h> |
| 25 | #include <linux/dmapool.h> | 25 | #include <linux/dmapool.h> |
| 26 | #include <linux/kernel.h> | 26 | #include <linux/kernel.h> |
| 27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 28 | #include <linux/ioport.h> | 28 | #include <linux/ioport.h> |
| 29 | #include <linux/sched.h> | 29 | #include <linux/sched.h> |
| 30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
| 31 | #include <linux/errno.h> | 31 | #include <linux/errno.h> |
| 32 | #include <linux/timer.h> | 32 | #include <linux/timer.h> |
| 33 | #include <linux/list.h> | 33 | #include <linux/list.h> |
| 34 | #include <linux/interrupt.h> | 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/usb.h> | 35 | #include <linux/usb.h> |
| 36 | #include <linux/usb/hcd.h> | 36 | #include <linux/usb/hcd.h> |
| 37 | #include <linux/moduleparam.h> | 37 | #include <linux/moduleparam.h> |
| 38 | #include <linux/dma-mapping.h> | 38 | #include <linux/dma-mapping.h> |
| 39 | #include <linux/io.h> | 39 | #include <linux/io.h> |
| 40 | 40 | ||
| 41 | #include <asm/irq.h> | 41 | #include <asm/irq.h> |
| 42 | #include <asm/unaligned.h> | 42 | #include <asm/unaligned.h> |
| 43 | 43 | ||
| 44 | #include <linux/irq.h> | 44 | #include <linux/irq.h> |
| 45 | #include <linux/platform_device.h> | 45 | #include <linux/platform_device.h> |
| 46 | 46 | ||
| 47 | #include "oxu210hp.h" | 47 | #include "oxu210hp.h" |
| 48 | 48 | ||
| 49 | #define DRIVER_VERSION "0.0.50" | 49 | #define DRIVER_VERSION "0.0.50" |
| 50 | 50 | ||
| 51 | /* | 51 | /* |
| 52 | * Main defines | 52 | * Main defines |
| 53 | */ | 53 | */ |
| 54 | 54 | ||
| 55 | #define oxu_dbg(oxu, fmt, args...) \ | 55 | #define oxu_dbg(oxu, fmt, args...) \ |
| 56 | dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args) | 56 | dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args) |
| 57 | #define oxu_err(oxu, fmt, args...) \ | 57 | #define oxu_err(oxu, fmt, args...) \ |
| 58 | dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args) | 58 | dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args) |
| 59 | #define oxu_info(oxu, fmt, args...) \ | 59 | #define oxu_info(oxu, fmt, args...) \ |
| 60 | dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args) | 60 | dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args) |
| 61 | 61 | ||
| 62 | #ifdef CONFIG_DYNAMIC_DEBUG | 62 | #ifdef CONFIG_DYNAMIC_DEBUG |
| 63 | #define DEBUG | 63 | #define DEBUG |
| 64 | #endif | 64 | #endif |
| 65 | 65 | ||
| 66 | static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu) | 66 | static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu) |
| 67 | { | 67 | { |
| 68 | return container_of((void *) oxu, struct usb_hcd, hcd_priv); | 68 | return container_of((void *) oxu, struct usb_hcd, hcd_priv); |
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd) | 71 | static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd) |
| 72 | { | 72 | { |
| 73 | return (struct oxu_hcd *) (hcd->hcd_priv); | 73 | return (struct oxu_hcd *) (hcd->hcd_priv); |
| 74 | } | 74 | } |
| 75 | 75 | ||
| 76 | /* | 76 | /* |
| 77 | * Debug stuff | 77 | * Debug stuff |
| 78 | */ | 78 | */ |
| 79 | 79 | ||
| 80 | #undef OXU_URB_TRACE | 80 | #undef OXU_URB_TRACE |
| 81 | #undef OXU_VERBOSE_DEBUG | 81 | #undef OXU_VERBOSE_DEBUG |
| 82 | 82 | ||
| 83 | #ifdef OXU_VERBOSE_DEBUG | 83 | #ifdef OXU_VERBOSE_DEBUG |
| 84 | #define oxu_vdbg oxu_dbg | 84 | #define oxu_vdbg oxu_dbg |
| 85 | #else | 85 | #else |
| 86 | #define oxu_vdbg(oxu, fmt, args...) /* Nop */ | 86 | #define oxu_vdbg(oxu, fmt, args...) /* Nop */ |
| 87 | #endif | 87 | #endif |
| 88 | 88 | ||
| 89 | #ifdef DEBUG | 89 | #ifdef DEBUG |
| 90 | 90 | ||
| 91 | static int __attribute__((__unused__)) | 91 | static int __attribute__((__unused__)) |
| 92 | dbg_status_buf(char *buf, unsigned len, const char *label, u32 status) | 92 | dbg_status_buf(char *buf, unsigned len, const char *label, u32 status) |
| 93 | { | 93 | { |
| 94 | return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s", | 94 | return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s", |
| 95 | label, label[0] ? " " : "", status, | 95 | label, label[0] ? " " : "", status, |
| 96 | (status & STS_ASS) ? " Async" : "", | 96 | (status & STS_ASS) ? " Async" : "", |
| 97 | (status & STS_PSS) ? " Periodic" : "", | 97 | (status & STS_PSS) ? " Periodic" : "", |
| 98 | (status & STS_RECL) ? " Recl" : "", | 98 | (status & STS_RECL) ? " Recl" : "", |
| 99 | (status & STS_HALT) ? " Halt" : "", | 99 | (status & STS_HALT) ? " Halt" : "", |
| 100 | (status & STS_IAA) ? " IAA" : "", | 100 | (status & STS_IAA) ? " IAA" : "", |
| 101 | (status & STS_FATAL) ? " FATAL" : "", | 101 | (status & STS_FATAL) ? " FATAL" : "", |
| 102 | (status & STS_FLR) ? " FLR" : "", | 102 | (status & STS_FLR) ? " FLR" : "", |
| 103 | (status & STS_PCD) ? " PCD" : "", | 103 | (status & STS_PCD) ? " PCD" : "", |
| 104 | (status & STS_ERR) ? " ERR" : "", | 104 | (status & STS_ERR) ? " ERR" : "", |
| 105 | (status & STS_INT) ? " INT" : "" | 105 | (status & STS_INT) ? " INT" : "" |
| 106 | ); | 106 | ); |
| 107 | } | 107 | } |
| 108 | 108 | ||
| 109 | static int __attribute__((__unused__)) | 109 | static int __attribute__((__unused__)) |
| 110 | dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable) | 110 | dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable) |
| 111 | { | 111 | { |
| 112 | return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s", | 112 | return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s", |
| 113 | label, label[0] ? " " : "", enable, | 113 | label, label[0] ? " " : "", enable, |
| 114 | (enable & STS_IAA) ? " IAA" : "", | 114 | (enable & STS_IAA) ? " IAA" : "", |
| 115 | (enable & STS_FATAL) ? " FATAL" : "", | 115 | (enable & STS_FATAL) ? " FATAL" : "", |
| 116 | (enable & STS_FLR) ? " FLR" : "", | 116 | (enable & STS_FLR) ? " FLR" : "", |
| 117 | (enable & STS_PCD) ? " PCD" : "", | 117 | (enable & STS_PCD) ? " PCD" : "", |
| 118 | (enable & STS_ERR) ? " ERR" : "", | 118 | (enable & STS_ERR) ? " ERR" : "", |
| 119 | (enable & STS_INT) ? " INT" : "" | 119 | (enable & STS_INT) ? " INT" : "" |
| 120 | ); | 120 | ); |
| 121 | } | 121 | } |
| 122 | 122 | ||
| 123 | static const char *const fls_strings[] = | 123 | static const char *const fls_strings[] = |
| 124 | { "1024", "512", "256", "??" }; | 124 | { "1024", "512", "256", "??" }; |
| 125 | 125 | ||
| 126 | static int dbg_command_buf(char *buf, unsigned len, | 126 | static int dbg_command_buf(char *buf, unsigned len, |
| 127 | const char *label, u32 command) | 127 | const char *label, u32 command) |
| 128 | { | 128 | { |
| 129 | return scnprintf(buf, len, | 129 | return scnprintf(buf, len, |
| 130 | "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s", | 130 | "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s", |
| 131 | label, label[0] ? " " : "", command, | 131 | label, label[0] ? " " : "", command, |
| 132 | (command & CMD_PARK) ? "park" : "(park)", | 132 | (command & CMD_PARK) ? "park" : "(park)", |
| 133 | CMD_PARK_CNT(command), | 133 | CMD_PARK_CNT(command), |
| 134 | (command >> 16) & 0x3f, | 134 | (command >> 16) & 0x3f, |
| 135 | (command & CMD_LRESET) ? " LReset" : "", | 135 | (command & CMD_LRESET) ? " LReset" : "", |
| 136 | (command & CMD_IAAD) ? " IAAD" : "", | 136 | (command & CMD_IAAD) ? " IAAD" : "", |
| 137 | (command & CMD_ASE) ? " Async" : "", | 137 | (command & CMD_ASE) ? " Async" : "", |
| 138 | (command & CMD_PSE) ? " Periodic" : "", | 138 | (command & CMD_PSE) ? " Periodic" : "", |
| 139 | fls_strings[(command >> 2) & 0x3], | 139 | fls_strings[(command >> 2) & 0x3], |
| 140 | (command & CMD_RESET) ? " Reset" : "", | 140 | (command & CMD_RESET) ? " Reset" : "", |
| 141 | (command & CMD_RUN) ? "RUN" : "HALT" | 141 | (command & CMD_RUN) ? "RUN" : "HALT" |
| 142 | ); | 142 | ); |
| 143 | } | 143 | } |
| 144 | 144 | ||
| 145 | static int dbg_port_buf(char *buf, unsigned len, const char *label, | 145 | static int dbg_port_buf(char *buf, unsigned len, const char *label, |
| 146 | int port, u32 status) | 146 | int port, u32 status) |
| 147 | { | 147 | { |
| 148 | char *sig; | 148 | char *sig; |
| 149 | 149 | ||
| 150 | /* signaling state */ | 150 | /* signaling state */ |
| 151 | switch (status & (3 << 10)) { | 151 | switch (status & (3 << 10)) { |
| 152 | case 0 << 10: | 152 | case 0 << 10: |
| 153 | sig = "se0"; | 153 | sig = "se0"; |
| 154 | break; | 154 | break; |
| 155 | case 1 << 10: | 155 | case 1 << 10: |
| 156 | sig = "k"; /* low speed */ | 156 | sig = "k"; /* low speed */ |
| 157 | break; | 157 | break; |
| 158 | case 2 << 10: | 158 | case 2 << 10: |
| 159 | sig = "j"; | 159 | sig = "j"; |
| 160 | break; | 160 | break; |
| 161 | default: | 161 | default: |
| 162 | sig = "?"; | 162 | sig = "?"; |
| 163 | break; | 163 | break; |
| 164 | } | 164 | } |
| 165 | 165 | ||
| 166 | return scnprintf(buf, len, | 166 | return scnprintf(buf, len, |
| 167 | "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s", | 167 | "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s", |
| 168 | label, label[0] ? " " : "", port, status, | 168 | label, label[0] ? " " : "", port, status, |
| 169 | (status & PORT_POWER) ? " POWER" : "", | 169 | (status & PORT_POWER) ? " POWER" : "", |
| 170 | (status & PORT_OWNER) ? " OWNER" : "", | 170 | (status & PORT_OWNER) ? " OWNER" : "", |
| 171 | sig, | 171 | sig, |
| 172 | (status & PORT_RESET) ? " RESET" : "", | 172 | (status & PORT_RESET) ? " RESET" : "", |
| 173 | (status & PORT_SUSPEND) ? " SUSPEND" : "", | 173 | (status & PORT_SUSPEND) ? " SUSPEND" : "", |
| 174 | (status & PORT_RESUME) ? " RESUME" : "", | 174 | (status & PORT_RESUME) ? " RESUME" : "", |
| 175 | (status & PORT_OCC) ? " OCC" : "", | 175 | (status & PORT_OCC) ? " OCC" : "", |
| 176 | (status & PORT_OC) ? " OC" : "", | 176 | (status & PORT_OC) ? " OC" : "", |
| 177 | (status & PORT_PEC) ? " PEC" : "", | 177 | (status & PORT_PEC) ? " PEC" : "", |
| 178 | (status & PORT_PE) ? " PE" : "", | 178 | (status & PORT_PE) ? " PE" : "", |
| 179 | (status & PORT_CSC) ? " CSC" : "", | 179 | (status & PORT_CSC) ? " CSC" : "", |
| 180 | (status & PORT_CONNECT) ? " CONNECT" : "" | 180 | (status & PORT_CONNECT) ? " CONNECT" : "" |
| 181 | ); | 181 | ); |
| 182 | } | 182 | } |
| 183 | 183 | ||
| 184 | #else | 184 | #else |
| 185 | 185 | ||
| 186 | static inline int __attribute__((__unused__)) | 186 | static inline int __attribute__((__unused__)) |
| 187 | dbg_status_buf(char *buf, unsigned len, const char *label, u32 status) | 187 | dbg_status_buf(char *buf, unsigned len, const char *label, u32 status) |
| 188 | { return 0; } | 188 | { return 0; } |
| 189 | 189 | ||
| 190 | static inline int __attribute__((__unused__)) | 190 | static inline int __attribute__((__unused__)) |
| 191 | dbg_command_buf(char *buf, unsigned len, const char *label, u32 command) | 191 | dbg_command_buf(char *buf, unsigned len, const char *label, u32 command) |
| 192 | { return 0; } | 192 | { return 0; } |
| 193 | 193 | ||
| 194 | static inline int __attribute__((__unused__)) | 194 | static inline int __attribute__((__unused__)) |
| 195 | dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable) | 195 | dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable) |
| 196 | { return 0; } | 196 | { return 0; } |
| 197 | 197 | ||
| 198 | static inline int __attribute__((__unused__)) | 198 | static inline int __attribute__((__unused__)) |
| 199 | dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status) | 199 | dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status) |
| 200 | { return 0; } | 200 | { return 0; } |
| 201 | 201 | ||
| 202 | #endif /* DEBUG */ | 202 | #endif /* DEBUG */ |
| 203 | 203 | ||
| 204 | /* functions have the "wrong" filename when they're output... */ | 204 | /* functions have the "wrong" filename when they're output... */ |
| 205 | #define dbg_status(oxu, label, status) { \ | 205 | #define dbg_status(oxu, label, status) { \ |
| 206 | char _buf[80]; \ | 206 | char _buf[80]; \ |
| 207 | dbg_status_buf(_buf, sizeof _buf, label, status); \ | 207 | dbg_status_buf(_buf, sizeof _buf, label, status); \ |
| 208 | oxu_dbg(oxu, "%s\n", _buf); \ | 208 | oxu_dbg(oxu, "%s\n", _buf); \ |
| 209 | } | 209 | } |
| 210 | 210 | ||
| 211 | #define dbg_cmd(oxu, label, command) { \ | 211 | #define dbg_cmd(oxu, label, command) { \ |
| 212 | char _buf[80]; \ | 212 | char _buf[80]; \ |
| 213 | dbg_command_buf(_buf, sizeof _buf, label, command); \ | 213 | dbg_command_buf(_buf, sizeof _buf, label, command); \ |
| 214 | oxu_dbg(oxu, "%s\n", _buf); \ | 214 | oxu_dbg(oxu, "%s\n", _buf); \ |
| 215 | } | 215 | } |
| 216 | 216 | ||
| 217 | #define dbg_port(oxu, label, port, status) { \ | 217 | #define dbg_port(oxu, label, port, status) { \ |
| 218 | char _buf[80]; \ | 218 | char _buf[80]; \ |
| 219 | dbg_port_buf(_buf, sizeof _buf, label, port, status); \ | 219 | dbg_port_buf(_buf, sizeof _buf, label, port, status); \ |
| 220 | oxu_dbg(oxu, "%s\n", _buf); \ | 220 | oxu_dbg(oxu, "%s\n", _buf); \ |
| 221 | } | 221 | } |
| 222 | 222 | ||
| 223 | /* | 223 | /* |
| 224 | * Module parameters | 224 | * Module parameters |
| 225 | */ | 225 | */ |
| 226 | 226 | ||
| 227 | /* Initial IRQ latency: faster than hw default */ | 227 | /* Initial IRQ latency: faster than hw default */ |
| 228 | static int log2_irq_thresh; /* 0 to 6 */ | 228 | static int log2_irq_thresh; /* 0 to 6 */ |
| 229 | module_param(log2_irq_thresh, int, S_IRUGO); | 229 | module_param(log2_irq_thresh, int, S_IRUGO); |
| 230 | MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | 230 | MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); |
| 231 | 231 | ||
| 232 | /* Initial park setting: slower than hw default */ | 232 | /* Initial park setting: slower than hw default */ |
| 233 | static unsigned park; | 233 | static unsigned park; |
| 234 | module_param(park, uint, S_IRUGO); | 234 | module_param(park, uint, S_IRUGO); |
| 235 | MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets"); | 235 | MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets"); |
| 236 | 236 | ||
| 237 | /* For flakey hardware, ignore overcurrent indicators */ | 237 | /* For flakey hardware, ignore overcurrent indicators */ |
| 238 | static bool ignore_oc; | 238 | static bool ignore_oc; |
| 239 | module_param(ignore_oc, bool, S_IRUGO); | 239 | module_param(ignore_oc, bool, S_IRUGO); |
| 240 | MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications"); | 240 | MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications"); |
| 241 | 241 | ||
| 242 | 242 | ||
| 243 | static void ehci_work(struct oxu_hcd *oxu); | 243 | static void ehci_work(struct oxu_hcd *oxu); |
| 244 | static int oxu_hub_control(struct usb_hcd *hcd, | 244 | static int oxu_hub_control(struct usb_hcd *hcd, |
| 245 | u16 typeReq, u16 wValue, u16 wIndex, | 245 | u16 typeReq, u16 wValue, u16 wIndex, |
| 246 | char *buf, u16 wLength); | 246 | char *buf, u16 wLength); |
| 247 | 247 | ||
| 248 | /* | 248 | /* |
| 249 | * Local functions | 249 | * Local functions |
| 250 | */ | 250 | */ |
| 251 | 251 | ||
| 252 | /* Low level read/write registers functions */ | 252 | /* Low level read/write registers functions */ |
| 253 | static inline u32 oxu_readl(void *base, u32 reg) | 253 | static inline u32 oxu_readl(void *base, u32 reg) |
| 254 | { | 254 | { |
| 255 | return readl(base + reg); | 255 | return readl(base + reg); |
| 256 | } | 256 | } |
| 257 | 257 | ||
| 258 | static inline void oxu_writel(void *base, u32 reg, u32 val) | 258 | static inline void oxu_writel(void *base, u32 reg, u32 val) |
| 259 | { | 259 | { |
| 260 | writel(val, base + reg); | 260 | writel(val, base + reg); |
| 261 | } | 261 | } |
| 262 | 262 | ||
| 263 | static inline void timer_action_done(struct oxu_hcd *oxu, | 263 | static inline void timer_action_done(struct oxu_hcd *oxu, |
| 264 | enum ehci_timer_action action) | 264 | enum ehci_timer_action action) |
| 265 | { | 265 | { |
| 266 | clear_bit(action, &oxu->actions); | 266 | clear_bit(action, &oxu->actions); |
| 267 | } | 267 | } |
| 268 | 268 | ||
| 269 | static inline void timer_action(struct oxu_hcd *oxu, | 269 | static inline void timer_action(struct oxu_hcd *oxu, |
| 270 | enum ehci_timer_action action) | 270 | enum ehci_timer_action action) |
| 271 | { | 271 | { |
| 272 | if (!test_and_set_bit(action, &oxu->actions)) { | 272 | if (!test_and_set_bit(action, &oxu->actions)) { |
| 273 | unsigned long t; | 273 | unsigned long t; |
| 274 | 274 | ||
| 275 | switch (action) { | 275 | switch (action) { |
| 276 | case TIMER_IAA_WATCHDOG: | 276 | case TIMER_IAA_WATCHDOG: |
| 277 | t = EHCI_IAA_JIFFIES; | 277 | t = EHCI_IAA_JIFFIES; |
| 278 | break; | 278 | break; |
| 279 | case TIMER_IO_WATCHDOG: | 279 | case TIMER_IO_WATCHDOG: |
| 280 | t = EHCI_IO_JIFFIES; | 280 | t = EHCI_IO_JIFFIES; |
| 281 | break; | 281 | break; |
| 282 | case TIMER_ASYNC_OFF: | 282 | case TIMER_ASYNC_OFF: |
| 283 | t = EHCI_ASYNC_JIFFIES; | 283 | t = EHCI_ASYNC_JIFFIES; |
| 284 | break; | 284 | break; |
| 285 | case TIMER_ASYNC_SHRINK: | 285 | case TIMER_ASYNC_SHRINK: |
| 286 | default: | 286 | default: |
| 287 | t = EHCI_SHRINK_JIFFIES; | 287 | t = EHCI_SHRINK_JIFFIES; |
| 288 | break; | 288 | break; |
| 289 | } | 289 | } |
| 290 | t += jiffies; | 290 | t += jiffies; |
| 291 | /* all timings except IAA watchdog can be overridden. | 291 | /* all timings except IAA watchdog can be overridden. |
| 292 | * async queue SHRINK often precedes IAA. while it's ready | 292 | * async queue SHRINK often precedes IAA. while it's ready |
| 293 | * to go OFF neither can matter, and afterwards the IO | 293 | * to go OFF neither can matter, and afterwards the IO |
| 294 | * watchdog stops unless there's still periodic traffic. | 294 | * watchdog stops unless there's still periodic traffic. |
| 295 | */ | 295 | */ |
| 296 | if (action != TIMER_IAA_WATCHDOG | 296 | if (action != TIMER_IAA_WATCHDOG |
| 297 | && t > oxu->watchdog.expires | 297 | && t > oxu->watchdog.expires |
| 298 | && timer_pending(&oxu->watchdog)) | 298 | && timer_pending(&oxu->watchdog)) |
| 299 | return; | 299 | return; |
| 300 | mod_timer(&oxu->watchdog, t); | 300 | mod_timer(&oxu->watchdog, t); |
| 301 | } | 301 | } |
| 302 | } | 302 | } |
| 303 | 303 | ||
| 304 | /* | 304 | /* |
| 305 | * handshake - spin reading hc until handshake completes or fails | 305 | * handshake - spin reading hc until handshake completes or fails |
| 306 | * @ptr: address of hc register to be read | 306 | * @ptr: address of hc register to be read |
| 307 | * @mask: bits to look at in result of read | 307 | * @mask: bits to look at in result of read |
| 308 | * @done: value of those bits when handshake succeeds | 308 | * @done: value of those bits when handshake succeeds |
| 309 | * @usec: timeout in microseconds | 309 | * @usec: timeout in microseconds |
| 310 | * | 310 | * |
| 311 | * Returns negative errno, or zero on success | 311 | * Returns negative errno, or zero on success |
| 312 | * | 312 | * |
| 313 | * Success happens when the "mask" bits have the specified value (hardware | 313 | * Success happens when the "mask" bits have the specified value (hardware |
| 314 | * handshake done). There are two failure modes: "usec" have passed (major | 314 | * handshake done). There are two failure modes: "usec" have passed (major |
| 315 | * hardware flakeout), or the register reads as all-ones (hardware removed). | 315 | * hardware flakeout), or the register reads as all-ones (hardware removed). |
| 316 | * | 316 | * |
| 317 | * That last failure should_only happen in cases like physical cardbus eject | 317 | * That last failure should_only happen in cases like physical cardbus eject |
| 318 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | 318 | * before driver shutdown. But it also seems to be caused by bugs in cardbus |
| 319 | * bridge shutdown: shutting down the bridge before the devices using it. | 319 | * bridge shutdown: shutting down the bridge before the devices using it. |
| 320 | */ | 320 | */ |
| 321 | static int handshake(struct oxu_hcd *oxu, void __iomem *ptr, | 321 | static int handshake(struct oxu_hcd *oxu, void __iomem *ptr, |
| 322 | u32 mask, u32 done, int usec) | 322 | u32 mask, u32 done, int usec) |
| 323 | { | 323 | { |
| 324 | u32 result; | 324 | u32 result; |
| 325 | 325 | ||
| 326 | do { | 326 | do { |
| 327 | result = readl(ptr); | 327 | result = readl(ptr); |
| 328 | if (result == ~(u32)0) /* card removed */ | 328 | if (result == ~(u32)0) /* card removed */ |
| 329 | return -ENODEV; | 329 | return -ENODEV; |
| 330 | result &= mask; | 330 | result &= mask; |
| 331 | if (result == done) | 331 | if (result == done) |
| 332 | return 0; | 332 | return 0; |
| 333 | udelay(1); | 333 | udelay(1); |
| 334 | usec--; | 334 | usec--; |
| 335 | } while (usec > 0); | 335 | } while (usec > 0); |
| 336 | return -ETIMEDOUT; | 336 | return -ETIMEDOUT; |
| 337 | } | 337 | } |
| 338 | 338 | ||
| 339 | /* Force HC to halt state from unknown (EHCI spec section 2.3) */ | 339 | /* Force HC to halt state from unknown (EHCI spec section 2.3) */ |
| 340 | static int ehci_halt(struct oxu_hcd *oxu) | 340 | static int ehci_halt(struct oxu_hcd *oxu) |
| 341 | { | 341 | { |
| 342 | u32 temp = readl(&oxu->regs->status); | 342 | u32 temp = readl(&oxu->regs->status); |
| 343 | 343 | ||
| 344 | /* disable any irqs left enabled by previous code */ | 344 | /* disable any irqs left enabled by previous code */ |
| 345 | writel(0, &oxu->regs->intr_enable); | 345 | writel(0, &oxu->regs->intr_enable); |
| 346 | 346 | ||
| 347 | if ((temp & STS_HALT) != 0) | 347 | if ((temp & STS_HALT) != 0) |
| 348 | return 0; | 348 | return 0; |
| 349 | 349 | ||
| 350 | temp = readl(&oxu->regs->command); | 350 | temp = readl(&oxu->regs->command); |
| 351 | temp &= ~CMD_RUN; | 351 | temp &= ~CMD_RUN; |
| 352 | writel(temp, &oxu->regs->command); | 352 | writel(temp, &oxu->regs->command); |
| 353 | return handshake(oxu, &oxu->regs->status, | 353 | return handshake(oxu, &oxu->regs->status, |
| 354 | STS_HALT, STS_HALT, 16 * 125); | 354 | STS_HALT, STS_HALT, 16 * 125); |
| 355 | } | 355 | } |
| 356 | 356 | ||
| 357 | /* Put TDI/ARC silicon into EHCI mode */ | 357 | /* Put TDI/ARC silicon into EHCI mode */ |
| 358 | static void tdi_reset(struct oxu_hcd *oxu) | 358 | static void tdi_reset(struct oxu_hcd *oxu) |
| 359 | { | 359 | { |
| 360 | u32 __iomem *reg_ptr; | 360 | u32 __iomem *reg_ptr; |
| 361 | u32 tmp; | 361 | u32 tmp; |
| 362 | 362 | ||
| 363 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68); | 363 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68); |
| 364 | tmp = readl(reg_ptr); | 364 | tmp = readl(reg_ptr); |
| 365 | tmp |= 0x3; | 365 | tmp |= 0x3; |
| 366 | writel(tmp, reg_ptr); | 366 | writel(tmp, reg_ptr); |
| 367 | } | 367 | } |
| 368 | 368 | ||
| 369 | /* Reset a non-running (STS_HALT == 1) controller */ | 369 | /* Reset a non-running (STS_HALT == 1) controller */ |
| 370 | static int ehci_reset(struct oxu_hcd *oxu) | 370 | static int ehci_reset(struct oxu_hcd *oxu) |
| 371 | { | 371 | { |
| 372 | int retval; | 372 | int retval; |
| 373 | u32 command = readl(&oxu->regs->command); | 373 | u32 command = readl(&oxu->regs->command); |
| 374 | 374 | ||
| 375 | command |= CMD_RESET; | 375 | command |= CMD_RESET; |
| 376 | dbg_cmd(oxu, "reset", command); | 376 | dbg_cmd(oxu, "reset", command); |
| 377 | writel(command, &oxu->regs->command); | 377 | writel(command, &oxu->regs->command); |
| 378 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 378 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
| 379 | oxu->next_statechange = jiffies; | 379 | oxu->next_statechange = jiffies; |
| 380 | retval = handshake(oxu, &oxu->regs->command, | 380 | retval = handshake(oxu, &oxu->regs->command, |
| 381 | CMD_RESET, 0, 250 * 1000); | 381 | CMD_RESET, 0, 250 * 1000); |
| 382 | 382 | ||
| 383 | if (retval) | 383 | if (retval) |
| 384 | return retval; | 384 | return retval; |
| 385 | 385 | ||
| 386 | tdi_reset(oxu); | 386 | tdi_reset(oxu); |
| 387 | 387 | ||
| 388 | return retval; | 388 | return retval; |
| 389 | } | 389 | } |
| 390 | 390 | ||
| 391 | /* Idle the controller (from running) */ | 391 | /* Idle the controller (from running) */ |
| 392 | static void ehci_quiesce(struct oxu_hcd *oxu) | 392 | static void ehci_quiesce(struct oxu_hcd *oxu) |
| 393 | { | 393 | { |
| 394 | u32 temp; | 394 | u32 temp; |
| 395 | 395 | ||
| 396 | #ifdef DEBUG | 396 | #ifdef DEBUG |
| 397 | if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) | 397 | if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) |
| 398 | BUG(); | 398 | BUG(); |
| 399 | #endif | 399 | #endif |
| 400 | 400 | ||
| 401 | /* wait for any schedule enables/disables to take effect */ | 401 | /* wait for any schedule enables/disables to take effect */ |
| 402 | temp = readl(&oxu->regs->command) << 10; | 402 | temp = readl(&oxu->regs->command) << 10; |
| 403 | temp &= STS_ASS | STS_PSS; | 403 | temp &= STS_ASS | STS_PSS; |
| 404 | if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS, | 404 | if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS, |
| 405 | temp, 16 * 125) != 0) { | 405 | temp, 16 * 125) != 0) { |
| 406 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 406 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
| 407 | return; | 407 | return; |
| 408 | } | 408 | } |
| 409 | 409 | ||
| 410 | /* then disable anything that's still active */ | 410 | /* then disable anything that's still active */ |
| 411 | temp = readl(&oxu->regs->command); | 411 | temp = readl(&oxu->regs->command); |
| 412 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); | 412 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
| 413 | writel(temp, &oxu->regs->command); | 413 | writel(temp, &oxu->regs->command); |
| 414 | 414 | ||
| 415 | /* hardware can take 16 microframes to turn off ... */ | 415 | /* hardware can take 16 microframes to turn off ... */ |
| 416 | if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS, | 416 | if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS, |
| 417 | 0, 16 * 125) != 0) { | 417 | 0, 16 * 125) != 0) { |
| 418 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 418 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
| 419 | return; | 419 | return; |
| 420 | } | 420 | } |
| 421 | } | 421 | } |
| 422 | 422 | ||
| 423 | static int check_reset_complete(struct oxu_hcd *oxu, int index, | 423 | static int check_reset_complete(struct oxu_hcd *oxu, int index, |
| 424 | u32 __iomem *status_reg, int port_status) | 424 | u32 __iomem *status_reg, int port_status) |
| 425 | { | 425 | { |
| 426 | if (!(port_status & PORT_CONNECT)) { | 426 | if (!(port_status & PORT_CONNECT)) { |
| 427 | oxu->reset_done[index] = 0; | 427 | oxu->reset_done[index] = 0; |
| 428 | return port_status; | 428 | return port_status; |
| 429 | } | 429 | } |
| 430 | 430 | ||
| 431 | /* if reset finished and it's still not enabled -- handoff */ | 431 | /* if reset finished and it's still not enabled -- handoff */ |
| 432 | if (!(port_status & PORT_PE)) { | 432 | if (!(port_status & PORT_PE)) { |
| 433 | oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n", | 433 | oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n", |
| 434 | index+1); | 434 | index+1); |
| 435 | return port_status; | 435 | return port_status; |
| 436 | } else | 436 | } else |
| 437 | oxu_dbg(oxu, "port %d high speed\n", index + 1); | 437 | oxu_dbg(oxu, "port %d high speed\n", index + 1); |
| 438 | 438 | ||
| 439 | return port_status; | 439 | return port_status; |
| 440 | } | 440 | } |
| 441 | 441 | ||
| 442 | static void ehci_hub_descriptor(struct oxu_hcd *oxu, | 442 | static void ehci_hub_descriptor(struct oxu_hcd *oxu, |
| 443 | struct usb_hub_descriptor *desc) | 443 | struct usb_hub_descriptor *desc) |
| 444 | { | 444 | { |
| 445 | int ports = HCS_N_PORTS(oxu->hcs_params); | 445 | int ports = HCS_N_PORTS(oxu->hcs_params); |
| 446 | u16 temp; | 446 | u16 temp; |
| 447 | 447 | ||
| 448 | desc->bDescriptorType = 0x29; | 448 | desc->bDescriptorType = 0x29; |
| 449 | desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */ | 449 | desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */ |
| 450 | desc->bHubContrCurrent = 0; | 450 | desc->bHubContrCurrent = 0; |
| 451 | 451 | ||
| 452 | desc->bNbrPorts = ports; | 452 | desc->bNbrPorts = ports; |
| 453 | temp = 1 + (ports / 8); | 453 | temp = 1 + (ports / 8); |
| 454 | desc->bDescLength = 7 + 2 * temp; | 454 | desc->bDescLength = 7 + 2 * temp; |
| 455 | 455 | ||
| 456 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 456 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
| 457 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); | 457 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
| 458 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); | 458 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
| 459 | 459 | ||
| 460 | temp = 0x0008; /* per-port overcurrent reporting */ | 460 | temp = 0x0008; /* per-port overcurrent reporting */ |
| 461 | if (HCS_PPC(oxu->hcs_params)) | 461 | if (HCS_PPC(oxu->hcs_params)) |
| 462 | temp |= 0x0001; /* per-port power control */ | 462 | temp |= 0x0001; /* per-port power control */ |
| 463 | else | 463 | else |
| 464 | temp |= 0x0002; /* no power switching */ | 464 | temp |= 0x0002; /* no power switching */ |
| 465 | desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp); | 465 | desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp); |
| 466 | } | 466 | } |
| 467 | 467 | ||
| 468 | 468 | ||
| 469 | /* Allocate an OXU210HP on-chip memory data buffer | 469 | /* Allocate an OXU210HP on-chip memory data buffer |
| 470 | * | 470 | * |
| 471 | * An on-chip memory data buffer is required for each OXU210HP USB transfer. | 471 | * An on-chip memory data buffer is required for each OXU210HP USB transfer. |
| 472 | * Each transfer descriptor has one or more on-chip memory data buffers. | 472 | * Each transfer descriptor has one or more on-chip memory data buffers. |
| 473 | * | 473 | * |
| 474 | * Data buffers are allocated from a fix sized pool of data blocks. | 474 | * Data buffers are allocated from a fix sized pool of data blocks. |
| 475 | * To minimise fragmentation and give reasonable memory utlisation, | 475 | * To minimise fragmentation and give reasonable memory utlisation, |
| 476 | * data buffers are allocated with sizes the power of 2 multiples of | 476 | * data buffers are allocated with sizes the power of 2 multiples of |
| 477 | * the block size, starting on an address a multiple of the allocated size. | 477 | * the block size, starting on an address a multiple of the allocated size. |
| 478 | * | 478 | * |
| 479 | * FIXME: callers of this function require a buffer to be allocated for | 479 | * FIXME: callers of this function require a buffer to be allocated for |
| 480 | * len=0. This is a waste of on-chip memory and should be fix. Then this | 480 | * len=0. This is a waste of on-chip memory and should be fix. Then this |
| 481 | * function should be changed to not allocate a buffer for len=0. | 481 | * function should be changed to not allocate a buffer for len=0. |
| 482 | */ | 482 | */ |
| 483 | static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len) | 483 | static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len) |
| 484 | { | 484 | { |
| 485 | int n_blocks; /* minium blocks needed to hold len */ | 485 | int n_blocks; /* minium blocks needed to hold len */ |
| 486 | int a_blocks; /* blocks allocated */ | 486 | int a_blocks; /* blocks allocated */ |
| 487 | int i, j; | 487 | int i, j; |
| 488 | 488 | ||
| 489 | /* Don't allocte bigger than supported */ | 489 | /* Don't allocte bigger than supported */ |
| 490 | if (len > BUFFER_SIZE * BUFFER_NUM) { | 490 | if (len > BUFFER_SIZE * BUFFER_NUM) { |
| 491 | oxu_err(oxu, "buffer too big (%d)\n", len); | 491 | oxu_err(oxu, "buffer too big (%d)\n", len); |
| 492 | return -ENOMEM; | 492 | return -ENOMEM; |
| 493 | } | 493 | } |
| 494 | 494 | ||
| 495 | spin_lock(&oxu->mem_lock); | 495 | spin_lock(&oxu->mem_lock); |
| 496 | 496 | ||
| 497 | /* Number of blocks needed to hold len */ | 497 | /* Number of blocks needed to hold len */ |
| 498 | n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE; | 498 | n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE; |
| 499 | 499 | ||
| 500 | /* Round the number of blocks up to the power of 2 */ | 500 | /* Round the number of blocks up to the power of 2 */ |
| 501 | for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1) | 501 | for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1) |
| 502 | ; | 502 | ; |
| 503 | 503 | ||
| 504 | /* Find a suitable available data buffer */ | 504 | /* Find a suitable available data buffer */ |
| 505 | for (i = 0; i < BUFFER_NUM; | 505 | for (i = 0; i < BUFFER_NUM; |
| 506 | i += max(a_blocks, (int)oxu->db_used[i])) { | 506 | i += max(a_blocks, (int)oxu->db_used[i])) { |
| 507 | 507 | ||
| 508 | /* Check all the required blocks are available */ | 508 | /* Check all the required blocks are available */ |
| 509 | for (j = 0; j < a_blocks; j++) | 509 | for (j = 0; j < a_blocks; j++) |
| 510 | if (oxu->db_used[i + j]) | 510 | if (oxu->db_used[i + j]) |
| 511 | break; | 511 | break; |
| 512 | 512 | ||
| 513 | if (j != a_blocks) | 513 | if (j != a_blocks) |
| 514 | continue; | 514 | continue; |
| 515 | 515 | ||
| 516 | /* Allocate blocks found! */ | 516 | /* Allocate blocks found! */ |
| 517 | qtd->buffer = (void *) &oxu->mem->db_pool[i]; | 517 | qtd->buffer = (void *) &oxu->mem->db_pool[i]; |
| 518 | qtd->buffer_dma = virt_to_phys(qtd->buffer); | 518 | qtd->buffer_dma = virt_to_phys(qtd->buffer); |
| 519 | 519 | ||
| 520 | qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks; | 520 | qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks; |
| 521 | oxu->db_used[i] = a_blocks; | 521 | oxu->db_used[i] = a_blocks; |
| 522 | 522 | ||
| 523 | spin_unlock(&oxu->mem_lock); | 523 | spin_unlock(&oxu->mem_lock); |
| 524 | 524 | ||
| 525 | return 0; | 525 | return 0; |
| 526 | } | 526 | } |
| 527 | 527 | ||
| 528 | /* Failed */ | 528 | /* Failed */ |
| 529 | 529 | ||
| 530 | spin_unlock(&oxu->mem_lock); | 530 | spin_unlock(&oxu->mem_lock); |
| 531 | 531 | ||
| 532 | return -ENOMEM; | 532 | return -ENOMEM; |
| 533 | } | 533 | } |
| 534 | 534 | ||
| 535 | static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) | 535 | static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) |
| 536 | { | 536 | { |
| 537 | int index; | 537 | int index; |
| 538 | 538 | ||
| 539 | spin_lock(&oxu->mem_lock); | 539 | spin_lock(&oxu->mem_lock); |
| 540 | 540 | ||
| 541 | index = (qtd->buffer - (void *) &oxu->mem->db_pool[0]) | 541 | index = (qtd->buffer - (void *) &oxu->mem->db_pool[0]) |
| 542 | / BUFFER_SIZE; | 542 | / BUFFER_SIZE; |
| 543 | oxu->db_used[index] = 0; | 543 | oxu->db_used[index] = 0; |
| 544 | qtd->qtd_buffer_len = 0; | 544 | qtd->qtd_buffer_len = 0; |
| 545 | qtd->buffer_dma = 0; | 545 | qtd->buffer_dma = 0; |
| 546 | qtd->buffer = NULL; | 546 | qtd->buffer = NULL; |
| 547 | 547 | ||
| 548 | spin_unlock(&oxu->mem_lock); | 548 | spin_unlock(&oxu->mem_lock); |
| 549 | } | 549 | } |
| 550 | 550 | ||
| 551 | static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma) | 551 | static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma) |
| 552 | { | 552 | { |
| 553 | memset(qtd, 0, sizeof *qtd); | 553 | memset(qtd, 0, sizeof *qtd); |
| 554 | qtd->qtd_dma = dma; | 554 | qtd->qtd_dma = dma; |
| 555 | qtd->hw_token = cpu_to_le32(QTD_STS_HALT); | 555 | qtd->hw_token = cpu_to_le32(QTD_STS_HALT); |
| 556 | qtd->hw_next = EHCI_LIST_END; | 556 | qtd->hw_next = EHCI_LIST_END; |
| 557 | qtd->hw_alt_next = EHCI_LIST_END; | 557 | qtd->hw_alt_next = EHCI_LIST_END; |
| 558 | INIT_LIST_HEAD(&qtd->qtd_list); | 558 | INIT_LIST_HEAD(&qtd->qtd_list); |
| 559 | } | 559 | } |
| 560 | 560 | ||
| 561 | static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) | 561 | static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) |
| 562 | { | 562 | { |
| 563 | int index; | 563 | int index; |
| 564 | 564 | ||
| 565 | if (qtd->buffer) | 565 | if (qtd->buffer) |
| 566 | oxu_buf_free(oxu, qtd); | 566 | oxu_buf_free(oxu, qtd); |
| 567 | 567 | ||
| 568 | spin_lock(&oxu->mem_lock); | 568 | spin_lock(&oxu->mem_lock); |
| 569 | 569 | ||
| 570 | index = qtd - &oxu->mem->qtd_pool[0]; | 570 | index = qtd - &oxu->mem->qtd_pool[0]; |
| 571 | oxu->qtd_used[index] = 0; | 571 | oxu->qtd_used[index] = 0; |
| 572 | 572 | ||
| 573 | spin_unlock(&oxu->mem_lock); | 573 | spin_unlock(&oxu->mem_lock); |
| 574 | } | 574 | } |
| 575 | 575 | ||
| 576 | static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu) | 576 | static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu) |
| 577 | { | 577 | { |
| 578 | int i; | 578 | int i; |
| 579 | struct ehci_qtd *qtd = NULL; | 579 | struct ehci_qtd *qtd = NULL; |
| 580 | 580 | ||
| 581 | spin_lock(&oxu->mem_lock); | 581 | spin_lock(&oxu->mem_lock); |
| 582 | 582 | ||
| 583 | for (i = 0; i < QTD_NUM; i++) | 583 | for (i = 0; i < QTD_NUM; i++) |
| 584 | if (!oxu->qtd_used[i]) | 584 | if (!oxu->qtd_used[i]) |
| 585 | break; | 585 | break; |
| 586 | 586 | ||
| 587 | if (i < QTD_NUM) { | 587 | if (i < QTD_NUM) { |
| 588 | qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i]; | 588 | qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i]; |
| 589 | memset(qtd, 0, sizeof *qtd); | 589 | memset(qtd, 0, sizeof *qtd); |
| 590 | 590 | ||
| 591 | qtd->hw_token = cpu_to_le32(QTD_STS_HALT); | 591 | qtd->hw_token = cpu_to_le32(QTD_STS_HALT); |
| 592 | qtd->hw_next = EHCI_LIST_END; | 592 | qtd->hw_next = EHCI_LIST_END; |
| 593 | qtd->hw_alt_next = EHCI_LIST_END; | 593 | qtd->hw_alt_next = EHCI_LIST_END; |
| 594 | INIT_LIST_HEAD(&qtd->qtd_list); | 594 | INIT_LIST_HEAD(&qtd->qtd_list); |
| 595 | 595 | ||
| 596 | qtd->qtd_dma = virt_to_phys(qtd); | 596 | qtd->qtd_dma = virt_to_phys(qtd); |
| 597 | 597 | ||
| 598 | oxu->qtd_used[i] = 1; | 598 | oxu->qtd_used[i] = 1; |
| 599 | } | 599 | } |
| 600 | 600 | ||
| 601 | spin_unlock(&oxu->mem_lock); | 601 | spin_unlock(&oxu->mem_lock); |
| 602 | 602 | ||
| 603 | return qtd; | 603 | return qtd; |
| 604 | } | 604 | } |
| 605 | 605 | ||
| 606 | static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh) | 606 | static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 607 | { | 607 | { |
| 608 | int index; | 608 | int index; |
| 609 | 609 | ||
| 610 | spin_lock(&oxu->mem_lock); | 610 | spin_lock(&oxu->mem_lock); |
| 611 | 611 | ||
| 612 | index = qh - &oxu->mem->qh_pool[0]; | 612 | index = qh - &oxu->mem->qh_pool[0]; |
| 613 | oxu->qh_used[index] = 0; | 613 | oxu->qh_used[index] = 0; |
| 614 | 614 | ||
| 615 | spin_unlock(&oxu->mem_lock); | 615 | spin_unlock(&oxu->mem_lock); |
| 616 | } | 616 | } |
| 617 | 617 | ||
| 618 | static void qh_destroy(struct kref *kref) | 618 | static void qh_destroy(struct kref *kref) |
| 619 | { | 619 | { |
| 620 | struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref); | 620 | struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref); |
| 621 | struct oxu_hcd *oxu = qh->oxu; | 621 | struct oxu_hcd *oxu = qh->oxu; |
| 622 | 622 | ||
| 623 | /* clean qtds first, and know this is not linked */ | 623 | /* clean qtds first, and know this is not linked */ |
| 624 | if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) { | 624 | if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) { |
| 625 | oxu_dbg(oxu, "unused qh not empty!\n"); | 625 | oxu_dbg(oxu, "unused qh not empty!\n"); |
| 626 | BUG(); | 626 | BUG(); |
| 627 | } | 627 | } |
| 628 | if (qh->dummy) | 628 | if (qh->dummy) |
| 629 | oxu_qtd_free(oxu, qh->dummy); | 629 | oxu_qtd_free(oxu, qh->dummy); |
| 630 | oxu_qh_free(oxu, qh); | 630 | oxu_qh_free(oxu, qh); |
| 631 | } | 631 | } |
| 632 | 632 | ||
| 633 | static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu) | 633 | static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu) |
| 634 | { | 634 | { |
| 635 | int i; | 635 | int i; |
| 636 | struct ehci_qh *qh = NULL; | 636 | struct ehci_qh *qh = NULL; |
| 637 | 637 | ||
| 638 | spin_lock(&oxu->mem_lock); | 638 | spin_lock(&oxu->mem_lock); |
| 639 | 639 | ||
| 640 | for (i = 0; i < QHEAD_NUM; i++) | 640 | for (i = 0; i < QHEAD_NUM; i++) |
| 641 | if (!oxu->qh_used[i]) | 641 | if (!oxu->qh_used[i]) |
| 642 | break; | 642 | break; |
| 643 | 643 | ||
| 644 | if (i < QHEAD_NUM) { | 644 | if (i < QHEAD_NUM) { |
| 645 | qh = (struct ehci_qh *) &oxu->mem->qh_pool[i]; | 645 | qh = (struct ehci_qh *) &oxu->mem->qh_pool[i]; |
| 646 | memset(qh, 0, sizeof *qh); | 646 | memset(qh, 0, sizeof *qh); |
| 647 | 647 | ||
| 648 | kref_init(&qh->kref); | 648 | kref_init(&qh->kref); |
| 649 | qh->oxu = oxu; | 649 | qh->oxu = oxu; |
| 650 | qh->qh_dma = virt_to_phys(qh); | 650 | qh->qh_dma = virt_to_phys(qh); |
| 651 | INIT_LIST_HEAD(&qh->qtd_list); | 651 | INIT_LIST_HEAD(&qh->qtd_list); |
| 652 | 652 | ||
| 653 | /* dummy td enables safe urb queuing */ | 653 | /* dummy td enables safe urb queuing */ |
| 654 | qh->dummy = ehci_qtd_alloc(oxu); | 654 | qh->dummy = ehci_qtd_alloc(oxu); |
| 655 | if (qh->dummy == NULL) { | 655 | if (qh->dummy == NULL) { |
| 656 | oxu_dbg(oxu, "no dummy td\n"); | 656 | oxu_dbg(oxu, "no dummy td\n"); |
| 657 | oxu->qh_used[i] = 0; | 657 | oxu->qh_used[i] = 0; |
| 658 | qh = NULL; | 658 | qh = NULL; |
| 659 | goto unlock; | 659 | goto unlock; |
| 660 | } | 660 | } |
| 661 | 661 | ||
| 662 | oxu->qh_used[i] = 1; | 662 | oxu->qh_used[i] = 1; |
| 663 | } | 663 | } |
| 664 | unlock: | 664 | unlock: |
| 665 | spin_unlock(&oxu->mem_lock); | 665 | spin_unlock(&oxu->mem_lock); |
| 666 | 666 | ||
| 667 | return qh; | 667 | return qh; |
| 668 | } | 668 | } |
| 669 | 669 | ||
| 670 | /* to share a qh (cpu threads, or hc) */ | 670 | /* to share a qh (cpu threads, or hc) */ |
| 671 | static inline struct ehci_qh *qh_get(struct ehci_qh *qh) | 671 | static inline struct ehci_qh *qh_get(struct ehci_qh *qh) |
| 672 | { | 672 | { |
| 673 | kref_get(&qh->kref); | 673 | kref_get(&qh->kref); |
| 674 | return qh; | 674 | return qh; |
| 675 | } | 675 | } |
| 676 | 676 | ||
| 677 | static inline void qh_put(struct ehci_qh *qh) | 677 | static inline void qh_put(struct ehci_qh *qh) |
| 678 | { | 678 | { |
| 679 | kref_put(&qh->kref, qh_destroy); | 679 | kref_put(&qh->kref, qh_destroy); |
| 680 | } | 680 | } |
| 681 | 681 | ||
| 682 | static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb) | 682 | static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb) |
| 683 | { | 683 | { |
| 684 | int index; | 684 | int index; |
| 685 | 685 | ||
| 686 | spin_lock(&oxu->mem_lock); | 686 | spin_lock(&oxu->mem_lock); |
| 687 | 687 | ||
| 688 | index = murb - &oxu->murb_pool[0]; | 688 | index = murb - &oxu->murb_pool[0]; |
| 689 | oxu->murb_used[index] = 0; | 689 | oxu->murb_used[index] = 0; |
| 690 | 690 | ||
| 691 | spin_unlock(&oxu->mem_lock); | 691 | spin_unlock(&oxu->mem_lock); |
| 692 | } | 692 | } |
| 693 | 693 | ||
| 694 | static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu) | 694 | static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu) |
| 695 | 695 | ||
| 696 | { | 696 | { |
| 697 | int i; | 697 | int i; |
| 698 | struct oxu_murb *murb = NULL; | 698 | struct oxu_murb *murb = NULL; |
| 699 | 699 | ||
| 700 | spin_lock(&oxu->mem_lock); | 700 | spin_lock(&oxu->mem_lock); |
| 701 | 701 | ||
| 702 | for (i = 0; i < MURB_NUM; i++) | 702 | for (i = 0; i < MURB_NUM; i++) |
| 703 | if (!oxu->murb_used[i]) | 703 | if (!oxu->murb_used[i]) |
| 704 | break; | 704 | break; |
| 705 | 705 | ||
| 706 | if (i < MURB_NUM) { | 706 | if (i < MURB_NUM) { |
| 707 | murb = &(oxu->murb_pool)[i]; | 707 | murb = &(oxu->murb_pool)[i]; |
| 708 | 708 | ||
| 709 | oxu->murb_used[i] = 1; | 709 | oxu->murb_used[i] = 1; |
| 710 | } | 710 | } |
| 711 | 711 | ||
| 712 | spin_unlock(&oxu->mem_lock); | 712 | spin_unlock(&oxu->mem_lock); |
| 713 | 713 | ||
| 714 | return murb; | 714 | return murb; |
| 715 | } | 715 | } |
| 716 | 716 | ||
| 717 | /* The queue heads and transfer descriptors are managed from pools tied | 717 | /* The queue heads and transfer descriptors are managed from pools tied |
| 718 | * to each of the "per device" structures. | 718 | * to each of the "per device" structures. |
| 719 | * This is the initialisation and cleanup code. | 719 | * This is the initialisation and cleanup code. |
| 720 | */ | 720 | */ |
| 721 | static void ehci_mem_cleanup(struct oxu_hcd *oxu) | 721 | static void ehci_mem_cleanup(struct oxu_hcd *oxu) |
| 722 | { | 722 | { |
| 723 | kfree(oxu->murb_pool); | 723 | kfree(oxu->murb_pool); |
| 724 | oxu->murb_pool = NULL; | 724 | oxu->murb_pool = NULL; |
| 725 | 725 | ||
| 726 | if (oxu->async) | 726 | if (oxu->async) |
| 727 | qh_put(oxu->async); | 727 | qh_put(oxu->async); |
| 728 | oxu->async = NULL; | 728 | oxu->async = NULL; |
| 729 | 729 | ||
| 730 | del_timer(&oxu->urb_timer); | 730 | del_timer(&oxu->urb_timer); |
| 731 | 731 | ||
| 732 | oxu->periodic = NULL; | 732 | oxu->periodic = NULL; |
| 733 | 733 | ||
| 734 | /* shadow periodic table */ | 734 | /* shadow periodic table */ |
| 735 | kfree(oxu->pshadow); | 735 | kfree(oxu->pshadow); |
| 736 | oxu->pshadow = NULL; | 736 | oxu->pshadow = NULL; |
| 737 | } | 737 | } |
| 738 | 738 | ||
| 739 | /* Remember to add cleanup code (above) if you add anything here. | 739 | /* Remember to add cleanup code (above) if you add anything here. |
| 740 | */ | 740 | */ |
| 741 | static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags) | 741 | static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags) |
| 742 | { | 742 | { |
| 743 | int i; | 743 | int i; |
| 744 | 744 | ||
| 745 | for (i = 0; i < oxu->periodic_size; i++) | 745 | for (i = 0; i < oxu->periodic_size; i++) |
| 746 | oxu->mem->frame_list[i] = EHCI_LIST_END; | 746 | oxu->mem->frame_list[i] = EHCI_LIST_END; |
| 747 | for (i = 0; i < QHEAD_NUM; i++) | 747 | for (i = 0; i < QHEAD_NUM; i++) |
| 748 | oxu->qh_used[i] = 0; | 748 | oxu->qh_used[i] = 0; |
| 749 | for (i = 0; i < QTD_NUM; i++) | 749 | for (i = 0; i < QTD_NUM; i++) |
| 750 | oxu->qtd_used[i] = 0; | 750 | oxu->qtd_used[i] = 0; |
| 751 | 751 | ||
| 752 | oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags); | 752 | oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags); |
| 753 | if (!oxu->murb_pool) | 753 | if (!oxu->murb_pool) |
| 754 | goto fail; | 754 | goto fail; |
| 755 | 755 | ||
| 756 | for (i = 0; i < MURB_NUM; i++) | 756 | for (i = 0; i < MURB_NUM; i++) |
| 757 | oxu->murb_used[i] = 0; | 757 | oxu->murb_used[i] = 0; |
| 758 | 758 | ||
| 759 | oxu->async = oxu_qh_alloc(oxu); | 759 | oxu->async = oxu_qh_alloc(oxu); |
| 760 | if (!oxu->async) | 760 | if (!oxu->async) |
| 761 | goto fail; | 761 | goto fail; |
| 762 | 762 | ||
| 763 | oxu->periodic = (__le32 *) &oxu->mem->frame_list; | 763 | oxu->periodic = (__le32 *) &oxu->mem->frame_list; |
| 764 | oxu->periodic_dma = virt_to_phys(oxu->periodic); | 764 | oxu->periodic_dma = virt_to_phys(oxu->periodic); |
| 765 | 765 | ||
| 766 | for (i = 0; i < oxu->periodic_size; i++) | 766 | for (i = 0; i < oxu->periodic_size; i++) |
| 767 | oxu->periodic[i] = EHCI_LIST_END; | 767 | oxu->periodic[i] = EHCI_LIST_END; |
| 768 | 768 | ||
| 769 | /* software shadow of hardware table */ | 769 | /* software shadow of hardware table */ |
| 770 | oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags); | 770 | oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags); |
| 771 | if (oxu->pshadow != NULL) | 771 | if (oxu->pshadow != NULL) |
| 772 | return 0; | 772 | return 0; |
| 773 | 773 | ||
| 774 | fail: | 774 | fail: |
| 775 | oxu_dbg(oxu, "couldn't init memory\n"); | 775 | oxu_dbg(oxu, "couldn't init memory\n"); |
| 776 | ehci_mem_cleanup(oxu); | 776 | ehci_mem_cleanup(oxu); |
| 777 | return -ENOMEM; | 777 | return -ENOMEM; |
| 778 | } | 778 | } |
| 779 | 779 | ||
| 780 | /* Fill a qtd, returning how much of the buffer we were able to queue up. | 780 | /* Fill a qtd, returning how much of the buffer we were able to queue up. |
| 781 | */ | 781 | */ |
| 782 | static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len, | 782 | static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len, |
| 783 | int token, int maxpacket) | 783 | int token, int maxpacket) |
| 784 | { | 784 | { |
| 785 | int i, count; | 785 | int i, count; |
| 786 | u64 addr = buf; | 786 | u64 addr = buf; |
| 787 | 787 | ||
| 788 | /* one buffer entry per 4K ... first might be short or unaligned */ | 788 | /* one buffer entry per 4K ... first might be short or unaligned */ |
| 789 | qtd->hw_buf[0] = cpu_to_le32((u32)addr); | 789 | qtd->hw_buf[0] = cpu_to_le32((u32)addr); |
| 790 | qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32)); | 790 | qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32)); |
| 791 | count = 0x1000 - (buf & 0x0fff); /* rest of that page */ | 791 | count = 0x1000 - (buf & 0x0fff); /* rest of that page */ |
| 792 | if (likely(len < count)) /* ... iff needed */ | 792 | if (likely(len < count)) /* ... iff needed */ |
| 793 | count = len; | 793 | count = len; |
| 794 | else { | 794 | else { |
| 795 | buf += 0x1000; | 795 | buf += 0x1000; |
| 796 | buf &= ~0x0fff; | 796 | buf &= ~0x0fff; |
| 797 | 797 | ||
| 798 | /* per-qtd limit: from 16K to 20K (best alignment) */ | 798 | /* per-qtd limit: from 16K to 20K (best alignment) */ |
| 799 | for (i = 1; count < len && i < 5; i++) { | 799 | for (i = 1; count < len && i < 5; i++) { |
| 800 | addr = buf; | 800 | addr = buf; |
| 801 | qtd->hw_buf[i] = cpu_to_le32((u32)addr); | 801 | qtd->hw_buf[i] = cpu_to_le32((u32)addr); |
| 802 | qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32)); | 802 | qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32)); |
| 803 | buf += 0x1000; | 803 | buf += 0x1000; |
| 804 | if ((count + 0x1000) < len) | 804 | if ((count + 0x1000) < len) |
| 805 | count += 0x1000; | 805 | count += 0x1000; |
| 806 | else | 806 | else |
| 807 | count = len; | 807 | count = len; |
| 808 | } | 808 | } |
| 809 | 809 | ||
| 810 | /* short packets may only terminate transfers */ | 810 | /* short packets may only terminate transfers */ |
| 811 | if (count != len) | 811 | if (count != len) |
| 812 | count -= (count % maxpacket); | 812 | count -= (count % maxpacket); |
| 813 | } | 813 | } |
| 814 | qtd->hw_token = cpu_to_le32((count << 16) | token); | 814 | qtd->hw_token = cpu_to_le32((count << 16) | token); |
| 815 | qtd->length = count; | 815 | qtd->length = count; |
| 816 | 816 | ||
| 817 | return count; | 817 | return count; |
| 818 | } | 818 | } |
| 819 | 819 | ||
| 820 | static inline void qh_update(struct oxu_hcd *oxu, | 820 | static inline void qh_update(struct oxu_hcd *oxu, |
| 821 | struct ehci_qh *qh, struct ehci_qtd *qtd) | 821 | struct ehci_qh *qh, struct ehci_qtd *qtd) |
| 822 | { | 822 | { |
| 823 | /* writes to an active overlay are unsafe */ | 823 | /* writes to an active overlay are unsafe */ |
| 824 | BUG_ON(qh->qh_state != QH_STATE_IDLE); | 824 | BUG_ON(qh->qh_state != QH_STATE_IDLE); |
| 825 | 825 | ||
| 826 | qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma); | 826 | qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma); |
| 827 | qh->hw_alt_next = EHCI_LIST_END; | 827 | qh->hw_alt_next = EHCI_LIST_END; |
| 828 | 828 | ||
| 829 | /* Except for control endpoints, we make hardware maintain data | 829 | /* Except for control endpoints, we make hardware maintain data |
| 830 | * toggle (like OHCI) ... here (re)initialize the toggle in the QH, | 830 | * toggle (like OHCI) ... here (re)initialize the toggle in the QH, |
| 831 | * and set the pseudo-toggle in udev. Only usb_clear_halt() will | 831 | * and set the pseudo-toggle in udev. Only usb_clear_halt() will |
| 832 | * ever clear it. | 832 | * ever clear it. |
| 833 | */ | 833 | */ |
| 834 | if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) { | 834 | if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) { |
| 835 | unsigned is_out, epnum; | 835 | unsigned is_out, epnum; |
| 836 | 836 | ||
| 837 | is_out = !(qtd->hw_token & cpu_to_le32(1 << 8)); | 837 | is_out = !(qtd->hw_token & cpu_to_le32(1 << 8)); |
| 838 | epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f; | 838 | epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f; |
| 839 | if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) { | 839 | if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) { |
| 840 | qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE); | 840 | qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE); |
| 841 | usb_settoggle(qh->dev, epnum, is_out, 1); | 841 | usb_settoggle(qh->dev, epnum, is_out, 1); |
| 842 | } | 842 | } |
| 843 | } | 843 | } |
| 844 | 844 | ||
| 845 | /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ | 845 | /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ |
| 846 | wmb(); | 846 | wmb(); |
| 847 | qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING); | 847 | qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING); |
| 848 | } | 848 | } |
| 849 | 849 | ||
| 850 | /* If it weren't for a common silicon quirk (writing the dummy into the qh | 850 | /* If it weren't for a common silicon quirk (writing the dummy into the qh |
| 851 | * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault | 851 | * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault |
| 852 | * recovery (including urb dequeue) would need software changes to a QH... | 852 | * recovery (including urb dequeue) would need software changes to a QH... |
| 853 | */ | 853 | */ |
| 854 | static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh) | 854 | static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 855 | { | 855 | { |
| 856 | struct ehci_qtd *qtd; | 856 | struct ehci_qtd *qtd; |
| 857 | 857 | ||
| 858 | if (list_empty(&qh->qtd_list)) | 858 | if (list_empty(&qh->qtd_list)) |
| 859 | qtd = qh->dummy; | 859 | qtd = qh->dummy; |
| 860 | else { | 860 | else { |
| 861 | qtd = list_entry(qh->qtd_list.next, | 861 | qtd = list_entry(qh->qtd_list.next, |
| 862 | struct ehci_qtd, qtd_list); | 862 | struct ehci_qtd, qtd_list); |
| 863 | /* first qtd may already be partially processed */ | 863 | /* first qtd may already be partially processed */ |
| 864 | if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current) | 864 | if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current) |
| 865 | qtd = NULL; | 865 | qtd = NULL; |
| 866 | } | 866 | } |
| 867 | 867 | ||
| 868 | if (qtd) | 868 | if (qtd) |
| 869 | qh_update(oxu, qh, qtd); | 869 | qh_update(oxu, qh, qtd); |
| 870 | } | 870 | } |
| 871 | 871 | ||
| 872 | static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb, | 872 | static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb, |
| 873 | size_t length, u32 token) | 873 | size_t length, u32 token) |
| 874 | { | 874 | { |
| 875 | /* count IN/OUT bytes, not SETUP (even short packets) */ | 875 | /* count IN/OUT bytes, not SETUP (even short packets) */ |
| 876 | if (likely(QTD_PID(token) != 2)) | 876 | if (likely(QTD_PID(token) != 2)) |
| 877 | urb->actual_length += length - QTD_LENGTH(token); | 877 | urb->actual_length += length - QTD_LENGTH(token); |
| 878 | 878 | ||
| 879 | /* don't modify error codes */ | 879 | /* don't modify error codes */ |
| 880 | if (unlikely(urb->status != -EINPROGRESS)) | 880 | if (unlikely(urb->status != -EINPROGRESS)) |
| 881 | return; | 881 | return; |
| 882 | 882 | ||
| 883 | /* force cleanup after short read; not always an error */ | 883 | /* force cleanup after short read; not always an error */ |
| 884 | if (unlikely(IS_SHORT_READ(token))) | 884 | if (unlikely(IS_SHORT_READ(token))) |
| 885 | urb->status = -EREMOTEIO; | 885 | urb->status = -EREMOTEIO; |
| 886 | 886 | ||
| 887 | /* serious "can't proceed" faults reported by the hardware */ | 887 | /* serious "can't proceed" faults reported by the hardware */ |
| 888 | if (token & QTD_STS_HALT) { | 888 | if (token & QTD_STS_HALT) { |
| 889 | if (token & QTD_STS_BABBLE) { | 889 | if (token & QTD_STS_BABBLE) { |
| 890 | /* FIXME "must" disable babbling device's port too */ | 890 | /* FIXME "must" disable babbling device's port too */ |
| 891 | urb->status = -EOVERFLOW; | 891 | urb->status = -EOVERFLOW; |
| 892 | } else if (token & QTD_STS_MMF) { | 892 | } else if (token & QTD_STS_MMF) { |
| 893 | /* fs/ls interrupt xfer missed the complete-split */ | 893 | /* fs/ls interrupt xfer missed the complete-split */ |
| 894 | urb->status = -EPROTO; | 894 | urb->status = -EPROTO; |
| 895 | } else if (token & QTD_STS_DBE) { | 895 | } else if (token & QTD_STS_DBE) { |
| 896 | urb->status = (QTD_PID(token) == 1) /* IN ? */ | 896 | urb->status = (QTD_PID(token) == 1) /* IN ? */ |
| 897 | ? -ENOSR /* hc couldn't read data */ | 897 | ? -ENOSR /* hc couldn't read data */ |
| 898 | : -ECOMM; /* hc couldn't write data */ | 898 | : -ECOMM; /* hc couldn't write data */ |
| 899 | } else if (token & QTD_STS_XACT) { | 899 | } else if (token & QTD_STS_XACT) { |
| 900 | /* timeout, bad crc, wrong PID, etc; retried */ | 900 | /* timeout, bad crc, wrong PID, etc; retried */ |
| 901 | if (QTD_CERR(token)) | 901 | if (QTD_CERR(token)) |
| 902 | urb->status = -EPIPE; | 902 | urb->status = -EPIPE; |
| 903 | else { | 903 | else { |
| 904 | oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n", | 904 | oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n", |
| 905 | urb->dev->devpath, | 905 | urb->dev->devpath, |
| 906 | usb_pipeendpoint(urb->pipe), | 906 | usb_pipeendpoint(urb->pipe), |
| 907 | usb_pipein(urb->pipe) ? "in" : "out"); | 907 | usb_pipein(urb->pipe) ? "in" : "out"); |
| 908 | urb->status = -EPROTO; | 908 | urb->status = -EPROTO; |
| 909 | } | 909 | } |
| 910 | /* CERR nonzero + no errors + halt --> stall */ | 910 | /* CERR nonzero + no errors + halt --> stall */ |
| 911 | } else if (QTD_CERR(token)) | 911 | } else if (QTD_CERR(token)) |
| 912 | urb->status = -EPIPE; | 912 | urb->status = -EPIPE; |
| 913 | else /* unknown */ | 913 | else /* unknown */ |
| 914 | urb->status = -EPROTO; | 914 | urb->status = -EPROTO; |
| 915 | 915 | ||
| 916 | oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n", | 916 | oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n", |
| 917 | usb_pipedevice(urb->pipe), | 917 | usb_pipedevice(urb->pipe), |
| 918 | usb_pipeendpoint(urb->pipe), | 918 | usb_pipeendpoint(urb->pipe), |
| 919 | usb_pipein(urb->pipe) ? "in" : "out", | 919 | usb_pipein(urb->pipe) ? "in" : "out", |
| 920 | token, urb->status); | 920 | token, urb->status); |
| 921 | } | 921 | } |
| 922 | } | 922 | } |
| 923 | 923 | ||
| 924 | static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb) | 924 | static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb) |
| 925 | __releases(oxu->lock) | 925 | __releases(oxu->lock) |
| 926 | __acquires(oxu->lock) | 926 | __acquires(oxu->lock) |
| 927 | { | 927 | { |
| 928 | if (likely(urb->hcpriv != NULL)) { | 928 | if (likely(urb->hcpriv != NULL)) { |
| 929 | struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv; | 929 | struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv; |
| 930 | 930 | ||
| 931 | /* S-mask in a QH means it's an interrupt urb */ | 931 | /* S-mask in a QH means it's an interrupt urb */ |
| 932 | if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) { | 932 | if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) { |
| 933 | 933 | ||
| 934 | /* ... update hc-wide periodic stats (for usbfs) */ | 934 | /* ... update hc-wide periodic stats (for usbfs) */ |
| 935 | oxu_to_hcd(oxu)->self.bandwidth_int_reqs--; | 935 | oxu_to_hcd(oxu)->self.bandwidth_int_reqs--; |
| 936 | } | 936 | } |
| 937 | qh_put(qh); | 937 | qh_put(qh); |
| 938 | } | 938 | } |
| 939 | 939 | ||
| 940 | urb->hcpriv = NULL; | 940 | urb->hcpriv = NULL; |
| 941 | switch (urb->status) { | 941 | switch (urb->status) { |
| 942 | case -EINPROGRESS: /* success */ | 942 | case -EINPROGRESS: /* success */ |
| 943 | urb->status = 0; | 943 | urb->status = 0; |
| 944 | default: /* fault */ | 944 | default: /* fault */ |
| 945 | break; | 945 | break; |
| 946 | case -EREMOTEIO: /* fault or normal */ | 946 | case -EREMOTEIO: /* fault or normal */ |
| 947 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | 947 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) |
| 948 | urb->status = 0; | 948 | urb->status = 0; |
| 949 | break; | 949 | break; |
| 950 | case -ECONNRESET: /* canceled */ | 950 | case -ECONNRESET: /* canceled */ |
| 951 | case -ENOENT: | 951 | case -ENOENT: |
| 952 | break; | 952 | break; |
| 953 | } | 953 | } |
| 954 | 954 | ||
| 955 | #ifdef OXU_URB_TRACE | 955 | #ifdef OXU_URB_TRACE |
| 956 | oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n", | 956 | oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n", |
| 957 | __func__, urb->dev->devpath, urb, | 957 | __func__, urb->dev->devpath, urb, |
| 958 | usb_pipeendpoint(urb->pipe), | 958 | usb_pipeendpoint(urb->pipe), |
| 959 | usb_pipein(urb->pipe) ? "in" : "out", | 959 | usb_pipein(urb->pipe) ? "in" : "out", |
| 960 | urb->status, | 960 | urb->status, |
| 961 | urb->actual_length, urb->transfer_buffer_length); | 961 | urb->actual_length, urb->transfer_buffer_length); |
| 962 | #endif | 962 | #endif |
| 963 | 963 | ||
| 964 | /* complete() can reenter this HCD */ | 964 | /* complete() can reenter this HCD */ |
| 965 | spin_unlock(&oxu->lock); | 965 | spin_unlock(&oxu->lock); |
| 966 | usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status); | 966 | usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status); |
| 967 | spin_lock(&oxu->lock); | 967 | spin_lock(&oxu->lock); |
| 968 | } | 968 | } |
| 969 | 969 | ||
| 970 | static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh); | 970 | static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh); |
| 971 | static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh); | 971 | static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh); |
| 972 | 972 | ||
| 973 | static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh); | 973 | static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh); |
| 974 | static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh); | 974 | static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh); |
| 975 | 975 | ||
| 976 | #define HALT_BIT cpu_to_le32(QTD_STS_HALT) | 976 | #define HALT_BIT cpu_to_le32(QTD_STS_HALT) |
| 977 | 977 | ||
| 978 | /* Process and free completed qtds for a qh, returning URBs to drivers. | 978 | /* Process and free completed qtds for a qh, returning URBs to drivers. |
| 979 | * Chases up to qh->hw_current. Returns number of completions called, | 979 | * Chases up to qh->hw_current. Returns number of completions called, |
| 980 | * indicating how much "real" work we did. | 980 | * indicating how much "real" work we did. |
| 981 | */ | 981 | */ |
| 982 | static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh) | 982 | static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 983 | { | 983 | { |
| 984 | struct ehci_qtd *last = NULL, *end = qh->dummy; | 984 | struct ehci_qtd *last = NULL, *end = qh->dummy; |
| 985 | struct list_head *entry, *tmp; | 985 | struct list_head *entry, *tmp; |
| 986 | int stopped; | 986 | int stopped; |
| 987 | unsigned count = 0; | 987 | unsigned count = 0; |
| 988 | int do_status = 0; | 988 | int do_status = 0; |
| 989 | u8 state; | 989 | u8 state; |
| 990 | struct oxu_murb *murb = NULL; | 990 | struct oxu_murb *murb = NULL; |
| 991 | 991 | ||
| 992 | if (unlikely(list_empty(&qh->qtd_list))) | 992 | if (unlikely(list_empty(&qh->qtd_list))) |
| 993 | return count; | 993 | return count; |
| 994 | 994 | ||
| 995 | /* completions (or tasks on other cpus) must never clobber HALT | 995 | /* completions (or tasks on other cpus) must never clobber HALT |
| 996 | * till we've gone through and cleaned everything up, even when | 996 | * till we've gone through and cleaned everything up, even when |
| 997 | * they add urbs to this qh's queue or mark them for unlinking. | 997 | * they add urbs to this qh's queue or mark them for unlinking. |
| 998 | * | 998 | * |
| 999 | * NOTE: unlinking expects to be done in queue order. | 999 | * NOTE: unlinking expects to be done in queue order. |
| 1000 | */ | 1000 | */ |
| 1001 | state = qh->qh_state; | 1001 | state = qh->qh_state; |
| 1002 | qh->qh_state = QH_STATE_COMPLETING; | 1002 | qh->qh_state = QH_STATE_COMPLETING; |
| 1003 | stopped = (state == QH_STATE_IDLE); | 1003 | stopped = (state == QH_STATE_IDLE); |
| 1004 | 1004 | ||
| 1005 | /* remove de-activated QTDs from front of queue. | 1005 | /* remove de-activated QTDs from front of queue. |
| 1006 | * after faults (including short reads), cleanup this urb | 1006 | * after faults (including short reads), cleanup this urb |
| 1007 | * then let the queue advance. | 1007 | * then let the queue advance. |
| 1008 | * if queue is stopped, handles unlinks. | 1008 | * if queue is stopped, handles unlinks. |
| 1009 | */ | 1009 | */ |
| 1010 | list_for_each_safe(entry, tmp, &qh->qtd_list) { | 1010 | list_for_each_safe(entry, tmp, &qh->qtd_list) { |
| 1011 | struct ehci_qtd *qtd; | 1011 | struct ehci_qtd *qtd; |
| 1012 | struct urb *urb; | 1012 | struct urb *urb; |
| 1013 | u32 token = 0; | 1013 | u32 token = 0; |
| 1014 | 1014 | ||
| 1015 | qtd = list_entry(entry, struct ehci_qtd, qtd_list); | 1015 | qtd = list_entry(entry, struct ehci_qtd, qtd_list); |
| 1016 | urb = qtd->urb; | 1016 | urb = qtd->urb; |
| 1017 | 1017 | ||
| 1018 | /* Clean up any state from previous QTD ...*/ | 1018 | /* Clean up any state from previous QTD ...*/ |
| 1019 | if (last) { | 1019 | if (last) { |
| 1020 | if (likely(last->urb != urb)) { | 1020 | if (likely(last->urb != urb)) { |
| 1021 | if (last->urb->complete == NULL) { | 1021 | if (last->urb->complete == NULL) { |
| 1022 | murb = (struct oxu_murb *) last->urb; | 1022 | murb = (struct oxu_murb *) last->urb; |
| 1023 | last->urb = murb->main; | 1023 | last->urb = murb->main; |
| 1024 | if (murb->last) { | 1024 | if (murb->last) { |
| 1025 | ehci_urb_done(oxu, last->urb); | 1025 | ehci_urb_done(oxu, last->urb); |
| 1026 | count++; | 1026 | count++; |
| 1027 | } | 1027 | } |
| 1028 | oxu_murb_free(oxu, murb); | 1028 | oxu_murb_free(oxu, murb); |
| 1029 | } else { | 1029 | } else { |
| 1030 | ehci_urb_done(oxu, last->urb); | 1030 | ehci_urb_done(oxu, last->urb); |
| 1031 | count++; | 1031 | count++; |
| 1032 | } | 1032 | } |
| 1033 | } | 1033 | } |
| 1034 | oxu_qtd_free(oxu, last); | 1034 | oxu_qtd_free(oxu, last); |
| 1035 | last = NULL; | 1035 | last = NULL; |
| 1036 | } | 1036 | } |
| 1037 | 1037 | ||
| 1038 | /* ignore urbs submitted during completions we reported */ | 1038 | /* ignore urbs submitted during completions we reported */ |
| 1039 | if (qtd == end) | 1039 | if (qtd == end) |
| 1040 | break; | 1040 | break; |
| 1041 | 1041 | ||
| 1042 | /* hardware copies qtd out of qh overlay */ | 1042 | /* hardware copies qtd out of qh overlay */ |
| 1043 | rmb(); | 1043 | rmb(); |
| 1044 | token = le32_to_cpu(qtd->hw_token); | 1044 | token = le32_to_cpu(qtd->hw_token); |
| 1045 | 1045 | ||
| 1046 | /* always clean up qtds the hc de-activated */ | 1046 | /* always clean up qtds the hc de-activated */ |
| 1047 | if ((token & QTD_STS_ACTIVE) == 0) { | 1047 | if ((token & QTD_STS_ACTIVE) == 0) { |
| 1048 | 1048 | ||
| 1049 | if ((token & QTD_STS_HALT) != 0) { | 1049 | if ((token & QTD_STS_HALT) != 0) { |
| 1050 | stopped = 1; | 1050 | stopped = 1; |
| 1051 | 1051 | ||
| 1052 | /* magic dummy for some short reads; qh won't advance. | 1052 | /* magic dummy for some short reads; qh won't advance. |
| 1053 | * that silicon quirk can kick in with this dummy too. | 1053 | * that silicon quirk can kick in with this dummy too. |
| 1054 | */ | 1054 | */ |
| 1055 | } else if (IS_SHORT_READ(token) && | 1055 | } else if (IS_SHORT_READ(token) && |
| 1056 | !(qtd->hw_alt_next & EHCI_LIST_END)) { | 1056 | !(qtd->hw_alt_next & EHCI_LIST_END)) { |
| 1057 | stopped = 1; | 1057 | stopped = 1; |
| 1058 | goto halt; | 1058 | goto halt; |
| 1059 | } | 1059 | } |
| 1060 | 1060 | ||
| 1061 | /* stop scanning when we reach qtds the hc is using */ | 1061 | /* stop scanning when we reach qtds the hc is using */ |
| 1062 | } else if (likely(!stopped && | 1062 | } else if (likely(!stopped && |
| 1063 | HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) { | 1063 | HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) { |
| 1064 | break; | 1064 | break; |
| 1065 | 1065 | ||
| 1066 | } else { | 1066 | } else { |
| 1067 | stopped = 1; | 1067 | stopped = 1; |
| 1068 | 1068 | ||
| 1069 | if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) | 1069 | if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) |
| 1070 | urb->status = -ESHUTDOWN; | 1070 | urb->status = -ESHUTDOWN; |
| 1071 | 1071 | ||
| 1072 | /* ignore active urbs unless some previous qtd | 1072 | /* ignore active urbs unless some previous qtd |
| 1073 | * for the urb faulted (including short read) or | 1073 | * for the urb faulted (including short read) or |
| 1074 | * its urb was canceled. we may patch qh or qtds. | 1074 | * its urb was canceled. we may patch qh or qtds. |
| 1075 | */ | 1075 | */ |
| 1076 | if (likely(urb->status == -EINPROGRESS)) | 1076 | if (likely(urb->status == -EINPROGRESS)) |
| 1077 | continue; | 1077 | continue; |
| 1078 | 1078 | ||
| 1079 | /* issue status after short control reads */ | 1079 | /* issue status after short control reads */ |
| 1080 | if (unlikely(do_status != 0) | 1080 | if (unlikely(do_status != 0) |
| 1081 | && QTD_PID(token) == 0 /* OUT */) { | 1081 | && QTD_PID(token) == 0 /* OUT */) { |
| 1082 | do_status = 0; | 1082 | do_status = 0; |
| 1083 | continue; | 1083 | continue; |
| 1084 | } | 1084 | } |
| 1085 | 1085 | ||
| 1086 | /* token in overlay may be most current */ | 1086 | /* token in overlay may be most current */ |
| 1087 | if (state == QH_STATE_IDLE | 1087 | if (state == QH_STATE_IDLE |
| 1088 | && cpu_to_le32(qtd->qtd_dma) | 1088 | && cpu_to_le32(qtd->qtd_dma) |
| 1089 | == qh->hw_current) | 1089 | == qh->hw_current) |
| 1090 | token = le32_to_cpu(qh->hw_token); | 1090 | token = le32_to_cpu(qh->hw_token); |
| 1091 | 1091 | ||
| 1092 | /* force halt for unlinked or blocked qh, so we'll | 1092 | /* force halt for unlinked or blocked qh, so we'll |
| 1093 | * patch the qh later and so that completions can't | 1093 | * patch the qh later and so that completions can't |
| 1094 | * activate it while we "know" it's stopped. | 1094 | * activate it while we "know" it's stopped. |
| 1095 | */ | 1095 | */ |
| 1096 | if ((HALT_BIT & qh->hw_token) == 0) { | 1096 | if ((HALT_BIT & qh->hw_token) == 0) { |
| 1097 | halt: | 1097 | halt: |
| 1098 | qh->hw_token |= HALT_BIT; | 1098 | qh->hw_token |= HALT_BIT; |
| 1099 | wmb(); | 1099 | wmb(); |
| 1100 | } | 1100 | } |
| 1101 | } | 1101 | } |
| 1102 | 1102 | ||
| 1103 | /* Remove it from the queue */ | 1103 | /* Remove it from the queue */ |
| 1104 | qtd_copy_status(oxu, urb->complete ? | 1104 | qtd_copy_status(oxu, urb->complete ? |
| 1105 | urb : ((struct oxu_murb *) urb)->main, | 1105 | urb : ((struct oxu_murb *) urb)->main, |
| 1106 | qtd->length, token); | 1106 | qtd->length, token); |
| 1107 | if ((usb_pipein(qtd->urb->pipe)) && | 1107 | if ((usb_pipein(qtd->urb->pipe)) && |
| 1108 | (NULL != qtd->transfer_buffer)) | 1108 | (NULL != qtd->transfer_buffer)) |
| 1109 | memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length); | 1109 | memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length); |
| 1110 | do_status = (urb->status == -EREMOTEIO) | 1110 | do_status = (urb->status == -EREMOTEIO) |
| 1111 | && usb_pipecontrol(urb->pipe); | 1111 | && usb_pipecontrol(urb->pipe); |
| 1112 | 1112 | ||
| 1113 | if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { | 1113 | if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { |
| 1114 | last = list_entry(qtd->qtd_list.prev, | 1114 | last = list_entry(qtd->qtd_list.prev, |
| 1115 | struct ehci_qtd, qtd_list); | 1115 | struct ehci_qtd, qtd_list); |
| 1116 | last->hw_next = qtd->hw_next; | 1116 | last->hw_next = qtd->hw_next; |
| 1117 | } | 1117 | } |
| 1118 | list_del(&qtd->qtd_list); | 1118 | list_del(&qtd->qtd_list); |
| 1119 | last = qtd; | 1119 | last = qtd; |
| 1120 | } | 1120 | } |
| 1121 | 1121 | ||
| 1122 | /* last urb's completion might still need calling */ | 1122 | /* last urb's completion might still need calling */ |
| 1123 | if (likely(last != NULL)) { | 1123 | if (likely(last != NULL)) { |
| 1124 | if (last->urb->complete == NULL) { | 1124 | if (last->urb->complete == NULL) { |
| 1125 | murb = (struct oxu_murb *) last->urb; | 1125 | murb = (struct oxu_murb *) last->urb; |
| 1126 | last->urb = murb->main; | 1126 | last->urb = murb->main; |
| 1127 | if (murb->last) { | 1127 | if (murb->last) { |
| 1128 | ehci_urb_done(oxu, last->urb); | 1128 | ehci_urb_done(oxu, last->urb); |
| 1129 | count++; | 1129 | count++; |
| 1130 | } | 1130 | } |
| 1131 | oxu_murb_free(oxu, murb); | 1131 | oxu_murb_free(oxu, murb); |
| 1132 | } else { | 1132 | } else { |
| 1133 | ehci_urb_done(oxu, last->urb); | 1133 | ehci_urb_done(oxu, last->urb); |
| 1134 | count++; | 1134 | count++; |
| 1135 | } | 1135 | } |
| 1136 | oxu_qtd_free(oxu, last); | 1136 | oxu_qtd_free(oxu, last); |
| 1137 | } | 1137 | } |
| 1138 | 1138 | ||
| 1139 | /* restore original state; caller must unlink or relink */ | 1139 | /* restore original state; caller must unlink or relink */ |
| 1140 | qh->qh_state = state; | 1140 | qh->qh_state = state; |
| 1141 | 1141 | ||
| 1142 | /* be sure the hardware's done with the qh before refreshing | 1142 | /* be sure the hardware's done with the qh before refreshing |
| 1143 | * it after fault cleanup, or recovering from silicon wrongly | 1143 | * it after fault cleanup, or recovering from silicon wrongly |
| 1144 | * overlaying the dummy qtd (which reduces DMA chatter). | 1144 | * overlaying the dummy qtd (which reduces DMA chatter). |
| 1145 | */ | 1145 | */ |
| 1146 | if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) { | 1146 | if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) { |
| 1147 | switch (state) { | 1147 | switch (state) { |
| 1148 | case QH_STATE_IDLE: | 1148 | case QH_STATE_IDLE: |
| 1149 | qh_refresh(oxu, qh); | 1149 | qh_refresh(oxu, qh); |
| 1150 | break; | 1150 | break; |
| 1151 | case QH_STATE_LINKED: | 1151 | case QH_STATE_LINKED: |
| 1152 | /* should be rare for periodic transfers, | 1152 | /* should be rare for periodic transfers, |
| 1153 | * except maybe high bandwidth ... | 1153 | * except maybe high bandwidth ... |
| 1154 | */ | 1154 | */ |
| 1155 | if ((cpu_to_le32(QH_SMASK) | 1155 | if ((cpu_to_le32(QH_SMASK) |
| 1156 | & qh->hw_info2) != 0) { | 1156 | & qh->hw_info2) != 0) { |
| 1157 | intr_deschedule(oxu, qh); | 1157 | intr_deschedule(oxu, qh); |
| 1158 | (void) qh_schedule(oxu, qh); | 1158 | (void) qh_schedule(oxu, qh); |
| 1159 | } else | 1159 | } else |
| 1160 | unlink_async(oxu, qh); | 1160 | unlink_async(oxu, qh); |
| 1161 | break; | 1161 | break; |
| 1162 | /* otherwise, unlink already started */ | 1162 | /* otherwise, unlink already started */ |
| 1163 | } | 1163 | } |
| 1164 | } | 1164 | } |
| 1165 | 1165 | ||
| 1166 | return count; | 1166 | return count; |
| 1167 | } | 1167 | } |
| 1168 | 1168 | ||
| 1169 | /* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */ | 1169 | /* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */ |
| 1170 | #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) | 1170 | #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) |
| 1171 | /* ... and packet size, for any kind of endpoint descriptor */ | 1171 | /* ... and packet size, for any kind of endpoint descriptor */ |
| 1172 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | 1172 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
| 1173 | 1173 | ||
| 1174 | /* Reverse of qh_urb_transaction: free a list of TDs. | 1174 | /* Reverse of qh_urb_transaction: free a list of TDs. |
| 1175 | * used for cleanup after errors, before HC sees an URB's TDs. | 1175 | * used for cleanup after errors, before HC sees an URB's TDs. |
| 1176 | */ | 1176 | */ |
| 1177 | static void qtd_list_free(struct oxu_hcd *oxu, | 1177 | static void qtd_list_free(struct oxu_hcd *oxu, |
| 1178 | struct urb *urb, struct list_head *qtd_list) | 1178 | struct urb *urb, struct list_head *qtd_list) |
| 1179 | { | 1179 | { |
| 1180 | struct list_head *entry, *temp; | 1180 | struct list_head *entry, *temp; |
| 1181 | 1181 | ||
| 1182 | list_for_each_safe(entry, temp, qtd_list) { | 1182 | list_for_each_safe(entry, temp, qtd_list) { |
| 1183 | struct ehci_qtd *qtd; | 1183 | struct ehci_qtd *qtd; |
| 1184 | 1184 | ||
| 1185 | qtd = list_entry(entry, struct ehci_qtd, qtd_list); | 1185 | qtd = list_entry(entry, struct ehci_qtd, qtd_list); |
| 1186 | list_del(&qtd->qtd_list); | 1186 | list_del(&qtd->qtd_list); |
| 1187 | oxu_qtd_free(oxu, qtd); | 1187 | oxu_qtd_free(oxu, qtd); |
| 1188 | } | 1188 | } |
| 1189 | } | 1189 | } |
| 1190 | 1190 | ||
| 1191 | /* Create a list of filled qtds for this URB; won't link into qh. | 1191 | /* Create a list of filled qtds for this URB; won't link into qh. |
| 1192 | */ | 1192 | */ |
| 1193 | static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu, | 1193 | static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu, |
| 1194 | struct urb *urb, | 1194 | struct urb *urb, |
| 1195 | struct list_head *head, | 1195 | struct list_head *head, |
| 1196 | gfp_t flags) | 1196 | gfp_t flags) |
| 1197 | { | 1197 | { |
| 1198 | struct ehci_qtd *qtd, *qtd_prev; | 1198 | struct ehci_qtd *qtd, *qtd_prev; |
| 1199 | dma_addr_t buf; | 1199 | dma_addr_t buf; |
| 1200 | int len, maxpacket; | 1200 | int len, maxpacket; |
| 1201 | int is_input; | 1201 | int is_input; |
| 1202 | u32 token; | 1202 | u32 token; |
| 1203 | void *transfer_buf = NULL; | 1203 | void *transfer_buf = NULL; |
| 1204 | int ret; | 1204 | int ret; |
| 1205 | 1205 | ||
| 1206 | /* | 1206 | /* |
| 1207 | * URBs map to sequences of QTDs: one logical transaction | 1207 | * URBs map to sequences of QTDs: one logical transaction |
| 1208 | */ | 1208 | */ |
| 1209 | qtd = ehci_qtd_alloc(oxu); | 1209 | qtd = ehci_qtd_alloc(oxu); |
| 1210 | if (unlikely(!qtd)) | 1210 | if (unlikely(!qtd)) |
| 1211 | return NULL; | 1211 | return NULL; |
| 1212 | list_add_tail(&qtd->qtd_list, head); | 1212 | list_add_tail(&qtd->qtd_list, head); |
| 1213 | qtd->urb = urb; | 1213 | qtd->urb = urb; |
| 1214 | 1214 | ||
| 1215 | token = QTD_STS_ACTIVE; | 1215 | token = QTD_STS_ACTIVE; |
| 1216 | token |= (EHCI_TUNE_CERR << 10); | 1216 | token |= (EHCI_TUNE_CERR << 10); |
| 1217 | /* for split transactions, SplitXState initialized to zero */ | 1217 | /* for split transactions, SplitXState initialized to zero */ |
| 1218 | 1218 | ||
| 1219 | len = urb->transfer_buffer_length; | 1219 | len = urb->transfer_buffer_length; |
| 1220 | is_input = usb_pipein(urb->pipe); | 1220 | is_input = usb_pipein(urb->pipe); |
| 1221 | if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input) | 1221 | if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input) |
| 1222 | urb->transfer_buffer = phys_to_virt(urb->transfer_dma); | 1222 | urb->transfer_buffer = phys_to_virt(urb->transfer_dma); |
| 1223 | 1223 | ||
| 1224 | if (usb_pipecontrol(urb->pipe)) { | 1224 | if (usb_pipecontrol(urb->pipe)) { |
| 1225 | /* SETUP pid */ | 1225 | /* SETUP pid */ |
| 1226 | ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest)); | 1226 | ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest)); |
| 1227 | if (ret) | 1227 | if (ret) |
| 1228 | goto cleanup; | 1228 | goto cleanup; |
| 1229 | 1229 | ||
| 1230 | qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest), | 1230 | qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest), |
| 1231 | token | (2 /* "setup" */ << 8), 8); | 1231 | token | (2 /* "setup" */ << 8), 8); |
| 1232 | memcpy(qtd->buffer, qtd->urb->setup_packet, | 1232 | memcpy(qtd->buffer, qtd->urb->setup_packet, |
| 1233 | sizeof(struct usb_ctrlrequest)); | 1233 | sizeof(struct usb_ctrlrequest)); |
| 1234 | 1234 | ||
| 1235 | /* ... and always at least one more pid */ | 1235 | /* ... and always at least one more pid */ |
| 1236 | token ^= QTD_TOGGLE; | 1236 | token ^= QTD_TOGGLE; |
| 1237 | qtd_prev = qtd; | 1237 | qtd_prev = qtd; |
| 1238 | qtd = ehci_qtd_alloc(oxu); | 1238 | qtd = ehci_qtd_alloc(oxu); |
| 1239 | if (unlikely(!qtd)) | 1239 | if (unlikely(!qtd)) |
| 1240 | goto cleanup; | 1240 | goto cleanup; |
| 1241 | qtd->urb = urb; | 1241 | qtd->urb = urb; |
| 1242 | qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); | 1242 | qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); |
| 1243 | list_add_tail(&qtd->qtd_list, head); | 1243 | list_add_tail(&qtd->qtd_list, head); |
| 1244 | 1244 | ||
| 1245 | /* for zero length DATA stages, STATUS is always IN */ | 1245 | /* for zero length DATA stages, STATUS is always IN */ |
| 1246 | if (len == 0) | 1246 | if (len == 0) |
| 1247 | token |= (1 /* "in" */ << 8); | 1247 | token |= (1 /* "in" */ << 8); |
| 1248 | } | 1248 | } |
| 1249 | 1249 | ||
| 1250 | /* | 1250 | /* |
| 1251 | * Data transfer stage: buffer setup | 1251 | * Data transfer stage: buffer setup |
| 1252 | */ | 1252 | */ |
| 1253 | 1253 | ||
| 1254 | ret = oxu_buf_alloc(oxu, qtd, len); | 1254 | ret = oxu_buf_alloc(oxu, qtd, len); |
| 1255 | if (ret) | 1255 | if (ret) |
| 1256 | goto cleanup; | 1256 | goto cleanup; |
| 1257 | 1257 | ||
| 1258 | buf = qtd->buffer_dma; | 1258 | buf = qtd->buffer_dma; |
| 1259 | transfer_buf = urb->transfer_buffer; | 1259 | transfer_buf = urb->transfer_buffer; |
| 1260 | 1260 | ||
| 1261 | if (!is_input) | 1261 | if (!is_input) |
| 1262 | memcpy(qtd->buffer, qtd->urb->transfer_buffer, len); | 1262 | memcpy(qtd->buffer, qtd->urb->transfer_buffer, len); |
| 1263 | 1263 | ||
| 1264 | if (is_input) | 1264 | if (is_input) |
| 1265 | token |= (1 /* "in" */ << 8); | 1265 | token |= (1 /* "in" */ << 8); |
| 1266 | /* else it's already initted to "out" pid (0 << 8) */ | 1266 | /* else it's already initted to "out" pid (0 << 8) */ |
| 1267 | 1267 | ||
| 1268 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); | 1268 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); |
| 1269 | 1269 | ||
| 1270 | /* | 1270 | /* |
| 1271 | * buffer gets wrapped in one or more qtds; | 1271 | * buffer gets wrapped in one or more qtds; |
| 1272 | * last one may be "short" (including zero len) | 1272 | * last one may be "short" (including zero len) |
| 1273 | * and may serve as a control status ack | 1273 | * and may serve as a control status ack |
| 1274 | */ | 1274 | */ |
| 1275 | for (;;) { | 1275 | for (;;) { |
| 1276 | int this_qtd_len; | 1276 | int this_qtd_len; |
| 1277 | 1277 | ||
| 1278 | this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket); | 1278 | this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket); |
| 1279 | qtd->transfer_buffer = transfer_buf; | 1279 | qtd->transfer_buffer = transfer_buf; |
| 1280 | len -= this_qtd_len; | 1280 | len -= this_qtd_len; |
| 1281 | buf += this_qtd_len; | 1281 | buf += this_qtd_len; |
| 1282 | transfer_buf += this_qtd_len; | 1282 | transfer_buf += this_qtd_len; |
| 1283 | if (is_input) | 1283 | if (is_input) |
| 1284 | qtd->hw_alt_next = oxu->async->hw_alt_next; | 1284 | qtd->hw_alt_next = oxu->async->hw_alt_next; |
| 1285 | 1285 | ||
| 1286 | /* qh makes control packets use qtd toggle; maybe switch it */ | 1286 | /* qh makes control packets use qtd toggle; maybe switch it */ |
| 1287 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) | 1287 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) |
| 1288 | token ^= QTD_TOGGLE; | 1288 | token ^= QTD_TOGGLE; |
| 1289 | 1289 | ||
| 1290 | if (likely(len <= 0)) | 1290 | if (likely(len <= 0)) |
| 1291 | break; | 1291 | break; |
| 1292 | 1292 | ||
| 1293 | qtd_prev = qtd; | 1293 | qtd_prev = qtd; |
| 1294 | qtd = ehci_qtd_alloc(oxu); | 1294 | qtd = ehci_qtd_alloc(oxu); |
| 1295 | if (unlikely(!qtd)) | 1295 | if (unlikely(!qtd)) |
| 1296 | goto cleanup; | 1296 | goto cleanup; |
| 1297 | if (likely(len > 0)) { | 1297 | if (likely(len > 0)) { |
| 1298 | ret = oxu_buf_alloc(oxu, qtd, len); | 1298 | ret = oxu_buf_alloc(oxu, qtd, len); |
| 1299 | if (ret) | 1299 | if (ret) |
| 1300 | goto cleanup; | 1300 | goto cleanup; |
| 1301 | } | 1301 | } |
| 1302 | qtd->urb = urb; | 1302 | qtd->urb = urb; |
| 1303 | qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); | 1303 | qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); |
| 1304 | list_add_tail(&qtd->qtd_list, head); | 1304 | list_add_tail(&qtd->qtd_list, head); |
| 1305 | } | 1305 | } |
| 1306 | 1306 | ||
| 1307 | /* unless the bulk/interrupt caller wants a chance to clean | 1307 | /* unless the bulk/interrupt caller wants a chance to clean |
| 1308 | * up after short reads, hc should advance qh past this urb | 1308 | * up after short reads, hc should advance qh past this urb |
| 1309 | */ | 1309 | */ |
| 1310 | if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 | 1310 | if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 |
| 1311 | || usb_pipecontrol(urb->pipe))) | 1311 | || usb_pipecontrol(urb->pipe))) |
| 1312 | qtd->hw_alt_next = EHCI_LIST_END; | 1312 | qtd->hw_alt_next = EHCI_LIST_END; |
| 1313 | 1313 | ||
| 1314 | /* | 1314 | /* |
| 1315 | * control requests may need a terminating data "status" ack; | 1315 | * control requests may need a terminating data "status" ack; |
| 1316 | * bulk ones may need a terminating short packet (zero length). | 1316 | * bulk ones may need a terminating short packet (zero length). |
| 1317 | */ | 1317 | */ |
| 1318 | if (likely(urb->transfer_buffer_length != 0)) { | 1318 | if (likely(urb->transfer_buffer_length != 0)) { |
| 1319 | int one_more = 0; | 1319 | int one_more = 0; |
| 1320 | 1320 | ||
| 1321 | if (usb_pipecontrol(urb->pipe)) { | 1321 | if (usb_pipecontrol(urb->pipe)) { |
| 1322 | one_more = 1; | 1322 | one_more = 1; |
| 1323 | token ^= 0x0100; /* "in" <--> "out" */ | 1323 | token ^= 0x0100; /* "in" <--> "out" */ |
| 1324 | token |= QTD_TOGGLE; /* force DATA1 */ | 1324 | token |= QTD_TOGGLE; /* force DATA1 */ |
| 1325 | } else if (usb_pipebulk(urb->pipe) | 1325 | } else if (usb_pipebulk(urb->pipe) |
| 1326 | && (urb->transfer_flags & URB_ZERO_PACKET) | 1326 | && (urb->transfer_flags & URB_ZERO_PACKET) |
| 1327 | && !(urb->transfer_buffer_length % maxpacket)) { | 1327 | && !(urb->transfer_buffer_length % maxpacket)) { |
| 1328 | one_more = 1; | 1328 | one_more = 1; |
| 1329 | } | 1329 | } |
| 1330 | if (one_more) { | 1330 | if (one_more) { |
| 1331 | qtd_prev = qtd; | 1331 | qtd_prev = qtd; |
| 1332 | qtd = ehci_qtd_alloc(oxu); | 1332 | qtd = ehci_qtd_alloc(oxu); |
| 1333 | if (unlikely(!qtd)) | 1333 | if (unlikely(!qtd)) |
| 1334 | goto cleanup; | 1334 | goto cleanup; |
| 1335 | qtd->urb = urb; | 1335 | qtd->urb = urb; |
| 1336 | qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); | 1336 | qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); |
| 1337 | list_add_tail(&qtd->qtd_list, head); | 1337 | list_add_tail(&qtd->qtd_list, head); |
| 1338 | 1338 | ||
| 1339 | /* never any data in such packets */ | 1339 | /* never any data in such packets */ |
| 1340 | qtd_fill(qtd, 0, 0, token, 0); | 1340 | qtd_fill(qtd, 0, 0, token, 0); |
| 1341 | } | 1341 | } |
| 1342 | } | 1342 | } |
| 1343 | 1343 | ||
| 1344 | /* by default, enable interrupt on urb completion */ | 1344 | /* by default, enable interrupt on urb completion */ |
| 1345 | qtd->hw_token |= cpu_to_le32(QTD_IOC); | 1345 | qtd->hw_token |= cpu_to_le32(QTD_IOC); |
| 1346 | return head; | 1346 | return head; |
| 1347 | 1347 | ||
| 1348 | cleanup: | 1348 | cleanup: |
| 1349 | qtd_list_free(oxu, urb, head); | 1349 | qtd_list_free(oxu, urb, head); |
| 1350 | return NULL; | 1350 | return NULL; |
| 1351 | } | 1351 | } |
| 1352 | 1352 | ||
| 1353 | /* Each QH holds a qtd list; a QH is used for everything except iso. | 1353 | /* Each QH holds a qtd list; a QH is used for everything except iso. |
| 1354 | * | 1354 | * |
| 1355 | * For interrupt urbs, the scheduler must set the microframe scheduling | 1355 | * For interrupt urbs, the scheduler must set the microframe scheduling |
| 1356 | * mask(s) each time the QH gets scheduled. For highspeed, that's | 1356 | * mask(s) each time the QH gets scheduled. For highspeed, that's |
| 1357 | * just one microframe in the s-mask. For split interrupt transactions | 1357 | * just one microframe in the s-mask. For split interrupt transactions |
| 1358 | * there are additional complications: c-mask, maybe FSTNs. | 1358 | * there are additional complications: c-mask, maybe FSTNs. |
| 1359 | */ | 1359 | */ |
| 1360 | static struct ehci_qh *qh_make(struct oxu_hcd *oxu, | 1360 | static struct ehci_qh *qh_make(struct oxu_hcd *oxu, |
| 1361 | struct urb *urb, gfp_t flags) | 1361 | struct urb *urb, gfp_t flags) |
| 1362 | { | 1362 | { |
| 1363 | struct ehci_qh *qh = oxu_qh_alloc(oxu); | 1363 | struct ehci_qh *qh = oxu_qh_alloc(oxu); |
| 1364 | u32 info1 = 0, info2 = 0; | 1364 | u32 info1 = 0, info2 = 0; |
| 1365 | int is_input, type; | 1365 | int is_input, type; |
| 1366 | int maxp = 0; | 1366 | int maxp = 0; |
| 1367 | 1367 | ||
| 1368 | if (!qh) | 1368 | if (!qh) |
| 1369 | return qh; | 1369 | return qh; |
| 1370 | 1370 | ||
| 1371 | /* | 1371 | /* |
| 1372 | * init endpoint/device data for this QH | 1372 | * init endpoint/device data for this QH |
| 1373 | */ | 1373 | */ |
| 1374 | info1 |= usb_pipeendpoint(urb->pipe) << 8; | 1374 | info1 |= usb_pipeendpoint(urb->pipe) << 8; |
| 1375 | info1 |= usb_pipedevice(urb->pipe) << 0; | 1375 | info1 |= usb_pipedevice(urb->pipe) << 0; |
| 1376 | 1376 | ||
| 1377 | is_input = usb_pipein(urb->pipe); | 1377 | is_input = usb_pipein(urb->pipe); |
| 1378 | type = usb_pipetype(urb->pipe); | 1378 | type = usb_pipetype(urb->pipe); |
| 1379 | maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input); | 1379 | maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input); |
| 1380 | 1380 | ||
| 1381 | /* Compute interrupt scheduling parameters just once, and save. | 1381 | /* Compute interrupt scheduling parameters just once, and save. |
| 1382 | * - allowing for high bandwidth, how many nsec/uframe are used? | 1382 | * - allowing for high bandwidth, how many nsec/uframe are used? |
| 1383 | * - split transactions need a second CSPLIT uframe; same question | 1383 | * - split transactions need a second CSPLIT uframe; same question |
| 1384 | * - splits also need a schedule gap (for full/low speed I/O) | 1384 | * - splits also need a schedule gap (for full/low speed I/O) |
| 1385 | * - qh has a polling interval | 1385 | * - qh has a polling interval |
| 1386 | * | 1386 | * |
| 1387 | * For control/bulk requests, the HC or TT handles these. | 1387 | * For control/bulk requests, the HC or TT handles these. |
| 1388 | */ | 1388 | */ |
| 1389 | if (type == PIPE_INTERRUPT) { | 1389 | if (type == PIPE_INTERRUPT) { |
| 1390 | qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH, | 1390 | qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH, |
| 1391 | is_input, 0, | 1391 | is_input, 0, |
| 1392 | hb_mult(maxp) * max_packet(maxp))); | 1392 | hb_mult(maxp) * max_packet(maxp))); |
| 1393 | qh->start = NO_FRAME; | 1393 | qh->start = NO_FRAME; |
| 1394 | 1394 | ||
| 1395 | if (urb->dev->speed == USB_SPEED_HIGH) { | 1395 | if (urb->dev->speed == USB_SPEED_HIGH) { |
| 1396 | qh->c_usecs = 0; | 1396 | qh->c_usecs = 0; |
| 1397 | qh->gap_uf = 0; | 1397 | qh->gap_uf = 0; |
| 1398 | 1398 | ||
| 1399 | qh->period = urb->interval >> 3; | 1399 | qh->period = urb->interval >> 3; |
| 1400 | if (qh->period == 0 && urb->interval != 1) { | 1400 | if (qh->period == 0 && urb->interval != 1) { |
| 1401 | /* NOTE interval 2 or 4 uframes could work. | 1401 | /* NOTE interval 2 or 4 uframes could work. |
| 1402 | * But interval 1 scheduling is simpler, and | 1402 | * But interval 1 scheduling is simpler, and |
| 1403 | * includes high bandwidth. | 1403 | * includes high bandwidth. |
| 1404 | */ | 1404 | */ |
| 1405 | oxu_dbg(oxu, "intr period %d uframes, NYET!\n", | 1405 | oxu_dbg(oxu, "intr period %d uframes, NYET!\n", |
| 1406 | urb->interval); | 1406 | urb->interval); |
| 1407 | goto done; | 1407 | goto done; |
| 1408 | } | 1408 | } |
| 1409 | } else { | 1409 | } else { |
| 1410 | struct usb_tt *tt = urb->dev->tt; | 1410 | struct usb_tt *tt = urb->dev->tt; |
| 1411 | int think_time; | 1411 | int think_time; |
| 1412 | 1412 | ||
| 1413 | /* gap is f(FS/LS transfer times) */ | 1413 | /* gap is f(FS/LS transfer times) */ |
| 1414 | qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed, | 1414 | qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed, |
| 1415 | is_input, 0, maxp) / (125 * 1000); | 1415 | is_input, 0, maxp) / (125 * 1000); |
| 1416 | 1416 | ||
| 1417 | /* FIXME this just approximates SPLIT/CSPLIT times */ | 1417 | /* FIXME this just approximates SPLIT/CSPLIT times */ |
| 1418 | if (is_input) { /* SPLIT, gap, CSPLIT+DATA */ | 1418 | if (is_input) { /* SPLIT, gap, CSPLIT+DATA */ |
| 1419 | qh->c_usecs = qh->usecs + HS_USECS(0); | 1419 | qh->c_usecs = qh->usecs + HS_USECS(0); |
| 1420 | qh->usecs = HS_USECS(1); | 1420 | qh->usecs = HS_USECS(1); |
| 1421 | } else { /* SPLIT+DATA, gap, CSPLIT */ | 1421 | } else { /* SPLIT+DATA, gap, CSPLIT */ |
| 1422 | qh->usecs += HS_USECS(1); | 1422 | qh->usecs += HS_USECS(1); |
| 1423 | qh->c_usecs = HS_USECS(0); | 1423 | qh->c_usecs = HS_USECS(0); |
| 1424 | } | 1424 | } |
| 1425 | 1425 | ||
| 1426 | think_time = tt ? tt->think_time : 0; | 1426 | think_time = tt ? tt->think_time : 0; |
| 1427 | qh->tt_usecs = NS_TO_US(think_time + | 1427 | qh->tt_usecs = NS_TO_US(think_time + |
| 1428 | usb_calc_bus_time(urb->dev->speed, | 1428 | usb_calc_bus_time(urb->dev->speed, |
| 1429 | is_input, 0, max_packet(maxp))); | 1429 | is_input, 0, max_packet(maxp))); |
| 1430 | qh->period = urb->interval; | 1430 | qh->period = urb->interval; |
| 1431 | } | 1431 | } |
| 1432 | } | 1432 | } |
| 1433 | 1433 | ||
| 1434 | /* support for tt scheduling, and access to toggles */ | 1434 | /* support for tt scheduling, and access to toggles */ |
| 1435 | qh->dev = urb->dev; | 1435 | qh->dev = urb->dev; |
| 1436 | 1436 | ||
| 1437 | /* using TT? */ | 1437 | /* using TT? */ |
| 1438 | switch (urb->dev->speed) { | 1438 | switch (urb->dev->speed) { |
| 1439 | case USB_SPEED_LOW: | 1439 | case USB_SPEED_LOW: |
| 1440 | info1 |= (1 << 12); /* EPS "low" */ | 1440 | info1 |= (1 << 12); /* EPS "low" */ |
| 1441 | /* FALL THROUGH */ | 1441 | /* FALL THROUGH */ |
| 1442 | 1442 | ||
| 1443 | case USB_SPEED_FULL: | 1443 | case USB_SPEED_FULL: |
| 1444 | /* EPS 0 means "full" */ | 1444 | /* EPS 0 means "full" */ |
| 1445 | if (type != PIPE_INTERRUPT) | 1445 | if (type != PIPE_INTERRUPT) |
| 1446 | info1 |= (EHCI_TUNE_RL_TT << 28); | 1446 | info1 |= (EHCI_TUNE_RL_TT << 28); |
| 1447 | if (type == PIPE_CONTROL) { | 1447 | if (type == PIPE_CONTROL) { |
| 1448 | info1 |= (1 << 27); /* for TT */ | 1448 | info1 |= (1 << 27); /* for TT */ |
| 1449 | info1 |= 1 << 14; /* toggle from qtd */ | 1449 | info1 |= 1 << 14; /* toggle from qtd */ |
| 1450 | } | 1450 | } |
| 1451 | info1 |= maxp << 16; | 1451 | info1 |= maxp << 16; |
| 1452 | 1452 | ||
| 1453 | info2 |= (EHCI_TUNE_MULT_TT << 30); | 1453 | info2 |= (EHCI_TUNE_MULT_TT << 30); |
| 1454 | info2 |= urb->dev->ttport << 23; | 1454 | info2 |= urb->dev->ttport << 23; |
| 1455 | 1455 | ||
| 1456 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ | 1456 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ |
| 1457 | 1457 | ||
| 1458 | break; | 1458 | break; |
| 1459 | 1459 | ||
| 1460 | case USB_SPEED_HIGH: /* no TT involved */ | 1460 | case USB_SPEED_HIGH: /* no TT involved */ |
| 1461 | info1 |= (2 << 12); /* EPS "high" */ | 1461 | info1 |= (2 << 12); /* EPS "high" */ |
| 1462 | if (type == PIPE_CONTROL) { | 1462 | if (type == PIPE_CONTROL) { |
| 1463 | info1 |= (EHCI_TUNE_RL_HS << 28); | 1463 | info1 |= (EHCI_TUNE_RL_HS << 28); |
| 1464 | info1 |= 64 << 16; /* usb2 fixed maxpacket */ | 1464 | info1 |= 64 << 16; /* usb2 fixed maxpacket */ |
| 1465 | info1 |= 1 << 14; /* toggle from qtd */ | 1465 | info1 |= 1 << 14; /* toggle from qtd */ |
| 1466 | info2 |= (EHCI_TUNE_MULT_HS << 30); | 1466 | info2 |= (EHCI_TUNE_MULT_HS << 30); |
| 1467 | } else if (type == PIPE_BULK) { | 1467 | } else if (type == PIPE_BULK) { |
| 1468 | info1 |= (EHCI_TUNE_RL_HS << 28); | 1468 | info1 |= (EHCI_TUNE_RL_HS << 28); |
| 1469 | info1 |= 512 << 16; /* usb2 fixed maxpacket */ | 1469 | info1 |= 512 << 16; /* usb2 fixed maxpacket */ |
| 1470 | info2 |= (EHCI_TUNE_MULT_HS << 30); | 1470 | info2 |= (EHCI_TUNE_MULT_HS << 30); |
| 1471 | } else { /* PIPE_INTERRUPT */ | 1471 | } else { /* PIPE_INTERRUPT */ |
| 1472 | info1 |= max_packet(maxp) << 16; | 1472 | info1 |= max_packet(maxp) << 16; |
| 1473 | info2 |= hb_mult(maxp) << 30; | 1473 | info2 |= hb_mult(maxp) << 30; |
| 1474 | } | 1474 | } |
| 1475 | break; | 1475 | break; |
| 1476 | default: | 1476 | default: |
| 1477 | oxu_dbg(oxu, "bogus dev %p speed %d\n", urb->dev, urb->dev->speed); | 1477 | oxu_dbg(oxu, "bogus dev %p speed %d\n", urb->dev, urb->dev->speed); |
| 1478 | done: | 1478 | done: |
| 1479 | qh_put(qh); | 1479 | qh_put(qh); |
| 1480 | return NULL; | 1480 | return NULL; |
| 1481 | } | 1481 | } |
| 1482 | 1482 | ||
| 1483 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ | 1483 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ |
| 1484 | 1484 | ||
| 1485 | /* init as live, toggle clear, advance to dummy */ | 1485 | /* init as live, toggle clear, advance to dummy */ |
| 1486 | qh->qh_state = QH_STATE_IDLE; | 1486 | qh->qh_state = QH_STATE_IDLE; |
| 1487 | qh->hw_info1 = cpu_to_le32(info1); | 1487 | qh->hw_info1 = cpu_to_le32(info1); |
| 1488 | qh->hw_info2 = cpu_to_le32(info2); | 1488 | qh->hw_info2 = cpu_to_le32(info2); |
| 1489 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1); | 1489 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1); |
| 1490 | qh_refresh(oxu, qh); | 1490 | qh_refresh(oxu, qh); |
| 1491 | return qh; | 1491 | return qh; |
| 1492 | } | 1492 | } |
| 1493 | 1493 | ||
| 1494 | /* Move qh (and its qtds) onto async queue; maybe enable queue. | 1494 | /* Move qh (and its qtds) onto async queue; maybe enable queue. |
| 1495 | */ | 1495 | */ |
| 1496 | static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh) | 1496 | static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 1497 | { | 1497 | { |
| 1498 | __le32 dma = QH_NEXT(qh->qh_dma); | 1498 | __le32 dma = QH_NEXT(qh->qh_dma); |
| 1499 | struct ehci_qh *head; | 1499 | struct ehci_qh *head; |
| 1500 | 1500 | ||
| 1501 | /* (re)start the async schedule? */ | 1501 | /* (re)start the async schedule? */ |
| 1502 | head = oxu->async; | 1502 | head = oxu->async; |
| 1503 | timer_action_done(oxu, TIMER_ASYNC_OFF); | 1503 | timer_action_done(oxu, TIMER_ASYNC_OFF); |
| 1504 | if (!head->qh_next.qh) { | 1504 | if (!head->qh_next.qh) { |
| 1505 | u32 cmd = readl(&oxu->regs->command); | 1505 | u32 cmd = readl(&oxu->regs->command); |
| 1506 | 1506 | ||
| 1507 | if (!(cmd & CMD_ASE)) { | 1507 | if (!(cmd & CMD_ASE)) { |
| 1508 | /* in case a clear of CMD_ASE didn't take yet */ | 1508 | /* in case a clear of CMD_ASE didn't take yet */ |
| 1509 | (void)handshake(oxu, &oxu->regs->status, | 1509 | (void)handshake(oxu, &oxu->regs->status, |
| 1510 | STS_ASS, 0, 150); | 1510 | STS_ASS, 0, 150); |
| 1511 | cmd |= CMD_ASE | CMD_RUN; | 1511 | cmd |= CMD_ASE | CMD_RUN; |
| 1512 | writel(cmd, &oxu->regs->command); | 1512 | writel(cmd, &oxu->regs->command); |
| 1513 | oxu_to_hcd(oxu)->state = HC_STATE_RUNNING; | 1513 | oxu_to_hcd(oxu)->state = HC_STATE_RUNNING; |
| 1514 | /* posted write need not be known to HC yet ... */ | 1514 | /* posted write need not be known to HC yet ... */ |
| 1515 | } | 1515 | } |
| 1516 | } | 1516 | } |
| 1517 | 1517 | ||
| 1518 | /* clear halt and/or toggle; and maybe recover from silicon quirk */ | 1518 | /* clear halt and/or toggle; and maybe recover from silicon quirk */ |
| 1519 | if (qh->qh_state == QH_STATE_IDLE) | 1519 | if (qh->qh_state == QH_STATE_IDLE) |
| 1520 | qh_refresh(oxu, qh); | 1520 | qh_refresh(oxu, qh); |
| 1521 | 1521 | ||
| 1522 | /* splice right after start */ | 1522 | /* splice right after start */ |
| 1523 | qh->qh_next = head->qh_next; | 1523 | qh->qh_next = head->qh_next; |
| 1524 | qh->hw_next = head->hw_next; | 1524 | qh->hw_next = head->hw_next; |
| 1525 | wmb(); | 1525 | wmb(); |
| 1526 | 1526 | ||
| 1527 | head->qh_next.qh = qh; | 1527 | head->qh_next.qh = qh; |
| 1528 | head->hw_next = dma; | 1528 | head->hw_next = dma; |
| 1529 | 1529 | ||
| 1530 | qh->qh_state = QH_STATE_LINKED; | 1530 | qh->qh_state = QH_STATE_LINKED; |
| 1531 | /* qtd completions reported later by interrupt */ | 1531 | /* qtd completions reported later by interrupt */ |
| 1532 | } | 1532 | } |
| 1533 | 1533 | ||
| 1534 | #define QH_ADDR_MASK cpu_to_le32(0x7f) | 1534 | #define QH_ADDR_MASK cpu_to_le32(0x7f) |
| 1535 | 1535 | ||
| 1536 | /* | 1536 | /* |
| 1537 | * For control/bulk/interrupt, return QH with these TDs appended. | 1537 | * For control/bulk/interrupt, return QH with these TDs appended. |
| 1538 | * Allocates and initializes the QH if necessary. | 1538 | * Allocates and initializes the QH if necessary. |
| 1539 | * Returns null if it can't allocate a QH it needs to. | 1539 | * Returns null if it can't allocate a QH it needs to. |
| 1540 | * If the QH has TDs (urbs) already, that's great. | 1540 | * If the QH has TDs (urbs) already, that's great. |
| 1541 | */ | 1541 | */ |
| 1542 | static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu, | 1542 | static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu, |
| 1543 | struct urb *urb, struct list_head *qtd_list, | 1543 | struct urb *urb, struct list_head *qtd_list, |
| 1544 | int epnum, void **ptr) | 1544 | int epnum, void **ptr) |
| 1545 | { | 1545 | { |
| 1546 | struct ehci_qh *qh = NULL; | 1546 | struct ehci_qh *qh = NULL; |
| 1547 | 1547 | ||
| 1548 | qh = (struct ehci_qh *) *ptr; | 1548 | qh = (struct ehci_qh *) *ptr; |
| 1549 | if (unlikely(qh == NULL)) { | 1549 | if (unlikely(qh == NULL)) { |
| 1550 | /* can't sleep here, we have oxu->lock... */ | 1550 | /* can't sleep here, we have oxu->lock... */ |
| 1551 | qh = qh_make(oxu, urb, GFP_ATOMIC); | 1551 | qh = qh_make(oxu, urb, GFP_ATOMIC); |
| 1552 | *ptr = qh; | 1552 | *ptr = qh; |
| 1553 | } | 1553 | } |
| 1554 | if (likely(qh != NULL)) { | 1554 | if (likely(qh != NULL)) { |
| 1555 | struct ehci_qtd *qtd; | 1555 | struct ehci_qtd *qtd; |
| 1556 | 1556 | ||
| 1557 | if (unlikely(list_empty(qtd_list))) | 1557 | if (unlikely(list_empty(qtd_list))) |
| 1558 | qtd = NULL; | 1558 | qtd = NULL; |
| 1559 | else | 1559 | else |
| 1560 | qtd = list_entry(qtd_list->next, struct ehci_qtd, | 1560 | qtd = list_entry(qtd_list->next, struct ehci_qtd, |
| 1561 | qtd_list); | 1561 | qtd_list); |
| 1562 | 1562 | ||
| 1563 | /* control qh may need patching ... */ | 1563 | /* control qh may need patching ... */ |
| 1564 | if (unlikely(epnum == 0)) { | 1564 | if (unlikely(epnum == 0)) { |
| 1565 | 1565 | ||
| 1566 | /* usb_reset_device() briefly reverts to address 0 */ | 1566 | /* usb_reset_device() briefly reverts to address 0 */ |
| 1567 | if (usb_pipedevice(urb->pipe) == 0) | 1567 | if (usb_pipedevice(urb->pipe) == 0) |
| 1568 | qh->hw_info1 &= ~QH_ADDR_MASK; | 1568 | qh->hw_info1 &= ~QH_ADDR_MASK; |
| 1569 | } | 1569 | } |
| 1570 | 1570 | ||
| 1571 | /* just one way to queue requests: swap with the dummy qtd. | 1571 | /* just one way to queue requests: swap with the dummy qtd. |
| 1572 | * only hc or qh_refresh() ever modify the overlay. | 1572 | * only hc or qh_refresh() ever modify the overlay. |
| 1573 | */ | 1573 | */ |
| 1574 | if (likely(qtd != NULL)) { | 1574 | if (likely(qtd != NULL)) { |
| 1575 | struct ehci_qtd *dummy; | 1575 | struct ehci_qtd *dummy; |
| 1576 | dma_addr_t dma; | 1576 | dma_addr_t dma; |
| 1577 | __le32 token; | 1577 | __le32 token; |
| 1578 | 1578 | ||
| 1579 | /* to avoid racing the HC, use the dummy td instead of | 1579 | /* to avoid racing the HC, use the dummy td instead of |
| 1580 | * the first td of our list (becomes new dummy). both | 1580 | * the first td of our list (becomes new dummy). both |
| 1581 | * tds stay deactivated until we're done, when the | 1581 | * tds stay deactivated until we're done, when the |
| 1582 | * HC is allowed to fetch the old dummy (4.10.2). | 1582 | * HC is allowed to fetch the old dummy (4.10.2). |
| 1583 | */ | 1583 | */ |
| 1584 | token = qtd->hw_token; | 1584 | token = qtd->hw_token; |
| 1585 | qtd->hw_token = HALT_BIT; | 1585 | qtd->hw_token = HALT_BIT; |
| 1586 | wmb(); | 1586 | wmb(); |
| 1587 | dummy = qh->dummy; | 1587 | dummy = qh->dummy; |
| 1588 | 1588 | ||
| 1589 | dma = dummy->qtd_dma; | 1589 | dma = dummy->qtd_dma; |
| 1590 | *dummy = *qtd; | 1590 | *dummy = *qtd; |
| 1591 | dummy->qtd_dma = dma; | 1591 | dummy->qtd_dma = dma; |
| 1592 | 1592 | ||
| 1593 | list_del(&qtd->qtd_list); | 1593 | list_del(&qtd->qtd_list); |
| 1594 | list_add(&dummy->qtd_list, qtd_list); | 1594 | list_add(&dummy->qtd_list, qtd_list); |
| 1595 | list_splice(qtd_list, qh->qtd_list.prev); | 1595 | list_splice(qtd_list, qh->qtd_list.prev); |
| 1596 | 1596 | ||
| 1597 | ehci_qtd_init(qtd, qtd->qtd_dma); | 1597 | ehci_qtd_init(qtd, qtd->qtd_dma); |
| 1598 | qh->dummy = qtd; | 1598 | qh->dummy = qtd; |
| 1599 | 1599 | ||
| 1600 | /* hc must see the new dummy at list end */ | 1600 | /* hc must see the new dummy at list end */ |
| 1601 | dma = qtd->qtd_dma; | 1601 | dma = qtd->qtd_dma; |
| 1602 | qtd = list_entry(qh->qtd_list.prev, | 1602 | qtd = list_entry(qh->qtd_list.prev, |
| 1603 | struct ehci_qtd, qtd_list); | 1603 | struct ehci_qtd, qtd_list); |
| 1604 | qtd->hw_next = QTD_NEXT(dma); | 1604 | qtd->hw_next = QTD_NEXT(dma); |
| 1605 | 1605 | ||
| 1606 | /* let the hc process these next qtds */ | 1606 | /* let the hc process these next qtds */ |
| 1607 | dummy->hw_token = (token & ~(0x80)); | 1607 | dummy->hw_token = (token & ~(0x80)); |
| 1608 | wmb(); | 1608 | wmb(); |
| 1609 | dummy->hw_token = token; | 1609 | dummy->hw_token = token; |
| 1610 | 1610 | ||
| 1611 | urb->hcpriv = qh_get(qh); | 1611 | urb->hcpriv = qh_get(qh); |
| 1612 | } | 1612 | } |
| 1613 | } | 1613 | } |
| 1614 | return qh; | 1614 | return qh; |
| 1615 | } | 1615 | } |
| 1616 | 1616 | ||
| 1617 | static int submit_async(struct oxu_hcd *oxu, struct urb *urb, | 1617 | static int submit_async(struct oxu_hcd *oxu, struct urb *urb, |
| 1618 | struct list_head *qtd_list, gfp_t mem_flags) | 1618 | struct list_head *qtd_list, gfp_t mem_flags) |
| 1619 | { | 1619 | { |
| 1620 | struct ehci_qtd *qtd; | 1620 | struct ehci_qtd *qtd; |
| 1621 | int epnum; | 1621 | int epnum; |
| 1622 | unsigned long flags; | 1622 | unsigned long flags; |
| 1623 | struct ehci_qh *qh = NULL; | 1623 | struct ehci_qh *qh = NULL; |
| 1624 | int rc = 0; | 1624 | int rc = 0; |
| 1625 | 1625 | ||
| 1626 | qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list); | 1626 | qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list); |
| 1627 | epnum = urb->ep->desc.bEndpointAddress; | 1627 | epnum = urb->ep->desc.bEndpointAddress; |
| 1628 | 1628 | ||
| 1629 | #ifdef OXU_URB_TRACE | 1629 | #ifdef OXU_URB_TRACE |
| 1630 | oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", | 1630 | oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", |
| 1631 | __func__, urb->dev->devpath, urb, | 1631 | __func__, urb->dev->devpath, urb, |
| 1632 | epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", | 1632 | epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", |
| 1633 | urb->transfer_buffer_length, | 1633 | urb->transfer_buffer_length, |
| 1634 | qtd, urb->ep->hcpriv); | 1634 | qtd, urb->ep->hcpriv); |
| 1635 | #endif | 1635 | #endif |
| 1636 | 1636 | ||
| 1637 | spin_lock_irqsave(&oxu->lock, flags); | 1637 | spin_lock_irqsave(&oxu->lock, flags); |
| 1638 | if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) { | 1638 | if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) { |
| 1639 | rc = -ESHUTDOWN; | 1639 | rc = -ESHUTDOWN; |
| 1640 | goto done; | 1640 | goto done; |
| 1641 | } | 1641 | } |
| 1642 | 1642 | ||
| 1643 | qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv); | 1643 | qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv); |
| 1644 | if (unlikely(qh == NULL)) { | 1644 | if (unlikely(qh == NULL)) { |
| 1645 | rc = -ENOMEM; | 1645 | rc = -ENOMEM; |
| 1646 | goto done; | 1646 | goto done; |
| 1647 | } | 1647 | } |
| 1648 | 1648 | ||
| 1649 | /* Control/bulk operations through TTs don't need scheduling, | 1649 | /* Control/bulk operations through TTs don't need scheduling, |
| 1650 | * the HC and TT handle it when the TT has a buffer ready. | 1650 | * the HC and TT handle it when the TT has a buffer ready. |
| 1651 | */ | 1651 | */ |
| 1652 | if (likely(qh->qh_state == QH_STATE_IDLE)) | 1652 | if (likely(qh->qh_state == QH_STATE_IDLE)) |
| 1653 | qh_link_async(oxu, qh_get(qh)); | 1653 | qh_link_async(oxu, qh_get(qh)); |
| 1654 | done: | 1654 | done: |
| 1655 | spin_unlock_irqrestore(&oxu->lock, flags); | 1655 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 1656 | if (unlikely(qh == NULL)) | 1656 | if (unlikely(qh == NULL)) |
| 1657 | qtd_list_free(oxu, urb, qtd_list); | 1657 | qtd_list_free(oxu, urb, qtd_list); |
| 1658 | return rc; | 1658 | return rc; |
| 1659 | } | 1659 | } |
| 1660 | 1660 | ||
| 1661 | /* The async qh for the qtds being reclaimed are now unlinked from the HC */ | 1661 | /* The async qh for the qtds being reclaimed are now unlinked from the HC */ |
| 1662 | 1662 | ||
| 1663 | static void end_unlink_async(struct oxu_hcd *oxu) | 1663 | static void end_unlink_async(struct oxu_hcd *oxu) |
| 1664 | { | 1664 | { |
| 1665 | struct ehci_qh *qh = oxu->reclaim; | 1665 | struct ehci_qh *qh = oxu->reclaim; |
| 1666 | struct ehci_qh *next; | 1666 | struct ehci_qh *next; |
| 1667 | 1667 | ||
| 1668 | timer_action_done(oxu, TIMER_IAA_WATCHDOG); | 1668 | timer_action_done(oxu, TIMER_IAA_WATCHDOG); |
| 1669 | 1669 | ||
| 1670 | qh->qh_state = QH_STATE_IDLE; | 1670 | qh->qh_state = QH_STATE_IDLE; |
| 1671 | qh->qh_next.qh = NULL; | 1671 | qh->qh_next.qh = NULL; |
| 1672 | qh_put(qh); /* refcount from reclaim */ | 1672 | qh_put(qh); /* refcount from reclaim */ |
| 1673 | 1673 | ||
| 1674 | /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ | 1674 | /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ |
| 1675 | next = qh->reclaim; | 1675 | next = qh->reclaim; |
| 1676 | oxu->reclaim = next; | 1676 | oxu->reclaim = next; |
| 1677 | oxu->reclaim_ready = 0; | 1677 | oxu->reclaim_ready = 0; |
| 1678 | qh->reclaim = NULL; | 1678 | qh->reclaim = NULL; |
| 1679 | 1679 | ||
| 1680 | qh_completions(oxu, qh); | 1680 | qh_completions(oxu, qh); |
| 1681 | 1681 | ||
| 1682 | if (!list_empty(&qh->qtd_list) | 1682 | if (!list_empty(&qh->qtd_list) |
| 1683 | && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) | 1683 | && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) |
| 1684 | qh_link_async(oxu, qh); | 1684 | qh_link_async(oxu, qh); |
| 1685 | else { | 1685 | else { |
| 1686 | qh_put(qh); /* refcount from async list */ | 1686 | qh_put(qh); /* refcount from async list */ |
| 1687 | 1687 | ||
| 1688 | /* it's not free to turn the async schedule on/off; leave it | 1688 | /* it's not free to turn the async schedule on/off; leave it |
| 1689 | * active but idle for a while once it empties. | 1689 | * active but idle for a while once it empties. |
| 1690 | */ | 1690 | */ |
| 1691 | if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) | 1691 | if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) |
| 1692 | && oxu->async->qh_next.qh == NULL) | 1692 | && oxu->async->qh_next.qh == NULL) |
| 1693 | timer_action(oxu, TIMER_ASYNC_OFF); | 1693 | timer_action(oxu, TIMER_ASYNC_OFF); |
| 1694 | } | 1694 | } |
| 1695 | 1695 | ||
| 1696 | if (next) { | 1696 | if (next) { |
| 1697 | oxu->reclaim = NULL; | 1697 | oxu->reclaim = NULL; |
| 1698 | start_unlink_async(oxu, next); | 1698 | start_unlink_async(oxu, next); |
| 1699 | } | 1699 | } |
| 1700 | } | 1700 | } |
| 1701 | 1701 | ||
| 1702 | /* makes sure the async qh will become idle */ | 1702 | /* makes sure the async qh will become idle */ |
| 1703 | /* caller must own oxu->lock */ | 1703 | /* caller must own oxu->lock */ |
| 1704 | 1704 | ||
| 1705 | static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh) | 1705 | static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 1706 | { | 1706 | { |
| 1707 | int cmd = readl(&oxu->regs->command); | 1707 | int cmd = readl(&oxu->regs->command); |
| 1708 | struct ehci_qh *prev; | 1708 | struct ehci_qh *prev; |
| 1709 | 1709 | ||
| 1710 | #ifdef DEBUG | 1710 | #ifdef DEBUG |
| 1711 | assert_spin_locked(&oxu->lock); | 1711 | assert_spin_locked(&oxu->lock); |
| 1712 | if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED | 1712 | if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED |
| 1713 | && qh->qh_state != QH_STATE_UNLINK_WAIT)) | 1713 | && qh->qh_state != QH_STATE_UNLINK_WAIT)) |
| 1714 | BUG(); | 1714 | BUG(); |
| 1715 | #endif | 1715 | #endif |
| 1716 | 1716 | ||
| 1717 | /* stop async schedule right now? */ | 1717 | /* stop async schedule right now? */ |
| 1718 | if (unlikely(qh == oxu->async)) { | 1718 | if (unlikely(qh == oxu->async)) { |
| 1719 | /* can't get here without STS_ASS set */ | 1719 | /* can't get here without STS_ASS set */ |
| 1720 | if (oxu_to_hcd(oxu)->state != HC_STATE_HALT | 1720 | if (oxu_to_hcd(oxu)->state != HC_STATE_HALT |
| 1721 | && !oxu->reclaim) { | 1721 | && !oxu->reclaim) { |
| 1722 | /* ... and CMD_IAAD clear */ | 1722 | /* ... and CMD_IAAD clear */ |
| 1723 | writel(cmd & ~CMD_ASE, &oxu->regs->command); | 1723 | writel(cmd & ~CMD_ASE, &oxu->regs->command); |
| 1724 | wmb(); | 1724 | wmb(); |
| 1725 | /* handshake later, if we need to */ | 1725 | /* handshake later, if we need to */ |
| 1726 | timer_action_done(oxu, TIMER_ASYNC_OFF); | 1726 | timer_action_done(oxu, TIMER_ASYNC_OFF); |
| 1727 | } | 1727 | } |
| 1728 | return; | 1728 | return; |
| 1729 | } | 1729 | } |
| 1730 | 1730 | ||
| 1731 | qh->qh_state = QH_STATE_UNLINK; | 1731 | qh->qh_state = QH_STATE_UNLINK; |
| 1732 | oxu->reclaim = qh = qh_get(qh); | 1732 | oxu->reclaim = qh = qh_get(qh); |
| 1733 | 1733 | ||
| 1734 | prev = oxu->async; | 1734 | prev = oxu->async; |
| 1735 | while (prev->qh_next.qh != qh) | 1735 | while (prev->qh_next.qh != qh) |
| 1736 | prev = prev->qh_next.qh; | 1736 | prev = prev->qh_next.qh; |
| 1737 | 1737 | ||
| 1738 | prev->hw_next = qh->hw_next; | 1738 | prev->hw_next = qh->hw_next; |
| 1739 | prev->qh_next = qh->qh_next; | 1739 | prev->qh_next = qh->qh_next; |
| 1740 | wmb(); | 1740 | wmb(); |
| 1741 | 1741 | ||
| 1742 | if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) { | 1742 | if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) { |
| 1743 | /* if (unlikely(qh->reclaim != 0)) | 1743 | /* if (unlikely(qh->reclaim != 0)) |
| 1744 | * this will recurse, probably not much | 1744 | * this will recurse, probably not much |
| 1745 | */ | 1745 | */ |
| 1746 | end_unlink_async(oxu); | 1746 | end_unlink_async(oxu); |
| 1747 | return; | 1747 | return; |
| 1748 | } | 1748 | } |
| 1749 | 1749 | ||
| 1750 | oxu->reclaim_ready = 0; | 1750 | oxu->reclaim_ready = 0; |
| 1751 | cmd |= CMD_IAAD; | 1751 | cmd |= CMD_IAAD; |
| 1752 | writel(cmd, &oxu->regs->command); | 1752 | writel(cmd, &oxu->regs->command); |
| 1753 | (void) readl(&oxu->regs->command); | 1753 | (void) readl(&oxu->regs->command); |
| 1754 | timer_action(oxu, TIMER_IAA_WATCHDOG); | 1754 | timer_action(oxu, TIMER_IAA_WATCHDOG); |
| 1755 | } | 1755 | } |
| 1756 | 1756 | ||
| 1757 | static void scan_async(struct oxu_hcd *oxu) | 1757 | static void scan_async(struct oxu_hcd *oxu) |
| 1758 | { | 1758 | { |
| 1759 | struct ehci_qh *qh; | 1759 | struct ehci_qh *qh; |
| 1760 | enum ehci_timer_action action = TIMER_IO_WATCHDOG; | 1760 | enum ehci_timer_action action = TIMER_IO_WATCHDOG; |
| 1761 | 1761 | ||
| 1762 | if (!++(oxu->stamp)) | 1762 | if (!++(oxu->stamp)) |
| 1763 | oxu->stamp++; | 1763 | oxu->stamp++; |
| 1764 | timer_action_done(oxu, TIMER_ASYNC_SHRINK); | 1764 | timer_action_done(oxu, TIMER_ASYNC_SHRINK); |
| 1765 | rescan: | 1765 | rescan: |
| 1766 | qh = oxu->async->qh_next.qh; | 1766 | qh = oxu->async->qh_next.qh; |
| 1767 | if (likely(qh != NULL)) { | 1767 | if (likely(qh != NULL)) { |
| 1768 | do { | 1768 | do { |
| 1769 | /* clean any finished work for this qh */ | 1769 | /* clean any finished work for this qh */ |
| 1770 | if (!list_empty(&qh->qtd_list) | 1770 | if (!list_empty(&qh->qtd_list) |
| 1771 | && qh->stamp != oxu->stamp) { | 1771 | && qh->stamp != oxu->stamp) { |
| 1772 | int temp; | 1772 | int temp; |
| 1773 | 1773 | ||
| 1774 | /* unlinks could happen here; completion | 1774 | /* unlinks could happen here; completion |
| 1775 | * reporting drops the lock. rescan using | 1775 | * reporting drops the lock. rescan using |
| 1776 | * the latest schedule, but don't rescan | 1776 | * the latest schedule, but don't rescan |
| 1777 | * qhs we already finished (no looping). | 1777 | * qhs we already finished (no looping). |
| 1778 | */ | 1778 | */ |
| 1779 | qh = qh_get(qh); | 1779 | qh = qh_get(qh); |
| 1780 | qh->stamp = oxu->stamp; | 1780 | qh->stamp = oxu->stamp; |
| 1781 | temp = qh_completions(oxu, qh); | 1781 | temp = qh_completions(oxu, qh); |
| 1782 | qh_put(qh); | 1782 | qh_put(qh); |
| 1783 | if (temp != 0) | 1783 | if (temp != 0) |
| 1784 | goto rescan; | 1784 | goto rescan; |
| 1785 | } | 1785 | } |
| 1786 | 1786 | ||
| 1787 | /* unlink idle entries, reducing HC PCI usage as well | 1787 | /* unlink idle entries, reducing HC PCI usage as well |
| 1788 | * as HCD schedule-scanning costs. delay for any qh | 1788 | * as HCD schedule-scanning costs. delay for any qh |
| 1789 | * we just scanned, there's a not-unusual case that it | 1789 | * we just scanned, there's a not-unusual case that it |
| 1790 | * doesn't stay idle for long. | 1790 | * doesn't stay idle for long. |
| 1791 | * (plus, avoids some kind of re-activation race.) | 1791 | * (plus, avoids some kind of re-activation race.) |
| 1792 | */ | 1792 | */ |
| 1793 | if (list_empty(&qh->qtd_list)) { | 1793 | if (list_empty(&qh->qtd_list)) { |
| 1794 | if (qh->stamp == oxu->stamp) | 1794 | if (qh->stamp == oxu->stamp) |
| 1795 | action = TIMER_ASYNC_SHRINK; | 1795 | action = TIMER_ASYNC_SHRINK; |
| 1796 | else if (!oxu->reclaim | 1796 | else if (!oxu->reclaim |
| 1797 | && qh->qh_state == QH_STATE_LINKED) | 1797 | && qh->qh_state == QH_STATE_LINKED) |
| 1798 | start_unlink_async(oxu, qh); | 1798 | start_unlink_async(oxu, qh); |
| 1799 | } | 1799 | } |
| 1800 | 1800 | ||
| 1801 | qh = qh->qh_next.qh; | 1801 | qh = qh->qh_next.qh; |
| 1802 | } while (qh); | 1802 | } while (qh); |
| 1803 | } | 1803 | } |
| 1804 | if (action == TIMER_ASYNC_SHRINK) | 1804 | if (action == TIMER_ASYNC_SHRINK) |
| 1805 | timer_action(oxu, TIMER_ASYNC_SHRINK); | 1805 | timer_action(oxu, TIMER_ASYNC_SHRINK); |
| 1806 | } | 1806 | } |
| 1807 | 1807 | ||
| 1808 | /* | 1808 | /* |
| 1809 | * periodic_next_shadow - return "next" pointer on shadow list | 1809 | * periodic_next_shadow - return "next" pointer on shadow list |
| 1810 | * @periodic: host pointer to qh/itd/sitd | 1810 | * @periodic: host pointer to qh/itd/sitd |
| 1811 | * @tag: hardware tag for type of this record | 1811 | * @tag: hardware tag for type of this record |
| 1812 | */ | 1812 | */ |
| 1813 | static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic, | 1813 | static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic, |
| 1814 | __le32 tag) | 1814 | __le32 tag) |
| 1815 | { | 1815 | { |
| 1816 | switch (tag) { | 1816 | switch (tag) { |
| 1817 | default: | 1817 | default: |
| 1818 | case Q_TYPE_QH: | 1818 | case Q_TYPE_QH: |
| 1819 | return &periodic->qh->qh_next; | 1819 | return &periodic->qh->qh_next; |
| 1820 | } | 1820 | } |
| 1821 | } | 1821 | } |
| 1822 | 1822 | ||
| 1823 | /* caller must hold oxu->lock */ | 1823 | /* caller must hold oxu->lock */ |
| 1824 | static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr) | 1824 | static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr) |
| 1825 | { | 1825 | { |
| 1826 | union ehci_shadow *prev_p = &oxu->pshadow[frame]; | 1826 | union ehci_shadow *prev_p = &oxu->pshadow[frame]; |
| 1827 | __le32 *hw_p = &oxu->periodic[frame]; | 1827 | __le32 *hw_p = &oxu->periodic[frame]; |
| 1828 | union ehci_shadow here = *prev_p; | 1828 | union ehci_shadow here = *prev_p; |
| 1829 | 1829 | ||
| 1830 | /* find predecessor of "ptr"; hw and shadow lists are in sync */ | 1830 | /* find predecessor of "ptr"; hw and shadow lists are in sync */ |
| 1831 | while (here.ptr && here.ptr != ptr) { | 1831 | while (here.ptr && here.ptr != ptr) { |
| 1832 | prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p)); | 1832 | prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p)); |
| 1833 | hw_p = here.hw_next; | 1833 | hw_p = here.hw_next; |
| 1834 | here = *prev_p; | 1834 | here = *prev_p; |
| 1835 | } | 1835 | } |
| 1836 | /* an interrupt entry (at list end) could have been shared */ | 1836 | /* an interrupt entry (at list end) could have been shared */ |
| 1837 | if (!here.ptr) | 1837 | if (!here.ptr) |
| 1838 | return; | 1838 | return; |
| 1839 | 1839 | ||
| 1840 | /* update shadow and hardware lists ... the old "next" pointers | 1840 | /* update shadow and hardware lists ... the old "next" pointers |
| 1841 | * from ptr may still be in use, the caller updates them. | 1841 | * from ptr may still be in use, the caller updates them. |
| 1842 | */ | 1842 | */ |
| 1843 | *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p)); | 1843 | *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p)); |
| 1844 | *hw_p = *here.hw_next; | 1844 | *hw_p = *here.hw_next; |
| 1845 | } | 1845 | } |
| 1846 | 1846 | ||
| 1847 | /* how many of the uframe's 125 usecs are allocated? */ | 1847 | /* how many of the uframe's 125 usecs are allocated? */ |
| 1848 | static unsigned short periodic_usecs(struct oxu_hcd *oxu, | 1848 | static unsigned short periodic_usecs(struct oxu_hcd *oxu, |
| 1849 | unsigned frame, unsigned uframe) | 1849 | unsigned frame, unsigned uframe) |
| 1850 | { | 1850 | { |
| 1851 | __le32 *hw_p = &oxu->periodic[frame]; | 1851 | __le32 *hw_p = &oxu->periodic[frame]; |
| 1852 | union ehci_shadow *q = &oxu->pshadow[frame]; | 1852 | union ehci_shadow *q = &oxu->pshadow[frame]; |
| 1853 | unsigned usecs = 0; | 1853 | unsigned usecs = 0; |
| 1854 | 1854 | ||
| 1855 | while (q->ptr) { | 1855 | while (q->ptr) { |
| 1856 | switch (Q_NEXT_TYPE(*hw_p)) { | 1856 | switch (Q_NEXT_TYPE(*hw_p)) { |
| 1857 | case Q_TYPE_QH: | 1857 | case Q_TYPE_QH: |
| 1858 | default: | 1858 | default: |
| 1859 | /* is it in the S-mask? */ | 1859 | /* is it in the S-mask? */ |
| 1860 | if (q->qh->hw_info2 & cpu_to_le32(1 << uframe)) | 1860 | if (q->qh->hw_info2 & cpu_to_le32(1 << uframe)) |
| 1861 | usecs += q->qh->usecs; | 1861 | usecs += q->qh->usecs; |
| 1862 | /* ... or C-mask? */ | 1862 | /* ... or C-mask? */ |
| 1863 | if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe))) | 1863 | if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe))) |
| 1864 | usecs += q->qh->c_usecs; | 1864 | usecs += q->qh->c_usecs; |
| 1865 | hw_p = &q->qh->hw_next; | 1865 | hw_p = &q->qh->hw_next; |
| 1866 | q = &q->qh->qh_next; | 1866 | q = &q->qh->qh_next; |
| 1867 | break; | 1867 | break; |
| 1868 | } | 1868 | } |
| 1869 | } | 1869 | } |
| 1870 | #ifdef DEBUG | 1870 | #ifdef DEBUG |
| 1871 | if (usecs > 100) | 1871 | if (usecs > 100) |
| 1872 | oxu_err(oxu, "uframe %d sched overrun: %d usecs\n", | 1872 | oxu_err(oxu, "uframe %d sched overrun: %d usecs\n", |
| 1873 | frame * 8 + uframe, usecs); | 1873 | frame * 8 + uframe, usecs); |
| 1874 | #endif | 1874 | #endif |
| 1875 | return usecs; | 1875 | return usecs; |
| 1876 | } | 1876 | } |
| 1877 | 1877 | ||
| 1878 | static int enable_periodic(struct oxu_hcd *oxu) | 1878 | static int enable_periodic(struct oxu_hcd *oxu) |
| 1879 | { | 1879 | { |
| 1880 | u32 cmd; | 1880 | u32 cmd; |
| 1881 | int status; | 1881 | int status; |
| 1882 | 1882 | ||
| 1883 | /* did clearing PSE did take effect yet? | 1883 | /* did clearing PSE did take effect yet? |
| 1884 | * takes effect only at frame boundaries... | 1884 | * takes effect only at frame boundaries... |
| 1885 | */ | 1885 | */ |
| 1886 | status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125); | 1886 | status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125); |
| 1887 | if (status != 0) { | 1887 | if (status != 0) { |
| 1888 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 1888 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
| 1889 | usb_hc_died(oxu_to_hcd(oxu)); | 1889 | usb_hc_died(oxu_to_hcd(oxu)); |
| 1890 | return status; | 1890 | return status; |
| 1891 | } | 1891 | } |
| 1892 | 1892 | ||
| 1893 | cmd = readl(&oxu->regs->command) | CMD_PSE; | 1893 | cmd = readl(&oxu->regs->command) | CMD_PSE; |
| 1894 | writel(cmd, &oxu->regs->command); | 1894 | writel(cmd, &oxu->regs->command); |
| 1895 | /* posted write ... PSS happens later */ | 1895 | /* posted write ... PSS happens later */ |
| 1896 | oxu_to_hcd(oxu)->state = HC_STATE_RUNNING; | 1896 | oxu_to_hcd(oxu)->state = HC_STATE_RUNNING; |
| 1897 | 1897 | ||
| 1898 | /* make sure ehci_work scans these */ | 1898 | /* make sure ehci_work scans these */ |
| 1899 | oxu->next_uframe = readl(&oxu->regs->frame_index) | 1899 | oxu->next_uframe = readl(&oxu->regs->frame_index) |
| 1900 | % (oxu->periodic_size << 3); | 1900 | % (oxu->periodic_size << 3); |
| 1901 | return 0; | 1901 | return 0; |
| 1902 | } | 1902 | } |
| 1903 | 1903 | ||
| 1904 | static int disable_periodic(struct oxu_hcd *oxu) | 1904 | static int disable_periodic(struct oxu_hcd *oxu) |
| 1905 | { | 1905 | { |
| 1906 | u32 cmd; | 1906 | u32 cmd; |
| 1907 | int status; | 1907 | int status; |
| 1908 | 1908 | ||
| 1909 | /* did setting PSE not take effect yet? | 1909 | /* did setting PSE not take effect yet? |
| 1910 | * takes effect only at frame boundaries... | 1910 | * takes effect only at frame boundaries... |
| 1911 | */ | 1911 | */ |
| 1912 | status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125); | 1912 | status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125); |
| 1913 | if (status != 0) { | 1913 | if (status != 0) { |
| 1914 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; | 1914 | oxu_to_hcd(oxu)->state = HC_STATE_HALT; |
| 1915 | usb_hc_died(oxu_to_hcd(oxu)); | 1915 | usb_hc_died(oxu_to_hcd(oxu)); |
| 1916 | return status; | 1916 | return status; |
| 1917 | } | 1917 | } |
| 1918 | 1918 | ||
| 1919 | cmd = readl(&oxu->regs->command) & ~CMD_PSE; | 1919 | cmd = readl(&oxu->regs->command) & ~CMD_PSE; |
| 1920 | writel(cmd, &oxu->regs->command); | 1920 | writel(cmd, &oxu->regs->command); |
| 1921 | /* posted write ... */ | 1921 | /* posted write ... */ |
| 1922 | 1922 | ||
| 1923 | oxu->next_uframe = -1; | 1923 | oxu->next_uframe = -1; |
| 1924 | return 0; | 1924 | return 0; |
| 1925 | } | 1925 | } |
| 1926 | 1926 | ||
| 1927 | /* periodic schedule slots have iso tds (normal or split) first, then a | 1927 | /* periodic schedule slots have iso tds (normal or split) first, then a |
| 1928 | * sparse tree for active interrupt transfers. | 1928 | * sparse tree for active interrupt transfers. |
| 1929 | * | 1929 | * |
| 1930 | * this just links in a qh; caller guarantees uframe masks are set right. | 1930 | * this just links in a qh; caller guarantees uframe masks are set right. |
| 1931 | * no FSTN support (yet; oxu 0.96+) | 1931 | * no FSTN support (yet; oxu 0.96+) |
| 1932 | */ | 1932 | */ |
| 1933 | static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh) | 1933 | static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 1934 | { | 1934 | { |
| 1935 | unsigned i; | 1935 | unsigned i; |
| 1936 | unsigned period = qh->period; | 1936 | unsigned period = qh->period; |
| 1937 | 1937 | ||
| 1938 | dev_dbg(&qh->dev->dev, | 1938 | dev_dbg(&qh->dev->dev, |
| 1939 | "link qh%d-%04x/%p start %d [%d/%d us]\n", | 1939 | "link qh%d-%04x/%p start %d [%d/%d us]\n", |
| 1940 | period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK), | 1940 | period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK), |
| 1941 | qh, qh->start, qh->usecs, qh->c_usecs); | 1941 | qh, qh->start, qh->usecs, qh->c_usecs); |
| 1942 | 1942 | ||
| 1943 | /* high bandwidth, or otherwise every microframe */ | 1943 | /* high bandwidth, or otherwise every microframe */ |
| 1944 | if (period == 0) | 1944 | if (period == 0) |
| 1945 | period = 1; | 1945 | period = 1; |
| 1946 | 1946 | ||
| 1947 | for (i = qh->start; i < oxu->periodic_size; i += period) { | 1947 | for (i = qh->start; i < oxu->periodic_size; i += period) { |
| 1948 | union ehci_shadow *prev = &oxu->pshadow[i]; | 1948 | union ehci_shadow *prev = &oxu->pshadow[i]; |
| 1949 | __le32 *hw_p = &oxu->periodic[i]; | 1949 | __le32 *hw_p = &oxu->periodic[i]; |
| 1950 | union ehci_shadow here = *prev; | 1950 | union ehci_shadow here = *prev; |
| 1951 | __le32 type = 0; | 1951 | __le32 type = 0; |
| 1952 | 1952 | ||
| 1953 | /* skip the iso nodes at list head */ | 1953 | /* skip the iso nodes at list head */ |
| 1954 | while (here.ptr) { | 1954 | while (here.ptr) { |
| 1955 | type = Q_NEXT_TYPE(*hw_p); | 1955 | type = Q_NEXT_TYPE(*hw_p); |
| 1956 | if (type == Q_TYPE_QH) | 1956 | if (type == Q_TYPE_QH) |
| 1957 | break; | 1957 | break; |
| 1958 | prev = periodic_next_shadow(prev, type); | 1958 | prev = periodic_next_shadow(prev, type); |
| 1959 | hw_p = &here.qh->hw_next; | 1959 | hw_p = &here.qh->hw_next; |
| 1960 | here = *prev; | 1960 | here = *prev; |
| 1961 | } | 1961 | } |
| 1962 | 1962 | ||
| 1963 | /* sorting each branch by period (slow-->fast) | 1963 | /* sorting each branch by period (slow-->fast) |
| 1964 | * enables sharing interior tree nodes | 1964 | * enables sharing interior tree nodes |
| 1965 | */ | 1965 | */ |
| 1966 | while (here.ptr && qh != here.qh) { | 1966 | while (here.ptr && qh != here.qh) { |
| 1967 | if (qh->period > here.qh->period) | 1967 | if (qh->period > here.qh->period) |
| 1968 | break; | 1968 | break; |
| 1969 | prev = &here.qh->qh_next; | 1969 | prev = &here.qh->qh_next; |
| 1970 | hw_p = &here.qh->hw_next; | 1970 | hw_p = &here.qh->hw_next; |
| 1971 | here = *prev; | 1971 | here = *prev; |
| 1972 | } | 1972 | } |
| 1973 | /* link in this qh, unless some earlier pass did that */ | 1973 | /* link in this qh, unless some earlier pass did that */ |
| 1974 | if (qh != here.qh) { | 1974 | if (qh != here.qh) { |
| 1975 | qh->qh_next = here; | 1975 | qh->qh_next = here; |
| 1976 | if (here.qh) | 1976 | if (here.qh) |
| 1977 | qh->hw_next = *hw_p; | 1977 | qh->hw_next = *hw_p; |
| 1978 | wmb(); | 1978 | wmb(); |
| 1979 | prev->qh = qh; | 1979 | prev->qh = qh; |
| 1980 | *hw_p = QH_NEXT(qh->qh_dma); | 1980 | *hw_p = QH_NEXT(qh->qh_dma); |
| 1981 | } | 1981 | } |
| 1982 | } | 1982 | } |
| 1983 | qh->qh_state = QH_STATE_LINKED; | 1983 | qh->qh_state = QH_STATE_LINKED; |
| 1984 | qh_get(qh); | 1984 | qh_get(qh); |
| 1985 | 1985 | ||
| 1986 | /* update per-qh bandwidth for usbfs */ | 1986 | /* update per-qh bandwidth for usbfs */ |
| 1987 | oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period | 1987 | oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period |
| 1988 | ? ((qh->usecs + qh->c_usecs) / qh->period) | 1988 | ? ((qh->usecs + qh->c_usecs) / qh->period) |
| 1989 | : (qh->usecs * 8); | 1989 | : (qh->usecs * 8); |
| 1990 | 1990 | ||
| 1991 | /* maybe enable periodic schedule processing */ | 1991 | /* maybe enable periodic schedule processing */ |
| 1992 | if (!oxu->periodic_sched++) | 1992 | if (!oxu->periodic_sched++) |
| 1993 | return enable_periodic(oxu); | 1993 | return enable_periodic(oxu); |
| 1994 | 1994 | ||
| 1995 | return 0; | 1995 | return 0; |
| 1996 | } | 1996 | } |
| 1997 | 1997 | ||
| 1998 | static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh) | 1998 | static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 1999 | { | 1999 | { |
| 2000 | unsigned i; | 2000 | unsigned i; |
| 2001 | unsigned period; | 2001 | unsigned period; |
| 2002 | 2002 | ||
| 2003 | /* FIXME: | 2003 | /* FIXME: |
| 2004 | * IF this isn't high speed | 2004 | * IF this isn't high speed |
| 2005 | * and this qh is active in the current uframe | 2005 | * and this qh is active in the current uframe |
| 2006 | * (and overlay token SplitXstate is false?) | 2006 | * (and overlay token SplitXstate is false?) |
| 2007 | * THEN | 2007 | * THEN |
| 2008 | * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore"); | 2008 | * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore"); |
| 2009 | */ | 2009 | */ |
| 2010 | 2010 | ||
| 2011 | /* high bandwidth, or otherwise part of every microframe */ | 2011 | /* high bandwidth, or otherwise part of every microframe */ |
| 2012 | period = qh->period; | 2012 | period = qh->period; |
| 2013 | if (period == 0) | 2013 | if (period == 0) |
| 2014 | period = 1; | 2014 | period = 1; |
| 2015 | 2015 | ||
| 2016 | for (i = qh->start; i < oxu->periodic_size; i += period) | 2016 | for (i = qh->start; i < oxu->periodic_size; i += period) |
| 2017 | periodic_unlink(oxu, i, qh); | 2017 | periodic_unlink(oxu, i, qh); |
| 2018 | 2018 | ||
| 2019 | /* update per-qh bandwidth for usbfs */ | 2019 | /* update per-qh bandwidth for usbfs */ |
| 2020 | oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period | 2020 | oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period |
| 2021 | ? ((qh->usecs + qh->c_usecs) / qh->period) | 2021 | ? ((qh->usecs + qh->c_usecs) / qh->period) |
| 2022 | : (qh->usecs * 8); | 2022 | : (qh->usecs * 8); |
| 2023 | 2023 | ||
| 2024 | dev_dbg(&qh->dev->dev, | 2024 | dev_dbg(&qh->dev->dev, |
| 2025 | "unlink qh%d-%04x/%p start %d [%d/%d us]\n", | 2025 | "unlink qh%d-%04x/%p start %d [%d/%d us]\n", |
| 2026 | qh->period, | 2026 | qh->period, |
| 2027 | le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK), | 2027 | le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK), |
| 2028 | qh, qh->start, qh->usecs, qh->c_usecs); | 2028 | qh, qh->start, qh->usecs, qh->c_usecs); |
| 2029 | 2029 | ||
| 2030 | /* qh->qh_next still "live" to HC */ | 2030 | /* qh->qh_next still "live" to HC */ |
| 2031 | qh->qh_state = QH_STATE_UNLINK; | 2031 | qh->qh_state = QH_STATE_UNLINK; |
| 2032 | qh->qh_next.ptr = NULL; | 2032 | qh->qh_next.ptr = NULL; |
| 2033 | qh_put(qh); | 2033 | qh_put(qh); |
| 2034 | 2034 | ||
| 2035 | /* maybe turn off periodic schedule */ | 2035 | /* maybe turn off periodic schedule */ |
| 2036 | oxu->periodic_sched--; | 2036 | oxu->periodic_sched--; |
| 2037 | if (!oxu->periodic_sched) | 2037 | if (!oxu->periodic_sched) |
| 2038 | (void) disable_periodic(oxu); | 2038 | (void) disable_periodic(oxu); |
| 2039 | } | 2039 | } |
| 2040 | 2040 | ||
| 2041 | static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh) | 2041 | static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 2042 | { | 2042 | { |
| 2043 | unsigned wait; | 2043 | unsigned wait; |
| 2044 | 2044 | ||
| 2045 | qh_unlink_periodic(oxu, qh); | 2045 | qh_unlink_periodic(oxu, qh); |
| 2046 | 2046 | ||
| 2047 | /* simple/paranoid: always delay, expecting the HC needs to read | 2047 | /* simple/paranoid: always delay, expecting the HC needs to read |
| 2048 | * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and | 2048 | * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and |
| 2049 | * expect hub_wq to clean up after any CSPLITs we won't issue. | 2049 | * expect hub_wq to clean up after any CSPLITs we won't issue. |
| 2050 | * active high speed queues may need bigger delays... | 2050 | * active high speed queues may need bigger delays... |
| 2051 | */ | 2051 | */ |
| 2052 | if (list_empty(&qh->qtd_list) | 2052 | if (list_empty(&qh->qtd_list) |
| 2053 | || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0) | 2053 | || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0) |
| 2054 | wait = 2; | 2054 | wait = 2; |
| 2055 | else | 2055 | else |
| 2056 | wait = 55; /* worst case: 3 * 1024 */ | 2056 | wait = 55; /* worst case: 3 * 1024 */ |
| 2057 | 2057 | ||
| 2058 | udelay(wait); | 2058 | udelay(wait); |
| 2059 | qh->qh_state = QH_STATE_IDLE; | 2059 | qh->qh_state = QH_STATE_IDLE; |
| 2060 | qh->hw_next = EHCI_LIST_END; | 2060 | qh->hw_next = EHCI_LIST_END; |
| 2061 | wmb(); | 2061 | wmb(); |
| 2062 | } | 2062 | } |
| 2063 | 2063 | ||
| 2064 | static int check_period(struct oxu_hcd *oxu, | 2064 | static int check_period(struct oxu_hcd *oxu, |
| 2065 | unsigned frame, unsigned uframe, | 2065 | unsigned frame, unsigned uframe, |
| 2066 | unsigned period, unsigned usecs) | 2066 | unsigned period, unsigned usecs) |
| 2067 | { | 2067 | { |
| 2068 | int claimed; | 2068 | int claimed; |
| 2069 | 2069 | ||
| 2070 | /* complete split running into next frame? | 2070 | /* complete split running into next frame? |
| 2071 | * given FSTN support, we could sometimes check... | 2071 | * given FSTN support, we could sometimes check... |
| 2072 | */ | 2072 | */ |
| 2073 | if (uframe >= 8) | 2073 | if (uframe >= 8) |
| 2074 | return 0; | 2074 | return 0; |
| 2075 | 2075 | ||
| 2076 | /* | 2076 | /* |
| 2077 | * 80% periodic == 100 usec/uframe available | 2077 | * 80% periodic == 100 usec/uframe available |
| 2078 | * convert "usecs we need" to "max already claimed" | 2078 | * convert "usecs we need" to "max already claimed" |
| 2079 | */ | 2079 | */ |
| 2080 | usecs = 100 - usecs; | 2080 | usecs = 100 - usecs; |
| 2081 | 2081 | ||
| 2082 | /* we "know" 2 and 4 uframe intervals were rejected; so | 2082 | /* we "know" 2 and 4 uframe intervals were rejected; so |
| 2083 | * for period 0, check _every_ microframe in the schedule. | 2083 | * for period 0, check _every_ microframe in the schedule. |
| 2084 | */ | 2084 | */ |
| 2085 | if (unlikely(period == 0)) { | 2085 | if (unlikely(period == 0)) { |
| 2086 | do { | 2086 | do { |
| 2087 | for (uframe = 0; uframe < 7; uframe++) { | 2087 | for (uframe = 0; uframe < 7; uframe++) { |
| 2088 | claimed = periodic_usecs(oxu, frame, uframe); | 2088 | claimed = periodic_usecs(oxu, frame, uframe); |
| 2089 | if (claimed > usecs) | 2089 | if (claimed > usecs) |
| 2090 | return 0; | 2090 | return 0; |
| 2091 | } | 2091 | } |
| 2092 | } while ((frame += 1) < oxu->periodic_size); | 2092 | } while ((frame += 1) < oxu->periodic_size); |
| 2093 | 2093 | ||
| 2094 | /* just check the specified uframe, at that period */ | 2094 | /* just check the specified uframe, at that period */ |
| 2095 | } else { | 2095 | } else { |
| 2096 | do { | 2096 | do { |
| 2097 | claimed = periodic_usecs(oxu, frame, uframe); | 2097 | claimed = periodic_usecs(oxu, frame, uframe); |
| 2098 | if (claimed > usecs) | 2098 | if (claimed > usecs) |
| 2099 | return 0; | 2099 | return 0; |
| 2100 | } while ((frame += period) < oxu->periodic_size); | 2100 | } while ((frame += period) < oxu->periodic_size); |
| 2101 | } | 2101 | } |
| 2102 | 2102 | ||
| 2103 | return 1; | 2103 | return 1; |
| 2104 | } | 2104 | } |
| 2105 | 2105 | ||
| 2106 | static int check_intr_schedule(struct oxu_hcd *oxu, | 2106 | static int check_intr_schedule(struct oxu_hcd *oxu, |
| 2107 | unsigned frame, unsigned uframe, | 2107 | unsigned frame, unsigned uframe, |
| 2108 | const struct ehci_qh *qh, __le32 *c_maskp) | 2108 | const struct ehci_qh *qh, __le32 *c_maskp) |
| 2109 | { | 2109 | { |
| 2110 | int retval = -ENOSPC; | 2110 | int retval = -ENOSPC; |
| 2111 | 2111 | ||
| 2112 | if (qh->c_usecs && uframe >= 6) /* FSTN territory? */ | 2112 | if (qh->c_usecs && uframe >= 6) /* FSTN territory? */ |
| 2113 | goto done; | 2113 | goto done; |
| 2114 | 2114 | ||
| 2115 | if (!check_period(oxu, frame, uframe, qh->period, qh->usecs)) | 2115 | if (!check_period(oxu, frame, uframe, qh->period, qh->usecs)) |
| 2116 | goto done; | 2116 | goto done; |
| 2117 | if (!qh->c_usecs) { | 2117 | if (!qh->c_usecs) { |
| 2118 | retval = 0; | 2118 | retval = 0; |
| 2119 | *c_maskp = 0; | 2119 | *c_maskp = 0; |
| 2120 | goto done; | 2120 | goto done; |
| 2121 | } | 2121 | } |
| 2122 | 2122 | ||
| 2123 | done: | 2123 | done: |
| 2124 | return retval; | 2124 | return retval; |
| 2125 | } | 2125 | } |
| 2126 | 2126 | ||
| 2127 | /* "first fit" scheduling policy used the first time through, | 2127 | /* "first fit" scheduling policy used the first time through, |
| 2128 | * or when the previous schedule slot can't be re-used. | 2128 | * or when the previous schedule slot can't be re-used. |
| 2129 | */ | 2129 | */ |
| 2130 | static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh) | 2130 | static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 2131 | { | 2131 | { |
| 2132 | int status; | 2132 | int status; |
| 2133 | unsigned uframe; | 2133 | unsigned uframe; |
| 2134 | __le32 c_mask; | 2134 | __le32 c_mask; |
| 2135 | unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */ | 2135 | unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */ |
| 2136 | 2136 | ||
| 2137 | qh_refresh(oxu, qh); | 2137 | qh_refresh(oxu, qh); |
| 2138 | qh->hw_next = EHCI_LIST_END; | 2138 | qh->hw_next = EHCI_LIST_END; |
| 2139 | frame = qh->start; | 2139 | frame = qh->start; |
| 2140 | 2140 | ||
| 2141 | /* reuse the previous schedule slots, if we can */ | 2141 | /* reuse the previous schedule slots, if we can */ |
| 2142 | if (frame < qh->period) { | 2142 | if (frame < qh->period) { |
| 2143 | uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK); | 2143 | uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK); |
| 2144 | status = check_intr_schedule(oxu, frame, --uframe, | 2144 | status = check_intr_schedule(oxu, frame, --uframe, |
| 2145 | qh, &c_mask); | 2145 | qh, &c_mask); |
| 2146 | } else { | 2146 | } else { |
| 2147 | uframe = 0; | 2147 | uframe = 0; |
| 2148 | c_mask = 0; | 2148 | c_mask = 0; |
| 2149 | status = -ENOSPC; | 2149 | status = -ENOSPC; |
| 2150 | } | 2150 | } |
| 2151 | 2151 | ||
| 2152 | /* else scan the schedule to find a group of slots such that all | 2152 | /* else scan the schedule to find a group of slots such that all |
| 2153 | * uframes have enough periodic bandwidth available. | 2153 | * uframes have enough periodic bandwidth available. |
| 2154 | */ | 2154 | */ |
| 2155 | if (status) { | 2155 | if (status) { |
| 2156 | /* "normal" case, uframing flexible except with splits */ | 2156 | /* "normal" case, uframing flexible except with splits */ |
| 2157 | if (qh->period) { | 2157 | if (qh->period) { |
| 2158 | frame = qh->period - 1; | 2158 | frame = qh->period - 1; |
| 2159 | do { | 2159 | do { |
| 2160 | for (uframe = 0; uframe < 8; uframe++) { | 2160 | for (uframe = 0; uframe < 8; uframe++) { |
| 2161 | status = check_intr_schedule(oxu, | 2161 | status = check_intr_schedule(oxu, |
| 2162 | frame, uframe, qh, | 2162 | frame, uframe, qh, |
| 2163 | &c_mask); | 2163 | &c_mask); |
| 2164 | if (status == 0) | 2164 | if (status == 0) |
| 2165 | break; | 2165 | break; |
| 2166 | } | 2166 | } |
| 2167 | } while (status && frame--); | 2167 | } while (status && frame--); |
| 2168 | 2168 | ||
| 2169 | /* qh->period == 0 means every uframe */ | 2169 | /* qh->period == 0 means every uframe */ |
| 2170 | } else { | 2170 | } else { |
| 2171 | frame = 0; | 2171 | frame = 0; |
| 2172 | status = check_intr_schedule(oxu, 0, 0, qh, &c_mask); | 2172 | status = check_intr_schedule(oxu, 0, 0, qh, &c_mask); |
| 2173 | } | 2173 | } |
| 2174 | if (status) | 2174 | if (status) |
| 2175 | goto done; | 2175 | goto done; |
| 2176 | qh->start = frame; | 2176 | qh->start = frame; |
| 2177 | 2177 | ||
| 2178 | /* reset S-frame and (maybe) C-frame masks */ | 2178 | /* reset S-frame and (maybe) C-frame masks */ |
| 2179 | qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK)); | 2179 | qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK)); |
| 2180 | qh->hw_info2 |= qh->period | 2180 | qh->hw_info2 |= qh->period |
| 2181 | ? cpu_to_le32(1 << uframe) | 2181 | ? cpu_to_le32(1 << uframe) |
| 2182 | : cpu_to_le32(QH_SMASK); | 2182 | : cpu_to_le32(QH_SMASK); |
| 2183 | qh->hw_info2 |= c_mask; | 2183 | qh->hw_info2 |= c_mask; |
| 2184 | } else | 2184 | } else |
| 2185 | oxu_dbg(oxu, "reused qh %p schedule\n", qh); | 2185 | oxu_dbg(oxu, "reused qh %p schedule\n", qh); |
| 2186 | 2186 | ||
| 2187 | /* stuff into the periodic schedule */ | 2187 | /* stuff into the periodic schedule */ |
| 2188 | status = qh_link_periodic(oxu, qh); | 2188 | status = qh_link_periodic(oxu, qh); |
| 2189 | done: | 2189 | done: |
| 2190 | return status; | 2190 | return status; |
| 2191 | } | 2191 | } |
| 2192 | 2192 | ||
| 2193 | static int intr_submit(struct oxu_hcd *oxu, struct urb *urb, | 2193 | static int intr_submit(struct oxu_hcd *oxu, struct urb *urb, |
| 2194 | struct list_head *qtd_list, gfp_t mem_flags) | 2194 | struct list_head *qtd_list, gfp_t mem_flags) |
| 2195 | { | 2195 | { |
| 2196 | unsigned epnum; | 2196 | unsigned epnum; |
| 2197 | unsigned long flags; | 2197 | unsigned long flags; |
| 2198 | struct ehci_qh *qh; | 2198 | struct ehci_qh *qh; |
| 2199 | int status = 0; | 2199 | int status = 0; |
| 2200 | struct list_head empty; | 2200 | struct list_head empty; |
| 2201 | 2201 | ||
| 2202 | /* get endpoint and transfer/schedule data */ | 2202 | /* get endpoint and transfer/schedule data */ |
| 2203 | epnum = urb->ep->desc.bEndpointAddress; | 2203 | epnum = urb->ep->desc.bEndpointAddress; |
| 2204 | 2204 | ||
| 2205 | spin_lock_irqsave(&oxu->lock, flags); | 2205 | spin_lock_irqsave(&oxu->lock, flags); |
| 2206 | 2206 | ||
| 2207 | if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) { | 2207 | if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) { |
| 2208 | status = -ESHUTDOWN; | 2208 | status = -ESHUTDOWN; |
| 2209 | goto done; | 2209 | goto done; |
| 2210 | } | 2210 | } |
| 2211 | 2211 | ||
| 2212 | /* get qh and force any scheduling errors */ | 2212 | /* get qh and force any scheduling errors */ |
| 2213 | INIT_LIST_HEAD(&empty); | 2213 | INIT_LIST_HEAD(&empty); |
| 2214 | qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv); | 2214 | qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv); |
| 2215 | if (qh == NULL) { | 2215 | if (qh == NULL) { |
| 2216 | status = -ENOMEM; | 2216 | status = -ENOMEM; |
| 2217 | goto done; | 2217 | goto done; |
| 2218 | } | 2218 | } |
| 2219 | if (qh->qh_state == QH_STATE_IDLE) { | 2219 | if (qh->qh_state == QH_STATE_IDLE) { |
| 2220 | status = qh_schedule(oxu, qh); | 2220 | status = qh_schedule(oxu, qh); |
| 2221 | if (status != 0) | 2221 | if (status != 0) |
| 2222 | goto done; | 2222 | goto done; |
| 2223 | } | 2223 | } |
| 2224 | 2224 | ||
| 2225 | /* then queue the urb's tds to the qh */ | 2225 | /* then queue the urb's tds to the qh */ |
| 2226 | qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv); | 2226 | qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv); |
| 2227 | BUG_ON(qh == NULL); | 2227 | BUG_ON(qh == NULL); |
| 2228 | 2228 | ||
| 2229 | /* ... update usbfs periodic stats */ | 2229 | /* ... update usbfs periodic stats */ |
| 2230 | oxu_to_hcd(oxu)->self.bandwidth_int_reqs++; | 2230 | oxu_to_hcd(oxu)->self.bandwidth_int_reqs++; |
| 2231 | 2231 | ||
| 2232 | done: | 2232 | done: |
| 2233 | spin_unlock_irqrestore(&oxu->lock, flags); | 2233 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 2234 | if (status) | 2234 | if (status) |
| 2235 | qtd_list_free(oxu, urb, qtd_list); | 2235 | qtd_list_free(oxu, urb, qtd_list); |
| 2236 | 2236 | ||
| 2237 | return status; | 2237 | return status; |
| 2238 | } | 2238 | } |
| 2239 | 2239 | ||
| 2240 | static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb, | 2240 | static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb, |
| 2241 | gfp_t mem_flags) | 2241 | gfp_t mem_flags) |
| 2242 | { | 2242 | { |
| 2243 | oxu_dbg(oxu, "iso support is missing!\n"); | 2243 | oxu_dbg(oxu, "iso support is missing!\n"); |
| 2244 | return -ENOSYS; | 2244 | return -ENOSYS; |
| 2245 | } | 2245 | } |
| 2246 | 2246 | ||
| 2247 | static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb, | 2247 | static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb, |
| 2248 | gfp_t mem_flags) | 2248 | gfp_t mem_flags) |
| 2249 | { | 2249 | { |
| 2250 | oxu_dbg(oxu, "split iso support is missing!\n"); | 2250 | oxu_dbg(oxu, "split iso support is missing!\n"); |
| 2251 | return -ENOSYS; | 2251 | return -ENOSYS; |
| 2252 | } | 2252 | } |
| 2253 | 2253 | ||
| 2254 | static void scan_periodic(struct oxu_hcd *oxu) | 2254 | static void scan_periodic(struct oxu_hcd *oxu) |
| 2255 | { | 2255 | { |
| 2256 | unsigned frame, clock, now_uframe, mod; | 2256 | unsigned frame, clock, now_uframe, mod; |
| 2257 | unsigned modified; | 2257 | unsigned modified; |
| 2258 | 2258 | ||
| 2259 | mod = oxu->periodic_size << 3; | 2259 | mod = oxu->periodic_size << 3; |
| 2260 | 2260 | ||
| 2261 | /* | 2261 | /* |
| 2262 | * When running, scan from last scan point up to "now" | 2262 | * When running, scan from last scan point up to "now" |
| 2263 | * else clean up by scanning everything that's left. | 2263 | * else clean up by scanning everything that's left. |
| 2264 | * Touches as few pages as possible: cache-friendly. | 2264 | * Touches as few pages as possible: cache-friendly. |
| 2265 | */ | 2265 | */ |
| 2266 | now_uframe = oxu->next_uframe; | 2266 | now_uframe = oxu->next_uframe; |
| 2267 | if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) | 2267 | if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) |
| 2268 | clock = readl(&oxu->regs->frame_index); | 2268 | clock = readl(&oxu->regs->frame_index); |
| 2269 | else | 2269 | else |
| 2270 | clock = now_uframe + mod - 1; | 2270 | clock = now_uframe + mod - 1; |
| 2271 | clock %= mod; | 2271 | clock %= mod; |
| 2272 | 2272 | ||
| 2273 | for (;;) { | 2273 | for (;;) { |
| 2274 | union ehci_shadow q, *q_p; | 2274 | union ehci_shadow q, *q_p; |
| 2275 | __le32 type, *hw_p; | 2275 | __le32 type, *hw_p; |
| 2276 | unsigned uframes; | 2276 | unsigned uframes; |
| 2277 | 2277 | ||
| 2278 | /* don't scan past the live uframe */ | 2278 | /* don't scan past the live uframe */ |
| 2279 | frame = now_uframe >> 3; | 2279 | frame = now_uframe >> 3; |
| 2280 | if (frame == (clock >> 3)) | 2280 | if (frame == (clock >> 3)) |
| 2281 | uframes = now_uframe & 0x07; | 2281 | uframes = now_uframe & 0x07; |
| 2282 | else { | 2282 | else { |
| 2283 | /* safe to scan the whole frame at once */ | 2283 | /* safe to scan the whole frame at once */ |
| 2284 | now_uframe |= 0x07; | 2284 | now_uframe |= 0x07; |
| 2285 | uframes = 8; | 2285 | uframes = 8; |
| 2286 | } | 2286 | } |
| 2287 | 2287 | ||
| 2288 | restart: | 2288 | restart: |
| 2289 | /* scan each element in frame's queue for completions */ | 2289 | /* scan each element in frame's queue for completions */ |
| 2290 | q_p = &oxu->pshadow[frame]; | 2290 | q_p = &oxu->pshadow[frame]; |
| 2291 | hw_p = &oxu->periodic[frame]; | 2291 | hw_p = &oxu->periodic[frame]; |
| 2292 | q.ptr = q_p->ptr; | 2292 | q.ptr = q_p->ptr; |
| 2293 | type = Q_NEXT_TYPE(*hw_p); | 2293 | type = Q_NEXT_TYPE(*hw_p); |
| 2294 | modified = 0; | 2294 | modified = 0; |
| 2295 | 2295 | ||
| 2296 | while (q.ptr != NULL) { | 2296 | while (q.ptr != NULL) { |
| 2297 | union ehci_shadow temp; | 2297 | union ehci_shadow temp; |
| 2298 | int live; | 2298 | int live; |
| 2299 | 2299 | ||
| 2300 | live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state); | 2300 | live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state); |
| 2301 | switch (type) { | 2301 | switch (type) { |
| 2302 | case Q_TYPE_QH: | 2302 | case Q_TYPE_QH: |
| 2303 | /* handle any completions */ | 2303 | /* handle any completions */ |
| 2304 | temp.qh = qh_get(q.qh); | 2304 | temp.qh = qh_get(q.qh); |
| 2305 | type = Q_NEXT_TYPE(q.qh->hw_next); | 2305 | type = Q_NEXT_TYPE(q.qh->hw_next); |
| 2306 | q = q.qh->qh_next; | 2306 | q = q.qh->qh_next; |
| 2307 | modified = qh_completions(oxu, temp.qh); | 2307 | modified = qh_completions(oxu, temp.qh); |
| 2308 | if (unlikely(list_empty(&temp.qh->qtd_list))) | 2308 | if (unlikely(list_empty(&temp.qh->qtd_list))) |
| 2309 | intr_deschedule(oxu, temp.qh); | 2309 | intr_deschedule(oxu, temp.qh); |
| 2310 | qh_put(temp.qh); | 2310 | qh_put(temp.qh); |
| 2311 | break; | 2311 | break; |
| 2312 | default: | 2312 | default: |
| 2313 | oxu_dbg(oxu, "corrupt type %d frame %d shadow %p\n", | 2313 | oxu_dbg(oxu, "corrupt type %d frame %d shadow %p\n", |
| 2314 | type, frame, q.ptr); | 2314 | type, frame, q.ptr); |
| 2315 | q.ptr = NULL; | 2315 | q.ptr = NULL; |
| 2316 | } | 2316 | } |
| 2317 | 2317 | ||
| 2318 | /* assume completion callbacks modify the queue */ | 2318 | /* assume completion callbacks modify the queue */ |
| 2319 | if (unlikely(modified)) | 2319 | if (unlikely(modified)) |
| 2320 | goto restart; | 2320 | goto restart; |
| 2321 | } | 2321 | } |
| 2322 | 2322 | ||
| 2323 | /* Stop when we catch up to the HC */ | 2323 | /* Stop when we catch up to the HC */ |
| 2324 | 2324 | ||
| 2325 | /* FIXME: this assumes we won't get lapped when | 2325 | /* FIXME: this assumes we won't get lapped when |
| 2326 | * latencies climb; that should be rare, but... | 2326 | * latencies climb; that should be rare, but... |
| 2327 | * detect it, and just go all the way around. | 2327 | * detect it, and just go all the way around. |
| 2328 | * FLR might help detect this case, so long as latencies | 2328 | * FLR might help detect this case, so long as latencies |
| 2329 | * don't exceed periodic_size msec (default 1.024 sec). | 2329 | * don't exceed periodic_size msec (default 1.024 sec). |
| 2330 | */ | 2330 | */ |
| 2331 | 2331 | ||
| 2332 | /* FIXME: likewise assumes HC doesn't halt mid-scan */ | 2332 | /* FIXME: likewise assumes HC doesn't halt mid-scan */ |
| 2333 | 2333 | ||
| 2334 | if (now_uframe == clock) { | 2334 | if (now_uframe == clock) { |
| 2335 | unsigned now; | 2335 | unsigned now; |
| 2336 | 2336 | ||
| 2337 | if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) | 2337 | if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) |
| 2338 | break; | 2338 | break; |
| 2339 | oxu->next_uframe = now_uframe; | 2339 | oxu->next_uframe = now_uframe; |
| 2340 | now = readl(&oxu->regs->frame_index) % mod; | 2340 | now = readl(&oxu->regs->frame_index) % mod; |
| 2341 | if (now_uframe == now) | 2341 | if (now_uframe == now) |
| 2342 | break; | 2342 | break; |
| 2343 | 2343 | ||
| 2344 | /* rescan the rest of this frame, then ... */ | 2344 | /* rescan the rest of this frame, then ... */ |
| 2345 | clock = now; | 2345 | clock = now; |
| 2346 | } else { | 2346 | } else { |
| 2347 | now_uframe++; | 2347 | now_uframe++; |
| 2348 | now_uframe %= mod; | 2348 | now_uframe %= mod; |
| 2349 | } | 2349 | } |
| 2350 | } | 2350 | } |
| 2351 | } | 2351 | } |
| 2352 | 2352 | ||
| 2353 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. | 2353 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
| 2354 | * The firmware seems to think that powering off is a wakeup event! | 2354 | * The firmware seems to think that powering off is a wakeup event! |
| 2355 | * This routine turns off remote wakeup and everything else, on all ports. | 2355 | * This routine turns off remote wakeup and everything else, on all ports. |
| 2356 | */ | 2356 | */ |
| 2357 | static void ehci_turn_off_all_ports(struct oxu_hcd *oxu) | 2357 | static void ehci_turn_off_all_ports(struct oxu_hcd *oxu) |
| 2358 | { | 2358 | { |
| 2359 | int port = HCS_N_PORTS(oxu->hcs_params); | 2359 | int port = HCS_N_PORTS(oxu->hcs_params); |
| 2360 | 2360 | ||
| 2361 | while (port--) | 2361 | while (port--) |
| 2362 | writel(PORT_RWC_BITS, &oxu->regs->port_status[port]); | 2362 | writel(PORT_RWC_BITS, &oxu->regs->port_status[port]); |
| 2363 | } | 2363 | } |
| 2364 | 2364 | ||
| 2365 | static void ehci_port_power(struct oxu_hcd *oxu, int is_on) | 2365 | static void ehci_port_power(struct oxu_hcd *oxu, int is_on) |
| 2366 | { | 2366 | { |
| 2367 | unsigned port; | 2367 | unsigned port; |
| 2368 | 2368 | ||
| 2369 | if (!HCS_PPC(oxu->hcs_params)) | 2369 | if (!HCS_PPC(oxu->hcs_params)) |
| 2370 | return; | 2370 | return; |
| 2371 | 2371 | ||
| 2372 | oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down"); | 2372 | oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down"); |
| 2373 | for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; ) | 2373 | for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; ) |
| 2374 | (void) oxu_hub_control(oxu_to_hcd(oxu), | 2374 | (void) oxu_hub_control(oxu_to_hcd(oxu), |
| 2375 | is_on ? SetPortFeature : ClearPortFeature, | 2375 | is_on ? SetPortFeature : ClearPortFeature, |
| 2376 | USB_PORT_FEAT_POWER, | 2376 | USB_PORT_FEAT_POWER, |
| 2377 | port--, NULL, 0); | 2377 | port--, NULL, 0); |
| 2378 | msleep(20); | 2378 | msleep(20); |
| 2379 | } | 2379 | } |
| 2380 | 2380 | ||
| 2381 | /* Called from some interrupts, timers, and so on. | 2381 | /* Called from some interrupts, timers, and so on. |
| 2382 | * It calls driver completion functions, after dropping oxu->lock. | 2382 | * It calls driver completion functions, after dropping oxu->lock. |
| 2383 | */ | 2383 | */ |
| 2384 | static void ehci_work(struct oxu_hcd *oxu) | 2384 | static void ehci_work(struct oxu_hcd *oxu) |
| 2385 | { | 2385 | { |
| 2386 | timer_action_done(oxu, TIMER_IO_WATCHDOG); | 2386 | timer_action_done(oxu, TIMER_IO_WATCHDOG); |
| 2387 | if (oxu->reclaim_ready) | 2387 | if (oxu->reclaim_ready) |
| 2388 | end_unlink_async(oxu); | 2388 | end_unlink_async(oxu); |
| 2389 | 2389 | ||
| 2390 | /* another CPU may drop oxu->lock during a schedule scan while | 2390 | /* another CPU may drop oxu->lock during a schedule scan while |
| 2391 | * it reports urb completions. this flag guards against bogus | 2391 | * it reports urb completions. this flag guards against bogus |
| 2392 | * attempts at re-entrant schedule scanning. | 2392 | * attempts at re-entrant schedule scanning. |
| 2393 | */ | 2393 | */ |
| 2394 | if (oxu->scanning) | 2394 | if (oxu->scanning) |
| 2395 | return; | 2395 | return; |
| 2396 | oxu->scanning = 1; | 2396 | oxu->scanning = 1; |
| 2397 | scan_async(oxu); | 2397 | scan_async(oxu); |
| 2398 | if (oxu->next_uframe != -1) | 2398 | if (oxu->next_uframe != -1) |
| 2399 | scan_periodic(oxu); | 2399 | scan_periodic(oxu); |
| 2400 | oxu->scanning = 0; | 2400 | oxu->scanning = 0; |
| 2401 | 2401 | ||
| 2402 | /* the IO watchdog guards against hardware or driver bugs that | 2402 | /* the IO watchdog guards against hardware or driver bugs that |
| 2403 | * misplace IRQs, and should let us run completely without IRQs. | 2403 | * misplace IRQs, and should let us run completely without IRQs. |
| 2404 | * such lossage has been observed on both VT6202 and VT8235. | 2404 | * such lossage has been observed on both VT6202 and VT8235. |
| 2405 | */ | 2405 | */ |
| 2406 | if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && | 2406 | if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && |
| 2407 | (oxu->async->qh_next.ptr != NULL || | 2407 | (oxu->async->qh_next.ptr != NULL || |
| 2408 | oxu->periodic_sched != 0)) | 2408 | oxu->periodic_sched != 0)) |
| 2409 | timer_action(oxu, TIMER_IO_WATCHDOG); | 2409 | timer_action(oxu, TIMER_IO_WATCHDOG); |
| 2410 | } | 2410 | } |
| 2411 | 2411 | ||
| 2412 | static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh) | 2412 | static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh) |
| 2413 | { | 2413 | { |
| 2414 | /* if we need to use IAA and it's busy, defer */ | 2414 | /* if we need to use IAA and it's busy, defer */ |
| 2415 | if (qh->qh_state == QH_STATE_LINKED | 2415 | if (qh->qh_state == QH_STATE_LINKED |
| 2416 | && oxu->reclaim | 2416 | && oxu->reclaim |
| 2417 | && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) { | 2417 | && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) { |
| 2418 | struct ehci_qh *last; | 2418 | struct ehci_qh *last; |
| 2419 | 2419 | ||
| 2420 | for (last = oxu->reclaim; | 2420 | for (last = oxu->reclaim; |
| 2421 | last->reclaim; | 2421 | last->reclaim; |
| 2422 | last = last->reclaim) | 2422 | last = last->reclaim) |
| 2423 | continue; | 2423 | continue; |
| 2424 | qh->qh_state = QH_STATE_UNLINK_WAIT; | 2424 | qh->qh_state = QH_STATE_UNLINK_WAIT; |
| 2425 | last->reclaim = qh; | 2425 | last->reclaim = qh; |
| 2426 | 2426 | ||
| 2427 | /* bypass IAA if the hc can't care */ | 2427 | /* bypass IAA if the hc can't care */ |
| 2428 | } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim) | 2428 | } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim) |
| 2429 | end_unlink_async(oxu); | 2429 | end_unlink_async(oxu); |
| 2430 | 2430 | ||
| 2431 | /* something else might have unlinked the qh by now */ | 2431 | /* something else might have unlinked the qh by now */ |
| 2432 | if (qh->qh_state == QH_STATE_LINKED) | 2432 | if (qh->qh_state == QH_STATE_LINKED) |
| 2433 | start_unlink_async(oxu, qh); | 2433 | start_unlink_async(oxu, qh); |
| 2434 | } | 2434 | } |
| 2435 | 2435 | ||
| 2436 | /* | 2436 | /* |
| 2437 | * USB host controller methods | 2437 | * USB host controller methods |
| 2438 | */ | 2438 | */ |
| 2439 | 2439 | ||
| 2440 | static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd) | 2440 | static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd) |
| 2441 | { | 2441 | { |
| 2442 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2442 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2443 | u32 status, pcd_status = 0; | 2443 | u32 status, pcd_status = 0; |
| 2444 | int bh; | 2444 | int bh; |
| 2445 | 2445 | ||
| 2446 | spin_lock(&oxu->lock); | 2446 | spin_lock(&oxu->lock); |
| 2447 | 2447 | ||
| 2448 | status = readl(&oxu->regs->status); | 2448 | status = readl(&oxu->regs->status); |
| 2449 | 2449 | ||
| 2450 | /* e.g. cardbus physical eject */ | 2450 | /* e.g. cardbus physical eject */ |
| 2451 | if (status == ~(u32) 0) { | 2451 | if (status == ~(u32) 0) { |
| 2452 | oxu_dbg(oxu, "device removed\n"); | 2452 | oxu_dbg(oxu, "device removed\n"); |
| 2453 | goto dead; | 2453 | goto dead; |
| 2454 | } | 2454 | } |
| 2455 | 2455 | ||
| 2456 | /* Shared IRQ? */ | 2456 | /* Shared IRQ? */ |
| 2457 | status &= INTR_MASK; | 2457 | status &= INTR_MASK; |
| 2458 | if (!status || unlikely(hcd->state == HC_STATE_HALT)) { | 2458 | if (!status || unlikely(hcd->state == HC_STATE_HALT)) { |
| 2459 | spin_unlock(&oxu->lock); | 2459 | spin_unlock(&oxu->lock); |
| 2460 | return IRQ_NONE; | 2460 | return IRQ_NONE; |
| 2461 | } | 2461 | } |
| 2462 | 2462 | ||
| 2463 | /* clear (just) interrupts */ | 2463 | /* clear (just) interrupts */ |
| 2464 | writel(status, &oxu->regs->status); | 2464 | writel(status, &oxu->regs->status); |
| 2465 | readl(&oxu->regs->command); /* unblock posted write */ | 2465 | readl(&oxu->regs->command); /* unblock posted write */ |
| 2466 | bh = 0; | 2466 | bh = 0; |
| 2467 | 2467 | ||
| 2468 | #ifdef OXU_VERBOSE_DEBUG | 2468 | #ifdef OXU_VERBOSE_DEBUG |
| 2469 | /* unrequested/ignored: Frame List Rollover */ | 2469 | /* unrequested/ignored: Frame List Rollover */ |
| 2470 | dbg_status(oxu, "irq", status); | 2470 | dbg_status(oxu, "irq", status); |
| 2471 | #endif | 2471 | #endif |
| 2472 | 2472 | ||
| 2473 | /* INT, ERR, and IAA interrupt rates can be throttled */ | 2473 | /* INT, ERR, and IAA interrupt rates can be throttled */ |
| 2474 | 2474 | ||
| 2475 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | 2475 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ |
| 2476 | if (likely((status & (STS_INT|STS_ERR)) != 0)) | 2476 | if (likely((status & (STS_INT|STS_ERR)) != 0)) |
| 2477 | bh = 1; | 2477 | bh = 1; |
| 2478 | 2478 | ||
| 2479 | /* complete the unlinking of some qh [4.15.2.3] */ | 2479 | /* complete the unlinking of some qh [4.15.2.3] */ |
| 2480 | if (status & STS_IAA) { | 2480 | if (status & STS_IAA) { |
| 2481 | oxu->reclaim_ready = 1; | 2481 | oxu->reclaim_ready = 1; |
| 2482 | bh = 1; | 2482 | bh = 1; |
| 2483 | } | 2483 | } |
| 2484 | 2484 | ||
| 2485 | /* remote wakeup [4.3.1] */ | 2485 | /* remote wakeup [4.3.1] */ |
| 2486 | if (status & STS_PCD) { | 2486 | if (status & STS_PCD) { |
| 2487 | unsigned i = HCS_N_PORTS(oxu->hcs_params); | 2487 | unsigned i = HCS_N_PORTS(oxu->hcs_params); |
| 2488 | pcd_status = status; | 2488 | pcd_status = status; |
| 2489 | 2489 | ||
| 2490 | /* resume root hub? */ | 2490 | /* resume root hub? */ |
| 2491 | if (!(readl(&oxu->regs->command) & CMD_RUN)) | 2491 | if (!(readl(&oxu->regs->command) & CMD_RUN)) |
| 2492 | usb_hcd_resume_root_hub(hcd); | 2492 | usb_hcd_resume_root_hub(hcd); |
| 2493 | 2493 | ||
| 2494 | while (i--) { | 2494 | while (i--) { |
| 2495 | int pstatus = readl(&oxu->regs->port_status[i]); | 2495 | int pstatus = readl(&oxu->regs->port_status[i]); |
| 2496 | 2496 | ||
| 2497 | if (pstatus & PORT_OWNER) | 2497 | if (pstatus & PORT_OWNER) |
| 2498 | continue; | 2498 | continue; |
| 2499 | if (!(pstatus & PORT_RESUME) | 2499 | if (!(pstatus & PORT_RESUME) |
| 2500 | || oxu->reset_done[i] != 0) | 2500 | || oxu->reset_done[i] != 0) |
| 2501 | continue; | 2501 | continue; |
| 2502 | 2502 | ||
| 2503 | /* start 20 msec resume signaling from this port, | 2503 | /* start 20 msec resume signaling from this port, |
| 2504 | * and make hub_wq collect PORT_STAT_C_SUSPEND to | 2504 | * and make hub_wq collect PORT_STAT_C_SUSPEND to |
| 2505 | * stop that signaling. | 2505 | * stop that signaling. |
| 2506 | */ | 2506 | */ |
| 2507 | oxu->reset_done[i] = jiffies + msecs_to_jiffies(20); | 2507 | oxu->reset_done[i] = jiffies + msecs_to_jiffies(20); |
| 2508 | oxu_dbg(oxu, "port %d remote wakeup\n", i + 1); | 2508 | oxu_dbg(oxu, "port %d remote wakeup\n", i + 1); |
| 2509 | mod_timer(&hcd->rh_timer, oxu->reset_done[i]); | 2509 | mod_timer(&hcd->rh_timer, oxu->reset_done[i]); |
| 2510 | } | 2510 | } |
| 2511 | } | 2511 | } |
| 2512 | 2512 | ||
| 2513 | /* PCI errors [4.15.2.4] */ | 2513 | /* PCI errors [4.15.2.4] */ |
| 2514 | if (unlikely((status & STS_FATAL) != 0)) { | 2514 | if (unlikely((status & STS_FATAL) != 0)) { |
| 2515 | /* bogus "fatal" IRQs appear on some chips... why? */ | 2515 | /* bogus "fatal" IRQs appear on some chips... why? */ |
| 2516 | status = readl(&oxu->regs->status); | 2516 | status = readl(&oxu->regs->status); |
| 2517 | dbg_cmd(oxu, "fatal", readl(&oxu->regs->command)); | 2517 | dbg_cmd(oxu, "fatal", readl(&oxu->regs->command)); |
| 2518 | dbg_status(oxu, "fatal", status); | 2518 | dbg_status(oxu, "fatal", status); |
| 2519 | if (status & STS_HALT) { | 2519 | if (status & STS_HALT) { |
| 2520 | oxu_err(oxu, "fatal error\n"); | 2520 | oxu_err(oxu, "fatal error\n"); |
| 2521 | dead: | 2521 | dead: |
| 2522 | ehci_reset(oxu); | 2522 | ehci_reset(oxu); |
| 2523 | writel(0, &oxu->regs->configured_flag); | 2523 | writel(0, &oxu->regs->configured_flag); |
| 2524 | usb_hc_died(hcd); | 2524 | usb_hc_died(hcd); |
| 2525 | /* generic layer kills/unlinks all urbs, then | 2525 | /* generic layer kills/unlinks all urbs, then |
| 2526 | * uses oxu_stop to clean up the rest | 2526 | * uses oxu_stop to clean up the rest |
| 2527 | */ | 2527 | */ |
| 2528 | bh = 1; | 2528 | bh = 1; |
| 2529 | } | 2529 | } |
| 2530 | } | 2530 | } |
| 2531 | 2531 | ||
| 2532 | if (bh) | 2532 | if (bh) |
| 2533 | ehci_work(oxu); | 2533 | ehci_work(oxu); |
| 2534 | spin_unlock(&oxu->lock); | 2534 | spin_unlock(&oxu->lock); |
| 2535 | if (pcd_status & STS_PCD) | 2535 | if (pcd_status & STS_PCD) |
| 2536 | usb_hcd_poll_rh_status(hcd); | 2536 | usb_hcd_poll_rh_status(hcd); |
| 2537 | return IRQ_HANDLED; | 2537 | return IRQ_HANDLED; |
| 2538 | } | 2538 | } |
| 2539 | 2539 | ||
| 2540 | static irqreturn_t oxu_irq(struct usb_hcd *hcd) | 2540 | static irqreturn_t oxu_irq(struct usb_hcd *hcd) |
| 2541 | { | 2541 | { |
| 2542 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2542 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2543 | int ret = IRQ_HANDLED; | 2543 | int ret = IRQ_HANDLED; |
| 2544 | 2544 | ||
| 2545 | u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS); | 2545 | u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS); |
| 2546 | u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET); | 2546 | u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET); |
| 2547 | 2547 | ||
| 2548 | /* Disable all interrupt */ | 2548 | /* Disable all interrupt */ |
| 2549 | oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable); | 2549 | oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable); |
| 2550 | 2550 | ||
| 2551 | if ((oxu->is_otg && (status & OXU_USBOTGI)) || | 2551 | if ((oxu->is_otg && (status & OXU_USBOTGI)) || |
| 2552 | (!oxu->is_otg && (status & OXU_USBSPHI))) | 2552 | (!oxu->is_otg && (status & OXU_USBSPHI))) |
| 2553 | oxu210_hcd_irq(hcd); | 2553 | oxu210_hcd_irq(hcd); |
| 2554 | else | 2554 | else |
| 2555 | ret = IRQ_NONE; | 2555 | ret = IRQ_NONE; |
| 2556 | 2556 | ||
| 2557 | /* Enable all interrupt back */ | 2557 | /* Enable all interrupt back */ |
| 2558 | oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable); | 2558 | oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable); |
| 2559 | 2559 | ||
| 2560 | return ret; | 2560 | return ret; |
| 2561 | } | 2561 | } |
| 2562 | 2562 | ||
| 2563 | static void oxu_watchdog(unsigned long param) | 2563 | static void oxu_watchdog(unsigned long param) |
| 2564 | { | 2564 | { |
| 2565 | struct oxu_hcd *oxu = (struct oxu_hcd *) param; | 2565 | struct oxu_hcd *oxu = (struct oxu_hcd *) param; |
| 2566 | unsigned long flags; | 2566 | unsigned long flags; |
| 2567 | 2567 | ||
| 2568 | spin_lock_irqsave(&oxu->lock, flags); | 2568 | spin_lock_irqsave(&oxu->lock, flags); |
| 2569 | 2569 | ||
| 2570 | /* lost IAA irqs wedge things badly; seen with a vt8235 */ | 2570 | /* lost IAA irqs wedge things badly; seen with a vt8235 */ |
| 2571 | if (oxu->reclaim) { | 2571 | if (oxu->reclaim) { |
| 2572 | u32 status = readl(&oxu->regs->status); | 2572 | u32 status = readl(&oxu->regs->status); |
| 2573 | if (status & STS_IAA) { | 2573 | if (status & STS_IAA) { |
| 2574 | oxu_vdbg(oxu, "lost IAA\n"); | 2574 | oxu_vdbg(oxu, "lost IAA\n"); |
| 2575 | writel(STS_IAA, &oxu->regs->status); | 2575 | writel(STS_IAA, &oxu->regs->status); |
| 2576 | oxu->reclaim_ready = 1; | 2576 | oxu->reclaim_ready = 1; |
| 2577 | } | 2577 | } |
| 2578 | } | 2578 | } |
| 2579 | 2579 | ||
| 2580 | /* stop async processing after it's idled a bit */ | 2580 | /* stop async processing after it's idled a bit */ |
| 2581 | if (test_bit(TIMER_ASYNC_OFF, &oxu->actions)) | 2581 | if (test_bit(TIMER_ASYNC_OFF, &oxu->actions)) |
| 2582 | start_unlink_async(oxu, oxu->async); | 2582 | start_unlink_async(oxu, oxu->async); |
| 2583 | 2583 | ||
| 2584 | /* oxu could run by timer, without IRQs ... */ | 2584 | /* oxu could run by timer, without IRQs ... */ |
| 2585 | ehci_work(oxu); | 2585 | ehci_work(oxu); |
| 2586 | 2586 | ||
| 2587 | spin_unlock_irqrestore(&oxu->lock, flags); | 2587 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 2588 | } | 2588 | } |
| 2589 | 2589 | ||
| 2590 | /* One-time init, only for memory state. | 2590 | /* One-time init, only for memory state. |
| 2591 | */ | 2591 | */ |
| 2592 | static int oxu_hcd_init(struct usb_hcd *hcd) | 2592 | static int oxu_hcd_init(struct usb_hcd *hcd) |
| 2593 | { | 2593 | { |
| 2594 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2594 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2595 | u32 temp; | 2595 | u32 temp; |
| 2596 | int retval; | 2596 | int retval; |
| 2597 | u32 hcc_params; | 2597 | u32 hcc_params; |
| 2598 | 2598 | ||
| 2599 | spin_lock_init(&oxu->lock); | 2599 | spin_lock_init(&oxu->lock); |
| 2600 | 2600 | ||
| 2601 | init_timer(&oxu->watchdog); | 2601 | init_timer(&oxu->watchdog); |
| 2602 | oxu->watchdog.function = oxu_watchdog; | 2602 | oxu->watchdog.function = oxu_watchdog; |
| 2603 | oxu->watchdog.data = (unsigned long) oxu; | 2603 | oxu->watchdog.data = (unsigned long) oxu; |
| 2604 | 2604 | ||
| 2605 | /* | 2605 | /* |
| 2606 | * hw default: 1K periodic list heads, one per frame. | 2606 | * hw default: 1K periodic list heads, one per frame. |
| 2607 | * periodic_size can shrink by USBCMD update if hcc_params allows. | 2607 | * periodic_size can shrink by USBCMD update if hcc_params allows. |
| 2608 | */ | 2608 | */ |
| 2609 | oxu->periodic_size = DEFAULT_I_TDPS; | 2609 | oxu->periodic_size = DEFAULT_I_TDPS; |
| 2610 | retval = ehci_mem_init(oxu, GFP_KERNEL); | 2610 | retval = ehci_mem_init(oxu, GFP_KERNEL); |
| 2611 | if (retval < 0) | 2611 | if (retval < 0) |
| 2612 | return retval; | 2612 | return retval; |
| 2613 | 2613 | ||
| 2614 | /* controllers may cache some of the periodic schedule ... */ | 2614 | /* controllers may cache some of the periodic schedule ... */ |
| 2615 | hcc_params = readl(&oxu->caps->hcc_params); | 2615 | hcc_params = readl(&oxu->caps->hcc_params); |
| 2616 | if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */ | 2616 | if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */ |
| 2617 | oxu->i_thresh = 8; | 2617 | oxu->i_thresh = 8; |
| 2618 | else /* N microframes cached */ | 2618 | else /* N microframes cached */ |
| 2619 | oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); | 2619 | oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
| 2620 | 2620 | ||
| 2621 | oxu->reclaim = NULL; | 2621 | oxu->reclaim = NULL; |
| 2622 | oxu->reclaim_ready = 0; | 2622 | oxu->reclaim_ready = 0; |
| 2623 | oxu->next_uframe = -1; | 2623 | oxu->next_uframe = -1; |
| 2624 | 2624 | ||
| 2625 | /* | 2625 | /* |
| 2626 | * dedicate a qh for the async ring head, since we couldn't unlink | 2626 | * dedicate a qh for the async ring head, since we couldn't unlink |
| 2627 | * a 'real' qh without stopping the async schedule [4.8]. use it | 2627 | * a 'real' qh without stopping the async schedule [4.8]. use it |
| 2628 | * as the 'reclamation list head' too. | 2628 | * as the 'reclamation list head' too. |
| 2629 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | 2629 | * its dummy is used in hw_alt_next of many tds, to prevent the qh |
| 2630 | * from automatically advancing to the next td after short reads. | 2630 | * from automatically advancing to the next td after short reads. |
| 2631 | */ | 2631 | */ |
| 2632 | oxu->async->qh_next.qh = NULL; | 2632 | oxu->async->qh_next.qh = NULL; |
| 2633 | oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma); | 2633 | oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma); |
| 2634 | oxu->async->hw_info1 = cpu_to_le32(QH_HEAD); | 2634 | oxu->async->hw_info1 = cpu_to_le32(QH_HEAD); |
| 2635 | oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT); | 2635 | oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT); |
| 2636 | oxu->async->hw_qtd_next = EHCI_LIST_END; | 2636 | oxu->async->hw_qtd_next = EHCI_LIST_END; |
| 2637 | oxu->async->qh_state = QH_STATE_LINKED; | 2637 | oxu->async->qh_state = QH_STATE_LINKED; |
| 2638 | oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma); | 2638 | oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma); |
| 2639 | 2639 | ||
| 2640 | /* clear interrupt enables, set irq latency */ | 2640 | /* clear interrupt enables, set irq latency */ |
| 2641 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | 2641 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) |
| 2642 | log2_irq_thresh = 0; | 2642 | log2_irq_thresh = 0; |
| 2643 | temp = 1 << (16 + log2_irq_thresh); | 2643 | temp = 1 << (16 + log2_irq_thresh); |
| 2644 | if (HCC_CANPARK(hcc_params)) { | 2644 | if (HCC_CANPARK(hcc_params)) { |
| 2645 | /* HW default park == 3, on hardware that supports it (like | 2645 | /* HW default park == 3, on hardware that supports it (like |
| 2646 | * NVidia and ALI silicon), maximizes throughput on the async | 2646 | * NVidia and ALI silicon), maximizes throughput on the async |
| 2647 | * schedule by avoiding QH fetches between transfers. | 2647 | * schedule by avoiding QH fetches between transfers. |
| 2648 | * | 2648 | * |
| 2649 | * With fast usb storage devices and NForce2, "park" seems to | 2649 | * With fast usb storage devices and NForce2, "park" seems to |
| 2650 | * make problems: throughput reduction (!), data errors... | 2650 | * make problems: throughput reduction (!), data errors... |
| 2651 | */ | 2651 | */ |
| 2652 | if (park) { | 2652 | if (park) { |
| 2653 | park = min(park, (unsigned) 3); | 2653 | park = min(park, (unsigned) 3); |
| 2654 | temp |= CMD_PARK; | 2654 | temp |= CMD_PARK; |
| 2655 | temp |= park << 8; | 2655 | temp |= park << 8; |
| 2656 | } | 2656 | } |
| 2657 | oxu_dbg(oxu, "park %d\n", park); | 2657 | oxu_dbg(oxu, "park %d\n", park); |
| 2658 | } | 2658 | } |
| 2659 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { | 2659 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
| 2660 | /* periodic schedule size can be smaller than default */ | 2660 | /* periodic schedule size can be smaller than default */ |
| 2661 | temp &= ~(3 << 2); | 2661 | temp &= ~(3 << 2); |
| 2662 | temp |= (EHCI_TUNE_FLS << 2); | 2662 | temp |= (EHCI_TUNE_FLS << 2); |
| 2663 | } | 2663 | } |
| 2664 | oxu->command = temp; | 2664 | oxu->command = temp; |
| 2665 | 2665 | ||
| 2666 | return 0; | 2666 | return 0; |
| 2667 | } | 2667 | } |
| 2668 | 2668 | ||
| 2669 | /* Called during probe() after chip reset completes. | 2669 | /* Called during probe() after chip reset completes. |
| 2670 | */ | 2670 | */ |
| 2671 | static int oxu_reset(struct usb_hcd *hcd) | 2671 | static int oxu_reset(struct usb_hcd *hcd) |
| 2672 | { | 2672 | { |
| 2673 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2673 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2674 | int ret; | 2674 | int ret; |
| 2675 | 2675 | ||
| 2676 | spin_lock_init(&oxu->mem_lock); | 2676 | spin_lock_init(&oxu->mem_lock); |
| 2677 | INIT_LIST_HEAD(&oxu->urb_list); | 2677 | INIT_LIST_HEAD(&oxu->urb_list); |
| 2678 | oxu->urb_len = 0; | 2678 | oxu->urb_len = 0; |
| 2679 | 2679 | ||
| 2680 | /* FIMXE */ | 2680 | /* FIMXE */ |
| 2681 | hcd->self.controller->dma_mask = NULL; | 2681 | hcd->self.controller->dma_mask = NULL; |
| 2682 | 2682 | ||
| 2683 | if (oxu->is_otg) { | 2683 | if (oxu->is_otg) { |
| 2684 | oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET; | 2684 | oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET; |
| 2685 | oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \ | 2685 | oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \ |
| 2686 | HC_LENGTH(readl(&oxu->caps->hc_capbase)); | 2686 | HC_LENGTH(readl(&oxu->caps->hc_capbase)); |
| 2687 | 2687 | ||
| 2688 | oxu->mem = hcd->regs + OXU_SPH_MEM; | 2688 | oxu->mem = hcd->regs + OXU_SPH_MEM; |
| 2689 | } else { | 2689 | } else { |
| 2690 | oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET; | 2690 | oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET; |
| 2691 | oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \ | 2691 | oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \ |
| 2692 | HC_LENGTH(readl(&oxu->caps->hc_capbase)); | 2692 | HC_LENGTH(readl(&oxu->caps->hc_capbase)); |
| 2693 | 2693 | ||
| 2694 | oxu->mem = hcd->regs + OXU_OTG_MEM; | 2694 | oxu->mem = hcd->regs + OXU_OTG_MEM; |
| 2695 | } | 2695 | } |
| 2696 | 2696 | ||
| 2697 | oxu->hcs_params = readl(&oxu->caps->hcs_params); | 2697 | oxu->hcs_params = readl(&oxu->caps->hcs_params); |
| 2698 | oxu->sbrn = 0x20; | 2698 | oxu->sbrn = 0x20; |
| 2699 | 2699 | ||
| 2700 | ret = oxu_hcd_init(hcd); | 2700 | ret = oxu_hcd_init(hcd); |
| 2701 | if (ret) | 2701 | if (ret) |
| 2702 | return ret; | 2702 | return ret; |
| 2703 | 2703 | ||
| 2704 | return 0; | 2704 | return 0; |
| 2705 | } | 2705 | } |
| 2706 | 2706 | ||
| 2707 | static int oxu_run(struct usb_hcd *hcd) | 2707 | static int oxu_run(struct usb_hcd *hcd) |
| 2708 | { | 2708 | { |
| 2709 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2709 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2710 | int retval; | 2710 | int retval; |
| 2711 | u32 temp, hcc_params; | 2711 | u32 temp, hcc_params; |
| 2712 | 2712 | ||
| 2713 | hcd->uses_new_polling = 1; | 2713 | hcd->uses_new_polling = 1; |
| 2714 | 2714 | ||
| 2715 | /* EHCI spec section 4.1 */ | 2715 | /* EHCI spec section 4.1 */ |
| 2716 | retval = ehci_reset(oxu); | 2716 | retval = ehci_reset(oxu); |
| 2717 | if (retval != 0) { | 2717 | if (retval != 0) { |
| 2718 | ehci_mem_cleanup(oxu); | 2718 | ehci_mem_cleanup(oxu); |
| 2719 | return retval; | 2719 | return retval; |
| 2720 | } | 2720 | } |
| 2721 | writel(oxu->periodic_dma, &oxu->regs->frame_list); | 2721 | writel(oxu->periodic_dma, &oxu->regs->frame_list); |
| 2722 | writel((u32) oxu->async->qh_dma, &oxu->regs->async_next); | 2722 | writel((u32) oxu->async->qh_dma, &oxu->regs->async_next); |
| 2723 | 2723 | ||
| 2724 | /* hcc_params controls whether oxu->regs->segment must (!!!) | 2724 | /* hcc_params controls whether oxu->regs->segment must (!!!) |
| 2725 | * be used; it constrains QH/ITD/SITD and QTD locations. | 2725 | * be used; it constrains QH/ITD/SITD and QTD locations. |
| 2726 | * pci_pool consistent memory always uses segment zero. | 2726 | * pci_pool consistent memory always uses segment zero. |
| 2727 | * streaming mappings for I/O buffers, like pci_map_single(), | 2727 | * streaming mappings for I/O buffers, like pci_map_single(), |
| 2728 | * can return segments above 4GB, if the device allows. | 2728 | * can return segments above 4GB, if the device allows. |
| 2729 | * | 2729 | * |
| 2730 | * NOTE: the dma mask is visible through dma_supported(), so | 2730 | * NOTE: the dma mask is visible through dma_supported(), so |
| 2731 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | 2731 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, |
| 2732 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | 2732 | * Scsi_Host.highmem_io, and so forth. It's readonly to all |
| 2733 | * host side drivers though. | 2733 | * host side drivers though. |
| 2734 | */ | 2734 | */ |
| 2735 | hcc_params = readl(&oxu->caps->hcc_params); | 2735 | hcc_params = readl(&oxu->caps->hcc_params); |
| 2736 | if (HCC_64BIT_ADDR(hcc_params)) | 2736 | if (HCC_64BIT_ADDR(hcc_params)) |
| 2737 | writel(0, &oxu->regs->segment); | 2737 | writel(0, &oxu->regs->segment); |
| 2738 | 2738 | ||
| 2739 | oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | | 2739 | oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | |
| 2740 | CMD_ASE | CMD_RESET); | 2740 | CMD_ASE | CMD_RESET); |
| 2741 | oxu->command |= CMD_RUN; | 2741 | oxu->command |= CMD_RUN; |
| 2742 | writel(oxu->command, &oxu->regs->command); | 2742 | writel(oxu->command, &oxu->regs->command); |
| 2743 | dbg_cmd(oxu, "init", oxu->command); | 2743 | dbg_cmd(oxu, "init", oxu->command); |
| 2744 | 2744 | ||
| 2745 | /* | 2745 | /* |
| 2746 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | 2746 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices |
| 2747 | * are explicitly handed to companion controller(s), so no TT is | 2747 | * are explicitly handed to companion controller(s), so no TT is |
| 2748 | * involved with the root hub. (Except where one is integrated, | 2748 | * involved with the root hub. (Except where one is integrated, |
| 2749 | * and there's no companion controller unless maybe for USB OTG.) | 2749 | * and there's no companion controller unless maybe for USB OTG.) |
| 2750 | */ | 2750 | */ |
| 2751 | hcd->state = HC_STATE_RUNNING; | 2751 | hcd->state = HC_STATE_RUNNING; |
| 2752 | writel(FLAG_CF, &oxu->regs->configured_flag); | 2752 | writel(FLAG_CF, &oxu->regs->configured_flag); |
| 2753 | readl(&oxu->regs->command); /* unblock posted writes */ | 2753 | readl(&oxu->regs->command); /* unblock posted writes */ |
| 2754 | 2754 | ||
| 2755 | temp = HC_VERSION(readl(&oxu->caps->hc_capbase)); | 2755 | temp = HC_VERSION(readl(&oxu->caps->hc_capbase)); |
| 2756 | oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n", | 2756 | oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n", |
| 2757 | ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f), | 2757 | ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f), |
| 2758 | temp >> 8, temp & 0xff, DRIVER_VERSION, | 2758 | temp >> 8, temp & 0xff, DRIVER_VERSION, |
| 2759 | ignore_oc ? ", overcurrent ignored" : ""); | 2759 | ignore_oc ? ", overcurrent ignored" : ""); |
| 2760 | 2760 | ||
| 2761 | writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */ | 2761 | writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */ |
| 2762 | 2762 | ||
| 2763 | return 0; | 2763 | return 0; |
| 2764 | } | 2764 | } |
| 2765 | 2765 | ||
| 2766 | static void oxu_stop(struct usb_hcd *hcd) | 2766 | static void oxu_stop(struct usb_hcd *hcd) |
| 2767 | { | 2767 | { |
| 2768 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2768 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2769 | 2769 | ||
| 2770 | /* Turn off port power on all root hub ports. */ | 2770 | /* Turn off port power on all root hub ports. */ |
| 2771 | ehci_port_power(oxu, 0); | 2771 | ehci_port_power(oxu, 0); |
| 2772 | 2772 | ||
| 2773 | /* no more interrupts ... */ | 2773 | /* no more interrupts ... */ |
| 2774 | del_timer_sync(&oxu->watchdog); | 2774 | del_timer_sync(&oxu->watchdog); |
| 2775 | 2775 | ||
| 2776 | spin_lock_irq(&oxu->lock); | 2776 | spin_lock_irq(&oxu->lock); |
| 2777 | if (HC_IS_RUNNING(hcd->state)) | 2777 | if (HC_IS_RUNNING(hcd->state)) |
| 2778 | ehci_quiesce(oxu); | 2778 | ehci_quiesce(oxu); |
| 2779 | 2779 | ||
| 2780 | ehci_reset(oxu); | 2780 | ehci_reset(oxu); |
| 2781 | writel(0, &oxu->regs->intr_enable); | 2781 | writel(0, &oxu->regs->intr_enable); |
| 2782 | spin_unlock_irq(&oxu->lock); | 2782 | spin_unlock_irq(&oxu->lock); |
| 2783 | 2783 | ||
| 2784 | /* let companion controllers work when we aren't */ | 2784 | /* let companion controllers work when we aren't */ |
| 2785 | writel(0, &oxu->regs->configured_flag); | 2785 | writel(0, &oxu->regs->configured_flag); |
| 2786 | 2786 | ||
| 2787 | /* root hub is shut down separately (first, when possible) */ | 2787 | /* root hub is shut down separately (first, when possible) */ |
| 2788 | spin_lock_irq(&oxu->lock); | 2788 | spin_lock_irq(&oxu->lock); |
| 2789 | if (oxu->async) | 2789 | if (oxu->async) |
| 2790 | ehci_work(oxu); | 2790 | ehci_work(oxu); |
| 2791 | spin_unlock_irq(&oxu->lock); | 2791 | spin_unlock_irq(&oxu->lock); |
| 2792 | ehci_mem_cleanup(oxu); | 2792 | ehci_mem_cleanup(oxu); |
| 2793 | 2793 | ||
| 2794 | dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status)); | 2794 | dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status)); |
| 2795 | } | 2795 | } |
| 2796 | 2796 | ||
| 2797 | /* Kick in for silicon on any bus (not just pci, etc). | 2797 | /* Kick in for silicon on any bus (not just pci, etc). |
| 2798 | * This forcibly disables dma and IRQs, helping kexec and other cases | 2798 | * This forcibly disables dma and IRQs, helping kexec and other cases |
| 2799 | * where the next system software may expect clean state. | 2799 | * where the next system software may expect clean state. |
| 2800 | */ | 2800 | */ |
| 2801 | static void oxu_shutdown(struct usb_hcd *hcd) | 2801 | static void oxu_shutdown(struct usb_hcd *hcd) |
| 2802 | { | 2802 | { |
| 2803 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2803 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2804 | 2804 | ||
| 2805 | (void) ehci_halt(oxu); | 2805 | (void) ehci_halt(oxu); |
| 2806 | ehci_turn_off_all_ports(oxu); | 2806 | ehci_turn_off_all_ports(oxu); |
| 2807 | 2807 | ||
| 2808 | /* make BIOS/etc use companion controller during reboot */ | 2808 | /* make BIOS/etc use companion controller during reboot */ |
| 2809 | writel(0, &oxu->regs->configured_flag); | 2809 | writel(0, &oxu->regs->configured_flag); |
| 2810 | 2810 | ||
| 2811 | /* unblock posted writes */ | 2811 | /* unblock posted writes */ |
| 2812 | readl(&oxu->regs->configured_flag); | 2812 | readl(&oxu->regs->configured_flag); |
| 2813 | } | 2813 | } |
| 2814 | 2814 | ||
| 2815 | /* Non-error returns are a promise to giveback() the urb later | 2815 | /* Non-error returns are a promise to giveback() the urb later |
| 2816 | * we drop ownership so next owner (or urb unlink) can get it | 2816 | * we drop ownership so next owner (or urb unlink) can get it |
| 2817 | * | 2817 | * |
| 2818 | * urb + dev is in hcd.self.controller.urb_list | 2818 | * urb + dev is in hcd.self.controller.urb_list |
| 2819 | * we're queueing TDs onto software and hardware lists | 2819 | * we're queueing TDs onto software and hardware lists |
| 2820 | * | 2820 | * |
| 2821 | * hcd-specific init for hcpriv hasn't been done yet | 2821 | * hcd-specific init for hcpriv hasn't been done yet |
| 2822 | * | 2822 | * |
| 2823 | * NOTE: control, bulk, and interrupt share the same code to append TDs | 2823 | * NOTE: control, bulk, and interrupt share the same code to append TDs |
| 2824 | * to a (possibly active) QH, and the same QH scanning code. | 2824 | * to a (possibly active) QH, and the same QH scanning code. |
| 2825 | */ | 2825 | */ |
| 2826 | static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | 2826 | static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
| 2827 | gfp_t mem_flags) | 2827 | gfp_t mem_flags) |
| 2828 | { | 2828 | { |
| 2829 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2829 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2830 | struct list_head qtd_list; | 2830 | struct list_head qtd_list; |
| 2831 | 2831 | ||
| 2832 | INIT_LIST_HEAD(&qtd_list); | 2832 | INIT_LIST_HEAD(&qtd_list); |
| 2833 | 2833 | ||
| 2834 | switch (usb_pipetype(urb->pipe)) { | 2834 | switch (usb_pipetype(urb->pipe)) { |
| 2835 | case PIPE_CONTROL: | 2835 | case PIPE_CONTROL: |
| 2836 | case PIPE_BULK: | 2836 | case PIPE_BULK: |
| 2837 | default: | 2837 | default: |
| 2838 | if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags)) | 2838 | if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags)) |
| 2839 | return -ENOMEM; | 2839 | return -ENOMEM; |
| 2840 | return submit_async(oxu, urb, &qtd_list, mem_flags); | 2840 | return submit_async(oxu, urb, &qtd_list, mem_flags); |
| 2841 | 2841 | ||
| 2842 | case PIPE_INTERRUPT: | 2842 | case PIPE_INTERRUPT: |
| 2843 | if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags)) | 2843 | if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags)) |
| 2844 | return -ENOMEM; | 2844 | return -ENOMEM; |
| 2845 | return intr_submit(oxu, urb, &qtd_list, mem_flags); | 2845 | return intr_submit(oxu, urb, &qtd_list, mem_flags); |
| 2846 | 2846 | ||
| 2847 | case PIPE_ISOCHRONOUS: | 2847 | case PIPE_ISOCHRONOUS: |
| 2848 | if (urb->dev->speed == USB_SPEED_HIGH) | 2848 | if (urb->dev->speed == USB_SPEED_HIGH) |
| 2849 | return itd_submit(oxu, urb, mem_flags); | 2849 | return itd_submit(oxu, urb, mem_flags); |
| 2850 | else | 2850 | else |
| 2851 | return sitd_submit(oxu, urb, mem_flags); | 2851 | return sitd_submit(oxu, urb, mem_flags); |
| 2852 | } | 2852 | } |
| 2853 | } | 2853 | } |
| 2854 | 2854 | ||
| 2855 | /* This function is responsible for breaking URBs with big data size | 2855 | /* This function is responsible for breaking URBs with big data size |
| 2856 | * into smaller size and processing small urbs in sequence. | 2856 | * into smaller size and processing small urbs in sequence. |
| 2857 | */ | 2857 | */ |
| 2858 | static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | 2858 | static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
| 2859 | gfp_t mem_flags) | 2859 | gfp_t mem_flags) |
| 2860 | { | 2860 | { |
| 2861 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2861 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2862 | int num, rem; | 2862 | int num, rem; |
| 2863 | int transfer_buffer_length; | 2863 | int transfer_buffer_length; |
| 2864 | void *transfer_buffer; | 2864 | void *transfer_buffer; |
| 2865 | struct urb *murb; | 2865 | struct urb *murb; |
| 2866 | int i, ret; | 2866 | int i, ret; |
| 2867 | 2867 | ||
| 2868 | /* If not bulk pipe just enqueue the URB */ | 2868 | /* If not bulk pipe just enqueue the URB */ |
| 2869 | if (!usb_pipebulk(urb->pipe)) | 2869 | if (!usb_pipebulk(urb->pipe)) |
| 2870 | return __oxu_urb_enqueue(hcd, urb, mem_flags); | 2870 | return __oxu_urb_enqueue(hcd, urb, mem_flags); |
| 2871 | 2871 | ||
| 2872 | /* Otherwise we should verify the USB transfer buffer size! */ | 2872 | /* Otherwise we should verify the USB transfer buffer size! */ |
| 2873 | transfer_buffer = urb->transfer_buffer; | 2873 | transfer_buffer = urb->transfer_buffer; |
| 2874 | transfer_buffer_length = urb->transfer_buffer_length; | 2874 | transfer_buffer_length = urb->transfer_buffer_length; |
| 2875 | 2875 | ||
| 2876 | num = urb->transfer_buffer_length / 4096; | 2876 | num = urb->transfer_buffer_length / 4096; |
| 2877 | rem = urb->transfer_buffer_length % 4096; | 2877 | rem = urb->transfer_buffer_length % 4096; |
| 2878 | if (rem != 0) | 2878 | if (rem != 0) |
| 2879 | num++; | 2879 | num++; |
| 2880 | 2880 | ||
| 2881 | /* If URB is smaller than 4096 bytes just enqueue it! */ | 2881 | /* If URB is smaller than 4096 bytes just enqueue it! */ |
| 2882 | if (num == 1) | 2882 | if (num == 1) |
| 2883 | return __oxu_urb_enqueue(hcd, urb, mem_flags); | 2883 | return __oxu_urb_enqueue(hcd, urb, mem_flags); |
| 2884 | 2884 | ||
| 2885 | /* Ok, we have more job to do! :) */ | 2885 | /* Ok, we have more job to do! :) */ |
| 2886 | 2886 | ||
| 2887 | for (i = 0; i < num - 1; i++) { | 2887 | for (i = 0; i < num - 1; i++) { |
| 2888 | /* Get free micro URB poll till a free urb is received */ | 2888 | /* Get free micro URB poll till a free urb is received */ |
| 2889 | 2889 | ||
| 2890 | do { | 2890 | do { |
| 2891 | murb = (struct urb *) oxu_murb_alloc(oxu); | 2891 | murb = (struct urb *) oxu_murb_alloc(oxu); |
| 2892 | if (!murb) | 2892 | if (!murb) |
| 2893 | schedule(); | 2893 | schedule(); |
| 2894 | } while (!murb); | 2894 | } while (!murb); |
| 2895 | 2895 | ||
| 2896 | /* Coping the urb */ | 2896 | /* Coping the urb */ |
| 2897 | memcpy(murb, urb, sizeof(struct urb)); | 2897 | memcpy(murb, urb, sizeof(struct urb)); |
| 2898 | 2898 | ||
| 2899 | murb->transfer_buffer_length = 4096; | 2899 | murb->transfer_buffer_length = 4096; |
| 2900 | murb->transfer_buffer = transfer_buffer + i * 4096; | 2900 | murb->transfer_buffer = transfer_buffer + i * 4096; |
| 2901 | 2901 | ||
| 2902 | /* Null pointer for the encodes that this is a micro urb */ | 2902 | /* Null pointer for the encodes that this is a micro urb */ |
| 2903 | murb->complete = NULL; | 2903 | murb->complete = NULL; |
| 2904 | 2904 | ||
| 2905 | ((struct oxu_murb *) murb)->main = urb; | 2905 | ((struct oxu_murb *) murb)->main = urb; |
| 2906 | ((struct oxu_murb *) murb)->last = 0; | 2906 | ((struct oxu_murb *) murb)->last = 0; |
| 2907 | 2907 | ||
| 2908 | /* This loop is to guarantee urb to be processed when there's | 2908 | /* This loop is to guarantee urb to be processed when there's |
| 2909 | * not enough resources at a particular time by retrying. | 2909 | * not enough resources at a particular time by retrying. |
| 2910 | */ | 2910 | */ |
| 2911 | do { | 2911 | do { |
| 2912 | ret = __oxu_urb_enqueue(hcd, murb, mem_flags); | 2912 | ret = __oxu_urb_enqueue(hcd, murb, mem_flags); |
| 2913 | if (ret) | 2913 | if (ret) |
| 2914 | schedule(); | 2914 | schedule(); |
| 2915 | } while (ret); | 2915 | } while (ret); |
| 2916 | } | 2916 | } |
| 2917 | 2917 | ||
| 2918 | /* Last urb requires special handling */ | 2918 | /* Last urb requires special handling */ |
| 2919 | 2919 | ||
| 2920 | /* Get free micro URB poll till a free urb is received */ | 2920 | /* Get free micro URB poll till a free urb is received */ |
| 2921 | do { | 2921 | do { |
| 2922 | murb = (struct urb *) oxu_murb_alloc(oxu); | 2922 | murb = (struct urb *) oxu_murb_alloc(oxu); |
| 2923 | if (!murb) | 2923 | if (!murb) |
| 2924 | schedule(); | 2924 | schedule(); |
| 2925 | } while (!murb); | 2925 | } while (!murb); |
| 2926 | 2926 | ||
| 2927 | /* Coping the urb */ | 2927 | /* Coping the urb */ |
| 2928 | memcpy(murb, urb, sizeof(struct urb)); | 2928 | memcpy(murb, urb, sizeof(struct urb)); |
| 2929 | 2929 | ||
| 2930 | murb->transfer_buffer_length = rem > 0 ? rem : 4096; | 2930 | murb->transfer_buffer_length = rem > 0 ? rem : 4096; |
| 2931 | murb->transfer_buffer = transfer_buffer + (num - 1) * 4096; | 2931 | murb->transfer_buffer = transfer_buffer + (num - 1) * 4096; |
| 2932 | 2932 | ||
| 2933 | /* Null pointer for the encodes that this is a micro urb */ | 2933 | /* Null pointer for the encodes that this is a micro urb */ |
| 2934 | murb->complete = NULL; | 2934 | murb->complete = NULL; |
| 2935 | 2935 | ||
| 2936 | ((struct oxu_murb *) murb)->main = urb; | 2936 | ((struct oxu_murb *) murb)->main = urb; |
| 2937 | ((struct oxu_murb *) murb)->last = 1; | 2937 | ((struct oxu_murb *) murb)->last = 1; |
| 2938 | 2938 | ||
| 2939 | do { | 2939 | do { |
| 2940 | ret = __oxu_urb_enqueue(hcd, murb, mem_flags); | 2940 | ret = __oxu_urb_enqueue(hcd, murb, mem_flags); |
| 2941 | if (ret) | 2941 | if (ret) |
| 2942 | schedule(); | 2942 | schedule(); |
| 2943 | } while (ret); | 2943 | } while (ret); |
| 2944 | 2944 | ||
| 2945 | return ret; | 2945 | return ret; |
| 2946 | } | 2946 | } |
| 2947 | 2947 | ||
| 2948 | /* Remove from hardware lists. | 2948 | /* Remove from hardware lists. |
| 2949 | * Completions normally happen asynchronously | 2949 | * Completions normally happen asynchronously |
| 2950 | */ | 2950 | */ |
| 2951 | static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | 2951 | static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
| 2952 | { | 2952 | { |
| 2953 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 2953 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 2954 | struct ehci_qh *qh; | 2954 | struct ehci_qh *qh; |
| 2955 | unsigned long flags; | 2955 | unsigned long flags; |
| 2956 | 2956 | ||
| 2957 | spin_lock_irqsave(&oxu->lock, flags); | 2957 | spin_lock_irqsave(&oxu->lock, flags); |
| 2958 | switch (usb_pipetype(urb->pipe)) { | 2958 | switch (usb_pipetype(urb->pipe)) { |
| 2959 | case PIPE_CONTROL: | 2959 | case PIPE_CONTROL: |
| 2960 | case PIPE_BULK: | 2960 | case PIPE_BULK: |
| 2961 | default: | 2961 | default: |
| 2962 | qh = (struct ehci_qh *) urb->hcpriv; | 2962 | qh = (struct ehci_qh *) urb->hcpriv; |
| 2963 | if (!qh) | 2963 | if (!qh) |
| 2964 | break; | 2964 | break; |
| 2965 | unlink_async(oxu, qh); | 2965 | unlink_async(oxu, qh); |
| 2966 | break; | 2966 | break; |
| 2967 | 2967 | ||
| 2968 | case PIPE_INTERRUPT: | 2968 | case PIPE_INTERRUPT: |
| 2969 | qh = (struct ehci_qh *) urb->hcpriv; | 2969 | qh = (struct ehci_qh *) urb->hcpriv; |
| 2970 | if (!qh) | 2970 | if (!qh) |
| 2971 | break; | 2971 | break; |
| 2972 | switch (qh->qh_state) { | 2972 | switch (qh->qh_state) { |
| 2973 | case QH_STATE_LINKED: | 2973 | case QH_STATE_LINKED: |
| 2974 | intr_deschedule(oxu, qh); | 2974 | intr_deschedule(oxu, qh); |
| 2975 | /* FALL THROUGH */ | 2975 | /* FALL THROUGH */ |
| 2976 | case QH_STATE_IDLE: | 2976 | case QH_STATE_IDLE: |
| 2977 | qh_completions(oxu, qh); | 2977 | qh_completions(oxu, qh); |
| 2978 | break; | 2978 | break; |
| 2979 | default: | 2979 | default: |
| 2980 | oxu_dbg(oxu, "bogus qh %p state %d\n", | 2980 | oxu_dbg(oxu, "bogus qh %p state %d\n", |
| 2981 | qh, qh->qh_state); | 2981 | qh, qh->qh_state); |
| 2982 | goto done; | 2982 | goto done; |
| 2983 | } | 2983 | } |
| 2984 | 2984 | ||
| 2985 | /* reschedule QH iff another request is queued */ | 2985 | /* reschedule QH iff another request is queued */ |
| 2986 | if (!list_empty(&qh->qtd_list) | 2986 | if (!list_empty(&qh->qtd_list) |
| 2987 | && HC_IS_RUNNING(hcd->state)) { | 2987 | && HC_IS_RUNNING(hcd->state)) { |
| 2988 | int status; | 2988 | int status; |
| 2989 | 2989 | ||
| 2990 | status = qh_schedule(oxu, qh); | 2990 | status = qh_schedule(oxu, qh); |
| 2991 | spin_unlock_irqrestore(&oxu->lock, flags); | 2991 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 2992 | 2992 | ||
| 2993 | if (status != 0) { | 2993 | if (status != 0) { |
| 2994 | /* shouldn't happen often, but ... | 2994 | /* shouldn't happen often, but ... |
| 2995 | * FIXME kill those tds' urbs | 2995 | * FIXME kill those tds' urbs |
| 2996 | */ | 2996 | */ |
| 2997 | dev_err(hcd->self.controller, | 2997 | dev_err(hcd->self.controller, |
| 2998 | "can't reschedule qh %p, err %d\n", qh, | 2998 | "can't reschedule qh %p, err %d\n", qh, |
| 2999 | status); | 2999 | status); |
| 3000 | } | 3000 | } |
| 3001 | return status; | 3001 | return status; |
| 3002 | } | 3002 | } |
| 3003 | break; | 3003 | break; |
| 3004 | } | 3004 | } |
| 3005 | done: | 3005 | done: |
| 3006 | spin_unlock_irqrestore(&oxu->lock, flags); | 3006 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 3007 | return 0; | 3007 | return 0; |
| 3008 | } | 3008 | } |
| 3009 | 3009 | ||
| 3010 | /* Bulk qh holds the data toggle */ | 3010 | /* Bulk qh holds the data toggle */ |
| 3011 | static void oxu_endpoint_disable(struct usb_hcd *hcd, | 3011 | static void oxu_endpoint_disable(struct usb_hcd *hcd, |
| 3012 | struct usb_host_endpoint *ep) | 3012 | struct usb_host_endpoint *ep) |
| 3013 | { | 3013 | { |
| 3014 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 3014 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 3015 | unsigned long flags; | 3015 | unsigned long flags; |
| 3016 | struct ehci_qh *qh, *tmp; | 3016 | struct ehci_qh *qh, *tmp; |
| 3017 | 3017 | ||
| 3018 | /* ASSERT: any requests/urbs are being unlinked */ | 3018 | /* ASSERT: any requests/urbs are being unlinked */ |
| 3019 | /* ASSERT: nobody can be submitting urbs for this any more */ | 3019 | /* ASSERT: nobody can be submitting urbs for this any more */ |
| 3020 | 3020 | ||
| 3021 | rescan: | 3021 | rescan: |
| 3022 | spin_lock_irqsave(&oxu->lock, flags); | 3022 | spin_lock_irqsave(&oxu->lock, flags); |
| 3023 | qh = ep->hcpriv; | 3023 | qh = ep->hcpriv; |
| 3024 | if (!qh) | 3024 | if (!qh) |
| 3025 | goto done; | 3025 | goto done; |
| 3026 | 3026 | ||
| 3027 | /* endpoints can be iso streams. for now, we don't | 3027 | /* endpoints can be iso streams. for now, we don't |
| 3028 | * accelerate iso completions ... so spin a while. | 3028 | * accelerate iso completions ... so spin a while. |
| 3029 | */ | 3029 | */ |
| 3030 | if (qh->hw_info1 == 0) { | 3030 | if (qh->hw_info1 == 0) { |
| 3031 | oxu_vdbg(oxu, "iso delay\n"); | 3031 | oxu_vdbg(oxu, "iso delay\n"); |
| 3032 | goto idle_timeout; | 3032 | goto idle_timeout; |
| 3033 | } | 3033 | } |
| 3034 | 3034 | ||
| 3035 | if (!HC_IS_RUNNING(hcd->state)) | 3035 | if (!HC_IS_RUNNING(hcd->state)) |
| 3036 | qh->qh_state = QH_STATE_IDLE; | 3036 | qh->qh_state = QH_STATE_IDLE; |
| 3037 | switch (qh->qh_state) { | 3037 | switch (qh->qh_state) { |
| 3038 | case QH_STATE_LINKED: | 3038 | case QH_STATE_LINKED: |
| 3039 | for (tmp = oxu->async->qh_next.qh; | 3039 | for (tmp = oxu->async->qh_next.qh; |
| 3040 | tmp && tmp != qh; | 3040 | tmp && tmp != qh; |
| 3041 | tmp = tmp->qh_next.qh) | 3041 | tmp = tmp->qh_next.qh) |
| 3042 | continue; | 3042 | continue; |
| 3043 | /* periodic qh self-unlinks on empty */ | 3043 | /* periodic qh self-unlinks on empty */ |
| 3044 | if (!tmp) | 3044 | if (!tmp) |
| 3045 | goto nogood; | 3045 | goto nogood; |
| 3046 | unlink_async(oxu, qh); | 3046 | unlink_async(oxu, qh); |
| 3047 | /* FALL THROUGH */ | 3047 | /* FALL THROUGH */ |
| 3048 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | 3048 | case QH_STATE_UNLINK: /* wait for hw to finish? */ |
| 3049 | idle_timeout: | 3049 | idle_timeout: |
| 3050 | spin_unlock_irqrestore(&oxu->lock, flags); | 3050 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 3051 | schedule_timeout_uninterruptible(1); | 3051 | schedule_timeout_uninterruptible(1); |
| 3052 | goto rescan; | 3052 | goto rescan; |
| 3053 | case QH_STATE_IDLE: /* fully unlinked */ | 3053 | case QH_STATE_IDLE: /* fully unlinked */ |
| 3054 | if (list_empty(&qh->qtd_list)) { | 3054 | if (list_empty(&qh->qtd_list)) { |
| 3055 | qh_put(qh); | 3055 | qh_put(qh); |
| 3056 | break; | 3056 | break; |
| 3057 | } | 3057 | } |
| 3058 | /* else FALL THROUGH */ | 3058 | /* else FALL THROUGH */ |
| 3059 | default: | 3059 | default: |
| 3060 | nogood: | 3060 | nogood: |
| 3061 | /* caller was supposed to have unlinked any requests; | 3061 | /* caller was supposed to have unlinked any requests; |
| 3062 | * that's not our job. just leak this memory. | 3062 | * that's not our job. just leak this memory. |
| 3063 | */ | 3063 | */ |
| 3064 | oxu_err(oxu, "qh %p (#%02x) state %d%s\n", | 3064 | oxu_err(oxu, "qh %p (#%02x) state %d%s\n", |
| 3065 | qh, ep->desc.bEndpointAddress, qh->qh_state, | 3065 | qh, ep->desc.bEndpointAddress, qh->qh_state, |
| 3066 | list_empty(&qh->qtd_list) ? "" : "(has tds)"); | 3066 | list_empty(&qh->qtd_list) ? "" : "(has tds)"); |
| 3067 | break; | 3067 | break; |
| 3068 | } | 3068 | } |
| 3069 | ep->hcpriv = NULL; | 3069 | ep->hcpriv = NULL; |
| 3070 | done: | 3070 | done: |
| 3071 | spin_unlock_irqrestore(&oxu->lock, flags); | 3071 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 3072 | } | 3072 | } |
| 3073 | 3073 | ||
| 3074 | static int oxu_get_frame(struct usb_hcd *hcd) | 3074 | static int oxu_get_frame(struct usb_hcd *hcd) |
| 3075 | { | 3075 | { |
| 3076 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 3076 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 3077 | 3077 | ||
| 3078 | return (readl(&oxu->regs->frame_index) >> 3) % | 3078 | return (readl(&oxu->regs->frame_index) >> 3) % |
| 3079 | oxu->periodic_size; | 3079 | oxu->periodic_size; |
| 3080 | } | 3080 | } |
| 3081 | 3081 | ||
| 3082 | /* Build "status change" packet (one or two bytes) from HC registers */ | 3082 | /* Build "status change" packet (one or two bytes) from HC registers */ |
| 3083 | static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf) | 3083 | static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf) |
| 3084 | { | 3084 | { |
| 3085 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 3085 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 3086 | u32 temp, mask, status = 0; | 3086 | u32 temp, mask, status = 0; |
| 3087 | int ports, i, retval = 1; | 3087 | int ports, i, retval = 1; |
| 3088 | unsigned long flags; | 3088 | unsigned long flags; |
| 3089 | 3089 | ||
| 3090 | /* if !PM_RUNTIME, root hub timers won't get shut down ... */ | 3090 | /* if !PM, root hub timers won't get shut down ... */ |
| 3091 | if (!HC_IS_RUNNING(hcd->state)) | 3091 | if (!HC_IS_RUNNING(hcd->state)) |
| 3092 | return 0; | 3092 | return 0; |
| 3093 | 3093 | ||
| 3094 | /* init status to no-changes */ | 3094 | /* init status to no-changes */ |
| 3095 | buf[0] = 0; | 3095 | buf[0] = 0; |
| 3096 | ports = HCS_N_PORTS(oxu->hcs_params); | 3096 | ports = HCS_N_PORTS(oxu->hcs_params); |
| 3097 | if (ports > 7) { | 3097 | if (ports > 7) { |
| 3098 | buf[1] = 0; | 3098 | buf[1] = 0; |
| 3099 | retval++; | 3099 | retval++; |
| 3100 | } | 3100 | } |
| 3101 | 3101 | ||
| 3102 | /* Some boards (mostly VIA?) report bogus overcurrent indications, | 3102 | /* Some boards (mostly VIA?) report bogus overcurrent indications, |
| 3103 | * causing massive log spam unless we completely ignore them. It | 3103 | * causing massive log spam unless we completely ignore them. It |
| 3104 | * may be relevant that VIA VT8235 controllers, where PORT_POWER is | 3104 | * may be relevant that VIA VT8235 controllers, where PORT_POWER is |
| 3105 | * always set, seem to clear PORT_OCC and PORT_CSC when writing to | 3105 | * always set, seem to clear PORT_OCC and PORT_CSC when writing to |
| 3106 | * PORT_POWER; that's surprising, but maybe within-spec. | 3106 | * PORT_POWER; that's surprising, but maybe within-spec. |
| 3107 | */ | 3107 | */ |
| 3108 | if (!ignore_oc) | 3108 | if (!ignore_oc) |
| 3109 | mask = PORT_CSC | PORT_PEC | PORT_OCC; | 3109 | mask = PORT_CSC | PORT_PEC | PORT_OCC; |
| 3110 | else | 3110 | else |
| 3111 | mask = PORT_CSC | PORT_PEC; | 3111 | mask = PORT_CSC | PORT_PEC; |
| 3112 | 3112 | ||
| 3113 | /* no hub change reports (bit 0) for now (power, ...) */ | 3113 | /* no hub change reports (bit 0) for now (power, ...) */ |
| 3114 | 3114 | ||
| 3115 | /* port N changes (bit N)? */ | 3115 | /* port N changes (bit N)? */ |
| 3116 | spin_lock_irqsave(&oxu->lock, flags); | 3116 | spin_lock_irqsave(&oxu->lock, flags); |
| 3117 | for (i = 0; i < ports; i++) { | 3117 | for (i = 0; i < ports; i++) { |
| 3118 | temp = readl(&oxu->regs->port_status[i]); | 3118 | temp = readl(&oxu->regs->port_status[i]); |
| 3119 | 3119 | ||
| 3120 | /* | 3120 | /* |
| 3121 | * Return status information even for ports with OWNER set. | 3121 | * Return status information even for ports with OWNER set. |
| 3122 | * Otherwise hub_wq wouldn't see the disconnect event when a | 3122 | * Otherwise hub_wq wouldn't see the disconnect event when a |
| 3123 | * high-speed device is switched over to the companion | 3123 | * high-speed device is switched over to the companion |
| 3124 | * controller by the user. | 3124 | * controller by the user. |
| 3125 | */ | 3125 | */ |
| 3126 | 3126 | ||
| 3127 | if (!(temp & PORT_CONNECT)) | 3127 | if (!(temp & PORT_CONNECT)) |
| 3128 | oxu->reset_done[i] = 0; | 3128 | oxu->reset_done[i] = 0; |
| 3129 | if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 && | 3129 | if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 && |
| 3130 | time_after_eq(jiffies, oxu->reset_done[i]))) { | 3130 | time_after_eq(jiffies, oxu->reset_done[i]))) { |
| 3131 | if (i < 7) | 3131 | if (i < 7) |
| 3132 | buf[0] |= 1 << (i + 1); | 3132 | buf[0] |= 1 << (i + 1); |
| 3133 | else | 3133 | else |
| 3134 | buf[1] |= 1 << (i - 7); | 3134 | buf[1] |= 1 << (i - 7); |
| 3135 | status = STS_PCD; | 3135 | status = STS_PCD; |
| 3136 | } | 3136 | } |
| 3137 | } | 3137 | } |
| 3138 | /* FIXME autosuspend idle root hubs */ | 3138 | /* FIXME autosuspend idle root hubs */ |
| 3139 | spin_unlock_irqrestore(&oxu->lock, flags); | 3139 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 3140 | return status ? retval : 0; | 3140 | return status ? retval : 0; |
| 3141 | } | 3141 | } |
| 3142 | 3142 | ||
| 3143 | /* Returns the speed of a device attached to a port on the root hub. */ | 3143 | /* Returns the speed of a device attached to a port on the root hub. */ |
| 3144 | static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu, | 3144 | static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu, |
| 3145 | unsigned int portsc) | 3145 | unsigned int portsc) |
| 3146 | { | 3146 | { |
| 3147 | switch ((portsc >> 26) & 3) { | 3147 | switch ((portsc >> 26) & 3) { |
| 3148 | case 0: | 3148 | case 0: |
| 3149 | return 0; | 3149 | return 0; |
| 3150 | case 1: | 3150 | case 1: |
| 3151 | return USB_PORT_STAT_LOW_SPEED; | 3151 | return USB_PORT_STAT_LOW_SPEED; |
| 3152 | case 2: | 3152 | case 2: |
| 3153 | default: | 3153 | default: |
| 3154 | return USB_PORT_STAT_HIGH_SPEED; | 3154 | return USB_PORT_STAT_HIGH_SPEED; |
| 3155 | } | 3155 | } |
| 3156 | } | 3156 | } |
| 3157 | 3157 | ||
| 3158 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | 3158 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
| 3159 | static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq, | 3159 | static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq, |
| 3160 | u16 wValue, u16 wIndex, char *buf, u16 wLength) | 3160 | u16 wValue, u16 wIndex, char *buf, u16 wLength) |
| 3161 | { | 3161 | { |
| 3162 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 3162 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 3163 | int ports = HCS_N_PORTS(oxu->hcs_params); | 3163 | int ports = HCS_N_PORTS(oxu->hcs_params); |
| 3164 | u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1]; | 3164 | u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1]; |
| 3165 | u32 temp, status; | 3165 | u32 temp, status; |
| 3166 | unsigned long flags; | 3166 | unsigned long flags; |
| 3167 | int retval = 0; | 3167 | int retval = 0; |
| 3168 | unsigned selector; | 3168 | unsigned selector; |
| 3169 | 3169 | ||
| 3170 | /* | 3170 | /* |
| 3171 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. | 3171 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. |
| 3172 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. | 3172 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. |
| 3173 | * (track current state ourselves) ... blink for diagnostics, | 3173 | * (track current state ourselves) ... blink for diagnostics, |
| 3174 | * power, "this is the one", etc. EHCI spec supports this. | 3174 | * power, "this is the one", etc. EHCI spec supports this. |
| 3175 | */ | 3175 | */ |
| 3176 | 3176 | ||
| 3177 | spin_lock_irqsave(&oxu->lock, flags); | 3177 | spin_lock_irqsave(&oxu->lock, flags); |
| 3178 | switch (typeReq) { | 3178 | switch (typeReq) { |
| 3179 | case ClearHubFeature: | 3179 | case ClearHubFeature: |
| 3180 | switch (wValue) { | 3180 | switch (wValue) { |
| 3181 | case C_HUB_LOCAL_POWER: | 3181 | case C_HUB_LOCAL_POWER: |
| 3182 | case C_HUB_OVER_CURRENT: | 3182 | case C_HUB_OVER_CURRENT: |
| 3183 | /* no hub-wide feature/status flags */ | 3183 | /* no hub-wide feature/status flags */ |
| 3184 | break; | 3184 | break; |
| 3185 | default: | 3185 | default: |
| 3186 | goto error; | 3186 | goto error; |
| 3187 | } | 3187 | } |
| 3188 | break; | 3188 | break; |
| 3189 | case ClearPortFeature: | 3189 | case ClearPortFeature: |
| 3190 | if (!wIndex || wIndex > ports) | 3190 | if (!wIndex || wIndex > ports) |
| 3191 | goto error; | 3191 | goto error; |
| 3192 | wIndex--; | 3192 | wIndex--; |
| 3193 | temp = readl(status_reg); | 3193 | temp = readl(status_reg); |
| 3194 | 3194 | ||
| 3195 | /* | 3195 | /* |
| 3196 | * Even if OWNER is set, so the port is owned by the | 3196 | * Even if OWNER is set, so the port is owned by the |
| 3197 | * companion controller, hub_wq needs to be able to clear | 3197 | * companion controller, hub_wq needs to be able to clear |
| 3198 | * the port-change status bits (especially | 3198 | * the port-change status bits (especially |
| 3199 | * USB_PORT_STAT_C_CONNECTION). | 3199 | * USB_PORT_STAT_C_CONNECTION). |
| 3200 | */ | 3200 | */ |
| 3201 | 3201 | ||
| 3202 | switch (wValue) { | 3202 | switch (wValue) { |
| 3203 | case USB_PORT_FEAT_ENABLE: | 3203 | case USB_PORT_FEAT_ENABLE: |
| 3204 | writel(temp & ~PORT_PE, status_reg); | 3204 | writel(temp & ~PORT_PE, status_reg); |
| 3205 | break; | 3205 | break; |
| 3206 | case USB_PORT_FEAT_C_ENABLE: | 3206 | case USB_PORT_FEAT_C_ENABLE: |
| 3207 | writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg); | 3207 | writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg); |
| 3208 | break; | 3208 | break; |
| 3209 | case USB_PORT_FEAT_SUSPEND: | 3209 | case USB_PORT_FEAT_SUSPEND: |
| 3210 | if (temp & PORT_RESET) | 3210 | if (temp & PORT_RESET) |
| 3211 | goto error; | 3211 | goto error; |
| 3212 | if (temp & PORT_SUSPEND) { | 3212 | if (temp & PORT_SUSPEND) { |
| 3213 | if ((temp & PORT_PE) == 0) | 3213 | if ((temp & PORT_PE) == 0) |
| 3214 | goto error; | 3214 | goto error; |
| 3215 | /* resume signaling for 20 msec */ | 3215 | /* resume signaling for 20 msec */ |
| 3216 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | 3216 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); |
| 3217 | writel(temp | PORT_RESUME, status_reg); | 3217 | writel(temp | PORT_RESUME, status_reg); |
| 3218 | oxu->reset_done[wIndex] = jiffies | 3218 | oxu->reset_done[wIndex] = jiffies |
| 3219 | + msecs_to_jiffies(20); | 3219 | + msecs_to_jiffies(20); |
| 3220 | } | 3220 | } |
| 3221 | break; | 3221 | break; |
| 3222 | case USB_PORT_FEAT_C_SUSPEND: | 3222 | case USB_PORT_FEAT_C_SUSPEND: |
| 3223 | /* we auto-clear this feature */ | 3223 | /* we auto-clear this feature */ |
| 3224 | break; | 3224 | break; |
| 3225 | case USB_PORT_FEAT_POWER: | 3225 | case USB_PORT_FEAT_POWER: |
| 3226 | if (HCS_PPC(oxu->hcs_params)) | 3226 | if (HCS_PPC(oxu->hcs_params)) |
| 3227 | writel(temp & ~(PORT_RWC_BITS | PORT_POWER), | 3227 | writel(temp & ~(PORT_RWC_BITS | PORT_POWER), |
| 3228 | status_reg); | 3228 | status_reg); |
| 3229 | break; | 3229 | break; |
| 3230 | case USB_PORT_FEAT_C_CONNECTION: | 3230 | case USB_PORT_FEAT_C_CONNECTION: |
| 3231 | writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg); | 3231 | writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg); |
| 3232 | break; | 3232 | break; |
| 3233 | case USB_PORT_FEAT_C_OVER_CURRENT: | 3233 | case USB_PORT_FEAT_C_OVER_CURRENT: |
| 3234 | writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg); | 3234 | writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg); |
| 3235 | break; | 3235 | break; |
| 3236 | case USB_PORT_FEAT_C_RESET: | 3236 | case USB_PORT_FEAT_C_RESET: |
| 3237 | /* GetPortStatus clears reset */ | 3237 | /* GetPortStatus clears reset */ |
| 3238 | break; | 3238 | break; |
| 3239 | default: | 3239 | default: |
| 3240 | goto error; | 3240 | goto error; |
| 3241 | } | 3241 | } |
| 3242 | readl(&oxu->regs->command); /* unblock posted write */ | 3242 | readl(&oxu->regs->command); /* unblock posted write */ |
| 3243 | break; | 3243 | break; |
| 3244 | case GetHubDescriptor: | 3244 | case GetHubDescriptor: |
| 3245 | ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *) | 3245 | ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *) |
| 3246 | buf); | 3246 | buf); |
| 3247 | break; | 3247 | break; |
| 3248 | case GetHubStatus: | 3248 | case GetHubStatus: |
| 3249 | /* no hub-wide feature/status flags */ | 3249 | /* no hub-wide feature/status flags */ |
| 3250 | memset(buf, 0, 4); | 3250 | memset(buf, 0, 4); |
| 3251 | break; | 3251 | break; |
| 3252 | case GetPortStatus: | 3252 | case GetPortStatus: |
| 3253 | if (!wIndex || wIndex > ports) | 3253 | if (!wIndex || wIndex > ports) |
| 3254 | goto error; | 3254 | goto error; |
| 3255 | wIndex--; | 3255 | wIndex--; |
| 3256 | status = 0; | 3256 | status = 0; |
| 3257 | temp = readl(status_reg); | 3257 | temp = readl(status_reg); |
| 3258 | 3258 | ||
| 3259 | /* wPortChange bits */ | 3259 | /* wPortChange bits */ |
| 3260 | if (temp & PORT_CSC) | 3260 | if (temp & PORT_CSC) |
| 3261 | status |= USB_PORT_STAT_C_CONNECTION << 16; | 3261 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
| 3262 | if (temp & PORT_PEC) | 3262 | if (temp & PORT_PEC) |
| 3263 | status |= USB_PORT_STAT_C_ENABLE << 16; | 3263 | status |= USB_PORT_STAT_C_ENABLE << 16; |
| 3264 | if ((temp & PORT_OCC) && !ignore_oc) | 3264 | if ((temp & PORT_OCC) && !ignore_oc) |
| 3265 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | 3265 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; |
| 3266 | 3266 | ||
| 3267 | /* whoever resumes must GetPortStatus to complete it!! */ | 3267 | /* whoever resumes must GetPortStatus to complete it!! */ |
| 3268 | if (temp & PORT_RESUME) { | 3268 | if (temp & PORT_RESUME) { |
| 3269 | 3269 | ||
| 3270 | /* Remote Wakeup received? */ | 3270 | /* Remote Wakeup received? */ |
| 3271 | if (!oxu->reset_done[wIndex]) { | 3271 | if (!oxu->reset_done[wIndex]) { |
| 3272 | /* resume signaling for 20 msec */ | 3272 | /* resume signaling for 20 msec */ |
| 3273 | oxu->reset_done[wIndex] = jiffies | 3273 | oxu->reset_done[wIndex] = jiffies |
| 3274 | + msecs_to_jiffies(20); | 3274 | + msecs_to_jiffies(20); |
| 3275 | /* check the port again */ | 3275 | /* check the port again */ |
| 3276 | mod_timer(&oxu_to_hcd(oxu)->rh_timer, | 3276 | mod_timer(&oxu_to_hcd(oxu)->rh_timer, |
| 3277 | oxu->reset_done[wIndex]); | 3277 | oxu->reset_done[wIndex]); |
| 3278 | } | 3278 | } |
| 3279 | 3279 | ||
| 3280 | /* resume completed? */ | 3280 | /* resume completed? */ |
| 3281 | else if (time_after_eq(jiffies, | 3281 | else if (time_after_eq(jiffies, |
| 3282 | oxu->reset_done[wIndex])) { | 3282 | oxu->reset_done[wIndex])) { |
| 3283 | status |= USB_PORT_STAT_C_SUSPEND << 16; | 3283 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
| 3284 | oxu->reset_done[wIndex] = 0; | 3284 | oxu->reset_done[wIndex] = 0; |
| 3285 | 3285 | ||
| 3286 | /* stop resume signaling */ | 3286 | /* stop resume signaling */ |
| 3287 | temp = readl(status_reg); | 3287 | temp = readl(status_reg); |
| 3288 | writel(temp & ~(PORT_RWC_BITS | PORT_RESUME), | 3288 | writel(temp & ~(PORT_RWC_BITS | PORT_RESUME), |
| 3289 | status_reg); | 3289 | status_reg); |
| 3290 | retval = handshake(oxu, status_reg, | 3290 | retval = handshake(oxu, status_reg, |
| 3291 | PORT_RESUME, 0, 2000 /* 2msec */); | 3291 | PORT_RESUME, 0, 2000 /* 2msec */); |
| 3292 | if (retval != 0) { | 3292 | if (retval != 0) { |
| 3293 | oxu_err(oxu, | 3293 | oxu_err(oxu, |
| 3294 | "port %d resume error %d\n", | 3294 | "port %d resume error %d\n", |
| 3295 | wIndex + 1, retval); | 3295 | wIndex + 1, retval); |
| 3296 | goto error; | 3296 | goto error; |
| 3297 | } | 3297 | } |
| 3298 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); | 3298 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); |
| 3299 | } | 3299 | } |
| 3300 | } | 3300 | } |
| 3301 | 3301 | ||
| 3302 | /* whoever resets must GetPortStatus to complete it!! */ | 3302 | /* whoever resets must GetPortStatus to complete it!! */ |
| 3303 | if ((temp & PORT_RESET) | 3303 | if ((temp & PORT_RESET) |
| 3304 | && time_after_eq(jiffies, | 3304 | && time_after_eq(jiffies, |
| 3305 | oxu->reset_done[wIndex])) { | 3305 | oxu->reset_done[wIndex])) { |
| 3306 | status |= USB_PORT_STAT_C_RESET << 16; | 3306 | status |= USB_PORT_STAT_C_RESET << 16; |
| 3307 | oxu->reset_done[wIndex] = 0; | 3307 | oxu->reset_done[wIndex] = 0; |
| 3308 | 3308 | ||
| 3309 | /* force reset to complete */ | 3309 | /* force reset to complete */ |
| 3310 | writel(temp & ~(PORT_RWC_BITS | PORT_RESET), | 3310 | writel(temp & ~(PORT_RWC_BITS | PORT_RESET), |
| 3311 | status_reg); | 3311 | status_reg); |
| 3312 | /* REVISIT: some hardware needs 550+ usec to clear | 3312 | /* REVISIT: some hardware needs 550+ usec to clear |
| 3313 | * this bit; seems too long to spin routinely... | 3313 | * this bit; seems too long to spin routinely... |
| 3314 | */ | 3314 | */ |
| 3315 | retval = handshake(oxu, status_reg, | 3315 | retval = handshake(oxu, status_reg, |
| 3316 | PORT_RESET, 0, 750); | 3316 | PORT_RESET, 0, 750); |
| 3317 | if (retval != 0) { | 3317 | if (retval != 0) { |
| 3318 | oxu_err(oxu, "port %d reset error %d\n", | 3318 | oxu_err(oxu, "port %d reset error %d\n", |
| 3319 | wIndex + 1, retval); | 3319 | wIndex + 1, retval); |
| 3320 | goto error; | 3320 | goto error; |
| 3321 | } | 3321 | } |
| 3322 | 3322 | ||
| 3323 | /* see what we found out */ | 3323 | /* see what we found out */ |
| 3324 | temp = check_reset_complete(oxu, wIndex, status_reg, | 3324 | temp = check_reset_complete(oxu, wIndex, status_reg, |
| 3325 | readl(status_reg)); | 3325 | readl(status_reg)); |
| 3326 | } | 3326 | } |
| 3327 | 3327 | ||
| 3328 | /* transfer dedicated ports to the companion hc */ | 3328 | /* transfer dedicated ports to the companion hc */ |
| 3329 | if ((temp & PORT_CONNECT) && | 3329 | if ((temp & PORT_CONNECT) && |
| 3330 | test_bit(wIndex, &oxu->companion_ports)) { | 3330 | test_bit(wIndex, &oxu->companion_ports)) { |
| 3331 | temp &= ~PORT_RWC_BITS; | 3331 | temp &= ~PORT_RWC_BITS; |
| 3332 | temp |= PORT_OWNER; | 3332 | temp |= PORT_OWNER; |
| 3333 | writel(temp, status_reg); | 3333 | writel(temp, status_reg); |
| 3334 | oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1); | 3334 | oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1); |
| 3335 | temp = readl(status_reg); | 3335 | temp = readl(status_reg); |
| 3336 | } | 3336 | } |
| 3337 | 3337 | ||
| 3338 | /* | 3338 | /* |
| 3339 | * Even if OWNER is set, there's no harm letting hub_wq | 3339 | * Even if OWNER is set, there's no harm letting hub_wq |
| 3340 | * see the wPortStatus values (they should all be 0 except | 3340 | * see the wPortStatus values (they should all be 0 except |
| 3341 | * for PORT_POWER anyway). | 3341 | * for PORT_POWER anyway). |
| 3342 | */ | 3342 | */ |
| 3343 | 3343 | ||
| 3344 | if (temp & PORT_CONNECT) { | 3344 | if (temp & PORT_CONNECT) { |
| 3345 | status |= USB_PORT_STAT_CONNECTION; | 3345 | status |= USB_PORT_STAT_CONNECTION; |
| 3346 | /* status may be from integrated TT */ | 3346 | /* status may be from integrated TT */ |
| 3347 | status |= oxu_port_speed(oxu, temp); | 3347 | status |= oxu_port_speed(oxu, temp); |
| 3348 | } | 3348 | } |
| 3349 | if (temp & PORT_PE) | 3349 | if (temp & PORT_PE) |
| 3350 | status |= USB_PORT_STAT_ENABLE; | 3350 | status |= USB_PORT_STAT_ENABLE; |
| 3351 | if (temp & (PORT_SUSPEND|PORT_RESUME)) | 3351 | if (temp & (PORT_SUSPEND|PORT_RESUME)) |
| 3352 | status |= USB_PORT_STAT_SUSPEND; | 3352 | status |= USB_PORT_STAT_SUSPEND; |
| 3353 | if (temp & PORT_OC) | 3353 | if (temp & PORT_OC) |
| 3354 | status |= USB_PORT_STAT_OVERCURRENT; | 3354 | status |= USB_PORT_STAT_OVERCURRENT; |
| 3355 | if (temp & PORT_RESET) | 3355 | if (temp & PORT_RESET) |
| 3356 | status |= USB_PORT_STAT_RESET; | 3356 | status |= USB_PORT_STAT_RESET; |
| 3357 | if (temp & PORT_POWER) | 3357 | if (temp & PORT_POWER) |
| 3358 | status |= USB_PORT_STAT_POWER; | 3358 | status |= USB_PORT_STAT_POWER; |
| 3359 | 3359 | ||
| 3360 | #ifndef OXU_VERBOSE_DEBUG | 3360 | #ifndef OXU_VERBOSE_DEBUG |
| 3361 | if (status & ~0xffff) /* only if wPortChange is interesting */ | 3361 | if (status & ~0xffff) /* only if wPortChange is interesting */ |
| 3362 | #endif | 3362 | #endif |
| 3363 | dbg_port(oxu, "GetStatus", wIndex + 1, temp); | 3363 | dbg_port(oxu, "GetStatus", wIndex + 1, temp); |
| 3364 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | 3364 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
| 3365 | break; | 3365 | break; |
| 3366 | case SetHubFeature: | 3366 | case SetHubFeature: |
| 3367 | switch (wValue) { | 3367 | switch (wValue) { |
| 3368 | case C_HUB_LOCAL_POWER: | 3368 | case C_HUB_LOCAL_POWER: |
| 3369 | case C_HUB_OVER_CURRENT: | 3369 | case C_HUB_OVER_CURRENT: |
| 3370 | /* no hub-wide feature/status flags */ | 3370 | /* no hub-wide feature/status flags */ |
| 3371 | break; | 3371 | break; |
| 3372 | default: | 3372 | default: |
| 3373 | goto error; | 3373 | goto error; |
| 3374 | } | 3374 | } |
| 3375 | break; | 3375 | break; |
| 3376 | case SetPortFeature: | 3376 | case SetPortFeature: |
| 3377 | selector = wIndex >> 8; | 3377 | selector = wIndex >> 8; |
| 3378 | wIndex &= 0xff; | 3378 | wIndex &= 0xff; |
| 3379 | if (!wIndex || wIndex > ports) | 3379 | if (!wIndex || wIndex > ports) |
| 3380 | goto error; | 3380 | goto error; |
| 3381 | wIndex--; | 3381 | wIndex--; |
| 3382 | temp = readl(status_reg); | 3382 | temp = readl(status_reg); |
| 3383 | if (temp & PORT_OWNER) | 3383 | if (temp & PORT_OWNER) |
| 3384 | break; | 3384 | break; |
| 3385 | 3385 | ||
| 3386 | temp &= ~PORT_RWC_BITS; | 3386 | temp &= ~PORT_RWC_BITS; |
| 3387 | switch (wValue) { | 3387 | switch (wValue) { |
| 3388 | case USB_PORT_FEAT_SUSPEND: | 3388 | case USB_PORT_FEAT_SUSPEND: |
| 3389 | if ((temp & PORT_PE) == 0 | 3389 | if ((temp & PORT_PE) == 0 |
| 3390 | || (temp & PORT_RESET) != 0) | 3390 | || (temp & PORT_RESET) != 0) |
| 3391 | goto error; | 3391 | goto error; |
| 3392 | if (device_may_wakeup(&hcd->self.root_hub->dev)) | 3392 | if (device_may_wakeup(&hcd->self.root_hub->dev)) |
| 3393 | temp |= PORT_WAKE_BITS; | 3393 | temp |= PORT_WAKE_BITS; |
| 3394 | writel(temp | PORT_SUSPEND, status_reg); | 3394 | writel(temp | PORT_SUSPEND, status_reg); |
| 3395 | break; | 3395 | break; |
| 3396 | case USB_PORT_FEAT_POWER: | 3396 | case USB_PORT_FEAT_POWER: |
| 3397 | if (HCS_PPC(oxu->hcs_params)) | 3397 | if (HCS_PPC(oxu->hcs_params)) |
| 3398 | writel(temp | PORT_POWER, status_reg); | 3398 | writel(temp | PORT_POWER, status_reg); |
| 3399 | break; | 3399 | break; |
| 3400 | case USB_PORT_FEAT_RESET: | 3400 | case USB_PORT_FEAT_RESET: |
| 3401 | if (temp & PORT_RESUME) | 3401 | if (temp & PORT_RESUME) |
| 3402 | goto error; | 3402 | goto error; |
| 3403 | /* line status bits may report this as low speed, | 3403 | /* line status bits may report this as low speed, |
| 3404 | * which can be fine if this root hub has a | 3404 | * which can be fine if this root hub has a |
| 3405 | * transaction translator built in. | 3405 | * transaction translator built in. |
| 3406 | */ | 3406 | */ |
| 3407 | oxu_vdbg(oxu, "port %d reset\n", wIndex + 1); | 3407 | oxu_vdbg(oxu, "port %d reset\n", wIndex + 1); |
| 3408 | temp |= PORT_RESET; | 3408 | temp |= PORT_RESET; |
| 3409 | temp &= ~PORT_PE; | 3409 | temp &= ~PORT_PE; |
| 3410 | 3410 | ||
| 3411 | /* | 3411 | /* |
| 3412 | * caller must wait, then call GetPortStatus | 3412 | * caller must wait, then call GetPortStatus |
| 3413 | * usb 2.0 spec says 50 ms resets on root | 3413 | * usb 2.0 spec says 50 ms resets on root |
| 3414 | */ | 3414 | */ |
| 3415 | oxu->reset_done[wIndex] = jiffies | 3415 | oxu->reset_done[wIndex] = jiffies |
| 3416 | + msecs_to_jiffies(50); | 3416 | + msecs_to_jiffies(50); |
| 3417 | writel(temp, status_reg); | 3417 | writel(temp, status_reg); |
| 3418 | break; | 3418 | break; |
| 3419 | 3419 | ||
| 3420 | /* For downstream facing ports (these): one hub port is put | 3420 | /* For downstream facing ports (these): one hub port is put |
| 3421 | * into test mode according to USB2 11.24.2.13, then the hub | 3421 | * into test mode according to USB2 11.24.2.13, then the hub |
| 3422 | * must be reset (which for root hub now means rmmod+modprobe, | 3422 | * must be reset (which for root hub now means rmmod+modprobe, |
| 3423 | * or else system reboot). See EHCI 2.3.9 and 4.14 for info | 3423 | * or else system reboot). See EHCI 2.3.9 and 4.14 for info |
| 3424 | * about the EHCI-specific stuff. | 3424 | * about the EHCI-specific stuff. |
| 3425 | */ | 3425 | */ |
| 3426 | case USB_PORT_FEAT_TEST: | 3426 | case USB_PORT_FEAT_TEST: |
| 3427 | if (!selector || selector > 5) | 3427 | if (!selector || selector > 5) |
| 3428 | goto error; | 3428 | goto error; |
| 3429 | ehci_quiesce(oxu); | 3429 | ehci_quiesce(oxu); |
| 3430 | ehci_halt(oxu); | 3430 | ehci_halt(oxu); |
| 3431 | temp |= selector << 16; | 3431 | temp |= selector << 16; |
| 3432 | writel(temp, status_reg); | 3432 | writel(temp, status_reg); |
| 3433 | break; | 3433 | break; |
| 3434 | 3434 | ||
| 3435 | default: | 3435 | default: |
| 3436 | goto error; | 3436 | goto error; |
| 3437 | } | 3437 | } |
| 3438 | readl(&oxu->regs->command); /* unblock posted writes */ | 3438 | readl(&oxu->regs->command); /* unblock posted writes */ |
| 3439 | break; | 3439 | break; |
| 3440 | 3440 | ||
| 3441 | default: | 3441 | default: |
| 3442 | error: | 3442 | error: |
| 3443 | /* "stall" on error */ | 3443 | /* "stall" on error */ |
| 3444 | retval = -EPIPE; | 3444 | retval = -EPIPE; |
| 3445 | } | 3445 | } |
| 3446 | spin_unlock_irqrestore(&oxu->lock, flags); | 3446 | spin_unlock_irqrestore(&oxu->lock, flags); |
| 3447 | return retval; | 3447 | return retval; |
| 3448 | } | 3448 | } |
| 3449 | 3449 | ||
| 3450 | #ifdef CONFIG_PM | 3450 | #ifdef CONFIG_PM |
| 3451 | 3451 | ||
| 3452 | static int oxu_bus_suspend(struct usb_hcd *hcd) | 3452 | static int oxu_bus_suspend(struct usb_hcd *hcd) |
| 3453 | { | 3453 | { |
| 3454 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 3454 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 3455 | int port; | 3455 | int port; |
| 3456 | int mask; | 3456 | int mask; |
| 3457 | 3457 | ||
| 3458 | oxu_dbg(oxu, "suspend root hub\n"); | 3458 | oxu_dbg(oxu, "suspend root hub\n"); |
| 3459 | 3459 | ||
| 3460 | if (time_before(jiffies, oxu->next_statechange)) | 3460 | if (time_before(jiffies, oxu->next_statechange)) |
| 3461 | msleep(5); | 3461 | msleep(5); |
| 3462 | 3462 | ||
| 3463 | port = HCS_N_PORTS(oxu->hcs_params); | 3463 | port = HCS_N_PORTS(oxu->hcs_params); |
| 3464 | spin_lock_irq(&oxu->lock); | 3464 | spin_lock_irq(&oxu->lock); |
| 3465 | 3465 | ||
| 3466 | /* stop schedules, clean any completed work */ | 3466 | /* stop schedules, clean any completed work */ |
| 3467 | if (HC_IS_RUNNING(hcd->state)) { | 3467 | if (HC_IS_RUNNING(hcd->state)) { |
| 3468 | ehci_quiesce(oxu); | 3468 | ehci_quiesce(oxu); |
| 3469 | hcd->state = HC_STATE_QUIESCING; | 3469 | hcd->state = HC_STATE_QUIESCING; |
| 3470 | } | 3470 | } |
| 3471 | oxu->command = readl(&oxu->regs->command); | 3471 | oxu->command = readl(&oxu->regs->command); |
| 3472 | if (oxu->reclaim) | 3472 | if (oxu->reclaim) |
| 3473 | oxu->reclaim_ready = 1; | 3473 | oxu->reclaim_ready = 1; |
| 3474 | ehci_work(oxu); | 3474 | ehci_work(oxu); |
| 3475 | 3475 | ||
| 3476 | /* Unlike other USB host controller types, EHCI doesn't have | 3476 | /* Unlike other USB host controller types, EHCI doesn't have |
| 3477 | * any notion of "global" or bus-wide suspend. The driver has | 3477 | * any notion of "global" or bus-wide suspend. The driver has |
| 3478 | * to manually suspend all the active unsuspended ports, and | 3478 | * to manually suspend all the active unsuspended ports, and |
| 3479 | * then manually resume them in the bus_resume() routine. | 3479 | * then manually resume them in the bus_resume() routine. |
| 3480 | */ | 3480 | */ |
| 3481 | oxu->bus_suspended = 0; | 3481 | oxu->bus_suspended = 0; |
| 3482 | while (port--) { | 3482 | while (port--) { |
| 3483 | u32 __iomem *reg = &oxu->regs->port_status[port]; | 3483 | u32 __iomem *reg = &oxu->regs->port_status[port]; |
| 3484 | u32 t1 = readl(reg) & ~PORT_RWC_BITS; | 3484 | u32 t1 = readl(reg) & ~PORT_RWC_BITS; |
| 3485 | u32 t2 = t1; | 3485 | u32 t2 = t1; |
| 3486 | 3486 | ||
| 3487 | /* keep track of which ports we suspend */ | 3487 | /* keep track of which ports we suspend */ |
| 3488 | if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) && | 3488 | if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) && |
| 3489 | !(t1 & PORT_SUSPEND)) { | 3489 | !(t1 & PORT_SUSPEND)) { |
| 3490 | t2 |= PORT_SUSPEND; | 3490 | t2 |= PORT_SUSPEND; |
| 3491 | set_bit(port, &oxu->bus_suspended); | 3491 | set_bit(port, &oxu->bus_suspended); |
| 3492 | } | 3492 | } |
| 3493 | 3493 | ||
| 3494 | /* enable remote wakeup on all ports */ | 3494 | /* enable remote wakeup on all ports */ |
| 3495 | if (device_may_wakeup(&hcd->self.root_hub->dev)) | 3495 | if (device_may_wakeup(&hcd->self.root_hub->dev)) |
| 3496 | t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E; | 3496 | t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E; |
| 3497 | else | 3497 | else |
| 3498 | t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E); | 3498 | t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E); |
| 3499 | 3499 | ||
| 3500 | if (t1 != t2) { | 3500 | if (t1 != t2) { |
| 3501 | oxu_vdbg(oxu, "port %d, %08x -> %08x\n", | 3501 | oxu_vdbg(oxu, "port %d, %08x -> %08x\n", |
| 3502 | port + 1, t1, t2); | 3502 | port + 1, t1, t2); |
| 3503 | writel(t2, reg); | 3503 | writel(t2, reg); |
| 3504 | } | 3504 | } |
| 3505 | } | 3505 | } |
| 3506 | 3506 | ||
| 3507 | /* turn off now-idle HC */ | 3507 | /* turn off now-idle HC */ |
| 3508 | del_timer_sync(&oxu->watchdog); | 3508 | del_timer_sync(&oxu->watchdog); |
| 3509 | ehci_halt(oxu); | 3509 | ehci_halt(oxu); |
| 3510 | hcd->state = HC_STATE_SUSPENDED; | 3510 | hcd->state = HC_STATE_SUSPENDED; |
| 3511 | 3511 | ||
| 3512 | /* allow remote wakeup */ | 3512 | /* allow remote wakeup */ |
| 3513 | mask = INTR_MASK; | 3513 | mask = INTR_MASK; |
| 3514 | if (!device_may_wakeup(&hcd->self.root_hub->dev)) | 3514 | if (!device_may_wakeup(&hcd->self.root_hub->dev)) |
| 3515 | mask &= ~STS_PCD; | 3515 | mask &= ~STS_PCD; |
| 3516 | writel(mask, &oxu->regs->intr_enable); | 3516 | writel(mask, &oxu->regs->intr_enable); |
| 3517 | readl(&oxu->regs->intr_enable); | 3517 | readl(&oxu->regs->intr_enable); |
| 3518 | 3518 | ||
| 3519 | oxu->next_statechange = jiffies + msecs_to_jiffies(10); | 3519 | oxu->next_statechange = jiffies + msecs_to_jiffies(10); |
| 3520 | spin_unlock_irq(&oxu->lock); | 3520 | spin_unlock_irq(&oxu->lock); |
| 3521 | return 0; | 3521 | return 0; |
| 3522 | } | 3522 | } |
| 3523 | 3523 | ||
| 3524 | /* Caller has locked the root hub, and should reset/reinit on error */ | 3524 | /* Caller has locked the root hub, and should reset/reinit on error */ |
| 3525 | static int oxu_bus_resume(struct usb_hcd *hcd) | 3525 | static int oxu_bus_resume(struct usb_hcd *hcd) |
| 3526 | { | 3526 | { |
| 3527 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); | 3527 | struct oxu_hcd *oxu = hcd_to_oxu(hcd); |
| 3528 | u32 temp; | 3528 | u32 temp; |
| 3529 | int i; | 3529 | int i; |
| 3530 | 3530 | ||
| 3531 | if (time_before(jiffies, oxu->next_statechange)) | 3531 | if (time_before(jiffies, oxu->next_statechange)) |
| 3532 | msleep(5); | 3532 | msleep(5); |
| 3533 | spin_lock_irq(&oxu->lock); | 3533 | spin_lock_irq(&oxu->lock); |
| 3534 | 3534 | ||
| 3535 | /* Ideally and we've got a real resume here, and no port's power | 3535 | /* Ideally and we've got a real resume here, and no port's power |
| 3536 | * was lost. (For PCI, that means Vaux was maintained.) But we | 3536 | * was lost. (For PCI, that means Vaux was maintained.) But we |
| 3537 | * could instead be restoring a swsusp snapshot -- so that BIOS was | 3537 | * could instead be restoring a swsusp snapshot -- so that BIOS was |
| 3538 | * the last user of the controller, not reset/pm hardware keeping | 3538 | * the last user of the controller, not reset/pm hardware keeping |
| 3539 | * state we gave to it. | 3539 | * state we gave to it. |
| 3540 | */ | 3540 | */ |
| 3541 | temp = readl(&oxu->regs->intr_enable); | 3541 | temp = readl(&oxu->regs->intr_enable); |
| 3542 | oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss"); | 3542 | oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss"); |
| 3543 | 3543 | ||
| 3544 | /* at least some APM implementations will try to deliver | 3544 | /* at least some APM implementations will try to deliver |
| 3545 | * IRQs right away, so delay them until we're ready. | 3545 | * IRQs right away, so delay them until we're ready. |
| 3546 | */ | 3546 | */ |
| 3547 | writel(0, &oxu->regs->intr_enable); | 3547 | writel(0, &oxu->regs->intr_enable); |
| 3548 | 3548 | ||
| 3549 | /* re-init operational registers */ | 3549 | /* re-init operational registers */ |
| 3550 | writel(0, &oxu->regs->segment); | 3550 | writel(0, &oxu->regs->segment); |
| 3551 | writel(oxu->periodic_dma, &oxu->regs->frame_list); | 3551 | writel(oxu->periodic_dma, &oxu->regs->frame_list); |
| 3552 | writel((u32) oxu->async->qh_dma, &oxu->regs->async_next); | 3552 | writel((u32) oxu->async->qh_dma, &oxu->regs->async_next); |
| 3553 | 3553 | ||
| 3554 | /* restore CMD_RUN, framelist size, and irq threshold */ | 3554 | /* restore CMD_RUN, framelist size, and irq threshold */ |
| 3555 | writel(oxu->command, &oxu->regs->command); | 3555 | writel(oxu->command, &oxu->regs->command); |
| 3556 | 3556 | ||
| 3557 | /* Some controller/firmware combinations need a delay during which | 3557 | /* Some controller/firmware combinations need a delay during which |
| 3558 | * they set up the port statuses. See Bugzilla #8190. */ | 3558 | * they set up the port statuses. See Bugzilla #8190. */ |
| 3559 | mdelay(8); | 3559 | mdelay(8); |
| 3560 | 3560 | ||
| 3561 | /* manually resume the ports we suspended during bus_suspend() */ | 3561 | /* manually resume the ports we suspended during bus_suspend() */ |
| 3562 | i = HCS_N_PORTS(oxu->hcs_params); | 3562 | i = HCS_N_PORTS(oxu->hcs_params); |
| 3563 | while (i--) { | 3563 | while (i--) { |
| 3564 | temp = readl(&oxu->regs->port_status[i]); | 3564 | temp = readl(&oxu->regs->port_status[i]); |
| 3565 | temp &= ~(PORT_RWC_BITS | 3565 | temp &= ~(PORT_RWC_BITS |
| 3566 | | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E); | 3566 | | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E); |
| 3567 | if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) { | 3567 | if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) { |
| 3568 | oxu->reset_done[i] = jiffies + msecs_to_jiffies(20); | 3568 | oxu->reset_done[i] = jiffies + msecs_to_jiffies(20); |
| 3569 | temp |= PORT_RESUME; | 3569 | temp |= PORT_RESUME; |
| 3570 | } | 3570 | } |
| 3571 | writel(temp, &oxu->regs->port_status[i]); | 3571 | writel(temp, &oxu->regs->port_status[i]); |
| 3572 | } | 3572 | } |
| 3573 | i = HCS_N_PORTS(oxu->hcs_params); | 3573 | i = HCS_N_PORTS(oxu->hcs_params); |
| 3574 | mdelay(20); | 3574 | mdelay(20); |
| 3575 | while (i--) { | 3575 | while (i--) { |
| 3576 | temp = readl(&oxu->regs->port_status[i]); | 3576 | temp = readl(&oxu->regs->port_status[i]); |
| 3577 | if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) { | 3577 | if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) { |
| 3578 | temp &= ~(PORT_RWC_BITS | PORT_RESUME); | 3578 | temp &= ~(PORT_RWC_BITS | PORT_RESUME); |
| 3579 | writel(temp, &oxu->regs->port_status[i]); | 3579 | writel(temp, &oxu->regs->port_status[i]); |
| 3580 | oxu_vdbg(oxu, "resumed port %d\n", i + 1); | 3580 | oxu_vdbg(oxu, "resumed port %d\n", i + 1); |
| 3581 | } | 3581 | } |
| 3582 | } | 3582 | } |
| 3583 | (void) readl(&oxu->regs->command); | 3583 | (void) readl(&oxu->regs->command); |
| 3584 | 3584 | ||
| 3585 | /* maybe re-activate the schedule(s) */ | 3585 | /* maybe re-activate the schedule(s) */ |
| 3586 | temp = 0; | 3586 | temp = 0; |
| 3587 | if (oxu->async->qh_next.qh) | 3587 | if (oxu->async->qh_next.qh) |
| 3588 | temp |= CMD_ASE; | 3588 | temp |= CMD_ASE; |
| 3589 | if (oxu->periodic_sched) | 3589 | if (oxu->periodic_sched) |
| 3590 | temp |= CMD_PSE; | 3590 | temp |= CMD_PSE; |
| 3591 | if (temp) { | 3591 | if (temp) { |
| 3592 | oxu->command |= temp; | 3592 | oxu->command |= temp; |
| 3593 | writel(oxu->command, &oxu->regs->command); | 3593 | writel(oxu->command, &oxu->regs->command); |
| 3594 | } | 3594 | } |
| 3595 | 3595 | ||
| 3596 | oxu->next_statechange = jiffies + msecs_to_jiffies(5); | 3596 | oxu->next_statechange = jiffies + msecs_to_jiffies(5); |
| 3597 | hcd->state = HC_STATE_RUNNING; | 3597 | hcd->state = HC_STATE_RUNNING; |
| 3598 | 3598 | ||
| 3599 | /* Now we can safely re-enable irqs */ | 3599 | /* Now we can safely re-enable irqs */ |
| 3600 | writel(INTR_MASK, &oxu->regs->intr_enable); | 3600 | writel(INTR_MASK, &oxu->regs->intr_enable); |
| 3601 | 3601 | ||
| 3602 | spin_unlock_irq(&oxu->lock); | 3602 | spin_unlock_irq(&oxu->lock); |
| 3603 | return 0; | 3603 | return 0; |
| 3604 | } | 3604 | } |
| 3605 | 3605 | ||
| 3606 | #else | 3606 | #else |
| 3607 | 3607 | ||
| 3608 | static int oxu_bus_suspend(struct usb_hcd *hcd) | 3608 | static int oxu_bus_suspend(struct usb_hcd *hcd) |
| 3609 | { | 3609 | { |
| 3610 | return 0; | 3610 | return 0; |
| 3611 | } | 3611 | } |
| 3612 | 3612 | ||
| 3613 | static int oxu_bus_resume(struct usb_hcd *hcd) | 3613 | static int oxu_bus_resume(struct usb_hcd *hcd) |
| 3614 | { | 3614 | { |
| 3615 | return 0; | 3615 | return 0; |
| 3616 | } | 3616 | } |
| 3617 | 3617 | ||
| 3618 | #endif /* CONFIG_PM */ | 3618 | #endif /* CONFIG_PM */ |
| 3619 | 3619 | ||
| 3620 | static const struct hc_driver oxu_hc_driver = { | 3620 | static const struct hc_driver oxu_hc_driver = { |
| 3621 | .description = "oxu210hp_hcd", | 3621 | .description = "oxu210hp_hcd", |
| 3622 | .product_desc = "oxu210hp HCD", | 3622 | .product_desc = "oxu210hp HCD", |
| 3623 | .hcd_priv_size = sizeof(struct oxu_hcd), | 3623 | .hcd_priv_size = sizeof(struct oxu_hcd), |
| 3624 | 3624 | ||
| 3625 | /* | 3625 | /* |
| 3626 | * Generic hardware linkage | 3626 | * Generic hardware linkage |
| 3627 | */ | 3627 | */ |
| 3628 | .irq = oxu_irq, | 3628 | .irq = oxu_irq, |
| 3629 | .flags = HCD_MEMORY | HCD_USB2, | 3629 | .flags = HCD_MEMORY | HCD_USB2, |
| 3630 | 3630 | ||
| 3631 | /* | 3631 | /* |
| 3632 | * Basic lifecycle operations | 3632 | * Basic lifecycle operations |
| 3633 | */ | 3633 | */ |
| 3634 | .reset = oxu_reset, | 3634 | .reset = oxu_reset, |
| 3635 | .start = oxu_run, | 3635 | .start = oxu_run, |
| 3636 | .stop = oxu_stop, | 3636 | .stop = oxu_stop, |
| 3637 | .shutdown = oxu_shutdown, | 3637 | .shutdown = oxu_shutdown, |
| 3638 | 3638 | ||
| 3639 | /* | 3639 | /* |
| 3640 | * Managing i/o requests and associated device resources | 3640 | * Managing i/o requests and associated device resources |
| 3641 | */ | 3641 | */ |
| 3642 | .urb_enqueue = oxu_urb_enqueue, | 3642 | .urb_enqueue = oxu_urb_enqueue, |
| 3643 | .urb_dequeue = oxu_urb_dequeue, | 3643 | .urb_dequeue = oxu_urb_dequeue, |
| 3644 | .endpoint_disable = oxu_endpoint_disable, | 3644 | .endpoint_disable = oxu_endpoint_disable, |
| 3645 | 3645 | ||
| 3646 | /* | 3646 | /* |
| 3647 | * Scheduling support | 3647 | * Scheduling support |
| 3648 | */ | 3648 | */ |
| 3649 | .get_frame_number = oxu_get_frame, | 3649 | .get_frame_number = oxu_get_frame, |
| 3650 | 3650 | ||
| 3651 | /* | 3651 | /* |
| 3652 | * Root hub support | 3652 | * Root hub support |
| 3653 | */ | 3653 | */ |
| 3654 | .hub_status_data = oxu_hub_status_data, | 3654 | .hub_status_data = oxu_hub_status_data, |
| 3655 | .hub_control = oxu_hub_control, | 3655 | .hub_control = oxu_hub_control, |
| 3656 | .bus_suspend = oxu_bus_suspend, | 3656 | .bus_suspend = oxu_bus_suspend, |
| 3657 | .bus_resume = oxu_bus_resume, | 3657 | .bus_resume = oxu_bus_resume, |
| 3658 | }; | 3658 | }; |
| 3659 | 3659 | ||
| 3660 | /* | 3660 | /* |
| 3661 | * Module stuff | 3661 | * Module stuff |
| 3662 | */ | 3662 | */ |
| 3663 | 3663 | ||
| 3664 | static void oxu_configuration(struct platform_device *pdev, void *base) | 3664 | static void oxu_configuration(struct platform_device *pdev, void *base) |
| 3665 | { | 3665 | { |
| 3666 | u32 tmp; | 3666 | u32 tmp; |
| 3667 | 3667 | ||
| 3668 | /* Initialize top level registers. | 3668 | /* Initialize top level registers. |
| 3669 | * First write ever | 3669 | * First write ever |
| 3670 | */ | 3670 | */ |
| 3671 | oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); | 3671 | oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); |
| 3672 | oxu_writel(base, OXU_SOFTRESET, OXU_SRESET); | 3672 | oxu_writel(base, OXU_SOFTRESET, OXU_SRESET); |
| 3673 | oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); | 3673 | oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); |
| 3674 | 3674 | ||
| 3675 | tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL); | 3675 | tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL); |
| 3676 | oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040); | 3676 | oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040); |
| 3677 | 3677 | ||
| 3678 | oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN | | 3678 | oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN | |
| 3679 | OXU_COMPARATOR | OXU_ASO_OP); | 3679 | OXU_COMPARATOR | OXU_ASO_OP); |
| 3680 | 3680 | ||
| 3681 | tmp = oxu_readl(base, OXU_CLKCTRL_SET); | 3681 | tmp = oxu_readl(base, OXU_CLKCTRL_SET); |
| 3682 | oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN); | 3682 | oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN); |
| 3683 | 3683 | ||
| 3684 | /* Clear all top interrupt enable */ | 3684 | /* Clear all top interrupt enable */ |
| 3685 | oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff); | 3685 | oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff); |
| 3686 | 3686 | ||
| 3687 | /* Clear all top interrupt status */ | 3687 | /* Clear all top interrupt status */ |
| 3688 | oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff); | 3688 | oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff); |
| 3689 | 3689 | ||
| 3690 | /* Enable all needed top interrupt except OTG SPH core */ | 3690 | /* Enable all needed top interrupt except OTG SPH core */ |
| 3691 | oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI); | 3691 | oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI); |
| 3692 | } | 3692 | } |
| 3693 | 3693 | ||
| 3694 | static int oxu_verify_id(struct platform_device *pdev, void *base) | 3694 | static int oxu_verify_id(struct platform_device *pdev, void *base) |
| 3695 | { | 3695 | { |
| 3696 | u32 id; | 3696 | u32 id; |
| 3697 | static const char * const bo[] = { | 3697 | static const char * const bo[] = { |
| 3698 | "reserved", | 3698 | "reserved", |
| 3699 | "128-pin LQFP", | 3699 | "128-pin LQFP", |
| 3700 | "84-pin TFBGA", | 3700 | "84-pin TFBGA", |
| 3701 | "reserved", | 3701 | "reserved", |
| 3702 | }; | 3702 | }; |
| 3703 | 3703 | ||
| 3704 | /* Read controller signature register to find a match */ | 3704 | /* Read controller signature register to find a match */ |
| 3705 | id = oxu_readl(base, OXU_DEVICEID); | 3705 | id = oxu_readl(base, OXU_DEVICEID); |
| 3706 | dev_info(&pdev->dev, "device ID %x\n", id); | 3706 | dev_info(&pdev->dev, "device ID %x\n", id); |
| 3707 | if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT)) | 3707 | if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT)) |
| 3708 | return -1; | 3708 | return -1; |
| 3709 | 3709 | ||
| 3710 | dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n", | 3710 | dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n", |
| 3711 | id >> OXU_REV_SHIFT, | 3711 | id >> OXU_REV_SHIFT, |
| 3712 | bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT], | 3712 | bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT], |
| 3713 | (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT, | 3713 | (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT, |
| 3714 | (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT); | 3714 | (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT); |
| 3715 | 3715 | ||
| 3716 | return 0; | 3716 | return 0; |
| 3717 | } | 3717 | } |
| 3718 | 3718 | ||
| 3719 | static const struct hc_driver oxu_hc_driver; | 3719 | static const struct hc_driver oxu_hc_driver; |
| 3720 | static struct usb_hcd *oxu_create(struct platform_device *pdev, | 3720 | static struct usb_hcd *oxu_create(struct platform_device *pdev, |
| 3721 | unsigned long memstart, unsigned long memlen, | 3721 | unsigned long memstart, unsigned long memlen, |
| 3722 | void *base, int irq, int otg) | 3722 | void *base, int irq, int otg) |
| 3723 | { | 3723 | { |
| 3724 | struct device *dev = &pdev->dev; | 3724 | struct device *dev = &pdev->dev; |
| 3725 | 3725 | ||
| 3726 | struct usb_hcd *hcd; | 3726 | struct usb_hcd *hcd; |
| 3727 | struct oxu_hcd *oxu; | 3727 | struct oxu_hcd *oxu; |
| 3728 | int ret; | 3728 | int ret; |
| 3729 | 3729 | ||
| 3730 | /* Set endian mode and host mode */ | 3730 | /* Set endian mode and host mode */ |
| 3731 | oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET), | 3731 | oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET), |
| 3732 | OXU_USBMODE, | 3732 | OXU_USBMODE, |
| 3733 | OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS); | 3733 | OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS); |
| 3734 | 3734 | ||
| 3735 | hcd = usb_create_hcd(&oxu_hc_driver, dev, | 3735 | hcd = usb_create_hcd(&oxu_hc_driver, dev, |
| 3736 | otg ? "oxu210hp_otg" : "oxu210hp_sph"); | 3736 | otg ? "oxu210hp_otg" : "oxu210hp_sph"); |
| 3737 | if (!hcd) | 3737 | if (!hcd) |
| 3738 | return ERR_PTR(-ENOMEM); | 3738 | return ERR_PTR(-ENOMEM); |
| 3739 | 3739 | ||
| 3740 | hcd->rsrc_start = memstart; | 3740 | hcd->rsrc_start = memstart; |
| 3741 | hcd->rsrc_len = memlen; | 3741 | hcd->rsrc_len = memlen; |
| 3742 | hcd->regs = base; | 3742 | hcd->regs = base; |
| 3743 | hcd->irq = irq; | 3743 | hcd->irq = irq; |
| 3744 | hcd->state = HC_STATE_HALT; | 3744 | hcd->state = HC_STATE_HALT; |
| 3745 | 3745 | ||
| 3746 | oxu = hcd_to_oxu(hcd); | 3746 | oxu = hcd_to_oxu(hcd); |
| 3747 | oxu->is_otg = otg; | 3747 | oxu->is_otg = otg; |
| 3748 | 3748 | ||
| 3749 | ret = usb_add_hcd(hcd, irq, IRQF_SHARED); | 3749 | ret = usb_add_hcd(hcd, irq, IRQF_SHARED); |
| 3750 | if (ret < 0) | 3750 | if (ret < 0) |
| 3751 | return ERR_PTR(ret); | 3751 | return ERR_PTR(ret); |
| 3752 | 3752 | ||
| 3753 | device_wakeup_enable(hcd->self.controller); | 3753 | device_wakeup_enable(hcd->self.controller); |
| 3754 | return hcd; | 3754 | return hcd; |
| 3755 | } | 3755 | } |
| 3756 | 3756 | ||
| 3757 | static int oxu_init(struct platform_device *pdev, | 3757 | static int oxu_init(struct platform_device *pdev, |
| 3758 | unsigned long memstart, unsigned long memlen, | 3758 | unsigned long memstart, unsigned long memlen, |
| 3759 | void *base, int irq) | 3759 | void *base, int irq) |
| 3760 | { | 3760 | { |
| 3761 | struct oxu_info *info = platform_get_drvdata(pdev); | 3761 | struct oxu_info *info = platform_get_drvdata(pdev); |
| 3762 | struct usb_hcd *hcd; | 3762 | struct usb_hcd *hcd; |
| 3763 | int ret; | 3763 | int ret; |
| 3764 | 3764 | ||
| 3765 | /* First time configuration at start up */ | 3765 | /* First time configuration at start up */ |
| 3766 | oxu_configuration(pdev, base); | 3766 | oxu_configuration(pdev, base); |
| 3767 | 3767 | ||
| 3768 | ret = oxu_verify_id(pdev, base); | 3768 | ret = oxu_verify_id(pdev, base); |
| 3769 | if (ret) { | 3769 | if (ret) { |
| 3770 | dev_err(&pdev->dev, "no devices found!\n"); | 3770 | dev_err(&pdev->dev, "no devices found!\n"); |
| 3771 | return -ENODEV; | 3771 | return -ENODEV; |
| 3772 | } | 3772 | } |
| 3773 | 3773 | ||
| 3774 | /* Create the OTG controller */ | 3774 | /* Create the OTG controller */ |
| 3775 | hcd = oxu_create(pdev, memstart, memlen, base, irq, 1); | 3775 | hcd = oxu_create(pdev, memstart, memlen, base, irq, 1); |
| 3776 | if (IS_ERR(hcd)) { | 3776 | if (IS_ERR(hcd)) { |
| 3777 | dev_err(&pdev->dev, "cannot create OTG controller!\n"); | 3777 | dev_err(&pdev->dev, "cannot create OTG controller!\n"); |
| 3778 | ret = PTR_ERR(hcd); | 3778 | ret = PTR_ERR(hcd); |
| 3779 | goto error_create_otg; | 3779 | goto error_create_otg; |
| 3780 | } | 3780 | } |
| 3781 | info->hcd[0] = hcd; | 3781 | info->hcd[0] = hcd; |
| 3782 | 3782 | ||
| 3783 | /* Create the SPH host controller */ | 3783 | /* Create the SPH host controller */ |
| 3784 | hcd = oxu_create(pdev, memstart, memlen, base, irq, 0); | 3784 | hcd = oxu_create(pdev, memstart, memlen, base, irq, 0); |
| 3785 | if (IS_ERR(hcd)) { | 3785 | if (IS_ERR(hcd)) { |
| 3786 | dev_err(&pdev->dev, "cannot create SPH controller!\n"); | 3786 | dev_err(&pdev->dev, "cannot create SPH controller!\n"); |
| 3787 | ret = PTR_ERR(hcd); | 3787 | ret = PTR_ERR(hcd); |
| 3788 | goto error_create_sph; | 3788 | goto error_create_sph; |
| 3789 | } | 3789 | } |
| 3790 | info->hcd[1] = hcd; | 3790 | info->hcd[1] = hcd; |
| 3791 | 3791 | ||
| 3792 | oxu_writel(base, OXU_CHIPIRQEN_SET, | 3792 | oxu_writel(base, OXU_CHIPIRQEN_SET, |
| 3793 | oxu_readl(base, OXU_CHIPIRQEN_SET) | 3); | 3793 | oxu_readl(base, OXU_CHIPIRQEN_SET) | 3); |
| 3794 | 3794 | ||
| 3795 | return 0; | 3795 | return 0; |
| 3796 | 3796 | ||
| 3797 | error_create_sph: | 3797 | error_create_sph: |
| 3798 | usb_remove_hcd(info->hcd[0]); | 3798 | usb_remove_hcd(info->hcd[0]); |
| 3799 | usb_put_hcd(info->hcd[0]); | 3799 | usb_put_hcd(info->hcd[0]); |
| 3800 | 3800 | ||
| 3801 | error_create_otg: | 3801 | error_create_otg: |
| 3802 | return ret; | 3802 | return ret; |
| 3803 | } | 3803 | } |
| 3804 | 3804 | ||
| 3805 | static int oxu_drv_probe(struct platform_device *pdev) | 3805 | static int oxu_drv_probe(struct platform_device *pdev) |
| 3806 | { | 3806 | { |
| 3807 | struct resource *res; | 3807 | struct resource *res; |
| 3808 | void *base; | 3808 | void *base; |
| 3809 | unsigned long memstart, memlen; | 3809 | unsigned long memstart, memlen; |
| 3810 | int irq, ret; | 3810 | int irq, ret; |
| 3811 | struct oxu_info *info; | 3811 | struct oxu_info *info; |
| 3812 | 3812 | ||
| 3813 | if (usb_disabled()) | 3813 | if (usb_disabled()) |
| 3814 | return -ENODEV; | 3814 | return -ENODEV; |
| 3815 | 3815 | ||
| 3816 | /* | 3816 | /* |
| 3817 | * Get the platform resources | 3817 | * Get the platform resources |
| 3818 | */ | 3818 | */ |
| 3819 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 3819 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 3820 | if (!res) { | 3820 | if (!res) { |
| 3821 | dev_err(&pdev->dev, | 3821 | dev_err(&pdev->dev, |
| 3822 | "no IRQ! Check %s setup!\n", dev_name(&pdev->dev)); | 3822 | "no IRQ! Check %s setup!\n", dev_name(&pdev->dev)); |
| 3823 | return -ENODEV; | 3823 | return -ENODEV; |
| 3824 | } | 3824 | } |
| 3825 | irq = res->start; | 3825 | irq = res->start; |
| 3826 | dev_dbg(&pdev->dev, "IRQ resource %d\n", irq); | 3826 | dev_dbg(&pdev->dev, "IRQ resource %d\n", irq); |
| 3827 | 3827 | ||
| 3828 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 3828 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 3829 | base = devm_ioremap_resource(&pdev->dev, res); | 3829 | base = devm_ioremap_resource(&pdev->dev, res); |
| 3830 | if (IS_ERR(base)) { | 3830 | if (IS_ERR(base)) { |
| 3831 | ret = PTR_ERR(base); | 3831 | ret = PTR_ERR(base); |
| 3832 | goto error; | 3832 | goto error; |
| 3833 | } | 3833 | } |
| 3834 | memstart = res->start; | 3834 | memstart = res->start; |
| 3835 | memlen = resource_size(res); | 3835 | memlen = resource_size(res); |
| 3836 | 3836 | ||
| 3837 | ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING); | 3837 | ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING); |
| 3838 | if (ret) { | 3838 | if (ret) { |
| 3839 | dev_err(&pdev->dev, "error setting irq type\n"); | 3839 | dev_err(&pdev->dev, "error setting irq type\n"); |
| 3840 | ret = -EFAULT; | 3840 | ret = -EFAULT; |
| 3841 | goto error; | 3841 | goto error; |
| 3842 | } | 3842 | } |
| 3843 | 3843 | ||
| 3844 | /* Allocate a driver data struct to hold useful info for both | 3844 | /* Allocate a driver data struct to hold useful info for both |
| 3845 | * SPH & OTG devices | 3845 | * SPH & OTG devices |
| 3846 | */ | 3846 | */ |
| 3847 | info = devm_kzalloc(&pdev->dev, sizeof(struct oxu_info), GFP_KERNEL); | 3847 | info = devm_kzalloc(&pdev->dev, sizeof(struct oxu_info), GFP_KERNEL); |
| 3848 | if (!info) { | 3848 | if (!info) { |
| 3849 | ret = -EFAULT; | 3849 | ret = -EFAULT; |
| 3850 | goto error; | 3850 | goto error; |
| 3851 | } | 3851 | } |
| 3852 | platform_set_drvdata(pdev, info); | 3852 | platform_set_drvdata(pdev, info); |
| 3853 | 3853 | ||
| 3854 | ret = oxu_init(pdev, memstart, memlen, base, irq); | 3854 | ret = oxu_init(pdev, memstart, memlen, base, irq); |
| 3855 | if (ret < 0) { | 3855 | if (ret < 0) { |
| 3856 | dev_dbg(&pdev->dev, "cannot init USB devices\n"); | 3856 | dev_dbg(&pdev->dev, "cannot init USB devices\n"); |
| 3857 | goto error; | 3857 | goto error; |
| 3858 | } | 3858 | } |
| 3859 | 3859 | ||
| 3860 | dev_info(&pdev->dev, "devices enabled and running\n"); | 3860 | dev_info(&pdev->dev, "devices enabled and running\n"); |
| 3861 | platform_set_drvdata(pdev, info); | 3861 | platform_set_drvdata(pdev, info); |
| 3862 | 3862 | ||
| 3863 | return 0; | 3863 | return 0; |
| 3864 | 3864 | ||
| 3865 | error: | 3865 | error: |
| 3866 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret); | 3866 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret); |
| 3867 | return ret; | 3867 | return ret; |
| 3868 | } | 3868 | } |
| 3869 | 3869 | ||
| 3870 | static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd) | 3870 | static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd) |
| 3871 | { | 3871 | { |
| 3872 | usb_remove_hcd(hcd); | 3872 | usb_remove_hcd(hcd); |
| 3873 | usb_put_hcd(hcd); | 3873 | usb_put_hcd(hcd); |
| 3874 | } | 3874 | } |
| 3875 | 3875 | ||
| 3876 | static int oxu_drv_remove(struct platform_device *pdev) | 3876 | static int oxu_drv_remove(struct platform_device *pdev) |
| 3877 | { | 3877 | { |
| 3878 | struct oxu_info *info = platform_get_drvdata(pdev); | 3878 | struct oxu_info *info = platform_get_drvdata(pdev); |
| 3879 | 3879 | ||
| 3880 | oxu_remove(pdev, info->hcd[0]); | 3880 | oxu_remove(pdev, info->hcd[0]); |
| 3881 | oxu_remove(pdev, info->hcd[1]); | 3881 | oxu_remove(pdev, info->hcd[1]); |
| 3882 | 3882 | ||
| 3883 | return 0; | 3883 | return 0; |
| 3884 | } | 3884 | } |
| 3885 | 3885 | ||
| 3886 | static void oxu_drv_shutdown(struct platform_device *pdev) | 3886 | static void oxu_drv_shutdown(struct platform_device *pdev) |
| 3887 | { | 3887 | { |
| 3888 | oxu_drv_remove(pdev); | 3888 | oxu_drv_remove(pdev); |
| 3889 | } | 3889 | } |
| 3890 | 3890 | ||
| 3891 | #if 0 | 3891 | #if 0 |
| 3892 | /* FIXME: TODO */ | 3892 | /* FIXME: TODO */ |
| 3893 | static int oxu_drv_suspend(struct device *dev) | 3893 | static int oxu_drv_suspend(struct device *dev) |
| 3894 | { | 3894 | { |
| 3895 | struct platform_device *pdev = to_platform_device(dev); | 3895 | struct platform_device *pdev = to_platform_device(dev); |
| 3896 | struct usb_hcd *hcd = dev_get_drvdata(dev); | 3896 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
| 3897 | 3897 | ||
| 3898 | return 0; | 3898 | return 0; |
| 3899 | } | 3899 | } |
| 3900 | 3900 | ||
| 3901 | static int oxu_drv_resume(struct device *dev) | 3901 | static int oxu_drv_resume(struct device *dev) |
| 3902 | { | 3902 | { |
| 3903 | struct platform_device *pdev = to_platform_device(dev); | 3903 | struct platform_device *pdev = to_platform_device(dev); |
| 3904 | struct usb_hcd *hcd = dev_get_drvdata(dev); | 3904 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
| 3905 | 3905 | ||
| 3906 | return 0; | 3906 | return 0; |
| 3907 | } | 3907 | } |
| 3908 | #else | 3908 | #else |
| 3909 | #define oxu_drv_suspend NULL | 3909 | #define oxu_drv_suspend NULL |
| 3910 | #define oxu_drv_resume NULL | 3910 | #define oxu_drv_resume NULL |
| 3911 | #endif | 3911 | #endif |
| 3912 | 3912 | ||
| 3913 | static struct platform_driver oxu_driver = { | 3913 | static struct platform_driver oxu_driver = { |
| 3914 | .probe = oxu_drv_probe, | 3914 | .probe = oxu_drv_probe, |
| 3915 | .remove = oxu_drv_remove, | 3915 | .remove = oxu_drv_remove, |
| 3916 | .shutdown = oxu_drv_shutdown, | 3916 | .shutdown = oxu_drv_shutdown, |
| 3917 | .suspend = oxu_drv_suspend, | 3917 | .suspend = oxu_drv_suspend, |
| 3918 | .resume = oxu_drv_resume, | 3918 | .resume = oxu_drv_resume, |
| 3919 | .driver = { | 3919 | .driver = { |
| 3920 | .name = "oxu210hp-hcd", | 3920 | .name = "oxu210hp-hcd", |
| 3921 | .bus = &platform_bus_type | 3921 | .bus = &platform_bus_type |
| 3922 | } | 3922 | } |
| 3923 | }; | 3923 | }; |
| 3924 | 3924 | ||
| 3925 | module_platform_driver(oxu_driver); | 3925 | module_platform_driver(oxu_driver); |
| 3926 | 3926 | ||
| 3927 | MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION); | 3927 | MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION); |
| 3928 | MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>"); | 3928 | MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>"); |
| 3929 | MODULE_LICENSE("GPL"); | 3929 | MODULE_LICENSE("GPL"); |
| 3930 | 3930 |
include/linux/devfreq.h
| 1 | /* | 1 | /* |
| 2 | * devfreq: Generic Dynamic Voltage and Frequency Scaling (DVFS) Framework | 2 | * devfreq: Generic Dynamic Voltage and Frequency Scaling (DVFS) Framework |
| 3 | * for Non-CPU Devices. | 3 | * for Non-CPU Devices. |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2011 Samsung Electronics | 5 | * Copyright (C) 2011 Samsung Electronics |
| 6 | * MyungJoo Ham <myungjoo.ham@samsung.com> | 6 | * MyungJoo Ham <myungjoo.ham@samsung.com> |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef __LINUX_DEVFREQ_H__ | 13 | #ifndef __LINUX_DEVFREQ_H__ |
| 14 | #define __LINUX_DEVFREQ_H__ | 14 | #define __LINUX_DEVFREQ_H__ |
| 15 | 15 | ||
| 16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
| 17 | #include <linux/notifier.h> | 17 | #include <linux/notifier.h> |
| 18 | #include <linux/pm_opp.h> | 18 | #include <linux/pm_opp.h> |
| 19 | 19 | ||
| 20 | #define DEVFREQ_NAME_LEN 16 | 20 | #define DEVFREQ_NAME_LEN 16 |
| 21 | 21 | ||
| 22 | struct devfreq; | 22 | struct devfreq; |
| 23 | 23 | ||
| 24 | /** | 24 | /** |
| 25 | * struct devfreq_dev_status - Data given from devfreq user device to | 25 | * struct devfreq_dev_status - Data given from devfreq user device to |
| 26 | * governors. Represents the performance | 26 | * governors. Represents the performance |
| 27 | * statistics. | 27 | * statistics. |
| 28 | * @total_time: The total time represented by this instance of | 28 | * @total_time: The total time represented by this instance of |
| 29 | * devfreq_dev_status | 29 | * devfreq_dev_status |
| 30 | * @busy_time: The time that the device was working among the | 30 | * @busy_time: The time that the device was working among the |
| 31 | * total_time. | 31 | * total_time. |
| 32 | * @current_frequency: The operating frequency. | 32 | * @current_frequency: The operating frequency. |
| 33 | * @private_data: An entry not specified by the devfreq framework. | 33 | * @private_data: An entry not specified by the devfreq framework. |
| 34 | * A device and a specific governor may have their | 34 | * A device and a specific governor may have their |
| 35 | * own protocol with private_data. However, because | 35 | * own protocol with private_data. However, because |
| 36 | * this is governor-specific, a governor using this | 36 | * this is governor-specific, a governor using this |
| 37 | * will be only compatible with devices aware of it. | 37 | * will be only compatible with devices aware of it. |
| 38 | */ | 38 | */ |
| 39 | struct devfreq_dev_status { | 39 | struct devfreq_dev_status { |
| 40 | /* both since the last measure */ | 40 | /* both since the last measure */ |
| 41 | unsigned long total_time; | 41 | unsigned long total_time; |
| 42 | unsigned long busy_time; | 42 | unsigned long busy_time; |
| 43 | unsigned long current_frequency; | 43 | unsigned long current_frequency; |
| 44 | void *private_data; | 44 | void *private_data; |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | /* | 47 | /* |
| 48 | * The resulting frequency should be at most this. (this bound is the | 48 | * The resulting frequency should be at most this. (this bound is the |
| 49 | * least upper bound; thus, the resulting freq should be lower or same) | 49 | * least upper bound; thus, the resulting freq should be lower or same) |
| 50 | * If the flag is not set, the resulting frequency should be at most the | 50 | * If the flag is not set, the resulting frequency should be at most the |
| 51 | * bound (greatest lower bound) | 51 | * bound (greatest lower bound) |
| 52 | */ | 52 | */ |
| 53 | #define DEVFREQ_FLAG_LEAST_UPPER_BOUND 0x1 | 53 | #define DEVFREQ_FLAG_LEAST_UPPER_BOUND 0x1 |
| 54 | 54 | ||
| 55 | /** | 55 | /** |
| 56 | * struct devfreq_dev_profile - Devfreq's user device profile | 56 | * struct devfreq_dev_profile - Devfreq's user device profile |
| 57 | * @initial_freq: The operating frequency when devfreq_add_device() is | 57 | * @initial_freq: The operating frequency when devfreq_add_device() is |
| 58 | * called. | 58 | * called. |
| 59 | * @polling_ms: The polling interval in ms. 0 disables polling. | 59 | * @polling_ms: The polling interval in ms. 0 disables polling. |
| 60 | * @target: The device should set its operating frequency at | 60 | * @target: The device should set its operating frequency at |
| 61 | * freq or lowest-upper-than-freq value. If freq is | 61 | * freq or lowest-upper-than-freq value. If freq is |
| 62 | * higher than any operable frequency, set maximum. | 62 | * higher than any operable frequency, set maximum. |
| 63 | * Before returning, target function should set | 63 | * Before returning, target function should set |
| 64 | * freq at the current frequency. | 64 | * freq at the current frequency. |
| 65 | * The "flags" parameter's possible values are | 65 | * The "flags" parameter's possible values are |
| 66 | * explained above with "DEVFREQ_FLAG_*" macros. | 66 | * explained above with "DEVFREQ_FLAG_*" macros. |
| 67 | * @get_dev_status: The device should provide the current performance | 67 | * @get_dev_status: The device should provide the current performance |
| 68 | * status to devfreq, which is used by governors. | 68 | * status to devfreq, which is used by governors. |
| 69 | * @get_cur_freq: The device should provide the current frequency | 69 | * @get_cur_freq: The device should provide the current frequency |
| 70 | * at which it is operating. | 70 | * at which it is operating. |
| 71 | * @exit: An optional callback that is called when devfreq | 71 | * @exit: An optional callback that is called when devfreq |
| 72 | * is removing the devfreq object due to error or | 72 | * is removing the devfreq object due to error or |
| 73 | * from devfreq_remove_device() call. If the user | 73 | * from devfreq_remove_device() call. If the user |
| 74 | * has registered devfreq->nb at a notifier-head, | 74 | * has registered devfreq->nb at a notifier-head, |
| 75 | * this is the time to unregister it. | 75 | * this is the time to unregister it. |
| 76 | * @freq_table: Optional list of frequencies to support statistics. | 76 | * @freq_table: Optional list of frequencies to support statistics. |
| 77 | * @max_state: The size of freq_table. | 77 | * @max_state: The size of freq_table. |
| 78 | */ | 78 | */ |
| 79 | struct devfreq_dev_profile { | 79 | struct devfreq_dev_profile { |
| 80 | unsigned long initial_freq; | 80 | unsigned long initial_freq; |
| 81 | unsigned int polling_ms; | 81 | unsigned int polling_ms; |
| 82 | 82 | ||
| 83 | int (*target)(struct device *dev, unsigned long *freq, u32 flags); | 83 | int (*target)(struct device *dev, unsigned long *freq, u32 flags); |
| 84 | int (*get_dev_status)(struct device *dev, | 84 | int (*get_dev_status)(struct device *dev, |
| 85 | struct devfreq_dev_status *stat); | 85 | struct devfreq_dev_status *stat); |
| 86 | int (*get_cur_freq)(struct device *dev, unsigned long *freq); | 86 | int (*get_cur_freq)(struct device *dev, unsigned long *freq); |
| 87 | void (*exit)(struct device *dev); | 87 | void (*exit)(struct device *dev); |
| 88 | 88 | ||
| 89 | unsigned int *freq_table; | 89 | unsigned int *freq_table; |
| 90 | unsigned int max_state; | 90 | unsigned int max_state; |
| 91 | }; | 91 | }; |
| 92 | 92 | ||
| 93 | /** | 93 | /** |
| 94 | * struct devfreq_governor - Devfreq policy governor | 94 | * struct devfreq_governor - Devfreq policy governor |
| 95 | * @node: list node - contains registered devfreq governors | 95 | * @node: list node - contains registered devfreq governors |
| 96 | * @name: Governor's name | 96 | * @name: Governor's name |
| 97 | * @get_target_freq: Returns desired operating frequency for the device. | 97 | * @get_target_freq: Returns desired operating frequency for the device. |
| 98 | * Basically, get_target_freq will run | 98 | * Basically, get_target_freq will run |
| 99 | * devfreq_dev_profile.get_dev_status() to get the | 99 | * devfreq_dev_profile.get_dev_status() to get the |
| 100 | * status of the device (load = busy_time / total_time). | 100 | * status of the device (load = busy_time / total_time). |
| 101 | * If no_central_polling is set, this callback is called | 101 | * If no_central_polling is set, this callback is called |
| 102 | * only with update_devfreq() notified by OPP. | 102 | * only with update_devfreq() notified by OPP. |
| 103 | * @event_handler: Callback for devfreq core framework to notify events | 103 | * @event_handler: Callback for devfreq core framework to notify events |
| 104 | * to governors. Events include per device governor | 104 | * to governors. Events include per device governor |
| 105 | * init and exit, opp changes out of devfreq, suspend | 105 | * init and exit, opp changes out of devfreq, suspend |
| 106 | * and resume of per device devfreq during device idle. | 106 | * and resume of per device devfreq during device idle. |
| 107 | * | 107 | * |
| 108 | * Note that the callbacks are called with devfreq->lock locked by devfreq. | 108 | * Note that the callbacks are called with devfreq->lock locked by devfreq. |
| 109 | */ | 109 | */ |
| 110 | struct devfreq_governor { | 110 | struct devfreq_governor { |
| 111 | struct list_head node; | 111 | struct list_head node; |
| 112 | 112 | ||
| 113 | const char name[DEVFREQ_NAME_LEN]; | 113 | const char name[DEVFREQ_NAME_LEN]; |
| 114 | int (*get_target_freq)(struct devfreq *this, unsigned long *freq); | 114 | int (*get_target_freq)(struct devfreq *this, unsigned long *freq); |
| 115 | int (*event_handler)(struct devfreq *devfreq, | 115 | int (*event_handler)(struct devfreq *devfreq, |
| 116 | unsigned int event, void *data); | 116 | unsigned int event, void *data); |
| 117 | }; | 117 | }; |
| 118 | 118 | ||
| 119 | /** | 119 | /** |
| 120 | * struct devfreq - Device devfreq structure | 120 | * struct devfreq - Device devfreq structure |
| 121 | * @node: list node - contains the devices with devfreq that have been | 121 | * @node: list node - contains the devices with devfreq that have been |
| 122 | * registered. | 122 | * registered. |
| 123 | * @lock: a mutex to protect accessing devfreq. | 123 | * @lock: a mutex to protect accessing devfreq. |
| 124 | * @dev: device registered by devfreq class. dev.parent is the device | 124 | * @dev: device registered by devfreq class. dev.parent is the device |
| 125 | * using devfreq. | 125 | * using devfreq. |
| 126 | * @profile: device-specific devfreq profile | 126 | * @profile: device-specific devfreq profile |
| 127 | * @governor: method how to choose frequency based on the usage. | 127 | * @governor: method how to choose frequency based on the usage. |
| 128 | * @governor_name: devfreq governor name for use with this devfreq | 128 | * @governor_name: devfreq governor name for use with this devfreq |
| 129 | * @nb: notifier block used to notify devfreq object that it should | 129 | * @nb: notifier block used to notify devfreq object that it should |
| 130 | * reevaluate operable frequencies. Devfreq users may use | 130 | * reevaluate operable frequencies. Devfreq users may use |
| 131 | * devfreq.nb to the corresponding register notifier call chain. | 131 | * devfreq.nb to the corresponding register notifier call chain. |
| 132 | * @work: delayed work for load monitoring. | 132 | * @work: delayed work for load monitoring. |
| 133 | * @previous_freq: previously configured frequency value. | 133 | * @previous_freq: previously configured frequency value. |
| 134 | * @data: Private data of the governor. The devfreq framework does not | 134 | * @data: Private data of the governor. The devfreq framework does not |
| 135 | * touch this. | 135 | * touch this. |
| 136 | * @min_freq: Limit minimum frequency requested by user (0: none) | 136 | * @min_freq: Limit minimum frequency requested by user (0: none) |
| 137 | * @max_freq: Limit maximum frequency requested by user (0: none) | 137 | * @max_freq: Limit maximum frequency requested by user (0: none) |
| 138 | * @stop_polling: devfreq polling status of a device. | 138 | * @stop_polling: devfreq polling status of a device. |
| 139 | * @total_trans: Number of devfreq transitions | 139 | * @total_trans: Number of devfreq transitions |
| 140 | * @trans_table: Statistics of devfreq transitions | 140 | * @trans_table: Statistics of devfreq transitions |
| 141 | * @time_in_state: Statistics of devfreq states | 141 | * @time_in_state: Statistics of devfreq states |
| 142 | * @last_stat_updated: The last time stat updated | 142 | * @last_stat_updated: The last time stat updated |
| 143 | * | 143 | * |
| 144 | * This structure stores the devfreq information for a give device. | 144 | * This structure stores the devfreq information for a give device. |
| 145 | * | 145 | * |
| 146 | * Note that when a governor accesses entries in struct devfreq in its | 146 | * Note that when a governor accesses entries in struct devfreq in its |
| 147 | * functions except for the context of callbacks defined in struct | 147 | * functions except for the context of callbacks defined in struct |
| 148 | * devfreq_governor, the governor should protect its access with the | 148 | * devfreq_governor, the governor should protect its access with the |
| 149 | * struct mutex lock in struct devfreq. A governor may use this mutex | 149 | * struct mutex lock in struct devfreq. A governor may use this mutex |
| 150 | * to protect its own private data in void *data as well. | 150 | * to protect its own private data in void *data as well. |
| 151 | */ | 151 | */ |
| 152 | struct devfreq { | 152 | struct devfreq { |
| 153 | struct list_head node; | 153 | struct list_head node; |
| 154 | 154 | ||
| 155 | struct mutex lock; | 155 | struct mutex lock; |
| 156 | struct device dev; | 156 | struct device dev; |
| 157 | struct devfreq_dev_profile *profile; | 157 | struct devfreq_dev_profile *profile; |
| 158 | const struct devfreq_governor *governor; | 158 | const struct devfreq_governor *governor; |
| 159 | char governor_name[DEVFREQ_NAME_LEN]; | 159 | char governor_name[DEVFREQ_NAME_LEN]; |
| 160 | struct notifier_block nb; | 160 | struct notifier_block nb; |
| 161 | struct delayed_work work; | 161 | struct delayed_work work; |
| 162 | 162 | ||
| 163 | unsigned long previous_freq; | 163 | unsigned long previous_freq; |
| 164 | 164 | ||
| 165 | void *data; /* private data for governors */ | 165 | void *data; /* private data for governors */ |
| 166 | 166 | ||
| 167 | unsigned long min_freq; | 167 | unsigned long min_freq; |
| 168 | unsigned long max_freq; | 168 | unsigned long max_freq; |
| 169 | bool stop_polling; | 169 | bool stop_polling; |
| 170 | 170 | ||
| 171 | /* information for device frequency transition */ | 171 | /* information for device frequency transition */ |
| 172 | unsigned int total_trans; | 172 | unsigned int total_trans; |
| 173 | unsigned int *trans_table; | 173 | unsigned int *trans_table; |
| 174 | unsigned long *time_in_state; | 174 | unsigned long *time_in_state; |
| 175 | unsigned long last_stat_updated; | 175 | unsigned long last_stat_updated; |
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | #if defined(CONFIG_PM_DEVFREQ) | 178 | #if defined(CONFIG_PM_DEVFREQ) |
| 179 | extern struct devfreq *devfreq_add_device(struct device *dev, | 179 | extern struct devfreq *devfreq_add_device(struct device *dev, |
| 180 | struct devfreq_dev_profile *profile, | 180 | struct devfreq_dev_profile *profile, |
| 181 | const char *governor_name, | 181 | const char *governor_name, |
| 182 | void *data); | 182 | void *data); |
| 183 | extern int devfreq_remove_device(struct devfreq *devfreq); | 183 | extern int devfreq_remove_device(struct devfreq *devfreq); |
| 184 | extern struct devfreq *devm_devfreq_add_device(struct device *dev, | 184 | extern struct devfreq *devm_devfreq_add_device(struct device *dev, |
| 185 | struct devfreq_dev_profile *profile, | 185 | struct devfreq_dev_profile *profile, |
| 186 | const char *governor_name, | 186 | const char *governor_name, |
| 187 | void *data); | 187 | void *data); |
| 188 | extern void devm_devfreq_remove_device(struct device *dev, | 188 | extern void devm_devfreq_remove_device(struct device *dev, |
| 189 | struct devfreq *devfreq); | 189 | struct devfreq *devfreq); |
| 190 | 190 | ||
| 191 | /* Supposed to be called by PM_SLEEP/PM_RUNTIME callbacks */ | 191 | /* Supposed to be called by PM callbacks */ |
| 192 | extern int devfreq_suspend_device(struct devfreq *devfreq); | 192 | extern int devfreq_suspend_device(struct devfreq *devfreq); |
| 193 | extern int devfreq_resume_device(struct devfreq *devfreq); | 193 | extern int devfreq_resume_device(struct devfreq *devfreq); |
| 194 | 194 | ||
| 195 | /* Helper functions for devfreq user device driver with OPP. */ | 195 | /* Helper functions for devfreq user device driver with OPP. */ |
| 196 | extern struct dev_pm_opp *devfreq_recommended_opp(struct device *dev, | 196 | extern struct dev_pm_opp *devfreq_recommended_opp(struct device *dev, |
| 197 | unsigned long *freq, u32 flags); | 197 | unsigned long *freq, u32 flags); |
| 198 | extern int devfreq_register_opp_notifier(struct device *dev, | 198 | extern int devfreq_register_opp_notifier(struct device *dev, |
| 199 | struct devfreq *devfreq); | 199 | struct devfreq *devfreq); |
| 200 | extern int devfreq_unregister_opp_notifier(struct device *dev, | 200 | extern int devfreq_unregister_opp_notifier(struct device *dev, |
| 201 | struct devfreq *devfreq); | 201 | struct devfreq *devfreq); |
| 202 | extern int devm_devfreq_register_opp_notifier(struct device *dev, | 202 | extern int devm_devfreq_register_opp_notifier(struct device *dev, |
| 203 | struct devfreq *devfreq); | 203 | struct devfreq *devfreq); |
| 204 | extern void devm_devfreq_unregister_opp_notifier(struct device *dev, | 204 | extern void devm_devfreq_unregister_opp_notifier(struct device *dev, |
| 205 | struct devfreq *devfreq); | 205 | struct devfreq *devfreq); |
| 206 | 206 | ||
| 207 | #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) | 207 | #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) |
| 208 | /** | 208 | /** |
| 209 | * struct devfreq_simple_ondemand_data - void *data fed to struct devfreq | 209 | * struct devfreq_simple_ondemand_data - void *data fed to struct devfreq |
| 210 | * and devfreq_add_device | 210 | * and devfreq_add_device |
| 211 | * @upthreshold: If the load is over this value, the frequency jumps. | 211 | * @upthreshold: If the load is over this value, the frequency jumps. |
| 212 | * Specify 0 to use the default. Valid value = 0 to 100. | 212 | * Specify 0 to use the default. Valid value = 0 to 100. |
| 213 | * @downdifferential: If the load is under upthreshold - downdifferential, | 213 | * @downdifferential: If the load is under upthreshold - downdifferential, |
| 214 | * the governor may consider slowing the frequency down. | 214 | * the governor may consider slowing the frequency down. |
| 215 | * Specify 0 to use the default. Valid value = 0 to 100. | 215 | * Specify 0 to use the default. Valid value = 0 to 100. |
| 216 | * downdifferential < upthreshold must hold. | 216 | * downdifferential < upthreshold must hold. |
| 217 | * | 217 | * |
| 218 | * If the fed devfreq_simple_ondemand_data pointer is NULL to the governor, | 218 | * If the fed devfreq_simple_ondemand_data pointer is NULL to the governor, |
| 219 | * the governor uses the default values. | 219 | * the governor uses the default values. |
| 220 | */ | 220 | */ |
| 221 | struct devfreq_simple_ondemand_data { | 221 | struct devfreq_simple_ondemand_data { |
| 222 | unsigned int upthreshold; | 222 | unsigned int upthreshold; |
| 223 | unsigned int downdifferential; | 223 | unsigned int downdifferential; |
| 224 | }; | 224 | }; |
| 225 | #endif | 225 | #endif |
| 226 | 226 | ||
| 227 | #else /* !CONFIG_PM_DEVFREQ */ | 227 | #else /* !CONFIG_PM_DEVFREQ */ |
| 228 | static inline struct devfreq *devfreq_add_device(struct device *dev, | 228 | static inline struct devfreq *devfreq_add_device(struct device *dev, |
| 229 | struct devfreq_dev_profile *profile, | 229 | struct devfreq_dev_profile *profile, |
| 230 | const char *governor_name, | 230 | const char *governor_name, |
| 231 | void *data) | 231 | void *data) |
| 232 | { | 232 | { |
| 233 | return ERR_PTR(-ENOSYS); | 233 | return ERR_PTR(-ENOSYS); |
| 234 | } | 234 | } |
| 235 | 235 | ||
| 236 | static inline int devfreq_remove_device(struct devfreq *devfreq) | 236 | static inline int devfreq_remove_device(struct devfreq *devfreq) |
| 237 | { | 237 | { |
| 238 | return 0; | 238 | return 0; |
| 239 | } | 239 | } |
| 240 | 240 | ||
| 241 | static inline struct devfreq *devm_devfreq_add_device(struct device *dev, | 241 | static inline struct devfreq *devm_devfreq_add_device(struct device *dev, |
| 242 | struct devfreq_dev_profile *profile, | 242 | struct devfreq_dev_profile *profile, |
| 243 | const char *governor_name, | 243 | const char *governor_name, |
| 244 | void *data) | 244 | void *data) |
| 245 | { | 245 | { |
| 246 | return ERR_PTR(-ENOSYS); | 246 | return ERR_PTR(-ENOSYS); |
| 247 | } | 247 | } |
| 248 | 248 | ||
| 249 | static inline void devm_devfreq_remove_device(struct device *dev, | 249 | static inline void devm_devfreq_remove_device(struct device *dev, |
| 250 | struct devfreq *devfreq) | 250 | struct devfreq *devfreq) |
| 251 | { | 251 | { |
| 252 | } | 252 | } |
| 253 | 253 | ||
| 254 | static inline int devfreq_suspend_device(struct devfreq *devfreq) | 254 | static inline int devfreq_suspend_device(struct devfreq *devfreq) |
| 255 | { | 255 | { |
| 256 | return 0; | 256 | return 0; |
| 257 | } | 257 | } |
| 258 | 258 | ||
| 259 | static inline int devfreq_resume_device(struct devfreq *devfreq) | 259 | static inline int devfreq_resume_device(struct devfreq *devfreq) |
| 260 | { | 260 | { |
| 261 | return 0; | 261 | return 0; |
| 262 | } | 262 | } |
| 263 | 263 | ||
| 264 | static inline struct dev_pm_opp *devfreq_recommended_opp(struct device *dev, | 264 | static inline struct dev_pm_opp *devfreq_recommended_opp(struct device *dev, |
| 265 | unsigned long *freq, u32 flags) | 265 | unsigned long *freq, u32 flags) |
| 266 | { | 266 | { |
| 267 | return ERR_PTR(-EINVAL); | 267 | return ERR_PTR(-EINVAL); |
| 268 | } | 268 | } |
| 269 | 269 | ||
| 270 | static inline int devfreq_register_opp_notifier(struct device *dev, | 270 | static inline int devfreq_register_opp_notifier(struct device *dev, |
| 271 | struct devfreq *devfreq) | 271 | struct devfreq *devfreq) |
| 272 | { | 272 | { |
| 273 | return -EINVAL; | 273 | return -EINVAL; |
| 274 | } | 274 | } |
| 275 | 275 | ||
| 276 | static inline int devfreq_unregister_opp_notifier(struct device *dev, | 276 | static inline int devfreq_unregister_opp_notifier(struct device *dev, |
| 277 | struct devfreq *devfreq) | 277 | struct devfreq *devfreq) |
| 278 | { | 278 | { |
| 279 | return -EINVAL; | 279 | return -EINVAL; |
| 280 | } | 280 | } |
| 281 | 281 | ||
| 282 | static inline int devm_devfreq_register_opp_notifier(struct device *dev, | 282 | static inline int devm_devfreq_register_opp_notifier(struct device *dev, |
| 283 | struct devfreq *devfreq) | 283 | struct devfreq *devfreq) |
| 284 | { | 284 | { |
| 285 | return -EINVAL; | 285 | return -EINVAL; |
| 286 | } | 286 | } |
| 287 | 287 | ||
| 288 | static inline void devm_devfreq_unregister_opp_notifier(struct device *dev, | 288 | static inline void devm_devfreq_unregister_opp_notifier(struct device *dev, |
| 289 | struct devfreq *devfreq) | 289 | struct devfreq *devfreq) |
| 290 | { | 290 | { |
| 291 | } | 291 | } |
| 292 | #endif /* CONFIG_PM_DEVFREQ */ | 292 | #endif /* CONFIG_PM_DEVFREQ */ |
| 293 | 293 | ||
| 294 | #endif /* __LINUX_DEVFREQ_H__ */ | 294 | #endif /* __LINUX_DEVFREQ_H__ */ |
| 295 | 295 |
kernel/power/Kconfig
| 1 | config SUSPEND | 1 | config SUSPEND |
| 2 | bool "Suspend to RAM and standby" | 2 | bool "Suspend to RAM and standby" |
| 3 | depends on ARCH_SUSPEND_POSSIBLE | 3 | depends on ARCH_SUSPEND_POSSIBLE |
| 4 | default y | 4 | default y |
| 5 | ---help--- | 5 | ---help--- |
| 6 | Allow the system to enter sleep states in which main memory is | 6 | Allow the system to enter sleep states in which main memory is |
| 7 | powered and thus its contents are preserved, such as the | 7 | powered and thus its contents are preserved, such as the |
| 8 | suspend-to-RAM state (e.g. the ACPI S3 state). | 8 | suspend-to-RAM state (e.g. the ACPI S3 state). |
| 9 | 9 | ||
| 10 | config SUSPEND_FREEZER | 10 | config SUSPEND_FREEZER |
| 11 | bool "Enable freezer for suspend to RAM/standby" \ | 11 | bool "Enable freezer for suspend to RAM/standby" \ |
| 12 | if ARCH_WANTS_FREEZER_CONTROL || BROKEN | 12 | if ARCH_WANTS_FREEZER_CONTROL || BROKEN |
| 13 | depends on SUSPEND | 13 | depends on SUSPEND |
| 14 | default y | 14 | default y |
| 15 | help | 15 | help |
| 16 | This allows you to turn off the freezer for suspend. If this is | 16 | This allows you to turn off the freezer for suspend. If this is |
| 17 | done, no tasks are frozen for suspend to RAM/standby. | 17 | done, no tasks are frozen for suspend to RAM/standby. |
| 18 | 18 | ||
| 19 | Turning OFF this setting is NOT recommended! If in doubt, say Y. | 19 | Turning OFF this setting is NOT recommended! If in doubt, say Y. |
| 20 | 20 | ||
| 21 | config HIBERNATE_CALLBACKS | 21 | config HIBERNATE_CALLBACKS |
| 22 | bool | 22 | bool |
| 23 | 23 | ||
| 24 | config HIBERNATION | 24 | config HIBERNATION |
| 25 | bool "Hibernation (aka 'suspend to disk')" | 25 | bool "Hibernation (aka 'suspend to disk')" |
| 26 | depends on SWAP && ARCH_HIBERNATION_POSSIBLE | 26 | depends on SWAP && ARCH_HIBERNATION_POSSIBLE |
| 27 | select HIBERNATE_CALLBACKS | 27 | select HIBERNATE_CALLBACKS |
| 28 | select LZO_COMPRESS | 28 | select LZO_COMPRESS |
| 29 | select LZO_DECOMPRESS | 29 | select LZO_DECOMPRESS |
| 30 | select CRC32 | 30 | select CRC32 |
| 31 | ---help--- | 31 | ---help--- |
| 32 | Enable the suspend to disk (STD) functionality, which is usually | 32 | Enable the suspend to disk (STD) functionality, which is usually |
| 33 | called "hibernation" in user interfaces. STD checkpoints the | 33 | called "hibernation" in user interfaces. STD checkpoints the |
| 34 | system and powers it off; and restores that checkpoint on reboot. | 34 | system and powers it off; and restores that checkpoint on reboot. |
| 35 | 35 | ||
| 36 | You can suspend your machine with 'echo disk > /sys/power/state' | 36 | You can suspend your machine with 'echo disk > /sys/power/state' |
| 37 | after placing resume=/dev/swappartition on the kernel command line | 37 | after placing resume=/dev/swappartition on the kernel command line |
| 38 | in your bootloader's configuration file. | 38 | in your bootloader's configuration file. |
| 39 | 39 | ||
| 40 | Alternatively, you can use the additional userland tools available | 40 | Alternatively, you can use the additional userland tools available |
| 41 | from <http://suspend.sf.net>. | 41 | from <http://suspend.sf.net>. |
| 42 | 42 | ||
| 43 | In principle it does not require ACPI or APM, although for example | 43 | In principle it does not require ACPI or APM, although for example |
| 44 | ACPI will be used for the final steps when it is available. One | 44 | ACPI will be used for the final steps when it is available. One |
| 45 | of the reasons to use software suspend is that the firmware hooks | 45 | of the reasons to use software suspend is that the firmware hooks |
| 46 | for suspend states like suspend-to-RAM (STR) often don't work very | 46 | for suspend states like suspend-to-RAM (STR) often don't work very |
| 47 | well with Linux. | 47 | well with Linux. |
| 48 | 48 | ||
| 49 | It creates an image which is saved in your active swap. Upon the next | 49 | It creates an image which is saved in your active swap. Upon the next |
| 50 | boot, pass the 'resume=/dev/swappartition' argument to the kernel to | 50 | boot, pass the 'resume=/dev/swappartition' argument to the kernel to |
| 51 | have it detect the saved image, restore memory state from it, and | 51 | have it detect the saved image, restore memory state from it, and |
| 52 | continue to run as before. If you do not want the previous state to | 52 | continue to run as before. If you do not want the previous state to |
| 53 | be reloaded, then use the 'noresume' kernel command line argument. | 53 | be reloaded, then use the 'noresume' kernel command line argument. |
| 54 | Note, however, that fsck will be run on your filesystems and you will | 54 | Note, however, that fsck will be run on your filesystems and you will |
| 55 | need to run mkswap against the swap partition used for the suspend. | 55 | need to run mkswap against the swap partition used for the suspend. |
| 56 | 56 | ||
| 57 | It also works with swap files to a limited extent (for details see | 57 | It also works with swap files to a limited extent (for details see |
| 58 | <file:Documentation/power/swsusp-and-swap-files.txt>). | 58 | <file:Documentation/power/swsusp-and-swap-files.txt>). |
| 59 | 59 | ||
| 60 | Right now you may boot without resuming and resume later but in the | 60 | Right now you may boot without resuming and resume later but in the |
| 61 | meantime you cannot use the swap partition(s)/file(s) involved in | 61 | meantime you cannot use the swap partition(s)/file(s) involved in |
| 62 | suspending. Also in this case you must not use the filesystems | 62 | suspending. Also in this case you must not use the filesystems |
| 63 | that were mounted before the suspend. In particular, you MUST NOT | 63 | that were mounted before the suspend. In particular, you MUST NOT |
| 64 | MOUNT any journaled filesystems mounted before the suspend or they | 64 | MOUNT any journaled filesystems mounted before the suspend or they |
| 65 | will get corrupted in a nasty way. | 65 | will get corrupted in a nasty way. |
| 66 | 66 | ||
| 67 | For more information take a look at <file:Documentation/power/swsusp.txt>. | 67 | For more information take a look at <file:Documentation/power/swsusp.txt>. |
| 68 | 68 | ||
| 69 | config ARCH_SAVE_PAGE_KEYS | 69 | config ARCH_SAVE_PAGE_KEYS |
| 70 | bool | 70 | bool |
| 71 | 71 | ||
| 72 | config PM_STD_PARTITION | 72 | config PM_STD_PARTITION |
| 73 | string "Default resume partition" | 73 | string "Default resume partition" |
| 74 | depends on HIBERNATION | 74 | depends on HIBERNATION |
| 75 | default "" | 75 | default "" |
| 76 | ---help--- | 76 | ---help--- |
| 77 | The default resume partition is the partition that the suspend- | 77 | The default resume partition is the partition that the suspend- |
| 78 | to-disk implementation will look for a suspended disk image. | 78 | to-disk implementation will look for a suspended disk image. |
| 79 | 79 | ||
| 80 | The partition specified here will be different for almost every user. | 80 | The partition specified here will be different for almost every user. |
| 81 | It should be a valid swap partition (at least for now) that is turned | 81 | It should be a valid swap partition (at least for now) that is turned |
| 82 | on before suspending. | 82 | on before suspending. |
| 83 | 83 | ||
| 84 | The partition specified can be overridden by specifying: | 84 | The partition specified can be overridden by specifying: |
| 85 | 85 | ||
| 86 | resume=/dev/<other device> | 86 | resume=/dev/<other device> |
| 87 | 87 | ||
| 88 | which will set the resume partition to the device specified. | 88 | which will set the resume partition to the device specified. |
| 89 | 89 | ||
| 90 | Note there is currently not a way to specify which device to save the | 90 | Note there is currently not a way to specify which device to save the |
| 91 | suspended image to. It will simply pick the first available swap | 91 | suspended image to. It will simply pick the first available swap |
| 92 | device. | 92 | device. |
| 93 | 93 | ||
| 94 | config PM_SLEEP | 94 | config PM_SLEEP |
| 95 | def_bool y | 95 | def_bool y |
| 96 | depends on SUSPEND || HIBERNATE_CALLBACKS | 96 | depends on SUSPEND || HIBERNATE_CALLBACKS |
| 97 | select PM_RUNTIME | 97 | select PM |
| 98 | 98 | ||
| 99 | config PM_SLEEP_SMP | 99 | config PM_SLEEP_SMP |
| 100 | def_bool y | 100 | def_bool y |
| 101 | depends on SMP | 101 | depends on SMP |
| 102 | depends on ARCH_SUSPEND_POSSIBLE || ARCH_HIBERNATION_POSSIBLE | 102 | depends on ARCH_SUSPEND_POSSIBLE || ARCH_HIBERNATION_POSSIBLE |
| 103 | depends on PM_SLEEP | 103 | depends on PM_SLEEP |
| 104 | select HOTPLUG_CPU | 104 | select HOTPLUG_CPU |
| 105 | 105 | ||
| 106 | config PM_AUTOSLEEP | 106 | config PM_AUTOSLEEP |
| 107 | bool "Opportunistic sleep" | 107 | bool "Opportunistic sleep" |
| 108 | depends on PM_SLEEP | 108 | depends on PM_SLEEP |
| 109 | default n | 109 | default n |
| 110 | ---help--- | 110 | ---help--- |
| 111 | Allow the kernel to trigger a system transition into a global sleep | 111 | Allow the kernel to trigger a system transition into a global sleep |
| 112 | state automatically whenever there are no active wakeup sources. | 112 | state automatically whenever there are no active wakeup sources. |
| 113 | 113 | ||
| 114 | config PM_WAKELOCKS | 114 | config PM_WAKELOCKS |
| 115 | bool "User space wakeup sources interface" | 115 | bool "User space wakeup sources interface" |
| 116 | depends on PM_SLEEP | 116 | depends on PM_SLEEP |
| 117 | default n | 117 | default n |
| 118 | ---help--- | 118 | ---help--- |
| 119 | Allow user space to create, activate and deactivate wakeup source | 119 | Allow user space to create, activate and deactivate wakeup source |
| 120 | objects with the help of a sysfs-based interface. | 120 | objects with the help of a sysfs-based interface. |
| 121 | 121 | ||
| 122 | config PM_WAKELOCKS_LIMIT | 122 | config PM_WAKELOCKS_LIMIT |
| 123 | int "Maximum number of user space wakeup sources (0 = no limit)" | 123 | int "Maximum number of user space wakeup sources (0 = no limit)" |
| 124 | range 0 100000 | 124 | range 0 100000 |
| 125 | default 100 | 125 | default 100 |
| 126 | depends on PM_WAKELOCKS | 126 | depends on PM_WAKELOCKS |
| 127 | 127 | ||
| 128 | config PM_WAKELOCKS_GC | 128 | config PM_WAKELOCKS_GC |
| 129 | bool "Garbage collector for user space wakeup sources" | 129 | bool "Garbage collector for user space wakeup sources" |
| 130 | depends on PM_WAKELOCKS | 130 | depends on PM_WAKELOCKS |
| 131 | default y | 131 | default y |
| 132 | 132 | ||
| 133 | config PM_RUNTIME | 133 | config PM |
| 134 | bool "Run-time PM core functionality" | 134 | bool "Device power management core functionality" |
| 135 | ---help--- | 135 | ---help--- |
| 136 | Enable functionality allowing I/O devices to be put into energy-saving | 136 | Enable functionality allowing I/O devices to be put into energy-saving |
| 137 | (low power) states at run time (or autosuspended) after a specified | 137 | (low power) states, for example after a specified period of inactivity |
| 138 | period of inactivity and woken up in response to a hardware-generated | 138 | (autosuspended), and woken up in response to a hardware-generated |
| 139 | wake-up event or a driver's request. | 139 | wake-up event or a driver's request. |
| 140 | 140 | ||
| 141 | Hardware support is generally required for this functionality to work | 141 | Hardware support is generally required for this functionality to work |
| 142 | and the bus type drivers of the buses the devices are on are | 142 | and the bus type drivers of the buses the devices are on are |
| 143 | responsible for the actual handling of the autosuspend requests and | 143 | responsible for the actual handling of device suspend requests and |
| 144 | wake-up events. | 144 | wake-up events. |
| 145 | |||
| 146 | config PM | ||
| 147 | def_bool y | ||
| 148 | depends on PM_SLEEP || PM_RUNTIME | ||
| 149 | 145 | ||
| 150 | config PM_DEBUG | 146 | config PM_DEBUG |
| 151 | bool "Power Management Debug Support" | 147 | bool "Power Management Debug Support" |
| 152 | depends on PM | 148 | depends on PM |
| 153 | ---help--- | 149 | ---help--- |
| 154 | This option enables various debugging support in the Power Management | 150 | This option enables various debugging support in the Power Management |
| 155 | code. This is helpful when debugging and reporting PM bugs, like | 151 | code. This is helpful when debugging and reporting PM bugs, like |
| 156 | suspend support. | 152 | suspend support. |
| 157 | 153 | ||
| 158 | config PM_ADVANCED_DEBUG | 154 | config PM_ADVANCED_DEBUG |
| 159 | bool "Extra PM attributes in sysfs for low-level debugging/testing" | 155 | bool "Extra PM attributes in sysfs for low-level debugging/testing" |
| 160 | depends on PM_DEBUG | 156 | depends on PM_DEBUG |
| 161 | ---help--- | 157 | ---help--- |
| 162 | Add extra sysfs attributes allowing one to access some Power Management | 158 | Add extra sysfs attributes allowing one to access some Power Management |
| 163 | fields of device objects from user space. If you are not a kernel | 159 | fields of device objects from user space. If you are not a kernel |
| 164 | developer interested in debugging/testing Power Management, say "no". | 160 | developer interested in debugging/testing Power Management, say "no". |
| 165 | 161 | ||
| 166 | config PM_TEST_SUSPEND | 162 | config PM_TEST_SUSPEND |
| 167 | bool "Test suspend/resume and wakealarm during bootup" | 163 | bool "Test suspend/resume and wakealarm during bootup" |
| 168 | depends on SUSPEND && PM_DEBUG && RTC_CLASS=y | 164 | depends on SUSPEND && PM_DEBUG && RTC_CLASS=y |
| 169 | ---help--- | 165 | ---help--- |
| 170 | This option will let you suspend your machine during bootup, and | 166 | This option will let you suspend your machine during bootup, and |
| 171 | make it wake up a few seconds later using an RTC wakeup alarm. | 167 | make it wake up a few seconds later using an RTC wakeup alarm. |
| 172 | Enable this with a kernel parameter like "test_suspend=mem". | 168 | Enable this with a kernel parameter like "test_suspend=mem". |
| 173 | 169 | ||
| 174 | You probably want to have your system's RTC driver statically | 170 | You probably want to have your system's RTC driver statically |
| 175 | linked, ensuring that it's available when this test runs. | 171 | linked, ensuring that it's available when this test runs. |
| 176 | 172 | ||
| 177 | config PM_SLEEP_DEBUG | 173 | config PM_SLEEP_DEBUG |
| 178 | def_bool y | 174 | def_bool y |
| 179 | depends on PM_DEBUG && PM_SLEEP | 175 | depends on PM_DEBUG && PM_SLEEP |
| 180 | 176 | ||
| 181 | config DPM_WATCHDOG | 177 | config DPM_WATCHDOG |
| 182 | bool "Device suspend/resume watchdog" | 178 | bool "Device suspend/resume watchdog" |
| 183 | depends on PM_DEBUG && PSTORE | 179 | depends on PM_DEBUG && PSTORE |
| 184 | ---help--- | 180 | ---help--- |
| 185 | Sets up a watchdog timer to capture drivers that are | 181 | Sets up a watchdog timer to capture drivers that are |
| 186 | locked up attempting to suspend/resume a device. | 182 | locked up attempting to suspend/resume a device. |
| 187 | A detected lockup causes system panic with message | 183 | A detected lockup causes system panic with message |
| 188 | captured in pstore device for inspection in subsequent | 184 | captured in pstore device for inspection in subsequent |
| 189 | boot session. | 185 | boot session. |
| 190 | 186 | ||
| 191 | config DPM_WATCHDOG_TIMEOUT | 187 | config DPM_WATCHDOG_TIMEOUT |
| 192 | int "Watchdog timeout in seconds" | 188 | int "Watchdog timeout in seconds" |
| 193 | range 1 120 | 189 | range 1 120 |
| 194 | default 12 | 190 | default 12 |
| 195 | depends on DPM_WATCHDOG | 191 | depends on DPM_WATCHDOG |
| 196 | 192 | ||
| 197 | config PM_TRACE | 193 | config PM_TRACE |
| 198 | bool | 194 | bool |
| 199 | help | 195 | help |
| 200 | This enables code to save the last PM event point across | 196 | This enables code to save the last PM event point across |
| 201 | reboot. The architecture needs to support this, x86 for | 197 | reboot. The architecture needs to support this, x86 for |
| 202 | example does by saving things in the RTC, see below. | 198 | example does by saving things in the RTC, see below. |
| 203 | 199 | ||
| 204 | The architecture specific code must provide the extern | 200 | The architecture specific code must provide the extern |
| 205 | functions from <linux/resume-trace.h> as well as the | 201 | functions from <linux/resume-trace.h> as well as the |
| 206 | <asm/resume-trace.h> header with a TRACE_RESUME() macro. | 202 | <asm/resume-trace.h> header with a TRACE_RESUME() macro. |
| 207 | 203 | ||
| 208 | The way the information is presented is architecture- | 204 | The way the information is presented is architecture- |
| 209 | dependent, x86 will print the information during a | 205 | dependent, x86 will print the information during a |
| 210 | late_initcall. | 206 | late_initcall. |
| 211 | 207 | ||
| 212 | config PM_TRACE_RTC | 208 | config PM_TRACE_RTC |
| 213 | bool "Suspend/resume event tracing" | 209 | bool "Suspend/resume event tracing" |
| 214 | depends on PM_SLEEP_DEBUG | 210 | depends on PM_SLEEP_DEBUG |
| 215 | depends on X86 | 211 | depends on X86 |
| 216 | select PM_TRACE | 212 | select PM_TRACE |
| 217 | ---help--- | 213 | ---help--- |
| 218 | This enables some cheesy code to save the last PM event point in the | 214 | This enables some cheesy code to save the last PM event point in the |
| 219 | RTC across reboots, so that you can debug a machine that just hangs | 215 | RTC across reboots, so that you can debug a machine that just hangs |
| 220 | during suspend (or more commonly, during resume). | 216 | during suspend (or more commonly, during resume). |
| 221 | 217 | ||
| 222 | To use this debugging feature you should attempt to suspend the | 218 | To use this debugging feature you should attempt to suspend the |
| 223 | machine, reboot it and then run | 219 | machine, reboot it and then run |
| 224 | 220 | ||
| 225 | dmesg -s 1000000 | grep 'hash matches' | 221 | dmesg -s 1000000 | grep 'hash matches' |
| 226 | 222 | ||
| 227 | CAUTION: this option will cause your machine's real-time clock to be | 223 | CAUTION: this option will cause your machine's real-time clock to be |
| 228 | set to an invalid time after a resume. | 224 | set to an invalid time after a resume. |
| 229 | 225 | ||
| 230 | config APM_EMULATION | 226 | config APM_EMULATION |
| 231 | tristate "Advanced Power Management Emulation" | 227 | tristate "Advanced Power Management Emulation" |
| 232 | depends on PM && SYS_SUPPORTS_APM_EMULATION | 228 | depends on PM && SYS_SUPPORTS_APM_EMULATION |
| 233 | help | 229 | help |
| 234 | APM is a BIOS specification for saving power using several different | 230 | APM is a BIOS specification for saving power using several different |
| 235 | techniques. This is mostly useful for battery powered laptops with | 231 | techniques. This is mostly useful for battery powered laptops with |
| 236 | APM compliant BIOSes. If you say Y here, the system time will be | 232 | APM compliant BIOSes. If you say Y here, the system time will be |
| 237 | reset after a RESUME operation, the /proc/apm device will provide | 233 | reset after a RESUME operation, the /proc/apm device will provide |
| 238 | battery status information, and user-space programs will receive | 234 | battery status information, and user-space programs will receive |
| 239 | notification of APM "events" (e.g. battery status change). | 235 | notification of APM "events" (e.g. battery status change). |
| 240 | 236 | ||
| 241 | In order to use APM, you will need supporting software. For location | 237 | In order to use APM, you will need supporting software. For location |
| 242 | and more information, read <file:Documentation/power/apm-acpi.txt> | 238 | and more information, read <file:Documentation/power/apm-acpi.txt> |
| 243 | and the Battery Powered Linux mini-HOWTO, available from | 239 | and the Battery Powered Linux mini-HOWTO, available from |
| 244 | <http://www.tldp.org/docs.html#howto>. | 240 | <http://www.tldp.org/docs.html#howto>. |
| 245 | 241 | ||
| 246 | This driver does not spin down disk drives (see the hdparm(8) | 242 | This driver does not spin down disk drives (see the hdparm(8) |
| 247 | manpage ("man 8 hdparm") for that), and it doesn't turn off | 243 | manpage ("man 8 hdparm") for that), and it doesn't turn off |
| 248 | VESA-compliant "green" monitors. | 244 | VESA-compliant "green" monitors. |
| 249 | 245 | ||
| 250 | Generally, if you don't have a battery in your machine, there isn't | 246 | Generally, if you don't have a battery in your machine, there isn't |
| 251 | much point in using this driver and you should say N. If you get | 247 | much point in using this driver and you should say N. If you get |
| 252 | random kernel OOPSes or reboots that don't seem to be related to | 248 | random kernel OOPSes or reboots that don't seem to be related to |
| 253 | anything, try disabling/enabling this option (or disabling/enabling | 249 | anything, try disabling/enabling this option (or disabling/enabling |
| 254 | APM in your BIOS). | 250 | APM in your BIOS). |
| 255 | 251 | ||
| 256 | config PM_OPP | 252 | config PM_OPP |
| 257 | bool | 253 | bool |
| 258 | ---help--- | 254 | ---help--- |
| 259 | SOCs have a standard set of tuples consisting of frequency and | 255 | SOCs have a standard set of tuples consisting of frequency and |
| 260 | voltage pairs that the device will support per voltage domain. This | 256 | voltage pairs that the device will support per voltage domain. This |
| 261 | is called Operating Performance Point or OPP. The actual definitions | 257 | is called Operating Performance Point or OPP. The actual definitions |
| 262 | of OPP varies over silicon within the same family of devices. | 258 | of OPP varies over silicon within the same family of devices. |
| 263 | 259 | ||
| 264 | OPP layer organizes the data internally using device pointers | 260 | OPP layer organizes the data internally using device pointers |
| 265 | representing individual voltage domains and provides SOC | 261 | representing individual voltage domains and provides SOC |
| 266 | implementations a ready to use framework to manage OPPs. | 262 | implementations a ready to use framework to manage OPPs. |
| 267 | For more information, read <file:Documentation/power/opp.txt> | 263 | For more information, read <file:Documentation/power/opp.txt> |
| 268 | 264 | ||
| 269 | config PM_CLK | 265 | config PM_CLK |
| 270 | def_bool y | 266 | def_bool y |
| 271 | depends on PM && HAVE_CLK | 267 | depends on PM && HAVE_CLK |
| 272 | 268 | ||
| 273 | config PM_GENERIC_DOMAINS | 269 | config PM_GENERIC_DOMAINS |
| 274 | bool | 270 | bool |
| 275 | depends on PM | 271 | depends on PM |
| 276 | 272 | ||
| 277 | config WQ_POWER_EFFICIENT_DEFAULT | 273 | config WQ_POWER_EFFICIENT_DEFAULT |
| 278 | bool "Enable workqueue power-efficient mode by default" | 274 | bool "Enable workqueue power-efficient mode by default" |
| 279 | depends on PM | 275 | depends on PM |
| 280 | default n | 276 | default n |
| 281 | help | 277 | help |
| 282 | Per-cpu workqueues are generally preferred because they show | 278 | Per-cpu workqueues are generally preferred because they show |
| 283 | better performance thanks to cache locality; unfortunately, | 279 | better performance thanks to cache locality; unfortunately, |
| 284 | per-cpu workqueues tend to be more power hungry than unbound | 280 | per-cpu workqueues tend to be more power hungry than unbound |
| 285 | workqueues. | 281 | workqueues. |
| 286 | 282 | ||
| 287 | Enabling workqueue.power_efficient kernel parameter makes the | 283 | Enabling workqueue.power_efficient kernel parameter makes the |
| 288 | per-cpu workqueues which were observed to contribute | 284 | per-cpu workqueues which were observed to contribute |
| 289 | significantly to power consumption unbound, leading to measurably | 285 | significantly to power consumption unbound, leading to measurably |
| 290 | lower power usage at the cost of small performance overhead. | 286 | lower power usage at the cost of small performance overhead. |
| 291 | 287 | ||
| 292 | This config option determines whether workqueue.power_efficient | 288 | This config option determines whether workqueue.power_efficient |
| 293 | is enabled by default. | 289 | is enabled by default. |
| 294 | 290 | ||
| 295 | If in doubt, say N. | 291 | If in doubt, say N. |
| 296 | 292 | ||
| 297 | config PM_GENERIC_DOMAINS_SLEEP | 293 | config PM_GENERIC_DOMAINS_SLEEP |
| 298 | def_bool y | 294 | def_bool y |
| 299 | depends on PM_SLEEP && PM_GENERIC_DOMAINS | 295 | depends on PM_SLEEP && PM_GENERIC_DOMAINS |
| 300 | 296 | ||
| 301 | config PM_GENERIC_DOMAINS_OF | 297 | config PM_GENERIC_DOMAINS_OF |
| 302 | def_bool y | 298 | def_bool y |
| 303 | depends on PM_GENERIC_DOMAINS && OF | 299 | depends on PM_GENERIC_DOMAINS && OF |
| 304 | 300 | ||
| 305 | config CPU_PM | 301 | config CPU_PM |
| 306 | bool | 302 | bool |
| 307 | 303 |
sound/soc/intel/sst-haswell-pcm.c
| 1 | /* | 1 | /* |
| 2 | * Intel SST Haswell/Broadwell PCM Support | 2 | * Intel SST Haswell/Broadwell PCM Support |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013, Intel Corporation. All rights reserved. | 4 | * Copyright (C) 2013, Intel Corporation. All rights reserved. |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License version | 7 | * modify it under the terms of the GNU General Public License version |
| 8 | * 2 as published by the Free Software Foundation. | 8 | * 2 as published by the Free Software Foundation. |
| 9 | * | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, | 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. | 13 | * GNU General Public License for more details. |
| 14 | * | 14 | * |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 18 | #include <linux/dma-mapping.h> | 18 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
| 20 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
| 21 | #include <linux/pm_runtime.h> | 21 | #include <linux/pm_runtime.h> |
| 22 | #include <asm/page.h> | 22 | #include <asm/page.h> |
| 23 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
| 24 | #include <sound/core.h> | 24 | #include <sound/core.h> |
| 25 | #include <sound/pcm.h> | 25 | #include <sound/pcm.h> |
| 26 | #include <sound/pcm_params.h> | 26 | #include <sound/pcm_params.h> |
| 27 | #include <sound/dmaengine_pcm.h> | 27 | #include <sound/dmaengine_pcm.h> |
| 28 | #include <sound/soc.h> | 28 | #include <sound/soc.h> |
| 29 | #include <sound/tlv.h> | 29 | #include <sound/tlv.h> |
| 30 | #include <sound/compress_driver.h> | 30 | #include <sound/compress_driver.h> |
| 31 | 31 | ||
| 32 | #include "sst-haswell-ipc.h" | 32 | #include "sst-haswell-ipc.h" |
| 33 | #include "sst-dsp-priv.h" | 33 | #include "sst-dsp-priv.h" |
| 34 | #include "sst-dsp.h" | 34 | #include "sst-dsp.h" |
| 35 | 35 | ||
| 36 | #define HSW_PCM_COUNT 6 | 36 | #define HSW_PCM_COUNT 6 |
| 37 | #define HSW_VOLUME_MAX 0x7FFFFFFF /* 0dB */ | 37 | #define HSW_VOLUME_MAX 0x7FFFFFFF /* 0dB */ |
| 38 | 38 | ||
| 39 | /* simple volume table */ | 39 | /* simple volume table */ |
| 40 | static const u32 volume_map[] = { | 40 | static const u32 volume_map[] = { |
| 41 | HSW_VOLUME_MAX >> 30, | 41 | HSW_VOLUME_MAX >> 30, |
| 42 | HSW_VOLUME_MAX >> 29, | 42 | HSW_VOLUME_MAX >> 29, |
| 43 | HSW_VOLUME_MAX >> 28, | 43 | HSW_VOLUME_MAX >> 28, |
| 44 | HSW_VOLUME_MAX >> 27, | 44 | HSW_VOLUME_MAX >> 27, |
| 45 | HSW_VOLUME_MAX >> 26, | 45 | HSW_VOLUME_MAX >> 26, |
| 46 | HSW_VOLUME_MAX >> 25, | 46 | HSW_VOLUME_MAX >> 25, |
| 47 | HSW_VOLUME_MAX >> 24, | 47 | HSW_VOLUME_MAX >> 24, |
| 48 | HSW_VOLUME_MAX >> 23, | 48 | HSW_VOLUME_MAX >> 23, |
| 49 | HSW_VOLUME_MAX >> 22, | 49 | HSW_VOLUME_MAX >> 22, |
| 50 | HSW_VOLUME_MAX >> 21, | 50 | HSW_VOLUME_MAX >> 21, |
| 51 | HSW_VOLUME_MAX >> 20, | 51 | HSW_VOLUME_MAX >> 20, |
| 52 | HSW_VOLUME_MAX >> 19, | 52 | HSW_VOLUME_MAX >> 19, |
| 53 | HSW_VOLUME_MAX >> 18, | 53 | HSW_VOLUME_MAX >> 18, |
| 54 | HSW_VOLUME_MAX >> 17, | 54 | HSW_VOLUME_MAX >> 17, |
| 55 | HSW_VOLUME_MAX >> 16, | 55 | HSW_VOLUME_MAX >> 16, |
| 56 | HSW_VOLUME_MAX >> 15, | 56 | HSW_VOLUME_MAX >> 15, |
| 57 | HSW_VOLUME_MAX >> 14, | 57 | HSW_VOLUME_MAX >> 14, |
| 58 | HSW_VOLUME_MAX >> 13, | 58 | HSW_VOLUME_MAX >> 13, |
| 59 | HSW_VOLUME_MAX >> 12, | 59 | HSW_VOLUME_MAX >> 12, |
| 60 | HSW_VOLUME_MAX >> 11, | 60 | HSW_VOLUME_MAX >> 11, |
| 61 | HSW_VOLUME_MAX >> 10, | 61 | HSW_VOLUME_MAX >> 10, |
| 62 | HSW_VOLUME_MAX >> 9, | 62 | HSW_VOLUME_MAX >> 9, |
| 63 | HSW_VOLUME_MAX >> 8, | 63 | HSW_VOLUME_MAX >> 8, |
| 64 | HSW_VOLUME_MAX >> 7, | 64 | HSW_VOLUME_MAX >> 7, |
| 65 | HSW_VOLUME_MAX >> 6, | 65 | HSW_VOLUME_MAX >> 6, |
| 66 | HSW_VOLUME_MAX >> 5, | 66 | HSW_VOLUME_MAX >> 5, |
| 67 | HSW_VOLUME_MAX >> 4, | 67 | HSW_VOLUME_MAX >> 4, |
| 68 | HSW_VOLUME_MAX >> 3, | 68 | HSW_VOLUME_MAX >> 3, |
| 69 | HSW_VOLUME_MAX >> 2, | 69 | HSW_VOLUME_MAX >> 2, |
| 70 | HSW_VOLUME_MAX >> 1, | 70 | HSW_VOLUME_MAX >> 1, |
| 71 | HSW_VOLUME_MAX >> 0, | 71 | HSW_VOLUME_MAX >> 0, |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | #define HSW_PCM_PERIODS_MAX 64 | 74 | #define HSW_PCM_PERIODS_MAX 64 |
| 75 | #define HSW_PCM_PERIODS_MIN 2 | 75 | #define HSW_PCM_PERIODS_MIN 2 |
| 76 | 76 | ||
| 77 | #define HSW_PCM_DAI_ID_SYSTEM 0 | 77 | #define HSW_PCM_DAI_ID_SYSTEM 0 |
| 78 | #define HSW_PCM_DAI_ID_OFFLOAD0 1 | 78 | #define HSW_PCM_DAI_ID_OFFLOAD0 1 |
| 79 | #define HSW_PCM_DAI_ID_OFFLOAD1 2 | 79 | #define HSW_PCM_DAI_ID_OFFLOAD1 2 |
| 80 | #define HSW_PCM_DAI_ID_LOOPBACK 3 | 80 | #define HSW_PCM_DAI_ID_LOOPBACK 3 |
| 81 | #define HSW_PCM_DAI_ID_CAPTURE 4 | 81 | #define HSW_PCM_DAI_ID_CAPTURE 4 |
| 82 | 82 | ||
| 83 | 83 | ||
| 84 | static const struct snd_pcm_hardware hsw_pcm_hardware = { | 84 | static const struct snd_pcm_hardware hsw_pcm_hardware = { |
| 85 | .info = SNDRV_PCM_INFO_MMAP | | 85 | .info = SNDRV_PCM_INFO_MMAP | |
| 86 | SNDRV_PCM_INFO_MMAP_VALID | | 86 | SNDRV_PCM_INFO_MMAP_VALID | |
| 87 | SNDRV_PCM_INFO_INTERLEAVED | | 87 | SNDRV_PCM_INFO_INTERLEAVED | |
| 88 | SNDRV_PCM_INFO_PAUSE | | 88 | SNDRV_PCM_INFO_PAUSE | |
| 89 | SNDRV_PCM_INFO_RESUME | | 89 | SNDRV_PCM_INFO_RESUME | |
| 90 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, | 90 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, |
| 91 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | | 91 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | |
| 92 | SNDRV_PCM_FMTBIT_S32_LE, | 92 | SNDRV_PCM_FMTBIT_S32_LE, |
| 93 | .period_bytes_min = PAGE_SIZE, | 93 | .period_bytes_min = PAGE_SIZE, |
| 94 | .period_bytes_max = (HSW_PCM_PERIODS_MAX / HSW_PCM_PERIODS_MIN) * PAGE_SIZE, | 94 | .period_bytes_max = (HSW_PCM_PERIODS_MAX / HSW_PCM_PERIODS_MIN) * PAGE_SIZE, |
| 95 | .periods_min = HSW_PCM_PERIODS_MIN, | 95 | .periods_min = HSW_PCM_PERIODS_MIN, |
| 96 | .periods_max = HSW_PCM_PERIODS_MAX, | 96 | .periods_max = HSW_PCM_PERIODS_MAX, |
| 97 | .buffer_bytes_max = HSW_PCM_PERIODS_MAX * PAGE_SIZE, | 97 | .buffer_bytes_max = HSW_PCM_PERIODS_MAX * PAGE_SIZE, |
| 98 | }; | 98 | }; |
| 99 | 99 | ||
| 100 | struct hsw_pcm_module_map { | 100 | struct hsw_pcm_module_map { |
| 101 | int dai_id; | 101 | int dai_id; |
| 102 | enum sst_hsw_module_id mod_id; | 102 | enum sst_hsw_module_id mod_id; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | /* private data for each PCM DSP stream */ | 105 | /* private data for each PCM DSP stream */ |
| 106 | struct hsw_pcm_data { | 106 | struct hsw_pcm_data { |
| 107 | int dai_id; | 107 | int dai_id; |
| 108 | struct sst_hsw_stream *stream; | 108 | struct sst_hsw_stream *stream; |
| 109 | struct sst_module_runtime *runtime; | 109 | struct sst_module_runtime *runtime; |
| 110 | struct sst_module_runtime_context context; | 110 | struct sst_module_runtime_context context; |
| 111 | struct snd_pcm *hsw_pcm; | 111 | struct snd_pcm *hsw_pcm; |
| 112 | u32 volume[2]; | 112 | u32 volume[2]; |
| 113 | struct snd_pcm_substream *substream; | 113 | struct snd_pcm_substream *substream; |
| 114 | struct snd_compr_stream *cstream; | 114 | struct snd_compr_stream *cstream; |
| 115 | unsigned int wpos; | 115 | unsigned int wpos; |
| 116 | struct mutex mutex; | 116 | struct mutex mutex; |
| 117 | bool allocated; | 117 | bool allocated; |
| 118 | int persistent_offset; | 118 | int persistent_offset; |
| 119 | }; | 119 | }; |
| 120 | 120 | ||
| 121 | enum hsw_pm_state { | 121 | enum hsw_pm_state { |
| 122 | HSW_PM_STATE_D3 = 0, | 122 | HSW_PM_STATE_D3 = 0, |
| 123 | HSW_PM_STATE_D0 = 1, | 123 | HSW_PM_STATE_D0 = 1, |
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | /* private data for the driver */ | 126 | /* private data for the driver */ |
| 127 | struct hsw_priv_data { | 127 | struct hsw_priv_data { |
| 128 | /* runtime DSP */ | 128 | /* runtime DSP */ |
| 129 | struct sst_hsw *hsw; | 129 | struct sst_hsw *hsw; |
| 130 | struct device *dev; | 130 | struct device *dev; |
| 131 | enum hsw_pm_state pm_state; | 131 | enum hsw_pm_state pm_state; |
| 132 | struct snd_soc_card *soc_card; | 132 | struct snd_soc_card *soc_card; |
| 133 | 133 | ||
| 134 | /* page tables */ | 134 | /* page tables */ |
| 135 | struct snd_dma_buffer dmab[HSW_PCM_COUNT][2]; | 135 | struct snd_dma_buffer dmab[HSW_PCM_COUNT][2]; |
| 136 | 136 | ||
| 137 | /* DAI data */ | 137 | /* DAI data */ |
| 138 | struct hsw_pcm_data pcm[HSW_PCM_COUNT]; | 138 | struct hsw_pcm_data pcm[HSW_PCM_COUNT]; |
| 139 | }; | 139 | }; |
| 140 | 140 | ||
| 141 | static u32 hsw_notify_pointer(struct sst_hsw_stream *stream, void *data); | 141 | static u32 hsw_notify_pointer(struct sst_hsw_stream *stream, void *data); |
| 142 | 142 | ||
| 143 | static inline u32 hsw_mixer_to_ipc(unsigned int value) | 143 | static inline u32 hsw_mixer_to_ipc(unsigned int value) |
| 144 | { | 144 | { |
| 145 | if (value >= ARRAY_SIZE(volume_map)) | 145 | if (value >= ARRAY_SIZE(volume_map)) |
| 146 | return volume_map[0]; | 146 | return volume_map[0]; |
| 147 | else | 147 | else |
| 148 | return volume_map[value]; | 148 | return volume_map[value]; |
| 149 | } | 149 | } |
| 150 | 150 | ||
| 151 | static inline unsigned int hsw_ipc_to_mixer(u32 value) | 151 | static inline unsigned int hsw_ipc_to_mixer(u32 value) |
| 152 | { | 152 | { |
| 153 | int i; | 153 | int i; |
| 154 | 154 | ||
| 155 | for (i = 0; i < ARRAY_SIZE(volume_map); i++) { | 155 | for (i = 0; i < ARRAY_SIZE(volume_map); i++) { |
| 156 | if (volume_map[i] >= value) | 156 | if (volume_map[i] >= value) |
| 157 | return i; | 157 | return i; |
| 158 | } | 158 | } |
| 159 | 159 | ||
| 160 | return i - 1; | 160 | return i - 1; |
| 161 | } | 161 | } |
| 162 | 162 | ||
| 163 | static int hsw_stream_volume_put(struct snd_kcontrol *kcontrol, | 163 | static int hsw_stream_volume_put(struct snd_kcontrol *kcontrol, |
| 164 | struct snd_ctl_elem_value *ucontrol) | 164 | struct snd_ctl_elem_value *ucontrol) |
| 165 | { | 165 | { |
| 166 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); | 166 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); |
| 167 | struct soc_mixer_control *mc = | 167 | struct soc_mixer_control *mc = |
| 168 | (struct soc_mixer_control *)kcontrol->private_value; | 168 | (struct soc_mixer_control *)kcontrol->private_value; |
| 169 | struct hsw_priv_data *pdata = | 169 | struct hsw_priv_data *pdata = |
| 170 | snd_soc_platform_get_drvdata(platform); | 170 | snd_soc_platform_get_drvdata(platform); |
| 171 | struct hsw_pcm_data *pcm_data = &pdata->pcm[mc->reg]; | 171 | struct hsw_pcm_data *pcm_data = &pdata->pcm[mc->reg]; |
| 172 | struct sst_hsw *hsw = pdata->hsw; | 172 | struct sst_hsw *hsw = pdata->hsw; |
| 173 | u32 volume; | 173 | u32 volume; |
| 174 | 174 | ||
| 175 | mutex_lock(&pcm_data->mutex); | 175 | mutex_lock(&pcm_data->mutex); |
| 176 | pm_runtime_get_sync(pdata->dev); | 176 | pm_runtime_get_sync(pdata->dev); |
| 177 | 177 | ||
| 178 | if (!pcm_data->stream) { | 178 | if (!pcm_data->stream) { |
| 179 | pcm_data->volume[0] = | 179 | pcm_data->volume[0] = |
| 180 | hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); | 180 | hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); |
| 181 | pcm_data->volume[1] = | 181 | pcm_data->volume[1] = |
| 182 | hsw_mixer_to_ipc(ucontrol->value.integer.value[1]); | 182 | hsw_mixer_to_ipc(ucontrol->value.integer.value[1]); |
| 183 | pm_runtime_mark_last_busy(pdata->dev); | 183 | pm_runtime_mark_last_busy(pdata->dev); |
| 184 | pm_runtime_put_autosuspend(pdata->dev); | 184 | pm_runtime_put_autosuspend(pdata->dev); |
| 185 | mutex_unlock(&pcm_data->mutex); | 185 | mutex_unlock(&pcm_data->mutex); |
| 186 | return 0; | 186 | return 0; |
| 187 | } | 187 | } |
| 188 | 188 | ||
| 189 | if (ucontrol->value.integer.value[0] == | 189 | if (ucontrol->value.integer.value[0] == |
| 190 | ucontrol->value.integer.value[1]) { | 190 | ucontrol->value.integer.value[1]) { |
| 191 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); | 191 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); |
| 192 | /* apply volume value to all channels */ | 192 | /* apply volume value to all channels */ |
| 193 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, SST_HSW_CHANNELS_ALL, volume); | 193 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, SST_HSW_CHANNELS_ALL, volume); |
| 194 | } else { | 194 | } else { |
| 195 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); | 195 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); |
| 196 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, 0, volume); | 196 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, 0, volume); |
| 197 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[1]); | 197 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[1]); |
| 198 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, 1, volume); | 198 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, 1, volume); |
| 199 | } | 199 | } |
| 200 | 200 | ||
| 201 | pm_runtime_mark_last_busy(pdata->dev); | 201 | pm_runtime_mark_last_busy(pdata->dev); |
| 202 | pm_runtime_put_autosuspend(pdata->dev); | 202 | pm_runtime_put_autosuspend(pdata->dev); |
| 203 | mutex_unlock(&pcm_data->mutex); | 203 | mutex_unlock(&pcm_data->mutex); |
| 204 | return 0; | 204 | return 0; |
| 205 | } | 205 | } |
| 206 | 206 | ||
| 207 | static int hsw_stream_volume_get(struct snd_kcontrol *kcontrol, | 207 | static int hsw_stream_volume_get(struct snd_kcontrol *kcontrol, |
| 208 | struct snd_ctl_elem_value *ucontrol) | 208 | struct snd_ctl_elem_value *ucontrol) |
| 209 | { | 209 | { |
| 210 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); | 210 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); |
| 211 | struct soc_mixer_control *mc = | 211 | struct soc_mixer_control *mc = |
| 212 | (struct soc_mixer_control *)kcontrol->private_value; | 212 | (struct soc_mixer_control *)kcontrol->private_value; |
| 213 | struct hsw_priv_data *pdata = | 213 | struct hsw_priv_data *pdata = |
| 214 | snd_soc_platform_get_drvdata(platform); | 214 | snd_soc_platform_get_drvdata(platform); |
| 215 | struct hsw_pcm_data *pcm_data = &pdata->pcm[mc->reg]; | 215 | struct hsw_pcm_data *pcm_data = &pdata->pcm[mc->reg]; |
| 216 | struct sst_hsw *hsw = pdata->hsw; | 216 | struct sst_hsw *hsw = pdata->hsw; |
| 217 | u32 volume; | 217 | u32 volume; |
| 218 | 218 | ||
| 219 | mutex_lock(&pcm_data->mutex); | 219 | mutex_lock(&pcm_data->mutex); |
| 220 | pm_runtime_get_sync(pdata->dev); | 220 | pm_runtime_get_sync(pdata->dev); |
| 221 | 221 | ||
| 222 | if (!pcm_data->stream) { | 222 | if (!pcm_data->stream) { |
| 223 | ucontrol->value.integer.value[0] = | 223 | ucontrol->value.integer.value[0] = |
| 224 | hsw_ipc_to_mixer(pcm_data->volume[0]); | 224 | hsw_ipc_to_mixer(pcm_data->volume[0]); |
| 225 | ucontrol->value.integer.value[1] = | 225 | ucontrol->value.integer.value[1] = |
| 226 | hsw_ipc_to_mixer(pcm_data->volume[1]); | 226 | hsw_ipc_to_mixer(pcm_data->volume[1]); |
| 227 | pm_runtime_mark_last_busy(pdata->dev); | 227 | pm_runtime_mark_last_busy(pdata->dev); |
| 228 | pm_runtime_put_autosuspend(pdata->dev); | 228 | pm_runtime_put_autosuspend(pdata->dev); |
| 229 | mutex_unlock(&pcm_data->mutex); | 229 | mutex_unlock(&pcm_data->mutex); |
| 230 | return 0; | 230 | return 0; |
| 231 | } | 231 | } |
| 232 | 232 | ||
| 233 | sst_hsw_stream_get_volume(hsw, pcm_data->stream, 0, 0, &volume); | 233 | sst_hsw_stream_get_volume(hsw, pcm_data->stream, 0, 0, &volume); |
| 234 | ucontrol->value.integer.value[0] = hsw_ipc_to_mixer(volume); | 234 | ucontrol->value.integer.value[0] = hsw_ipc_to_mixer(volume); |
| 235 | sst_hsw_stream_get_volume(hsw, pcm_data->stream, 0, 1, &volume); | 235 | sst_hsw_stream_get_volume(hsw, pcm_data->stream, 0, 1, &volume); |
| 236 | ucontrol->value.integer.value[1] = hsw_ipc_to_mixer(volume); | 236 | ucontrol->value.integer.value[1] = hsw_ipc_to_mixer(volume); |
| 237 | 237 | ||
| 238 | pm_runtime_mark_last_busy(pdata->dev); | 238 | pm_runtime_mark_last_busy(pdata->dev); |
| 239 | pm_runtime_put_autosuspend(pdata->dev); | 239 | pm_runtime_put_autosuspend(pdata->dev); |
| 240 | mutex_unlock(&pcm_data->mutex); | 240 | mutex_unlock(&pcm_data->mutex); |
| 241 | 241 | ||
| 242 | return 0; | 242 | return 0; |
| 243 | } | 243 | } |
| 244 | 244 | ||
| 245 | static int hsw_volume_put(struct snd_kcontrol *kcontrol, | 245 | static int hsw_volume_put(struct snd_kcontrol *kcontrol, |
| 246 | struct snd_ctl_elem_value *ucontrol) | 246 | struct snd_ctl_elem_value *ucontrol) |
| 247 | { | 247 | { |
| 248 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); | 248 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); |
| 249 | struct hsw_priv_data *pdata = snd_soc_platform_get_drvdata(platform); | 249 | struct hsw_priv_data *pdata = snd_soc_platform_get_drvdata(platform); |
| 250 | struct sst_hsw *hsw = pdata->hsw; | 250 | struct sst_hsw *hsw = pdata->hsw; |
| 251 | u32 volume; | 251 | u32 volume; |
| 252 | 252 | ||
| 253 | pm_runtime_get_sync(pdata->dev); | 253 | pm_runtime_get_sync(pdata->dev); |
| 254 | 254 | ||
| 255 | if (ucontrol->value.integer.value[0] == | 255 | if (ucontrol->value.integer.value[0] == |
| 256 | ucontrol->value.integer.value[1]) { | 256 | ucontrol->value.integer.value[1]) { |
| 257 | 257 | ||
| 258 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); | 258 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); |
| 259 | sst_hsw_mixer_set_volume(hsw, 0, SST_HSW_CHANNELS_ALL, volume); | 259 | sst_hsw_mixer_set_volume(hsw, 0, SST_HSW_CHANNELS_ALL, volume); |
| 260 | 260 | ||
| 261 | } else { | 261 | } else { |
| 262 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); | 262 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[0]); |
| 263 | sst_hsw_mixer_set_volume(hsw, 0, 0, volume); | 263 | sst_hsw_mixer_set_volume(hsw, 0, 0, volume); |
| 264 | 264 | ||
| 265 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[1]); | 265 | volume = hsw_mixer_to_ipc(ucontrol->value.integer.value[1]); |
| 266 | sst_hsw_mixer_set_volume(hsw, 0, 1, volume); | 266 | sst_hsw_mixer_set_volume(hsw, 0, 1, volume); |
| 267 | } | 267 | } |
| 268 | 268 | ||
| 269 | pm_runtime_mark_last_busy(pdata->dev); | 269 | pm_runtime_mark_last_busy(pdata->dev); |
| 270 | pm_runtime_put_autosuspend(pdata->dev); | 270 | pm_runtime_put_autosuspend(pdata->dev); |
| 271 | return 0; | 271 | return 0; |
| 272 | } | 272 | } |
| 273 | 273 | ||
| 274 | static int hsw_volume_get(struct snd_kcontrol *kcontrol, | 274 | static int hsw_volume_get(struct snd_kcontrol *kcontrol, |
| 275 | struct snd_ctl_elem_value *ucontrol) | 275 | struct snd_ctl_elem_value *ucontrol) |
| 276 | { | 276 | { |
| 277 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); | 277 | struct snd_soc_platform *platform = snd_soc_kcontrol_platform(kcontrol); |
| 278 | struct hsw_priv_data *pdata = snd_soc_platform_get_drvdata(platform); | 278 | struct hsw_priv_data *pdata = snd_soc_platform_get_drvdata(platform); |
| 279 | struct sst_hsw *hsw = pdata->hsw; | 279 | struct sst_hsw *hsw = pdata->hsw; |
| 280 | unsigned int volume = 0; | 280 | unsigned int volume = 0; |
| 281 | 281 | ||
| 282 | pm_runtime_get_sync(pdata->dev); | 282 | pm_runtime_get_sync(pdata->dev); |
| 283 | sst_hsw_mixer_get_volume(hsw, 0, 0, &volume); | 283 | sst_hsw_mixer_get_volume(hsw, 0, 0, &volume); |
| 284 | ucontrol->value.integer.value[0] = hsw_ipc_to_mixer(volume); | 284 | ucontrol->value.integer.value[0] = hsw_ipc_to_mixer(volume); |
| 285 | 285 | ||
| 286 | sst_hsw_mixer_get_volume(hsw, 0, 1, &volume); | 286 | sst_hsw_mixer_get_volume(hsw, 0, 1, &volume); |
| 287 | ucontrol->value.integer.value[1] = hsw_ipc_to_mixer(volume); | 287 | ucontrol->value.integer.value[1] = hsw_ipc_to_mixer(volume); |
| 288 | 288 | ||
| 289 | pm_runtime_mark_last_busy(pdata->dev); | 289 | pm_runtime_mark_last_busy(pdata->dev); |
| 290 | pm_runtime_put_autosuspend(pdata->dev); | 290 | pm_runtime_put_autosuspend(pdata->dev); |
| 291 | return 0; | 291 | return 0; |
| 292 | } | 292 | } |
| 293 | 293 | ||
| 294 | /* TLV used by both global and stream volumes */ | 294 | /* TLV used by both global and stream volumes */ |
| 295 | static const DECLARE_TLV_DB_SCALE(hsw_vol_tlv, -9000, 300, 1); | 295 | static const DECLARE_TLV_DB_SCALE(hsw_vol_tlv, -9000, 300, 1); |
| 296 | 296 | ||
| 297 | /* System Pin has no volume control */ | 297 | /* System Pin has no volume control */ |
| 298 | static const struct snd_kcontrol_new hsw_volume_controls[] = { | 298 | static const struct snd_kcontrol_new hsw_volume_controls[] = { |
| 299 | /* Global DSP volume */ | 299 | /* Global DSP volume */ |
| 300 | SOC_DOUBLE_EXT_TLV("Master Playback Volume", 0, 0, 8, | 300 | SOC_DOUBLE_EXT_TLV("Master Playback Volume", 0, 0, 8, |
| 301 | ARRAY_SIZE(volume_map) - 1, 0, | 301 | ARRAY_SIZE(volume_map) - 1, 0, |
| 302 | hsw_volume_get, hsw_volume_put, hsw_vol_tlv), | 302 | hsw_volume_get, hsw_volume_put, hsw_vol_tlv), |
| 303 | /* Offload 0 volume */ | 303 | /* Offload 0 volume */ |
| 304 | SOC_DOUBLE_EXT_TLV("Media0 Playback Volume", 1, 0, 8, | 304 | SOC_DOUBLE_EXT_TLV("Media0 Playback Volume", 1, 0, 8, |
| 305 | ARRAY_SIZE(volume_map) - 1, 0, | 305 | ARRAY_SIZE(volume_map) - 1, 0, |
| 306 | hsw_stream_volume_get, hsw_stream_volume_put, hsw_vol_tlv), | 306 | hsw_stream_volume_get, hsw_stream_volume_put, hsw_vol_tlv), |
| 307 | /* Offload 1 volume */ | 307 | /* Offload 1 volume */ |
| 308 | SOC_DOUBLE_EXT_TLV("Media1 Playback Volume", 2, 0, 8, | 308 | SOC_DOUBLE_EXT_TLV("Media1 Playback Volume", 2, 0, 8, |
| 309 | ARRAY_SIZE(volume_map) - 1, 0, | 309 | ARRAY_SIZE(volume_map) - 1, 0, |
| 310 | hsw_stream_volume_get, hsw_stream_volume_put, hsw_vol_tlv), | 310 | hsw_stream_volume_get, hsw_stream_volume_put, hsw_vol_tlv), |
| 311 | /* Mic Capture volume */ | 311 | /* Mic Capture volume */ |
| 312 | SOC_DOUBLE_EXT_TLV("Mic Capture Volume", 0, 0, 8, | 312 | SOC_DOUBLE_EXT_TLV("Mic Capture Volume", 0, 0, 8, |
| 313 | ARRAY_SIZE(volume_map) - 1, 0, | 313 | ARRAY_SIZE(volume_map) - 1, 0, |
| 314 | hsw_stream_volume_get, hsw_stream_volume_put, hsw_vol_tlv), | 314 | hsw_stream_volume_get, hsw_stream_volume_put, hsw_vol_tlv), |
| 315 | }; | 315 | }; |
| 316 | 316 | ||
| 317 | /* Create DMA buffer page table for DSP */ | 317 | /* Create DMA buffer page table for DSP */ |
| 318 | static int create_adsp_page_table(struct snd_pcm_substream *substream, | 318 | static int create_adsp_page_table(struct snd_pcm_substream *substream, |
| 319 | struct hsw_priv_data *pdata, struct snd_soc_pcm_runtime *rtd, | 319 | struct hsw_priv_data *pdata, struct snd_soc_pcm_runtime *rtd, |
| 320 | unsigned char *dma_area, size_t size, int pcm) | 320 | unsigned char *dma_area, size_t size, int pcm) |
| 321 | { | 321 | { |
| 322 | struct snd_dma_buffer *dmab = snd_pcm_get_dma_buf(substream); | 322 | struct snd_dma_buffer *dmab = snd_pcm_get_dma_buf(substream); |
| 323 | int i, pages, stream = substream->stream; | 323 | int i, pages, stream = substream->stream; |
| 324 | 324 | ||
| 325 | pages = snd_sgbuf_aligned_pages(size); | 325 | pages = snd_sgbuf_aligned_pages(size); |
| 326 | 326 | ||
| 327 | dev_dbg(rtd->dev, "generating page table for %p size 0x%zu pages %d\n", | 327 | dev_dbg(rtd->dev, "generating page table for %p size 0x%zu pages %d\n", |
| 328 | dma_area, size, pages); | 328 | dma_area, size, pages); |
| 329 | 329 | ||
| 330 | for (i = 0; i < pages; i++) { | 330 | for (i = 0; i < pages; i++) { |
| 331 | u32 idx = (((i << 2) + i)) >> 1; | 331 | u32 idx = (((i << 2) + i)) >> 1; |
| 332 | u32 pfn = snd_sgbuf_get_addr(dmab, i * PAGE_SIZE) >> PAGE_SHIFT; | 332 | u32 pfn = snd_sgbuf_get_addr(dmab, i * PAGE_SIZE) >> PAGE_SHIFT; |
| 333 | u32 *pg_table; | 333 | u32 *pg_table; |
| 334 | 334 | ||
| 335 | dev_dbg(rtd->dev, "pfn i %i idx %d pfn %x\n", i, idx, pfn); | 335 | dev_dbg(rtd->dev, "pfn i %i idx %d pfn %x\n", i, idx, pfn); |
| 336 | 336 | ||
| 337 | pg_table = (u32 *)(pdata->dmab[pcm][stream].area + idx); | 337 | pg_table = (u32 *)(pdata->dmab[pcm][stream].area + idx); |
| 338 | 338 | ||
| 339 | if (i & 1) | 339 | if (i & 1) |
| 340 | *pg_table |= (pfn << 4); | 340 | *pg_table |= (pfn << 4); |
| 341 | else | 341 | else |
| 342 | *pg_table |= pfn; | 342 | *pg_table |= pfn; |
| 343 | } | 343 | } |
| 344 | 344 | ||
| 345 | return 0; | 345 | return 0; |
| 346 | } | 346 | } |
| 347 | 347 | ||
| 348 | /* this may get called several times by oss emulation */ | 348 | /* this may get called several times by oss emulation */ |
| 349 | static int hsw_pcm_hw_params(struct snd_pcm_substream *substream, | 349 | static int hsw_pcm_hw_params(struct snd_pcm_substream *substream, |
| 350 | struct snd_pcm_hw_params *params) | 350 | struct snd_pcm_hw_params *params) |
| 351 | { | 351 | { |
| 352 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 352 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 353 | struct snd_pcm_runtime *runtime = substream->runtime; | 353 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 354 | struct hsw_priv_data *pdata = | 354 | struct hsw_priv_data *pdata = |
| 355 | snd_soc_platform_get_drvdata(rtd->platform); | 355 | snd_soc_platform_get_drvdata(rtd->platform); |
| 356 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); | 356 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); |
| 357 | struct sst_hsw *hsw = pdata->hsw; | 357 | struct sst_hsw *hsw = pdata->hsw; |
| 358 | struct sst_module *module_data; | 358 | struct sst_module *module_data; |
| 359 | struct sst_dsp *dsp; | 359 | struct sst_dsp *dsp; |
| 360 | struct snd_dma_buffer *dmab; | 360 | struct snd_dma_buffer *dmab; |
| 361 | enum sst_hsw_stream_type stream_type; | 361 | enum sst_hsw_stream_type stream_type; |
| 362 | enum sst_hsw_stream_path_id path_id; | 362 | enum sst_hsw_stream_path_id path_id; |
| 363 | u32 rate, bits, map, pages, module_id; | 363 | u32 rate, bits, map, pages, module_id; |
| 364 | u8 channels; | 364 | u8 channels; |
| 365 | int ret; | 365 | int ret; |
| 366 | 366 | ||
| 367 | /* check if we are being called a subsequent time */ | 367 | /* check if we are being called a subsequent time */ |
| 368 | if (pcm_data->allocated) { | 368 | if (pcm_data->allocated) { |
| 369 | ret = sst_hsw_stream_reset(hsw, pcm_data->stream); | 369 | ret = sst_hsw_stream_reset(hsw, pcm_data->stream); |
| 370 | if (ret < 0) | 370 | if (ret < 0) |
| 371 | dev_dbg(rtd->dev, "error: reset stream failed %d\n", | 371 | dev_dbg(rtd->dev, "error: reset stream failed %d\n", |
| 372 | ret); | 372 | ret); |
| 373 | 373 | ||
| 374 | ret = sst_hsw_stream_free(hsw, pcm_data->stream); | 374 | ret = sst_hsw_stream_free(hsw, pcm_data->stream); |
| 375 | if (ret < 0) { | 375 | if (ret < 0) { |
| 376 | dev_dbg(rtd->dev, "error: free stream failed %d\n", | 376 | dev_dbg(rtd->dev, "error: free stream failed %d\n", |
| 377 | ret); | 377 | ret); |
| 378 | return ret; | 378 | return ret; |
| 379 | } | 379 | } |
| 380 | pcm_data->allocated = false; | 380 | pcm_data->allocated = false; |
| 381 | 381 | ||
| 382 | pcm_data->stream = sst_hsw_stream_new(hsw, rtd->cpu_dai->id, | 382 | pcm_data->stream = sst_hsw_stream_new(hsw, rtd->cpu_dai->id, |
| 383 | hsw_notify_pointer, pcm_data); | 383 | hsw_notify_pointer, pcm_data); |
| 384 | if (pcm_data->stream == NULL) { | 384 | if (pcm_data->stream == NULL) { |
| 385 | dev_err(rtd->dev, "error: failed to create stream\n"); | 385 | dev_err(rtd->dev, "error: failed to create stream\n"); |
| 386 | return -EINVAL; | 386 | return -EINVAL; |
| 387 | } | 387 | } |
| 388 | } | 388 | } |
| 389 | 389 | ||
| 390 | /* stream direction */ | 390 | /* stream direction */ |
| 391 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 391 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 392 | path_id = SST_HSW_STREAM_PATH_SSP0_OUT; | 392 | path_id = SST_HSW_STREAM_PATH_SSP0_OUT; |
| 393 | else | 393 | else |
| 394 | path_id = SST_HSW_STREAM_PATH_SSP0_IN; | 394 | path_id = SST_HSW_STREAM_PATH_SSP0_IN; |
| 395 | 395 | ||
| 396 | /* DSP stream type depends on DAI ID */ | 396 | /* DSP stream type depends on DAI ID */ |
| 397 | switch (rtd->cpu_dai->id) { | 397 | switch (rtd->cpu_dai->id) { |
| 398 | case 0: | 398 | case 0: |
| 399 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | 399 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 400 | stream_type = SST_HSW_STREAM_TYPE_SYSTEM; | 400 | stream_type = SST_HSW_STREAM_TYPE_SYSTEM; |
| 401 | module_id = SST_HSW_MODULE_PCM_SYSTEM; | 401 | module_id = SST_HSW_MODULE_PCM_SYSTEM; |
| 402 | } | 402 | } |
| 403 | else { | 403 | else { |
| 404 | stream_type = SST_HSW_STREAM_TYPE_CAPTURE; | 404 | stream_type = SST_HSW_STREAM_TYPE_CAPTURE; |
| 405 | module_id = SST_HSW_MODULE_PCM_CAPTURE; | 405 | module_id = SST_HSW_MODULE_PCM_CAPTURE; |
| 406 | } | 406 | } |
| 407 | break; | 407 | break; |
| 408 | case 1: | 408 | case 1: |
| 409 | case 2: | 409 | case 2: |
| 410 | stream_type = SST_HSW_STREAM_TYPE_RENDER; | 410 | stream_type = SST_HSW_STREAM_TYPE_RENDER; |
| 411 | module_id = SST_HSW_MODULE_PCM; | 411 | module_id = SST_HSW_MODULE_PCM; |
| 412 | break; | 412 | break; |
| 413 | case 3: | 413 | case 3: |
| 414 | /* path ID needs to be OUT for loopback */ | 414 | /* path ID needs to be OUT for loopback */ |
| 415 | stream_type = SST_HSW_STREAM_TYPE_LOOPBACK; | 415 | stream_type = SST_HSW_STREAM_TYPE_LOOPBACK; |
| 416 | path_id = SST_HSW_STREAM_PATH_SSP0_OUT; | 416 | path_id = SST_HSW_STREAM_PATH_SSP0_OUT; |
| 417 | module_id = SST_HSW_MODULE_PCM_REFERENCE; | 417 | module_id = SST_HSW_MODULE_PCM_REFERENCE; |
| 418 | break; | 418 | break; |
| 419 | default: | 419 | default: |
| 420 | dev_err(rtd->dev, "error: invalid DAI ID %d\n", | 420 | dev_err(rtd->dev, "error: invalid DAI ID %d\n", |
| 421 | rtd->cpu_dai->id); | 421 | rtd->cpu_dai->id); |
| 422 | return -EINVAL; | 422 | return -EINVAL; |
| 423 | }; | 423 | }; |
| 424 | 424 | ||
| 425 | ret = sst_hsw_stream_format(hsw, pcm_data->stream, | 425 | ret = sst_hsw_stream_format(hsw, pcm_data->stream, |
| 426 | path_id, stream_type, SST_HSW_STREAM_FORMAT_PCM_FORMAT); | 426 | path_id, stream_type, SST_HSW_STREAM_FORMAT_PCM_FORMAT); |
| 427 | if (ret < 0) { | 427 | if (ret < 0) { |
| 428 | dev_err(rtd->dev, "error: failed to set format %d\n", ret); | 428 | dev_err(rtd->dev, "error: failed to set format %d\n", ret); |
| 429 | return ret; | 429 | return ret; |
| 430 | } | 430 | } |
| 431 | 431 | ||
| 432 | rate = params_rate(params); | 432 | rate = params_rate(params); |
| 433 | ret = sst_hsw_stream_set_rate(hsw, pcm_data->stream, rate); | 433 | ret = sst_hsw_stream_set_rate(hsw, pcm_data->stream, rate); |
| 434 | if (ret < 0) { | 434 | if (ret < 0) { |
| 435 | dev_err(rtd->dev, "error: could not set rate %d\n", rate); | 435 | dev_err(rtd->dev, "error: could not set rate %d\n", rate); |
| 436 | return ret; | 436 | return ret; |
| 437 | } | 437 | } |
| 438 | 438 | ||
| 439 | switch (params_format(params)) { | 439 | switch (params_format(params)) { |
| 440 | case SNDRV_PCM_FORMAT_S16_LE: | 440 | case SNDRV_PCM_FORMAT_S16_LE: |
| 441 | bits = SST_HSW_DEPTH_16BIT; | 441 | bits = SST_HSW_DEPTH_16BIT; |
| 442 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 16); | 442 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 16); |
| 443 | break; | 443 | break; |
| 444 | case SNDRV_PCM_FORMAT_S24_LE: | 444 | case SNDRV_PCM_FORMAT_S24_LE: |
| 445 | bits = SST_HSW_DEPTH_32BIT; | 445 | bits = SST_HSW_DEPTH_32BIT; |
| 446 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 24); | 446 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 24); |
| 447 | break; | 447 | break; |
| 448 | case SNDRV_PCM_FORMAT_S8: | 448 | case SNDRV_PCM_FORMAT_S8: |
| 449 | bits = SST_HSW_DEPTH_8BIT; | 449 | bits = SST_HSW_DEPTH_8BIT; |
| 450 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 8); | 450 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 8); |
| 451 | break; | 451 | break; |
| 452 | case SNDRV_PCM_FORMAT_S32_LE: | 452 | case SNDRV_PCM_FORMAT_S32_LE: |
| 453 | bits = SST_HSW_DEPTH_32BIT; | 453 | bits = SST_HSW_DEPTH_32BIT; |
| 454 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 32); | 454 | sst_hsw_stream_set_valid(hsw, pcm_data->stream, 32); |
| 455 | break; | 455 | break; |
| 456 | default: | 456 | default: |
| 457 | dev_err(rtd->dev, "error: invalid format %d\n", | 457 | dev_err(rtd->dev, "error: invalid format %d\n", |
| 458 | params_format(params)); | 458 | params_format(params)); |
| 459 | return -EINVAL; | 459 | return -EINVAL; |
| 460 | } | 460 | } |
| 461 | 461 | ||
| 462 | ret = sst_hsw_stream_set_bits(hsw, pcm_data->stream, bits); | 462 | ret = sst_hsw_stream_set_bits(hsw, pcm_data->stream, bits); |
| 463 | if (ret < 0) { | 463 | if (ret < 0) { |
| 464 | dev_err(rtd->dev, "error: could not set bits %d\n", bits); | 464 | dev_err(rtd->dev, "error: could not set bits %d\n", bits); |
| 465 | return ret; | 465 | return ret; |
| 466 | } | 466 | } |
| 467 | 467 | ||
| 468 | channels = params_channels(params); | 468 | channels = params_channels(params); |
| 469 | map = create_channel_map(SST_HSW_CHANNEL_CONFIG_STEREO); | 469 | map = create_channel_map(SST_HSW_CHANNEL_CONFIG_STEREO); |
| 470 | sst_hsw_stream_set_map_config(hsw, pcm_data->stream, | 470 | sst_hsw_stream_set_map_config(hsw, pcm_data->stream, |
| 471 | map, SST_HSW_CHANNEL_CONFIG_STEREO); | 471 | map, SST_HSW_CHANNEL_CONFIG_STEREO); |
| 472 | 472 | ||
| 473 | ret = sst_hsw_stream_set_channels(hsw, pcm_data->stream, channels); | 473 | ret = sst_hsw_stream_set_channels(hsw, pcm_data->stream, channels); |
| 474 | if (ret < 0) { | 474 | if (ret < 0) { |
| 475 | dev_err(rtd->dev, "error: could not set channels %d\n", | 475 | dev_err(rtd->dev, "error: could not set channels %d\n", |
| 476 | channels); | 476 | channels); |
| 477 | return ret; | 477 | return ret; |
| 478 | } | 478 | } |
| 479 | 479 | ||
| 480 | ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); | 480 | ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); |
| 481 | if (ret < 0) { | 481 | if (ret < 0) { |
| 482 | dev_err(rtd->dev, "error: could not allocate %d bytes for PCM %d\n", | 482 | dev_err(rtd->dev, "error: could not allocate %d bytes for PCM %d\n", |
| 483 | params_buffer_bytes(params), ret); | 483 | params_buffer_bytes(params), ret); |
| 484 | return ret; | 484 | return ret; |
| 485 | } | 485 | } |
| 486 | 486 | ||
| 487 | dmab = snd_pcm_get_dma_buf(substream); | 487 | dmab = snd_pcm_get_dma_buf(substream); |
| 488 | 488 | ||
| 489 | ret = create_adsp_page_table(substream, pdata, rtd, runtime->dma_area, | 489 | ret = create_adsp_page_table(substream, pdata, rtd, runtime->dma_area, |
| 490 | runtime->dma_bytes, rtd->cpu_dai->id); | 490 | runtime->dma_bytes, rtd->cpu_dai->id); |
| 491 | if (ret < 0) | 491 | if (ret < 0) |
| 492 | return ret; | 492 | return ret; |
| 493 | 493 | ||
| 494 | sst_hsw_stream_set_style(hsw, pcm_data->stream, | 494 | sst_hsw_stream_set_style(hsw, pcm_data->stream, |
| 495 | SST_HSW_INTERLEAVING_PER_CHANNEL); | 495 | SST_HSW_INTERLEAVING_PER_CHANNEL); |
| 496 | 496 | ||
| 497 | if (runtime->dma_bytes % PAGE_SIZE) | 497 | if (runtime->dma_bytes % PAGE_SIZE) |
| 498 | pages = (runtime->dma_bytes / PAGE_SIZE) + 1; | 498 | pages = (runtime->dma_bytes / PAGE_SIZE) + 1; |
| 499 | else | 499 | else |
| 500 | pages = runtime->dma_bytes / PAGE_SIZE; | 500 | pages = runtime->dma_bytes / PAGE_SIZE; |
| 501 | 501 | ||
| 502 | ret = sst_hsw_stream_buffer(hsw, pcm_data->stream, | 502 | ret = sst_hsw_stream_buffer(hsw, pcm_data->stream, |
| 503 | pdata->dmab[rtd->cpu_dai->id][substream->stream].addr, | 503 | pdata->dmab[rtd->cpu_dai->id][substream->stream].addr, |
| 504 | pages, runtime->dma_bytes, 0, | 504 | pages, runtime->dma_bytes, 0, |
| 505 | snd_sgbuf_get_addr(dmab, 0) >> PAGE_SHIFT); | 505 | snd_sgbuf_get_addr(dmab, 0) >> PAGE_SHIFT); |
| 506 | if (ret < 0) { | 506 | if (ret < 0) { |
| 507 | dev_err(rtd->dev, "error: failed to set DMA buffer %d\n", ret); | 507 | dev_err(rtd->dev, "error: failed to set DMA buffer %d\n", ret); |
| 508 | return ret; | 508 | return ret; |
| 509 | } | 509 | } |
| 510 | 510 | ||
| 511 | dsp = sst_hsw_get_dsp(hsw); | 511 | dsp = sst_hsw_get_dsp(hsw); |
| 512 | 512 | ||
| 513 | module_data = sst_module_get_from_id(dsp, module_id); | 513 | module_data = sst_module_get_from_id(dsp, module_id); |
| 514 | if (module_data == NULL) { | 514 | if (module_data == NULL) { |
| 515 | dev_err(rtd->dev, "error: failed to get module config\n"); | 515 | dev_err(rtd->dev, "error: failed to get module config\n"); |
| 516 | return -EINVAL; | 516 | return -EINVAL; |
| 517 | } | 517 | } |
| 518 | 518 | ||
| 519 | sst_hsw_stream_set_module_info(hsw, pcm_data->stream, | 519 | sst_hsw_stream_set_module_info(hsw, pcm_data->stream, |
| 520 | pcm_data->runtime); | 520 | pcm_data->runtime); |
| 521 | 521 | ||
| 522 | ret = sst_hsw_stream_commit(hsw, pcm_data->stream); | 522 | ret = sst_hsw_stream_commit(hsw, pcm_data->stream); |
| 523 | if (ret < 0) { | 523 | if (ret < 0) { |
| 524 | dev_err(rtd->dev, "error: failed to commit stream %d\n", ret); | 524 | dev_err(rtd->dev, "error: failed to commit stream %d\n", ret); |
| 525 | return ret; | 525 | return ret; |
| 526 | } | 526 | } |
| 527 | 527 | ||
| 528 | if (!pcm_data->allocated) { | 528 | if (!pcm_data->allocated) { |
| 529 | /* Set previous saved volume */ | 529 | /* Set previous saved volume */ |
| 530 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, | 530 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, |
| 531 | 0, pcm_data->volume[0]); | 531 | 0, pcm_data->volume[0]); |
| 532 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, | 532 | sst_hsw_stream_set_volume(hsw, pcm_data->stream, 0, |
| 533 | 1, pcm_data->volume[1]); | 533 | 1, pcm_data->volume[1]); |
| 534 | pcm_data->allocated = true; | 534 | pcm_data->allocated = true; |
| 535 | } | 535 | } |
| 536 | 536 | ||
| 537 | ret = sst_hsw_stream_pause(hsw, pcm_data->stream, 1); | 537 | ret = sst_hsw_stream_pause(hsw, pcm_data->stream, 1); |
| 538 | if (ret < 0) | 538 | if (ret < 0) |
| 539 | dev_err(rtd->dev, "error: failed to pause %d\n", ret); | 539 | dev_err(rtd->dev, "error: failed to pause %d\n", ret); |
| 540 | 540 | ||
| 541 | return 0; | 541 | return 0; |
| 542 | } | 542 | } |
| 543 | 543 | ||
| 544 | static int hsw_pcm_hw_free(struct snd_pcm_substream *substream) | 544 | static int hsw_pcm_hw_free(struct snd_pcm_substream *substream) |
| 545 | { | 545 | { |
| 546 | snd_pcm_lib_free_pages(substream); | 546 | snd_pcm_lib_free_pages(substream); |
| 547 | return 0; | 547 | return 0; |
| 548 | } | 548 | } |
| 549 | 549 | ||
| 550 | static int hsw_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | 550 | static int hsw_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
| 551 | { | 551 | { |
| 552 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 552 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 553 | struct hsw_priv_data *pdata = | 553 | struct hsw_priv_data *pdata = |
| 554 | snd_soc_platform_get_drvdata(rtd->platform); | 554 | snd_soc_platform_get_drvdata(rtd->platform); |
| 555 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); | 555 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); |
| 556 | struct sst_hsw *hsw = pdata->hsw; | 556 | struct sst_hsw *hsw = pdata->hsw; |
| 557 | 557 | ||
| 558 | switch (cmd) { | 558 | switch (cmd) { |
| 559 | case SNDRV_PCM_TRIGGER_START: | 559 | case SNDRV_PCM_TRIGGER_START: |
| 560 | case SNDRV_PCM_TRIGGER_RESUME: | 560 | case SNDRV_PCM_TRIGGER_RESUME: |
| 561 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | 561 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 562 | sst_hsw_stream_resume(hsw, pcm_data->stream, 0); | 562 | sst_hsw_stream_resume(hsw, pcm_data->stream, 0); |
| 563 | break; | 563 | break; |
| 564 | case SNDRV_PCM_TRIGGER_STOP: | 564 | case SNDRV_PCM_TRIGGER_STOP: |
| 565 | case SNDRV_PCM_TRIGGER_SUSPEND: | 565 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 566 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | 566 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 567 | sst_hsw_stream_pause(hsw, pcm_data->stream, 0); | 567 | sst_hsw_stream_pause(hsw, pcm_data->stream, 0); |
| 568 | break; | 568 | break; |
| 569 | default: | 569 | default: |
| 570 | break; | 570 | break; |
| 571 | } | 571 | } |
| 572 | 572 | ||
| 573 | return 0; | 573 | return 0; |
| 574 | } | 574 | } |
| 575 | 575 | ||
| 576 | static u32 hsw_notify_pointer(struct sst_hsw_stream *stream, void *data) | 576 | static u32 hsw_notify_pointer(struct sst_hsw_stream *stream, void *data) |
| 577 | { | 577 | { |
| 578 | struct hsw_pcm_data *pcm_data = data; | 578 | struct hsw_pcm_data *pcm_data = data; |
| 579 | struct snd_pcm_substream *substream = pcm_data->substream; | 579 | struct snd_pcm_substream *substream = pcm_data->substream; |
| 580 | struct snd_pcm_runtime *runtime = substream->runtime; | 580 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 581 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 581 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 582 | u32 pos; | 582 | u32 pos; |
| 583 | 583 | ||
| 584 | pos = frames_to_bytes(runtime, | 584 | pos = frames_to_bytes(runtime, |
| 585 | (runtime->control->appl_ptr % runtime->buffer_size)); | 585 | (runtime->control->appl_ptr % runtime->buffer_size)); |
| 586 | 586 | ||
| 587 | dev_vdbg(rtd->dev, "PCM: App pointer %d bytes\n", pos); | 587 | dev_vdbg(rtd->dev, "PCM: App pointer %d bytes\n", pos); |
| 588 | 588 | ||
| 589 | /* let alsa know we have play a period */ | 589 | /* let alsa know we have play a period */ |
| 590 | snd_pcm_period_elapsed(substream); | 590 | snd_pcm_period_elapsed(substream); |
| 591 | return pos; | 591 | return pos; |
| 592 | } | 592 | } |
| 593 | 593 | ||
| 594 | static snd_pcm_uframes_t hsw_pcm_pointer(struct snd_pcm_substream *substream) | 594 | static snd_pcm_uframes_t hsw_pcm_pointer(struct snd_pcm_substream *substream) |
| 595 | { | 595 | { |
| 596 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 596 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 597 | struct snd_pcm_runtime *runtime = substream->runtime; | 597 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 598 | struct hsw_priv_data *pdata = | 598 | struct hsw_priv_data *pdata = |
| 599 | snd_soc_platform_get_drvdata(rtd->platform); | 599 | snd_soc_platform_get_drvdata(rtd->platform); |
| 600 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); | 600 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); |
| 601 | struct sst_hsw *hsw = pdata->hsw; | 601 | struct sst_hsw *hsw = pdata->hsw; |
| 602 | snd_pcm_uframes_t offset; | 602 | snd_pcm_uframes_t offset; |
| 603 | uint64_t ppos; | 603 | uint64_t ppos; |
| 604 | u32 position = sst_hsw_get_dsp_position(hsw, pcm_data->stream); | 604 | u32 position = sst_hsw_get_dsp_position(hsw, pcm_data->stream); |
| 605 | 605 | ||
| 606 | offset = bytes_to_frames(runtime, position); | 606 | offset = bytes_to_frames(runtime, position); |
| 607 | ppos = sst_hsw_get_dsp_presentation_position(hsw, pcm_data->stream); | 607 | ppos = sst_hsw_get_dsp_presentation_position(hsw, pcm_data->stream); |
| 608 | 608 | ||
| 609 | dev_vdbg(rtd->dev, "PCM: DMA pointer %du bytes, pos %llu\n", | 609 | dev_vdbg(rtd->dev, "PCM: DMA pointer %du bytes, pos %llu\n", |
| 610 | position, ppos); | 610 | position, ppos); |
| 611 | return offset; | 611 | return offset; |
| 612 | } | 612 | } |
| 613 | 613 | ||
| 614 | static int hsw_pcm_open(struct snd_pcm_substream *substream) | 614 | static int hsw_pcm_open(struct snd_pcm_substream *substream) |
| 615 | { | 615 | { |
| 616 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 616 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 617 | struct hsw_priv_data *pdata = | 617 | struct hsw_priv_data *pdata = |
| 618 | snd_soc_platform_get_drvdata(rtd->platform); | 618 | snd_soc_platform_get_drvdata(rtd->platform); |
| 619 | struct hsw_pcm_data *pcm_data; | 619 | struct hsw_pcm_data *pcm_data; |
| 620 | struct sst_hsw *hsw = pdata->hsw; | 620 | struct sst_hsw *hsw = pdata->hsw; |
| 621 | 621 | ||
| 622 | pcm_data = &pdata->pcm[rtd->cpu_dai->id]; | 622 | pcm_data = &pdata->pcm[rtd->cpu_dai->id]; |
| 623 | 623 | ||
| 624 | mutex_lock(&pcm_data->mutex); | 624 | mutex_lock(&pcm_data->mutex); |
| 625 | pm_runtime_get_sync(pdata->dev); | 625 | pm_runtime_get_sync(pdata->dev); |
| 626 | 626 | ||
| 627 | snd_soc_pcm_set_drvdata(rtd, pcm_data); | 627 | snd_soc_pcm_set_drvdata(rtd, pcm_data); |
| 628 | pcm_data->substream = substream; | 628 | pcm_data->substream = substream; |
| 629 | 629 | ||
| 630 | snd_soc_set_runtime_hwparams(substream, &hsw_pcm_hardware); | 630 | snd_soc_set_runtime_hwparams(substream, &hsw_pcm_hardware); |
| 631 | 631 | ||
| 632 | pcm_data->stream = sst_hsw_stream_new(hsw, rtd->cpu_dai->id, | 632 | pcm_data->stream = sst_hsw_stream_new(hsw, rtd->cpu_dai->id, |
| 633 | hsw_notify_pointer, pcm_data); | 633 | hsw_notify_pointer, pcm_data); |
| 634 | if (pcm_data->stream == NULL) { | 634 | if (pcm_data->stream == NULL) { |
| 635 | dev_err(rtd->dev, "error: failed to create stream\n"); | 635 | dev_err(rtd->dev, "error: failed to create stream\n"); |
| 636 | pm_runtime_mark_last_busy(pdata->dev); | 636 | pm_runtime_mark_last_busy(pdata->dev); |
| 637 | pm_runtime_put_autosuspend(pdata->dev); | 637 | pm_runtime_put_autosuspend(pdata->dev); |
| 638 | mutex_unlock(&pcm_data->mutex); | 638 | mutex_unlock(&pcm_data->mutex); |
| 639 | return -EINVAL; | 639 | return -EINVAL; |
| 640 | } | 640 | } |
| 641 | 641 | ||
| 642 | mutex_unlock(&pcm_data->mutex); | 642 | mutex_unlock(&pcm_data->mutex); |
| 643 | return 0; | 643 | return 0; |
| 644 | } | 644 | } |
| 645 | 645 | ||
| 646 | static int hsw_pcm_close(struct snd_pcm_substream *substream) | 646 | static int hsw_pcm_close(struct snd_pcm_substream *substream) |
| 647 | { | 647 | { |
| 648 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 648 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 649 | struct hsw_priv_data *pdata = | 649 | struct hsw_priv_data *pdata = |
| 650 | snd_soc_platform_get_drvdata(rtd->platform); | 650 | snd_soc_platform_get_drvdata(rtd->platform); |
| 651 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); | 651 | struct hsw_pcm_data *pcm_data = snd_soc_pcm_get_drvdata(rtd); |
| 652 | struct sst_hsw *hsw = pdata->hsw; | 652 | struct sst_hsw *hsw = pdata->hsw; |
| 653 | int ret; | 653 | int ret; |
| 654 | 654 | ||
| 655 | mutex_lock(&pcm_data->mutex); | 655 | mutex_lock(&pcm_data->mutex); |
| 656 | ret = sst_hsw_stream_reset(hsw, pcm_data->stream); | 656 | ret = sst_hsw_stream_reset(hsw, pcm_data->stream); |
| 657 | if (ret < 0) { | 657 | if (ret < 0) { |
| 658 | dev_dbg(rtd->dev, "error: reset stream failed %d\n", ret); | 658 | dev_dbg(rtd->dev, "error: reset stream failed %d\n", ret); |
| 659 | goto out; | 659 | goto out; |
| 660 | } | 660 | } |
| 661 | 661 | ||
| 662 | ret = sst_hsw_stream_free(hsw, pcm_data->stream); | 662 | ret = sst_hsw_stream_free(hsw, pcm_data->stream); |
| 663 | if (ret < 0) { | 663 | if (ret < 0) { |
| 664 | dev_dbg(rtd->dev, "error: free stream failed %d\n", ret); | 664 | dev_dbg(rtd->dev, "error: free stream failed %d\n", ret); |
| 665 | goto out; | 665 | goto out; |
| 666 | } | 666 | } |
| 667 | pcm_data->allocated = 0; | 667 | pcm_data->allocated = 0; |
| 668 | pcm_data->stream = NULL; | 668 | pcm_data->stream = NULL; |
| 669 | 669 | ||
| 670 | out: | 670 | out: |
| 671 | pm_runtime_mark_last_busy(pdata->dev); | 671 | pm_runtime_mark_last_busy(pdata->dev); |
| 672 | pm_runtime_put_autosuspend(pdata->dev); | 672 | pm_runtime_put_autosuspend(pdata->dev); |
| 673 | mutex_unlock(&pcm_data->mutex); | 673 | mutex_unlock(&pcm_data->mutex); |
| 674 | return ret; | 674 | return ret; |
| 675 | } | 675 | } |
| 676 | 676 | ||
| 677 | static struct snd_pcm_ops hsw_pcm_ops = { | 677 | static struct snd_pcm_ops hsw_pcm_ops = { |
| 678 | .open = hsw_pcm_open, | 678 | .open = hsw_pcm_open, |
| 679 | .close = hsw_pcm_close, | 679 | .close = hsw_pcm_close, |
| 680 | .ioctl = snd_pcm_lib_ioctl, | 680 | .ioctl = snd_pcm_lib_ioctl, |
| 681 | .hw_params = hsw_pcm_hw_params, | 681 | .hw_params = hsw_pcm_hw_params, |
| 682 | .hw_free = hsw_pcm_hw_free, | 682 | .hw_free = hsw_pcm_hw_free, |
| 683 | .trigger = hsw_pcm_trigger, | 683 | .trigger = hsw_pcm_trigger, |
| 684 | .pointer = hsw_pcm_pointer, | 684 | .pointer = hsw_pcm_pointer, |
| 685 | .page = snd_pcm_sgbuf_ops_page, | 685 | .page = snd_pcm_sgbuf_ops_page, |
| 686 | }; | 686 | }; |
| 687 | 687 | ||
| 688 | /* static mappings between PCMs and modules - may be dynamic in future */ | 688 | /* static mappings between PCMs and modules - may be dynamic in future */ |
| 689 | static struct hsw_pcm_module_map mod_map[] = { | 689 | static struct hsw_pcm_module_map mod_map[] = { |
| 690 | {HSW_PCM_DAI_ID_SYSTEM, SST_HSW_MODULE_PCM_SYSTEM}, | 690 | {HSW_PCM_DAI_ID_SYSTEM, SST_HSW_MODULE_PCM_SYSTEM}, |
| 691 | {HSW_PCM_DAI_ID_OFFLOAD0, SST_HSW_MODULE_PCM}, | 691 | {HSW_PCM_DAI_ID_OFFLOAD0, SST_HSW_MODULE_PCM}, |
| 692 | {HSW_PCM_DAI_ID_OFFLOAD1, SST_HSW_MODULE_PCM}, | 692 | {HSW_PCM_DAI_ID_OFFLOAD1, SST_HSW_MODULE_PCM}, |
| 693 | {HSW_PCM_DAI_ID_LOOPBACK, SST_HSW_MODULE_PCM_REFERENCE}, | 693 | {HSW_PCM_DAI_ID_LOOPBACK, SST_HSW_MODULE_PCM_REFERENCE}, |
| 694 | {HSW_PCM_DAI_ID_CAPTURE, SST_HSW_MODULE_PCM_CAPTURE}, | 694 | {HSW_PCM_DAI_ID_CAPTURE, SST_HSW_MODULE_PCM_CAPTURE}, |
| 695 | }; | 695 | }; |
| 696 | 696 | ||
| 697 | static int hsw_pcm_create_modules(struct hsw_priv_data *pdata) | 697 | static int hsw_pcm_create_modules(struct hsw_priv_data *pdata) |
| 698 | { | 698 | { |
| 699 | struct sst_hsw *hsw = pdata->hsw; | 699 | struct sst_hsw *hsw = pdata->hsw; |
| 700 | struct hsw_pcm_data *pcm_data; | 700 | struct hsw_pcm_data *pcm_data; |
| 701 | int i; | 701 | int i; |
| 702 | 702 | ||
| 703 | for (i = 0; i < ARRAY_SIZE(mod_map); i++) { | 703 | for (i = 0; i < ARRAY_SIZE(mod_map); i++) { |
| 704 | pcm_data = &pdata->pcm[i]; | 704 | pcm_data = &pdata->pcm[i]; |
| 705 | 705 | ||
| 706 | /* create new runtime module, use same offset if recreated */ | 706 | /* create new runtime module, use same offset if recreated */ |
| 707 | pcm_data->runtime = sst_hsw_runtime_module_create(hsw, | 707 | pcm_data->runtime = sst_hsw_runtime_module_create(hsw, |
| 708 | mod_map[i].mod_id, pcm_data->persistent_offset); | 708 | mod_map[i].mod_id, pcm_data->persistent_offset); |
| 709 | if (pcm_data->runtime == NULL) | 709 | if (pcm_data->runtime == NULL) |
| 710 | goto err; | 710 | goto err; |
| 711 | pcm_data->persistent_offset = | 711 | pcm_data->persistent_offset = |
| 712 | pcm_data->runtime->persistent_offset; | 712 | pcm_data->runtime->persistent_offset; |
| 713 | } | 713 | } |
| 714 | 714 | ||
| 715 | return 0; | 715 | return 0; |
| 716 | 716 | ||
| 717 | err: | 717 | err: |
| 718 | for (--i; i >= 0; i--) { | 718 | for (--i; i >= 0; i--) { |
| 719 | pcm_data = &pdata->pcm[i]; | 719 | pcm_data = &pdata->pcm[i]; |
| 720 | sst_hsw_runtime_module_free(pcm_data->runtime); | 720 | sst_hsw_runtime_module_free(pcm_data->runtime); |
| 721 | } | 721 | } |
| 722 | 722 | ||
| 723 | return -ENODEV; | 723 | return -ENODEV; |
| 724 | } | 724 | } |
| 725 | 725 | ||
| 726 | static void hsw_pcm_free_modules(struct hsw_priv_data *pdata) | 726 | static void hsw_pcm_free_modules(struct hsw_priv_data *pdata) |
| 727 | { | 727 | { |
| 728 | struct hsw_pcm_data *pcm_data; | 728 | struct hsw_pcm_data *pcm_data; |
| 729 | int i; | 729 | int i; |
| 730 | 730 | ||
| 731 | for (i = 0; i < ARRAY_SIZE(mod_map); i++) { | 731 | for (i = 0; i < ARRAY_SIZE(mod_map); i++) { |
| 732 | pcm_data = &pdata->pcm[i]; | 732 | pcm_data = &pdata->pcm[i]; |
| 733 | 733 | ||
| 734 | sst_hsw_runtime_module_free(pcm_data->runtime); | 734 | sst_hsw_runtime_module_free(pcm_data->runtime); |
| 735 | } | 735 | } |
| 736 | } | 736 | } |
| 737 | 737 | ||
| 738 | static void hsw_pcm_free(struct snd_pcm *pcm) | 738 | static void hsw_pcm_free(struct snd_pcm *pcm) |
| 739 | { | 739 | { |
| 740 | snd_pcm_lib_preallocate_free_for_all(pcm); | 740 | snd_pcm_lib_preallocate_free_for_all(pcm); |
| 741 | } | 741 | } |
| 742 | 742 | ||
| 743 | static int hsw_pcm_new(struct snd_soc_pcm_runtime *rtd) | 743 | static int hsw_pcm_new(struct snd_soc_pcm_runtime *rtd) |
| 744 | { | 744 | { |
| 745 | struct snd_pcm *pcm = rtd->pcm; | 745 | struct snd_pcm *pcm = rtd->pcm; |
| 746 | struct snd_soc_platform *platform = rtd->platform; | 746 | struct snd_soc_platform *platform = rtd->platform; |
| 747 | struct sst_pdata *pdata = dev_get_platdata(platform->dev); | 747 | struct sst_pdata *pdata = dev_get_platdata(platform->dev); |
| 748 | struct hsw_priv_data *priv_data = dev_get_drvdata(platform->dev); | 748 | struct hsw_priv_data *priv_data = dev_get_drvdata(platform->dev); |
| 749 | struct device *dev = pdata->dma_dev; | 749 | struct device *dev = pdata->dma_dev; |
| 750 | int ret = 0; | 750 | int ret = 0; |
| 751 | 751 | ||
| 752 | if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream || | 752 | if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream || |
| 753 | pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { | 753 | pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { |
| 754 | ret = snd_pcm_lib_preallocate_pages_for_all(pcm, | 754 | ret = snd_pcm_lib_preallocate_pages_for_all(pcm, |
| 755 | SNDRV_DMA_TYPE_DEV_SG, | 755 | SNDRV_DMA_TYPE_DEV_SG, |
| 756 | dev, | 756 | dev, |
| 757 | hsw_pcm_hardware.buffer_bytes_max, | 757 | hsw_pcm_hardware.buffer_bytes_max, |
| 758 | hsw_pcm_hardware.buffer_bytes_max); | 758 | hsw_pcm_hardware.buffer_bytes_max); |
| 759 | if (ret) { | 759 | if (ret) { |
| 760 | dev_err(rtd->dev, "dma buffer allocation failed %d\n", | 760 | dev_err(rtd->dev, "dma buffer allocation failed %d\n", |
| 761 | ret); | 761 | ret); |
| 762 | return ret; | 762 | return ret; |
| 763 | } | 763 | } |
| 764 | } | 764 | } |
| 765 | priv_data->pcm[rtd->cpu_dai->id].hsw_pcm = pcm; | 765 | priv_data->pcm[rtd->cpu_dai->id].hsw_pcm = pcm; |
| 766 | 766 | ||
| 767 | return ret; | 767 | return ret; |
| 768 | } | 768 | } |
| 769 | 769 | ||
| 770 | #define HSW_FORMATS \ | 770 | #define HSW_FORMATS \ |
| 771 | (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | 771 | (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) |
| 772 | 772 | ||
| 773 | static struct snd_soc_dai_driver hsw_dais[] = { | 773 | static struct snd_soc_dai_driver hsw_dais[] = { |
| 774 | { | 774 | { |
| 775 | .name = "System Pin", | 775 | .name = "System Pin", |
| 776 | .id = HSW_PCM_DAI_ID_SYSTEM, | 776 | .id = HSW_PCM_DAI_ID_SYSTEM, |
| 777 | .playback = { | 777 | .playback = { |
| 778 | .stream_name = "System Playback", | 778 | .stream_name = "System Playback", |
| 779 | .channels_min = 2, | 779 | .channels_min = 2, |
| 780 | .channels_max = 2, | 780 | .channels_max = 2, |
| 781 | .rates = SNDRV_PCM_RATE_48000, | 781 | .rates = SNDRV_PCM_RATE_48000, |
| 782 | .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, | 782 | .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, |
| 783 | }, | 783 | }, |
| 784 | .capture = { | 784 | .capture = { |
| 785 | .stream_name = "Analog Capture", | 785 | .stream_name = "Analog Capture", |
| 786 | .channels_min = 2, | 786 | .channels_min = 2, |
| 787 | .channels_max = 4, | 787 | .channels_max = 4, |
| 788 | .rates = SNDRV_PCM_RATE_48000, | 788 | .rates = SNDRV_PCM_RATE_48000, |
| 789 | .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, | 789 | .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, |
| 790 | }, | 790 | }, |
| 791 | }, | 791 | }, |
| 792 | { | 792 | { |
| 793 | /* PCM */ | 793 | /* PCM */ |
| 794 | .name = "Offload0 Pin", | 794 | .name = "Offload0 Pin", |
| 795 | .id = HSW_PCM_DAI_ID_OFFLOAD0, | 795 | .id = HSW_PCM_DAI_ID_OFFLOAD0, |
| 796 | .playback = { | 796 | .playback = { |
| 797 | .stream_name = "Offload0 Playback", | 797 | .stream_name = "Offload0 Playback", |
| 798 | .channels_min = 2, | 798 | .channels_min = 2, |
| 799 | .channels_max = 2, | 799 | .channels_max = 2, |
| 800 | .rates = SNDRV_PCM_RATE_8000_192000, | 800 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 801 | .formats = HSW_FORMATS, | 801 | .formats = HSW_FORMATS, |
| 802 | }, | 802 | }, |
| 803 | }, | 803 | }, |
| 804 | { | 804 | { |
| 805 | /* PCM */ | 805 | /* PCM */ |
| 806 | .name = "Offload1 Pin", | 806 | .name = "Offload1 Pin", |
| 807 | .id = HSW_PCM_DAI_ID_OFFLOAD1, | 807 | .id = HSW_PCM_DAI_ID_OFFLOAD1, |
| 808 | .playback = { | 808 | .playback = { |
| 809 | .stream_name = "Offload1 Playback", | 809 | .stream_name = "Offload1 Playback", |
| 810 | .channels_min = 2, | 810 | .channels_min = 2, |
| 811 | .channels_max = 2, | 811 | .channels_max = 2, |
| 812 | .rates = SNDRV_PCM_RATE_8000_192000, | 812 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 813 | .formats = HSW_FORMATS, | 813 | .formats = HSW_FORMATS, |
| 814 | }, | 814 | }, |
| 815 | }, | 815 | }, |
| 816 | { | 816 | { |
| 817 | .name = "Loopback Pin", | 817 | .name = "Loopback Pin", |
| 818 | .id = HSW_PCM_DAI_ID_LOOPBACK, | 818 | .id = HSW_PCM_DAI_ID_LOOPBACK, |
| 819 | .capture = { | 819 | .capture = { |
| 820 | .stream_name = "Loopback Capture", | 820 | .stream_name = "Loopback Capture", |
| 821 | .channels_min = 2, | 821 | .channels_min = 2, |
| 822 | .channels_max = 2, | 822 | .channels_max = 2, |
| 823 | .rates = SNDRV_PCM_RATE_48000, | 823 | .rates = SNDRV_PCM_RATE_48000, |
| 824 | .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, | 824 | .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, |
| 825 | }, | 825 | }, |
| 826 | }, | 826 | }, |
| 827 | }; | 827 | }; |
| 828 | 828 | ||
| 829 | static const struct snd_soc_dapm_widget widgets[] = { | 829 | static const struct snd_soc_dapm_widget widgets[] = { |
| 830 | 830 | ||
| 831 | /* Backend DAIs */ | 831 | /* Backend DAIs */ |
| 832 | SND_SOC_DAPM_AIF_IN("SSP0 CODEC IN", NULL, 0, SND_SOC_NOPM, 0, 0), | 832 | SND_SOC_DAPM_AIF_IN("SSP0 CODEC IN", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 833 | SND_SOC_DAPM_AIF_OUT("SSP0 CODEC OUT", NULL, 0, SND_SOC_NOPM, 0, 0), | 833 | SND_SOC_DAPM_AIF_OUT("SSP0 CODEC OUT", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 834 | SND_SOC_DAPM_AIF_IN("SSP1 BT IN", NULL, 0, SND_SOC_NOPM, 0, 0), | 834 | SND_SOC_DAPM_AIF_IN("SSP1 BT IN", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 835 | SND_SOC_DAPM_AIF_OUT("SSP1 BT OUT", NULL, 0, SND_SOC_NOPM, 0, 0), | 835 | SND_SOC_DAPM_AIF_OUT("SSP1 BT OUT", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 836 | 836 | ||
| 837 | /* Global Playback Mixer */ | 837 | /* Global Playback Mixer */ |
| 838 | SND_SOC_DAPM_MIXER("Playback VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), | 838 | SND_SOC_DAPM_MIXER("Playback VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 839 | }; | 839 | }; |
| 840 | 840 | ||
| 841 | static const struct snd_soc_dapm_route graph[] = { | 841 | static const struct snd_soc_dapm_route graph[] = { |
| 842 | 842 | ||
| 843 | /* Playback Mixer */ | 843 | /* Playback Mixer */ |
| 844 | {"Playback VMixer", NULL, "System Playback"}, | 844 | {"Playback VMixer", NULL, "System Playback"}, |
| 845 | {"Playback VMixer", NULL, "Offload0 Playback"}, | 845 | {"Playback VMixer", NULL, "Offload0 Playback"}, |
| 846 | {"Playback VMixer", NULL, "Offload1 Playback"}, | 846 | {"Playback VMixer", NULL, "Offload1 Playback"}, |
| 847 | 847 | ||
| 848 | {"SSP0 CODEC OUT", NULL, "Playback VMixer"}, | 848 | {"SSP0 CODEC OUT", NULL, "Playback VMixer"}, |
| 849 | 849 | ||
| 850 | {"Analog Capture", NULL, "SSP0 CODEC IN"}, | 850 | {"Analog Capture", NULL, "SSP0 CODEC IN"}, |
| 851 | }; | 851 | }; |
| 852 | 852 | ||
| 853 | static int hsw_pcm_probe(struct snd_soc_platform *platform) | 853 | static int hsw_pcm_probe(struct snd_soc_platform *platform) |
| 854 | { | 854 | { |
| 855 | struct hsw_priv_data *priv_data = snd_soc_platform_get_drvdata(platform); | 855 | struct hsw_priv_data *priv_data = snd_soc_platform_get_drvdata(platform); |
| 856 | struct sst_pdata *pdata = dev_get_platdata(platform->dev); | 856 | struct sst_pdata *pdata = dev_get_platdata(platform->dev); |
| 857 | struct device *dma_dev, *dev; | 857 | struct device *dma_dev, *dev; |
| 858 | int i, ret = 0; | 858 | int i, ret = 0; |
| 859 | 859 | ||
| 860 | if (!pdata) | 860 | if (!pdata) |
| 861 | return -ENODEV; | 861 | return -ENODEV; |
| 862 | 862 | ||
| 863 | dev = platform->dev; | 863 | dev = platform->dev; |
| 864 | dma_dev = pdata->dma_dev; | 864 | dma_dev = pdata->dma_dev; |
| 865 | 865 | ||
| 866 | priv_data->hsw = pdata->dsp; | 866 | priv_data->hsw = pdata->dsp; |
| 867 | priv_data->dev = platform->dev; | 867 | priv_data->dev = platform->dev; |
| 868 | priv_data->pm_state = HSW_PM_STATE_D0; | 868 | priv_data->pm_state = HSW_PM_STATE_D0; |
| 869 | priv_data->soc_card = platform->component.card; | 869 | priv_data->soc_card = platform->component.card; |
| 870 | 870 | ||
| 871 | /* allocate DSP buffer page tables */ | 871 | /* allocate DSP buffer page tables */ |
| 872 | for (i = 0; i < ARRAY_SIZE(hsw_dais); i++) { | 872 | for (i = 0; i < ARRAY_SIZE(hsw_dais); i++) { |
| 873 | 873 | ||
| 874 | mutex_init(&priv_data->pcm[i].mutex); | 874 | mutex_init(&priv_data->pcm[i].mutex); |
| 875 | 875 | ||
| 876 | /* playback */ | 876 | /* playback */ |
| 877 | if (hsw_dais[i].playback.channels_min) { | 877 | if (hsw_dais[i].playback.channels_min) { |
| 878 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dma_dev, | 878 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dma_dev, |
| 879 | PAGE_SIZE, &priv_data->dmab[i][0]); | 879 | PAGE_SIZE, &priv_data->dmab[i][0]); |
| 880 | if (ret < 0) | 880 | if (ret < 0) |
| 881 | goto err; | 881 | goto err; |
| 882 | } | 882 | } |
| 883 | 883 | ||
| 884 | /* capture */ | 884 | /* capture */ |
| 885 | if (hsw_dais[i].capture.channels_min) { | 885 | if (hsw_dais[i].capture.channels_min) { |
| 886 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dma_dev, | 886 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dma_dev, |
| 887 | PAGE_SIZE, &priv_data->dmab[i][1]); | 887 | PAGE_SIZE, &priv_data->dmab[i][1]); |
| 888 | if (ret < 0) | 888 | if (ret < 0) |
| 889 | goto err; | 889 | goto err; |
| 890 | } | 890 | } |
| 891 | } | 891 | } |
| 892 | 892 | ||
| 893 | /* allocate runtime modules */ | 893 | /* allocate runtime modules */ |
| 894 | hsw_pcm_create_modules(priv_data); | 894 | hsw_pcm_create_modules(priv_data); |
| 895 | 895 | ||
| 896 | /* enable runtime PM with auto suspend */ | 896 | /* enable runtime PM with auto suspend */ |
| 897 | pm_runtime_set_autosuspend_delay(platform->dev, | 897 | pm_runtime_set_autosuspend_delay(platform->dev, |
| 898 | SST_RUNTIME_SUSPEND_DELAY); | 898 | SST_RUNTIME_SUSPEND_DELAY); |
| 899 | pm_runtime_use_autosuspend(platform->dev); | 899 | pm_runtime_use_autosuspend(platform->dev); |
| 900 | pm_runtime_enable(platform->dev); | 900 | pm_runtime_enable(platform->dev); |
| 901 | pm_runtime_idle(platform->dev); | 901 | pm_runtime_idle(platform->dev); |
| 902 | 902 | ||
| 903 | return 0; | 903 | return 0; |
| 904 | 904 | ||
| 905 | err: | 905 | err: |
| 906 | for (;i >= 0; i--) { | 906 | for (;i >= 0; i--) { |
| 907 | if (hsw_dais[i].playback.channels_min) | 907 | if (hsw_dais[i].playback.channels_min) |
| 908 | snd_dma_free_pages(&priv_data->dmab[i][0]); | 908 | snd_dma_free_pages(&priv_data->dmab[i][0]); |
| 909 | if (hsw_dais[i].capture.channels_min) | 909 | if (hsw_dais[i].capture.channels_min) |
| 910 | snd_dma_free_pages(&priv_data->dmab[i][1]); | 910 | snd_dma_free_pages(&priv_data->dmab[i][1]); |
| 911 | } | 911 | } |
| 912 | return ret; | 912 | return ret; |
| 913 | } | 913 | } |
| 914 | 914 | ||
| 915 | static int hsw_pcm_remove(struct snd_soc_platform *platform) | 915 | static int hsw_pcm_remove(struct snd_soc_platform *platform) |
| 916 | { | 916 | { |
| 917 | struct hsw_priv_data *priv_data = | 917 | struct hsw_priv_data *priv_data = |
| 918 | snd_soc_platform_get_drvdata(platform); | 918 | snd_soc_platform_get_drvdata(platform); |
| 919 | int i; | 919 | int i; |
| 920 | 920 | ||
| 921 | pm_runtime_disable(platform->dev); | 921 | pm_runtime_disable(platform->dev); |
| 922 | hsw_pcm_free_modules(priv_data); | 922 | hsw_pcm_free_modules(priv_data); |
| 923 | 923 | ||
| 924 | for (i = 0; i < ARRAY_SIZE(hsw_dais); i++) { | 924 | for (i = 0; i < ARRAY_SIZE(hsw_dais); i++) { |
| 925 | if (hsw_dais[i].playback.channels_min) | 925 | if (hsw_dais[i].playback.channels_min) |
| 926 | snd_dma_free_pages(&priv_data->dmab[i][0]); | 926 | snd_dma_free_pages(&priv_data->dmab[i][0]); |
| 927 | if (hsw_dais[i].capture.channels_min) | 927 | if (hsw_dais[i].capture.channels_min) |
| 928 | snd_dma_free_pages(&priv_data->dmab[i][1]); | 928 | snd_dma_free_pages(&priv_data->dmab[i][1]); |
| 929 | } | 929 | } |
| 930 | 930 | ||
| 931 | return 0; | 931 | return 0; |
| 932 | } | 932 | } |
| 933 | 933 | ||
| 934 | static struct snd_soc_platform_driver hsw_soc_platform = { | 934 | static struct snd_soc_platform_driver hsw_soc_platform = { |
| 935 | .probe = hsw_pcm_probe, | 935 | .probe = hsw_pcm_probe, |
| 936 | .remove = hsw_pcm_remove, | 936 | .remove = hsw_pcm_remove, |
| 937 | .ops = &hsw_pcm_ops, | 937 | .ops = &hsw_pcm_ops, |
| 938 | .pcm_new = hsw_pcm_new, | 938 | .pcm_new = hsw_pcm_new, |
| 939 | .pcm_free = hsw_pcm_free, | 939 | .pcm_free = hsw_pcm_free, |
| 940 | }; | 940 | }; |
| 941 | 941 | ||
| 942 | static const struct snd_soc_component_driver hsw_dai_component = { | 942 | static const struct snd_soc_component_driver hsw_dai_component = { |
| 943 | .name = "haswell-dai", | 943 | .name = "haswell-dai", |
| 944 | .controls = hsw_volume_controls, | 944 | .controls = hsw_volume_controls, |
| 945 | .num_controls = ARRAY_SIZE(hsw_volume_controls), | 945 | .num_controls = ARRAY_SIZE(hsw_volume_controls), |
| 946 | .dapm_widgets = widgets, | 946 | .dapm_widgets = widgets, |
| 947 | .num_dapm_widgets = ARRAY_SIZE(widgets), | 947 | .num_dapm_widgets = ARRAY_SIZE(widgets), |
| 948 | .dapm_routes = graph, | 948 | .dapm_routes = graph, |
| 949 | .num_dapm_routes = ARRAY_SIZE(graph), | 949 | .num_dapm_routes = ARRAY_SIZE(graph), |
| 950 | }; | 950 | }; |
| 951 | 951 | ||
| 952 | static int hsw_pcm_dev_probe(struct platform_device *pdev) | 952 | static int hsw_pcm_dev_probe(struct platform_device *pdev) |
| 953 | { | 953 | { |
| 954 | struct sst_pdata *sst_pdata = dev_get_platdata(&pdev->dev); | 954 | struct sst_pdata *sst_pdata = dev_get_platdata(&pdev->dev); |
| 955 | struct hsw_priv_data *priv_data; | 955 | struct hsw_priv_data *priv_data; |
| 956 | int ret; | 956 | int ret; |
| 957 | 957 | ||
| 958 | if (!sst_pdata) | 958 | if (!sst_pdata) |
| 959 | return -EINVAL; | 959 | return -EINVAL; |
| 960 | 960 | ||
| 961 | priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv_data), GFP_KERNEL); | 961 | priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv_data), GFP_KERNEL); |
| 962 | if (!priv_data) | 962 | if (!priv_data) |
| 963 | return -ENOMEM; | 963 | return -ENOMEM; |
| 964 | 964 | ||
| 965 | ret = sst_hsw_dsp_init(&pdev->dev, sst_pdata); | 965 | ret = sst_hsw_dsp_init(&pdev->dev, sst_pdata); |
| 966 | if (ret < 0) | 966 | if (ret < 0) |
| 967 | return -ENODEV; | 967 | return -ENODEV; |
| 968 | 968 | ||
| 969 | priv_data->hsw = sst_pdata->dsp; | 969 | priv_data->hsw = sst_pdata->dsp; |
| 970 | platform_set_drvdata(pdev, priv_data); | 970 | platform_set_drvdata(pdev, priv_data); |
| 971 | 971 | ||
| 972 | ret = snd_soc_register_platform(&pdev->dev, &hsw_soc_platform); | 972 | ret = snd_soc_register_platform(&pdev->dev, &hsw_soc_platform); |
| 973 | if (ret < 0) | 973 | if (ret < 0) |
| 974 | goto err_plat; | 974 | goto err_plat; |
| 975 | 975 | ||
| 976 | ret = snd_soc_register_component(&pdev->dev, &hsw_dai_component, | 976 | ret = snd_soc_register_component(&pdev->dev, &hsw_dai_component, |
| 977 | hsw_dais, ARRAY_SIZE(hsw_dais)); | 977 | hsw_dais, ARRAY_SIZE(hsw_dais)); |
| 978 | if (ret < 0) | 978 | if (ret < 0) |
| 979 | goto err_comp; | 979 | goto err_comp; |
| 980 | 980 | ||
| 981 | return 0; | 981 | return 0; |
| 982 | 982 | ||
| 983 | err_comp: | 983 | err_comp: |
| 984 | snd_soc_unregister_platform(&pdev->dev); | 984 | snd_soc_unregister_platform(&pdev->dev); |
| 985 | err_plat: | 985 | err_plat: |
| 986 | sst_hsw_dsp_free(&pdev->dev, sst_pdata); | 986 | sst_hsw_dsp_free(&pdev->dev, sst_pdata); |
| 987 | return 0; | 987 | return 0; |
| 988 | } | 988 | } |
| 989 | 989 | ||
| 990 | static int hsw_pcm_dev_remove(struct platform_device *pdev) | 990 | static int hsw_pcm_dev_remove(struct platform_device *pdev) |
| 991 | { | 991 | { |
| 992 | struct sst_pdata *sst_pdata = dev_get_platdata(&pdev->dev); | 992 | struct sst_pdata *sst_pdata = dev_get_platdata(&pdev->dev); |
| 993 | 993 | ||
| 994 | snd_soc_unregister_platform(&pdev->dev); | 994 | snd_soc_unregister_platform(&pdev->dev); |
| 995 | snd_soc_unregister_component(&pdev->dev); | 995 | snd_soc_unregister_component(&pdev->dev); |
| 996 | sst_hsw_dsp_free(&pdev->dev, sst_pdata); | 996 | sst_hsw_dsp_free(&pdev->dev, sst_pdata); |
| 997 | 997 | ||
| 998 | return 0; | 998 | return 0; |
| 999 | } | 999 | } |
| 1000 | 1000 | ||
| 1001 | #ifdef CONFIG_PM_RUNTIME | 1001 | #ifdef CONFIG_PM |
| 1002 | 1002 | ||
| 1003 | static int hsw_pcm_runtime_idle(struct device *dev) | 1003 | static int hsw_pcm_runtime_idle(struct device *dev) |
| 1004 | { | 1004 | { |
| 1005 | return 0; | 1005 | return 0; |
| 1006 | } | 1006 | } |
| 1007 | 1007 | ||
| 1008 | static int hsw_pcm_runtime_suspend(struct device *dev) | 1008 | static int hsw_pcm_runtime_suspend(struct device *dev) |
| 1009 | { | 1009 | { |
| 1010 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); | 1010 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); |
| 1011 | struct sst_hsw *hsw = pdata->hsw; | 1011 | struct sst_hsw *hsw = pdata->hsw; |
| 1012 | 1012 | ||
| 1013 | if (pdata->pm_state == HSW_PM_STATE_D3) | 1013 | if (pdata->pm_state == HSW_PM_STATE_D3) |
| 1014 | return 0; | 1014 | return 0; |
| 1015 | 1015 | ||
| 1016 | sst_hsw_dsp_runtime_suspend(hsw); | 1016 | sst_hsw_dsp_runtime_suspend(hsw); |
| 1017 | sst_hsw_dsp_runtime_sleep(hsw); | 1017 | sst_hsw_dsp_runtime_sleep(hsw); |
| 1018 | pdata->pm_state = HSW_PM_STATE_D3; | 1018 | pdata->pm_state = HSW_PM_STATE_D3; |
| 1019 | 1019 | ||
| 1020 | return 0; | 1020 | return 0; |
| 1021 | } | 1021 | } |
| 1022 | 1022 | ||
| 1023 | static int hsw_pcm_runtime_resume(struct device *dev) | 1023 | static int hsw_pcm_runtime_resume(struct device *dev) |
| 1024 | { | 1024 | { |
| 1025 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); | 1025 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); |
| 1026 | struct sst_hsw *hsw = pdata->hsw; | 1026 | struct sst_hsw *hsw = pdata->hsw; |
| 1027 | int ret; | 1027 | int ret; |
| 1028 | 1028 | ||
| 1029 | if (pdata->pm_state == HSW_PM_STATE_D0) | 1029 | if (pdata->pm_state == HSW_PM_STATE_D0) |
| 1030 | return 0; | 1030 | return 0; |
| 1031 | 1031 | ||
| 1032 | ret = sst_hsw_dsp_load(hsw); | 1032 | ret = sst_hsw_dsp_load(hsw); |
| 1033 | if (ret < 0) { | 1033 | if (ret < 0) { |
| 1034 | dev_err(dev, "failed to reload %d\n", ret); | 1034 | dev_err(dev, "failed to reload %d\n", ret); |
| 1035 | return ret; | 1035 | return ret; |
| 1036 | } | 1036 | } |
| 1037 | 1037 | ||
| 1038 | ret = hsw_pcm_create_modules(pdata); | 1038 | ret = hsw_pcm_create_modules(pdata); |
| 1039 | if (ret < 0) { | 1039 | if (ret < 0) { |
| 1040 | dev_err(dev, "failed to create modules %d\n", ret); | 1040 | dev_err(dev, "failed to create modules %d\n", ret); |
| 1041 | return ret; | 1041 | return ret; |
| 1042 | } | 1042 | } |
| 1043 | 1043 | ||
| 1044 | ret = sst_hsw_dsp_runtime_resume(hsw); | 1044 | ret = sst_hsw_dsp_runtime_resume(hsw); |
| 1045 | if (ret < 0) | 1045 | if (ret < 0) |
| 1046 | return ret; | 1046 | return ret; |
| 1047 | else if (ret == 1) /* no action required */ | 1047 | else if (ret == 1) /* no action required */ |
| 1048 | return 0; | 1048 | return 0; |
| 1049 | 1049 | ||
| 1050 | pdata->pm_state = HSW_PM_STATE_D0; | 1050 | pdata->pm_state = HSW_PM_STATE_D0; |
| 1051 | return ret; | 1051 | return ret; |
| 1052 | } | 1052 | } |
| 1053 | 1053 | ||
| 1054 | #else | 1054 | #else |
| 1055 | #define hsw_pcm_runtime_idle NULL | 1055 | #define hsw_pcm_runtime_idle NULL |
| 1056 | #define hsw_pcm_runtime_suspend NULL | 1056 | #define hsw_pcm_runtime_suspend NULL |
| 1057 | #define hsw_pcm_runtime_resume NULL | 1057 | #define hsw_pcm_runtime_resume NULL |
| 1058 | #endif | 1058 | #endif |
| 1059 | 1059 | ||
| 1060 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PM_RUNTIME) | 1060 | #ifdef CONFIG_PM |
| 1061 | 1061 | ||
| 1062 | static void hsw_pcm_complete(struct device *dev) | 1062 | static void hsw_pcm_complete(struct device *dev) |
| 1063 | { | 1063 | { |
| 1064 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); | 1064 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); |
| 1065 | struct sst_hsw *hsw = pdata->hsw; | 1065 | struct sst_hsw *hsw = pdata->hsw; |
| 1066 | struct hsw_pcm_data *pcm_data; | 1066 | struct hsw_pcm_data *pcm_data; |
| 1067 | int i, err; | 1067 | int i, err; |
| 1068 | 1068 | ||
| 1069 | if (pdata->pm_state == HSW_PM_STATE_D0) | 1069 | if (pdata->pm_state == HSW_PM_STATE_D0) |
| 1070 | return; | 1070 | return; |
| 1071 | 1071 | ||
| 1072 | err = sst_hsw_dsp_load(hsw); | 1072 | err = sst_hsw_dsp_load(hsw); |
| 1073 | if (err < 0) { | 1073 | if (err < 0) { |
| 1074 | dev_err(dev, "failed to reload %d\n", err); | 1074 | dev_err(dev, "failed to reload %d\n", err); |
| 1075 | return; | 1075 | return; |
| 1076 | } | 1076 | } |
| 1077 | 1077 | ||
| 1078 | err = hsw_pcm_create_modules(pdata); | 1078 | err = hsw_pcm_create_modules(pdata); |
| 1079 | if (err < 0) { | 1079 | if (err < 0) { |
| 1080 | dev_err(dev, "failed to create modules %d\n", err); | 1080 | dev_err(dev, "failed to create modules %d\n", err); |
| 1081 | return; | 1081 | return; |
| 1082 | } | 1082 | } |
| 1083 | 1083 | ||
| 1084 | for (i = 0; i < HSW_PCM_DAI_ID_CAPTURE + 1; i++) { | 1084 | for (i = 0; i < HSW_PCM_DAI_ID_CAPTURE + 1; i++) { |
| 1085 | pcm_data = &pdata->pcm[i]; | 1085 | pcm_data = &pdata->pcm[i]; |
| 1086 | 1086 | ||
| 1087 | if (!pcm_data->substream) | 1087 | if (!pcm_data->substream) |
| 1088 | continue; | 1088 | continue; |
| 1089 | 1089 | ||
| 1090 | err = sst_module_runtime_restore(pcm_data->runtime, | 1090 | err = sst_module_runtime_restore(pcm_data->runtime, |
| 1091 | &pcm_data->context); | 1091 | &pcm_data->context); |
| 1092 | if (err < 0) | 1092 | if (err < 0) |
| 1093 | dev_err(dev, "failed to restore context for PCM %d\n", i); | 1093 | dev_err(dev, "failed to restore context for PCM %d\n", i); |
| 1094 | } | 1094 | } |
| 1095 | 1095 | ||
| 1096 | snd_soc_resume(pdata->soc_card->dev); | 1096 | snd_soc_resume(pdata->soc_card->dev); |
| 1097 | 1097 | ||
| 1098 | err = sst_hsw_dsp_runtime_resume(hsw); | 1098 | err = sst_hsw_dsp_runtime_resume(hsw); |
| 1099 | if (err < 0) | 1099 | if (err < 0) |
| 1100 | return; | 1100 | return; |
| 1101 | else if (err == 1) /* no action required */ | 1101 | else if (err == 1) /* no action required */ |
| 1102 | return; | 1102 | return; |
| 1103 | 1103 | ||
| 1104 | pdata->pm_state = HSW_PM_STATE_D0; | 1104 | pdata->pm_state = HSW_PM_STATE_D0; |
| 1105 | return; | 1105 | return; |
| 1106 | } | 1106 | } |
| 1107 | 1107 | ||
| 1108 | static int hsw_pcm_prepare(struct device *dev) | 1108 | static int hsw_pcm_prepare(struct device *dev) |
| 1109 | { | 1109 | { |
| 1110 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); | 1110 | struct hsw_priv_data *pdata = dev_get_drvdata(dev); |
| 1111 | struct sst_hsw *hsw = pdata->hsw; | 1111 | struct sst_hsw *hsw = pdata->hsw; |
| 1112 | struct hsw_pcm_data *pcm_data; | 1112 | struct hsw_pcm_data *pcm_data; |
| 1113 | int i, err; | 1113 | int i, err; |
| 1114 | 1114 | ||
| 1115 | if (pdata->pm_state == HSW_PM_STATE_D3) | 1115 | if (pdata->pm_state == HSW_PM_STATE_D3) |
| 1116 | return 0; | 1116 | return 0; |
| 1117 | /* suspend all active streams */ | 1117 | /* suspend all active streams */ |
| 1118 | for (i = 0; i < HSW_PCM_DAI_ID_CAPTURE + 1; i++) { | 1118 | for (i = 0; i < HSW_PCM_DAI_ID_CAPTURE + 1; i++) { |
| 1119 | pcm_data = &pdata->pcm[i]; | 1119 | pcm_data = &pdata->pcm[i]; |
| 1120 | 1120 | ||
| 1121 | if (!pcm_data->substream) | 1121 | if (!pcm_data->substream) |
| 1122 | continue; | 1122 | continue; |
| 1123 | dev_dbg(dev, "suspending pcm %d\n", i); | 1123 | dev_dbg(dev, "suspending pcm %d\n", i); |
| 1124 | snd_pcm_suspend_all(pcm_data->hsw_pcm); | 1124 | snd_pcm_suspend_all(pcm_data->hsw_pcm); |
| 1125 | 1125 | ||
| 1126 | /* We need to wait until the DSP FW stops the streams */ | 1126 | /* We need to wait until the DSP FW stops the streams */ |
| 1127 | msleep(2); | 1127 | msleep(2); |
| 1128 | } | 1128 | } |
| 1129 | 1129 | ||
| 1130 | snd_soc_suspend(pdata->soc_card->dev); | 1130 | snd_soc_suspend(pdata->soc_card->dev); |
| 1131 | snd_soc_poweroff(pdata->soc_card->dev); | 1131 | snd_soc_poweroff(pdata->soc_card->dev); |
| 1132 | 1132 | ||
| 1133 | /* enter D3 state and stall */ | 1133 | /* enter D3 state and stall */ |
| 1134 | sst_hsw_dsp_runtime_suspend(hsw); | 1134 | sst_hsw_dsp_runtime_suspend(hsw); |
| 1135 | 1135 | ||
| 1136 | /* preserve persistent memory */ | 1136 | /* preserve persistent memory */ |
| 1137 | for (i = 0; i < HSW_PCM_DAI_ID_CAPTURE + 1; i++) { | 1137 | for (i = 0; i < HSW_PCM_DAI_ID_CAPTURE + 1; i++) { |
| 1138 | pcm_data = &pdata->pcm[i]; | 1138 | pcm_data = &pdata->pcm[i]; |
| 1139 | 1139 | ||
| 1140 | if (!pcm_data->substream) | 1140 | if (!pcm_data->substream) |
| 1141 | continue; | 1141 | continue; |
| 1142 | 1142 | ||
| 1143 | dev_dbg(dev, "saving context pcm %d\n", i); | 1143 | dev_dbg(dev, "saving context pcm %d\n", i); |
| 1144 | err = sst_module_runtime_save(pcm_data->runtime, | 1144 | err = sst_module_runtime_save(pcm_data->runtime, |
| 1145 | &pcm_data->context); | 1145 | &pcm_data->context); |
| 1146 | if (err < 0) | 1146 | if (err < 0) |
| 1147 | dev_err(dev, "failed to save context for PCM %d\n", i); | 1147 | dev_err(dev, "failed to save context for PCM %d\n", i); |
| 1148 | } | 1148 | } |
| 1149 | 1149 | ||
| 1150 | /* put the DSP to sleep */ | 1150 | /* put the DSP to sleep */ |
| 1151 | sst_hsw_dsp_runtime_sleep(hsw); | 1151 | sst_hsw_dsp_runtime_sleep(hsw); |
| 1152 | pdata->pm_state = HSW_PM_STATE_D3; | 1152 | pdata->pm_state = HSW_PM_STATE_D3; |
| 1153 | 1153 | ||
| 1154 | return 0; | 1154 | return 0; |
| 1155 | } | 1155 | } |
| 1156 | 1156 | ||
| 1157 | #else | 1157 | #else |
| 1158 | #define hsw_pcm_prepare NULL | 1158 | #define hsw_pcm_prepare NULL |
| 1159 | #define hsw_pcm_complete NULL | 1159 | #define hsw_pcm_complete NULL |
| 1160 | #endif | 1160 | #endif |
| 1161 | 1161 | ||
| 1162 | static const struct dev_pm_ops hsw_pcm_pm = { | 1162 | static const struct dev_pm_ops hsw_pcm_pm = { |
| 1163 | .runtime_idle = hsw_pcm_runtime_idle, | 1163 | .runtime_idle = hsw_pcm_runtime_idle, |
| 1164 | .runtime_suspend = hsw_pcm_runtime_suspend, | 1164 | .runtime_suspend = hsw_pcm_runtime_suspend, |
| 1165 | .runtime_resume = hsw_pcm_runtime_resume, | 1165 | .runtime_resume = hsw_pcm_runtime_resume, |
| 1166 | .prepare = hsw_pcm_prepare, | 1166 | .prepare = hsw_pcm_prepare, |
| 1167 | .complete = hsw_pcm_complete, | 1167 | .complete = hsw_pcm_complete, |
| 1168 | }; | 1168 | }; |
| 1169 | 1169 | ||
| 1170 | static struct platform_driver hsw_pcm_driver = { | 1170 | static struct platform_driver hsw_pcm_driver = { |
| 1171 | .driver = { | 1171 | .driver = { |
| 1172 | .name = "haswell-pcm-audio", | 1172 | .name = "haswell-pcm-audio", |
| 1173 | .pm = &hsw_pcm_pm, | 1173 | .pm = &hsw_pcm_pm, |
| 1174 | }, | 1174 | }, |
| 1175 | 1175 | ||
| 1176 | .probe = hsw_pcm_dev_probe, | 1176 | .probe = hsw_pcm_dev_probe, |
| 1177 | .remove = hsw_pcm_dev_remove, | 1177 | .remove = hsw_pcm_dev_remove, |
| 1178 | }; | 1178 | }; |
| 1179 | module_platform_driver(hsw_pcm_driver); | 1179 | module_platform_driver(hsw_pcm_driver); |
| 1180 | 1180 | ||
| 1181 | MODULE_AUTHOR("Liam Girdwood, Xingchao Wang"); | 1181 | MODULE_AUTHOR("Liam Girdwood, Xingchao Wang"); |
| 1182 | MODULE_DESCRIPTION("Haswell/Lynxpoint + Broadwell/Wildcatpoint PCM"); | 1182 | MODULE_DESCRIPTION("Haswell/Lynxpoint + Broadwell/Wildcatpoint PCM"); |
| 1183 | MODULE_LICENSE("GPL v2"); | 1183 | MODULE_LICENSE("GPL v2"); |
| 1184 | MODULE_ALIAS("platform:haswell-pcm-audio"); | 1184 | MODULE_ALIAS("platform:haswell-pcm-audio"); |
| 1185 | 1185 |