Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 6548be50135e2a406c767cfef246b7d5a1c1cc66

Authored by Dan Murphy 2014-06-05 00:05:02 +0800

Exists in ti-linux-3.15.y and in 1 other branch

Merge branch 'master' of http://git.kernel.org/pub/scm/linux/kernel/git/torvalds…

…/linux into ti-linux-3.15.y

* 'master' of http://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux:
  intel_pstate: Improve initial busy calculation
  intel_pstate: add sample time scaling
  intel_pstate: Correct rounding in busy calculation
  intel_pstate: Remove C0 tracking
  drm/radeon: use the CP DMA on CIK
  drm/radeon: sync page table updates
  drm/radeon: fix vm buffer size estimation
  drm/crtc-helper: skip locking checks in panicking path
  drm/radeon/dpm: resume fixes for some systems

Signed-off-by: Dan Murphy <DMurphy@ti.com>

Showing 7 changed files Inline Diff

drivers/cpufreq/intel_pstate.c
drivers/gpu/drm/drm_crtc_helper.c
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/radeon_vm.c

drivers/cpufreq/intel_pstate.c

Diff comments View file @ 6548be5

1	/*	1	/*
2	* intel_pstate.c: Native P state management for Intel processors	2	* intel_pstate.c: Native P state management for Intel processors
3	*	3	*
4	* (C) Copyright 2012 Intel Corporation	4	* (C) Copyright 2012 Intel Corporation
5	* Author: Dirk Brandewie <dirk.j.brandewie@intel.com>	5	* Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6	*	6	*
7	* This program is free software; you can redistribute it and/or	7	* This program is free software; you can redistribute it and/or
8	* modify it under the terms of the GNU General Public License	8	* modify it under the terms of the GNU General Public License
9	* as published by the Free Software Foundation; version 2	9	* as published by the Free Software Foundation; version 2
10	* of the License.	10	* of the License.
11	*/	11	*/
12		12
13	#include <linux/kernel.h>	13	#include <linux/kernel.h>
14	#include <linux/kernel_stat.h>	14	#include <linux/kernel_stat.h>
15	#include <linux/module.h>	15	#include <linux/module.h>
16	#include <linux/ktime.h>	16	#include <linux/ktime.h>
17	#include <linux/hrtimer.h>	17	#include <linux/hrtimer.h>
18	#include <linux/tick.h>	18	#include <linux/tick.h>
19	#include <linux/slab.h>	19	#include <linux/slab.h>
20	#include <linux/sched.h>	20	#include <linux/sched.h>
21	#include <linux/list.h>	21	#include <linux/list.h>
22	#include <linux/cpu.h>	22	#include <linux/cpu.h>
23	#include <linux/cpufreq.h>	23	#include <linux/cpufreq.h>
24	#include <linux/sysfs.h>	24	#include <linux/sysfs.h>
25	#include <linux/types.h>	25	#include <linux/types.h>
26	#include <linux/fs.h>	26	#include <linux/fs.h>
27	#include <linux/debugfs.h>	27	#include <linux/debugfs.h>
28	#include <linux/acpi.h>	28	#include <linux/acpi.h>
29	#include <trace/events/power.h>	29	#include <trace/events/power.h>
30		30
31	#include <asm/div64.h>	31	#include <asm/div64.h>
32	#include <asm/msr.h>	32	#include <asm/msr.h>
33	#include <asm/cpu_device_id.h>	33	#include <asm/cpu_device_id.h>
34		34
35	#define SAMPLE_COUNT 3	35	#define SAMPLE_COUNT 3
36		36
37	#define BYT_RATIOS 0x66a	37	#define BYT_RATIOS 0x66a
38	#define BYT_VIDS 0x66b	38	#define BYT_VIDS 0x66b
39	#define BYT_TURBO_RATIOS 0x66c	39	#define BYT_TURBO_RATIOS 0x66c
40	#define BYT_TURBO_VIDS 0x66d	40	#define BYT_TURBO_VIDS 0x66d
41		41
42		42
43	#define FRAC_BITS 6	43	#define FRAC_BITS 8
44	#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)	44	#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
45	#define fp_toint(X) ((X) >> FRAC_BITS)	45	#define fp_toint(X) ((X) >> FRAC_BITS)
46	#define FP_ROUNDUP(X) ((X) += 1 << FRAC_BITS)
47		46
		47
48	static inline int32_t mul_fp(int32_t x, int32_t y)	48	static inline int32_t mul_fp(int32_t x, int32_t y)
49	{	49	{
50	return ((int64_t)x * (int64_t)y) >> FRAC_BITS;	50	return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
51	}	51	}
52		52
53	static inline int32_t div_fp(int32_t x, int32_t y)	53	static inline int32_t div_fp(int32_t x, int32_t y)
54	{	54	{
55	return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);	55	return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);
56	}	56	}
57		57
58	struct sample {	58	struct sample {
59	int32_t core_pct_busy;	59	int32_t core_pct_busy;
60	u64 aperf;	60	u64 aperf;
61	u64 mperf;	61	u64 mperf;
62	unsigned long long tsc;
63	int freq;	62	int freq;
		63	ktime_t time;
64	};	64	};
65		65
66	struct pstate_data {	66	struct pstate_data {
67	int current_pstate;	67	int current_pstate;
68	int min_pstate;	68	int min_pstate;
69	int max_pstate;	69	int max_pstate;
70	int turbo_pstate;	70	int turbo_pstate;
71	};	71	};
72		72
73	struct vid_data {	73	struct vid_data {
74	int min;	74	int min;
75	int max;	75	int max;
76	int turbo;	76	int turbo;
77	int32_t ratio;	77	int32_t ratio;
78	};	78	};
79		79
80	struct _pid {	80	struct _pid {
81	int setpoint;	81	int setpoint;
82	int32_t integral;	82	int32_t integral;
83	int32_t p_gain;	83	int32_t p_gain;
84	int32_t i_gain;	84	int32_t i_gain;
85	int32_t d_gain;	85	int32_t d_gain;
86	int deadband;	86	int deadband;
87	int32_t last_err;	87	int32_t last_err;
88	};	88	};
89		89
90	struct cpudata {	90	struct cpudata {
91	int cpu;	91	int cpu;
92		92
93	char name[64];	93	char name[64];
94		94
95	struct timer_list timer;	95	struct timer_list timer;
96		96
97	struct pstate_data pstate;	97	struct pstate_data pstate;
98	struct vid_data vid;	98	struct vid_data vid;
99	struct _pid pid;	99	struct _pid pid;
100		100
		101	ktime_t last_sample_time;
101	u64 prev_aperf;	102	u64 prev_aperf;
102	u64 prev_mperf;	103	u64 prev_mperf;
103	unsigned long long prev_tsc;
104	struct sample sample;	104	struct sample sample;
105	};	105	};
106		106
107	static struct cpudata **all_cpu_data;	107	static struct cpudata **all_cpu_data;
108	struct pstate_adjust_policy {	108	struct pstate_adjust_policy {
109	int sample_rate_ms;	109	int sample_rate_ms;
110	int deadband;	110	int deadband;
111	int setpoint;	111	int setpoint;
112	int p_gain_pct;	112	int p_gain_pct;
113	int d_gain_pct;	113	int d_gain_pct;
114	int i_gain_pct;	114	int i_gain_pct;
115	};	115	};
116		116
117	struct pstate_funcs {	117	struct pstate_funcs {
118	int (*get_max)(void);	118	int (*get_max)(void);
119	int (*get_min)(void);	119	int (*get_min)(void);
120	int (*get_turbo)(void);	120	int (*get_turbo)(void);
121	void (set)(struct cpudata, int pstate);	121	void (set)(struct cpudata, int pstate);
122	void (get_vid)(struct cpudata );	122	void (get_vid)(struct cpudata );
123	};	123	};
124		124
125	struct cpu_defaults {	125	struct cpu_defaults {
126	struct pstate_adjust_policy pid_policy;	126	struct pstate_adjust_policy pid_policy;
127	struct pstate_funcs funcs;	127	struct pstate_funcs funcs;
128	};	128	};
129		129
130	static struct pstate_adjust_policy pid_params;	130	static struct pstate_adjust_policy pid_params;
131	static struct pstate_funcs pstate_funcs;	131	static struct pstate_funcs pstate_funcs;
132		132
133	struct perf_limits {	133	struct perf_limits {
134	int no_turbo;	134	int no_turbo;
135	int max_perf_pct;	135	int max_perf_pct;
136	int min_perf_pct;	136	int min_perf_pct;
137	int32_t max_perf;	137	int32_t max_perf;
138	int32_t min_perf;	138	int32_t min_perf;
139	int max_policy_pct;	139	int max_policy_pct;
140	int max_sysfs_pct;	140	int max_sysfs_pct;
141	};	141	};
142		142
143	static struct perf_limits limits = {	143	static struct perf_limits limits = {
144	.no_turbo = 0,	144	.no_turbo = 0,
145	.max_perf_pct = 100,	145	.max_perf_pct = 100,
146	.max_perf = int_tofp(1),	146	.max_perf = int_tofp(1),
147	.min_perf_pct = 0,	147	.min_perf_pct = 0,
148	.min_perf = 0,	148	.min_perf = 0,
149	.max_policy_pct = 100,	149	.max_policy_pct = 100,
150	.max_sysfs_pct = 100,	150	.max_sysfs_pct = 100,
151	};	151	};
152		152
153	static inline void pid_reset(struct _pid *pid, int setpoint, int busy,	153	static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
154	int deadband, int integral) {	154	int deadband, int integral) {
155	pid->setpoint = setpoint;	155	pid->setpoint = setpoint;
156	pid->deadband = deadband;	156	pid->deadband = deadband;
157	pid->integral = int_tofp(integral);	157	pid->integral = int_tofp(integral);
158	pid->last_err = int_tofp(setpoint) - int_tofp(busy);	158	pid->last_err = int_tofp(setpoint) - int_tofp(busy);
159	}	159	}
160		160
161	static inline void pid_p_gain_set(struct _pid *pid, int percent)	161	static inline void pid_p_gain_set(struct _pid *pid, int percent)
162	{	162	{
163	pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));	163	pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
164	}	164	}
165		165
166	static inline void pid_i_gain_set(struct _pid *pid, int percent)	166	static inline void pid_i_gain_set(struct _pid *pid, int percent)
167	{	167	{
168	pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));	168	pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
169	}	169	}
170		170
171	static inline void pid_d_gain_set(struct _pid *pid, int percent)	171	static inline void pid_d_gain_set(struct _pid *pid, int percent)
172	{	172	{
173		173
174	pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));	174	pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
175	}	175	}
176		176
177	static signed int pid_calc(struct _pid *pid, int32_t busy)	177	static signed int pid_calc(struct _pid *pid, int32_t busy)
178	{	178	{
179	signed int result;	179	signed int result;
180	int32_t pterm, dterm, fp_error;	180	int32_t pterm, dterm, fp_error;
181	int32_t integral_limit;	181	int32_t integral_limit;
182		182
183	fp_error = int_tofp(pid->setpoint) - busy;	183	fp_error = int_tofp(pid->setpoint) - busy;
184		184
185	if (abs(fp_error) <= int_tofp(pid->deadband))	185	if (abs(fp_error) <= int_tofp(pid->deadband))
186	return 0;	186	return 0;
187		187
188	pterm = mul_fp(pid->p_gain, fp_error);	188	pterm = mul_fp(pid->p_gain, fp_error);
189		189
190	pid->integral += fp_error;	190	pid->integral += fp_error;
191		191
192	/* limit the integral term */	192	/* limit the integral term */
193	integral_limit = int_tofp(30);	193	integral_limit = int_tofp(30);
194	if (pid->integral > integral_limit)	194	if (pid->integral > integral_limit)
195	pid->integral = integral_limit;	195	pid->integral = integral_limit;
196	if (pid->integral < -integral_limit)	196	if (pid->integral < -integral_limit)
197	pid->integral = -integral_limit;	197	pid->integral = -integral_limit;
198		198
199	dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);	199	dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
200	pid->last_err = fp_error;	200	pid->last_err = fp_error;
201		201
202	result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;	202	result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
203		203	if (result >= 0)
		204	result = result + (1 << (FRAC_BITS-1));
		205	else
		206	result = result - (1 << (FRAC_BITS-1));
204	return (signed int)fp_toint(result);	207	return (signed int)fp_toint(result);
205	}	208	}
206		209
207	static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)	210	static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
208	{	211	{
209	pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);	212	pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
210	pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);	213	pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
211	pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);	214	pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
212		215
213	pid_reset(&cpu->pid,	216	pid_reset(&cpu->pid,
214	pid_params.setpoint,	217	pid_params.setpoint,
215	100,	218	100,
216	pid_params.deadband,	219	pid_params.deadband,
217	0);	220	0);
218	}	221	}
219		222
220	static inline void intel_pstate_reset_all_pid(void)	223	static inline void intel_pstate_reset_all_pid(void)
221	{	224	{
222	unsigned int cpu;	225	unsigned int cpu;
223	for_each_online_cpu(cpu) {	226	for_each_online_cpu(cpu) {
224	if (all_cpu_data[cpu])	227	if (all_cpu_data[cpu])
225	intel_pstate_busy_pid_reset(all_cpu_data[cpu]);	228	intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
226	}	229	}
227	}	230	}
228		231
229	/************************ debugfs begin **********************/	232	/************************ debugfs begin **********************/
230	static int pid_param_set(void *data, u64 val)	233	static int pid_param_set(void *data, u64 val)
231	{	234	{
232	(u32 )data = val;	235	(u32 )data = val;
233	intel_pstate_reset_all_pid();	236	intel_pstate_reset_all_pid();
234	return 0;	237	return 0;
235	}	238	}
236	static int pid_param_get(void data, u64 val)	239	static int pid_param_get(void data, u64 val)
237	{	240	{
238	val = (u32 *)data;	241	val = (u32 *)data;
239	return 0;	242	return 0;
240	}	243	}
241	DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,	244	DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,
242	pid_param_set, "%llu\n");	245	pid_param_set, "%llu\n");
243		246
244	struct pid_param {	247	struct pid_param {
245	char *name;	248	char *name;
246	void *value;	249	void *value;
247	};	250	};
248		251
249	static struct pid_param pid_files[] = {	252	static struct pid_param pid_files[] = {
250	{"sample_rate_ms", &pid_params.sample_rate_ms},	253	{"sample_rate_ms", &pid_params.sample_rate_ms},
251	{"d_gain_pct", &pid_params.d_gain_pct},	254	{"d_gain_pct", &pid_params.d_gain_pct},
252	{"i_gain_pct", &pid_params.i_gain_pct},	255	{"i_gain_pct", &pid_params.i_gain_pct},
253	{"deadband", &pid_params.deadband},	256	{"deadband", &pid_params.deadband},
254	{"setpoint", &pid_params.setpoint},	257	{"setpoint", &pid_params.setpoint},
255	{"p_gain_pct", &pid_params.p_gain_pct},	258	{"p_gain_pct", &pid_params.p_gain_pct},
256	{NULL, NULL}	259	{NULL, NULL}
257	};	260	};
258		261
259	static struct dentry *debugfs_parent;	262	static struct dentry *debugfs_parent;
260	static void intel_pstate_debug_expose_params(void)	263	static void intel_pstate_debug_expose_params(void)
261	{	264	{
262	int i = 0;	265	int i = 0;
263		266
264	debugfs_parent = debugfs_create_dir("pstate_snb", NULL);	267	debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
265	if (IS_ERR_OR_NULL(debugfs_parent))	268	if (IS_ERR_OR_NULL(debugfs_parent))
266	return;	269	return;
267	while (pid_files[i].name) {	270	while (pid_files[i].name) {
268	debugfs_create_file(pid_files[i].name, 0660,	271	debugfs_create_file(pid_files[i].name, 0660,
269	debugfs_parent, pid_files[i].value,	272	debugfs_parent, pid_files[i].value,
270	&fops_pid_param);	273	&fops_pid_param);
271	i++;	274	i++;
272	}	275	}
273	}	276	}
274		277
275	/************************ debugfs end **********************/	278	/************************ debugfs end **********************/
276		279
277	/************************ sysfs begin **********************/	280	/************************ sysfs begin **********************/
278	#define show_one(file_name, object) \	281	#define show_one(file_name, object) \
279	static ssize_t show_##file_name \	282	static ssize_t show_##file_name \
280	(struct kobject kobj, struct attribute attr, char *buf) \	283	(struct kobject kobj, struct attribute attr, char *buf) \
281	{ \	284	{ \
282	return sprintf(buf, "%u\n", limits.object); \	285	return sprintf(buf, "%u\n", limits.object); \
283	}	286	}
284		287
285	static ssize_t store_no_turbo(struct kobject a, struct attribute b,	288	static ssize_t store_no_turbo(struct kobject a, struct attribute b,
286	const char *buf, size_t count)	289	const char *buf, size_t count)
287	{	290	{
288	unsigned int input;	291	unsigned int input;
289	int ret;	292	int ret;
290	ret = sscanf(buf, "%u", &input);	293	ret = sscanf(buf, "%u", &input);
291	if (ret != 1)	294	if (ret != 1)
292	return -EINVAL;	295	return -EINVAL;
293	limits.no_turbo = clamp_t(int, input, 0 , 1);	296	limits.no_turbo = clamp_t(int, input, 0 , 1);
294		297
295	return count;	298	return count;
296	}	299	}
297		300
298	static ssize_t store_max_perf_pct(struct kobject a, struct attribute b,	301	static ssize_t store_max_perf_pct(struct kobject a, struct attribute b,
299	const char *buf, size_t count)	302	const char *buf, size_t count)
300	{	303	{
301	unsigned int input;	304	unsigned int input;
302	int ret;	305	int ret;
303	ret = sscanf(buf, "%u", &input);	306	ret = sscanf(buf, "%u", &input);
304	if (ret != 1)	307	if (ret != 1)
305	return -EINVAL;	308	return -EINVAL;
306		309
307	limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);	310	limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
308	limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);	311	limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
309	limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));	312	limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
310	return count;	313	return count;
311	}	314	}
312		315
313	static ssize_t store_min_perf_pct(struct kobject a, struct attribute b,	316	static ssize_t store_min_perf_pct(struct kobject a, struct attribute b,
314	const char *buf, size_t count)	317	const char *buf, size_t count)
315	{	318	{
316	unsigned int input;	319	unsigned int input;
317	int ret;	320	int ret;
318	ret = sscanf(buf, "%u", &input);	321	ret = sscanf(buf, "%u", &input);
319	if (ret != 1)	322	if (ret != 1)
320	return -EINVAL;	323	return -EINVAL;
321	limits.min_perf_pct = clamp_t(int, input, 0 , 100);	324	limits.min_perf_pct = clamp_t(int, input, 0 , 100);
322	limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));	325	limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
323		326
324	return count;	327	return count;
325	}	328	}
326		329
327	show_one(no_turbo, no_turbo);	330	show_one(no_turbo, no_turbo);
328	show_one(max_perf_pct, max_perf_pct);	331	show_one(max_perf_pct, max_perf_pct);
329	show_one(min_perf_pct, min_perf_pct);	332	show_one(min_perf_pct, min_perf_pct);
330		333
331	define_one_global_rw(no_turbo);	334	define_one_global_rw(no_turbo);
332	define_one_global_rw(max_perf_pct);	335	define_one_global_rw(max_perf_pct);
333	define_one_global_rw(min_perf_pct);	336	define_one_global_rw(min_perf_pct);
334		337
335	static struct attribute *intel_pstate_attributes[] = {	338	static struct attribute *intel_pstate_attributes[] = {
336	&no_turbo.attr,	339	&no_turbo.attr,
337	&max_perf_pct.attr,	340	&max_perf_pct.attr,
338	&min_perf_pct.attr,	341	&min_perf_pct.attr,
339	NULL	342	NULL
340	};	343	};
341		344
342	static struct attribute_group intel_pstate_attr_group = {	345	static struct attribute_group intel_pstate_attr_group = {
343	.attrs = intel_pstate_attributes,	346	.attrs = intel_pstate_attributes,
344	};	347	};
345	static struct kobject *intel_pstate_kobject;	348	static struct kobject *intel_pstate_kobject;
346		349
347	static void intel_pstate_sysfs_expose_params(void)	350	static void intel_pstate_sysfs_expose_params(void)
348	{	351	{
349	int rc;	352	int rc;
350		353
351	intel_pstate_kobject = kobject_create_and_add("intel_pstate",	354	intel_pstate_kobject = kobject_create_and_add("intel_pstate",
352	&cpu_subsys.dev_root->kobj);	355	&cpu_subsys.dev_root->kobj);
353	BUG_ON(!intel_pstate_kobject);	356	BUG_ON(!intel_pstate_kobject);
354	rc = sysfs_create_group(intel_pstate_kobject,	357	rc = sysfs_create_group(intel_pstate_kobject,
355	&intel_pstate_attr_group);	358	&intel_pstate_attr_group);
356	BUG_ON(rc);	359	BUG_ON(rc);
357	}	360	}
358		361
359	/************************ sysfs end **********************/	362	/************************ sysfs end **********************/
360	static int byt_get_min_pstate(void)	363	static int byt_get_min_pstate(void)
361	{	364	{
362	u64 value;	365	u64 value;
363	rdmsrl(BYT_RATIOS, value);	366	rdmsrl(BYT_RATIOS, value);
364	return (value >> 8) & 0x3F;	367	return (value >> 8) & 0x3F;
365	}	368	}
366		369
367	static int byt_get_max_pstate(void)	370	static int byt_get_max_pstate(void)
368	{	371	{
369	u64 value;	372	u64 value;
370	rdmsrl(BYT_RATIOS, value);	373	rdmsrl(BYT_RATIOS, value);
371	return (value >> 16) & 0x3F;	374	return (value >> 16) & 0x3F;
372	}	375	}
373		376
374	static int byt_get_turbo_pstate(void)	377	static int byt_get_turbo_pstate(void)
375	{	378	{
376	u64 value;	379	u64 value;
377	rdmsrl(BYT_TURBO_RATIOS, value);	380	rdmsrl(BYT_TURBO_RATIOS, value);
378	return value & 0x3F;	381	return value & 0x3F;
379	}	382	}
380		383
381	static void byt_set_pstate(struct cpudata *cpudata, int pstate)	384	static void byt_set_pstate(struct cpudata *cpudata, int pstate)
382	{	385	{
383	u64 val;	386	u64 val;
384	int32_t vid_fp;	387	int32_t vid_fp;
385	u32 vid;	388	u32 vid;
386		389
387	val = pstate << 8;	390	val = pstate << 8;
388	if (limits.no_turbo)	391	if (limits.no_turbo)
389	val \|= (u64)1 << 32;	392	val \|= (u64)1 << 32;
390		393
391	vid_fp = cpudata->vid.min + mul_fp(	394	vid_fp = cpudata->vid.min + mul_fp(
392	int_tofp(pstate - cpudata->pstate.min_pstate),	395	int_tofp(pstate - cpudata->pstate.min_pstate),
393	cpudata->vid.ratio);	396	cpudata->vid.ratio);
394		397
395	vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);	398	vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
396	vid = fp_toint(vid_fp);	399	vid = fp_toint(vid_fp);
397		400
398	if (pstate > cpudata->pstate.max_pstate)	401	if (pstate > cpudata->pstate.max_pstate)
399	vid = cpudata->vid.turbo;	402	vid = cpudata->vid.turbo;
400		403
401	val \|= vid;	404	val \|= vid;
402		405
403	wrmsrl(MSR_IA32_PERF_CTL, val);	406	wrmsrl(MSR_IA32_PERF_CTL, val);
404	}	407	}
405		408
406	static void byt_get_vid(struct cpudata *cpudata)	409	static void byt_get_vid(struct cpudata *cpudata)
407	{	410	{
408	u64 value;	411	u64 value;
409		412
410		413
411	rdmsrl(BYT_VIDS, value);	414	rdmsrl(BYT_VIDS, value);
412	cpudata->vid.min = int_tofp((value >> 8) & 0x3f);	415	cpudata->vid.min = int_tofp((value >> 8) & 0x3f);
413	cpudata->vid.max = int_tofp((value >> 16) & 0x3f);	416	cpudata->vid.max = int_tofp((value >> 16) & 0x3f);
414	cpudata->vid.ratio = div_fp(	417	cpudata->vid.ratio = div_fp(
415	cpudata->vid.max - cpudata->vid.min,	418	cpudata->vid.max - cpudata->vid.min,
416	int_tofp(cpudata->pstate.max_pstate -	419	int_tofp(cpudata->pstate.max_pstate -
417	cpudata->pstate.min_pstate));	420	cpudata->pstate.min_pstate));
418		421
419	rdmsrl(BYT_TURBO_VIDS, value);	422	rdmsrl(BYT_TURBO_VIDS, value);
420	cpudata->vid.turbo = value & 0x7f;	423	cpudata->vid.turbo = value & 0x7f;
421	}	424	}
422		425
423		426
424	static int core_get_min_pstate(void)	427	static int core_get_min_pstate(void)
425	{	428	{
426	u64 value;	429	u64 value;
427	rdmsrl(MSR_PLATFORM_INFO, value);	430	rdmsrl(MSR_PLATFORM_INFO, value);
428	return (value >> 40) & 0xFF;	431	return (value >> 40) & 0xFF;
429	}	432	}
430		433
431	static int core_get_max_pstate(void)	434	static int core_get_max_pstate(void)
432	{	435	{
433	u64 value;	436	u64 value;
434	rdmsrl(MSR_PLATFORM_INFO, value);	437	rdmsrl(MSR_PLATFORM_INFO, value);
435	return (value >> 8) & 0xFF;	438	return (value >> 8) & 0xFF;
436	}	439	}
437		440
438	static int core_get_turbo_pstate(void)	441	static int core_get_turbo_pstate(void)
439	{	442	{
440	u64 value;	443	u64 value;
441	int nont, ret;	444	int nont, ret;
442	rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);	445	rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
443	nont = core_get_max_pstate();	446	nont = core_get_max_pstate();
444	ret = ((value) & 255);	447	ret = ((value) & 255);
445	if (ret <= nont)	448	if (ret <= nont)
446	ret = nont;	449	ret = nont;
447	return ret;	450	return ret;
448	}	451	}
449		452
450	static void core_set_pstate(struct cpudata *cpudata, int pstate)	453	static void core_set_pstate(struct cpudata *cpudata, int pstate)
451	{	454	{
452	u64 val;	455	u64 val;
453		456
454	val = pstate << 8;	457	val = pstate << 8;
455	if (limits.no_turbo)	458	if (limits.no_turbo)
456	val \|= (u64)1 << 32;	459	val \|= (u64)1 << 32;
457		460
458	wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);	461	wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
459	}	462	}
460		463
461	static struct cpu_defaults core_params = {	464	static struct cpu_defaults core_params = {
462	.pid_policy = {	465	.pid_policy = {
463	.sample_rate_ms = 10,	466	.sample_rate_ms = 10,
464	.deadband = 0,	467	.deadband = 0,
465	.setpoint = 97,	468	.setpoint = 97,
466	.p_gain_pct = 20,	469	.p_gain_pct = 20,
467	.d_gain_pct = 0,	470	.d_gain_pct = 0,
468	.i_gain_pct = 0,	471	.i_gain_pct = 0,
469	},	472	},
470	.funcs = {	473	.funcs = {
471	.get_max = core_get_max_pstate,	474	.get_max = core_get_max_pstate,
472	.get_min = core_get_min_pstate,	475	.get_min = core_get_min_pstate,
473	.get_turbo = core_get_turbo_pstate,	476	.get_turbo = core_get_turbo_pstate,
474	.set = core_set_pstate,	477	.set = core_set_pstate,
475	},	478	},
476	};	479	};
477		480
478	static struct cpu_defaults byt_params = {	481	static struct cpu_defaults byt_params = {
479	.pid_policy = {	482	.pid_policy = {
480	.sample_rate_ms = 10,	483	.sample_rate_ms = 10,
481	.deadband = 0,	484	.deadband = 0,
482	.setpoint = 97,	485	.setpoint = 97,
483	.p_gain_pct = 14,	486	.p_gain_pct = 14,
484	.d_gain_pct = 0,	487	.d_gain_pct = 0,
485	.i_gain_pct = 4,	488	.i_gain_pct = 4,
486	},	489	},
487	.funcs = {	490	.funcs = {
488	.get_max = byt_get_max_pstate,	491	.get_max = byt_get_max_pstate,
489	.get_min = byt_get_min_pstate,	492	.get_min = byt_get_min_pstate,
490	.get_turbo = byt_get_turbo_pstate,	493	.get_turbo = byt_get_turbo_pstate,
491	.set = byt_set_pstate,	494	.set = byt_set_pstate,
492	.get_vid = byt_get_vid,	495	.get_vid = byt_get_vid,
493	},	496	},
494	};	497	};
495		498
496		499
497	static void intel_pstate_get_min_max(struct cpudata cpu, int min, int *max)	500	static void intel_pstate_get_min_max(struct cpudata cpu, int min, int *max)
498	{	501	{
499	int max_perf = cpu->pstate.turbo_pstate;	502	int max_perf = cpu->pstate.turbo_pstate;
500	int max_perf_adj;	503	int max_perf_adj;
501	int min_perf;	504	int min_perf;
502	if (limits.no_turbo)	505	if (limits.no_turbo)
503	max_perf = cpu->pstate.max_pstate;	506	max_perf = cpu->pstate.max_pstate;
504		507
505	max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));	508	max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
506	*max = clamp_t(int, max_perf_adj,	509	*max = clamp_t(int, max_perf_adj,
507	cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);	510	cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
508		511
509	min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));	512	min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
510	*min = clamp_t(int, min_perf,	513	*min = clamp_t(int, min_perf,
511	cpu->pstate.min_pstate, max_perf);	514	cpu->pstate.min_pstate, max_perf);
512	}	515	}
513		516
514	static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)	517	static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
515	{	518	{
516	int max_perf, min_perf;	519	int max_perf, min_perf;
517		520
518	intel_pstate_get_min_max(cpu, &min_perf, &max_perf);	521	intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
519		522
520	pstate = clamp_t(int, pstate, min_perf, max_perf);	523	pstate = clamp_t(int, pstate, min_perf, max_perf);
521		524
522	if (pstate == cpu->pstate.current_pstate)	525	if (pstate == cpu->pstate.current_pstate)
523	return;	526	return;
524		527
525	trace_cpu_frequency(pstate * 100000, cpu->cpu);	528	trace_cpu_frequency(pstate * 100000, cpu->cpu);
526		529
527	cpu->pstate.current_pstate = pstate;	530	cpu->pstate.current_pstate = pstate;
528		531
529	pstate_funcs.set(cpu, pstate);	532	pstate_funcs.set(cpu, pstate);
530	}	533	}
531		534
532	static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)	535	static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
533	{	536	{
534	int target;	537	int target;
535	target = cpu->pstate.current_pstate + steps;	538	target = cpu->pstate.current_pstate + steps;
536		539
537	intel_pstate_set_pstate(cpu, target);	540	intel_pstate_set_pstate(cpu, target);
538	}	541	}
539		542
540	static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)	543	static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)
541	{	544	{
542	int target;	545	int target;
543	target = cpu->pstate.current_pstate - steps;	546	target = cpu->pstate.current_pstate - steps;
544	intel_pstate_set_pstate(cpu, target);	547	intel_pstate_set_pstate(cpu, target);
545	}	548	}
546		549
547	static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)	550	static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
548	{	551	{
549	sprintf(cpu->name, "Intel 2nd generation core");	552	sprintf(cpu->name, "Intel 2nd generation core");
550		553
551	cpu->pstate.min_pstate = pstate_funcs.get_min();	554	cpu->pstate.min_pstate = pstate_funcs.get_min();
552	cpu->pstate.max_pstate = pstate_funcs.get_max();	555	cpu->pstate.max_pstate = pstate_funcs.get_max();
553	cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();	556	cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
554		557
555	if (pstate_funcs.get_vid)	558	if (pstate_funcs.get_vid)
556	pstate_funcs.get_vid(cpu);	559	pstate_funcs.get_vid(cpu);
557	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);	560	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
558	}	561	}
559		562
560	static inline void intel_pstate_calc_busy(struct cpudata *cpu,	563	static inline void intel_pstate_calc_busy(struct cpudata *cpu,
561	struct sample *sample)	564	struct sample *sample)
562	{	565	{
563	int32_t core_pct;	566	int64_t core_pct;
564	int32_t c0_pct;	567	int32_t rem;
565		568
566	core_pct = div_fp(int_tofp((sample->aperf)),	569	core_pct = int_tofp(sample->aperf) * int_tofp(100);
567	int_tofp((sample->mperf)));	570	core_pct = div_u64_rem(core_pct, int_tofp(sample->mperf), &rem);
568	core_pct = mul_fp(core_pct, int_tofp(100));
569	FP_ROUNDUP(core_pct);
570		571
571	c0_pct = div_fp(int_tofp(sample->mperf), int_tofp(sample->tsc));	572	if ((rem << 1) >= int_tofp(sample->mperf))
		573	core_pct += 1;
572		574
573	sample->freq = fp_toint(	575	sample->freq = fp_toint(
574	mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));	576	mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
575		577
576	sample->core_pct_busy = mul_fp(core_pct, c0_pct);	578	sample->core_pct_busy = (int32_t)core_pct;
577	}	579	}
578		580
579	static inline void intel_pstate_sample(struct cpudata *cpu)	581	static inline void intel_pstate_sample(struct cpudata *cpu)
580	{	582	{
581	u64 aperf, mperf;	583	u64 aperf, mperf;
582	unsigned long long tsc;
583		584
584	rdmsrl(MSR_IA32_APERF, aperf);	585	rdmsrl(MSR_IA32_APERF, aperf);
585	rdmsrl(MSR_IA32_MPERF, mperf);	586	rdmsrl(MSR_IA32_MPERF, mperf);
586	tsc = native_read_tsc();
587		587
588	aperf = aperf >> FRAC_BITS;	588	aperf = aperf >> FRAC_BITS;
589	mperf = mperf >> FRAC_BITS;	589	mperf = mperf >> FRAC_BITS;
590	tsc = tsc >> FRAC_BITS;
591		590
		591	cpu->last_sample_time = cpu->sample.time;
		592	cpu->sample.time = ktime_get();
592	cpu->sample.aperf = aperf;	593	cpu->sample.aperf = aperf;
593	cpu->sample.mperf = mperf;	594	cpu->sample.mperf = mperf;
594	cpu->sample.tsc = tsc;
595	cpu->sample.aperf -= cpu->prev_aperf;	595	cpu->sample.aperf -= cpu->prev_aperf;
596	cpu->sample.mperf -= cpu->prev_mperf;	596	cpu->sample.mperf -= cpu->prev_mperf;
597	cpu->sample.tsc -= cpu->prev_tsc;
598		597
599	intel_pstate_calc_busy(cpu, &cpu->sample);	598	intel_pstate_calc_busy(cpu, &cpu->sample);
600		599
601	cpu->prev_aperf = aperf;	600	cpu->prev_aperf = aperf;
602	cpu->prev_mperf = mperf;	601	cpu->prev_mperf = mperf;
603	cpu->prev_tsc = tsc;
604	}	602	}
605		603
606	static inline void intel_pstate_set_sample_time(struct cpudata *cpu)	604	static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
607	{	605	{
608	int sample_time, delay;	606	int sample_time, delay;
609		607
610	sample_time = pid_params.sample_rate_ms;	608	sample_time = pid_params.sample_rate_ms;
611	delay = msecs_to_jiffies(sample_time);	609	delay = msecs_to_jiffies(sample_time);
612	mod_timer_pinned(&cpu->timer, jiffies + delay);	610	mod_timer_pinned(&cpu->timer, jiffies + delay);
613	}	611	}
614		612
615	static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)	613	static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
616	{	614	{
617	int32_t core_busy, max_pstate, current_pstate;	615	int32_t core_busy, max_pstate, current_pstate, sample_ratio;
		616	u32 duration_us;
		617	u32 sample_time;
618		618
619	core_busy = cpu->sample.core_pct_busy;	619	core_busy = cpu->sample.core_pct_busy;
620	max_pstate = int_tofp(cpu->pstate.max_pstate);	620	max_pstate = int_tofp(cpu->pstate.max_pstate);
621	current_pstate = int_tofp(cpu->pstate.current_pstate);	621	current_pstate = int_tofp(cpu->pstate.current_pstate);
622	core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));	622	core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
623	return FP_ROUNDUP(core_busy);	623
		624	sample_time = (pid_params.sample_rate_ms * USEC_PER_MSEC);
		625	duration_us = (u32) ktime_us_delta(cpu->sample.time,
		626	cpu->last_sample_time);
		627	if (duration_us > sample_time * 3) {
		628	sample_ratio = div_fp(int_tofp(sample_time),
		629	int_tofp(duration_us));
		630	core_busy = mul_fp(core_busy, sample_ratio);
		631	}
		632
		633	return core_busy;
624	}	634	}
625		635
626	static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)	636	static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
627	{	637	{
628	int32_t busy_scaled;	638	int32_t busy_scaled;
629	struct _pid *pid;	639	struct _pid *pid;
630	signed int ctl = 0;	640	signed int ctl = 0;
631	int steps;	641	int steps;
632		642
633	pid = &cpu->pid;	643	pid = &cpu->pid;
634	busy_scaled = intel_pstate_get_scaled_busy(cpu);	644	busy_scaled = intel_pstate_get_scaled_busy(cpu);
635		645
636	ctl = pid_calc(pid, busy_scaled);	646	ctl = pid_calc(pid, busy_scaled);
637		647
638	steps = abs(ctl);	648	steps = abs(ctl);
639		649
640	if (ctl < 0)	650	if (ctl < 0)
641	intel_pstate_pstate_increase(cpu, steps);	651	intel_pstate_pstate_increase(cpu, steps);
642	else	652	else
643	intel_pstate_pstate_decrease(cpu, steps);	653	intel_pstate_pstate_decrease(cpu, steps);
644	}	654	}
645		655
646	static void intel_pstate_timer_func(unsigned long __data)	656	static void intel_pstate_timer_func(unsigned long __data)
647	{	657	{
648	struct cpudata cpu = (struct cpudata ) __data;	658	struct cpudata cpu = (struct cpudata ) __data;
649	struct sample *sample;	659	struct sample *sample;
650		660
651	intel_pstate_sample(cpu);	661	intel_pstate_sample(cpu);
652		662
653	sample = &cpu->sample;	663	sample = &cpu->sample;
654		664
655	intel_pstate_adjust_busy_pstate(cpu);	665	intel_pstate_adjust_busy_pstate(cpu);
656		666
657	trace_pstate_sample(fp_toint(sample->core_pct_busy),	667	trace_pstate_sample(fp_toint(sample->core_pct_busy),
658	fp_toint(intel_pstate_get_scaled_busy(cpu)),	668	fp_toint(intel_pstate_get_scaled_busy(cpu)),
659	cpu->pstate.current_pstate,	669	cpu->pstate.current_pstate,
660	sample->mperf,	670	sample->mperf,
661	sample->aperf,	671	sample->aperf,
662	sample->freq);	672	sample->freq);
663		673
664	intel_pstate_set_sample_time(cpu);	674	intel_pstate_set_sample_time(cpu);
665	}	675	}
666		676
667	#define ICPU(model, policy) \	677	#define ICPU(model, policy) \
668	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\	678	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
669	(unsigned long)&policy }	679	(unsigned long)&policy }
670		680
671	static const struct x86_cpu_id intel_pstate_cpu_ids[] = {	681	static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
672	ICPU(0x2a, core_params),	682	ICPU(0x2a, core_params),
673	ICPU(0x2d, core_params),	683	ICPU(0x2d, core_params),
674	ICPU(0x37, byt_params),	684	ICPU(0x37, byt_params),
675	ICPU(0x3a, core_params),	685	ICPU(0x3a, core_params),
676	ICPU(0x3c, core_params),	686	ICPU(0x3c, core_params),
677	ICPU(0x3e, core_params),	687	ICPU(0x3e, core_params),
678	ICPU(0x3f, core_params),	688	ICPU(0x3f, core_params),
679	ICPU(0x45, core_params),	689	ICPU(0x45, core_params),
680	ICPU(0x46, core_params),	690	ICPU(0x46, core_params),
681	{}	691	{}
682	};	692	};
683	MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);	693	MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
684		694
685	static int intel_pstate_init_cpu(unsigned int cpunum)	695	static int intel_pstate_init_cpu(unsigned int cpunum)
686	{	696	{
687		697
688	const struct x86_cpu_id *id;	698	const struct x86_cpu_id *id;
689	struct cpudata *cpu;	699	struct cpudata *cpu;
690		700
691	id = x86_match_cpu(intel_pstate_cpu_ids);	701	id = x86_match_cpu(intel_pstate_cpu_ids);
692	if (!id)	702	if (!id)
693	return -ENODEV;	703	return -ENODEV;
694		704
695	all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);	705	all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
696	if (!all_cpu_data[cpunum])	706	if (!all_cpu_data[cpunum])
697	return -ENOMEM;	707	return -ENOMEM;
698		708
699	cpu = all_cpu_data[cpunum];	709	cpu = all_cpu_data[cpunum];
700		710
701	intel_pstate_get_cpu_pstates(cpu);	711	intel_pstate_get_cpu_pstates(cpu);
702		712
703	cpu->cpu = cpunum;	713	cpu->cpu = cpunum;
704		714
705	init_timer_deferrable(&cpu->timer);	715	init_timer_deferrable(&cpu->timer);
706	cpu->timer.function = intel_pstate_timer_func;	716	cpu->timer.function = intel_pstate_timer_func;
707	cpu->timer.data =	717	cpu->timer.data =
708	(unsigned long)cpu;	718	(unsigned long)cpu;
709	cpu->timer.expires = jiffies + HZ/100;	719	cpu->timer.expires = jiffies + HZ/100;
710	intel_pstate_busy_pid_reset(cpu);	720	intel_pstate_busy_pid_reset(cpu);
711	intel_pstate_sample(cpu);	721	intel_pstate_sample(cpu);
712		722
713	add_timer_on(&cpu->timer, cpunum);	723	add_timer_on(&cpu->timer, cpunum);
714		724
715	pr_info("Intel pstate controlling: cpu %d\n", cpunum);	725	pr_info("Intel pstate controlling: cpu %d\n", cpunum);
716		726
717	return 0;	727	return 0;
718	}	728	}
719		729
720	static unsigned int intel_pstate_get(unsigned int cpu_num)	730	static unsigned int intel_pstate_get(unsigned int cpu_num)
721	{	731	{
722	struct sample *sample;	732	struct sample *sample;
723	struct cpudata *cpu;	733	struct cpudata *cpu;
724		734
725	cpu = all_cpu_data[cpu_num];	735	cpu = all_cpu_data[cpu_num];
726	if (!cpu)	736	if (!cpu)
727	return 0;	737	return 0;
728	sample = &cpu->sample;	738	sample = &cpu->sample;
729	return sample->freq;	739	return sample->freq;
730	}	740	}
731		741
732	static int intel_pstate_set_policy(struct cpufreq_policy *policy)	742	static int intel_pstate_set_policy(struct cpufreq_policy *policy)
733	{	743	{
734	struct cpudata *cpu;	744	struct cpudata *cpu;
735		745
736	cpu = all_cpu_data[policy->cpu];	746	cpu = all_cpu_data[policy->cpu];
737		747
738	if (!policy->cpuinfo.max_freq)	748	if (!policy->cpuinfo.max_freq)
739	return -ENODEV;	749	return -ENODEV;
740		750
741	if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {	751	if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
742	limits.min_perf_pct = 100;	752	limits.min_perf_pct = 100;
743	limits.min_perf = int_tofp(1);	753	limits.min_perf = int_tofp(1);
744	limits.max_perf_pct = 100;	754	limits.max_perf_pct = 100;
745	limits.max_perf = int_tofp(1);	755	limits.max_perf = int_tofp(1);
746	limits.no_turbo = 0;	756	limits.no_turbo = 0;
747	return 0;	757	return 0;
748	}	758	}
749	limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;	759	limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
750	limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);	760	limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
751	limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));	761	limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
752		762
753	limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;	763	limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;
754	limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);	764	limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
755	limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);	765	limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
756	limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));	766	limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
757		767
758	return 0;	768	return 0;
759	}	769	}
760		770
761	static int intel_pstate_verify_policy(struct cpufreq_policy *policy)	771	static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
762	{	772	{
763	cpufreq_verify_within_cpu_limits(policy);	773	cpufreq_verify_within_cpu_limits(policy);
764		774
765	if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&	775	if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
766	(policy->policy != CPUFREQ_POLICY_PERFORMANCE))	776	(policy->policy != CPUFREQ_POLICY_PERFORMANCE))
767	return -EINVAL;	777	return -EINVAL;
768		778
769	return 0;	779	return 0;
770	}	780	}
771		781
772	static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)	782	static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
773	{	783	{
774	int cpu_num = policy->cpu;	784	int cpu_num = policy->cpu;
775	struct cpudata *cpu = all_cpu_data[cpu_num];	785	struct cpudata *cpu = all_cpu_data[cpu_num];
776		786
777	pr_info("intel_pstate CPU %d exiting\n", cpu_num);	787	pr_info("intel_pstate CPU %d exiting\n", cpu_num);
778		788
779	del_timer_sync(&all_cpu_data[cpu_num]->timer);	789	del_timer_sync(&all_cpu_data[cpu_num]->timer);
780	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);	790	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
781	kfree(all_cpu_data[cpu_num]);	791	kfree(all_cpu_data[cpu_num]);
782	all_cpu_data[cpu_num] = NULL;	792	all_cpu_data[cpu_num] = NULL;
783	}	793	}
784		794
785	static int intel_pstate_cpu_init(struct cpufreq_policy *policy)	795	static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
786	{	796	{
787	struct cpudata *cpu;	797	struct cpudata *cpu;
788	int rc;	798	int rc;
789		799
790	rc = intel_pstate_init_cpu(policy->cpu);	800	rc = intel_pstate_init_cpu(policy->cpu);
791	if (rc)	801	if (rc)
792	return rc;	802	return rc;
793		803
794	cpu = all_cpu_data[policy->cpu];	804	cpu = all_cpu_data[policy->cpu];
795		805
796	if (!limits.no_turbo &&	806	if (!limits.no_turbo &&
797	limits.min_perf_pct == 100 && limits.max_perf_pct == 100)	807	limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
798	policy->policy = CPUFREQ_POLICY_PERFORMANCE;	808	policy->policy = CPUFREQ_POLICY_PERFORMANCE;
799	else	809	else
800	policy->policy = CPUFREQ_POLICY_POWERSAVE;	810	policy->policy = CPUFREQ_POLICY_POWERSAVE;
801		811
802	policy->min = cpu->pstate.min_pstate * 100000;	812	policy->min = cpu->pstate.min_pstate * 100000;
803	policy->max = cpu->pstate.turbo_pstate * 100000;	813	policy->max = cpu->pstate.turbo_pstate * 100000;
804		814
805	/* cpuinfo and default policy values */	815	/* cpuinfo and default policy values */
806	policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;	816	policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
807	policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;	817	policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
808	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;	818	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
809	cpumask_set_cpu(policy->cpu, policy->cpus);	819	cpumask_set_cpu(policy->cpu, policy->cpus);
810		820
811	return 0;	821	return 0;
812	}	822	}
813		823
814	static struct cpufreq_driver intel_pstate_driver = {	824	static struct cpufreq_driver intel_pstate_driver = {
815	.flags = CPUFREQ_CONST_LOOPS,	825	.flags = CPUFREQ_CONST_LOOPS,
816	.verify = intel_pstate_verify_policy,	826	.verify = intel_pstate_verify_policy,
817	.setpolicy = intel_pstate_set_policy,	827	.setpolicy = intel_pstate_set_policy,
818	.get = intel_pstate_get,	828	.get = intel_pstate_get,
819	.init = intel_pstate_cpu_init,	829	.init = intel_pstate_cpu_init,
820	.stop_cpu = intel_pstate_stop_cpu,	830	.stop_cpu = intel_pstate_stop_cpu,
821	.name = "intel_pstate",	831	.name = "intel_pstate",
822	};	832	};
823		833
824	static int __initdata no_load;	834	static int __initdata no_load;
825		835
826	static int intel_pstate_msrs_not_valid(void)	836	static int intel_pstate_msrs_not_valid(void)
827	{	837	{
828	/* Check that all the msr's we are using are valid. */	838	/* Check that all the msr's we are using are valid. */
829	u64 aperf, mperf, tmp;	839	u64 aperf, mperf, tmp;
830		840
831	rdmsrl(MSR_IA32_APERF, aperf);	841	rdmsrl(MSR_IA32_APERF, aperf);
832	rdmsrl(MSR_IA32_MPERF, mperf);	842	rdmsrl(MSR_IA32_MPERF, mperf);
833		843
834	if (!pstate_funcs.get_max() \|\|	844	if (!pstate_funcs.get_max() \|\|
835	!pstate_funcs.get_min() \|\|	845	!pstate_funcs.get_min() \|\|
836	!pstate_funcs.get_turbo())	846	!pstate_funcs.get_turbo())
837	return -ENODEV;	847	return -ENODEV;
838		848
839	rdmsrl(MSR_IA32_APERF, tmp);	849	rdmsrl(MSR_IA32_APERF, tmp);
840	if (!(tmp - aperf))	850	if (!(tmp - aperf))
841	return -ENODEV;	851	return -ENODEV;
842		852
843	rdmsrl(MSR_IA32_MPERF, tmp);	853	rdmsrl(MSR_IA32_MPERF, tmp);
844	if (!(tmp - mperf))	854	if (!(tmp - mperf))
845	return -ENODEV;	855	return -ENODEV;
846		856
847	return 0;	857	return 0;
848	}	858	}
849		859
850	static void copy_pid_params(struct pstate_adjust_policy *policy)	860	static void copy_pid_params(struct pstate_adjust_policy *policy)
851	{	861	{
852	pid_params.sample_rate_ms = policy->sample_rate_ms;	862	pid_params.sample_rate_ms = policy->sample_rate_ms;
853	pid_params.p_gain_pct = policy->p_gain_pct;	863	pid_params.p_gain_pct = policy->p_gain_pct;
854	pid_params.i_gain_pct = policy->i_gain_pct;	864	pid_params.i_gain_pct = policy->i_gain_pct;
855	pid_params.d_gain_pct = policy->d_gain_pct;	865	pid_params.d_gain_pct = policy->d_gain_pct;
856	pid_params.deadband = policy->deadband;	866	pid_params.deadband = policy->deadband;
857	pid_params.setpoint = policy->setpoint;	867	pid_params.setpoint = policy->setpoint;
858	}	868	}
859		869
860	static void copy_cpu_funcs(struct pstate_funcs *funcs)	870	static void copy_cpu_funcs(struct pstate_funcs *funcs)
861	{	871	{
862	pstate_funcs.get_max = funcs->get_max;	872	pstate_funcs.get_max = funcs->get_max;
863	pstate_funcs.get_min = funcs->get_min;	873	pstate_funcs.get_min = funcs->get_min;
864	pstate_funcs.get_turbo = funcs->get_turbo;	874	pstate_funcs.get_turbo = funcs->get_turbo;
865	pstate_funcs.set = funcs->set;	875	pstate_funcs.set = funcs->set;
866	pstate_funcs.get_vid = funcs->get_vid;	876	pstate_funcs.get_vid = funcs->get_vid;
867	}	877	}
868		878
869	#if IS_ENABLED(CONFIG_ACPI)	879	#if IS_ENABLED(CONFIG_ACPI)
870	#include <acpi/processor.h>	880	#include <acpi/processor.h>
871		881
872	static bool intel_pstate_no_acpi_pss(void)	882	static bool intel_pstate_no_acpi_pss(void)
873	{	883	{
874	int i;	884	int i;
875		885
876	for_each_possible_cpu(i) {	886	for_each_possible_cpu(i) {
877	acpi_status status;	887	acpi_status status;
878	union acpi_object *pss;	888	union acpi_object *pss;
879	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };	889	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
880	struct acpi_processor *pr = per_cpu(processors, i);	890	struct acpi_processor *pr = per_cpu(processors, i);
881		891
882	if (!pr)	892	if (!pr)
883	continue;	893	continue;
884		894
885	status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);	895	status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
886	if (ACPI_FAILURE(status))	896	if (ACPI_FAILURE(status))
887	continue;	897	continue;
888		898
889	pss = buffer.pointer;	899	pss = buffer.pointer;
890	if (pss && pss->type == ACPI_TYPE_PACKAGE) {	900	if (pss && pss->type == ACPI_TYPE_PACKAGE) {
891	kfree(pss);	901	kfree(pss);
892	return false;	902	return false;
893	}	903	}
894		904
895	kfree(pss);	905	kfree(pss);
896	}	906	}
897		907
898	return true;	908	return true;
899	}	909	}
900		910
901	struct hw_vendor_info {	911	struct hw_vendor_info {
902	u16 valid;	912	u16 valid;
903	char oem_id[ACPI_OEM_ID_SIZE];	913	char oem_id[ACPI_OEM_ID_SIZE];
904	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];	914	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
905	};	915	};
906		916
907	/* Hardware vendor-specific info that has its own power management modes */	917	/* Hardware vendor-specific info that has its own power management modes */
908	static struct hw_vendor_info vendor_info[] = {	918	static struct hw_vendor_info vendor_info[] = {
909	{1, "HP ", "ProLiant"},	919	{1, "HP ", "ProLiant"},
910	{0, "", ""},	920	{0, "", ""},
911	};	921	};
912		922
913	static bool intel_pstate_platform_pwr_mgmt_exists(void)	923	static bool intel_pstate_platform_pwr_mgmt_exists(void)
914	{	924	{
915	struct acpi_table_header hdr;	925	struct acpi_table_header hdr;
916	struct hw_vendor_info *v_info;	926	struct hw_vendor_info *v_info;
917		927
918	if (acpi_disabled	928	if (acpi_disabled
919	\|\| ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))	929	\|\| ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
920	return false;	930	return false;
921		931
922	for (v_info = vendor_info; v_info->valid; v_info++) {	932	for (v_info = vendor_info; v_info->valid; v_info++) {
923	if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)	933	if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)
924	&& !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)	934	&& !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)
925	&& intel_pstate_no_acpi_pss())	935	&& intel_pstate_no_acpi_pss())
926	return true;	936	return true;
927	}	937	}
928		938
929	return false;	939	return false;
930	}	940	}
931	#else /* CONFIG_ACPI not enabled */	941	#else /* CONFIG_ACPI not enabled */
932	static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }	942	static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
933	#endif /* CONFIG_ACPI */	943	#endif /* CONFIG_ACPI */
934		944
935	static int __init intel_pstate_init(void)	945	static int __init intel_pstate_init(void)
936	{	946	{
937	int cpu, rc = 0;	947	int cpu, rc = 0;
938	const struct x86_cpu_id *id;	948	const struct x86_cpu_id *id;
939	struct cpu_defaults *cpu_info;	949	struct cpu_defaults *cpu_info;
940		950
941	if (no_load)	951	if (no_load)
942	return -ENODEV;	952	return -ENODEV;
943		953
944	id = x86_match_cpu(intel_pstate_cpu_ids);	954	id = x86_match_cpu(intel_pstate_cpu_ids);
945	if (!id)	955	if (!id)
946	return -ENODEV;	956	return -ENODEV;
947		957
948	/*	958	/*
949	* The Intel pstate driver will be ignored if the platform	959	* The Intel pstate driver will be ignored if the platform
950	* firmware has its own power management modes.	960	* firmware has its own power management modes.
951	*/	961	*/
952	if (intel_pstate_platform_pwr_mgmt_exists())	962	if (intel_pstate_platform_pwr_mgmt_exists())
953	return -ENODEV;	963	return -ENODEV;
954		964
955	cpu_info = (struct cpu_defaults *)id->driver_data;	965	cpu_info = (struct cpu_defaults *)id->driver_data;
956		966
957	copy_pid_params(&cpu_info->pid_policy);	967	copy_pid_params(&cpu_info->pid_policy);
958	copy_cpu_funcs(&cpu_info->funcs);	968	copy_cpu_funcs(&cpu_info->funcs);
959		969
960	if (intel_pstate_msrs_not_valid())	970	if (intel_pstate_msrs_not_valid())
961	return -ENODEV;	971	return -ENODEV;
962		972
963	pr_info("Intel P-state driver initializing.\n");	973	pr_info("Intel P-state driver initializing.\n");
964		974
965	all_cpu_data = vzalloc(sizeof(void ) num_possible_cpus());	975	all_cpu_data = vzalloc(sizeof(void ) num_possible_cpus());
966	if (!all_cpu_data)	976	if (!all_cpu_data)
967	return -ENOMEM;	977	return -ENOMEM;
968		978
969	rc = cpufreq_register_driver(&intel_pstate_driver);	979	rc = cpufreq_register_driver(&intel_pstate_driver);
970	if (rc)	980	if (rc)
971	goto out;	981	goto out;
972		982
973	intel_pstate_debug_expose_params();	983	intel_pstate_debug_expose_params();
974	intel_pstate_sysfs_expose_params();	984	intel_pstate_sysfs_expose_params();
975		985
976	return rc;	986	return rc;
977	out:	987	out:
978	get_online_cpus();	988	get_online_cpus();
979	for_each_online_cpu(cpu) {	989	for_each_online_cpu(cpu) {
980	if (all_cpu_data[cpu]) {	990	if (all_cpu_data[cpu]) {
981	del_timer_sync(&all_cpu_data[cpu]->timer);	991	del_timer_sync(&all_cpu_data[cpu]->timer);
982	kfree(all_cpu_data[cpu]);	992	kfree(all_cpu_data[cpu]);
983	}	993	}
984	}	994	}
985		995
986	put_online_cpus();	996	put_online_cpus();
987	vfree(all_cpu_data);	997	vfree(all_cpu_data);
988	return -ENODEV;	998	return -ENODEV;
989	}	999	}
990	device_initcall(intel_pstate_init);	1000	device_initcall(intel_pstate_init);
991		1001
992	static int __init intel_pstate_setup(char *str)	1002	static int __init intel_pstate_setup(char *str)
993	{	1003	{
994	if (!str)	1004	if (!str)
995	return -EINVAL;	1005	return -EINVAL;

drivers/gpu/drm/drm_crtc_helper.c

Diff comments View file @ 6548be5

 /*
  * Copyright (c) 2006-2008 Intel Corporation
  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
  *
  * DRM core CRTC related functions
  *
  * Permission to use, copy, modify, distribute, and sell this software and its
  * documentation for any purpose is hereby granted without fee, provided that
  * the above copyright notice appear in all copies and that both that copyright
  * notice and this permission notice appear in supporting documentation, and
  * that the name of the copyright holders not be used in advertising or
  * publicity pertaining to distribution of the software without specific,
  * written prior permission.  The copyright holders make no representations
  * about the suitability of this software for any purpose.  It is provided "as
  * is" without express or implied warranty.
  *
  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  * OF THIS SOFTWARE.
  *
  * Authors:
  *      Keith Packard
  *	Eric Anholt <eric@anholt.net>
  *      Dave Airlie <airlied@linux.ie>
  *      Jesse Barnes <jesse.barnes@intel.com>
  */
+#include <linux/kernel.h>
 #include <linux/export.h>
 #include <linux/moduleparam.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_edid.h>
 MODULE_AUTHOR("David Airlie, Jesse Barnes");
 MODULE_DESCRIPTION("DRM KMS helper");
 MODULE_LICENSE("GPL and additional rights");
 /**
  * drm_helper_move_panel_connectors_to_head() - move panels to the front in the
  * 						connector list
  * @dev: drm device to operate on
  *
  * Some userspace presumes that the first connected connector is the main
  * display, where it's supposed to display e.g. the login screen. For
  * laptops, this should be the main panel. Use this function to sort all
  * (eDP/LVDS) panels to the front of the connector list, instead of
  * painstakingly trying to initialize them in the right order.
  */
 void drm_helper_move_panel_connectors_to_head(struct drm_device *dev)
 {
 	struct drm_connector *connector, *tmp;
 	struct list_head panel_list;
 	INIT_LIST_HEAD(&panel_list);
 	list_for_each_entry_safe(connector, tmp,
 				 &dev->mode_config.connector_list, head) {
 		if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS ||
 		    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
 			list_move_tail(&connector->head, &panel_list);
 	}
 	list_splice(&panel_list, &dev->mode_config.connector_list);
 }
 EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head);
 /**
  * drm_helper_encoder_in_use - check if a given encoder is in use
  * @encoder: encoder to check
  *
  * Checks whether @encoder is with the current mode setting output configuration
  * in use by any connector. This doesn't mean that it is actually enabled since
  * the DPMS state is tracked separately.
  *
  * Returns:
  * True if @encoder is used, false otherwise.
  */
 bool drm_helper_encoder_in_use(struct drm_encoder *encoder)
 {
 	struct drm_connector *connector;
 	struct drm_device *dev = encoder->dev;
-	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
+	/*
+	 * We can expect this mutex to be locked if we are not panicking.
+	 * Locking is currently fubar in the panic handler.
+	 */
+	if (!oops_in_progress)
+		WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 		if (connector->encoder == encoder)
 			return true;
 	return false;
 }
 EXPORT_SYMBOL(drm_helper_encoder_in_use);
 /**
  * drm_helper_crtc_in_use - check if a given CRTC is in a mode_config
  * @crtc: CRTC to check
  *
  * Checks whether @crtc is with the current mode setting output configuration
  * in use by any connector. This doesn't mean that it is actually enabled since
  * the DPMS state is tracked separately.
  *
  * Returns:
  * True if @crtc is used, false otherwise.
  */
 bool drm_helper_crtc_in_use(struct drm_crtc *crtc)
 {
 	struct drm_encoder *encoder;
 	struct drm_device *dev = crtc->dev;
-	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
+	/*
+	 * We can expect this mutex to be locked if we are not panicking.
+	 * Locking is currently fubar in the panic handler.
+	 */
+	if (!oops_in_progress)
+		WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
 		if (encoder->crtc == crtc && drm_helper_encoder_in_use(encoder))
 			return true;
 	return false;
 }
 EXPORT_SYMBOL(drm_helper_crtc_in_use);
 static void
 drm_encoder_disable(struct drm_encoder *encoder)
 {
 	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 	if (encoder->bridge)
 		encoder->bridge->funcs->disable(encoder->bridge);
 	if (encoder_funcs->disable)
 		(*encoder_funcs->disable)(encoder);
 	else
 		(*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
 	if (encoder->bridge)
 		encoder->bridge->funcs->post_disable(encoder->bridge);
 }
 static void __drm_helper_disable_unused_functions(struct drm_device *dev)
 {
 	struct drm_encoder *encoder;
 	struct drm_connector *connector;
 	struct drm_crtc *crtc;
 	drm_warn_on_modeset_not_all_locked(dev);
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		if (!connector->encoder)
 			continue;
 	}
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (!drm_helper_encoder_in_use(encoder)) {
 			drm_encoder_disable(encoder);
 			/* disconnector encoder from any connector */
 			encoder->crtc = NULL;
 		}
 	}
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 		crtc->enabled = drm_helper_crtc_in_use(crtc);
 		if (!crtc->enabled) {
 			if (crtc_funcs->disable)
 				(*crtc_funcs->disable)(crtc);
 			else
 				(*crtc_funcs->dpms)(crtc, DRM_MODE_DPMS_OFF);
 			crtc->primary->fb = NULL;
 		}
 	}
 }
 /**
  * drm_helper_disable_unused_functions - disable unused objects
  * @dev: DRM device
  *
  * This function walks through the entire mode setting configuration of @dev. It
  * will remove any crtc links of unused encoders and encoder links of
  * disconnected connectors. Then it will disable all unused encoders and crtcs
  * either by calling their disable callback if available or by calling their
  * dpms callback with DRM_MODE_DPMS_OFF.
  */
 void drm_helper_disable_unused_functions(struct drm_device *dev)
 {
 	drm_modeset_lock_all(dev);
 	__drm_helper_disable_unused_functions(dev);
 	drm_modeset_unlock_all(dev);
 }
 EXPORT_SYMBOL(drm_helper_disable_unused_functions);
 /*
  * Check the CRTC we're going to map each output to vs. its current
  * CRTC.  If they don't match, we have to disable the output and the CRTC
  * since the driver will have to re-route things.
  */
 static void
 drm_crtc_prepare_encoders(struct drm_device *dev)
 {
 	struct drm_encoder_helper_funcs *encoder_funcs;
 	struct drm_encoder *encoder;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		encoder_funcs = encoder->helper_private;
 		/* Disable unused encoders */
 		if (encoder->crtc == NULL)
 			drm_encoder_disable(encoder);
 		/* Disable encoders whose CRTC is about to change */
 		if (encoder_funcs->get_crtc &&
 		    encoder->crtc != (*encoder_funcs->get_crtc)(encoder))
 			drm_encoder_disable(encoder);
 	}
 }
 /**
  * drm_crtc_helper_set_mode - internal helper to set a mode
  * @crtc: CRTC to program
  * @mode: mode to use
  * @x: horizontal offset into the surface
  * @y: vertical offset into the surface
  * @old_fb: old framebuffer, for cleanup
  *
  * Try to set @mode on @crtc.  Give @crtc and its associated connectors a chance
  * to fixup or reject the mode prior to trying to set it. This is an internal
  * helper that drivers could e.g. use to update properties that require the
  * entire output pipe to be disabled and re-enabled in a new configuration. For
  * example for changing whether audio is enabled on a hdmi link or for changing
  * panel fitter or dither attributes. It is also called by the
  * drm_crtc_helper_set_config() helper function to drive the mode setting
  * sequence.
  *
  * Returns:
  * True if the mode was set successfully, false otherwise.
  */
 bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
 			      struct drm_display_mode *mode,
 			      int x, int y,
 			      struct drm_framebuffer *old_fb)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_display_mode *adjusted_mode, saved_mode;
 	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 	struct drm_encoder_helper_funcs *encoder_funcs;
 	int saved_x, saved_y;
 	bool saved_enabled;
 	struct drm_encoder *encoder;
 	bool ret = true;
 	drm_warn_on_modeset_not_all_locked(dev);
 	saved_enabled = crtc->enabled;
 	crtc->enabled = drm_helper_crtc_in_use(crtc);
 	if (!crtc->enabled)
 		return true;
 	adjusted_mode = drm_mode_duplicate(dev, mode);
 	if (!adjusted_mode) {
 		crtc->enabled = saved_enabled;
 		return false;
 	}
 	saved_mode = crtc->mode;
 	saved_x = crtc->x;
 	saved_y = crtc->y;
 	/* Update crtc values up front so the driver can rely on them for mode
 	 * setting.
 	 */
 	crtc->mode = *mode;
 	crtc->x = x;
 	crtc->y = y;
 	/* Pass our mode to the connectors and the CRTC to give them a chance to
 	 * adjust it according to limitations or connector properties, and also
 	 * a chance to reject the mode entirely.
 	 */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		if (encoder->bridge && encoder->bridge->funcs->mode_fixup) {
 			ret = encoder->bridge->funcs->mode_fixup(
 					encoder->bridge, mode, adjusted_mode);
 			if (!ret) {
 				DRM_DEBUG_KMS("Bridge fixup failed\n");
 				goto done;
 			}
 		}
 		encoder_funcs = encoder->helper_private;
 		if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
 						      adjusted_mode))) {
 			DRM_DEBUG_KMS("Encoder fixup failed\n");
 			goto done;
 		}
 	}
 	if (!(ret = crtc_funcs->mode_fixup(crtc, mode, adjusted_mode))) {
 		DRM_DEBUG_KMS("CRTC fixup failed\n");
 		goto done;
 	}
 	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
 	/* Prepare the encoders and CRTCs before setting the mode. */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		if (encoder->bridge)
 			encoder->bridge->funcs->disable(encoder->bridge);
 		encoder_funcs = encoder->helper_private;
 		/* Disable the encoders as the first thing we do. */
 		encoder_funcs->prepare(encoder);
 		if (encoder->bridge)
 			encoder->bridge->funcs->post_disable(encoder->bridge);
 	}
 	drm_crtc_prepare_encoders(dev);
 	crtc_funcs->prepare(crtc);
 	/* Set up the DPLL and any encoders state that needs to adjust or depend
 	 * on the DPLL.
 	 */
 	ret = !crtc_funcs->mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
 	if (!ret)
 	    goto done;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
 			encoder->base.id, drm_get_encoder_name(encoder),
 			mode->base.id, mode->name);
 		encoder_funcs = encoder->helper_private;
 		encoder_funcs->mode_set(encoder, mode, adjusted_mode);
 		if (encoder->bridge && encoder->bridge->funcs->mode_set)
 			encoder->bridge->funcs->mode_set(encoder->bridge, mode,
 					adjusted_mode);
 	}
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	crtc_funcs->commit(crtc);
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		if (encoder->bridge)
 			encoder->bridge->funcs->pre_enable(encoder->bridge);
 		encoder_funcs = encoder->helper_private;
 		encoder_funcs->commit(encoder);
 		if (encoder->bridge)
 			encoder->bridge->funcs->enable(encoder->bridge);
 	}
 	/* Store real post-adjustment hardware mode. */
 	crtc->hwmode = *adjusted_mode;
 	/* Calculate and store various constants which
 	 * are later needed by vblank and swap-completion
 	 * timestamping. They are derived from true hwmode.
 	 */
 	drm_calc_timestamping_constants(crtc, &crtc->hwmode);
 	/* FIXME: add subpixel order */
 done:
 	drm_mode_destroy(dev, adjusted_mode);
 	if (!ret) {
 		crtc->enabled = saved_enabled;
 		crtc->mode = saved_mode;
 		crtc->x = saved_x;
 		crtc->y = saved_y;
 	}
 	return ret;
 }
 EXPORT_SYMBOL(drm_crtc_helper_set_mode);
 static int
 drm_crtc_helper_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_connector *connector;
 	struct drm_encoder *encoder;
 	/* Decouple all encoders and their attached connectors from this crtc */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 			if (connector->encoder != encoder)
 				continue;
 			connector->encoder = NULL;
 			/*
 			 * drm_helper_disable_unused_functions() ought to be
 			 * doing this, but since we've decoupled the encoder
 			 * from the connector above, the required connection
 			 * between them is henceforth no longer available.
 			 */
 			connector->dpms = DRM_MODE_DPMS_OFF;
 		}
 	}
 	__drm_helper_disable_unused_functions(dev);
 	return 0;
 }
 /**
  * drm_crtc_helper_set_config - set a new config from userspace
  * @set: mode set configuration
  *
  * Setup a new configuration, provided by the upper layers (either an ioctl call
  * from userspace or internally e.g. from the fbdev support code) in @set, and
  * enable it. This is the main helper functions for drivers that implement
  * kernel mode setting with the crtc helper functions and the assorted
  * ->prepare(), ->modeset() and ->commit() helper callbacks.
  *
  * Returns:
  * Returns 0 on success, negative errno numbers on failure.
  */
 int drm_crtc_helper_set_config(struct drm_mode_set *set)
 {
 	struct drm_device *dev;
 	struct drm_crtc *new_crtc;
 	struct drm_encoder *save_encoders, *new_encoder, *encoder;
 	bool mode_changed = false; /* if true do a full mode set */
 	bool fb_changed = false; /* if true and !mode_changed just do a flip */
 	struct drm_connector *save_connectors, *connector;
 	int count = 0, ro, fail = 0;
 	struct drm_crtc_helper_funcs *crtc_funcs;
 	struct drm_mode_set save_set;
 	int ret;
 	int i;
 	DRM_DEBUG_KMS("\n");
 	BUG_ON(!set);
 	BUG_ON(!set->crtc);
 	BUG_ON(!set->crtc->helper_private);
 	/* Enforce sane interface api - has been abused by the fb helper. */
 	BUG_ON(!set->mode && set->fb);
 	BUG_ON(set->fb && set->num_connectors == 0);
 	crtc_funcs = set->crtc->helper_private;
 	if (!set->mode)
 		set->fb = NULL;
 	if (set->fb) {
 		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
 				set->crtc->base.id, set->fb->base.id,
 				(int)set->num_connectors, set->x, set->y);
 	} else {
 		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
 		return drm_crtc_helper_disable(set->crtc);
 	}
 	dev = set->crtc->dev;
 	drm_warn_on_modeset_not_all_locked(dev);
 	/*
 	 * Allocate space for the backup of all (non-pointer) encoder and
 	 * connector data.
 	 */
 	save_encoders = kzalloc(dev->mode_config.num_encoder *
 				sizeof(struct drm_encoder), GFP_KERNEL);
 	if (!save_encoders)
 		return -ENOMEM;
 	save_connectors = kzalloc(dev->mode_config.num_connector *
 				sizeof(struct drm_connector), GFP_KERNEL);
 	if (!save_connectors) {
 		kfree(save_encoders);
 		return -ENOMEM;
 	}
 	/*
 	 * Copy data. Note that driver private data is not affected.
 	 * Should anything bad happen only the expected state is
 	 * restored, not the drivers personal bookkeeping.
 	 */
 	count = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		save_encoders[count++] = *encoder;
 	}
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		save_connectors[count++] = *connector;
 	}
 	save_set.crtc = set->crtc;
 	save_set.mode = &set->crtc->mode;
 	save_set.x = set->crtc->x;
 	save_set.y = set->crtc->y;
 	save_set.fb = set->crtc->primary->fb;
 	/* We should be able to check here if the fb has the same properties
 	 * and then just flip_or_move it */
 	if (set->crtc->primary->fb != set->fb) {
 		/* If we have no fb then treat it as a full mode set */
 		if (set->crtc->primary->fb == NULL) {
 			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
 			mode_changed = true;
 		} else if (set->fb == NULL) {
 			mode_changed = true;
 		} else if (set->fb->pixel_format !=
 			   set->crtc->primary->fb->pixel_format) {
 			mode_changed = true;
 		} else
 			fb_changed = true;
 	}
 	if (set->x != set->crtc->x || set->y != set->crtc->y)
 		fb_changed = true;
 	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
 		DRM_DEBUG_KMS("modes are different, full mode set\n");
 		drm_mode_debug_printmodeline(&set->crtc->mode);
 		drm_mode_debug_printmodeline(set->mode);
 		mode_changed = true;
 	}
 	/* a) traverse passed in connector list and get encoders for them */
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		struct drm_connector_helper_funcs *connector_funcs =
 			connector->helper_private;
 		new_encoder = connector->encoder;
 		for (ro = 0; ro < set->num_connectors; ro++) {
 			if (set->connectors[ro] == connector) {
 				new_encoder = connector_funcs->best_encoder(connector);
 				/* if we can't get an encoder for a connector
 				   we are setting now - then fail */
 				if (new_encoder == NULL)
 					/* don't break so fail path works correct */
 					fail = 1;
 				if (connector->dpms != DRM_MODE_DPMS_ON) {
 					DRM_DEBUG_KMS("connector dpms not on, full mode switch\n");
 					mode_changed = true;
 				}
 				break;
 			}
 		}
 		if (new_encoder != connector->encoder) {
 			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
 			mode_changed = true;
 			/* If the encoder is reused for another connector, then
 			 * the appropriate crtc will be set later.
 			 */
 			if (connector->encoder)
 				connector->encoder->crtc = NULL;
 			connector->encoder = new_encoder;
 		}
 	}
 	if (fail) {
 		ret = -EINVAL;
 		goto fail;
 	}
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		if (!connector->encoder)
 			continue;
 		if (connector->encoder->crtc == set->crtc)
 			new_crtc = NULL;
 		else
 			new_crtc = connector->encoder->crtc;
 		for (ro = 0; ro < set->num_connectors; ro++) {
 			if (set->connectors[ro] == connector)
 				new_crtc = set->crtc;
 		}
 		/* Make sure the new CRTC will work with the encoder */
 		if (new_crtc &&
 		    !drm_encoder_crtc_ok(connector->encoder, new_crtc)) {
 			ret = -EINVAL;
 			goto fail;
 		}
 		if (new_crtc != connector->encoder->crtc) {
 			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
 			mode_changed = true;
 			connector->encoder->crtc = new_crtc;
 		}
 		if (new_crtc) {
 			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
 				connector->base.id, drm_get_connector_name(connector),
 				new_crtc->base.id);
 		} else {
 			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
 				connector->base.id, drm_get_connector_name(connector));
 		}
 	}
 	/* mode_set_base is not a required function */
 	if (fb_changed && !crtc_funcs->mode_set_base)
 		mode_changed = true;
 	if (mode_changed) {
 		if (drm_helper_crtc_in_use(set->crtc)) {
 			DRM_DEBUG_KMS("attempting to set mode from"
 					" userspace\n");
 			drm_mode_debug_printmodeline(set->mode);
 			set->crtc->primary->fb = set->fb;
 			if (!drm_crtc_helper_set_mode(set->crtc, set->mode,
 						      set->x, set->y,
 						      save_set.fb)) {
 				DRM_ERROR("failed to set mode on [CRTC:%d]\n",
 					  set->crtc->base.id);
 				set->crtc->primary->fb = save_set.fb;
 				ret = -EINVAL;
 				goto fail;
 			}
 			DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
 			for (i = 0; i < set->num_connectors; i++) {
 				DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
 					      drm_get_connector_name(set->connectors[i]));
 				set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
 			}
 		}
 		__drm_helper_disable_unused_functions(dev);
 	} else if (fb_changed) {
 		set->crtc->x = set->x;
 		set->crtc->y = set->y;
 		set->crtc->primary->fb = set->fb;
 		ret = crtc_funcs->mode_set_base(set->crtc,
 						set->x, set->y, save_set.fb);
 		if (ret != 0) {
 			set->crtc->x = save_set.x;
 			set->crtc->y = save_set.y;
 			set->crtc->primary->fb = save_set.fb;
 			goto fail;
 		}
 	}
 	kfree(save_connectors);
 	kfree(save_encoders);
 	return 0;
 fail:
 	/* Restore all previous data. */
 	count = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		*encoder = save_encoders[count++];
 	}
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		*connector = save_connectors[count++];
 	}
 	/* Try to restore the config */
 	if (mode_changed &&
 	    !drm_crtc_helper_set_mode(save_set.crtc, save_set.mode, save_set.x,
 				      save_set.y, save_set.fb))
 		DRM_ERROR("failed to restore config after modeset failure\n");
 	kfree(save_connectors);
 	kfree(save_encoders);
 	return ret;
 }
 EXPORT_SYMBOL(drm_crtc_helper_set_config);
 static int drm_helper_choose_encoder_dpms(struct drm_encoder *encoder)
 {
 	int dpms = DRM_MODE_DPMS_OFF;
 	struct drm_connector *connector;
 	struct drm_device *dev = encoder->dev;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 		if (connector->encoder == encoder)
 			if (connector->dpms < dpms)
 				dpms = connector->dpms;
 	return dpms;
 }
 /* Helper which handles bridge ordering around encoder dpms */
 static void drm_helper_encoder_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct drm_bridge *bridge = encoder->bridge;
 	struct drm_encoder_helper_funcs *encoder_funcs;
 	if (bridge) {
 		if (mode == DRM_MODE_DPMS_ON)
 			bridge->funcs->pre_enable(bridge);
 		else
 			bridge->funcs->disable(bridge);
 	}
 	encoder_funcs = encoder->helper_private;
 	if (encoder_funcs->dpms)
 		encoder_funcs->dpms(encoder, mode);
 	if (bridge) {
 		if (mode == DRM_MODE_DPMS_ON)
 			bridge->funcs->enable(bridge);
 		else
 			bridge->funcs->post_disable(bridge);
 	}
 }
 static int drm_helper_choose_crtc_dpms(struct drm_crtc *crtc)
 {
 	int dpms = DRM_MODE_DPMS_OFF;
 	struct drm_connector *connector;
 	struct drm_device *dev = crtc->dev;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 		if (connector->encoder && connector->encoder->crtc == crtc)
 			if (connector->dpms < dpms)
 				dpms = connector->dpms;
 	return dpms;
 }
 /**
  * drm_helper_connector_dpms() - connector dpms helper implementation
  * @connector: affected connector
  * @mode: DPMS mode
  *
  * This is the main helper function provided by the crtc helper framework for
  * implementing the DPMS connector attribute. It computes the new desired DPMS
  * state for all encoders and crtcs in the output mesh and calls the ->dpms()
  * callback provided by the driver appropriately.
  */
 void drm_helper_connector_dpms(struct drm_connector *connector, int mode)
 {
 	struct drm_encoder *encoder = connector->encoder;
 	struct drm_crtc *crtc = encoder ? encoder->crtc : NULL;
 	int old_dpms, encoder_dpms = DRM_MODE_DPMS_OFF;
 	if (mode == connector->dpms)
 		return;
 	old_dpms = connector->dpms;
 	connector->dpms = mode;
 	if (encoder)
 		encoder_dpms = drm_helper_choose_encoder_dpms(encoder);
 	/* from off to on, do crtc then encoder */
 	if (mode < old_dpms) {
 		if (crtc) {
 			struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 			if (crtc_funcs->dpms)
 				(*crtc_funcs->dpms) (crtc,
 						     drm_helper_choose_crtc_dpms(crtc));
 		}
 		if (encoder)
 			drm_helper_encoder_dpms(encoder, encoder_dpms);
 	}
 	/* from on to off, do encoder then crtc */
 	if (mode > old_dpms) {
 		if (encoder)
 			drm_helper_encoder_dpms(encoder, encoder_dpms);
 		if (crtc) {
 			struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 			if (crtc_funcs->dpms)
 				(*crtc_funcs->dpms) (crtc,
 						     drm_helper_choose_crtc_dpms(crtc));
 		}
 	}
 	return;
 }
 EXPORT_SYMBOL(drm_helper_connector_dpms);
 /**
  * drm_helper_mode_fill_fb_struct - fill out framebuffer metadata
  * @fb: drm_framebuffer object to fill out
  * @mode_cmd: metadata from the userspace fb creation request
  *
  * This helper can be used in a drivers fb_create callback to pre-fill the fb's
  * metadata fields.
  */
 void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
 				    struct drm_mode_fb_cmd2 *mode_cmd)
 {
 	int i;
 	fb->width = mode_cmd->width;
 	fb->height = mode_cmd->height;
 	for (i = 0; i < 4; i++) {
 		fb->pitches[i] = mode_cmd->pitches[i];
 		fb->offsets[i] = mode_cmd->offsets[i];
 	}
 	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
 				    &fb->bits_per_pixel);
 	fb->pixel_format = mode_cmd->pixel_format;
 }
 EXPORT_SYMBOL(drm_helper_mode_fill_fb_struct);
 /**
  * drm_helper_resume_force_mode - force-restore mode setting configuration
  * @dev: drm_device which should be restored
  *
  * Drivers which use the mode setting helpers can use this function to
  * force-restore the mode setting configuration e.g. on resume or when something
  * else might have trampled over the hw state (like some overzealous old BIOSen
  * tended to do).
  *
  * This helper doesn't provide a error return value since restoring the old
  * config should never fail due to resource allocation issues since the driver
  * has successfully set the restored configuration already. Hence this should
  * boil down to the equivalent of a few dpms on calls, which also don't provide
  * an error code.
  *
  * Drivers where simply restoring an old configuration again might fail (e.g.
  * due to slight differences in allocating shared resources when the
  * configuration is restored in a different order than when userspace set it up)
  * need to use their own restore logic.
  */
 void drm_helper_resume_force_mode(struct drm_device *dev)
 {
 	struct drm_crtc *crtc;
 	struct drm_encoder *encoder;
 	struct drm_crtc_helper_funcs *crtc_funcs;
 	int encoder_dpms;
 	bool ret;
 	drm_modeset_lock_all(dev);
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		if (!crtc->enabled)
 			continue;
 		ret = drm_crtc_helper_set_mode(crtc, &crtc->mode,
 					       crtc->x, crtc->y, crtc->primary->fb);
 		/* Restoring the old config should never fail! */
 		if (ret == false)
 			DRM_ERROR("failed to set mode on crtc %p\n", crtc);
 		/* Turn off outputs that were already powered off */
 		if (drm_helper_choose_crtc_dpms(crtc)) {
 			list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 				if(encoder->crtc != crtc)
 					continue;
 				encoder_dpms = drm_helper_choose_encoder_dpms(
 							encoder);
 				drm_helper_encoder_dpms(encoder, encoder_dpms);
 			}
 			crtc_funcs = crtc->helper_private;
 			if (crtc_funcs->dpms)
 				(*crtc_funcs->dpms) (crtc,
 						     drm_helper_choose_crtc_dpms(crtc));
 		}
 	}
 	/* disable the unused connectors while restoring the modesetting */
 	__drm_helper_disable_unused_functions(dev);
 	drm_modeset_unlock_all(dev);
 }
 EXPORT_SYMBOL(drm_helper_resume_force_mode);

drivers/gpu/drm/radeon/atombios_crtc.c

Diff comments View file @ 6548be5

 /*
  * Copyright 2007-8 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Dave Airlie
  *          Alex Deucher
  */
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
 #include <drm/drm_fixed.h>
 #include "radeon.h"
 #include "atom.h"
 #include "atom-bits.h"
 static void atombios_overscan_setup(struct drm_crtc *crtc,
 				    struct drm_display_mode *mode,
 				    struct drm_display_mode *adjusted_mode)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
 	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
 	int a1, a2;
 	memset(&args, 0, sizeof(args));
 	args.ucCRTC = radeon_crtc->crtc_id;
 	switch (radeon_crtc->rmx_type) {
 	case RMX_CENTER:
 		args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
 		args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
 		args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
 		args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
 		break;
 	case RMX_ASPECT:
 		a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
 		a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
 		if (a1 > a2) {
 			args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
 			args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
 		} else if (a2 > a1) {
 			args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
 			args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
 		}
 		break;
 	case RMX_FULL:
 	default:
 		args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
 		args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
 		args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
 		args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
 		break;
 	}
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static void atombios_scaler_setup(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	ENABLE_SCALER_PS_ALLOCATION args;
 	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
 	struct radeon_encoder *radeon_encoder =
 		to_radeon_encoder(radeon_crtc->encoder);
 	/* fixme - fill in enc_priv for atom dac */
 	enum radeon_tv_std tv_std = TV_STD_NTSC;
 	bool is_tv = false, is_cv = false;
 	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
 		return;
 	if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 		struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 		tv_std = tv_dac->tv_std;
 		is_tv = true;
 	}
 	memset(&args, 0, sizeof(args));
 	args.ucScaler = radeon_crtc->crtc_id;
 	if (is_tv) {
 		switch (tv_std) {
 		case TV_STD_NTSC:
 		default:
 			args.ucTVStandard = ATOM_TV_NTSC;
 			break;
 		case TV_STD_PAL:
 			args.ucTVStandard = ATOM_TV_PAL;
 			break;
 		case TV_STD_PAL_M:
 			args.ucTVStandard = ATOM_TV_PALM;
 			break;
 		case TV_STD_PAL_60:
 			args.ucTVStandard = ATOM_TV_PAL60;
 			break;
 		case TV_STD_NTSC_J:
 			args.ucTVStandard = ATOM_TV_NTSCJ;
 			break;
 		case TV_STD_SCART_PAL:
 			args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 			break;
 		case TV_STD_SECAM:
 			args.ucTVStandard = ATOM_TV_SECAM;
 			break;
 		case TV_STD_PAL_CN:
 			args.ucTVStandard = ATOM_TV_PALCN;
 			break;
 		}
 		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 	} else if (is_cv) {
 		args.ucTVStandard = ATOM_TV_CV;
 		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 	} else {
 		switch (radeon_crtc->rmx_type) {
 		case RMX_FULL:
 			args.ucEnable = ATOM_SCALER_EXPANSION;
 			break;
 		case RMX_CENTER:
 			args.ucEnable = ATOM_SCALER_CENTER;
 			break;
 		case RMX_ASPECT:
 			args.ucEnable = ATOM_SCALER_EXPANSION;
 			break;
 		default:
 			if (ASIC_IS_AVIVO(rdev))
 				args.ucEnable = ATOM_SCALER_DISABLE;
 			else
 				args.ucEnable = ATOM_SCALER_CENTER;
 			break;
 		}
 	}
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 	if ((is_tv || is_cv)
 	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 		atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 	}
 }
 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int index =
 	    GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 	ENABLE_CRTC_PS_ALLOCATION args;
 	memset(&args, 0, sizeof(args));
 	args.ucCRTC = radeon_crtc->crtc_id;
 	args.ucEnable = lock;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 	ENABLE_CRTC_PS_ALLOCATION args;
 	memset(&args, 0, sizeof(args));
 	args.ucCRTC = radeon_crtc->crtc_id;
 	args.ucEnable = state;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 	ENABLE_CRTC_PS_ALLOCATION args;
 	memset(&args, 0, sizeof(args));
 	args.ucCRTC = radeon_crtc->crtc_id;
 	args.ucEnable = state;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static const u32 vga_control_regs[6] =
 {
 	AVIVO_D1VGA_CONTROL,
 	AVIVO_D2VGA_CONTROL,
 	EVERGREEN_D3VGA_CONTROL,
 	EVERGREEN_D4VGA_CONTROL,
 	EVERGREEN_D5VGA_CONTROL,
 	EVERGREEN_D6VGA_CONTROL,
 };
 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 	BLANK_CRTC_PS_ALLOCATION args;
 	u32 vga_control = 0;
 	memset(&args, 0, sizeof(args));
 	if (ASIC_IS_DCE8(rdev)) {
 		vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
 		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
 	}
 	args.ucCRTC = radeon_crtc->crtc_id;
 	args.ucBlanking = state;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 	if (ASIC_IS_DCE8(rdev)) {
 		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
 	}
 }
 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 	memset(&args, 0, sizeof(args));
 	args.ucDispPipeId = radeon_crtc->crtc_id;
 	args.ucEnable = state;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		radeon_crtc->enabled = true;
-		/* adjust pm to dpms changes BEFORE enabling crtcs */
-		radeon_pm_compute_clocks(rdev);
 		atombios_enable_crtc(crtc, ATOM_ENABLE);
 		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 			atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 		atombios_blank_crtc(crtc, ATOM_DISABLE);
 		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 		radeon_crtc_load_lut(crtc);
 		break;
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 	case DRM_MODE_DPMS_OFF:
 		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 		if (radeon_crtc->enabled)
 			atombios_blank_crtc(crtc, ATOM_ENABLE);
 		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 			atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 		atombios_enable_crtc(crtc, ATOM_DISABLE);
 		radeon_crtc->enabled = false;
-		/* adjust pm to dpms changes AFTER disabling crtcs */
-		radeon_pm_compute_clocks(rdev);
 		break;
 	}
+	/* adjust pm to dpms */
+	radeon_pm_compute_clocks(rdev);
 }
 static void
 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 			     struct drm_display_mode *mode)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 	u16 misc = 0;
 	memset(&args, 0, sizeof(args));
 	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 	args.usH_Blanking_Time =
 		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 	args.usV_Blanking_Time =
 		cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 	args.usH_SyncOffset =
 		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 	args.usH_SyncWidth =
 		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 	args.usV_SyncOffset =
 		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 	args.usV_SyncWidth =
 		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 	args.ucH_Border = radeon_crtc->h_border;
 	args.ucV_Border = radeon_crtc->v_border;
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		misc |= ATOM_VSYNC_POLARITY;
 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 		misc |= ATOM_HSYNC_POLARITY;
 	if (mode->flags & DRM_MODE_FLAG_CSYNC)
 		misc |= ATOM_COMPOSITESYNC;
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		misc |= ATOM_INTERLACE;
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		misc |= ATOM_DOUBLE_CLOCK_MODE;
 	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 	args.ucCRTC = radeon_crtc->crtc_id;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 				     struct drm_display_mode *mode)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 	u16 misc = 0;
 	memset(&args, 0, sizeof(args));
 	args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 	args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 	args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 	args.usH_SyncWidth =
 		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 	args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 	args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 	args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 	args.usV_SyncWidth =
 		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 	args.ucOverscanRight = radeon_crtc->h_border;
 	args.ucOverscanLeft = radeon_crtc->h_border;
 	args.ucOverscanBottom = radeon_crtc->v_border;
 	args.ucOverscanTop = radeon_crtc->v_border;
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		misc |= ATOM_VSYNC_POLARITY;
 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 		misc |= ATOM_HSYNC_POLARITY;
 	if (mode->flags & DRM_MODE_FLAG_CSYNC)
 		misc |= ATOM_COMPOSITESYNC;
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		misc |= ATOM_INTERLACE;
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		misc |= ATOM_DOUBLE_CLOCK_MODE;
 	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 	args.ucCRTC = radeon_crtc->crtc_id;
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 {
 	u32 ss_cntl;
 	if (ASIC_IS_DCE4(rdev)) {
 		switch (pll_id) {
 		case ATOM_PPLL1:
 			ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 			WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 			break;
 		case ATOM_PPLL2:
 			ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 			WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 			break;
 		case ATOM_DCPLL:
 		case ATOM_PPLL_INVALID:
 			return;
 		}
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		switch (pll_id) {
 		case ATOM_PPLL1:
 			ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 			ss_cntl &= ~1;
 			WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 			break;
 		case ATOM_PPLL2:
 			ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 			ss_cntl &= ~1;
 			WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 			break;
 		case ATOM_DCPLL:
 		case ATOM_PPLL_INVALID:
 			return;
 		}
 	}
 }
 union atom_enable_ss {
 	ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 };
 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 				     int enable,
 				     int pll_id,
 				     int crtc_id,
 				     struct radeon_atom_ss *ss)
 {
 	unsigned i;
 	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 	union atom_enable_ss args;
 	if (enable) {
 		/* Don't mess with SS if percentage is 0 or external ss.
 		 * SS is already disabled previously, and disabling it
 		 * again can cause display problems if the pll is already
 		 * programmed.
 		 */
 		if (ss->percentage == 0)
 			return;
 		if (ss->type & ATOM_EXTERNAL_SS_MASK)
 			return;
 	} else {
 		for (i = 0; i < rdev->num_crtc; i++) {
 			if (rdev->mode_info.crtcs[i] &&
 			    rdev->mode_info.crtcs[i]->enabled &&
 			    i != crtc_id &&
 			    pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 				/* one other crtc is using this pll don't turn
 				 * off spread spectrum as it might turn off
 				 * display on active crtc
 				 */
 				return;
 			}
 		}
 	}
 	memset(&args, 0, sizeof(args));
 	if (ASIC_IS_DCE5(rdev)) {
 		args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 		args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 		switch (pll_id) {
 		case ATOM_PPLL1:
 			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 			break;
 		case ATOM_PPLL2:
 			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 			break;
 		case ATOM_DCPLL:
 			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 			break;
 		case ATOM_PPLL_INVALID:
 			return;
 		}
 		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 		args.v3.ucEnable = enable;
 	} else if (ASIC_IS_DCE4(rdev)) {
 		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 		args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 		switch (pll_id) {
 		case ATOM_PPLL1:
 			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 			break;
 		case ATOM_PPLL2:
 			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 			break;
 		case ATOM_DCPLL:
 			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 			break;
 		case ATOM_PPLL_INVALID:
 			return;
 		}
 		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 		args.v2.ucEnable = enable;
 	} else if (ASIC_IS_DCE3(rdev)) {
 		args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 		args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 		args.v1.ucSpreadSpectrumStep = ss->step;
 		args.v1.ucSpreadSpectrumDelay = ss->delay;
 		args.v1.ucSpreadSpectrumRange = ss->range;
 		args.v1.ucPpll = pll_id;
 		args.v1.ucEnable = enable;
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 			atombios_disable_ss(rdev, pll_id);
 			return;
 		}
 		args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 		args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 		args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 		args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 		args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 		args.lvds_ss_2.ucEnable = enable;
 	} else {
 		if (enable == ATOM_DISABLE) {
 			atombios_disable_ss(rdev, pll_id);
 			return;
 		}
 		args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 		args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 		args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 		args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 		args.lvds_ss.ucEnable = enable;
 	}
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 union adjust_pixel_clock {
 	ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 };
 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 			       struct drm_display_mode *mode)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_encoder *encoder = radeon_crtc->encoder;
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 	u32 adjusted_clock = mode->clock;
 	int encoder_mode = atombios_get_encoder_mode(encoder);
 	u32 dp_clock = mode->clock;
 	int bpc = radeon_crtc->bpc;
 	bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 	/* reset the pll flags */
 	radeon_crtc->pll_flags = 0;
 	if (ASIC_IS_AVIVO(rdev)) {
 		if ((rdev->family == CHIP_RS600) ||
 		    (rdev->family == CHIP_RS690) ||
 		    (rdev->family == CHIP_RS740))
 			radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 				RADEON_PLL_PREFER_CLOSEST_LOWER);
 		if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)	/* range limits??? */
 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 		else
 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 		if (rdev->family < CHIP_RV770)
 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 		/* use frac fb div on APUs */
 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 		/* use frac fb div on RS780/RS880 */
 		if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 		if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 	} else {
 		radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 		if (mode->clock > 200000)	/* range limits??? */
 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 		else
 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 	}
 	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 	    (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 		if (connector) {
 			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 			struct radeon_connector_atom_dig *dig_connector =
 				radeon_connector->con_priv;
 			dp_clock = dig_connector->dp_clock;
 		}
 	}
 	/* use recommended ref_div for ss */
 	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 		if (radeon_crtc->ss_enabled) {
 			if (radeon_crtc->ss.refdiv) {
 				radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 				radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 				if (ASIC_IS_AVIVO(rdev))
 					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 			}
 		}
 	}
 	if (ASIC_IS_AVIVO(rdev)) {
 		/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 			adjusted_clock = mode->clock * 2;
 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 			radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 	} else {
 		if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 			radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 		if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 			radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 	}
 	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 	 * accordingly based on the encoder/transmitter to work around
 	 * special hw requirements.
 	 */
 	if (ASIC_IS_DCE3(rdev)) {
 		union adjust_pixel_clock args;
 		u8 frev, crev;
 		int index;
 		index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 					   &crev))
 			return adjusted_clock;
 		memset(&args, 0, sizeof(args));
 		switch (frev) {
 		case 1:
 			switch (crev) {
 			case 1:
 			case 2:
 				args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 				args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 				args.v1.ucEncodeMode = encoder_mode;
 				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 					args.v1.ucConfig |=
 						ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 				atom_execute_table(rdev->mode_info.atom_context,
 						   index, (uint32_t *)&args);
 				adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 				break;
 			case 3:
 				args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 				args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 				args.v3.sInput.ucEncodeMode = encoder_mode;
 				args.v3.sInput.ucDispPllConfig = 0;
 				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 					args.v3.sInput.ucDispPllConfig |=
 						DISPPLL_CONFIG_SS_ENABLE;
 				if (ENCODER_MODE_IS_DP(encoder_mode)) {
 					args.v3.sInput.ucDispPllConfig |=
 						DISPPLL_CONFIG_COHERENT_MODE;
 					/* 16200 or 27000 */
 					args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 				} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 					if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 						/* deep color support */
 						args.v3.sInput.usPixelClock =
 							cpu_to_le16((mode->clock * bpc / 8) / 10);
 					if (dig->coherent_mode)
 						args.v3.sInput.ucDispPllConfig |=
 							DISPPLL_CONFIG_COHERENT_MODE;
 					if (is_duallink)
 						args.v3.sInput.ucDispPllConfig |=
 							DISPPLL_CONFIG_DUAL_LINK;
 				}
 				if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 				    ENCODER_OBJECT_ID_NONE)
 					args.v3.sInput.ucExtTransmitterID =
 						radeon_encoder_get_dp_bridge_encoder_id(encoder);
 				else
 					args.v3.sInput.ucExtTransmitterID = 0;
 				atom_execute_table(rdev->mode_info.atom_context,
 						   index, (uint32_t *)&args);
 				adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 				if (args.v3.sOutput.ucRefDiv) {
 					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 					radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 					radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 				}
 				if (args.v3.sOutput.ucPostDiv) {
 					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 					radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 					radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 				}
 				break;
 			default:
 				DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 				return adjusted_clock;
 			}
 			break;
 		default:
 			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 			return adjusted_clock;
 		}
 	}
 	return adjusted_clock;
 }
 union set_pixel_clock {
 	SET_PIXEL_CLOCK_PS_ALLOCATION base;
 	PIXEL_CLOCK_PARAMETERS v1;
 	PIXEL_CLOCK_PARAMETERS_V2 v2;
 	PIXEL_CLOCK_PARAMETERS_V3 v3;
 	PIXEL_CLOCK_PARAMETERS_V5 v5;
 	PIXEL_CLOCK_PARAMETERS_V6 v6;
 };
 /* on DCE5, make sure the voltage is high enough to support the
  * required disp clk.
  */
 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 				    u32 dispclk)
 {
 	u8 frev, crev;
 	int index;
 	union set_pixel_clock args;
 	memset(&args, 0, sizeof(args));
 	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 				   &crev))
 		return;
 	switch (frev) {
 	case 1:
 		switch (crev) {
 		case 5:
 			/* if the default dcpll clock is specified,
 			 * SetPixelClock provides the dividers
 			 */
 			args.v5.ucCRTC = ATOM_CRTC_INVALID;
 			args.v5.usPixelClock = cpu_to_le16(dispclk);
 			args.v5.ucPpll = ATOM_DCPLL;
 			break;
 		case 6:
 			/* if the default dcpll clock is specified,
 			 * SetPixelClock provides the dividers
 			 */
 			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 			if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 				args.v6.ucPpll = ATOM_EXT_PLL1;
 			else if (ASIC_IS_DCE6(rdev))
 				args.v6.ucPpll = ATOM_PPLL0;
 			else
 				args.v6.ucPpll = ATOM_DCPLL;
 			break;
 		default:
 			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 			return;
 		}
 		break;
 	default:
 		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 		return;
 	}
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 				      u32 crtc_id,
 				      int pll_id,
 				      u32 encoder_mode,
 				      u32 encoder_id,
 				      u32 clock,
 				      u32 ref_div,
 				      u32 fb_div,
 				      u32 frac_fb_div,
 				      u32 post_div,
 				      int bpc,
 				      bool ss_enabled,
 				      struct radeon_atom_ss *ss)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	u8 frev, crev;
 	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 	union set_pixel_clock args;
 	memset(&args, 0, sizeof(args));
 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 				   &crev))
 		return;
 	switch (frev) {
 	case 1:
 		switch (crev) {
 		case 1:
 			if (clock == ATOM_DISABLE)
 				return;
 			args.v1.usPixelClock = cpu_to_le16(clock / 10);
 			args.v1.usRefDiv = cpu_to_le16(ref_div);
 			args.v1.usFbDiv = cpu_to_le16(fb_div);
 			args.v1.ucFracFbDiv = frac_fb_div;
 			args.v1.ucPostDiv = post_div;
 			args.v1.ucPpll = pll_id;
 			args.v1.ucCRTC = crtc_id;
 			args.v1.ucRefDivSrc = 1;
 			break;
 		case 2:
 			args.v2.usPixelClock = cpu_to_le16(clock / 10);
 			args.v2.usRefDiv = cpu_to_le16(ref_div);
 			args.v2.usFbDiv = cpu_to_le16(fb_div);
 			args.v2.ucFracFbDiv = frac_fb_div;
 			args.v2.ucPostDiv = post_div;
 			args.v2.ucPpll = pll_id;
 			args.v2.ucCRTC = crtc_id;
 			args.v2.ucRefDivSrc = 1;
 			break;
 		case 3:
 			args.v3.usPixelClock = cpu_to_le16(clock / 10);
 			args.v3.usRefDiv = cpu_to_le16(ref_div);
 			args.v3.usFbDiv = cpu_to_le16(fb_div);
 			args.v3.ucFracFbDiv = frac_fb_div;
 			args.v3.ucPostDiv = post_div;
 			args.v3.ucPpll = pll_id;
 			if (crtc_id == ATOM_CRTC2)
 				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 			else
 				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 				args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 			args.v3.ucTransmitterId = encoder_id;
 			args.v3.ucEncoderMode = encoder_mode;
 			break;
 		case 5:
 			args.v5.ucCRTC = crtc_id;
 			args.v5.usPixelClock = cpu_to_le16(clock / 10);
 			args.v5.ucRefDiv = ref_div;
 			args.v5.usFbDiv = cpu_to_le16(fb_div);
 			args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 			args.v5.ucPostDiv = post_div;
 			args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 			switch (bpc) {
 			case 8:
 			default:
 				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 				break;
 			case 10:
 				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 				break;
 			}
 			args.v5.ucTransmitterID = encoder_id;
 			args.v5.ucEncoderMode = encoder_mode;
 			args.v5.ucPpll = pll_id;
 			break;
 		case 6:
 			args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 			args.v6.ucRefDiv = ref_div;
 			args.v6.usFbDiv = cpu_to_le16(fb_div);
 			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 			args.v6.ucPostDiv = post_div;
 			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 			switch (bpc) {
 			case 8:
 			default:
 				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 				break;
 			case 10:
 				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 				break;
 			case 12:
 				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 				break;
 			case 16:
 				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 				break;
 			}
 			args.v6.ucTransmitterID = encoder_id;
 			args.v6.ucEncoderMode = encoder_mode;
 			args.v6.ucPpll = pll_id;
 			break;
 		default:
 			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 			return;
 		}
 		break;
 	default:
 		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 		return;
 	}
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder =
 		to_radeon_encoder(radeon_crtc->encoder);
 	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 	radeon_crtc->bpc = 8;
 	radeon_crtc->ss_enabled = false;
 	if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 	    (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 		struct drm_connector *connector =
 			radeon_get_connector_for_encoder(radeon_crtc->encoder);
 		struct radeon_connector *radeon_connector =
 			to_radeon_connector(connector);
 		struct radeon_connector_atom_dig *dig_connector =
 			radeon_connector->con_priv;
 		int dp_clock;
 		radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 		switch (encoder_mode) {
 		case ATOM_ENCODER_MODE_DP_MST:
 		case ATOM_ENCODER_MODE_DP:
 			/* DP/eDP */
 			dp_clock = dig_connector->dp_clock / 10;
 			if (ASIC_IS_DCE4(rdev))
 				radeon_crtc->ss_enabled =
 					radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 									 ASIC_INTERNAL_SS_ON_DP,
 									 dp_clock);
 			else {
 				if (dp_clock == 16200) {
 					radeon_crtc->ss_enabled =
 						radeon_atombios_get_ppll_ss_info(rdev,
 										 &radeon_crtc->ss,
 										 ATOM_DP_SS_ID2);
 					if (!radeon_crtc->ss_enabled)
 						radeon_crtc->ss_enabled =
 							radeon_atombios_get_ppll_ss_info(rdev,
 											 &radeon_crtc->ss,
 											 ATOM_DP_SS_ID1);
 				} else {
 					radeon_crtc->ss_enabled =
 						radeon_atombios_get_ppll_ss_info(rdev,
 										 &radeon_crtc->ss,
 										 ATOM_DP_SS_ID1);
 				}
 				/* disable spread spectrum on DCE3 DP */
 				radeon_crtc->ss_enabled = false;
 			}
 			break;
 		case ATOM_ENCODER_MODE_LVDS:
 			if (ASIC_IS_DCE4(rdev))
 				radeon_crtc->ss_enabled =
 					radeon_atombios_get_asic_ss_info(rdev,
 									 &radeon_crtc->ss,
 									 dig->lcd_ss_id,
 									 mode->clock / 10);
 			else
 				radeon_crtc->ss_enabled =
 					radeon_atombios_get_ppll_ss_info(rdev,
 									 &radeon_crtc->ss,
 									 dig->lcd_ss_id);
 			break;
 		case ATOM_ENCODER_MODE_DVI:
 			if (ASIC_IS_DCE4(rdev))
 				radeon_crtc->ss_enabled =
 					radeon_atombios_get_asic_ss_info(rdev,
 									 &radeon_crtc->ss,
 									 ASIC_INTERNAL_SS_ON_TMDS,
 									 mode->clock / 10);
 			break;
 		case ATOM_ENCODER_MODE_HDMI:
 			if (ASIC_IS_DCE4(rdev))
 				radeon_crtc->ss_enabled =
 					radeon_atombios_get_asic_ss_info(rdev,
 									 &radeon_crtc->ss,
 									 ASIC_INTERNAL_SS_ON_HDMI,
 									 mode->clock / 10);
 			break;
 		default:
 			break;
 		}
 	}
 	/* adjust pixel clock as needed */
 	radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
 	return true;
 }
 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder =
 		to_radeon_encoder(radeon_crtc->encoder);
 	u32 pll_clock = mode->clock;
 	u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 	struct radeon_pll *pll;
 	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 	switch (radeon_crtc->pll_id) {
 	case ATOM_PPLL1:
 		pll = &rdev->clock.p1pll;
 		break;
 	case ATOM_PPLL2:
 		pll = &rdev->clock.p2pll;
 		break;
 	case ATOM_DCPLL:
 	case ATOM_PPLL_INVALID:
 	default:
 		pll = &rdev->clock.dcpll;
 		break;
 	}
 	/* update pll params */
 	pll->flags = radeon_crtc->pll_flags;
 	pll->reference_div = radeon_crtc->pll_reference_div;
 	pll->post_div = radeon_crtc->pll_post_div;
 	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 		/* TV seems to prefer the legacy algo on some boards */
 		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
 					  &fb_div, &frac_fb_div, &ref_div, &post_div);
 	else if (ASIC_IS_AVIVO(rdev))
 		radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
 					 &fb_div, &frac_fb_div, &ref_div, &post_div);
 	else
 		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
 					  &fb_div, &frac_fb_div, &ref_div, &post_div);
 	atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
 				 radeon_crtc->crtc_id, &radeon_crtc->ss);
 	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
 				  encoder_mode, radeon_encoder->encoder_id, mode->clock,
 				  ref_div, fb_div, frac_fb_div, post_div,
 				  radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
 	if (radeon_crtc->ss_enabled) {
 		/* calculate ss amount and step size */
 		if (ASIC_IS_DCE4(rdev)) {
 			u32 step_size;
 			u32 amount = (((fb_div * 10) + frac_fb_div) *
 				      (u32)radeon_crtc->ss.percentage) /
 				(100 * (u32)radeon_crtc->ss.percentage_divider);
 			radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
 			radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
 				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
 			if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
 				step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
 					(125 * 25 * pll->reference_freq / 100);
 			else
 				step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
 					(125 * 25 * pll->reference_freq / 100);
 			radeon_crtc->ss.step = step_size;
 		}
 		atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
 					 radeon_crtc->crtc_id, &radeon_crtc->ss);
 	}
 }
 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 int x, int y, int atomic)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_framebuffer *radeon_fb;
 	struct drm_framebuffer *target_fb;
 	struct drm_gem_object *obj;
 	struct radeon_bo *rbo;
 	uint64_t fb_location;
 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 	unsigned bankw, bankh, mtaspect, tile_split;
 	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
 	u32 tmp, viewport_w, viewport_h;
 	int r;
 	/* no fb bound */
 	if (!atomic && !crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
 	if (atomic) {
 		radeon_fb = to_radeon_framebuffer(fb);
 		target_fb = fb;
 	}
 	else {
 		radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 		target_fb = crtc->primary->fb;
 	}
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	 */
 	obj = radeon_fb->obj;
 	rbo = gem_to_radeon_bo(obj);
 	r = radeon_bo_reserve(rbo, false);
 	if (unlikely(r != 0))
 		return r;
 	if (atomic)
 		fb_location = radeon_bo_gpu_offset(rbo);
 	else {
 		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 		if (unlikely(r != 0)) {
 			radeon_bo_unreserve(rbo);
 			return -EINVAL;
 		}
 	}
 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 	radeon_bo_unreserve(rbo);
 	switch (target_fb->bits_per_pixel) {
 	case 8:
 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
 			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
 		break;
 	case 15:
 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
 		break;
 	case 16:
 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
 #ifdef __BIG_ENDIAN
 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
 #endif
 		break;
 	case 24:
 	case 32:
 		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
 			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
 #ifdef __BIG_ENDIAN
 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
 #endif
 		break;
 	default:
 		DRM_ERROR("Unsupported screen depth %d\n",
 			  target_fb->bits_per_pixel);
 		return -EINVAL;
 	}
 	if (tiling_flags & RADEON_TILING_MACRO) {
 		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
 		/* Set NUM_BANKS. */
 		if (rdev->family >= CHIP_TAHITI) {
 			unsigned index, num_banks;
 			if (rdev->family >= CHIP_BONAIRE) {
 				unsigned tileb, tile_split_bytes;
 				/* Calculate the macrotile mode index. */
 				tile_split_bytes = 64 << tile_split;
 				tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
 				tileb = min(tile_split_bytes, tileb);
 				for (index = 0; tileb > 64; index++)
 					tileb >>= 1;
 				if (index >= 16) {
 					DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
 						  target_fb->bits_per_pixel, tile_split);
 					return -EINVAL;
 				}
 				num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
 			} else {
 				switch (target_fb->bits_per_pixel) {
 				case 8:
 					index = 10;
 					break;
 				case 16:
 					index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
 					break;
 				default:
 				case 32:
 					index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
 					break;
 				}
 				num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
 			}
 			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
 		} else {
 			/* NI and older. */
 			if (rdev->family >= CHIP_CAYMAN)
 				tmp = rdev->config.cayman.tile_config;
 			else
 				tmp = rdev->config.evergreen.tile_config;
 			switch ((tmp & 0xf0) >> 4) {
 			case 0: /* 4 banks */
 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
 				break;
 			case 1: /* 8 banks */
 			default:
 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
 				break;
 			case 2: /* 16 banks */
 				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
 				break;
 			}
 		}
 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
 		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
 		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
 		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
 		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
 		if (rdev->family >= CHIP_BONAIRE) {
 			/* XXX need to know more about the surface tiling mode */
 			fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
 		}
 	} else if (tiling_flags & RADEON_TILING_MICRO)
 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 	if (rdev->family >= CHIP_BONAIRE) {
 		/* Read the pipe config from the 2D TILED SCANOUT mode.
 		 * It should be the same for the other modes too, but not all
 		 * modes set the pipe config field. */
 		u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
 		fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
 	} else if ((rdev->family == CHIP_TAHITI) ||
 		   (rdev->family == CHIP_PITCAIRN))
 		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
 	else if ((rdev->family == CHIP_VERDE) ||
 		 (rdev->family == CHIP_OLAND) ||
 		 (rdev->family == CHIP_HAINAN)) /* for completeness.  HAINAN has no display hw */
 		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
 	switch (radeon_crtc->crtc_id) {
 	case 0:
 		WREG32(AVIVO_D1VGA_CONTROL, 0);
 		break;
 	case 1:
 		WREG32(AVIVO_D2VGA_CONTROL, 0);
 		break;
 	case 2:
 		WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 		break;
 	case 3:
 		WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 		break;
 	case 4:
 		WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 		break;
 	case 5:
 		WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 		break;
 	default:
 		break;
 	}
 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 	       upper_32_bits(fb_location));
 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 	       upper_32_bits(fb_location));
 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 	       (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 	       (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
 	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
 	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 	if (rdev->family >= CHIP_BONAIRE)
 		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 		       target_fb->height);
 	else
 		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 		       target_fb->height);
 	x &= ~3;
 	y &= ~1;
 	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
 	       (x << 16) | y);
 	viewport_w = crtc->mode.hdisplay;
 	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 	       (viewport_w << 16) | viewport_h);
 	/* pageflip setup */
 	/* make sure flip is at vb rather than hb */
 	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
 	tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
 	/* set pageflip to happen anywhere in vblank interval */
 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
 	if (!atomic && fb && fb != crtc->primary->fb) {
 		radeon_fb = to_radeon_framebuffer(fb);
 		rbo = gem_to_radeon_bo(radeon_fb->obj);
 		r = radeon_bo_reserve(rbo, false);
 		if (unlikely(r != 0))
 			return r;
 		radeon_bo_unpin(rbo);
 		radeon_bo_unreserve(rbo);
 	}
 	/* Bytes per pixel may have changed */
 	radeon_bandwidth_update(rdev);
 	return 0;
 }
 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
 				  struct drm_framebuffer *fb,
 				  int x, int y, int atomic)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_framebuffer *radeon_fb;
 	struct drm_gem_object *obj;
 	struct radeon_bo *rbo;
 	struct drm_framebuffer *target_fb;
 	uint64_t fb_location;
 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
 	u32 tmp, viewport_w, viewport_h;
 	int r;
 	/* no fb bound */
 	if (!atomic && !crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
 	if (atomic) {
 		radeon_fb = to_radeon_framebuffer(fb);
 		target_fb = fb;
 	}
 	else {
 		radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 		target_fb = crtc->primary->fb;
 	}
 	obj = radeon_fb->obj;
 	rbo = gem_to_radeon_bo(obj);
 	r = radeon_bo_reserve(rbo, false);
 	if (unlikely(r != 0))
 		return r;
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	 */
 	if (atomic)
 		fb_location = radeon_bo_gpu_offset(rbo);
 	else {
 		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 		if (unlikely(r != 0)) {
 			radeon_bo_unreserve(rbo);
 			return -EINVAL;
 		}
 	}
 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 	radeon_bo_unreserve(rbo);
 	switch (target_fb->bits_per_pixel) {
 	case 8:
 		fb_format =
 		    AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
 		    AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
 		break;
 	case 15:
 		fb_format =
 		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 		    AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 		break;
 	case 16:
 		fb_format =
 		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 		    AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 #ifdef __BIG_ENDIAN
 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
 #endif
 		break;
 	case 24:
 	case 32:
 		fb_format =
 		    AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
 		    AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 #ifdef __BIG_ENDIAN
 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
 #endif
 		break;
 	default:
 		DRM_ERROR("Unsupported screen depth %d\n",
 			  target_fb->bits_per_pixel);
 		return -EINVAL;
 	}
 	if (rdev->family >= CHIP_R600) {
 		if (tiling_flags & RADEON_TILING_MACRO)
 			fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
 		else if (tiling_flags & RADEON_TILING_MICRO)
 			fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
 	} else {
 		if (tiling_flags & RADEON_TILING_MACRO)
 			fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 		if (tiling_flags & RADEON_TILING_MICRO)
 			fb_format |= AVIVO_D1GRPH_TILED;
 	}
 	if (radeon_crtc->crtc_id == 0)
 		WREG32(AVIVO_D1VGA_CONTROL, 0);
 	else
 		WREG32(AVIVO_D2VGA_CONTROL, 0);
 	if (rdev->family >= CHIP_RV770) {
 		if (radeon_crtc->crtc_id) {
 			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
 			WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
 		} else {
 			WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
 			WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
 		}
 	}
 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 	       (u32) fb_location);
 	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
 	       radeon_crtc->crtc_offset, (u32) fb_location);
 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 	if (rdev->family >= CHIP_R600)
 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
 	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
 	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 	       target_fb->height);
 	x &= ~3;
 	y &= ~1;
 	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
 	       (x << 16) | y);
 	viewport_w = crtc->mode.hdisplay;
 	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
 	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 	       (viewport_w << 16) | viewport_h);
 	/* pageflip setup */
 	/* make sure flip is at vb rather than hb */
 	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
 	tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
 	/* set pageflip to happen anywhere in vblank interval */
 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
 	if (!atomic && fb && fb != crtc->primary->fb) {
 		radeon_fb = to_radeon_framebuffer(fb);
 		rbo = gem_to_radeon_bo(radeon_fb->obj);
 		r = radeon_bo_reserve(rbo, false);
 		if (unlikely(r != 0))
 			return r;
 		radeon_bo_unpin(rbo);
 		radeon_bo_unreserve(rbo);
 	}
 	/* Bytes per pixel may have changed */
 	radeon_bandwidth_update(rdev);
 	return 0;
 }
 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 			   struct drm_framebuffer *old_fb)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	if (ASIC_IS_DCE4(rdev))
 		return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
 	else if (ASIC_IS_AVIVO(rdev))
 		return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
 	else
 		return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 }
 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
                                   struct drm_framebuffer *fb,
 				  int x, int y, enum mode_set_atomic state)
 {
        struct drm_device *dev = crtc->dev;
        struct radeon_device *rdev = dev->dev_private;
 	if (ASIC_IS_DCE4(rdev))
 		return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
 	else if (ASIC_IS_AVIVO(rdev))
 		return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
 	else
 		return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 /* properly set additional regs when using atombios */
 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	u32 disp_merge_cntl;
 	switch (radeon_crtc->crtc_id) {
 	case 0:
 		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 		break;
 	case 1:
 		disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 		disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 		WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 		WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
 		WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
 		break;
 	}
 }
 /**
  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
  *
  * @crtc: drm crtc
  *
  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
  */
 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_crtc *test_crtc;
 	struct radeon_crtc *test_radeon_crtc;
 	u32 pll_in_use = 0;
 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
 		if (crtc == test_crtc)
 			continue;
 		test_radeon_crtc = to_radeon_crtc(test_crtc);
 		if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
 			pll_in_use |= (1 << test_radeon_crtc->pll_id);
 	}
 	return pll_in_use;
 }
 /**
  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
  *
  * @crtc: drm crtc
  *
  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
  * also in DP mode.  For DP, a single PPLL can be used for all DP
  * crtcs/encoders.
  */
 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_crtc *test_crtc;
 	struct radeon_crtc *test_radeon_crtc;
 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
 		if (crtc == test_crtc)
 			continue;
 		test_radeon_crtc = to_radeon_crtc(test_crtc);
 		if (test_radeon_crtc->encoder &&
 		    ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
 			/* for DP use the same PLL for all */
 			if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
 				return test_radeon_crtc->pll_id;
 		}
 	}
 	return ATOM_PPLL_INVALID;
 }
 /**
  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
  *
  * @crtc: drm crtc
  * @encoder: drm encoder
  *
  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
  * be shared (i.e., same clock).
  */
 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct drm_crtc *test_crtc;
 	struct radeon_crtc *test_radeon_crtc;
 	u32 adjusted_clock, test_adjusted_clock;
 	adjusted_clock = radeon_crtc->adjusted_clock;
 	if (adjusted_clock == 0)
 		return ATOM_PPLL_INVALID;
 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
 		if (crtc == test_crtc)
 			continue;
 		test_radeon_crtc = to_radeon_crtc(test_crtc);
 		if (test_radeon_crtc->encoder &&
 		    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
 			/* check if we are already driving this connector with another crtc */
 			if (test_radeon_crtc->connector == radeon_crtc->connector) {
 				/* if we are, return that pll */
 				if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
 					return test_radeon_crtc->pll_id;
 			}
 			/* for non-DP check the clock */
 			test_adjusted_clock = test_radeon_crtc->adjusted_clock;
 			if ((crtc->mode.clock == test_crtc->mode.clock) &&
 			    (adjusted_clock == test_adjusted_clock) &&
 			    (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
 			    (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
 				return test_radeon_crtc->pll_id;
 		}
 	}
 	return ATOM_PPLL_INVALID;
 }
 /**
  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
  *
  * @crtc: drm crtc
  *
  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
  * monitors a dedicated PPLL must be used.  If a particular board has
  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
  * as there is no need to program the PLL itself.  If we are not able to
  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
  * avoid messing up an existing monitor.
  *
  * Asic specific PLL information
  *
  * DCE 8.x
  * KB/KV
  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
  * CI
  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
  *
  * DCE 6.1
  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
  *
  * DCE 6.0
  * - PPLL0 is available to all UNIPHY (DP only)
  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
  *
  * DCE 5.0
  * - DCPLL is available to all UNIPHY (DP only)
  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
  *
  * DCE 3.0/4.0/4.1
  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
  *
  */
 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder =
 		to_radeon_encoder(radeon_crtc->encoder);
 	u32 pll_in_use;
 	int pll;
 	if (ASIC_IS_DCE8(rdev)) {
 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
 			if (rdev->clock.dp_extclk)
 				/* skip PPLL programming if using ext clock */
 				return ATOM_PPLL_INVALID;
 			else {
 				/* use the same PPLL for all DP monitors */
 				pll = radeon_get_shared_dp_ppll(crtc);
 				if (pll != ATOM_PPLL_INVALID)
 					return pll;
 			}
 		} else {
 			/* use the same PPLL for all monitors with the same clock */
 			pll = radeon_get_shared_nondp_ppll(crtc);
 			if (pll != ATOM_PPLL_INVALID)
 				return pll;
 		}
 		/* otherwise, pick one of the plls */
 		if ((rdev->family == CHIP_KAVERI) ||
 		    (rdev->family == CHIP_KABINI) ||
 		    (rdev->family == CHIP_MULLINS)) {
 			/* KB/KV/ML has PPLL1 and PPLL2 */
 			pll_in_use = radeon_get_pll_use_mask(crtc);
 			if (!(pll_in_use & (1 << ATOM_PPLL2)))
 				return ATOM_PPLL2;
 			if (!(pll_in_use & (1 << ATOM_PPLL1)))
 				return ATOM_PPLL1;
 			DRM_ERROR("unable to allocate a PPLL\n");
 			return ATOM_PPLL_INVALID;
 		} else {
 			/* CI has PPLL0, PPLL1, and PPLL2 */
 			pll_in_use = radeon_get_pll_use_mask(crtc);
 			if (!(pll_in_use & (1 << ATOM_PPLL2)))
 				return ATOM_PPLL2;
 			if (!(pll_in_use & (1 << ATOM_PPLL1)))
 				return ATOM_PPLL1;
 			if (!(pll_in_use & (1 << ATOM_PPLL0)))
 				return ATOM_PPLL0;
 			DRM_ERROR("unable to allocate a PPLL\n");
 			return ATOM_PPLL_INVALID;
 		}
 	} else if (ASIC_IS_DCE61(rdev)) {
 		struct radeon_encoder_atom_dig *dig =
 			radeon_encoder->enc_priv;
 		if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
 		    (dig->linkb == false))
 			/* UNIPHY A uses PPLL2 */
 			return ATOM_PPLL2;
 		else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
 			/* UNIPHY B/C/D/E/F */
 			if (rdev->clock.dp_extclk)
 				/* skip PPLL programming if using ext clock */
 				return ATOM_PPLL_INVALID;
 			else {
 				/* use the same PPLL for all DP monitors */
 				pll = radeon_get_shared_dp_ppll(crtc);
 				if (pll != ATOM_PPLL_INVALID)
 					return pll;
 			}
 		} else {
 			/* use the same PPLL for all monitors with the same clock */
 			pll = radeon_get_shared_nondp_ppll(crtc);
 			if (pll != ATOM_PPLL_INVALID)
 				return pll;
 		}
 		/* UNIPHY B/C/D/E/F */
 		pll_in_use = radeon_get_pll_use_mask(crtc);
 		if (!(pll_in_use & (1 << ATOM_PPLL0)))
 			return ATOM_PPLL0;
 		if (!(pll_in_use & (1 << ATOM_PPLL1)))
 			return ATOM_PPLL1;
 		DRM_ERROR("unable to allocate a PPLL\n");
 		return ATOM_PPLL_INVALID;
 	} else if (ASIC_IS_DCE41(rdev)) {
 		/* Don't share PLLs on DCE4.1 chips */
 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
 			if (rdev->clock.dp_extclk)
 				/* skip PPLL programming if using ext clock */
 				return ATOM_PPLL_INVALID;
 		}
 		pll_in_use = radeon_get_pll_use_mask(crtc);
 		if (!(pll_in_use & (1 << ATOM_PPLL1)))
 			return ATOM_PPLL1;
 		if (!(pll_in_use & (1 << ATOM_PPLL2)))
 			return ATOM_PPLL2;
 		DRM_ERROR("unable to allocate a PPLL\n");
 		return ATOM_PPLL_INVALID;
 	} else if (ASIC_IS_DCE4(rdev)) {
 		/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
 		 * depending on the asic:
 		 * DCE4: PPLL or ext clock
 		 * DCE5: PPLL, DCPLL, or ext clock
 		 * DCE6: PPLL, PPLL0, or ext clock
 		 *
 		 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
 		 * PPLL/DCPLL programming and only program the DP DTO for the
 		 * crtc virtual pixel clock.
 		 */
 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
 			if (rdev->clock.dp_extclk)
 				/* skip PPLL programming if using ext clock */
 				return ATOM_PPLL_INVALID;
 			else if (ASIC_IS_DCE6(rdev))
 				/* use PPLL0 for all DP */
 				return ATOM_PPLL0;
 			else if (ASIC_IS_DCE5(rdev))
 				/* use DCPLL for all DP */
 				return ATOM_DCPLL;
 			else {
 				/* use the same PPLL for all DP monitors */
 				pll = radeon_get_shared_dp_ppll(crtc);
 				if (pll != ATOM_PPLL_INVALID)
 					return pll;
 			}
 		} else {
 			/* use the same PPLL for all monitors with the same clock */
 			pll = radeon_get_shared_nondp_ppll(crtc);
 			if (pll != ATOM_PPLL_INVALID)
 				return pll;
 		}
 		/* all other cases */
 		pll_in_use = radeon_get_pll_use_mask(crtc);
 		if (!(pll_in_use & (1 << ATOM_PPLL1)))
 			return ATOM_PPLL1;
 		if (!(pll_in_use & (1 << ATOM_PPLL2)))
 			return ATOM_PPLL2;
 		DRM_ERROR("unable to allocate a PPLL\n");
 		return ATOM_PPLL_INVALID;
 	} else {
 		/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
 		/* some atombios (observed in some DCE2/DCE3) code have a bug,
 		 * the matching btw pll and crtc is done through
 		 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
 		 * pll (1 or 2) to select which register to write. ie if using
 		 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
 		 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
 		 * choose which value to write. Which is reverse order from
 		 * register logic. So only case that works is when pllid is
 		 * same as crtcid or when both pll and crtc are enabled and
 		 * both use same clock.
 		 *
 		 * So just return crtc id as if crtc and pll were hard linked
 		 * together even if they aren't
 		 */
 		return radeon_crtc->crtc_id;
 	}
 }
 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
 {
 	/* always set DCPLL */
 	if (ASIC_IS_DCE6(rdev))
 		atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
 	else if (ASIC_IS_DCE4(rdev)) {
 		struct radeon_atom_ss ss;
 		bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
 								   ASIC_INTERNAL_SS_ON_DCPLL,
 								   rdev->clock.default_dispclk);
 		if (ss_enabled)
 			atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
 		/* XXX: DCE5, make sure voltage, dispclk is high enough */
 		atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
 		if (ss_enabled)
 			atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
 	}
 }
 int atombios_crtc_mode_set(struct drm_crtc *crtc,
 			   struct drm_display_mode *mode,
 			   struct drm_display_mode *adjusted_mode,
 			   int x, int y, struct drm_framebuffer *old_fb)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder =
 		to_radeon_encoder(radeon_crtc->encoder);
 	bool is_tvcv = false;
 	if (radeon_encoder->active_device &
 	    (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
 		is_tvcv = true;
 	if (!radeon_crtc->adjusted_clock)
 		return -EINVAL;
 	atombios_crtc_set_pll(crtc, adjusted_mode);
 	if (ASIC_IS_DCE4(rdev))
 		atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
 	else if (ASIC_IS_AVIVO(rdev)) {
 		if (is_tvcv)
 			atombios_crtc_set_timing(crtc, adjusted_mode);
 		else
 			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
 	} else {
 		atombios_crtc_set_timing(crtc, adjusted_mode);
 		if (radeon_crtc->crtc_id == 0)
 			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
 		radeon_legacy_atom_fixup(crtc);
 	}
 	atombios_crtc_set_base(crtc, x, y, old_fb);
 	atombios_overscan_setup(crtc, mode, adjusted_mode);
 	atombios_scaler_setup(crtc);
 	/* update the hw version fpr dpm */
 	radeon_crtc->hw_mode = *adjusted_mode;
 	return 0;
 }
 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 				     const struct drm_display_mode *mode,
 				     struct drm_display_mode *adjusted_mode)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct drm_encoder *encoder;
 	/* assign the encoder to the radeon crtc to avoid repeated lookups later */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc == crtc) {
 			radeon_crtc->encoder = encoder;
 			radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
 			break;
 		}
 	}
 	if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
 		radeon_crtc->encoder = NULL;
 		radeon_crtc->connector = NULL;
 		return false;
 	}
 	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
 		return false;
 	if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
 		return false;
 	/* pick pll */
 	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
 	/* if we can't get a PPLL for a non-DP encoder, fail */
 	if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
 	    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
 		return false;
 	return true;
 }
 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	/* disable crtc pair power gating before programming */
 	if (ASIC_IS_DCE6(rdev))
 		atombios_powergate_crtc(crtc, ATOM_DISABLE);
 	atombios_lock_crtc(crtc, ATOM_ENABLE);
 	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 }
 static void atombios_crtc_commit(struct drm_crtc *crtc)
 {
 	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 	atombios_lock_crtc(crtc, ATOM_DISABLE);
 }
 static void atombios_crtc_disable(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_atom_ss ss;
 	int i;
 	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->primary->fb) {
 		int r;
 		struct radeon_framebuffer *radeon_fb;
 		struct radeon_bo *rbo;
 		radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 		rbo = gem_to_radeon_bo(radeon_fb->obj);
 		r = radeon_bo_reserve(rbo, false);
 		if (unlikely(r))
 			DRM_ERROR("failed to reserve rbo before unpin\n");
 		else {
 			radeon_bo_unpin(rbo);
 			radeon_bo_unreserve(rbo);
 		}
 	}
 	/* disable the GRPH */
 	if (ASIC_IS_DCE4(rdev))
 		WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
 	else if (ASIC_IS_AVIVO(rdev))
 		WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
 	if (ASIC_IS_DCE6(rdev))
 		atombios_powergate_crtc(crtc, ATOM_ENABLE);
 	for (i = 0; i < rdev->num_crtc; i++) {
 		if (rdev->mode_info.crtcs[i] &&
 		    rdev->mode_info.crtcs[i]->enabled &&
 		    i != radeon_crtc->crtc_id &&
 		    radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 			/* one other crtc is using this pll don't turn
 			 * off the pll
 			 */
 			goto done;
 		}
 	}
 	switch (radeon_crtc->pll_id) {
 	case ATOM_PPLL1:
 	case ATOM_PPLL2:
 		/* disable the ppll */
 		atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
 					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
 		break;
 	case ATOM_PPLL0:
 		/* disable the ppll */
 		if ((rdev->family == CHIP_ARUBA) ||
 		    (rdev->family == CHIP_BONAIRE) ||
 		    (rdev->family == CHIP_HAWAII))
 			atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
 						  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
 		break;
 	default:
 		break;
 	}
 done:
 	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
 	radeon_crtc->adjusted_clock = 0;
 	radeon_crtc->encoder = NULL;
 	radeon_crtc->connector = NULL;
 }
 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 	.dpms = atombios_crtc_dpms,
 	.mode_fixup = atombios_crtc_mode_fixup,
 	.mode_set = atombios_crtc_mode_set,
 	.mode_set_base = atombios_crtc_set_base,
 	.mode_set_base_atomic = atombios_crtc_set_base_atomic,
 	.prepare = atombios_crtc_prepare,
 	.commit = atombios_crtc_commit,
 	.load_lut = radeon_crtc_load_lut,
 	.disable = atombios_crtc_disable,
 };
 void radeon_atombios_init_crtc(struct drm_device *dev,
 			       struct radeon_crtc *radeon_crtc)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	if (ASIC_IS_DCE4(rdev)) {
 		switch (radeon_crtc->crtc_id) {
 		case 0:
 		default:
 			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
 			break;
 		case 1:
 			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
 			break;
 		case 2:
 			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
 			break;
 		case 3:
 			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
 			break;
 		case 4:
 			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
 			break;
 		case 5:
 			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
 			break;
 		}
 	} else {
 		if (radeon_crtc->crtc_id == 1)
 			radeon_crtc->crtc_offset =
 				AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
 		else
 			radeon_crtc->crtc_offset = 0;
 	}
 	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
 	radeon_crtc->adjusted_clock = 0;
 	radeon_crtc->encoder = NULL;
 	radeon_crtc->connector = NULL;
 	drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);

drivers/gpu/drm/radeon/radeon_asic.c

Diff comments View file @ 6548be5

1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28		28
29	#include <linux/console.h>	29	#include <linux/console.h>
30	#include <drm/drmP.h>	30	#include <drm/drmP.h>
31	#include <drm/drm_crtc_helper.h>	31	#include <drm/drm_crtc_helper.h>
32	#include <drm/radeon_drm.h>	32	#include <drm/radeon_drm.h>
33	#include <linux/vgaarb.h>	33	#include <linux/vgaarb.h>
34	#include <linux/vga_switcheroo.h>	34	#include <linux/vga_switcheroo.h>
35	#include "radeon_reg.h"	35	#include "radeon_reg.h"
36	#include "radeon.h"	36	#include "radeon.h"
37	#include "radeon_asic.h"	37	#include "radeon_asic.h"
38	#include "atom.h"	38	#include "atom.h"
39		39
40	/*	40	/*
41	* Registers accessors functions.	41	* Registers accessors functions.
42	*/	42	*/
43	/**	43	/**
44	* radeon_invalid_rreg - dummy reg read function	44	* radeon_invalid_rreg - dummy reg read function
45	*	45	*
46	* @rdev: radeon device pointer	46	* @rdev: radeon device pointer
47	* @reg: offset of register	47	* @reg: offset of register
48	*	48	*
49	* Dummy register read function. Used for register blocks	49	* Dummy register read function. Used for register blocks
50	* that certain asics don't have (all asics).	50	* that certain asics don't have (all asics).
51	* Returns the value in the register.	51	* Returns the value in the register.
52	*/	52	*/
53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)	53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54	{	54	{
55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);	55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56	BUG_ON(1);	56	BUG_ON(1);
57	return 0;	57	return 0;
58	}	58	}
59		59
60	/**	60	/**
61	* radeon_invalid_wreg - dummy reg write function	61	* radeon_invalid_wreg - dummy reg write function
62	*	62	*
63	* @rdev: radeon device pointer	63	* @rdev: radeon device pointer
64	* @reg: offset of register	64	* @reg: offset of register
65	* @v: value to write to the register	65	* @v: value to write to the register
66	*	66	*
67	* Dummy register read function. Used for register blocks	67	* Dummy register read function. Used for register blocks
68	* that certain asics don't have (all asics).	68	* that certain asics don't have (all asics).
69	*/	69	*/
70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)	70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71	{	71	{
72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",	72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73	reg, v);	73	reg, v);
74	BUG_ON(1);	74	BUG_ON(1);
75	}	75	}
76		76
77	/**	77	/**
78	* radeon_register_accessor_init - sets up the register accessor callbacks	78	* radeon_register_accessor_init - sets up the register accessor callbacks
79	*	79	*
80	* @rdev: radeon device pointer	80	* @rdev: radeon device pointer
81	*	81	*
82	* Sets up the register accessor callbacks for various register	82	* Sets up the register accessor callbacks for various register
83	* apertures. Not all asics have all apertures (all asics).	83	* apertures. Not all asics have all apertures (all asics).
84	*/	84	*/
85	static void radeon_register_accessor_init(struct radeon_device *rdev)	85	static void radeon_register_accessor_init(struct radeon_device *rdev)
86	{	86	{
87	rdev->mc_rreg = &radeon_invalid_rreg;	87	rdev->mc_rreg = &radeon_invalid_rreg;
88	rdev->mc_wreg = &radeon_invalid_wreg;	88	rdev->mc_wreg = &radeon_invalid_wreg;
89	rdev->pll_rreg = &radeon_invalid_rreg;	89	rdev->pll_rreg = &radeon_invalid_rreg;
90	rdev->pll_wreg = &radeon_invalid_wreg;	90	rdev->pll_wreg = &radeon_invalid_wreg;
91	rdev->pciep_rreg = &radeon_invalid_rreg;	91	rdev->pciep_rreg = &radeon_invalid_rreg;
92	rdev->pciep_wreg = &radeon_invalid_wreg;	92	rdev->pciep_wreg = &radeon_invalid_wreg;
93		93
94	/* Don't change order as we are overridding accessor. */	94	/* Don't change order as we are overridding accessor. */
95	if (rdev->family < CHIP_RV515) {	95	if (rdev->family < CHIP_RV515) {
96	rdev->pcie_reg_mask = 0xff;	96	rdev->pcie_reg_mask = 0xff;
97	} else {	97	} else {
98	rdev->pcie_reg_mask = 0x7ff;	98	rdev->pcie_reg_mask = 0x7ff;
99	}	99	}
100	/* FIXME: not sure here */	100	/* FIXME: not sure here */
101	if (rdev->family <= CHIP_R580) {	101	if (rdev->family <= CHIP_R580) {
102	rdev->pll_rreg = &r100_pll_rreg;	102	rdev->pll_rreg = &r100_pll_rreg;
103	rdev->pll_wreg = &r100_pll_wreg;	103	rdev->pll_wreg = &r100_pll_wreg;
104	}	104	}
105	if (rdev->family >= CHIP_R420) {	105	if (rdev->family >= CHIP_R420) {
106	rdev->mc_rreg = &r420_mc_rreg;	106	rdev->mc_rreg = &r420_mc_rreg;
107	rdev->mc_wreg = &r420_mc_wreg;	107	rdev->mc_wreg = &r420_mc_wreg;
108	}	108	}
109	if (rdev->family >= CHIP_RV515) {	109	if (rdev->family >= CHIP_RV515) {
110	rdev->mc_rreg = &rv515_mc_rreg;	110	rdev->mc_rreg = &rv515_mc_rreg;
111	rdev->mc_wreg = &rv515_mc_wreg;	111	rdev->mc_wreg = &rv515_mc_wreg;
112	}	112	}
113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {	113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
114	rdev->mc_rreg = &rs400_mc_rreg;	114	rdev->mc_rreg = &rs400_mc_rreg;
115	rdev->mc_wreg = &rs400_mc_wreg;	115	rdev->mc_wreg = &rs400_mc_wreg;
116	}	116	}
117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {	117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
118	rdev->mc_rreg = &rs690_mc_rreg;	118	rdev->mc_rreg = &rs690_mc_rreg;
119	rdev->mc_wreg = &rs690_mc_wreg;	119	rdev->mc_wreg = &rs690_mc_wreg;
120	}	120	}
121	if (rdev->family == CHIP_RS600) {	121	if (rdev->family == CHIP_RS600) {
122	rdev->mc_rreg = &rs600_mc_rreg;	122	rdev->mc_rreg = &rs600_mc_rreg;
123	rdev->mc_wreg = &rs600_mc_wreg;	123	rdev->mc_wreg = &rs600_mc_wreg;
124	}	124	}
125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {	125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
126	rdev->mc_rreg = &rs780_mc_rreg;	126	rdev->mc_rreg = &rs780_mc_rreg;
127	rdev->mc_wreg = &rs780_mc_wreg;	127	rdev->mc_wreg = &rs780_mc_wreg;
128	}	128	}
129		129
130	if (rdev->family >= CHIP_BONAIRE) {	130	if (rdev->family >= CHIP_BONAIRE) {
131	rdev->pciep_rreg = &cik_pciep_rreg;	131	rdev->pciep_rreg = &cik_pciep_rreg;
132	rdev->pciep_wreg = &cik_pciep_wreg;	132	rdev->pciep_wreg = &cik_pciep_wreg;
133	} else if (rdev->family >= CHIP_R600) {	133	} else if (rdev->family >= CHIP_R600) {
134	rdev->pciep_rreg = &r600_pciep_rreg;	134	rdev->pciep_rreg = &r600_pciep_rreg;
135	rdev->pciep_wreg = &r600_pciep_wreg;	135	rdev->pciep_wreg = &r600_pciep_wreg;
136	}	136	}
137	}	137	}
138		138
139		139
140	/* helper to disable agp */	140	/* helper to disable agp */
141	/**	141	/**
142	* radeon_agp_disable - AGP disable helper function	142	* radeon_agp_disable - AGP disable helper function
143	*	143	*
144	* @rdev: radeon device pointer	144	* @rdev: radeon device pointer
145	*	145	*
146	* Removes AGP flags and changes the gart callbacks on AGP	146	* Removes AGP flags and changes the gart callbacks on AGP
147	* cards when using the internal gart rather than AGP (all asics).	147	* cards when using the internal gart rather than AGP (all asics).
148	*/	148	*/
149	void radeon_agp_disable(struct radeon_device *rdev)	149	void radeon_agp_disable(struct radeon_device *rdev)
150	{	150	{
151	rdev->flags &= ~RADEON_IS_AGP;	151	rdev->flags &= ~RADEON_IS_AGP;
152	if (rdev->family >= CHIP_R600) {	152	if (rdev->family >= CHIP_R600) {
153	DRM_INFO("Forcing AGP to PCIE mode\n");	153	DRM_INFO("Forcing AGP to PCIE mode\n");
154	rdev->flags \|= RADEON_IS_PCIE;	154	rdev->flags \|= RADEON_IS_PCIE;
155	} else if (rdev->family >= CHIP_RV515 \|\|	155	} else if (rdev->family >= CHIP_RV515 \|\|
156	rdev->family == CHIP_RV380 \|\|	156	rdev->family == CHIP_RV380 \|\|
157	rdev->family == CHIP_RV410 \|\|	157	rdev->family == CHIP_RV410 \|\|
158	rdev->family == CHIP_R423) {	158	rdev->family == CHIP_R423) {
159	DRM_INFO("Forcing AGP to PCIE mode\n");	159	DRM_INFO("Forcing AGP to PCIE mode\n");
160	rdev->flags \|= RADEON_IS_PCIE;	160	rdev->flags \|= RADEON_IS_PCIE;
161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;	161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;	162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163	} else {	163	} else {
164	DRM_INFO("Forcing AGP to PCI mode\n");	164	DRM_INFO("Forcing AGP to PCI mode\n");
165	rdev->flags \|= RADEON_IS_PCI;	165	rdev->flags \|= RADEON_IS_PCI;
166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;	166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;	167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168	}	168	}
169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;	169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170	}	170	}
171		171
172	/*	172	/*
173	* ASIC	173	* ASIC
174	*/	174	*/
175		175
176	static struct radeon_asic_ring r100_gfx_ring = {	176	static struct radeon_asic_ring r100_gfx_ring = {
177	.ib_execute = &r100_ring_ib_execute,	177	.ib_execute = &r100_ring_ib_execute,
178	.emit_fence = &r100_fence_ring_emit,	178	.emit_fence = &r100_fence_ring_emit,
179	.emit_semaphore = &r100_semaphore_ring_emit,	179	.emit_semaphore = &r100_semaphore_ring_emit,
180	.cs_parse = &r100_cs_parse,	180	.cs_parse = &r100_cs_parse,
181	.ring_start = &r100_ring_start,	181	.ring_start = &r100_ring_start,
182	.ring_test = &r100_ring_test,	182	.ring_test = &r100_ring_test,
183	.ib_test = &r100_ib_test,	183	.ib_test = &r100_ib_test,
184	.is_lockup = &r100_gpu_is_lockup,	184	.is_lockup = &r100_gpu_is_lockup,
185	.get_rptr = &r100_gfx_get_rptr,	185	.get_rptr = &r100_gfx_get_rptr,
186	.get_wptr = &r100_gfx_get_wptr,	186	.get_wptr = &r100_gfx_get_wptr,
187	.set_wptr = &r100_gfx_set_wptr,	187	.set_wptr = &r100_gfx_set_wptr,
188	};	188	};
189		189
190	static struct radeon_asic r100_asic = {	190	static struct radeon_asic r100_asic = {
191	.init = &r100_init,	191	.init = &r100_init,
192	.fini = &r100_fini,	192	.fini = &r100_fini,
193	.suspend = &r100_suspend,	193	.suspend = &r100_suspend,
194	.resume = &r100_resume,	194	.resume = &r100_resume,
195	.vga_set_state = &r100_vga_set_state,	195	.vga_set_state = &r100_vga_set_state,
196	.asic_reset = &r100_asic_reset,	196	.asic_reset = &r100_asic_reset,
197	.ioctl_wait_idle = NULL,	197	.ioctl_wait_idle = NULL,
198	.gui_idle = &r100_gui_idle,	198	.gui_idle = &r100_gui_idle,
199	.mc_wait_for_idle = &r100_mc_wait_for_idle,	199	.mc_wait_for_idle = &r100_mc_wait_for_idle,
200	.gart = {	200	.gart = {
201	.tlb_flush = &r100_pci_gart_tlb_flush,	201	.tlb_flush = &r100_pci_gart_tlb_flush,
202	.set_page = &r100_pci_gart_set_page,	202	.set_page = &r100_pci_gart_set_page,
203	},	203	},
204	.ring = {	204	.ring = {
205	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring	205	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
206	},	206	},
207	.irq = {	207	.irq = {
208	.set = &r100_irq_set,	208	.set = &r100_irq_set,
209	.process = &r100_irq_process,	209	.process = &r100_irq_process,
210	},	210	},
211	.display = {	211	.display = {
212	.bandwidth_update = &r100_bandwidth_update,	212	.bandwidth_update = &r100_bandwidth_update,
213	.get_vblank_counter = &r100_get_vblank_counter,	213	.get_vblank_counter = &r100_get_vblank_counter,
214	.wait_for_vblank = &r100_wait_for_vblank,	214	.wait_for_vblank = &r100_wait_for_vblank,
215	.set_backlight_level = &radeon_legacy_set_backlight_level,	215	.set_backlight_level = &radeon_legacy_set_backlight_level,
216	.get_backlight_level = &radeon_legacy_get_backlight_level,	216	.get_backlight_level = &radeon_legacy_get_backlight_level,
217	},	217	},
218	.copy = {	218	.copy = {
219	.blit = &r100_copy_blit,	219	.blit = &r100_copy_blit,
220	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	220	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221	.dma = NULL,	221	.dma = NULL,
222	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	222	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223	.copy = &r100_copy_blit,	223	.copy = &r100_copy_blit,
224	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	224	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225	},	225	},
226	.surface = {	226	.surface = {
227	.set_reg = r100_set_surface_reg,	227	.set_reg = r100_set_surface_reg,
228	.clear_reg = r100_clear_surface_reg,	228	.clear_reg = r100_clear_surface_reg,
229	},	229	},
230	.hpd = {	230	.hpd = {
231	.init = &r100_hpd_init,	231	.init = &r100_hpd_init,
232	.fini = &r100_hpd_fini,	232	.fini = &r100_hpd_fini,
233	.sense = &r100_hpd_sense,	233	.sense = &r100_hpd_sense,
234	.set_polarity = &r100_hpd_set_polarity,	234	.set_polarity = &r100_hpd_set_polarity,
235	},	235	},
236	.pm = {	236	.pm = {
237	.misc = &r100_pm_misc,	237	.misc = &r100_pm_misc,
238	.prepare = &r100_pm_prepare,	238	.prepare = &r100_pm_prepare,
239	.finish = &r100_pm_finish,	239	.finish = &r100_pm_finish,
240	.init_profile = &r100_pm_init_profile,	240	.init_profile = &r100_pm_init_profile,
241	.get_dynpm_state = &r100_pm_get_dynpm_state,	241	.get_dynpm_state = &r100_pm_get_dynpm_state,
242	.get_engine_clock = &radeon_legacy_get_engine_clock,	242	.get_engine_clock = &radeon_legacy_get_engine_clock,
243	.set_engine_clock = &radeon_legacy_set_engine_clock,	243	.set_engine_clock = &radeon_legacy_set_engine_clock,
244	.get_memory_clock = &radeon_legacy_get_memory_clock,	244	.get_memory_clock = &radeon_legacy_get_memory_clock,
245	.set_memory_clock = NULL,	245	.set_memory_clock = NULL,
246	.get_pcie_lanes = NULL,	246	.get_pcie_lanes = NULL,
247	.set_pcie_lanes = NULL,	247	.set_pcie_lanes = NULL,
248	.set_clock_gating = &radeon_legacy_set_clock_gating,	248	.set_clock_gating = &radeon_legacy_set_clock_gating,
249	},	249	},
250	.pflip = {	250	.pflip = {
251	.pre_page_flip = &r100_pre_page_flip,	251	.pre_page_flip = &r100_pre_page_flip,
252	.page_flip = &r100_page_flip,	252	.page_flip = &r100_page_flip,
253	.post_page_flip = &r100_post_page_flip,	253	.post_page_flip = &r100_post_page_flip,
254	},	254	},
255	};	255	};
256		256
257	static struct radeon_asic r200_asic = {	257	static struct radeon_asic r200_asic = {
258	.init = &r100_init,	258	.init = &r100_init,
259	.fini = &r100_fini,	259	.fini = &r100_fini,
260	.suspend = &r100_suspend,	260	.suspend = &r100_suspend,
261	.resume = &r100_resume,	261	.resume = &r100_resume,
262	.vga_set_state = &r100_vga_set_state,	262	.vga_set_state = &r100_vga_set_state,
263	.asic_reset = &r100_asic_reset,	263	.asic_reset = &r100_asic_reset,
264	.ioctl_wait_idle = NULL,	264	.ioctl_wait_idle = NULL,
265	.gui_idle = &r100_gui_idle,	265	.gui_idle = &r100_gui_idle,
266	.mc_wait_for_idle = &r100_mc_wait_for_idle,	266	.mc_wait_for_idle = &r100_mc_wait_for_idle,
267	.gart = {	267	.gart = {
268	.tlb_flush = &r100_pci_gart_tlb_flush,	268	.tlb_flush = &r100_pci_gart_tlb_flush,
269	.set_page = &r100_pci_gart_set_page,	269	.set_page = &r100_pci_gart_set_page,
270	},	270	},
271	.ring = {	271	.ring = {
272	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring	272	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
273	},	273	},
274	.irq = {	274	.irq = {
275	.set = &r100_irq_set,	275	.set = &r100_irq_set,
276	.process = &r100_irq_process,	276	.process = &r100_irq_process,
277	},	277	},
278	.display = {	278	.display = {
279	.bandwidth_update = &r100_bandwidth_update,	279	.bandwidth_update = &r100_bandwidth_update,
280	.get_vblank_counter = &r100_get_vblank_counter,	280	.get_vblank_counter = &r100_get_vblank_counter,
281	.wait_for_vblank = &r100_wait_for_vblank,	281	.wait_for_vblank = &r100_wait_for_vblank,
282	.set_backlight_level = &radeon_legacy_set_backlight_level,	282	.set_backlight_level = &radeon_legacy_set_backlight_level,
283	.get_backlight_level = &radeon_legacy_get_backlight_level,	283	.get_backlight_level = &radeon_legacy_get_backlight_level,
284	},	284	},
285	.copy = {	285	.copy = {
286	.blit = &r100_copy_blit,	286	.blit = &r100_copy_blit,
287	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	287	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
288	.dma = &r200_copy_dma,	288	.dma = &r200_copy_dma,
289	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	289	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
290	.copy = &r100_copy_blit,	290	.copy = &r100_copy_blit,
291	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	291	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
292	},	292	},
293	.surface = {	293	.surface = {
294	.set_reg = r100_set_surface_reg,	294	.set_reg = r100_set_surface_reg,
295	.clear_reg = r100_clear_surface_reg,	295	.clear_reg = r100_clear_surface_reg,
296	},	296	},
297	.hpd = {	297	.hpd = {
298	.init = &r100_hpd_init,	298	.init = &r100_hpd_init,
299	.fini = &r100_hpd_fini,	299	.fini = &r100_hpd_fini,
300	.sense = &r100_hpd_sense,	300	.sense = &r100_hpd_sense,
301	.set_polarity = &r100_hpd_set_polarity,	301	.set_polarity = &r100_hpd_set_polarity,
302	},	302	},
303	.pm = {	303	.pm = {
304	.misc = &r100_pm_misc,	304	.misc = &r100_pm_misc,
305	.prepare = &r100_pm_prepare,	305	.prepare = &r100_pm_prepare,
306	.finish = &r100_pm_finish,	306	.finish = &r100_pm_finish,
307	.init_profile = &r100_pm_init_profile,	307	.init_profile = &r100_pm_init_profile,
308	.get_dynpm_state = &r100_pm_get_dynpm_state,	308	.get_dynpm_state = &r100_pm_get_dynpm_state,
309	.get_engine_clock = &radeon_legacy_get_engine_clock,	309	.get_engine_clock = &radeon_legacy_get_engine_clock,
310	.set_engine_clock = &radeon_legacy_set_engine_clock,	310	.set_engine_clock = &radeon_legacy_set_engine_clock,
311	.get_memory_clock = &radeon_legacy_get_memory_clock,	311	.get_memory_clock = &radeon_legacy_get_memory_clock,
312	.set_memory_clock = NULL,	312	.set_memory_clock = NULL,
313	.get_pcie_lanes = NULL,	313	.get_pcie_lanes = NULL,
314	.set_pcie_lanes = NULL,	314	.set_pcie_lanes = NULL,
315	.set_clock_gating = &radeon_legacy_set_clock_gating,	315	.set_clock_gating = &radeon_legacy_set_clock_gating,
316	},	316	},
317	.pflip = {	317	.pflip = {
318	.pre_page_flip = &r100_pre_page_flip,	318	.pre_page_flip = &r100_pre_page_flip,
319	.page_flip = &r100_page_flip,	319	.page_flip = &r100_page_flip,
320	.post_page_flip = &r100_post_page_flip,	320	.post_page_flip = &r100_post_page_flip,
321	},	321	},
322	};	322	};
323		323
324	static struct radeon_asic_ring r300_gfx_ring = {	324	static struct radeon_asic_ring r300_gfx_ring = {
325	.ib_execute = &r100_ring_ib_execute,	325	.ib_execute = &r100_ring_ib_execute,
326	.emit_fence = &r300_fence_ring_emit,	326	.emit_fence = &r300_fence_ring_emit,
327	.emit_semaphore = &r100_semaphore_ring_emit,	327	.emit_semaphore = &r100_semaphore_ring_emit,
328	.cs_parse = &r300_cs_parse,	328	.cs_parse = &r300_cs_parse,
329	.ring_start = &r300_ring_start,	329	.ring_start = &r300_ring_start,
330	.ring_test = &r100_ring_test,	330	.ring_test = &r100_ring_test,
331	.ib_test = &r100_ib_test,	331	.ib_test = &r100_ib_test,
332	.is_lockup = &r100_gpu_is_lockup,	332	.is_lockup = &r100_gpu_is_lockup,
333	.get_rptr = &r100_gfx_get_rptr,	333	.get_rptr = &r100_gfx_get_rptr,
334	.get_wptr = &r100_gfx_get_wptr,	334	.get_wptr = &r100_gfx_get_wptr,
335	.set_wptr = &r100_gfx_set_wptr,	335	.set_wptr = &r100_gfx_set_wptr,
336	};	336	};
337		337
338	static struct radeon_asic r300_asic = {	338	static struct radeon_asic r300_asic = {
339	.init = &r300_init,	339	.init = &r300_init,
340	.fini = &r300_fini,	340	.fini = &r300_fini,
341	.suspend = &r300_suspend,	341	.suspend = &r300_suspend,
342	.resume = &r300_resume,	342	.resume = &r300_resume,
343	.vga_set_state = &r100_vga_set_state,	343	.vga_set_state = &r100_vga_set_state,
344	.asic_reset = &r300_asic_reset,	344	.asic_reset = &r300_asic_reset,
345	.ioctl_wait_idle = NULL,	345	.ioctl_wait_idle = NULL,
346	.gui_idle = &r100_gui_idle,	346	.gui_idle = &r100_gui_idle,
347	.mc_wait_for_idle = &r300_mc_wait_for_idle,	347	.mc_wait_for_idle = &r300_mc_wait_for_idle,
348	.gart = {	348	.gart = {
349	.tlb_flush = &r100_pci_gart_tlb_flush,	349	.tlb_flush = &r100_pci_gart_tlb_flush,
350	.set_page = &r100_pci_gart_set_page,	350	.set_page = &r100_pci_gart_set_page,
351	},	351	},
352	.ring = {	352	.ring = {
353	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	353	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
354	},	354	},
355	.irq = {	355	.irq = {
356	.set = &r100_irq_set,	356	.set = &r100_irq_set,
357	.process = &r100_irq_process,	357	.process = &r100_irq_process,
358	},	358	},
359	.display = {	359	.display = {
360	.bandwidth_update = &r100_bandwidth_update,	360	.bandwidth_update = &r100_bandwidth_update,
361	.get_vblank_counter = &r100_get_vblank_counter,	361	.get_vblank_counter = &r100_get_vblank_counter,
362	.wait_for_vblank = &r100_wait_for_vblank,	362	.wait_for_vblank = &r100_wait_for_vblank,
363	.set_backlight_level = &radeon_legacy_set_backlight_level,	363	.set_backlight_level = &radeon_legacy_set_backlight_level,
364	.get_backlight_level = &radeon_legacy_get_backlight_level,	364	.get_backlight_level = &radeon_legacy_get_backlight_level,
365	},	365	},
366	.copy = {	366	.copy = {
367	.blit = &r100_copy_blit,	367	.blit = &r100_copy_blit,
368	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	368	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369	.dma = &r200_copy_dma,	369	.dma = &r200_copy_dma,
370	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	370	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371	.copy = &r100_copy_blit,	371	.copy = &r100_copy_blit,
372	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	372	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
373	},	373	},
374	.surface = {	374	.surface = {
375	.set_reg = r100_set_surface_reg,	375	.set_reg = r100_set_surface_reg,
376	.clear_reg = r100_clear_surface_reg,	376	.clear_reg = r100_clear_surface_reg,
377	},	377	},
378	.hpd = {	378	.hpd = {
379	.init = &r100_hpd_init,	379	.init = &r100_hpd_init,
380	.fini = &r100_hpd_fini,	380	.fini = &r100_hpd_fini,
381	.sense = &r100_hpd_sense,	381	.sense = &r100_hpd_sense,
382	.set_polarity = &r100_hpd_set_polarity,	382	.set_polarity = &r100_hpd_set_polarity,
383	},	383	},
384	.pm = {	384	.pm = {
385	.misc = &r100_pm_misc,	385	.misc = &r100_pm_misc,
386	.prepare = &r100_pm_prepare,	386	.prepare = &r100_pm_prepare,
387	.finish = &r100_pm_finish,	387	.finish = &r100_pm_finish,
388	.init_profile = &r100_pm_init_profile,	388	.init_profile = &r100_pm_init_profile,
389	.get_dynpm_state = &r100_pm_get_dynpm_state,	389	.get_dynpm_state = &r100_pm_get_dynpm_state,
390	.get_engine_clock = &radeon_legacy_get_engine_clock,	390	.get_engine_clock = &radeon_legacy_get_engine_clock,
391	.set_engine_clock = &radeon_legacy_set_engine_clock,	391	.set_engine_clock = &radeon_legacy_set_engine_clock,
392	.get_memory_clock = &radeon_legacy_get_memory_clock,	392	.get_memory_clock = &radeon_legacy_get_memory_clock,
393	.set_memory_clock = NULL,	393	.set_memory_clock = NULL,
394	.get_pcie_lanes = &rv370_get_pcie_lanes,	394	.get_pcie_lanes = &rv370_get_pcie_lanes,
395	.set_pcie_lanes = &rv370_set_pcie_lanes,	395	.set_pcie_lanes = &rv370_set_pcie_lanes,
396	.set_clock_gating = &radeon_legacy_set_clock_gating,	396	.set_clock_gating = &radeon_legacy_set_clock_gating,
397	},	397	},
398	.pflip = {	398	.pflip = {
399	.pre_page_flip = &r100_pre_page_flip,	399	.pre_page_flip = &r100_pre_page_flip,
400	.page_flip = &r100_page_flip,	400	.page_flip = &r100_page_flip,
401	.post_page_flip = &r100_post_page_flip,	401	.post_page_flip = &r100_post_page_flip,
402	},	402	},
403	};	403	};
404		404
405	static struct radeon_asic r300_asic_pcie = {	405	static struct radeon_asic r300_asic_pcie = {
406	.init = &r300_init,	406	.init = &r300_init,
407	.fini = &r300_fini,	407	.fini = &r300_fini,
408	.suspend = &r300_suspend,	408	.suspend = &r300_suspend,
409	.resume = &r300_resume,	409	.resume = &r300_resume,
410	.vga_set_state = &r100_vga_set_state,	410	.vga_set_state = &r100_vga_set_state,
411	.asic_reset = &r300_asic_reset,	411	.asic_reset = &r300_asic_reset,
412	.ioctl_wait_idle = NULL,	412	.ioctl_wait_idle = NULL,
413	.gui_idle = &r100_gui_idle,	413	.gui_idle = &r100_gui_idle,
414	.mc_wait_for_idle = &r300_mc_wait_for_idle,	414	.mc_wait_for_idle = &r300_mc_wait_for_idle,
415	.gart = {	415	.gart = {
416	.tlb_flush = &rv370_pcie_gart_tlb_flush,	416	.tlb_flush = &rv370_pcie_gart_tlb_flush,
417	.set_page = &rv370_pcie_gart_set_page,	417	.set_page = &rv370_pcie_gart_set_page,
418	},	418	},
419	.ring = {	419	.ring = {
420	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	420	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
421	},	421	},
422	.irq = {	422	.irq = {
423	.set = &r100_irq_set,	423	.set = &r100_irq_set,
424	.process = &r100_irq_process,	424	.process = &r100_irq_process,
425	},	425	},
426	.display = {	426	.display = {
427	.bandwidth_update = &r100_bandwidth_update,	427	.bandwidth_update = &r100_bandwidth_update,
428	.get_vblank_counter = &r100_get_vblank_counter,	428	.get_vblank_counter = &r100_get_vblank_counter,
429	.wait_for_vblank = &r100_wait_for_vblank,	429	.wait_for_vblank = &r100_wait_for_vblank,
430	.set_backlight_level = &radeon_legacy_set_backlight_level,	430	.set_backlight_level = &radeon_legacy_set_backlight_level,
431	.get_backlight_level = &radeon_legacy_get_backlight_level,	431	.get_backlight_level = &radeon_legacy_get_backlight_level,
432	},	432	},
433	.copy = {	433	.copy = {
434	.blit = &r100_copy_blit,	434	.blit = &r100_copy_blit,
435	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	435	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
436	.dma = &r200_copy_dma,	436	.dma = &r200_copy_dma,
437	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	437	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438	.copy = &r100_copy_blit,	438	.copy = &r100_copy_blit,
439	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	439	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
440	},	440	},
441	.surface = {	441	.surface = {
442	.set_reg = r100_set_surface_reg,	442	.set_reg = r100_set_surface_reg,
443	.clear_reg = r100_clear_surface_reg,	443	.clear_reg = r100_clear_surface_reg,
444	},	444	},
445	.hpd = {	445	.hpd = {
446	.init = &r100_hpd_init,	446	.init = &r100_hpd_init,
447	.fini = &r100_hpd_fini,	447	.fini = &r100_hpd_fini,
448	.sense = &r100_hpd_sense,	448	.sense = &r100_hpd_sense,
449	.set_polarity = &r100_hpd_set_polarity,	449	.set_polarity = &r100_hpd_set_polarity,
450	},	450	},
451	.pm = {	451	.pm = {
452	.misc = &r100_pm_misc,	452	.misc = &r100_pm_misc,
453	.prepare = &r100_pm_prepare,	453	.prepare = &r100_pm_prepare,
454	.finish = &r100_pm_finish,	454	.finish = &r100_pm_finish,
455	.init_profile = &r100_pm_init_profile,	455	.init_profile = &r100_pm_init_profile,
456	.get_dynpm_state = &r100_pm_get_dynpm_state,	456	.get_dynpm_state = &r100_pm_get_dynpm_state,
457	.get_engine_clock = &radeon_legacy_get_engine_clock,	457	.get_engine_clock = &radeon_legacy_get_engine_clock,
458	.set_engine_clock = &radeon_legacy_set_engine_clock,	458	.set_engine_clock = &radeon_legacy_set_engine_clock,
459	.get_memory_clock = &radeon_legacy_get_memory_clock,	459	.get_memory_clock = &radeon_legacy_get_memory_clock,
460	.set_memory_clock = NULL,	460	.set_memory_clock = NULL,
461	.get_pcie_lanes = &rv370_get_pcie_lanes,	461	.get_pcie_lanes = &rv370_get_pcie_lanes,
462	.set_pcie_lanes = &rv370_set_pcie_lanes,	462	.set_pcie_lanes = &rv370_set_pcie_lanes,
463	.set_clock_gating = &radeon_legacy_set_clock_gating,	463	.set_clock_gating = &radeon_legacy_set_clock_gating,
464	},	464	},
465	.pflip = {	465	.pflip = {
466	.pre_page_flip = &r100_pre_page_flip,	466	.pre_page_flip = &r100_pre_page_flip,
467	.page_flip = &r100_page_flip,	467	.page_flip = &r100_page_flip,
468	.post_page_flip = &r100_post_page_flip,	468	.post_page_flip = &r100_post_page_flip,
469	},	469	},
470	};	470	};
471		471
472	static struct radeon_asic r420_asic = {	472	static struct radeon_asic r420_asic = {
473	.init = &r420_init,	473	.init = &r420_init,
474	.fini = &r420_fini,	474	.fini = &r420_fini,
475	.suspend = &r420_suspend,	475	.suspend = &r420_suspend,
476	.resume = &r420_resume,	476	.resume = &r420_resume,
477	.vga_set_state = &r100_vga_set_state,	477	.vga_set_state = &r100_vga_set_state,
478	.asic_reset = &r300_asic_reset,	478	.asic_reset = &r300_asic_reset,
479	.ioctl_wait_idle = NULL,	479	.ioctl_wait_idle = NULL,
480	.gui_idle = &r100_gui_idle,	480	.gui_idle = &r100_gui_idle,
481	.mc_wait_for_idle = &r300_mc_wait_for_idle,	481	.mc_wait_for_idle = &r300_mc_wait_for_idle,
482	.gart = {	482	.gart = {
483	.tlb_flush = &rv370_pcie_gart_tlb_flush,	483	.tlb_flush = &rv370_pcie_gart_tlb_flush,
484	.set_page = &rv370_pcie_gart_set_page,	484	.set_page = &rv370_pcie_gart_set_page,
485	},	485	},
486	.ring = {	486	.ring = {
487	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	487	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
488	},	488	},
489	.irq = {	489	.irq = {
490	.set = &r100_irq_set,	490	.set = &r100_irq_set,
491	.process = &r100_irq_process,	491	.process = &r100_irq_process,
492	},	492	},
493	.display = {	493	.display = {
494	.bandwidth_update = &r100_bandwidth_update,	494	.bandwidth_update = &r100_bandwidth_update,
495	.get_vblank_counter = &r100_get_vblank_counter,	495	.get_vblank_counter = &r100_get_vblank_counter,
496	.wait_for_vblank = &r100_wait_for_vblank,	496	.wait_for_vblank = &r100_wait_for_vblank,
497	.set_backlight_level = &atombios_set_backlight_level,	497	.set_backlight_level = &atombios_set_backlight_level,
498	.get_backlight_level = &atombios_get_backlight_level,	498	.get_backlight_level = &atombios_get_backlight_level,
499	},	499	},
500	.copy = {	500	.copy = {
501	.blit = &r100_copy_blit,	501	.blit = &r100_copy_blit,
502	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	502	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503	.dma = &r200_copy_dma,	503	.dma = &r200_copy_dma,
504	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	504	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505	.copy = &r100_copy_blit,	505	.copy = &r100_copy_blit,
506	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	506	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
507	},	507	},
508	.surface = {	508	.surface = {
509	.set_reg = r100_set_surface_reg,	509	.set_reg = r100_set_surface_reg,
510	.clear_reg = r100_clear_surface_reg,	510	.clear_reg = r100_clear_surface_reg,
511	},	511	},
512	.hpd = {	512	.hpd = {
513	.init = &r100_hpd_init,	513	.init = &r100_hpd_init,
514	.fini = &r100_hpd_fini,	514	.fini = &r100_hpd_fini,
515	.sense = &r100_hpd_sense,	515	.sense = &r100_hpd_sense,
516	.set_polarity = &r100_hpd_set_polarity,	516	.set_polarity = &r100_hpd_set_polarity,
517	},	517	},
518	.pm = {	518	.pm = {
519	.misc = &r100_pm_misc,	519	.misc = &r100_pm_misc,
520	.prepare = &r100_pm_prepare,	520	.prepare = &r100_pm_prepare,
521	.finish = &r100_pm_finish,	521	.finish = &r100_pm_finish,
522	.init_profile = &r420_pm_init_profile,	522	.init_profile = &r420_pm_init_profile,
523	.get_dynpm_state = &r100_pm_get_dynpm_state,	523	.get_dynpm_state = &r100_pm_get_dynpm_state,
524	.get_engine_clock = &radeon_atom_get_engine_clock,	524	.get_engine_clock = &radeon_atom_get_engine_clock,
525	.set_engine_clock = &radeon_atom_set_engine_clock,	525	.set_engine_clock = &radeon_atom_set_engine_clock,
526	.get_memory_clock = &radeon_atom_get_memory_clock,	526	.get_memory_clock = &radeon_atom_get_memory_clock,
527	.set_memory_clock = &radeon_atom_set_memory_clock,	527	.set_memory_clock = &radeon_atom_set_memory_clock,
528	.get_pcie_lanes = &rv370_get_pcie_lanes,	528	.get_pcie_lanes = &rv370_get_pcie_lanes,
529	.set_pcie_lanes = &rv370_set_pcie_lanes,	529	.set_pcie_lanes = &rv370_set_pcie_lanes,
530	.set_clock_gating = &radeon_atom_set_clock_gating,	530	.set_clock_gating = &radeon_atom_set_clock_gating,
531	},	531	},
532	.pflip = {	532	.pflip = {
533	.pre_page_flip = &r100_pre_page_flip,	533	.pre_page_flip = &r100_pre_page_flip,
534	.page_flip = &r100_page_flip,	534	.page_flip = &r100_page_flip,
535	.post_page_flip = &r100_post_page_flip,	535	.post_page_flip = &r100_post_page_flip,
536	},	536	},
537	};	537	};
538		538
539	static struct radeon_asic rs400_asic = {	539	static struct radeon_asic rs400_asic = {
540	.init = &rs400_init,	540	.init = &rs400_init,
541	.fini = &rs400_fini,	541	.fini = &rs400_fini,
542	.suspend = &rs400_suspend,	542	.suspend = &rs400_suspend,
543	.resume = &rs400_resume,	543	.resume = &rs400_resume,
544	.vga_set_state = &r100_vga_set_state,	544	.vga_set_state = &r100_vga_set_state,
545	.asic_reset = &r300_asic_reset,	545	.asic_reset = &r300_asic_reset,
546	.ioctl_wait_idle = NULL,	546	.ioctl_wait_idle = NULL,
547	.gui_idle = &r100_gui_idle,	547	.gui_idle = &r100_gui_idle,
548	.mc_wait_for_idle = &rs400_mc_wait_for_idle,	548	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
549	.gart = {	549	.gart = {
550	.tlb_flush = &rs400_gart_tlb_flush,	550	.tlb_flush = &rs400_gart_tlb_flush,
551	.set_page = &rs400_gart_set_page,	551	.set_page = &rs400_gart_set_page,
552	},	552	},
553	.ring = {	553	.ring = {
554	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	554	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
555	},	555	},
556	.irq = {	556	.irq = {
557	.set = &r100_irq_set,	557	.set = &r100_irq_set,
558	.process = &r100_irq_process,	558	.process = &r100_irq_process,
559	},	559	},
560	.display = {	560	.display = {
561	.bandwidth_update = &r100_bandwidth_update,	561	.bandwidth_update = &r100_bandwidth_update,
562	.get_vblank_counter = &r100_get_vblank_counter,	562	.get_vblank_counter = &r100_get_vblank_counter,
563	.wait_for_vblank = &r100_wait_for_vblank,	563	.wait_for_vblank = &r100_wait_for_vblank,
564	.set_backlight_level = &radeon_legacy_set_backlight_level,	564	.set_backlight_level = &radeon_legacy_set_backlight_level,
565	.get_backlight_level = &radeon_legacy_get_backlight_level,	565	.get_backlight_level = &radeon_legacy_get_backlight_level,
566	},	566	},
567	.copy = {	567	.copy = {
568	.blit = &r100_copy_blit,	568	.blit = &r100_copy_blit,
569	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	569	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
570	.dma = &r200_copy_dma,	570	.dma = &r200_copy_dma,
571	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	571	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
572	.copy = &r100_copy_blit,	572	.copy = &r100_copy_blit,
573	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	573	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
574	},	574	},
575	.surface = {	575	.surface = {
576	.set_reg = r100_set_surface_reg,	576	.set_reg = r100_set_surface_reg,
577	.clear_reg = r100_clear_surface_reg,	577	.clear_reg = r100_clear_surface_reg,
578	},	578	},
579	.hpd = {	579	.hpd = {
580	.init = &r100_hpd_init,	580	.init = &r100_hpd_init,
581	.fini = &r100_hpd_fini,	581	.fini = &r100_hpd_fini,
582	.sense = &r100_hpd_sense,	582	.sense = &r100_hpd_sense,
583	.set_polarity = &r100_hpd_set_polarity,	583	.set_polarity = &r100_hpd_set_polarity,
584	},	584	},
585	.pm = {	585	.pm = {
586	.misc = &r100_pm_misc,	586	.misc = &r100_pm_misc,
587	.prepare = &r100_pm_prepare,	587	.prepare = &r100_pm_prepare,
588	.finish = &r100_pm_finish,	588	.finish = &r100_pm_finish,
589	.init_profile = &r100_pm_init_profile,	589	.init_profile = &r100_pm_init_profile,
590	.get_dynpm_state = &r100_pm_get_dynpm_state,	590	.get_dynpm_state = &r100_pm_get_dynpm_state,
591	.get_engine_clock = &radeon_legacy_get_engine_clock,	591	.get_engine_clock = &radeon_legacy_get_engine_clock,
592	.set_engine_clock = &radeon_legacy_set_engine_clock,	592	.set_engine_clock = &radeon_legacy_set_engine_clock,
593	.get_memory_clock = &radeon_legacy_get_memory_clock,	593	.get_memory_clock = &radeon_legacy_get_memory_clock,
594	.set_memory_clock = NULL,	594	.set_memory_clock = NULL,
595	.get_pcie_lanes = NULL,	595	.get_pcie_lanes = NULL,
596	.set_pcie_lanes = NULL,	596	.set_pcie_lanes = NULL,
597	.set_clock_gating = &radeon_legacy_set_clock_gating,	597	.set_clock_gating = &radeon_legacy_set_clock_gating,
598	},	598	},
599	.pflip = {	599	.pflip = {
600	.pre_page_flip = &r100_pre_page_flip,	600	.pre_page_flip = &r100_pre_page_flip,
601	.page_flip = &r100_page_flip,	601	.page_flip = &r100_page_flip,
602	.post_page_flip = &r100_post_page_flip,	602	.post_page_flip = &r100_post_page_flip,
603	},	603	},
604	};	604	};
605		605
606	static struct radeon_asic rs600_asic = {	606	static struct radeon_asic rs600_asic = {
607	.init = &rs600_init,	607	.init = &rs600_init,
608	.fini = &rs600_fini,	608	.fini = &rs600_fini,
609	.suspend = &rs600_suspend,	609	.suspend = &rs600_suspend,
610	.resume = &rs600_resume,	610	.resume = &rs600_resume,
611	.vga_set_state = &r100_vga_set_state,	611	.vga_set_state = &r100_vga_set_state,
612	.asic_reset = &rs600_asic_reset,	612	.asic_reset = &rs600_asic_reset,
613	.ioctl_wait_idle = NULL,	613	.ioctl_wait_idle = NULL,
614	.gui_idle = &r100_gui_idle,	614	.gui_idle = &r100_gui_idle,
615	.mc_wait_for_idle = &rs600_mc_wait_for_idle,	615	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
616	.gart = {	616	.gart = {
617	.tlb_flush = &rs600_gart_tlb_flush,	617	.tlb_flush = &rs600_gart_tlb_flush,
618	.set_page = &rs600_gart_set_page,	618	.set_page = &rs600_gart_set_page,
619	},	619	},
620	.ring = {	620	.ring = {
621	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	621	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
622	},	622	},
623	.irq = {	623	.irq = {
624	.set = &rs600_irq_set,	624	.set = &rs600_irq_set,
625	.process = &rs600_irq_process,	625	.process = &rs600_irq_process,
626	},	626	},
627	.display = {	627	.display = {
628	.bandwidth_update = &rs600_bandwidth_update,	628	.bandwidth_update = &rs600_bandwidth_update,
629	.get_vblank_counter = &rs600_get_vblank_counter,	629	.get_vblank_counter = &rs600_get_vblank_counter,
630	.wait_for_vblank = &avivo_wait_for_vblank,	630	.wait_for_vblank = &avivo_wait_for_vblank,
631	.set_backlight_level = &atombios_set_backlight_level,	631	.set_backlight_level = &atombios_set_backlight_level,
632	.get_backlight_level = &atombios_get_backlight_level,	632	.get_backlight_level = &atombios_get_backlight_level,
633	.hdmi_enable = &r600_hdmi_enable,	633	.hdmi_enable = &r600_hdmi_enable,
634	.hdmi_setmode = &r600_hdmi_setmode,	634	.hdmi_setmode = &r600_hdmi_setmode,
635	},	635	},
636	.copy = {	636	.copy = {
637	.blit = &r100_copy_blit,	637	.blit = &r100_copy_blit,
638	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	638	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639	.dma = &r200_copy_dma,	639	.dma = &r200_copy_dma,
640	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	640	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
641	.copy = &r100_copy_blit,	641	.copy = &r100_copy_blit,
642	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	642	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
643	},	643	},
644	.surface = {	644	.surface = {
645	.set_reg = r100_set_surface_reg,	645	.set_reg = r100_set_surface_reg,
646	.clear_reg = r100_clear_surface_reg,	646	.clear_reg = r100_clear_surface_reg,
647	},	647	},
648	.hpd = {	648	.hpd = {
649	.init = &rs600_hpd_init,	649	.init = &rs600_hpd_init,
650	.fini = &rs600_hpd_fini,	650	.fini = &rs600_hpd_fini,
651	.sense = &rs600_hpd_sense,	651	.sense = &rs600_hpd_sense,
652	.set_polarity = &rs600_hpd_set_polarity,	652	.set_polarity = &rs600_hpd_set_polarity,
653	},	653	},
654	.pm = {	654	.pm = {
655	.misc = &rs600_pm_misc,	655	.misc = &rs600_pm_misc,
656	.prepare = &rs600_pm_prepare,	656	.prepare = &rs600_pm_prepare,
657	.finish = &rs600_pm_finish,	657	.finish = &rs600_pm_finish,
658	.init_profile = &r420_pm_init_profile,	658	.init_profile = &r420_pm_init_profile,
659	.get_dynpm_state = &r100_pm_get_dynpm_state,	659	.get_dynpm_state = &r100_pm_get_dynpm_state,
660	.get_engine_clock = &radeon_atom_get_engine_clock,	660	.get_engine_clock = &radeon_atom_get_engine_clock,
661	.set_engine_clock = &radeon_atom_set_engine_clock,	661	.set_engine_clock = &radeon_atom_set_engine_clock,
662	.get_memory_clock = &radeon_atom_get_memory_clock,	662	.get_memory_clock = &radeon_atom_get_memory_clock,
663	.set_memory_clock = &radeon_atom_set_memory_clock,	663	.set_memory_clock = &radeon_atom_set_memory_clock,
664	.get_pcie_lanes = NULL,	664	.get_pcie_lanes = NULL,
665	.set_pcie_lanes = NULL,	665	.set_pcie_lanes = NULL,
666	.set_clock_gating = &radeon_atom_set_clock_gating,	666	.set_clock_gating = &radeon_atom_set_clock_gating,
667	},	667	},
668	.pflip = {	668	.pflip = {
669	.pre_page_flip = &rs600_pre_page_flip,	669	.pre_page_flip = &rs600_pre_page_flip,
670	.page_flip = &rs600_page_flip,	670	.page_flip = &rs600_page_flip,
671	.post_page_flip = &rs600_post_page_flip,	671	.post_page_flip = &rs600_post_page_flip,
672	},	672	},
673	};	673	};
674		674
675	static struct radeon_asic rs690_asic = {	675	static struct radeon_asic rs690_asic = {
676	.init = &rs690_init,	676	.init = &rs690_init,
677	.fini = &rs690_fini,	677	.fini = &rs690_fini,
678	.suspend = &rs690_suspend,	678	.suspend = &rs690_suspend,
679	.resume = &rs690_resume,	679	.resume = &rs690_resume,
680	.vga_set_state = &r100_vga_set_state,	680	.vga_set_state = &r100_vga_set_state,
681	.asic_reset = &rs600_asic_reset,	681	.asic_reset = &rs600_asic_reset,
682	.ioctl_wait_idle = NULL,	682	.ioctl_wait_idle = NULL,
683	.gui_idle = &r100_gui_idle,	683	.gui_idle = &r100_gui_idle,
684	.mc_wait_for_idle = &rs690_mc_wait_for_idle,	684	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
685	.gart = {	685	.gart = {
686	.tlb_flush = &rs400_gart_tlb_flush,	686	.tlb_flush = &rs400_gart_tlb_flush,
687	.set_page = &rs400_gart_set_page,	687	.set_page = &rs400_gart_set_page,
688	},	688	},
689	.ring = {	689	.ring = {
690	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	690	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
691	},	691	},
692	.irq = {	692	.irq = {
693	.set = &rs600_irq_set,	693	.set = &rs600_irq_set,
694	.process = &rs600_irq_process,	694	.process = &rs600_irq_process,
695	},	695	},
696	.display = {	696	.display = {
697	.get_vblank_counter = &rs600_get_vblank_counter,	697	.get_vblank_counter = &rs600_get_vblank_counter,
698	.bandwidth_update = &rs690_bandwidth_update,	698	.bandwidth_update = &rs690_bandwidth_update,
699	.wait_for_vblank = &avivo_wait_for_vblank,	699	.wait_for_vblank = &avivo_wait_for_vblank,
700	.set_backlight_level = &atombios_set_backlight_level,	700	.set_backlight_level = &atombios_set_backlight_level,
701	.get_backlight_level = &atombios_get_backlight_level,	701	.get_backlight_level = &atombios_get_backlight_level,
702	.hdmi_enable = &r600_hdmi_enable,	702	.hdmi_enable = &r600_hdmi_enable,
703	.hdmi_setmode = &r600_hdmi_setmode,	703	.hdmi_setmode = &r600_hdmi_setmode,
704	},	704	},
705	.copy = {	705	.copy = {
706	.blit = &r100_copy_blit,	706	.blit = &r100_copy_blit,
707	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	707	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
708	.dma = &r200_copy_dma,	708	.dma = &r200_copy_dma,
709	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	709	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
710	.copy = &r200_copy_dma,	710	.copy = &r200_copy_dma,
711	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	711	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
712	},	712	},
713	.surface = {	713	.surface = {
714	.set_reg = r100_set_surface_reg,	714	.set_reg = r100_set_surface_reg,
715	.clear_reg = r100_clear_surface_reg,	715	.clear_reg = r100_clear_surface_reg,
716	},	716	},
717	.hpd = {	717	.hpd = {
718	.init = &rs600_hpd_init,	718	.init = &rs600_hpd_init,
719	.fini = &rs600_hpd_fini,	719	.fini = &rs600_hpd_fini,
720	.sense = &rs600_hpd_sense,	720	.sense = &rs600_hpd_sense,
721	.set_polarity = &rs600_hpd_set_polarity,	721	.set_polarity = &rs600_hpd_set_polarity,
722	},	722	},
723	.pm = {	723	.pm = {
724	.misc = &rs600_pm_misc,	724	.misc = &rs600_pm_misc,
725	.prepare = &rs600_pm_prepare,	725	.prepare = &rs600_pm_prepare,
726	.finish = &rs600_pm_finish,	726	.finish = &rs600_pm_finish,
727	.init_profile = &r420_pm_init_profile,	727	.init_profile = &r420_pm_init_profile,
728	.get_dynpm_state = &r100_pm_get_dynpm_state,	728	.get_dynpm_state = &r100_pm_get_dynpm_state,
729	.get_engine_clock = &radeon_atom_get_engine_clock,	729	.get_engine_clock = &radeon_atom_get_engine_clock,
730	.set_engine_clock = &radeon_atom_set_engine_clock,	730	.set_engine_clock = &radeon_atom_set_engine_clock,
731	.get_memory_clock = &radeon_atom_get_memory_clock,	731	.get_memory_clock = &radeon_atom_get_memory_clock,
732	.set_memory_clock = &radeon_atom_set_memory_clock,	732	.set_memory_clock = &radeon_atom_set_memory_clock,
733	.get_pcie_lanes = NULL,	733	.get_pcie_lanes = NULL,
734	.set_pcie_lanes = NULL,	734	.set_pcie_lanes = NULL,
735	.set_clock_gating = &radeon_atom_set_clock_gating,	735	.set_clock_gating = &radeon_atom_set_clock_gating,
736	},	736	},
737	.pflip = {	737	.pflip = {
738	.pre_page_flip = &rs600_pre_page_flip,	738	.pre_page_flip = &rs600_pre_page_flip,
739	.page_flip = &rs600_page_flip,	739	.page_flip = &rs600_page_flip,
740	.post_page_flip = &rs600_post_page_flip,	740	.post_page_flip = &rs600_post_page_flip,
741	},	741	},
742	};	742	};
743		743
744	static struct radeon_asic rv515_asic = {	744	static struct radeon_asic rv515_asic = {
745	.init = &rv515_init,	745	.init = &rv515_init,
746	.fini = &rv515_fini,	746	.fini = &rv515_fini,
747	.suspend = &rv515_suspend,	747	.suspend = &rv515_suspend,
748	.resume = &rv515_resume,	748	.resume = &rv515_resume,
749	.vga_set_state = &r100_vga_set_state,	749	.vga_set_state = &r100_vga_set_state,
750	.asic_reset = &rs600_asic_reset,	750	.asic_reset = &rs600_asic_reset,
751	.ioctl_wait_idle = NULL,	751	.ioctl_wait_idle = NULL,
752	.gui_idle = &r100_gui_idle,	752	.gui_idle = &r100_gui_idle,
753	.mc_wait_for_idle = &rv515_mc_wait_for_idle,	753	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
754	.gart = {	754	.gart = {
755	.tlb_flush = &rv370_pcie_gart_tlb_flush,	755	.tlb_flush = &rv370_pcie_gart_tlb_flush,
756	.set_page = &rv370_pcie_gart_set_page,	756	.set_page = &rv370_pcie_gart_set_page,
757	},	757	},
758	.ring = {	758	.ring = {
759	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	759	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
760	},	760	},
761	.irq = {	761	.irq = {
762	.set = &rs600_irq_set,	762	.set = &rs600_irq_set,
763	.process = &rs600_irq_process,	763	.process = &rs600_irq_process,
764	},	764	},
765	.display = {	765	.display = {
766	.get_vblank_counter = &rs600_get_vblank_counter,	766	.get_vblank_counter = &rs600_get_vblank_counter,
767	.bandwidth_update = &rv515_bandwidth_update,	767	.bandwidth_update = &rv515_bandwidth_update,
768	.wait_for_vblank = &avivo_wait_for_vblank,	768	.wait_for_vblank = &avivo_wait_for_vblank,
769	.set_backlight_level = &atombios_set_backlight_level,	769	.set_backlight_level = &atombios_set_backlight_level,
770	.get_backlight_level = &atombios_get_backlight_level,	770	.get_backlight_level = &atombios_get_backlight_level,
771	},	771	},
772	.copy = {	772	.copy = {
773	.blit = &r100_copy_blit,	773	.blit = &r100_copy_blit,
774	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	774	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775	.dma = &r200_copy_dma,	775	.dma = &r200_copy_dma,
776	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	776	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777	.copy = &r100_copy_blit,	777	.copy = &r100_copy_blit,
778	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	778	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779	},	779	},
780	.surface = {	780	.surface = {
781	.set_reg = r100_set_surface_reg,	781	.set_reg = r100_set_surface_reg,
782	.clear_reg = r100_clear_surface_reg,	782	.clear_reg = r100_clear_surface_reg,
783	},	783	},
784	.hpd = {	784	.hpd = {
785	.init = &rs600_hpd_init,	785	.init = &rs600_hpd_init,
786	.fini = &rs600_hpd_fini,	786	.fini = &rs600_hpd_fini,
787	.sense = &rs600_hpd_sense,	787	.sense = &rs600_hpd_sense,
788	.set_polarity = &rs600_hpd_set_polarity,	788	.set_polarity = &rs600_hpd_set_polarity,
789	},	789	},
790	.pm = {	790	.pm = {
791	.misc = &rs600_pm_misc,	791	.misc = &rs600_pm_misc,
792	.prepare = &rs600_pm_prepare,	792	.prepare = &rs600_pm_prepare,
793	.finish = &rs600_pm_finish,	793	.finish = &rs600_pm_finish,
794	.init_profile = &r420_pm_init_profile,	794	.init_profile = &r420_pm_init_profile,
795	.get_dynpm_state = &r100_pm_get_dynpm_state,	795	.get_dynpm_state = &r100_pm_get_dynpm_state,
796	.get_engine_clock = &radeon_atom_get_engine_clock,	796	.get_engine_clock = &radeon_atom_get_engine_clock,
797	.set_engine_clock = &radeon_atom_set_engine_clock,	797	.set_engine_clock = &radeon_atom_set_engine_clock,
798	.get_memory_clock = &radeon_atom_get_memory_clock,	798	.get_memory_clock = &radeon_atom_get_memory_clock,
799	.set_memory_clock = &radeon_atom_set_memory_clock,	799	.set_memory_clock = &radeon_atom_set_memory_clock,
800	.get_pcie_lanes = &rv370_get_pcie_lanes,	800	.get_pcie_lanes = &rv370_get_pcie_lanes,
801	.set_pcie_lanes = &rv370_set_pcie_lanes,	801	.set_pcie_lanes = &rv370_set_pcie_lanes,
802	.set_clock_gating = &radeon_atom_set_clock_gating,	802	.set_clock_gating = &radeon_atom_set_clock_gating,
803	},	803	},
804	.pflip = {	804	.pflip = {
805	.pre_page_flip = &rs600_pre_page_flip,	805	.pre_page_flip = &rs600_pre_page_flip,
806	.page_flip = &rs600_page_flip,	806	.page_flip = &rs600_page_flip,
807	.post_page_flip = &rs600_post_page_flip,	807	.post_page_flip = &rs600_post_page_flip,
808	},	808	},
809	};	809	};
810		810
811	static struct radeon_asic r520_asic = {	811	static struct radeon_asic r520_asic = {
812	.init = &r520_init,	812	.init = &r520_init,
813	.fini = &rv515_fini,	813	.fini = &rv515_fini,
814	.suspend = &rv515_suspend,	814	.suspend = &rv515_suspend,
815	.resume = &r520_resume,	815	.resume = &r520_resume,
816	.vga_set_state = &r100_vga_set_state,	816	.vga_set_state = &r100_vga_set_state,
817	.asic_reset = &rs600_asic_reset,	817	.asic_reset = &rs600_asic_reset,
818	.ioctl_wait_idle = NULL,	818	.ioctl_wait_idle = NULL,
819	.gui_idle = &r100_gui_idle,	819	.gui_idle = &r100_gui_idle,
820	.mc_wait_for_idle = &r520_mc_wait_for_idle,	820	.mc_wait_for_idle = &r520_mc_wait_for_idle,
821	.gart = {	821	.gart = {
822	.tlb_flush = &rv370_pcie_gart_tlb_flush,	822	.tlb_flush = &rv370_pcie_gart_tlb_flush,
823	.set_page = &rv370_pcie_gart_set_page,	823	.set_page = &rv370_pcie_gart_set_page,
824	},	824	},
825	.ring = {	825	.ring = {
826	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	826	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
827	},	827	},
828	.irq = {	828	.irq = {
829	.set = &rs600_irq_set,	829	.set = &rs600_irq_set,
830	.process = &rs600_irq_process,	830	.process = &rs600_irq_process,
831	},	831	},
832	.display = {	832	.display = {
833	.bandwidth_update = &rv515_bandwidth_update,	833	.bandwidth_update = &rv515_bandwidth_update,
834	.get_vblank_counter = &rs600_get_vblank_counter,	834	.get_vblank_counter = &rs600_get_vblank_counter,
835	.wait_for_vblank = &avivo_wait_for_vblank,	835	.wait_for_vblank = &avivo_wait_for_vblank,
836	.set_backlight_level = &atombios_set_backlight_level,	836	.set_backlight_level = &atombios_set_backlight_level,
837	.get_backlight_level = &atombios_get_backlight_level,	837	.get_backlight_level = &atombios_get_backlight_level,
838	},	838	},
839	.copy = {	839	.copy = {
840	.blit = &r100_copy_blit,	840	.blit = &r100_copy_blit,
841	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	841	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
842	.dma = &r200_copy_dma,	842	.dma = &r200_copy_dma,
843	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,	843	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
844	.copy = &r100_copy_blit,	844	.copy = &r100_copy_blit,
845	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	845	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
846	},	846	},
847	.surface = {	847	.surface = {
848	.set_reg = r100_set_surface_reg,	848	.set_reg = r100_set_surface_reg,
849	.clear_reg = r100_clear_surface_reg,	849	.clear_reg = r100_clear_surface_reg,
850	},	850	},
851	.hpd = {	851	.hpd = {
852	.init = &rs600_hpd_init,	852	.init = &rs600_hpd_init,
853	.fini = &rs600_hpd_fini,	853	.fini = &rs600_hpd_fini,
854	.sense = &rs600_hpd_sense,	854	.sense = &rs600_hpd_sense,
855	.set_polarity = &rs600_hpd_set_polarity,	855	.set_polarity = &rs600_hpd_set_polarity,
856	},	856	},
857	.pm = {	857	.pm = {
858	.misc = &rs600_pm_misc,	858	.misc = &rs600_pm_misc,
859	.prepare = &rs600_pm_prepare,	859	.prepare = &rs600_pm_prepare,
860	.finish = &rs600_pm_finish,	860	.finish = &rs600_pm_finish,
861	.init_profile = &r420_pm_init_profile,	861	.init_profile = &r420_pm_init_profile,
862	.get_dynpm_state = &r100_pm_get_dynpm_state,	862	.get_dynpm_state = &r100_pm_get_dynpm_state,
863	.get_engine_clock = &radeon_atom_get_engine_clock,	863	.get_engine_clock = &radeon_atom_get_engine_clock,
864	.set_engine_clock = &radeon_atom_set_engine_clock,	864	.set_engine_clock = &radeon_atom_set_engine_clock,
865	.get_memory_clock = &radeon_atom_get_memory_clock,	865	.get_memory_clock = &radeon_atom_get_memory_clock,
866	.set_memory_clock = &radeon_atom_set_memory_clock,	866	.set_memory_clock = &radeon_atom_set_memory_clock,
867	.get_pcie_lanes = &rv370_get_pcie_lanes,	867	.get_pcie_lanes = &rv370_get_pcie_lanes,
868	.set_pcie_lanes = &rv370_set_pcie_lanes,	868	.set_pcie_lanes = &rv370_set_pcie_lanes,
869	.set_clock_gating = &radeon_atom_set_clock_gating,	869	.set_clock_gating = &radeon_atom_set_clock_gating,
870	},	870	},
871	.pflip = {	871	.pflip = {
872	.pre_page_flip = &rs600_pre_page_flip,	872	.pre_page_flip = &rs600_pre_page_flip,
873	.page_flip = &rs600_page_flip,	873	.page_flip = &rs600_page_flip,
874	.post_page_flip = &rs600_post_page_flip,	874	.post_page_flip = &rs600_post_page_flip,
875	},	875	},
876	};	876	};
877		877
878	static struct radeon_asic_ring r600_gfx_ring = {	878	static struct radeon_asic_ring r600_gfx_ring = {
879	.ib_execute = &r600_ring_ib_execute,	879	.ib_execute = &r600_ring_ib_execute,
880	.emit_fence = &r600_fence_ring_emit,	880	.emit_fence = &r600_fence_ring_emit,
881	.emit_semaphore = &r600_semaphore_ring_emit,	881	.emit_semaphore = &r600_semaphore_ring_emit,
882	.cs_parse = &r600_cs_parse,	882	.cs_parse = &r600_cs_parse,
883	.ring_test = &r600_ring_test,	883	.ring_test = &r600_ring_test,
884	.ib_test = &r600_ib_test,	884	.ib_test = &r600_ib_test,
885	.is_lockup = &r600_gfx_is_lockup,	885	.is_lockup = &r600_gfx_is_lockup,
886	.get_rptr = &r600_gfx_get_rptr,	886	.get_rptr = &r600_gfx_get_rptr,
887	.get_wptr = &r600_gfx_get_wptr,	887	.get_wptr = &r600_gfx_get_wptr,
888	.set_wptr = &r600_gfx_set_wptr,	888	.set_wptr = &r600_gfx_set_wptr,
889	};	889	};
890		890
891	static struct radeon_asic_ring r600_dma_ring = {	891	static struct radeon_asic_ring r600_dma_ring = {
892	.ib_execute = &r600_dma_ring_ib_execute,	892	.ib_execute = &r600_dma_ring_ib_execute,
893	.emit_fence = &r600_dma_fence_ring_emit,	893	.emit_fence = &r600_dma_fence_ring_emit,
894	.emit_semaphore = &r600_dma_semaphore_ring_emit,	894	.emit_semaphore = &r600_dma_semaphore_ring_emit,
895	.cs_parse = &r600_dma_cs_parse,	895	.cs_parse = &r600_dma_cs_parse,
896	.ring_test = &r600_dma_ring_test,	896	.ring_test = &r600_dma_ring_test,
897	.ib_test = &r600_dma_ib_test,	897	.ib_test = &r600_dma_ib_test,
898	.is_lockup = &r600_dma_is_lockup,	898	.is_lockup = &r600_dma_is_lockup,
899	.get_rptr = &r600_dma_get_rptr,	899	.get_rptr = &r600_dma_get_rptr,
900	.get_wptr = &r600_dma_get_wptr,	900	.get_wptr = &r600_dma_get_wptr,
901	.set_wptr = &r600_dma_set_wptr,	901	.set_wptr = &r600_dma_set_wptr,
902	};	902	};
903		903
904	static struct radeon_asic r600_asic = {	904	static struct radeon_asic r600_asic = {
905	.init = &r600_init,	905	.init = &r600_init,
906	.fini = &r600_fini,	906	.fini = &r600_fini,
907	.suspend = &r600_suspend,	907	.suspend = &r600_suspend,
908	.resume = &r600_resume,	908	.resume = &r600_resume,
909	.vga_set_state = &r600_vga_set_state,	909	.vga_set_state = &r600_vga_set_state,
910	.asic_reset = &r600_asic_reset,	910	.asic_reset = &r600_asic_reset,
911	.ioctl_wait_idle = r600_ioctl_wait_idle,	911	.ioctl_wait_idle = r600_ioctl_wait_idle,
912	.gui_idle = &r600_gui_idle,	912	.gui_idle = &r600_gui_idle,
913	.mc_wait_for_idle = &r600_mc_wait_for_idle,	913	.mc_wait_for_idle = &r600_mc_wait_for_idle,
914	.get_xclk = &r600_get_xclk,	914	.get_xclk = &r600_get_xclk,
915	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	915	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
916	.gart = {	916	.gart = {
917	.tlb_flush = &r600_pcie_gart_tlb_flush,	917	.tlb_flush = &r600_pcie_gart_tlb_flush,
918	.set_page = &rs600_gart_set_page,	918	.set_page = &rs600_gart_set_page,
919	},	919	},
920	.ring = {	920	.ring = {
921	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	921	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
922	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	922	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
923	},	923	},
924	.irq = {	924	.irq = {
925	.set = &r600_irq_set,	925	.set = &r600_irq_set,
926	.process = &r600_irq_process,	926	.process = &r600_irq_process,
927	},	927	},
928	.display = {	928	.display = {
929	.bandwidth_update = &rv515_bandwidth_update,	929	.bandwidth_update = &rv515_bandwidth_update,
930	.get_vblank_counter = &rs600_get_vblank_counter,	930	.get_vblank_counter = &rs600_get_vblank_counter,
931	.wait_for_vblank = &avivo_wait_for_vblank,	931	.wait_for_vblank = &avivo_wait_for_vblank,
932	.set_backlight_level = &atombios_set_backlight_level,	932	.set_backlight_level = &atombios_set_backlight_level,
933	.get_backlight_level = &atombios_get_backlight_level,	933	.get_backlight_level = &atombios_get_backlight_level,
934	.hdmi_enable = &r600_hdmi_enable,	934	.hdmi_enable = &r600_hdmi_enable,
935	.hdmi_setmode = &r600_hdmi_setmode,	935	.hdmi_setmode = &r600_hdmi_setmode,
936	},	936	},
937	.copy = {	937	.copy = {
938	.blit = &r600_copy_cpdma,	938	.blit = &r600_copy_cpdma,
939	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	939	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
940	.dma = &r600_copy_dma,	940	.dma = &r600_copy_dma,
941	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	941	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
942	.copy = &r600_copy_cpdma,	942	.copy = &r600_copy_cpdma,
943	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	943	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
944	},	944	},
945	.surface = {	945	.surface = {
946	.set_reg = r600_set_surface_reg,	946	.set_reg = r600_set_surface_reg,
947	.clear_reg = r600_clear_surface_reg,	947	.clear_reg = r600_clear_surface_reg,
948	},	948	},
949	.hpd = {	949	.hpd = {
950	.init = &r600_hpd_init,	950	.init = &r600_hpd_init,
951	.fini = &r600_hpd_fini,	951	.fini = &r600_hpd_fini,
952	.sense = &r600_hpd_sense,	952	.sense = &r600_hpd_sense,
953	.set_polarity = &r600_hpd_set_polarity,	953	.set_polarity = &r600_hpd_set_polarity,
954	},	954	},
955	.pm = {	955	.pm = {
956	.misc = &r600_pm_misc,	956	.misc = &r600_pm_misc,
957	.prepare = &rs600_pm_prepare,	957	.prepare = &rs600_pm_prepare,
958	.finish = &rs600_pm_finish,	958	.finish = &rs600_pm_finish,
959	.init_profile = &r600_pm_init_profile,	959	.init_profile = &r600_pm_init_profile,
960	.get_dynpm_state = &r600_pm_get_dynpm_state,	960	.get_dynpm_state = &r600_pm_get_dynpm_state,
961	.get_engine_clock = &radeon_atom_get_engine_clock,	961	.get_engine_clock = &radeon_atom_get_engine_clock,
962	.set_engine_clock = &radeon_atom_set_engine_clock,	962	.set_engine_clock = &radeon_atom_set_engine_clock,
963	.get_memory_clock = &radeon_atom_get_memory_clock,	963	.get_memory_clock = &radeon_atom_get_memory_clock,
964	.set_memory_clock = &radeon_atom_set_memory_clock,	964	.set_memory_clock = &radeon_atom_set_memory_clock,
965	.get_pcie_lanes = &r600_get_pcie_lanes,	965	.get_pcie_lanes = &r600_get_pcie_lanes,
966	.set_pcie_lanes = &r600_set_pcie_lanes,	966	.set_pcie_lanes = &r600_set_pcie_lanes,
967	.set_clock_gating = NULL,	967	.set_clock_gating = NULL,
968	.get_temperature = &rv6xx_get_temp,	968	.get_temperature = &rv6xx_get_temp,
969	},	969	},
970	.pflip = {	970	.pflip = {
971	.pre_page_flip = &rs600_pre_page_flip,	971	.pre_page_flip = &rs600_pre_page_flip,
972	.page_flip = &rs600_page_flip,	972	.page_flip = &rs600_page_flip,
973	.post_page_flip = &rs600_post_page_flip,	973	.post_page_flip = &rs600_post_page_flip,
974	},	974	},
975	};	975	};
976		976
977	static struct radeon_asic rv6xx_asic = {	977	static struct radeon_asic rv6xx_asic = {
978	.init = &r600_init,	978	.init = &r600_init,
979	.fini = &r600_fini,	979	.fini = &r600_fini,
980	.suspend = &r600_suspend,	980	.suspend = &r600_suspend,
981	.resume = &r600_resume,	981	.resume = &r600_resume,
982	.vga_set_state = &r600_vga_set_state,	982	.vga_set_state = &r600_vga_set_state,
983	.asic_reset = &r600_asic_reset,	983	.asic_reset = &r600_asic_reset,
984	.ioctl_wait_idle = r600_ioctl_wait_idle,	984	.ioctl_wait_idle = r600_ioctl_wait_idle,
985	.gui_idle = &r600_gui_idle,	985	.gui_idle = &r600_gui_idle,
986	.mc_wait_for_idle = &r600_mc_wait_for_idle,	986	.mc_wait_for_idle = &r600_mc_wait_for_idle,
987	.get_xclk = &r600_get_xclk,	987	.get_xclk = &r600_get_xclk,
988	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	988	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
989	.gart = {	989	.gart = {
990	.tlb_flush = &r600_pcie_gart_tlb_flush,	990	.tlb_flush = &r600_pcie_gart_tlb_flush,
991	.set_page = &rs600_gart_set_page,	991	.set_page = &rs600_gart_set_page,
992	},	992	},
993	.ring = {	993	.ring = {
994	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	994	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
995	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	995	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
996	},	996	},
997	.irq = {	997	.irq = {
998	.set = &r600_irq_set,	998	.set = &r600_irq_set,
999	.process = &r600_irq_process,	999	.process = &r600_irq_process,
1000	},	1000	},
1001	.display = {	1001	.display = {
1002	.bandwidth_update = &rv515_bandwidth_update,	1002	.bandwidth_update = &rv515_bandwidth_update,
1003	.get_vblank_counter = &rs600_get_vblank_counter,	1003	.get_vblank_counter = &rs600_get_vblank_counter,
1004	.wait_for_vblank = &avivo_wait_for_vblank,	1004	.wait_for_vblank = &avivo_wait_for_vblank,
1005	.set_backlight_level = &atombios_set_backlight_level,	1005	.set_backlight_level = &atombios_set_backlight_level,
1006	.get_backlight_level = &atombios_get_backlight_level,	1006	.get_backlight_level = &atombios_get_backlight_level,
1007	.hdmi_enable = &r600_hdmi_enable,	1007	.hdmi_enable = &r600_hdmi_enable,
1008	.hdmi_setmode = &r600_hdmi_setmode,	1008	.hdmi_setmode = &r600_hdmi_setmode,
1009	},	1009	},
1010	.copy = {	1010	.copy = {
1011	.blit = &r600_copy_cpdma,	1011	.blit = &r600_copy_cpdma,
1012	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1012	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1013	.dma = &r600_copy_dma,	1013	.dma = &r600_copy_dma,
1014	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1014	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1015	.copy = &r600_copy_cpdma,	1015	.copy = &r600_copy_cpdma,
1016	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1016	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1017	},	1017	},
1018	.surface = {	1018	.surface = {
1019	.set_reg = r600_set_surface_reg,	1019	.set_reg = r600_set_surface_reg,
1020	.clear_reg = r600_clear_surface_reg,	1020	.clear_reg = r600_clear_surface_reg,
1021	},	1021	},
1022	.hpd = {	1022	.hpd = {
1023	.init = &r600_hpd_init,	1023	.init = &r600_hpd_init,
1024	.fini = &r600_hpd_fini,	1024	.fini = &r600_hpd_fini,
1025	.sense = &r600_hpd_sense,	1025	.sense = &r600_hpd_sense,
1026	.set_polarity = &r600_hpd_set_polarity,	1026	.set_polarity = &r600_hpd_set_polarity,
1027	},	1027	},
1028	.pm = {	1028	.pm = {
1029	.misc = &r600_pm_misc,	1029	.misc = &r600_pm_misc,
1030	.prepare = &rs600_pm_prepare,	1030	.prepare = &rs600_pm_prepare,
1031	.finish = &rs600_pm_finish,	1031	.finish = &rs600_pm_finish,
1032	.init_profile = &r600_pm_init_profile,	1032	.init_profile = &r600_pm_init_profile,
1033	.get_dynpm_state = &r600_pm_get_dynpm_state,	1033	.get_dynpm_state = &r600_pm_get_dynpm_state,
1034	.get_engine_clock = &radeon_atom_get_engine_clock,	1034	.get_engine_clock = &radeon_atom_get_engine_clock,
1035	.set_engine_clock = &radeon_atom_set_engine_clock,	1035	.set_engine_clock = &radeon_atom_set_engine_clock,
1036	.get_memory_clock = &radeon_atom_get_memory_clock,	1036	.get_memory_clock = &radeon_atom_get_memory_clock,
1037	.set_memory_clock = &radeon_atom_set_memory_clock,	1037	.set_memory_clock = &radeon_atom_set_memory_clock,
1038	.get_pcie_lanes = &r600_get_pcie_lanes,	1038	.get_pcie_lanes = &r600_get_pcie_lanes,
1039	.set_pcie_lanes = &r600_set_pcie_lanes,	1039	.set_pcie_lanes = &r600_set_pcie_lanes,
1040	.set_clock_gating = NULL,	1040	.set_clock_gating = NULL,
1041	.get_temperature = &rv6xx_get_temp,	1041	.get_temperature = &rv6xx_get_temp,
1042	.set_uvd_clocks = &r600_set_uvd_clocks,	1042	.set_uvd_clocks = &r600_set_uvd_clocks,
1043	},	1043	},
1044	.dpm = {	1044	.dpm = {
1045	.init = &rv6xx_dpm_init,	1045	.init = &rv6xx_dpm_init,
1046	.setup_asic = &rv6xx_setup_asic,	1046	.setup_asic = &rv6xx_setup_asic,
1047	.enable = &rv6xx_dpm_enable,	1047	.enable = &rv6xx_dpm_enable,
1048	.late_enable = &r600_dpm_late_enable,	1048	.late_enable = &r600_dpm_late_enable,
1049	.disable = &rv6xx_dpm_disable,	1049	.disable = &rv6xx_dpm_disable,
1050	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1050	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1051	.set_power_state = &rv6xx_dpm_set_power_state,	1051	.set_power_state = &rv6xx_dpm_set_power_state,
1052	.post_set_power_state = &r600_dpm_post_set_power_state,	1052	.post_set_power_state = &r600_dpm_post_set_power_state,
1053	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,	1053	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1054	.fini = &rv6xx_dpm_fini,	1054	.fini = &rv6xx_dpm_fini,
1055	.get_sclk = &rv6xx_dpm_get_sclk,	1055	.get_sclk = &rv6xx_dpm_get_sclk,
1056	.get_mclk = &rv6xx_dpm_get_mclk,	1056	.get_mclk = &rv6xx_dpm_get_mclk,
1057	.print_power_state = &rv6xx_dpm_print_power_state,	1057	.print_power_state = &rv6xx_dpm_print_power_state,
1058	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,	1058	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1059	.force_performance_level = &rv6xx_dpm_force_performance_level,	1059	.force_performance_level = &rv6xx_dpm_force_performance_level,
1060	},	1060	},
1061	.pflip = {	1061	.pflip = {
1062	.pre_page_flip = &rs600_pre_page_flip,	1062	.pre_page_flip = &rs600_pre_page_flip,
1063	.page_flip = &rs600_page_flip,	1063	.page_flip = &rs600_page_flip,
1064	.post_page_flip = &rs600_post_page_flip,	1064	.post_page_flip = &rs600_post_page_flip,
1065	},	1065	},
1066	};	1066	};
1067		1067
1068	static struct radeon_asic rs780_asic = {	1068	static struct radeon_asic rs780_asic = {
1069	.init = &r600_init,	1069	.init = &r600_init,
1070	.fini = &r600_fini,	1070	.fini = &r600_fini,
1071	.suspend = &r600_suspend,	1071	.suspend = &r600_suspend,
1072	.resume = &r600_resume,	1072	.resume = &r600_resume,
1073	.vga_set_state = &r600_vga_set_state,	1073	.vga_set_state = &r600_vga_set_state,
1074	.asic_reset = &r600_asic_reset,	1074	.asic_reset = &r600_asic_reset,
1075	.ioctl_wait_idle = r600_ioctl_wait_idle,	1075	.ioctl_wait_idle = r600_ioctl_wait_idle,
1076	.gui_idle = &r600_gui_idle,	1076	.gui_idle = &r600_gui_idle,
1077	.mc_wait_for_idle = &r600_mc_wait_for_idle,	1077	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1078	.get_xclk = &r600_get_xclk,	1078	.get_xclk = &r600_get_xclk,
1079	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1079	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1080	.gart = {	1080	.gart = {
1081	.tlb_flush = &r600_pcie_gart_tlb_flush,	1081	.tlb_flush = &r600_pcie_gart_tlb_flush,
1082	.set_page = &rs600_gart_set_page,	1082	.set_page = &rs600_gart_set_page,
1083	},	1083	},
1084	.ring = {	1084	.ring = {
1085	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	1085	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1086	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	1086	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1087	},	1087	},
1088	.irq = {	1088	.irq = {
1089	.set = &r600_irq_set,	1089	.set = &r600_irq_set,
1090	.process = &r600_irq_process,	1090	.process = &r600_irq_process,
1091	},	1091	},
1092	.display = {	1092	.display = {
1093	.bandwidth_update = &rs690_bandwidth_update,	1093	.bandwidth_update = &rs690_bandwidth_update,
1094	.get_vblank_counter = &rs600_get_vblank_counter,	1094	.get_vblank_counter = &rs600_get_vblank_counter,
1095	.wait_for_vblank = &avivo_wait_for_vblank,	1095	.wait_for_vblank = &avivo_wait_for_vblank,
1096	.set_backlight_level = &atombios_set_backlight_level,	1096	.set_backlight_level = &atombios_set_backlight_level,
1097	.get_backlight_level = &atombios_get_backlight_level,	1097	.get_backlight_level = &atombios_get_backlight_level,
1098	.hdmi_enable = &r600_hdmi_enable,	1098	.hdmi_enable = &r600_hdmi_enable,
1099	.hdmi_setmode = &r600_hdmi_setmode,	1099	.hdmi_setmode = &r600_hdmi_setmode,
1100	},	1100	},
1101	.copy = {	1101	.copy = {
1102	.blit = &r600_copy_cpdma,	1102	.blit = &r600_copy_cpdma,
1103	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1103	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1104	.dma = &r600_copy_dma,	1104	.dma = &r600_copy_dma,
1105	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1105	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1106	.copy = &r600_copy_cpdma,	1106	.copy = &r600_copy_cpdma,
1107	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1107	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1108	},	1108	},
1109	.surface = {	1109	.surface = {
1110	.set_reg = r600_set_surface_reg,	1110	.set_reg = r600_set_surface_reg,
1111	.clear_reg = r600_clear_surface_reg,	1111	.clear_reg = r600_clear_surface_reg,
1112	},	1112	},
1113	.hpd = {	1113	.hpd = {
1114	.init = &r600_hpd_init,	1114	.init = &r600_hpd_init,
1115	.fini = &r600_hpd_fini,	1115	.fini = &r600_hpd_fini,
1116	.sense = &r600_hpd_sense,	1116	.sense = &r600_hpd_sense,
1117	.set_polarity = &r600_hpd_set_polarity,	1117	.set_polarity = &r600_hpd_set_polarity,
1118	},	1118	},
1119	.pm = {	1119	.pm = {
1120	.misc = &r600_pm_misc,	1120	.misc = &r600_pm_misc,
1121	.prepare = &rs600_pm_prepare,	1121	.prepare = &rs600_pm_prepare,
1122	.finish = &rs600_pm_finish,	1122	.finish = &rs600_pm_finish,
1123	.init_profile = &rs780_pm_init_profile,	1123	.init_profile = &rs780_pm_init_profile,
1124	.get_dynpm_state = &r600_pm_get_dynpm_state,	1124	.get_dynpm_state = &r600_pm_get_dynpm_state,
1125	.get_engine_clock = &radeon_atom_get_engine_clock,	1125	.get_engine_clock = &radeon_atom_get_engine_clock,
1126	.set_engine_clock = &radeon_atom_set_engine_clock,	1126	.set_engine_clock = &radeon_atom_set_engine_clock,
1127	.get_memory_clock = NULL,	1127	.get_memory_clock = NULL,
1128	.set_memory_clock = NULL,	1128	.set_memory_clock = NULL,
1129	.get_pcie_lanes = NULL,	1129	.get_pcie_lanes = NULL,
1130	.set_pcie_lanes = NULL,	1130	.set_pcie_lanes = NULL,
1131	.set_clock_gating = NULL,	1131	.set_clock_gating = NULL,
1132	.get_temperature = &rv6xx_get_temp,	1132	.get_temperature = &rv6xx_get_temp,
1133	.set_uvd_clocks = &r600_set_uvd_clocks,	1133	.set_uvd_clocks = &r600_set_uvd_clocks,
1134	},	1134	},
1135	.dpm = {	1135	.dpm = {
1136	.init = &rs780_dpm_init,	1136	.init = &rs780_dpm_init,
1137	.setup_asic = &rs780_dpm_setup_asic,	1137	.setup_asic = &rs780_dpm_setup_asic,
1138	.enable = &rs780_dpm_enable,	1138	.enable = &rs780_dpm_enable,
1139	.late_enable = &r600_dpm_late_enable,	1139	.late_enable = &r600_dpm_late_enable,
1140	.disable = &rs780_dpm_disable,	1140	.disable = &rs780_dpm_disable,
1141	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1141	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1142	.set_power_state = &rs780_dpm_set_power_state,	1142	.set_power_state = &rs780_dpm_set_power_state,
1143	.post_set_power_state = &r600_dpm_post_set_power_state,	1143	.post_set_power_state = &r600_dpm_post_set_power_state,
1144	.display_configuration_changed = &rs780_dpm_display_configuration_changed,	1144	.display_configuration_changed = &rs780_dpm_display_configuration_changed,
1145	.fini = &rs780_dpm_fini,	1145	.fini = &rs780_dpm_fini,
1146	.get_sclk = &rs780_dpm_get_sclk,	1146	.get_sclk = &rs780_dpm_get_sclk,
1147	.get_mclk = &rs780_dpm_get_mclk,	1147	.get_mclk = &rs780_dpm_get_mclk,
1148	.print_power_state = &rs780_dpm_print_power_state,	1148	.print_power_state = &rs780_dpm_print_power_state,
1149	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,	1149	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1150	.force_performance_level = &rs780_dpm_force_performance_level,	1150	.force_performance_level = &rs780_dpm_force_performance_level,
1151	},	1151	},
1152	.pflip = {	1152	.pflip = {
1153	.pre_page_flip = &rs600_pre_page_flip,	1153	.pre_page_flip = &rs600_pre_page_flip,
1154	.page_flip = &rs600_page_flip,	1154	.page_flip = &rs600_page_flip,
1155	.post_page_flip = &rs600_post_page_flip,	1155	.post_page_flip = &rs600_post_page_flip,
1156	},	1156	},
1157	};	1157	};
1158		1158
1159	static struct radeon_asic_ring rv770_uvd_ring = {	1159	static struct radeon_asic_ring rv770_uvd_ring = {
1160	.ib_execute = &uvd_v1_0_ib_execute,	1160	.ib_execute = &uvd_v1_0_ib_execute,
1161	.emit_fence = &uvd_v2_2_fence_emit,	1161	.emit_fence = &uvd_v2_2_fence_emit,
1162	.emit_semaphore = &uvd_v1_0_semaphore_emit,	1162	.emit_semaphore = &uvd_v1_0_semaphore_emit,
1163	.cs_parse = &radeon_uvd_cs_parse,	1163	.cs_parse = &radeon_uvd_cs_parse,
1164	.ring_test = &uvd_v1_0_ring_test,	1164	.ring_test = &uvd_v1_0_ring_test,
1165	.ib_test = &uvd_v1_0_ib_test,	1165	.ib_test = &uvd_v1_0_ib_test,
1166	.is_lockup = &radeon_ring_test_lockup,	1166	.is_lockup = &radeon_ring_test_lockup,
1167	.get_rptr = &uvd_v1_0_get_rptr,	1167	.get_rptr = &uvd_v1_0_get_rptr,
1168	.get_wptr = &uvd_v1_0_get_wptr,	1168	.get_wptr = &uvd_v1_0_get_wptr,
1169	.set_wptr = &uvd_v1_0_set_wptr,	1169	.set_wptr = &uvd_v1_0_set_wptr,
1170	};	1170	};
1171		1171
1172	static struct radeon_asic rv770_asic = {	1172	static struct radeon_asic rv770_asic = {
1173	.init = &rv770_init,	1173	.init = &rv770_init,
1174	.fini = &rv770_fini,	1174	.fini = &rv770_fini,
1175	.suspend = &rv770_suspend,	1175	.suspend = &rv770_suspend,
1176	.resume = &rv770_resume,	1176	.resume = &rv770_resume,
1177	.asic_reset = &r600_asic_reset,	1177	.asic_reset = &r600_asic_reset,
1178	.vga_set_state = &r600_vga_set_state,	1178	.vga_set_state = &r600_vga_set_state,
1179	.ioctl_wait_idle = r600_ioctl_wait_idle,	1179	.ioctl_wait_idle = r600_ioctl_wait_idle,
1180	.gui_idle = &r600_gui_idle,	1180	.gui_idle = &r600_gui_idle,
1181	.mc_wait_for_idle = &r600_mc_wait_for_idle,	1181	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1182	.get_xclk = &rv770_get_xclk,	1182	.get_xclk = &rv770_get_xclk,
1183	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1183	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1184	.gart = {	1184	.gart = {
1185	.tlb_flush = &r600_pcie_gart_tlb_flush,	1185	.tlb_flush = &r600_pcie_gart_tlb_flush,
1186	.set_page = &rs600_gart_set_page,	1186	.set_page = &rs600_gart_set_page,
1187	},	1187	},
1188	.ring = {	1188	.ring = {
1189	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	1189	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1190	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	1190	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1191	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1191	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1192	},	1192	},
1193	.irq = {	1193	.irq = {
1194	.set = &r600_irq_set,	1194	.set = &r600_irq_set,
1195	.process = &r600_irq_process,	1195	.process = &r600_irq_process,
1196	},	1196	},
1197	.display = {	1197	.display = {
1198	.bandwidth_update = &rv515_bandwidth_update,	1198	.bandwidth_update = &rv515_bandwidth_update,
1199	.get_vblank_counter = &rs600_get_vblank_counter,	1199	.get_vblank_counter = &rs600_get_vblank_counter,
1200	.wait_for_vblank = &avivo_wait_for_vblank,	1200	.wait_for_vblank = &avivo_wait_for_vblank,
1201	.set_backlight_level = &atombios_set_backlight_level,	1201	.set_backlight_level = &atombios_set_backlight_level,
1202	.get_backlight_level = &atombios_get_backlight_level,	1202	.get_backlight_level = &atombios_get_backlight_level,
1203	.hdmi_enable = &r600_hdmi_enable,	1203	.hdmi_enable = &r600_hdmi_enable,
1204	.hdmi_setmode = &r600_hdmi_setmode,	1204	.hdmi_setmode = &r600_hdmi_setmode,
1205	},	1205	},
1206	.copy = {	1206	.copy = {
1207	.blit = &r600_copy_cpdma,	1207	.blit = &r600_copy_cpdma,
1208	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1208	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1209	.dma = &rv770_copy_dma,	1209	.dma = &rv770_copy_dma,
1210	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1210	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1211	.copy = &rv770_copy_dma,	1211	.copy = &rv770_copy_dma,
1212	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1212	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1213	},	1213	},
1214	.surface = {	1214	.surface = {
1215	.set_reg = r600_set_surface_reg,	1215	.set_reg = r600_set_surface_reg,
1216	.clear_reg = r600_clear_surface_reg,	1216	.clear_reg = r600_clear_surface_reg,
1217	},	1217	},
1218	.hpd = {	1218	.hpd = {
1219	.init = &r600_hpd_init,	1219	.init = &r600_hpd_init,
1220	.fini = &r600_hpd_fini,	1220	.fini = &r600_hpd_fini,
1221	.sense = &r600_hpd_sense,	1221	.sense = &r600_hpd_sense,
1222	.set_polarity = &r600_hpd_set_polarity,	1222	.set_polarity = &r600_hpd_set_polarity,
1223	},	1223	},
1224	.pm = {	1224	.pm = {
1225	.misc = &rv770_pm_misc,	1225	.misc = &rv770_pm_misc,
1226	.prepare = &rs600_pm_prepare,	1226	.prepare = &rs600_pm_prepare,
1227	.finish = &rs600_pm_finish,	1227	.finish = &rs600_pm_finish,
1228	.init_profile = &r600_pm_init_profile,	1228	.init_profile = &r600_pm_init_profile,
1229	.get_dynpm_state = &r600_pm_get_dynpm_state,	1229	.get_dynpm_state = &r600_pm_get_dynpm_state,
1230	.get_engine_clock = &radeon_atom_get_engine_clock,	1230	.get_engine_clock = &radeon_atom_get_engine_clock,
1231	.set_engine_clock = &radeon_atom_set_engine_clock,	1231	.set_engine_clock = &radeon_atom_set_engine_clock,
1232	.get_memory_clock = &radeon_atom_get_memory_clock,	1232	.get_memory_clock = &radeon_atom_get_memory_clock,
1233	.set_memory_clock = &radeon_atom_set_memory_clock,	1233	.set_memory_clock = &radeon_atom_set_memory_clock,
1234	.get_pcie_lanes = &r600_get_pcie_lanes,	1234	.get_pcie_lanes = &r600_get_pcie_lanes,
1235	.set_pcie_lanes = &r600_set_pcie_lanes,	1235	.set_pcie_lanes = &r600_set_pcie_lanes,
1236	.set_clock_gating = &radeon_atom_set_clock_gating,	1236	.set_clock_gating = &radeon_atom_set_clock_gating,
1237	.set_uvd_clocks = &rv770_set_uvd_clocks,	1237	.set_uvd_clocks = &rv770_set_uvd_clocks,
1238	.get_temperature = &rv770_get_temp,	1238	.get_temperature = &rv770_get_temp,
1239	},	1239	},
1240	.dpm = {	1240	.dpm = {
1241	.init = &rv770_dpm_init,	1241	.init = &rv770_dpm_init,
1242	.setup_asic = &rv770_dpm_setup_asic,	1242	.setup_asic = &rv770_dpm_setup_asic,
1243	.enable = &rv770_dpm_enable,	1243	.enable = &rv770_dpm_enable,
1244	.late_enable = &rv770_dpm_late_enable,	1244	.late_enable = &rv770_dpm_late_enable,
1245	.disable = &rv770_dpm_disable,	1245	.disable = &rv770_dpm_disable,
1246	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1246	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1247	.set_power_state = &rv770_dpm_set_power_state,	1247	.set_power_state = &rv770_dpm_set_power_state,
1248	.post_set_power_state = &r600_dpm_post_set_power_state,	1248	.post_set_power_state = &r600_dpm_post_set_power_state,
1249	.display_configuration_changed = &rv770_dpm_display_configuration_changed,	1249	.display_configuration_changed = &rv770_dpm_display_configuration_changed,
1250	.fini = &rv770_dpm_fini,	1250	.fini = &rv770_dpm_fini,
1251	.get_sclk = &rv770_dpm_get_sclk,	1251	.get_sclk = &rv770_dpm_get_sclk,
1252	.get_mclk = &rv770_dpm_get_mclk,	1252	.get_mclk = &rv770_dpm_get_mclk,
1253	.print_power_state = &rv770_dpm_print_power_state,	1253	.print_power_state = &rv770_dpm_print_power_state,
1254	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,	1254	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1255	.force_performance_level = &rv770_dpm_force_performance_level,	1255	.force_performance_level = &rv770_dpm_force_performance_level,
1256	.vblank_too_short = &rv770_dpm_vblank_too_short,	1256	.vblank_too_short = &rv770_dpm_vblank_too_short,
1257	},	1257	},
1258	.pflip = {	1258	.pflip = {
1259	.pre_page_flip = &rs600_pre_page_flip,	1259	.pre_page_flip = &rs600_pre_page_flip,
1260	.page_flip = &rv770_page_flip,	1260	.page_flip = &rv770_page_flip,
1261	.post_page_flip = &rs600_post_page_flip,	1261	.post_page_flip = &rs600_post_page_flip,
1262	},	1262	},
1263	};	1263	};
1264		1264
1265	static struct radeon_asic_ring evergreen_gfx_ring = {	1265	static struct radeon_asic_ring evergreen_gfx_ring = {
1266	.ib_execute = &evergreen_ring_ib_execute,	1266	.ib_execute = &evergreen_ring_ib_execute,
1267	.emit_fence = &r600_fence_ring_emit,	1267	.emit_fence = &r600_fence_ring_emit,
1268	.emit_semaphore = &r600_semaphore_ring_emit,	1268	.emit_semaphore = &r600_semaphore_ring_emit,
1269	.cs_parse = &evergreen_cs_parse,	1269	.cs_parse = &evergreen_cs_parse,
1270	.ring_test = &r600_ring_test,	1270	.ring_test = &r600_ring_test,
1271	.ib_test = &r600_ib_test,	1271	.ib_test = &r600_ib_test,
1272	.is_lockup = &evergreen_gfx_is_lockup,	1272	.is_lockup = &evergreen_gfx_is_lockup,
1273	.get_rptr = &r600_gfx_get_rptr,	1273	.get_rptr = &r600_gfx_get_rptr,
1274	.get_wptr = &r600_gfx_get_wptr,	1274	.get_wptr = &r600_gfx_get_wptr,
1275	.set_wptr = &r600_gfx_set_wptr,	1275	.set_wptr = &r600_gfx_set_wptr,
1276	};	1276	};
1277		1277
1278	static struct radeon_asic_ring evergreen_dma_ring = {	1278	static struct radeon_asic_ring evergreen_dma_ring = {
1279	.ib_execute = &evergreen_dma_ring_ib_execute,	1279	.ib_execute = &evergreen_dma_ring_ib_execute,
1280	.emit_fence = &evergreen_dma_fence_ring_emit,	1280	.emit_fence = &evergreen_dma_fence_ring_emit,
1281	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1281	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1282	.cs_parse = &evergreen_dma_cs_parse,	1282	.cs_parse = &evergreen_dma_cs_parse,
1283	.ring_test = &r600_dma_ring_test,	1283	.ring_test = &r600_dma_ring_test,
1284	.ib_test = &r600_dma_ib_test,	1284	.ib_test = &r600_dma_ib_test,
1285	.is_lockup = &evergreen_dma_is_lockup,	1285	.is_lockup = &evergreen_dma_is_lockup,
1286	.get_rptr = &r600_dma_get_rptr,	1286	.get_rptr = &r600_dma_get_rptr,
1287	.get_wptr = &r600_dma_get_wptr,	1287	.get_wptr = &r600_dma_get_wptr,
1288	.set_wptr = &r600_dma_set_wptr,	1288	.set_wptr = &r600_dma_set_wptr,
1289	};	1289	};
1290		1290
1291	static struct radeon_asic evergreen_asic = {	1291	static struct radeon_asic evergreen_asic = {
1292	.init = &evergreen_init,	1292	.init = &evergreen_init,
1293	.fini = &evergreen_fini,	1293	.fini = &evergreen_fini,
1294	.suspend = &evergreen_suspend,	1294	.suspend = &evergreen_suspend,
1295	.resume = &evergreen_resume,	1295	.resume = &evergreen_resume,
1296	.asic_reset = &evergreen_asic_reset,	1296	.asic_reset = &evergreen_asic_reset,
1297	.vga_set_state = &r600_vga_set_state,	1297	.vga_set_state = &r600_vga_set_state,
1298	.ioctl_wait_idle = r600_ioctl_wait_idle,	1298	.ioctl_wait_idle = r600_ioctl_wait_idle,
1299	.gui_idle = &r600_gui_idle,	1299	.gui_idle = &r600_gui_idle,
1300	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1300	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1301	.get_xclk = &rv770_get_xclk,	1301	.get_xclk = &rv770_get_xclk,
1302	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1302	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1303	.gart = {	1303	.gart = {
1304	.tlb_flush = &evergreen_pcie_gart_tlb_flush,	1304	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1305	.set_page = &rs600_gart_set_page,	1305	.set_page = &rs600_gart_set_page,
1306	},	1306	},
1307	.ring = {	1307	.ring = {
1308	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,	1308	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1309	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,	1309	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1310	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1310	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1311	},	1311	},
1312	.irq = {	1312	.irq = {
1313	.set = &evergreen_irq_set,	1313	.set = &evergreen_irq_set,
1314	.process = &evergreen_irq_process,	1314	.process = &evergreen_irq_process,
1315	},	1315	},
1316	.display = {	1316	.display = {
1317	.bandwidth_update = &evergreen_bandwidth_update,	1317	.bandwidth_update = &evergreen_bandwidth_update,
1318	.get_vblank_counter = &evergreen_get_vblank_counter,	1318	.get_vblank_counter = &evergreen_get_vblank_counter,
1319	.wait_for_vblank = &dce4_wait_for_vblank,	1319	.wait_for_vblank = &dce4_wait_for_vblank,
1320	.set_backlight_level = &atombios_set_backlight_level,	1320	.set_backlight_level = &atombios_set_backlight_level,
1321	.get_backlight_level = &atombios_get_backlight_level,	1321	.get_backlight_level = &atombios_get_backlight_level,
1322	.hdmi_enable = &evergreen_hdmi_enable,	1322	.hdmi_enable = &evergreen_hdmi_enable,
1323	.hdmi_setmode = &evergreen_hdmi_setmode,	1323	.hdmi_setmode = &evergreen_hdmi_setmode,
1324	},	1324	},
1325	.copy = {	1325	.copy = {
1326	.blit = &r600_copy_cpdma,	1326	.blit = &r600_copy_cpdma,
1327	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1327	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1328	.dma = &evergreen_copy_dma,	1328	.dma = &evergreen_copy_dma,
1329	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1329	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1330	.copy = &evergreen_copy_dma,	1330	.copy = &evergreen_copy_dma,
1331	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1331	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1332	},	1332	},
1333	.surface = {	1333	.surface = {
1334	.set_reg = r600_set_surface_reg,	1334	.set_reg = r600_set_surface_reg,
1335	.clear_reg = r600_clear_surface_reg,	1335	.clear_reg = r600_clear_surface_reg,
1336	},	1336	},
1337	.hpd = {	1337	.hpd = {
1338	.init = &evergreen_hpd_init,	1338	.init = &evergreen_hpd_init,
1339	.fini = &evergreen_hpd_fini,	1339	.fini = &evergreen_hpd_fini,
1340	.sense = &evergreen_hpd_sense,	1340	.sense = &evergreen_hpd_sense,
1341	.set_polarity = &evergreen_hpd_set_polarity,	1341	.set_polarity = &evergreen_hpd_set_polarity,
1342	},	1342	},
1343	.pm = {	1343	.pm = {
1344	.misc = &evergreen_pm_misc,	1344	.misc = &evergreen_pm_misc,
1345	.prepare = &evergreen_pm_prepare,	1345	.prepare = &evergreen_pm_prepare,
1346	.finish = &evergreen_pm_finish,	1346	.finish = &evergreen_pm_finish,
1347	.init_profile = &r600_pm_init_profile,	1347	.init_profile = &r600_pm_init_profile,
1348	.get_dynpm_state = &r600_pm_get_dynpm_state,	1348	.get_dynpm_state = &r600_pm_get_dynpm_state,
1349	.get_engine_clock = &radeon_atom_get_engine_clock,	1349	.get_engine_clock = &radeon_atom_get_engine_clock,
1350	.set_engine_clock = &radeon_atom_set_engine_clock,	1350	.set_engine_clock = &radeon_atom_set_engine_clock,
1351	.get_memory_clock = &radeon_atom_get_memory_clock,	1351	.get_memory_clock = &radeon_atom_get_memory_clock,
1352	.set_memory_clock = &radeon_atom_set_memory_clock,	1352	.set_memory_clock = &radeon_atom_set_memory_clock,
1353	.get_pcie_lanes = &r600_get_pcie_lanes,	1353	.get_pcie_lanes = &r600_get_pcie_lanes,
1354	.set_pcie_lanes = &r600_set_pcie_lanes,	1354	.set_pcie_lanes = &r600_set_pcie_lanes,
1355	.set_clock_gating = NULL,	1355	.set_clock_gating = NULL,
1356	.set_uvd_clocks = &evergreen_set_uvd_clocks,	1356	.set_uvd_clocks = &evergreen_set_uvd_clocks,
1357	.get_temperature = &evergreen_get_temp,	1357	.get_temperature = &evergreen_get_temp,
1358	},	1358	},
1359	.dpm = {	1359	.dpm = {
1360	.init = &cypress_dpm_init,	1360	.init = &cypress_dpm_init,
1361	.setup_asic = &cypress_dpm_setup_asic,	1361	.setup_asic = &cypress_dpm_setup_asic,
1362	.enable = &cypress_dpm_enable,	1362	.enable = &cypress_dpm_enable,
1363	.late_enable = &rv770_dpm_late_enable,	1363	.late_enable = &rv770_dpm_late_enable,
1364	.disable = &cypress_dpm_disable,	1364	.disable = &cypress_dpm_disable,
1365	.pre_set_power_state = &r600_dpm_pre_set_power_state,	1365	.pre_set_power_state = &r600_dpm_pre_set_power_state,
1366	.set_power_state = &cypress_dpm_set_power_state,	1366	.set_power_state = &cypress_dpm_set_power_state,
1367	.post_set_power_state = &r600_dpm_post_set_power_state,	1367	.post_set_power_state = &r600_dpm_post_set_power_state,
1368	.display_configuration_changed = &cypress_dpm_display_configuration_changed,	1368	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1369	.fini = &cypress_dpm_fini,	1369	.fini = &cypress_dpm_fini,
1370	.get_sclk = &rv770_dpm_get_sclk,	1370	.get_sclk = &rv770_dpm_get_sclk,
1371	.get_mclk = &rv770_dpm_get_mclk,	1371	.get_mclk = &rv770_dpm_get_mclk,
1372	.print_power_state = &rv770_dpm_print_power_state,	1372	.print_power_state = &rv770_dpm_print_power_state,
1373	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,	1373	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1374	.force_performance_level = &rv770_dpm_force_performance_level,	1374	.force_performance_level = &rv770_dpm_force_performance_level,
1375	.vblank_too_short = &cypress_dpm_vblank_too_short,	1375	.vblank_too_short = &cypress_dpm_vblank_too_short,
1376	},	1376	},
1377	.pflip = {	1377	.pflip = {
1378	.pre_page_flip = &evergreen_pre_page_flip,	1378	.pre_page_flip = &evergreen_pre_page_flip,
1379	.page_flip = &evergreen_page_flip,	1379	.page_flip = &evergreen_page_flip,
1380	.post_page_flip = &evergreen_post_page_flip,	1380	.post_page_flip = &evergreen_post_page_flip,
1381	},	1381	},
1382	};	1382	};
1383		1383
1384	static struct radeon_asic sumo_asic = {	1384	static struct radeon_asic sumo_asic = {
1385	.init = &evergreen_init,	1385	.init = &evergreen_init,
1386	.fini = &evergreen_fini,	1386	.fini = &evergreen_fini,
1387	.suspend = &evergreen_suspend,	1387	.suspend = &evergreen_suspend,
1388	.resume = &evergreen_resume,	1388	.resume = &evergreen_resume,
1389	.asic_reset = &evergreen_asic_reset,	1389	.asic_reset = &evergreen_asic_reset,
1390	.vga_set_state = &r600_vga_set_state,	1390	.vga_set_state = &r600_vga_set_state,
1391	.ioctl_wait_idle = r600_ioctl_wait_idle,	1391	.ioctl_wait_idle = r600_ioctl_wait_idle,
1392	.gui_idle = &r600_gui_idle,	1392	.gui_idle = &r600_gui_idle,
1393	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1393	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1394	.get_xclk = &r600_get_xclk,	1394	.get_xclk = &r600_get_xclk,
1395	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1395	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1396	.gart = {	1396	.gart = {
1397	.tlb_flush = &evergreen_pcie_gart_tlb_flush,	1397	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398	.set_page = &rs600_gart_set_page,	1398	.set_page = &rs600_gart_set_page,
1399	},	1399	},
1400	.ring = {	1400	.ring = {
1401	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,	1401	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1402	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,	1402	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1403	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1403	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1404	},	1404	},
1405	.irq = {	1405	.irq = {
1406	.set = &evergreen_irq_set,	1406	.set = &evergreen_irq_set,
1407	.process = &evergreen_irq_process,	1407	.process = &evergreen_irq_process,
1408	},	1408	},
1409	.display = {	1409	.display = {
1410	.bandwidth_update = &evergreen_bandwidth_update,	1410	.bandwidth_update = &evergreen_bandwidth_update,
1411	.get_vblank_counter = &evergreen_get_vblank_counter,	1411	.get_vblank_counter = &evergreen_get_vblank_counter,
1412	.wait_for_vblank = &dce4_wait_for_vblank,	1412	.wait_for_vblank = &dce4_wait_for_vblank,
1413	.set_backlight_level = &atombios_set_backlight_level,	1413	.set_backlight_level = &atombios_set_backlight_level,
1414	.get_backlight_level = &atombios_get_backlight_level,	1414	.get_backlight_level = &atombios_get_backlight_level,
1415	.hdmi_enable = &evergreen_hdmi_enable,	1415	.hdmi_enable = &evergreen_hdmi_enable,
1416	.hdmi_setmode = &evergreen_hdmi_setmode,	1416	.hdmi_setmode = &evergreen_hdmi_setmode,
1417	},	1417	},
1418	.copy = {	1418	.copy = {
1419	.blit = &r600_copy_cpdma,	1419	.blit = &r600_copy_cpdma,
1420	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1420	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1421	.dma = &evergreen_copy_dma,	1421	.dma = &evergreen_copy_dma,
1422	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1422	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1423	.copy = &evergreen_copy_dma,	1423	.copy = &evergreen_copy_dma,
1424	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1424	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1425	},	1425	},
1426	.surface = {	1426	.surface = {
1427	.set_reg = r600_set_surface_reg,	1427	.set_reg = r600_set_surface_reg,
1428	.clear_reg = r600_clear_surface_reg,	1428	.clear_reg = r600_clear_surface_reg,
1429	},	1429	},
1430	.hpd = {	1430	.hpd = {
1431	.init = &evergreen_hpd_init,	1431	.init = &evergreen_hpd_init,
1432	.fini = &evergreen_hpd_fini,	1432	.fini = &evergreen_hpd_fini,
1433	.sense = &evergreen_hpd_sense,	1433	.sense = &evergreen_hpd_sense,
1434	.set_polarity = &evergreen_hpd_set_polarity,	1434	.set_polarity = &evergreen_hpd_set_polarity,
1435	},	1435	},
1436	.pm = {	1436	.pm = {
1437	.misc = &evergreen_pm_misc,	1437	.misc = &evergreen_pm_misc,
1438	.prepare = &evergreen_pm_prepare,	1438	.prepare = &evergreen_pm_prepare,
1439	.finish = &evergreen_pm_finish,	1439	.finish = &evergreen_pm_finish,
1440	.init_profile = &sumo_pm_init_profile,	1440	.init_profile = &sumo_pm_init_profile,
1441	.get_dynpm_state = &r600_pm_get_dynpm_state,	1441	.get_dynpm_state = &r600_pm_get_dynpm_state,
1442	.get_engine_clock = &radeon_atom_get_engine_clock,	1442	.get_engine_clock = &radeon_atom_get_engine_clock,
1443	.set_engine_clock = &radeon_atom_set_engine_clock,	1443	.set_engine_clock = &radeon_atom_set_engine_clock,
1444	.get_memory_clock = NULL,	1444	.get_memory_clock = NULL,
1445	.set_memory_clock = NULL,	1445	.set_memory_clock = NULL,
1446	.get_pcie_lanes = NULL,	1446	.get_pcie_lanes = NULL,
1447	.set_pcie_lanes = NULL,	1447	.set_pcie_lanes = NULL,
1448	.set_clock_gating = NULL,	1448	.set_clock_gating = NULL,
1449	.set_uvd_clocks = &sumo_set_uvd_clocks,	1449	.set_uvd_clocks = &sumo_set_uvd_clocks,
1450	.get_temperature = &sumo_get_temp,	1450	.get_temperature = &sumo_get_temp,
1451	},	1451	},
1452	.dpm = {	1452	.dpm = {
1453	.init = &sumo_dpm_init,	1453	.init = &sumo_dpm_init,
1454	.setup_asic = &sumo_dpm_setup_asic,	1454	.setup_asic = &sumo_dpm_setup_asic,
1455	.enable = &sumo_dpm_enable,	1455	.enable = &sumo_dpm_enable,
1456	.late_enable = &sumo_dpm_late_enable,	1456	.late_enable = &sumo_dpm_late_enable,
1457	.disable = &sumo_dpm_disable,	1457	.disable = &sumo_dpm_disable,
1458	.pre_set_power_state = &sumo_dpm_pre_set_power_state,	1458	.pre_set_power_state = &sumo_dpm_pre_set_power_state,
1459	.set_power_state = &sumo_dpm_set_power_state,	1459	.set_power_state = &sumo_dpm_set_power_state,
1460	.post_set_power_state = &sumo_dpm_post_set_power_state,	1460	.post_set_power_state = &sumo_dpm_post_set_power_state,
1461	.display_configuration_changed = &sumo_dpm_display_configuration_changed,	1461	.display_configuration_changed = &sumo_dpm_display_configuration_changed,
1462	.fini = &sumo_dpm_fini,	1462	.fini = &sumo_dpm_fini,
1463	.get_sclk = &sumo_dpm_get_sclk,	1463	.get_sclk = &sumo_dpm_get_sclk,
1464	.get_mclk = &sumo_dpm_get_mclk,	1464	.get_mclk = &sumo_dpm_get_mclk,
1465	.print_power_state = &sumo_dpm_print_power_state,	1465	.print_power_state = &sumo_dpm_print_power_state,
1466	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,	1466	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1467	.force_performance_level = &sumo_dpm_force_performance_level,	1467	.force_performance_level = &sumo_dpm_force_performance_level,
1468	},	1468	},
1469	.pflip = {	1469	.pflip = {
1470	.pre_page_flip = &evergreen_pre_page_flip,	1470	.pre_page_flip = &evergreen_pre_page_flip,
1471	.page_flip = &evergreen_page_flip,	1471	.page_flip = &evergreen_page_flip,
1472	.post_page_flip = &evergreen_post_page_flip,	1472	.post_page_flip = &evergreen_post_page_flip,
1473	},	1473	},
1474	};	1474	};
1475		1475
1476	static struct radeon_asic btc_asic = {	1476	static struct radeon_asic btc_asic = {
1477	.init = &evergreen_init,	1477	.init = &evergreen_init,
1478	.fini = &evergreen_fini,	1478	.fini = &evergreen_fini,
1479	.suspend = &evergreen_suspend,	1479	.suspend = &evergreen_suspend,
1480	.resume = &evergreen_resume,	1480	.resume = &evergreen_resume,
1481	.asic_reset = &evergreen_asic_reset,	1481	.asic_reset = &evergreen_asic_reset,
1482	.vga_set_state = &r600_vga_set_state,	1482	.vga_set_state = &r600_vga_set_state,
1483	.ioctl_wait_idle = r600_ioctl_wait_idle,	1483	.ioctl_wait_idle = r600_ioctl_wait_idle,
1484	.gui_idle = &r600_gui_idle,	1484	.gui_idle = &r600_gui_idle,
1485	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1485	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1486	.get_xclk = &rv770_get_xclk,	1486	.get_xclk = &rv770_get_xclk,
1487	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1487	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1488	.gart = {	1488	.gart = {
1489	.tlb_flush = &evergreen_pcie_gart_tlb_flush,	1489	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1490	.set_page = &rs600_gart_set_page,	1490	.set_page = &rs600_gart_set_page,
1491	},	1491	},
1492	.ring = {	1492	.ring = {
1493	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,	1493	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1494	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,	1494	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1495	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,	1495	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1496	},	1496	},
1497	.irq = {	1497	.irq = {
1498	.set = &evergreen_irq_set,	1498	.set = &evergreen_irq_set,
1499	.process = &evergreen_irq_process,	1499	.process = &evergreen_irq_process,
1500	},	1500	},
1501	.display = {	1501	.display = {
1502	.bandwidth_update = &evergreen_bandwidth_update,	1502	.bandwidth_update = &evergreen_bandwidth_update,
1503	.get_vblank_counter = &evergreen_get_vblank_counter,	1503	.get_vblank_counter = &evergreen_get_vblank_counter,
1504	.wait_for_vblank = &dce4_wait_for_vblank,	1504	.wait_for_vblank = &dce4_wait_for_vblank,
1505	.set_backlight_level = &atombios_set_backlight_level,	1505	.set_backlight_level = &atombios_set_backlight_level,
1506	.get_backlight_level = &atombios_get_backlight_level,	1506	.get_backlight_level = &atombios_get_backlight_level,
1507	.hdmi_enable = &evergreen_hdmi_enable,	1507	.hdmi_enable = &evergreen_hdmi_enable,
1508	.hdmi_setmode = &evergreen_hdmi_setmode,	1508	.hdmi_setmode = &evergreen_hdmi_setmode,
1509	},	1509	},
1510	.copy = {	1510	.copy = {
1511	.blit = &r600_copy_cpdma,	1511	.blit = &r600_copy_cpdma,
1512	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1512	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1513	.dma = &evergreen_copy_dma,	1513	.dma = &evergreen_copy_dma,
1514	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1514	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1515	.copy = &evergreen_copy_dma,	1515	.copy = &evergreen_copy_dma,
1516	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1516	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1517	},	1517	},
1518	.surface = {	1518	.surface = {
1519	.set_reg = r600_set_surface_reg,	1519	.set_reg = r600_set_surface_reg,
1520	.clear_reg = r600_clear_surface_reg,	1520	.clear_reg = r600_clear_surface_reg,
1521	},	1521	},
1522	.hpd = {	1522	.hpd = {
1523	.init = &evergreen_hpd_init,	1523	.init = &evergreen_hpd_init,
1524	.fini = &evergreen_hpd_fini,	1524	.fini = &evergreen_hpd_fini,
1525	.sense = &evergreen_hpd_sense,	1525	.sense = &evergreen_hpd_sense,
1526	.set_polarity = &evergreen_hpd_set_polarity,	1526	.set_polarity = &evergreen_hpd_set_polarity,
1527	},	1527	},
1528	.pm = {	1528	.pm = {
1529	.misc = &evergreen_pm_misc,	1529	.misc = &evergreen_pm_misc,
1530	.prepare = &evergreen_pm_prepare,	1530	.prepare = &evergreen_pm_prepare,
1531	.finish = &evergreen_pm_finish,	1531	.finish = &evergreen_pm_finish,
1532	.init_profile = &btc_pm_init_profile,	1532	.init_profile = &btc_pm_init_profile,
1533	.get_dynpm_state = &r600_pm_get_dynpm_state,	1533	.get_dynpm_state = &r600_pm_get_dynpm_state,
1534	.get_engine_clock = &radeon_atom_get_engine_clock,	1534	.get_engine_clock = &radeon_atom_get_engine_clock,
1535	.set_engine_clock = &radeon_atom_set_engine_clock,	1535	.set_engine_clock = &radeon_atom_set_engine_clock,
1536	.get_memory_clock = &radeon_atom_get_memory_clock,	1536	.get_memory_clock = &radeon_atom_get_memory_clock,
1537	.set_memory_clock = &radeon_atom_set_memory_clock,	1537	.set_memory_clock = &radeon_atom_set_memory_clock,
1538	.get_pcie_lanes = &r600_get_pcie_lanes,	1538	.get_pcie_lanes = &r600_get_pcie_lanes,
1539	.set_pcie_lanes = &r600_set_pcie_lanes,	1539	.set_pcie_lanes = &r600_set_pcie_lanes,
1540	.set_clock_gating = NULL,	1540	.set_clock_gating = NULL,
1541	.set_uvd_clocks = &evergreen_set_uvd_clocks,	1541	.set_uvd_clocks = &evergreen_set_uvd_clocks,
1542	.get_temperature = &evergreen_get_temp,	1542	.get_temperature = &evergreen_get_temp,
1543	},	1543	},
1544	.dpm = {	1544	.dpm = {
1545	.init = &btc_dpm_init,	1545	.init = &btc_dpm_init,
1546	.setup_asic = &btc_dpm_setup_asic,	1546	.setup_asic = &btc_dpm_setup_asic,
1547	.enable = &btc_dpm_enable,	1547	.enable = &btc_dpm_enable,
1548	.late_enable = &rv770_dpm_late_enable,	1548	.late_enable = &rv770_dpm_late_enable,
1549	.disable = &btc_dpm_disable,	1549	.disable = &btc_dpm_disable,
1550	.pre_set_power_state = &btc_dpm_pre_set_power_state,	1550	.pre_set_power_state = &btc_dpm_pre_set_power_state,
1551	.set_power_state = &btc_dpm_set_power_state,	1551	.set_power_state = &btc_dpm_set_power_state,
1552	.post_set_power_state = &btc_dpm_post_set_power_state,	1552	.post_set_power_state = &btc_dpm_post_set_power_state,
1553	.display_configuration_changed = &cypress_dpm_display_configuration_changed,	1553	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1554	.fini = &btc_dpm_fini,	1554	.fini = &btc_dpm_fini,
1555	.get_sclk = &btc_dpm_get_sclk,	1555	.get_sclk = &btc_dpm_get_sclk,
1556	.get_mclk = &btc_dpm_get_mclk,	1556	.get_mclk = &btc_dpm_get_mclk,
1557	.print_power_state = &rv770_dpm_print_power_state,	1557	.print_power_state = &rv770_dpm_print_power_state,
1558	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,	1558	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1559	.force_performance_level = &rv770_dpm_force_performance_level,	1559	.force_performance_level = &rv770_dpm_force_performance_level,
1560	.vblank_too_short = &btc_dpm_vblank_too_short,	1560	.vblank_too_short = &btc_dpm_vblank_too_short,
1561	},	1561	},
1562	.pflip = {	1562	.pflip = {
1563	.pre_page_flip = &evergreen_pre_page_flip,	1563	.pre_page_flip = &evergreen_pre_page_flip,
1564	.page_flip = &evergreen_page_flip,	1564	.page_flip = &evergreen_page_flip,
1565	.post_page_flip = &evergreen_post_page_flip,	1565	.post_page_flip = &evergreen_post_page_flip,
1566	},	1566	},
1567	};	1567	};
1568		1568
1569	static struct radeon_asic_ring cayman_gfx_ring = {	1569	static struct radeon_asic_ring cayman_gfx_ring = {
1570	.ib_execute = &cayman_ring_ib_execute,	1570	.ib_execute = &cayman_ring_ib_execute,
1571	.ib_parse = &evergreen_ib_parse,	1571	.ib_parse = &evergreen_ib_parse,
1572	.emit_fence = &cayman_fence_ring_emit,	1572	.emit_fence = &cayman_fence_ring_emit,
1573	.emit_semaphore = &r600_semaphore_ring_emit,	1573	.emit_semaphore = &r600_semaphore_ring_emit,
1574	.cs_parse = &evergreen_cs_parse,	1574	.cs_parse = &evergreen_cs_parse,
1575	.ring_test = &r600_ring_test,	1575	.ring_test = &r600_ring_test,
1576	.ib_test = &r600_ib_test,	1576	.ib_test = &r600_ib_test,
1577	.is_lockup = &cayman_gfx_is_lockup,	1577	.is_lockup = &cayman_gfx_is_lockup,
1578	.vm_flush = &cayman_vm_flush,	1578	.vm_flush = &cayman_vm_flush,
1579	.get_rptr = &cayman_gfx_get_rptr,	1579	.get_rptr = &cayman_gfx_get_rptr,
1580	.get_wptr = &cayman_gfx_get_wptr,	1580	.get_wptr = &cayman_gfx_get_wptr,
1581	.set_wptr = &cayman_gfx_set_wptr,	1581	.set_wptr = &cayman_gfx_set_wptr,
1582	};	1582	};
1583		1583
1584	static struct radeon_asic_ring cayman_dma_ring = {	1584	static struct radeon_asic_ring cayman_dma_ring = {
1585	.ib_execute = &cayman_dma_ring_ib_execute,	1585	.ib_execute = &cayman_dma_ring_ib_execute,
1586	.ib_parse = &evergreen_dma_ib_parse,	1586	.ib_parse = &evergreen_dma_ib_parse,
1587	.emit_fence = &evergreen_dma_fence_ring_emit,	1587	.emit_fence = &evergreen_dma_fence_ring_emit,
1588	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1588	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1589	.cs_parse = &evergreen_dma_cs_parse,	1589	.cs_parse = &evergreen_dma_cs_parse,
1590	.ring_test = &r600_dma_ring_test,	1590	.ring_test = &r600_dma_ring_test,
1591	.ib_test = &r600_dma_ib_test,	1591	.ib_test = &r600_dma_ib_test,
1592	.is_lockup = &cayman_dma_is_lockup,	1592	.is_lockup = &cayman_dma_is_lockup,
1593	.vm_flush = &cayman_dma_vm_flush,	1593	.vm_flush = &cayman_dma_vm_flush,
1594	.get_rptr = &cayman_dma_get_rptr,	1594	.get_rptr = &cayman_dma_get_rptr,
1595	.get_wptr = &cayman_dma_get_wptr,	1595	.get_wptr = &cayman_dma_get_wptr,
1596	.set_wptr = &cayman_dma_set_wptr	1596	.set_wptr = &cayman_dma_set_wptr
1597	};	1597	};
1598		1598
1599	static struct radeon_asic_ring cayman_uvd_ring = {	1599	static struct radeon_asic_ring cayman_uvd_ring = {
1600	.ib_execute = &uvd_v1_0_ib_execute,	1600	.ib_execute = &uvd_v1_0_ib_execute,
1601	.emit_fence = &uvd_v2_2_fence_emit,	1601	.emit_fence = &uvd_v2_2_fence_emit,
1602	.emit_semaphore = &uvd_v3_1_semaphore_emit,	1602	.emit_semaphore = &uvd_v3_1_semaphore_emit,
1603	.cs_parse = &radeon_uvd_cs_parse,	1603	.cs_parse = &radeon_uvd_cs_parse,
1604	.ring_test = &uvd_v1_0_ring_test,	1604	.ring_test = &uvd_v1_0_ring_test,
1605	.ib_test = &uvd_v1_0_ib_test,	1605	.ib_test = &uvd_v1_0_ib_test,
1606	.is_lockup = &radeon_ring_test_lockup,	1606	.is_lockup = &radeon_ring_test_lockup,
1607	.get_rptr = &uvd_v1_0_get_rptr,	1607	.get_rptr = &uvd_v1_0_get_rptr,
1608	.get_wptr = &uvd_v1_0_get_wptr,	1608	.get_wptr = &uvd_v1_0_get_wptr,
1609	.set_wptr = &uvd_v1_0_set_wptr,	1609	.set_wptr = &uvd_v1_0_set_wptr,
1610	};	1610	};
1611		1611
1612	static struct radeon_asic cayman_asic = {	1612	static struct radeon_asic cayman_asic = {
1613	.init = &cayman_init,	1613	.init = &cayman_init,
1614	.fini = &cayman_fini,	1614	.fini = &cayman_fini,
1615	.suspend = &cayman_suspend,	1615	.suspend = &cayman_suspend,
1616	.resume = &cayman_resume,	1616	.resume = &cayman_resume,
1617	.asic_reset = &cayman_asic_reset,	1617	.asic_reset = &cayman_asic_reset,
1618	.vga_set_state = &r600_vga_set_state,	1618	.vga_set_state = &r600_vga_set_state,
1619	.ioctl_wait_idle = r600_ioctl_wait_idle,	1619	.ioctl_wait_idle = r600_ioctl_wait_idle,
1620	.gui_idle = &r600_gui_idle,	1620	.gui_idle = &r600_gui_idle,
1621	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1621	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1622	.get_xclk = &rv770_get_xclk,	1622	.get_xclk = &rv770_get_xclk,
1623	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1623	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1624	.gart = {	1624	.gart = {
1625	.tlb_flush = &cayman_pcie_gart_tlb_flush,	1625	.tlb_flush = &cayman_pcie_gart_tlb_flush,
1626	.set_page = &rs600_gart_set_page,	1626	.set_page = &rs600_gart_set_page,
1627	},	1627	},
1628	.vm = {	1628	.vm = {
1629	.init = &cayman_vm_init,	1629	.init = &cayman_vm_init,
1630	.fini = &cayman_vm_fini,	1630	.fini = &cayman_vm_fini,
1631	.set_page = &cayman_dma_vm_set_page,	1631	.set_page = &cayman_dma_vm_set_page,
1632	},	1632	},
1633	.ring = {	1633	.ring = {
1634	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,	1634	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1635	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,	1635	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1636	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,	1636	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1637	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,	1637	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1638	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,	1638	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1639	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	1639	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1640	},	1640	},
1641	.irq = {	1641	.irq = {
1642	.set = &evergreen_irq_set,	1642	.set = &evergreen_irq_set,
1643	.process = &evergreen_irq_process,	1643	.process = &evergreen_irq_process,
1644	},	1644	},
1645	.display = {	1645	.display = {
1646	.bandwidth_update = &evergreen_bandwidth_update,	1646	.bandwidth_update = &evergreen_bandwidth_update,
1647	.get_vblank_counter = &evergreen_get_vblank_counter,	1647	.get_vblank_counter = &evergreen_get_vblank_counter,
1648	.wait_for_vblank = &dce4_wait_for_vblank,	1648	.wait_for_vblank = &dce4_wait_for_vblank,
1649	.set_backlight_level = &atombios_set_backlight_level,	1649	.set_backlight_level = &atombios_set_backlight_level,
1650	.get_backlight_level = &atombios_get_backlight_level,	1650	.get_backlight_level = &atombios_get_backlight_level,
1651	.hdmi_enable = &evergreen_hdmi_enable,	1651	.hdmi_enable = &evergreen_hdmi_enable,
1652	.hdmi_setmode = &evergreen_hdmi_setmode,	1652	.hdmi_setmode = &evergreen_hdmi_setmode,
1653	},	1653	},
1654	.copy = {	1654	.copy = {
1655	.blit = &r600_copy_cpdma,	1655	.blit = &r600_copy_cpdma,
1656	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1656	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1657	.dma = &evergreen_copy_dma,	1657	.dma = &evergreen_copy_dma,
1658	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1658	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1659	.copy = &evergreen_copy_dma,	1659	.copy = &evergreen_copy_dma,
1660	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1660	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1661	},	1661	},
1662	.surface = {	1662	.surface = {
1663	.set_reg = r600_set_surface_reg,	1663	.set_reg = r600_set_surface_reg,
1664	.clear_reg = r600_clear_surface_reg,	1664	.clear_reg = r600_clear_surface_reg,
1665	},	1665	},
1666	.hpd = {	1666	.hpd = {
1667	.init = &evergreen_hpd_init,	1667	.init = &evergreen_hpd_init,
1668	.fini = &evergreen_hpd_fini,	1668	.fini = &evergreen_hpd_fini,
1669	.sense = &evergreen_hpd_sense,	1669	.sense = &evergreen_hpd_sense,
1670	.set_polarity = &evergreen_hpd_set_polarity,	1670	.set_polarity = &evergreen_hpd_set_polarity,
1671	},	1671	},
1672	.pm = {	1672	.pm = {
1673	.misc = &evergreen_pm_misc,	1673	.misc = &evergreen_pm_misc,
1674	.prepare = &evergreen_pm_prepare,	1674	.prepare = &evergreen_pm_prepare,
1675	.finish = &evergreen_pm_finish,	1675	.finish = &evergreen_pm_finish,
1676	.init_profile = &btc_pm_init_profile,	1676	.init_profile = &btc_pm_init_profile,
1677	.get_dynpm_state = &r600_pm_get_dynpm_state,	1677	.get_dynpm_state = &r600_pm_get_dynpm_state,
1678	.get_engine_clock = &radeon_atom_get_engine_clock,	1678	.get_engine_clock = &radeon_atom_get_engine_clock,
1679	.set_engine_clock = &radeon_atom_set_engine_clock,	1679	.set_engine_clock = &radeon_atom_set_engine_clock,
1680	.get_memory_clock = &radeon_atom_get_memory_clock,	1680	.get_memory_clock = &radeon_atom_get_memory_clock,
1681	.set_memory_clock = &radeon_atom_set_memory_clock,	1681	.set_memory_clock = &radeon_atom_set_memory_clock,
1682	.get_pcie_lanes = &r600_get_pcie_lanes,	1682	.get_pcie_lanes = &r600_get_pcie_lanes,
1683	.set_pcie_lanes = &r600_set_pcie_lanes,	1683	.set_pcie_lanes = &r600_set_pcie_lanes,
1684	.set_clock_gating = NULL,	1684	.set_clock_gating = NULL,
1685	.set_uvd_clocks = &evergreen_set_uvd_clocks,	1685	.set_uvd_clocks = &evergreen_set_uvd_clocks,
1686	.get_temperature = &evergreen_get_temp,	1686	.get_temperature = &evergreen_get_temp,
1687	},	1687	},
1688	.dpm = {	1688	.dpm = {
1689	.init = &ni_dpm_init,	1689	.init = &ni_dpm_init,
1690	.setup_asic = &ni_dpm_setup_asic,	1690	.setup_asic = &ni_dpm_setup_asic,
1691	.enable = &ni_dpm_enable,	1691	.enable = &ni_dpm_enable,
1692	.late_enable = &rv770_dpm_late_enable,	1692	.late_enable = &rv770_dpm_late_enable,
1693	.disable = &ni_dpm_disable,	1693	.disable = &ni_dpm_disable,
1694	.pre_set_power_state = &ni_dpm_pre_set_power_state,	1694	.pre_set_power_state = &ni_dpm_pre_set_power_state,
1695	.set_power_state = &ni_dpm_set_power_state,	1695	.set_power_state = &ni_dpm_set_power_state,
1696	.post_set_power_state = &ni_dpm_post_set_power_state,	1696	.post_set_power_state = &ni_dpm_post_set_power_state,
1697	.display_configuration_changed = &cypress_dpm_display_configuration_changed,	1697	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1698	.fini = &ni_dpm_fini,	1698	.fini = &ni_dpm_fini,
1699	.get_sclk = &ni_dpm_get_sclk,	1699	.get_sclk = &ni_dpm_get_sclk,
1700	.get_mclk = &ni_dpm_get_mclk,	1700	.get_mclk = &ni_dpm_get_mclk,
1701	.print_power_state = &ni_dpm_print_power_state,	1701	.print_power_state = &ni_dpm_print_power_state,
1702	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,	1702	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1703	.force_performance_level = &ni_dpm_force_performance_level,	1703	.force_performance_level = &ni_dpm_force_performance_level,
1704	.vblank_too_short = &ni_dpm_vblank_too_short,	1704	.vblank_too_short = &ni_dpm_vblank_too_short,
1705	},	1705	},
1706	.pflip = {	1706	.pflip = {
1707	.pre_page_flip = &evergreen_pre_page_flip,	1707	.pre_page_flip = &evergreen_pre_page_flip,
1708	.page_flip = &evergreen_page_flip,	1708	.page_flip = &evergreen_page_flip,
1709	.post_page_flip = &evergreen_post_page_flip,	1709	.post_page_flip = &evergreen_post_page_flip,
1710	},	1710	},
1711	};	1711	};
1712		1712
1713	static struct radeon_asic trinity_asic = {	1713	static struct radeon_asic trinity_asic = {
1714	.init = &cayman_init,	1714	.init = &cayman_init,
1715	.fini = &cayman_fini,	1715	.fini = &cayman_fini,
1716	.suspend = &cayman_suspend,	1716	.suspend = &cayman_suspend,
1717	.resume = &cayman_resume,	1717	.resume = &cayman_resume,
1718	.asic_reset = &cayman_asic_reset,	1718	.asic_reset = &cayman_asic_reset,
1719	.vga_set_state = &r600_vga_set_state,	1719	.vga_set_state = &r600_vga_set_state,
1720	.ioctl_wait_idle = r600_ioctl_wait_idle,	1720	.ioctl_wait_idle = r600_ioctl_wait_idle,
1721	.gui_idle = &r600_gui_idle,	1721	.gui_idle = &r600_gui_idle,
1722	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1722	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1723	.get_xclk = &r600_get_xclk,	1723	.get_xclk = &r600_get_xclk,
1724	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1724	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1725	.gart = {	1725	.gart = {
1726	.tlb_flush = &cayman_pcie_gart_tlb_flush,	1726	.tlb_flush = &cayman_pcie_gart_tlb_flush,
1727	.set_page = &rs600_gart_set_page,	1727	.set_page = &rs600_gart_set_page,
1728	},	1728	},
1729	.vm = {	1729	.vm = {
1730	.init = &cayman_vm_init,	1730	.init = &cayman_vm_init,
1731	.fini = &cayman_vm_fini,	1731	.fini = &cayman_vm_fini,
1732	.set_page = &cayman_dma_vm_set_page,	1732	.set_page = &cayman_dma_vm_set_page,
1733	},	1733	},
1734	.ring = {	1734	.ring = {
1735	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,	1735	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1736	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,	1736	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1737	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,	1737	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1738	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,	1738	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1739	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,	1739	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1740	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	1740	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1741	},	1741	},
1742	.irq = {	1742	.irq = {
1743	.set = &evergreen_irq_set,	1743	.set = &evergreen_irq_set,
1744	.process = &evergreen_irq_process,	1744	.process = &evergreen_irq_process,
1745	},	1745	},
1746	.display = {	1746	.display = {
1747	.bandwidth_update = &dce6_bandwidth_update,	1747	.bandwidth_update = &dce6_bandwidth_update,
1748	.get_vblank_counter = &evergreen_get_vblank_counter,	1748	.get_vblank_counter = &evergreen_get_vblank_counter,
1749	.wait_for_vblank = &dce4_wait_for_vblank,	1749	.wait_for_vblank = &dce4_wait_for_vblank,
1750	.set_backlight_level = &atombios_set_backlight_level,	1750	.set_backlight_level = &atombios_set_backlight_level,
1751	.get_backlight_level = &atombios_get_backlight_level,	1751	.get_backlight_level = &atombios_get_backlight_level,
1752	.hdmi_enable = &evergreen_hdmi_enable,	1752	.hdmi_enable = &evergreen_hdmi_enable,
1753	.hdmi_setmode = &evergreen_hdmi_setmode,	1753	.hdmi_setmode = &evergreen_hdmi_setmode,
1754	},	1754	},
1755	.copy = {	1755	.copy = {
1756	.blit = &r600_copy_cpdma,	1756	.blit = &r600_copy_cpdma,
1757	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1757	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1758	.dma = &evergreen_copy_dma,	1758	.dma = &evergreen_copy_dma,
1759	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1759	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1760	.copy = &evergreen_copy_dma,	1760	.copy = &evergreen_copy_dma,
1761	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1761	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1762	},	1762	},
1763	.surface = {	1763	.surface = {
1764	.set_reg = r600_set_surface_reg,	1764	.set_reg = r600_set_surface_reg,
1765	.clear_reg = r600_clear_surface_reg,	1765	.clear_reg = r600_clear_surface_reg,
1766	},	1766	},
1767	.hpd = {	1767	.hpd = {
1768	.init = &evergreen_hpd_init,	1768	.init = &evergreen_hpd_init,
1769	.fini = &evergreen_hpd_fini,	1769	.fini = &evergreen_hpd_fini,
1770	.sense = &evergreen_hpd_sense,	1770	.sense = &evergreen_hpd_sense,
1771	.set_polarity = &evergreen_hpd_set_polarity,	1771	.set_polarity = &evergreen_hpd_set_polarity,
1772	},	1772	},
1773	.pm = {	1773	.pm = {
1774	.misc = &evergreen_pm_misc,	1774	.misc = &evergreen_pm_misc,
1775	.prepare = &evergreen_pm_prepare,	1775	.prepare = &evergreen_pm_prepare,
1776	.finish = &evergreen_pm_finish,	1776	.finish = &evergreen_pm_finish,
1777	.init_profile = &sumo_pm_init_profile,	1777	.init_profile = &sumo_pm_init_profile,
1778	.get_dynpm_state = &r600_pm_get_dynpm_state,	1778	.get_dynpm_state = &r600_pm_get_dynpm_state,
1779	.get_engine_clock = &radeon_atom_get_engine_clock,	1779	.get_engine_clock = &radeon_atom_get_engine_clock,
1780	.set_engine_clock = &radeon_atom_set_engine_clock,	1780	.set_engine_clock = &radeon_atom_set_engine_clock,
1781	.get_memory_clock = NULL,	1781	.get_memory_clock = NULL,
1782	.set_memory_clock = NULL,	1782	.set_memory_clock = NULL,
1783	.get_pcie_lanes = NULL,	1783	.get_pcie_lanes = NULL,
1784	.set_pcie_lanes = NULL,	1784	.set_pcie_lanes = NULL,
1785	.set_clock_gating = NULL,	1785	.set_clock_gating = NULL,
1786	.set_uvd_clocks = &sumo_set_uvd_clocks,	1786	.set_uvd_clocks = &sumo_set_uvd_clocks,
1787	.get_temperature = &tn_get_temp,	1787	.get_temperature = &tn_get_temp,
1788	},	1788	},
1789	.dpm = {	1789	.dpm = {
1790	.init = &trinity_dpm_init,	1790	.init = &trinity_dpm_init,
1791	.setup_asic = &trinity_dpm_setup_asic,	1791	.setup_asic = &trinity_dpm_setup_asic,
1792	.enable = &trinity_dpm_enable,	1792	.enable = &trinity_dpm_enable,
1793	.late_enable = &trinity_dpm_late_enable,	1793	.late_enable = &trinity_dpm_late_enable,
1794	.disable = &trinity_dpm_disable,	1794	.disable = &trinity_dpm_disable,
1795	.pre_set_power_state = &trinity_dpm_pre_set_power_state,	1795	.pre_set_power_state = &trinity_dpm_pre_set_power_state,
1796	.set_power_state = &trinity_dpm_set_power_state,	1796	.set_power_state = &trinity_dpm_set_power_state,
1797	.post_set_power_state = &trinity_dpm_post_set_power_state,	1797	.post_set_power_state = &trinity_dpm_post_set_power_state,
1798	.display_configuration_changed = &trinity_dpm_display_configuration_changed,	1798	.display_configuration_changed = &trinity_dpm_display_configuration_changed,
1799	.fini = &trinity_dpm_fini,	1799	.fini = &trinity_dpm_fini,
1800	.get_sclk = &trinity_dpm_get_sclk,	1800	.get_sclk = &trinity_dpm_get_sclk,
1801	.get_mclk = &trinity_dpm_get_mclk,	1801	.get_mclk = &trinity_dpm_get_mclk,
1802	.print_power_state = &trinity_dpm_print_power_state,	1802	.print_power_state = &trinity_dpm_print_power_state,
1803	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,	1803	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1804	.force_performance_level = &trinity_dpm_force_performance_level,	1804	.force_performance_level = &trinity_dpm_force_performance_level,
1805	.enable_bapm = &trinity_dpm_enable_bapm,	1805	.enable_bapm = &trinity_dpm_enable_bapm,
1806	},	1806	},
1807	.pflip = {	1807	.pflip = {
1808	.pre_page_flip = &evergreen_pre_page_flip,	1808	.pre_page_flip = &evergreen_pre_page_flip,
1809	.page_flip = &evergreen_page_flip,	1809	.page_flip = &evergreen_page_flip,
1810	.post_page_flip = &evergreen_post_page_flip,	1810	.post_page_flip = &evergreen_post_page_flip,
1811	},	1811	},
1812	};	1812	};
1813		1813
1814	static struct radeon_asic_ring si_gfx_ring = {	1814	static struct radeon_asic_ring si_gfx_ring = {
1815	.ib_execute = &si_ring_ib_execute,	1815	.ib_execute = &si_ring_ib_execute,
1816	.ib_parse = &si_ib_parse,	1816	.ib_parse = &si_ib_parse,
1817	.emit_fence = &si_fence_ring_emit,	1817	.emit_fence = &si_fence_ring_emit,
1818	.emit_semaphore = &r600_semaphore_ring_emit,	1818	.emit_semaphore = &r600_semaphore_ring_emit,
1819	.cs_parse = NULL,	1819	.cs_parse = NULL,
1820	.ring_test = &r600_ring_test,	1820	.ring_test = &r600_ring_test,
1821	.ib_test = &r600_ib_test,	1821	.ib_test = &r600_ib_test,
1822	.is_lockup = &si_gfx_is_lockup,	1822	.is_lockup = &si_gfx_is_lockup,
1823	.vm_flush = &si_vm_flush,	1823	.vm_flush = &si_vm_flush,
1824	.get_rptr = &cayman_gfx_get_rptr,	1824	.get_rptr = &cayman_gfx_get_rptr,
1825	.get_wptr = &cayman_gfx_get_wptr,	1825	.get_wptr = &cayman_gfx_get_wptr,
1826	.set_wptr = &cayman_gfx_set_wptr,	1826	.set_wptr = &cayman_gfx_set_wptr,
1827	};	1827	};
1828		1828
1829	static struct radeon_asic_ring si_dma_ring = {	1829	static struct radeon_asic_ring si_dma_ring = {
1830	.ib_execute = &cayman_dma_ring_ib_execute,	1830	.ib_execute = &cayman_dma_ring_ib_execute,
1831	.ib_parse = &evergreen_dma_ib_parse,	1831	.ib_parse = &evergreen_dma_ib_parse,
1832	.emit_fence = &evergreen_dma_fence_ring_emit,	1832	.emit_fence = &evergreen_dma_fence_ring_emit,
1833	.emit_semaphore = &r600_dma_semaphore_ring_emit,	1833	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1834	.cs_parse = NULL,	1834	.cs_parse = NULL,
1835	.ring_test = &r600_dma_ring_test,	1835	.ring_test = &r600_dma_ring_test,
1836	.ib_test = &r600_dma_ib_test,	1836	.ib_test = &r600_dma_ib_test,
1837	.is_lockup = &si_dma_is_lockup,	1837	.is_lockup = &si_dma_is_lockup,
1838	.vm_flush = &si_dma_vm_flush,	1838	.vm_flush = &si_dma_vm_flush,
1839	.get_rptr = &cayman_dma_get_rptr,	1839	.get_rptr = &cayman_dma_get_rptr,
1840	.get_wptr = &cayman_dma_get_wptr,	1840	.get_wptr = &cayman_dma_get_wptr,
1841	.set_wptr = &cayman_dma_set_wptr,	1841	.set_wptr = &cayman_dma_set_wptr,
1842	};	1842	};
1843		1843
1844	static struct radeon_asic si_asic = {	1844	static struct radeon_asic si_asic = {
1845	.init = &si_init,	1845	.init = &si_init,
1846	.fini = &si_fini,	1846	.fini = &si_fini,
1847	.suspend = &si_suspend,	1847	.suspend = &si_suspend,
1848	.resume = &si_resume,	1848	.resume = &si_resume,
1849	.asic_reset = &si_asic_reset,	1849	.asic_reset = &si_asic_reset,
1850	.vga_set_state = &r600_vga_set_state,	1850	.vga_set_state = &r600_vga_set_state,
1851	.ioctl_wait_idle = r600_ioctl_wait_idle,	1851	.ioctl_wait_idle = r600_ioctl_wait_idle,
1852	.gui_idle = &r600_gui_idle,	1852	.gui_idle = &r600_gui_idle,
1853	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	1853	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1854	.get_xclk = &si_get_xclk,	1854	.get_xclk = &si_get_xclk,
1855	.get_gpu_clock_counter = &si_get_gpu_clock_counter,	1855	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
1856	.gart = {	1856	.gart = {
1857	.tlb_flush = &si_pcie_gart_tlb_flush,	1857	.tlb_flush = &si_pcie_gart_tlb_flush,
1858	.set_page = &rs600_gart_set_page,	1858	.set_page = &rs600_gart_set_page,
1859	},	1859	},
1860	.vm = {	1860	.vm = {
1861	.init = &si_vm_init,	1861	.init = &si_vm_init,
1862	.fini = &si_vm_fini,	1862	.fini = &si_vm_fini,
1863	.set_page = &si_dma_vm_set_page,	1863	.set_page = &si_dma_vm_set_page,
1864	},	1864	},
1865	.ring = {	1865	.ring = {
1866	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,	1866	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1867	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,	1867	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1868	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,	1868	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1869	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,	1869	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1870	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,	1870	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1871	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	1871	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1872	},	1872	},
1873	.irq = {	1873	.irq = {
1874	.set = &si_irq_set,	1874	.set = &si_irq_set,
1875	.process = &si_irq_process,	1875	.process = &si_irq_process,
1876	},	1876	},
1877	.display = {	1877	.display = {
1878	.bandwidth_update = &dce6_bandwidth_update,	1878	.bandwidth_update = &dce6_bandwidth_update,
1879	.get_vblank_counter = &evergreen_get_vblank_counter,	1879	.get_vblank_counter = &evergreen_get_vblank_counter,
1880	.wait_for_vblank = &dce4_wait_for_vblank,	1880	.wait_for_vblank = &dce4_wait_for_vblank,
1881	.set_backlight_level = &atombios_set_backlight_level,	1881	.set_backlight_level = &atombios_set_backlight_level,
1882	.get_backlight_level = &atombios_get_backlight_level,	1882	.get_backlight_level = &atombios_get_backlight_level,
1883	.hdmi_enable = &evergreen_hdmi_enable,	1883	.hdmi_enable = &evergreen_hdmi_enable,
1884	.hdmi_setmode = &evergreen_hdmi_setmode,	1884	.hdmi_setmode = &evergreen_hdmi_setmode,
1885	},	1885	},
1886	.copy = {	1886	.copy = {
1887	.blit = &r600_copy_cpdma,	1887	.blit = &r600_copy_cpdma,
1888	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1888	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1889	.dma = &si_copy_dma,	1889	.dma = &si_copy_dma,
1890	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	1890	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1891	.copy = &si_copy_dma,	1891	.copy = &si_copy_dma,
1892	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	1892	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1893	},	1893	},
1894	.surface = {	1894	.surface = {
1895	.set_reg = r600_set_surface_reg,	1895	.set_reg = r600_set_surface_reg,
1896	.clear_reg = r600_clear_surface_reg,	1896	.clear_reg = r600_clear_surface_reg,
1897	},	1897	},
1898	.hpd = {	1898	.hpd = {
1899	.init = &evergreen_hpd_init,	1899	.init = &evergreen_hpd_init,
1900	.fini = &evergreen_hpd_fini,	1900	.fini = &evergreen_hpd_fini,
1901	.sense = &evergreen_hpd_sense,	1901	.sense = &evergreen_hpd_sense,
1902	.set_polarity = &evergreen_hpd_set_polarity,	1902	.set_polarity = &evergreen_hpd_set_polarity,
1903	},	1903	},
1904	.pm = {	1904	.pm = {
1905	.misc = &evergreen_pm_misc,	1905	.misc = &evergreen_pm_misc,
1906	.prepare = &evergreen_pm_prepare,	1906	.prepare = &evergreen_pm_prepare,
1907	.finish = &evergreen_pm_finish,	1907	.finish = &evergreen_pm_finish,
1908	.init_profile = &sumo_pm_init_profile,	1908	.init_profile = &sumo_pm_init_profile,
1909	.get_dynpm_state = &r600_pm_get_dynpm_state,	1909	.get_dynpm_state = &r600_pm_get_dynpm_state,
1910	.get_engine_clock = &radeon_atom_get_engine_clock,	1910	.get_engine_clock = &radeon_atom_get_engine_clock,
1911	.set_engine_clock = &radeon_atom_set_engine_clock,	1911	.set_engine_clock = &radeon_atom_set_engine_clock,
1912	.get_memory_clock = &radeon_atom_get_memory_clock,	1912	.get_memory_clock = &radeon_atom_get_memory_clock,
1913	.set_memory_clock = &radeon_atom_set_memory_clock,	1913	.set_memory_clock = &radeon_atom_set_memory_clock,
1914	.get_pcie_lanes = &r600_get_pcie_lanes,	1914	.get_pcie_lanes = &r600_get_pcie_lanes,
1915	.set_pcie_lanes = &r600_set_pcie_lanes,	1915	.set_pcie_lanes = &r600_set_pcie_lanes,
1916	.set_clock_gating = NULL,	1916	.set_clock_gating = NULL,
1917	.set_uvd_clocks = &si_set_uvd_clocks,	1917	.set_uvd_clocks = &si_set_uvd_clocks,
1918	.get_temperature = &si_get_temp,	1918	.get_temperature = &si_get_temp,
1919	},	1919	},
1920	.dpm = {	1920	.dpm = {
1921	.init = &si_dpm_init,	1921	.init = &si_dpm_init,
1922	.setup_asic = &si_dpm_setup_asic,	1922	.setup_asic = &si_dpm_setup_asic,
1923	.enable = &si_dpm_enable,	1923	.enable = &si_dpm_enable,
1924	.late_enable = &si_dpm_late_enable,	1924	.late_enable = &si_dpm_late_enable,
1925	.disable = &si_dpm_disable,	1925	.disable = &si_dpm_disable,
1926	.pre_set_power_state = &si_dpm_pre_set_power_state,	1926	.pre_set_power_state = &si_dpm_pre_set_power_state,
1927	.set_power_state = &si_dpm_set_power_state,	1927	.set_power_state = &si_dpm_set_power_state,
1928	.post_set_power_state = &si_dpm_post_set_power_state,	1928	.post_set_power_state = &si_dpm_post_set_power_state,
1929	.display_configuration_changed = &si_dpm_display_configuration_changed,	1929	.display_configuration_changed = &si_dpm_display_configuration_changed,
1930	.fini = &si_dpm_fini,	1930	.fini = &si_dpm_fini,
1931	.get_sclk = &ni_dpm_get_sclk,	1931	.get_sclk = &ni_dpm_get_sclk,
1932	.get_mclk = &ni_dpm_get_mclk,	1932	.get_mclk = &ni_dpm_get_mclk,
1933	.print_power_state = &ni_dpm_print_power_state,	1933	.print_power_state = &ni_dpm_print_power_state,
1934	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,	1934	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1935	.force_performance_level = &si_dpm_force_performance_level,	1935	.force_performance_level = &si_dpm_force_performance_level,
1936	.vblank_too_short = &ni_dpm_vblank_too_short,	1936	.vblank_too_short = &ni_dpm_vblank_too_short,
1937	},	1937	},
1938	.pflip = {	1938	.pflip = {
1939	.pre_page_flip = &evergreen_pre_page_flip,	1939	.pre_page_flip = &evergreen_pre_page_flip,
1940	.page_flip = &evergreen_page_flip,	1940	.page_flip = &evergreen_page_flip,
1941	.post_page_flip = &evergreen_post_page_flip,	1941	.post_page_flip = &evergreen_post_page_flip,
1942	},	1942	},
1943	};	1943	};
1944		1944
1945	static struct radeon_asic_ring ci_gfx_ring = {	1945	static struct radeon_asic_ring ci_gfx_ring = {
1946	.ib_execute = &cik_ring_ib_execute,	1946	.ib_execute = &cik_ring_ib_execute,
1947	.ib_parse = &cik_ib_parse,	1947	.ib_parse = &cik_ib_parse,
1948	.emit_fence = &cik_fence_gfx_ring_emit,	1948	.emit_fence = &cik_fence_gfx_ring_emit,
1949	.emit_semaphore = &cik_semaphore_ring_emit,	1949	.emit_semaphore = &cik_semaphore_ring_emit,
1950	.cs_parse = NULL,	1950	.cs_parse = NULL,
1951	.ring_test = &cik_ring_test,	1951	.ring_test = &cik_ring_test,
1952	.ib_test = &cik_ib_test,	1952	.ib_test = &cik_ib_test,
1953	.is_lockup = &cik_gfx_is_lockup,	1953	.is_lockup = &cik_gfx_is_lockup,
1954	.vm_flush = &cik_vm_flush,	1954	.vm_flush = &cik_vm_flush,
1955	.get_rptr = &cik_gfx_get_rptr,	1955	.get_rptr = &cik_gfx_get_rptr,
1956	.get_wptr = &cik_gfx_get_wptr,	1956	.get_wptr = &cik_gfx_get_wptr,
1957	.set_wptr = &cik_gfx_set_wptr,	1957	.set_wptr = &cik_gfx_set_wptr,
1958	};	1958	};
1959		1959
1960	static struct radeon_asic_ring ci_cp_ring = {	1960	static struct radeon_asic_ring ci_cp_ring = {
1961	.ib_execute = &cik_ring_ib_execute,	1961	.ib_execute = &cik_ring_ib_execute,
1962	.ib_parse = &cik_ib_parse,	1962	.ib_parse = &cik_ib_parse,
1963	.emit_fence = &cik_fence_compute_ring_emit,	1963	.emit_fence = &cik_fence_compute_ring_emit,
1964	.emit_semaphore = &cik_semaphore_ring_emit,	1964	.emit_semaphore = &cik_semaphore_ring_emit,
1965	.cs_parse = NULL,	1965	.cs_parse = NULL,
1966	.ring_test = &cik_ring_test,	1966	.ring_test = &cik_ring_test,
1967	.ib_test = &cik_ib_test,	1967	.ib_test = &cik_ib_test,
1968	.is_lockup = &cik_gfx_is_lockup,	1968	.is_lockup = &cik_gfx_is_lockup,
1969	.vm_flush = &cik_vm_flush,	1969	.vm_flush = &cik_vm_flush,
1970	.get_rptr = &cik_compute_get_rptr,	1970	.get_rptr = &cik_compute_get_rptr,
1971	.get_wptr = &cik_compute_get_wptr,	1971	.get_wptr = &cik_compute_get_wptr,
1972	.set_wptr = &cik_compute_set_wptr,	1972	.set_wptr = &cik_compute_set_wptr,
1973	};	1973	};
1974		1974
1975	static struct radeon_asic_ring ci_dma_ring = {	1975	static struct radeon_asic_ring ci_dma_ring = {
1976	.ib_execute = &cik_sdma_ring_ib_execute,	1976	.ib_execute = &cik_sdma_ring_ib_execute,
1977	.ib_parse = &cik_ib_parse,	1977	.ib_parse = &cik_ib_parse,
1978	.emit_fence = &cik_sdma_fence_ring_emit,	1978	.emit_fence = &cik_sdma_fence_ring_emit,
1979	.emit_semaphore = &cik_sdma_semaphore_ring_emit,	1979	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
1980	.cs_parse = NULL,	1980	.cs_parse = NULL,
1981	.ring_test = &cik_sdma_ring_test,	1981	.ring_test = &cik_sdma_ring_test,
1982	.ib_test = &cik_sdma_ib_test,	1982	.ib_test = &cik_sdma_ib_test,
1983	.is_lockup = &cik_sdma_is_lockup,	1983	.is_lockup = &cik_sdma_is_lockup,
1984	.vm_flush = &cik_dma_vm_flush,	1984	.vm_flush = &cik_dma_vm_flush,
1985	.get_rptr = &cik_sdma_get_rptr,	1985	.get_rptr = &cik_sdma_get_rptr,
1986	.get_wptr = &cik_sdma_get_wptr,	1986	.get_wptr = &cik_sdma_get_wptr,
1987	.set_wptr = &cik_sdma_set_wptr,	1987	.set_wptr = &cik_sdma_set_wptr,
1988	};	1988	};
1989		1989
1990	static struct radeon_asic_ring ci_vce_ring = {	1990	static struct radeon_asic_ring ci_vce_ring = {
1991	.ib_execute = &radeon_vce_ib_execute,	1991	.ib_execute = &radeon_vce_ib_execute,
1992	.emit_fence = &radeon_vce_fence_emit,	1992	.emit_fence = &radeon_vce_fence_emit,
1993	.emit_semaphore = &radeon_vce_semaphore_emit,	1993	.emit_semaphore = &radeon_vce_semaphore_emit,
1994	.cs_parse = &radeon_vce_cs_parse,	1994	.cs_parse = &radeon_vce_cs_parse,
1995	.ring_test = &radeon_vce_ring_test,	1995	.ring_test = &radeon_vce_ring_test,
1996	.ib_test = &radeon_vce_ib_test,	1996	.ib_test = &radeon_vce_ib_test,
1997	.is_lockup = &radeon_ring_test_lockup,	1997	.is_lockup = &radeon_ring_test_lockup,
1998	.get_rptr = &vce_v1_0_get_rptr,	1998	.get_rptr = &vce_v1_0_get_rptr,
1999	.get_wptr = &vce_v1_0_get_wptr,	1999	.get_wptr = &vce_v1_0_get_wptr,
2000	.set_wptr = &vce_v1_0_set_wptr,	2000	.set_wptr = &vce_v1_0_set_wptr,
2001	};	2001	};
2002		2002
2003	static struct radeon_asic ci_asic = {	2003	static struct radeon_asic ci_asic = {
2004	.init = &cik_init,	2004	.init = &cik_init,
2005	.fini = &cik_fini,	2005	.fini = &cik_fini,
2006	.suspend = &cik_suspend,	2006	.suspend = &cik_suspend,
2007	.resume = &cik_resume,	2007	.resume = &cik_resume,
2008	.asic_reset = &cik_asic_reset,	2008	.asic_reset = &cik_asic_reset,
2009	.vga_set_state = &r600_vga_set_state,	2009	.vga_set_state = &r600_vga_set_state,
2010	.ioctl_wait_idle = NULL,	2010	.ioctl_wait_idle = NULL,
2011	.gui_idle = &r600_gui_idle,	2011	.gui_idle = &r600_gui_idle,
2012	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	2012	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2013	.get_xclk = &cik_get_xclk,	2013	.get_xclk = &cik_get_xclk,
2014	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,	2014	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2015	.gart = {	2015	.gart = {
2016	.tlb_flush = &cik_pcie_gart_tlb_flush,	2016	.tlb_flush = &cik_pcie_gart_tlb_flush,
2017	.set_page = &rs600_gart_set_page,	2017	.set_page = &rs600_gart_set_page,
2018	},	2018	},
2019	.vm = {	2019	.vm = {
2020	.init = &cik_vm_init,	2020	.init = &cik_vm_init,
2021	.fini = &cik_vm_fini,	2021	.fini = &cik_vm_fini,
2022	.set_page = &cik_sdma_vm_set_page,	2022	.set_page = &cik_sdma_vm_set_page,
2023	},	2023	},
2024	.ring = {	2024	.ring = {
2025	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,	2025	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2026	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,	2026	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2027	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,	2027	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2028	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,	2028	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2029	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,	2029	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2030	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	2030	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2031	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,	2031	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2032	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,	2032	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2033	},	2033	},
2034	.irq = {	2034	.irq = {
2035	.set = &cik_irq_set,	2035	.set = &cik_irq_set,
2036	.process = &cik_irq_process,	2036	.process = &cik_irq_process,
2037	},	2037	},
2038	.display = {	2038	.display = {
2039	.bandwidth_update = &dce8_bandwidth_update,	2039	.bandwidth_update = &dce8_bandwidth_update,
2040	.get_vblank_counter = &evergreen_get_vblank_counter,	2040	.get_vblank_counter = &evergreen_get_vblank_counter,
2041	.wait_for_vblank = &dce4_wait_for_vblank,	2041	.wait_for_vblank = &dce4_wait_for_vblank,
2042	.set_backlight_level = &atombios_set_backlight_level,	2042	.set_backlight_level = &atombios_set_backlight_level,
2043	.get_backlight_level = &atombios_get_backlight_level,	2043	.get_backlight_level = &atombios_get_backlight_level,
2044	.hdmi_enable = &evergreen_hdmi_enable,	2044	.hdmi_enable = &evergreen_hdmi_enable,
2045	.hdmi_setmode = &evergreen_hdmi_setmode,	2045	.hdmi_setmode = &evergreen_hdmi_setmode,
2046	},	2046	},
2047	.copy = {	2047	.copy = {
2048	.blit = &cik_copy_cpdma,	2048	.blit = &cik_copy_cpdma,
2049	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	2049	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2050	.dma = &cik_copy_dma,	2050	.dma = &cik_copy_dma,
2051	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	2051	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2052	.copy = &cik_copy_dma,	2052	.copy = &cik_copy_cpdma,
2053	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	2053	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2054	},	2054	},
2055	.surface = {	2055	.surface = {
2056	.set_reg = r600_set_surface_reg,	2056	.set_reg = r600_set_surface_reg,
2057	.clear_reg = r600_clear_surface_reg,	2057	.clear_reg = r600_clear_surface_reg,
2058	},	2058	},
2059	.hpd = {	2059	.hpd = {
2060	.init = &evergreen_hpd_init,	2060	.init = &evergreen_hpd_init,
2061	.fini = &evergreen_hpd_fini,	2061	.fini = &evergreen_hpd_fini,
2062	.sense = &evergreen_hpd_sense,	2062	.sense = &evergreen_hpd_sense,
2063	.set_polarity = &evergreen_hpd_set_polarity,	2063	.set_polarity = &evergreen_hpd_set_polarity,
2064	},	2064	},
2065	.pm = {	2065	.pm = {
2066	.misc = &evergreen_pm_misc,	2066	.misc = &evergreen_pm_misc,
2067	.prepare = &evergreen_pm_prepare,	2067	.prepare = &evergreen_pm_prepare,
2068	.finish = &evergreen_pm_finish,	2068	.finish = &evergreen_pm_finish,
2069	.init_profile = &sumo_pm_init_profile,	2069	.init_profile = &sumo_pm_init_profile,
2070	.get_dynpm_state = &r600_pm_get_dynpm_state,	2070	.get_dynpm_state = &r600_pm_get_dynpm_state,
2071	.get_engine_clock = &radeon_atom_get_engine_clock,	2071	.get_engine_clock = &radeon_atom_get_engine_clock,
2072	.set_engine_clock = &radeon_atom_set_engine_clock,	2072	.set_engine_clock = &radeon_atom_set_engine_clock,
2073	.get_memory_clock = &radeon_atom_get_memory_clock,	2073	.get_memory_clock = &radeon_atom_get_memory_clock,
2074	.set_memory_clock = &radeon_atom_set_memory_clock,	2074	.set_memory_clock = &radeon_atom_set_memory_clock,
2075	.get_pcie_lanes = NULL,	2075	.get_pcie_lanes = NULL,
2076	.set_pcie_lanes = NULL,	2076	.set_pcie_lanes = NULL,
2077	.set_clock_gating = NULL,	2077	.set_clock_gating = NULL,
2078	.set_uvd_clocks = &cik_set_uvd_clocks,	2078	.set_uvd_clocks = &cik_set_uvd_clocks,
2079	.set_vce_clocks = &cik_set_vce_clocks,	2079	.set_vce_clocks = &cik_set_vce_clocks,
2080	.get_temperature = &ci_get_temp,	2080	.get_temperature = &ci_get_temp,
2081	},	2081	},
2082	.dpm = {	2082	.dpm = {
2083	.init = &ci_dpm_init,	2083	.init = &ci_dpm_init,
2084	.setup_asic = &ci_dpm_setup_asic,	2084	.setup_asic = &ci_dpm_setup_asic,
2085	.enable = &ci_dpm_enable,	2085	.enable = &ci_dpm_enable,
2086	.late_enable = &ci_dpm_late_enable,	2086	.late_enable = &ci_dpm_late_enable,
2087	.disable = &ci_dpm_disable,	2087	.disable = &ci_dpm_disable,
2088	.pre_set_power_state = &ci_dpm_pre_set_power_state,	2088	.pre_set_power_state = &ci_dpm_pre_set_power_state,
2089	.set_power_state = &ci_dpm_set_power_state,	2089	.set_power_state = &ci_dpm_set_power_state,
2090	.post_set_power_state = &ci_dpm_post_set_power_state,	2090	.post_set_power_state = &ci_dpm_post_set_power_state,
2091	.display_configuration_changed = &ci_dpm_display_configuration_changed,	2091	.display_configuration_changed = &ci_dpm_display_configuration_changed,
2092	.fini = &ci_dpm_fini,	2092	.fini = &ci_dpm_fini,
2093	.get_sclk = &ci_dpm_get_sclk,	2093	.get_sclk = &ci_dpm_get_sclk,
2094	.get_mclk = &ci_dpm_get_mclk,	2094	.get_mclk = &ci_dpm_get_mclk,
2095	.print_power_state = &ci_dpm_print_power_state,	2095	.print_power_state = &ci_dpm_print_power_state,
2096	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,	2096	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2097	.force_performance_level = &ci_dpm_force_performance_level,	2097	.force_performance_level = &ci_dpm_force_performance_level,
2098	.vblank_too_short = &ci_dpm_vblank_too_short,	2098	.vblank_too_short = &ci_dpm_vblank_too_short,
2099	.powergate_uvd = &ci_dpm_powergate_uvd,	2099	.powergate_uvd = &ci_dpm_powergate_uvd,
2100	},	2100	},
2101	.pflip = {	2101	.pflip = {
2102	.pre_page_flip = &evergreen_pre_page_flip,	2102	.pre_page_flip = &evergreen_pre_page_flip,
2103	.page_flip = &evergreen_page_flip,	2103	.page_flip = &evergreen_page_flip,
2104	.post_page_flip = &evergreen_post_page_flip,	2104	.post_page_flip = &evergreen_post_page_flip,
2105	},	2105	},
2106	};	2106	};
2107		2107
2108	static struct radeon_asic kv_asic = {	2108	static struct radeon_asic kv_asic = {
2109	.init = &cik_init,	2109	.init = &cik_init,
2110	.fini = &cik_fini,	2110	.fini = &cik_fini,
2111	.suspend = &cik_suspend,	2111	.suspend = &cik_suspend,
2112	.resume = &cik_resume,	2112	.resume = &cik_resume,
2113	.asic_reset = &cik_asic_reset,	2113	.asic_reset = &cik_asic_reset,
2114	.vga_set_state = &r600_vga_set_state,	2114	.vga_set_state = &r600_vga_set_state,
2115	.ioctl_wait_idle = NULL,	2115	.ioctl_wait_idle = NULL,
2116	.gui_idle = &r600_gui_idle,	2116	.gui_idle = &r600_gui_idle,
2117	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,	2117	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2118	.get_xclk = &cik_get_xclk,	2118	.get_xclk = &cik_get_xclk,
2119	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,	2119	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2120	.gart = {	2120	.gart = {
2121	.tlb_flush = &cik_pcie_gart_tlb_flush,	2121	.tlb_flush = &cik_pcie_gart_tlb_flush,
2122	.set_page = &rs600_gart_set_page,	2122	.set_page = &rs600_gart_set_page,
2123	},	2123	},
2124	.vm = {	2124	.vm = {
2125	.init = &cik_vm_init,	2125	.init = &cik_vm_init,
2126	.fini = &cik_vm_fini,	2126	.fini = &cik_vm_fini,
2127	.set_page = &cik_sdma_vm_set_page,	2127	.set_page = &cik_sdma_vm_set_page,
2128	},	2128	},
2129	.ring = {	2129	.ring = {
2130	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,	2130	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2131	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,	2131	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2132	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,	2132	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2133	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,	2133	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2134	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,	2134	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2135	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,	2135	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2136	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,	2136	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2137	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,	2137	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2138	},	2138	},
2139	.irq = {	2139	.irq = {
2140	.set = &cik_irq_set,	2140	.set = &cik_irq_set,
2141	.process = &cik_irq_process,	2141	.process = &cik_irq_process,
2142	},	2142	},
2143	.display = {	2143	.display = {
2144	.bandwidth_update = &dce8_bandwidth_update,	2144	.bandwidth_update = &dce8_bandwidth_update,
2145	.get_vblank_counter = &evergreen_get_vblank_counter,	2145	.get_vblank_counter = &evergreen_get_vblank_counter,
2146	.wait_for_vblank = &dce4_wait_for_vblank,	2146	.wait_for_vblank = &dce4_wait_for_vblank,
2147	.set_backlight_level = &atombios_set_backlight_level,	2147	.set_backlight_level = &atombios_set_backlight_level,
2148	.get_backlight_level = &atombios_get_backlight_level,	2148	.get_backlight_level = &atombios_get_backlight_level,
2149	.hdmi_enable = &evergreen_hdmi_enable,	2149	.hdmi_enable = &evergreen_hdmi_enable,
2150	.hdmi_setmode = &evergreen_hdmi_setmode,	2150	.hdmi_setmode = &evergreen_hdmi_setmode,
2151	},	2151	},
2152	.copy = {	2152	.copy = {
2153	.blit = &cik_copy_cpdma,	2153	.blit = &cik_copy_cpdma,
2154	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	2154	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2155	.dma = &cik_copy_dma,	2155	.dma = &cik_copy_dma,
2156	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,	2156	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2157	.copy = &cik_copy_dma,	2157	.copy = &cik_copy_dma,
2158	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,	2158	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2159	},	2159	},
2160	.surface = {	2160	.surface = {
2161	.set_reg = r600_set_surface_reg,	2161	.set_reg = r600_set_surface_reg,
2162	.clear_reg = r600_clear_surface_reg,	2162	.clear_reg = r600_clear_surface_reg,
2163	},	2163	},
2164	.hpd = {	2164	.hpd = {
2165	.init = &evergreen_hpd_init,	2165	.init = &evergreen_hpd_init,
2166	.fini = &evergreen_hpd_fini,	2166	.fini = &evergreen_hpd_fini,
2167	.sense = &evergreen_hpd_sense,	2167	.sense = &evergreen_hpd_sense,
2168	.set_polarity = &evergreen_hpd_set_polarity,	2168	.set_polarity = &evergreen_hpd_set_polarity,
2169	},	2169	},
2170	.pm = {	2170	.pm = {
2171	.misc = &evergreen_pm_misc,	2171	.misc = &evergreen_pm_misc,
2172	.prepare = &evergreen_pm_prepare,	2172	.prepare = &evergreen_pm_prepare,
2173	.finish = &evergreen_pm_finish,	2173	.finish = &evergreen_pm_finish,
2174	.init_profile = &sumo_pm_init_profile,	2174	.init_profile = &sumo_pm_init_profile,
2175	.get_dynpm_state = &r600_pm_get_dynpm_state,	2175	.get_dynpm_state = &r600_pm_get_dynpm_state,
2176	.get_engine_clock = &radeon_atom_get_engine_clock,	2176	.get_engine_clock = &radeon_atom_get_engine_clock,
2177	.set_engine_clock = &radeon_atom_set_engine_clock,	2177	.set_engine_clock = &radeon_atom_set_engine_clock,
2178	.get_memory_clock = &radeon_atom_get_memory_clock,	2178	.get_memory_clock = &radeon_atom_get_memory_clock,
2179	.set_memory_clock = &radeon_atom_set_memory_clock,	2179	.set_memory_clock = &radeon_atom_set_memory_clock,
2180	.get_pcie_lanes = NULL,	2180	.get_pcie_lanes = NULL,
2181	.set_pcie_lanes = NULL,	2181	.set_pcie_lanes = NULL,
2182	.set_clock_gating = NULL,	2182	.set_clock_gating = NULL,
2183	.set_uvd_clocks = &cik_set_uvd_clocks,	2183	.set_uvd_clocks = &cik_set_uvd_clocks,
2184	.set_vce_clocks = &cik_set_vce_clocks,	2184	.set_vce_clocks = &cik_set_vce_clocks,
2185	.get_temperature = &kv_get_temp,	2185	.get_temperature = &kv_get_temp,
2186	},	2186	},
2187	.dpm = {	2187	.dpm = {
2188	.init = &kv_dpm_init,	2188	.init = &kv_dpm_init,
2189	.setup_asic = &kv_dpm_setup_asic,	2189	.setup_asic = &kv_dpm_setup_asic,
2190	.enable = &kv_dpm_enable,	2190	.enable = &kv_dpm_enable,
2191	.late_enable = &kv_dpm_late_enable,	2191	.late_enable = &kv_dpm_late_enable,
2192	.disable = &kv_dpm_disable,	2192	.disable = &kv_dpm_disable,
2193	.pre_set_power_state = &kv_dpm_pre_set_power_state,	2193	.pre_set_power_state = &kv_dpm_pre_set_power_state,
2194	.set_power_state = &kv_dpm_set_power_state,	2194	.set_power_state = &kv_dpm_set_power_state,
2195	.post_set_power_state = &kv_dpm_post_set_power_state,	2195	.post_set_power_state = &kv_dpm_post_set_power_state,
2196	.display_configuration_changed = &kv_dpm_display_configuration_changed,	2196	.display_configuration_changed = &kv_dpm_display_configuration_changed,
2197	.fini = &kv_dpm_fini,	2197	.fini = &kv_dpm_fini,
2198	.get_sclk = &kv_dpm_get_sclk,	2198	.get_sclk = &kv_dpm_get_sclk,
2199	.get_mclk = &kv_dpm_get_mclk,	2199	.get_mclk = &kv_dpm_get_mclk,
2200	.print_power_state = &kv_dpm_print_power_state,	2200	.print_power_state = &kv_dpm_print_power_state,
2201	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,	2201	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2202	.force_performance_level = &kv_dpm_force_performance_level,	2202	.force_performance_level = &kv_dpm_force_performance_level,
2203	.powergate_uvd = &kv_dpm_powergate_uvd,	2203	.powergate_uvd = &kv_dpm_powergate_uvd,
2204	.enable_bapm = &kv_dpm_enable_bapm,	2204	.enable_bapm = &kv_dpm_enable_bapm,
2205	},	2205	},
2206	.pflip = {	2206	.pflip = {
2207	.pre_page_flip = &evergreen_pre_page_flip,	2207	.pre_page_flip = &evergreen_pre_page_flip,
2208	.page_flip = &evergreen_page_flip,	2208	.page_flip = &evergreen_page_flip,
2209	.post_page_flip = &evergreen_post_page_flip,	2209	.post_page_flip = &evergreen_post_page_flip,
2210	},	2210	},
2211	};	2211	};
2212		2212
2213	/**	2213	/**
2214	* radeon_asic_init - register asic specific callbacks	2214	* radeon_asic_init - register asic specific callbacks
2215	*	2215	*
2216	* @rdev: radeon device pointer	2216	* @rdev: radeon device pointer
2217	*	2217	*
2218	* Registers the appropriate asic specific callbacks for each	2218	* Registers the appropriate asic specific callbacks for each
2219	* chip family. Also sets other asics specific info like the number	2219	* chip family. Also sets other asics specific info like the number
2220	* of crtcs and the register aperture accessors (all asics).	2220	* of crtcs and the register aperture accessors (all asics).
2221	* Returns 0 for success.	2221	* Returns 0 for success.
2222	*/	2222	*/
2223	int radeon_asic_init(struct radeon_device *rdev)	2223	int radeon_asic_init(struct radeon_device *rdev)
2224	{	2224	{
2225	radeon_register_accessor_init(rdev);	2225	radeon_register_accessor_init(rdev);
2226		2226
2227	/* set the number of crtcs */	2227	/* set the number of crtcs */
2228	if (rdev->flags & RADEON_SINGLE_CRTC)	2228	if (rdev->flags & RADEON_SINGLE_CRTC)
2229	rdev->num_crtc = 1;	2229	rdev->num_crtc = 1;
2230	else	2230	else
2231	rdev->num_crtc = 2;	2231	rdev->num_crtc = 2;
2232		2232
2233	rdev->has_uvd = false;	2233	rdev->has_uvd = false;
2234		2234
2235	switch (rdev->family) {	2235	switch (rdev->family) {
2236	case CHIP_R100:	2236	case CHIP_R100:
2237	case CHIP_RV100:	2237	case CHIP_RV100:
2238	case CHIP_RS100:	2238	case CHIP_RS100:
2239	case CHIP_RV200:	2239	case CHIP_RV200:
2240	case CHIP_RS200:	2240	case CHIP_RS200:
2241	rdev->asic = &r100_asic;	2241	rdev->asic = &r100_asic;
2242	break;	2242	break;
2243	case CHIP_R200:	2243	case CHIP_R200:
2244	case CHIP_RV250:	2244	case CHIP_RV250:
2245	case CHIP_RS300:	2245	case CHIP_RS300:
2246	case CHIP_RV280:	2246	case CHIP_RV280:
2247	rdev->asic = &r200_asic;	2247	rdev->asic = &r200_asic;
2248	break;	2248	break;
2249	case CHIP_R300:	2249	case CHIP_R300:
2250	case CHIP_R350:	2250	case CHIP_R350:
2251	case CHIP_RV350:	2251	case CHIP_RV350:
2252	case CHIP_RV380:	2252	case CHIP_RV380:
2253	if (rdev->flags & RADEON_IS_PCIE)	2253	if (rdev->flags & RADEON_IS_PCIE)
2254	rdev->asic = &r300_asic_pcie;	2254	rdev->asic = &r300_asic_pcie;
2255	else	2255	else
2256	rdev->asic = &r300_asic;	2256	rdev->asic = &r300_asic;
2257	break;	2257	break;
2258	case CHIP_R420:	2258	case CHIP_R420:
2259	case CHIP_R423:	2259	case CHIP_R423:
2260	case CHIP_RV410:	2260	case CHIP_RV410:
2261	rdev->asic = &r420_asic;	2261	rdev->asic = &r420_asic;
2262	/* handle macs */	2262	/* handle macs */
2263	if (rdev->bios == NULL) {	2263	if (rdev->bios == NULL) {
2264	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;	2264	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2265	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;	2265	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2266	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;	2266	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2267	rdev->asic->pm.set_memory_clock = NULL;	2267	rdev->asic->pm.set_memory_clock = NULL;
2268	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;	2268	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2269	}	2269	}
2270	break;	2270	break;
2271	case CHIP_RS400:	2271	case CHIP_RS400:
2272	case CHIP_RS480:	2272	case CHIP_RS480:
2273	rdev->asic = &rs400_asic;	2273	rdev->asic = &rs400_asic;
2274	break;	2274	break;
2275	case CHIP_RS600:	2275	case CHIP_RS600:
2276	rdev->asic = &rs600_asic;	2276	rdev->asic = &rs600_asic;
2277	break;	2277	break;
2278	case CHIP_RS690:	2278	case CHIP_RS690:
2279	case CHIP_RS740:	2279	case CHIP_RS740:
2280	rdev->asic = &rs690_asic;	2280	rdev->asic = &rs690_asic;
2281	break;	2281	break;
2282	case CHIP_RV515:	2282	case CHIP_RV515:
2283	rdev->asic = &rv515_asic;	2283	rdev->asic = &rv515_asic;
2284	break;	2284	break;
2285	case CHIP_R520:	2285	case CHIP_R520:
2286	case CHIP_RV530:	2286	case CHIP_RV530:
2287	case CHIP_RV560:	2287	case CHIP_RV560:
2288	case CHIP_RV570:	2288	case CHIP_RV570:
2289	case CHIP_R580:	2289	case CHIP_R580:
2290	rdev->asic = &r520_asic;	2290	rdev->asic = &r520_asic;
2291	break;	2291	break;
2292	case CHIP_R600:	2292	case CHIP_R600:
2293	rdev->asic = &r600_asic;	2293	rdev->asic = &r600_asic;
2294	break;	2294	break;
2295	case CHIP_RV610:	2295	case CHIP_RV610:
2296	case CHIP_RV630:	2296	case CHIP_RV630:
2297	case CHIP_RV620:	2297	case CHIP_RV620:
2298	case CHIP_RV635:	2298	case CHIP_RV635:
2299	case CHIP_RV670:	2299	case CHIP_RV670:
2300	rdev->asic = &rv6xx_asic;	2300	rdev->asic = &rv6xx_asic;
2301	rdev->has_uvd = true;	2301	rdev->has_uvd = true;
2302	break;	2302	break;
2303	case CHIP_RS780:	2303	case CHIP_RS780:
2304	case CHIP_RS880:	2304	case CHIP_RS880:
2305	rdev->asic = &rs780_asic;	2305	rdev->asic = &rs780_asic;
2306	rdev->has_uvd = true;	2306	rdev->has_uvd = true;
2307	break;	2307	break;
2308	case CHIP_RV770:	2308	case CHIP_RV770:
2309	case CHIP_RV730:	2309	case CHIP_RV730:
2310	case CHIP_RV710:	2310	case CHIP_RV710:
2311	case CHIP_RV740:	2311	case CHIP_RV740:
2312	rdev->asic = &rv770_asic;	2312	rdev->asic = &rv770_asic;
2313	rdev->has_uvd = true;	2313	rdev->has_uvd = true;
2314	break;	2314	break;
2315	case CHIP_CEDAR:	2315	case CHIP_CEDAR:
2316	case CHIP_REDWOOD:	2316	case CHIP_REDWOOD:
2317	case CHIP_JUNIPER:	2317	case CHIP_JUNIPER:
2318	case CHIP_CYPRESS:	2318	case CHIP_CYPRESS:
2319	case CHIP_HEMLOCK:	2319	case CHIP_HEMLOCK:
2320	/* set num crtcs */	2320	/* set num crtcs */
2321	if (rdev->family == CHIP_CEDAR)	2321	if (rdev->family == CHIP_CEDAR)
2322	rdev->num_crtc = 4;	2322	rdev->num_crtc = 4;
2323	else	2323	else
2324	rdev->num_crtc = 6;	2324	rdev->num_crtc = 6;
2325	rdev->asic = &evergreen_asic;	2325	rdev->asic = &evergreen_asic;
2326	rdev->has_uvd = true;	2326	rdev->has_uvd = true;
2327	break;	2327	break;
2328	case CHIP_PALM:	2328	case CHIP_PALM:
2329	case CHIP_SUMO:	2329	case CHIP_SUMO:
2330	case CHIP_SUMO2:	2330	case CHIP_SUMO2:
2331	rdev->asic = &sumo_asic;	2331	rdev->asic = &sumo_asic;
2332	rdev->has_uvd = true;	2332	rdev->has_uvd = true;
2333	break;	2333	break;
2334	case CHIP_BARTS:	2334	case CHIP_BARTS:
2335	case CHIP_TURKS:	2335	case CHIP_TURKS:
2336	case CHIP_CAICOS:	2336	case CHIP_CAICOS:
2337	/* set num crtcs */	2337	/* set num crtcs */
2338	if (rdev->family == CHIP_CAICOS)	2338	if (rdev->family == CHIP_CAICOS)
2339	rdev->num_crtc = 4;	2339	rdev->num_crtc = 4;
2340	else	2340	else
2341	rdev->num_crtc = 6;	2341	rdev->num_crtc = 6;
2342	rdev->asic = &btc_asic;	2342	rdev->asic = &btc_asic;
2343	rdev->has_uvd = true;	2343	rdev->has_uvd = true;
2344	break;	2344	break;
2345	case CHIP_CAYMAN:	2345	case CHIP_CAYMAN:
2346	rdev->asic = &cayman_asic;	2346	rdev->asic = &cayman_asic;
2347	/* set num crtcs */	2347	/* set num crtcs */
2348	rdev->num_crtc = 6;	2348	rdev->num_crtc = 6;
2349	rdev->has_uvd = true;	2349	rdev->has_uvd = true;
2350	break;	2350	break;
2351	case CHIP_ARUBA:	2351	case CHIP_ARUBA:
2352	rdev->asic = &trinity_asic;	2352	rdev->asic = &trinity_asic;
2353	/* set num crtcs */	2353	/* set num crtcs */
2354	rdev->num_crtc = 4;	2354	rdev->num_crtc = 4;
2355	rdev->has_uvd = true;	2355	rdev->has_uvd = true;
2356	break;	2356	break;
2357	case CHIP_TAHITI:	2357	case CHIP_TAHITI:
2358	case CHIP_PITCAIRN:	2358	case CHIP_PITCAIRN:
2359	case CHIP_VERDE:	2359	case CHIP_VERDE:
2360	case CHIP_OLAND:	2360	case CHIP_OLAND:
2361	case CHIP_HAINAN:	2361	case CHIP_HAINAN:
2362	rdev->asic = &si_asic;	2362	rdev->asic = &si_asic;
2363	/* set num crtcs */	2363	/* set num crtcs */
2364	if (rdev->family == CHIP_HAINAN)	2364	if (rdev->family == CHIP_HAINAN)
2365	rdev->num_crtc = 0;	2365	rdev->num_crtc = 0;
2366	else if (rdev->family == CHIP_OLAND)	2366	else if (rdev->family == CHIP_OLAND)
2367	rdev->num_crtc = 2;	2367	rdev->num_crtc = 2;
2368	else	2368	else
2369	rdev->num_crtc = 6;	2369	rdev->num_crtc = 6;
2370	if (rdev->family == CHIP_HAINAN)	2370	if (rdev->family == CHIP_HAINAN)
2371	rdev->has_uvd = false;	2371	rdev->has_uvd = false;
2372	else	2372	else
2373	rdev->has_uvd = true;	2373	rdev->has_uvd = true;
2374	switch (rdev->family) {	2374	switch (rdev->family) {
2375	case CHIP_TAHITI:	2375	case CHIP_TAHITI:
2376	rdev->cg_flags =	2376	rdev->cg_flags =
2377	RADEON_CG_SUPPORT_GFX_MGCG \|	2377	RADEON_CG_SUPPORT_GFX_MGCG \|
2378	RADEON_CG_SUPPORT_GFX_MGLS \|	2378	RADEON_CG_SUPPORT_GFX_MGLS \|
2379	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2379	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2380	RADEON_CG_SUPPORT_GFX_CGLS \|	2380	RADEON_CG_SUPPORT_GFX_CGLS \|
2381	RADEON_CG_SUPPORT_GFX_CGTS \|	2381	RADEON_CG_SUPPORT_GFX_CGTS \|
2382	RADEON_CG_SUPPORT_GFX_CP_LS \|	2382	RADEON_CG_SUPPORT_GFX_CP_LS \|
2383	RADEON_CG_SUPPORT_MC_MGCG \|	2383	RADEON_CG_SUPPORT_MC_MGCG \|
2384	RADEON_CG_SUPPORT_SDMA_MGCG \|	2384	RADEON_CG_SUPPORT_SDMA_MGCG \|
2385	RADEON_CG_SUPPORT_BIF_LS \|	2385	RADEON_CG_SUPPORT_BIF_LS \|
2386	RADEON_CG_SUPPORT_VCE_MGCG \|	2386	RADEON_CG_SUPPORT_VCE_MGCG \|
2387	RADEON_CG_SUPPORT_UVD_MGCG \|	2387	RADEON_CG_SUPPORT_UVD_MGCG \|
2388	RADEON_CG_SUPPORT_HDP_LS \|	2388	RADEON_CG_SUPPORT_HDP_LS \|
2389	RADEON_CG_SUPPORT_HDP_MGCG;	2389	RADEON_CG_SUPPORT_HDP_MGCG;
2390	rdev->pg_flags = 0;	2390	rdev->pg_flags = 0;
2391	break;	2391	break;
2392	case CHIP_PITCAIRN:	2392	case CHIP_PITCAIRN:
2393	rdev->cg_flags =	2393	rdev->cg_flags =
2394	RADEON_CG_SUPPORT_GFX_MGCG \|	2394	RADEON_CG_SUPPORT_GFX_MGCG \|
2395	RADEON_CG_SUPPORT_GFX_MGLS \|	2395	RADEON_CG_SUPPORT_GFX_MGLS \|
2396	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2396	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2397	RADEON_CG_SUPPORT_GFX_CGLS \|	2397	RADEON_CG_SUPPORT_GFX_CGLS \|
2398	RADEON_CG_SUPPORT_GFX_CGTS \|	2398	RADEON_CG_SUPPORT_GFX_CGTS \|
2399	RADEON_CG_SUPPORT_GFX_CP_LS \|	2399	RADEON_CG_SUPPORT_GFX_CP_LS \|
2400	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2400	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2401	RADEON_CG_SUPPORT_MC_LS \|	2401	RADEON_CG_SUPPORT_MC_LS \|
2402	RADEON_CG_SUPPORT_MC_MGCG \|	2402	RADEON_CG_SUPPORT_MC_MGCG \|
2403	RADEON_CG_SUPPORT_SDMA_MGCG \|	2403	RADEON_CG_SUPPORT_SDMA_MGCG \|
2404	RADEON_CG_SUPPORT_BIF_LS \|	2404	RADEON_CG_SUPPORT_BIF_LS \|
2405	RADEON_CG_SUPPORT_VCE_MGCG \|	2405	RADEON_CG_SUPPORT_VCE_MGCG \|
2406	RADEON_CG_SUPPORT_UVD_MGCG \|	2406	RADEON_CG_SUPPORT_UVD_MGCG \|
2407	RADEON_CG_SUPPORT_HDP_LS \|	2407	RADEON_CG_SUPPORT_HDP_LS \|
2408	RADEON_CG_SUPPORT_HDP_MGCG;	2408	RADEON_CG_SUPPORT_HDP_MGCG;
2409	rdev->pg_flags = 0;	2409	rdev->pg_flags = 0;
2410	break;	2410	break;
2411	case CHIP_VERDE:	2411	case CHIP_VERDE:
2412	rdev->cg_flags =	2412	rdev->cg_flags =
2413	RADEON_CG_SUPPORT_GFX_MGCG \|	2413	RADEON_CG_SUPPORT_GFX_MGCG \|
2414	RADEON_CG_SUPPORT_GFX_MGLS \|	2414	RADEON_CG_SUPPORT_GFX_MGLS \|
2415	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2415	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2416	RADEON_CG_SUPPORT_GFX_CGLS \|	2416	RADEON_CG_SUPPORT_GFX_CGLS \|
2417	RADEON_CG_SUPPORT_GFX_CGTS \|	2417	RADEON_CG_SUPPORT_GFX_CGTS \|
2418	RADEON_CG_SUPPORT_GFX_CP_LS \|	2418	RADEON_CG_SUPPORT_GFX_CP_LS \|
2419	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2419	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2420	RADEON_CG_SUPPORT_MC_LS \|	2420	RADEON_CG_SUPPORT_MC_LS \|
2421	RADEON_CG_SUPPORT_MC_MGCG \|	2421	RADEON_CG_SUPPORT_MC_MGCG \|
2422	RADEON_CG_SUPPORT_SDMA_MGCG \|	2422	RADEON_CG_SUPPORT_SDMA_MGCG \|
2423	RADEON_CG_SUPPORT_BIF_LS \|	2423	RADEON_CG_SUPPORT_BIF_LS \|
2424	RADEON_CG_SUPPORT_VCE_MGCG \|	2424	RADEON_CG_SUPPORT_VCE_MGCG \|
2425	RADEON_CG_SUPPORT_UVD_MGCG \|	2425	RADEON_CG_SUPPORT_UVD_MGCG \|
2426	RADEON_CG_SUPPORT_HDP_LS \|	2426	RADEON_CG_SUPPORT_HDP_LS \|
2427	RADEON_CG_SUPPORT_HDP_MGCG;	2427	RADEON_CG_SUPPORT_HDP_MGCG;
2428	rdev->pg_flags = 0 \|	2428	rdev->pg_flags = 0 \|
2429	/RADEON_PG_SUPPORT_GFX_PG \| /	2429	/RADEON_PG_SUPPORT_GFX_PG \| /
2430	RADEON_PG_SUPPORT_SDMA;	2430	RADEON_PG_SUPPORT_SDMA;
2431	break;	2431	break;
2432	case CHIP_OLAND:	2432	case CHIP_OLAND:
2433	rdev->cg_flags =	2433	rdev->cg_flags =
2434	RADEON_CG_SUPPORT_GFX_MGCG \|	2434	RADEON_CG_SUPPORT_GFX_MGCG \|
2435	RADEON_CG_SUPPORT_GFX_MGLS \|	2435	RADEON_CG_SUPPORT_GFX_MGLS \|
2436	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2436	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2437	RADEON_CG_SUPPORT_GFX_CGLS \|	2437	RADEON_CG_SUPPORT_GFX_CGLS \|
2438	RADEON_CG_SUPPORT_GFX_CGTS \|	2438	RADEON_CG_SUPPORT_GFX_CGTS \|
2439	RADEON_CG_SUPPORT_GFX_CP_LS \|	2439	RADEON_CG_SUPPORT_GFX_CP_LS \|
2440	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2440	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2441	RADEON_CG_SUPPORT_MC_LS \|	2441	RADEON_CG_SUPPORT_MC_LS \|
2442	RADEON_CG_SUPPORT_MC_MGCG \|	2442	RADEON_CG_SUPPORT_MC_MGCG \|
2443	RADEON_CG_SUPPORT_SDMA_MGCG \|	2443	RADEON_CG_SUPPORT_SDMA_MGCG \|
2444	RADEON_CG_SUPPORT_BIF_LS \|	2444	RADEON_CG_SUPPORT_BIF_LS \|
2445	RADEON_CG_SUPPORT_UVD_MGCG \|	2445	RADEON_CG_SUPPORT_UVD_MGCG \|
2446	RADEON_CG_SUPPORT_HDP_LS \|	2446	RADEON_CG_SUPPORT_HDP_LS \|
2447	RADEON_CG_SUPPORT_HDP_MGCG;	2447	RADEON_CG_SUPPORT_HDP_MGCG;
2448	rdev->pg_flags = 0;	2448	rdev->pg_flags = 0;
2449	break;	2449	break;
2450	case CHIP_HAINAN:	2450	case CHIP_HAINAN:
2451	rdev->cg_flags =	2451	rdev->cg_flags =
2452	RADEON_CG_SUPPORT_GFX_MGCG \|	2452	RADEON_CG_SUPPORT_GFX_MGCG \|
2453	RADEON_CG_SUPPORT_GFX_MGLS \|	2453	RADEON_CG_SUPPORT_GFX_MGLS \|
2454	/RADEON_CG_SUPPORT_GFX_CGCG \|/	2454	/RADEON_CG_SUPPORT_GFX_CGCG \|/
2455	RADEON_CG_SUPPORT_GFX_CGLS \|	2455	RADEON_CG_SUPPORT_GFX_CGLS \|
2456	RADEON_CG_SUPPORT_GFX_CGTS \|	2456	RADEON_CG_SUPPORT_GFX_CGTS \|
2457	RADEON_CG_SUPPORT_GFX_CP_LS \|	2457	RADEON_CG_SUPPORT_GFX_CP_LS \|
2458	RADEON_CG_SUPPORT_GFX_RLC_LS \|	2458	RADEON_CG_SUPPORT_GFX_RLC_LS \|
2459	RADEON_CG_SUPPORT_MC_LS \|	2459	RADEON_CG_SUPPORT_MC_LS \|
2460	RADEON_CG_SUPPORT_MC_MGCG \|	2460	RADEON_CG_SUPPORT_MC_MGCG \|
2461	RADEON_CG_SUPPORT_SDMA_MGCG \|	2461	RADEON_CG_SUPPORT_SDMA_MGCG \|
2462	RADEON_CG_SUPPORT_BIF_LS \|	2462	RADEON_CG_SUPPORT_BIF_LS \|
2463	RADEON_CG_SUPPORT_HDP_LS \|	2463	RADEON_CG_SUPPORT_HDP_LS \|
2464	RADEON_CG_SUPPORT_HDP_MGCG;	2464	RADEON_CG_SUPPORT_HDP_MGCG;
2465	rdev->pg_flags = 0;	2465	rdev->pg_flags = 0;
2466	break;	2466	break;
2467	default:	2467	default:
2468	rdev->cg_flags = 0;	2468	rdev->cg_flags = 0;
2469	rdev->pg_flags = 0;	2469	rdev->pg_flags = 0;
2470	break;	2470	break;
2471	}	2471	}
2472	break;	2472	break;
2473	case CHIP_BONAIRE:	2473	case CHIP_BONAIRE:
2474	case CHIP_HAWAII:	2474	case CHIP_HAWAII:
2475	rdev->asic = &ci_asic;	2475	rdev->asic = &ci_asic;
2476	rdev->num_crtc = 6;	2476	rdev->num_crtc = 6;
2477	rdev->has_uvd = true;	2477	rdev->has_uvd = true;
2478	if (rdev->family == CHIP_BONAIRE) {	2478	if (rdev->family == CHIP_BONAIRE) {
2479	rdev->cg_flags =	2479	rdev->cg_flags =
2480	RADEON_CG_SUPPORT_GFX_MGCG \|	2480	RADEON_CG_SUPPORT_GFX_MGCG \|
2481	RADEON_CG_SUPPORT_GFX_MGLS \|	2481	RADEON_CG_SUPPORT_GFX_MGLS \|
2482	RADEON_CG_SUPPORT_GFX_CGCG \|	2482	RADEON_CG_SUPPORT_GFX_CGCG \|
2483	RADEON_CG_SUPPORT_GFX_CGLS \|	2483	RADEON_CG_SUPPORT_GFX_CGLS \|
2484	RADEON_CG_SUPPORT_GFX_CGTS \|	2484	RADEON_CG_SUPPORT_GFX_CGTS \|
2485	RADEON_CG_SUPPORT_GFX_CGTS_LS \|	2485	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
2486	RADEON_CG_SUPPORT_GFX_CP_LS \|	2486	RADEON_CG_SUPPORT_GFX_CP_LS \|
2487	RADEON_CG_SUPPORT_MC_LS \|	2487	RADEON_CG_SUPPORT_MC_LS \|
2488	RADEON_CG_SUPPORT_MC_MGCG \|	2488	RADEON_CG_SUPPORT_MC_MGCG \|
2489	RADEON_CG_SUPPORT_SDMA_MGCG \|	2489	RADEON_CG_SUPPORT_SDMA_MGCG \|
2490	RADEON_CG_SUPPORT_SDMA_LS \|	2490	RADEON_CG_SUPPORT_SDMA_LS \|
2491	RADEON_CG_SUPPORT_BIF_LS \|	2491	RADEON_CG_SUPPORT_BIF_LS \|
2492	RADEON_CG_SUPPORT_VCE_MGCG \|	2492	RADEON_CG_SUPPORT_VCE_MGCG \|
2493	RADEON_CG_SUPPORT_UVD_MGCG \|	2493	RADEON_CG_SUPPORT_UVD_MGCG \|
2494	RADEON_CG_SUPPORT_HDP_LS \|	2494	RADEON_CG_SUPPORT_HDP_LS \|
2495	RADEON_CG_SUPPORT_HDP_MGCG;	2495	RADEON_CG_SUPPORT_HDP_MGCG;
2496	rdev->pg_flags = 0;	2496	rdev->pg_flags = 0;
2497	} else {	2497	} else {
2498	rdev->cg_flags =	2498	rdev->cg_flags =
2499	RADEON_CG_SUPPORT_GFX_MGCG \|	2499	RADEON_CG_SUPPORT_GFX_MGCG \|
2500	RADEON_CG_SUPPORT_GFX_MGLS \|	2500	RADEON_CG_SUPPORT_GFX_MGLS \|
2501	RADEON_CG_SUPPORT_GFX_CGCG \|	2501	RADEON_CG_SUPPORT_GFX_CGCG \|
2502	RADEON_CG_SUPPORT_GFX_CGLS \|	2502	RADEON_CG_SUPPORT_GFX_CGLS \|
2503	RADEON_CG_SUPPORT_GFX_CGTS \|	2503	RADEON_CG_SUPPORT_GFX_CGTS \|
2504	RADEON_CG_SUPPORT_GFX_CP_LS \|	2504	RADEON_CG_SUPPORT_GFX_CP_LS \|
2505	RADEON_CG_SUPPORT_MC_LS \|	2505	RADEON_CG_SUPPORT_MC_LS \|
2506	RADEON_CG_SUPPORT_MC_MGCG \|	2506	RADEON_CG_SUPPORT_MC_MGCG \|
2507	RADEON_CG_SUPPORT_SDMA_MGCG \|	2507	RADEON_CG_SUPPORT_SDMA_MGCG \|
2508	RADEON_CG_SUPPORT_SDMA_LS \|	2508	RADEON_CG_SUPPORT_SDMA_LS \|
2509	RADEON_CG_SUPPORT_BIF_LS \|	2509	RADEON_CG_SUPPORT_BIF_LS \|
2510	RADEON_CG_SUPPORT_VCE_MGCG \|	2510	RADEON_CG_SUPPORT_VCE_MGCG \|
2511	RADEON_CG_SUPPORT_UVD_MGCG \|	2511	RADEON_CG_SUPPORT_UVD_MGCG \|
2512	RADEON_CG_SUPPORT_HDP_LS \|	2512	RADEON_CG_SUPPORT_HDP_LS \|
2513	RADEON_CG_SUPPORT_HDP_MGCG;	2513	RADEON_CG_SUPPORT_HDP_MGCG;
2514	rdev->pg_flags = 0;	2514	rdev->pg_flags = 0;
2515	}	2515	}
2516	break;	2516	break;
2517	case CHIP_KAVERI:	2517	case CHIP_KAVERI:
2518	case CHIP_KABINI:	2518	case CHIP_KABINI:
2519	case CHIP_MULLINS:	2519	case CHIP_MULLINS:
2520	rdev->asic = &kv_asic;	2520	rdev->asic = &kv_asic;
2521	/* set num crtcs */	2521	/* set num crtcs */
2522	if (rdev->family == CHIP_KAVERI) {	2522	if (rdev->family == CHIP_KAVERI) {
2523	rdev->num_crtc = 4;	2523	rdev->num_crtc = 4;
2524	rdev->cg_flags =	2524	rdev->cg_flags =
2525	RADEON_CG_SUPPORT_GFX_MGCG \|	2525	RADEON_CG_SUPPORT_GFX_MGCG \|
2526	RADEON_CG_SUPPORT_GFX_MGLS \|	2526	RADEON_CG_SUPPORT_GFX_MGLS \|
2527	RADEON_CG_SUPPORT_GFX_CGCG \|	2527	RADEON_CG_SUPPORT_GFX_CGCG \|
2528	RADEON_CG_SUPPORT_GFX_CGLS \|	2528	RADEON_CG_SUPPORT_GFX_CGLS \|
2529	RADEON_CG_SUPPORT_GFX_CGTS \|	2529	RADEON_CG_SUPPORT_GFX_CGTS \|
2530	RADEON_CG_SUPPORT_GFX_CGTS_LS \|	2530	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
2531	RADEON_CG_SUPPORT_GFX_CP_LS \|	2531	RADEON_CG_SUPPORT_GFX_CP_LS \|
2532	RADEON_CG_SUPPORT_SDMA_MGCG \|	2532	RADEON_CG_SUPPORT_SDMA_MGCG \|
2533	RADEON_CG_SUPPORT_SDMA_LS \|	2533	RADEON_CG_SUPPORT_SDMA_LS \|
2534	RADEON_CG_SUPPORT_BIF_LS \|	2534	RADEON_CG_SUPPORT_BIF_LS \|
2535	RADEON_CG_SUPPORT_VCE_MGCG \|	2535	RADEON_CG_SUPPORT_VCE_MGCG \|
2536	RADEON_CG_SUPPORT_UVD_MGCG \|	2536	RADEON_CG_SUPPORT_UVD_MGCG \|
2537	RADEON_CG_SUPPORT_HDP_LS \|	2537	RADEON_CG_SUPPORT_HDP_LS \|
2538	RADEON_CG_SUPPORT_HDP_MGCG;	2538	RADEON_CG_SUPPORT_HDP_MGCG;
2539	rdev->pg_flags = 0;	2539	rdev->pg_flags = 0;
2540	/*RADEON_PG_SUPPORT_GFX_PG \|	2540	/*RADEON_PG_SUPPORT_GFX_PG \|
2541	RADEON_PG_SUPPORT_GFX_SMG \|	2541	RADEON_PG_SUPPORT_GFX_SMG \|
2542	RADEON_PG_SUPPORT_GFX_DMG \|	2542	RADEON_PG_SUPPORT_GFX_DMG \|
2543	RADEON_PG_SUPPORT_UVD \|	2543	RADEON_PG_SUPPORT_UVD \|
2544	RADEON_PG_SUPPORT_VCE \|	2544	RADEON_PG_SUPPORT_VCE \|
2545	RADEON_PG_SUPPORT_CP \|	2545	RADEON_PG_SUPPORT_CP \|
2546	RADEON_PG_SUPPORT_GDS \|	2546	RADEON_PG_SUPPORT_GDS \|
2547	RADEON_PG_SUPPORT_RLC_SMU_HS \|	2547	RADEON_PG_SUPPORT_RLC_SMU_HS \|
2548	RADEON_PG_SUPPORT_ACP \|	2548	RADEON_PG_SUPPORT_ACP \|
2549	RADEON_PG_SUPPORT_SAMU;*/	2549	RADEON_PG_SUPPORT_SAMU;*/
2550	} else {	2550	} else {
2551	rdev->num_crtc = 2;	2551	rdev->num_crtc = 2;
2552	rdev->cg_flags =	2552	rdev->cg_flags =
2553	RADEON_CG_SUPPORT_GFX_MGCG \|	2553	RADEON_CG_SUPPORT_GFX_MGCG \|
2554	RADEON_CG_SUPPORT_GFX_MGLS \|	2554	RADEON_CG_SUPPORT_GFX_MGLS \|
2555	RADEON_CG_SUPPORT_GFX_CGCG \|	2555	RADEON_CG_SUPPORT_GFX_CGCG \|
2556	RADEON_CG_SUPPORT_GFX_CGLS \|	2556	RADEON_CG_SUPPORT_GFX_CGLS \|
2557	RADEON_CG_SUPPORT_GFX_CGTS \|	2557	RADEON_CG_SUPPORT_GFX_CGTS \|
2558	RADEON_CG_SUPPORT_GFX_CGTS_LS \|	2558	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
2559	RADEON_CG_SUPPORT_GFX_CP_LS \|	2559	RADEON_CG_SUPPORT_GFX_CP_LS \|
2560	RADEON_CG_SUPPORT_SDMA_MGCG \|	2560	RADEON_CG_SUPPORT_SDMA_MGCG \|
2561	RADEON_CG_SUPPORT_SDMA_LS \|	2561	RADEON_CG_SUPPORT_SDMA_LS \|
2562	RADEON_CG_SUPPORT_BIF_LS \|	2562	RADEON_CG_SUPPORT_BIF_LS \|
2563	RADEON_CG_SUPPORT_VCE_MGCG \|	2563	RADEON_CG_SUPPORT_VCE_MGCG \|
2564	RADEON_CG_SUPPORT_UVD_MGCG \|	2564	RADEON_CG_SUPPORT_UVD_MGCG \|
2565	RADEON_CG_SUPPORT_HDP_LS \|	2565	RADEON_CG_SUPPORT_HDP_LS \|
2566	RADEON_CG_SUPPORT_HDP_MGCG;	2566	RADEON_CG_SUPPORT_HDP_MGCG;
2567	rdev->pg_flags = 0;	2567	rdev->pg_flags = 0;
2568	/*RADEON_PG_SUPPORT_GFX_PG \|	2568	/*RADEON_PG_SUPPORT_GFX_PG \|
2569	RADEON_PG_SUPPORT_GFX_SMG \|	2569	RADEON_PG_SUPPORT_GFX_SMG \|
2570	RADEON_PG_SUPPORT_UVD \|	2570	RADEON_PG_SUPPORT_UVD \|
2571	RADEON_PG_SUPPORT_VCE \|	2571	RADEON_PG_SUPPORT_VCE \|
2572	RADEON_PG_SUPPORT_CP \|	2572	RADEON_PG_SUPPORT_CP \|
2573	RADEON_PG_SUPPORT_GDS \|	2573	RADEON_PG_SUPPORT_GDS \|
2574	RADEON_PG_SUPPORT_RLC_SMU_HS \|	2574	RADEON_PG_SUPPORT_RLC_SMU_HS \|
2575	RADEON_PG_SUPPORT_SAMU;*/	2575	RADEON_PG_SUPPORT_SAMU;*/
2576	}	2576	}
2577	rdev->has_uvd = true;	2577	rdev->has_uvd = true;
2578	break;	2578	break;
2579	default:	2579	default:
2580	/* FIXME: not supported yet */	2580	/* FIXME: not supported yet */
2581	return -EINVAL;	2581	return -EINVAL;
2582	}	2582	}
2583		2583
2584	if (rdev->flags & RADEON_IS_IGP) {	2584	if (rdev->flags & RADEON_IS_IGP) {
2585	rdev->asic->pm.get_memory_clock = NULL;	2585	rdev->asic->pm.get_memory_clock = NULL;
2586	rdev->asic->pm.set_memory_clock = NULL;	2586	rdev->asic->pm.set_memory_clock = NULL;
2587	}	2587	}
2588		2588
2589	return 0;	2589	return 0;
2590	}	2590	}
2591		2591
2592		2592

drivers/gpu/drm/radeon/radeon_device.c

Diff comments View file @ 6548be5

 /*
  * Copyright 2008 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  * Copyright 2009 Jerome Glisse.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
  */
 #include <linux/console.h>
 #include <linux/slab.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
 #include <linux/vgaarb.h>
 #include <linux/vga_switcheroo.h>
 #include <linux/efi.h>
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "atom.h"
 static const char radeon_family_name[][16] = {
 	"R100",
 	"RV100",
 	"RS100",
 	"RV200",
 	"RS200",
 	"R200",
 	"RV250",
 	"RS300",
 	"RV280",
 	"R300",
 	"R350",
 	"RV350",
 	"RV380",
 	"R420",
 	"R423",
 	"RV410",
 	"RS400",
 	"RS480",
 	"RS600",
 	"RS690",
 	"RS740",
 	"RV515",
 	"R520",
 	"RV530",
 	"RV560",
 	"RV570",
 	"R580",
 	"R600",
 	"RV610",
 	"RV630",
 	"RV670",
 	"RV620",
 	"RV635",
 	"RS780",
 	"RS880",
 	"RV770",
 	"RV730",
 	"RV710",
 	"RV740",
 	"CEDAR",
 	"REDWOOD",
 	"JUNIPER",
 	"CYPRESS",
 	"HEMLOCK",
 	"PALM",
 	"SUMO",
 	"SUMO2",
 	"BARTS",
 	"TURKS",
 	"CAICOS",
 	"CAYMAN",
 	"ARUBA",
 	"TAHITI",
 	"PITCAIRN",
 	"VERDE",
 	"OLAND",
 	"HAINAN",
 	"BONAIRE",
 	"KAVERI",
 	"KABINI",
 	"HAWAII",
 	"MULLINS",
 	"LAST",
 };
 bool radeon_is_px(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	if (rdev->flags & RADEON_IS_PX)
 		return true;
 	return false;
 }
 /**
  * radeon_program_register_sequence - program an array of registers.
  *
  * @rdev: radeon_device pointer
  * @registers: pointer to the register array
  * @array_size: size of the register array
  *
  * Programs an array or registers with and and or masks.
  * This is a helper for setting golden registers.
  */
 void radeon_program_register_sequence(struct radeon_device *rdev,
 				      const u32 *registers,
 				      const u32 array_size)
 {
 	u32 tmp, reg, and_mask, or_mask;
 	int i;
 	if (array_size % 3)
 		return;
 	for (i = 0; i < array_size; i +=3) {
 		reg = registers[i + 0];
 		and_mask = registers[i + 1];
 		or_mask = registers[i + 2];
 		if (and_mask == 0xffffffff) {
 			tmp = or_mask;
 		} else {
 			tmp = RREG32(reg);
 			tmp &= ~and_mask;
 			tmp |= or_mask;
 		}
 		WREG32(reg, tmp);
 	}
 }
 void radeon_pci_config_reset(struct radeon_device *rdev)
 {
 	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
 }
 /**
  * radeon_surface_init - Clear GPU surface registers.
  *
  * @rdev: radeon_device pointer
  *
  * Clear GPU surface registers (r1xx-r5xx).
  */
 void radeon_surface_init(struct radeon_device *rdev)
 {
 	/* FIXME: check this out */
 	if (rdev->family < CHIP_R600) {
 		int i;
 		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 			if (rdev->surface_regs[i].bo)
 				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 			else
 				radeon_clear_surface_reg(rdev, i);
 		}
 		/* enable surfaces */
 		WREG32(RADEON_SURFACE_CNTL, 0);
 	}
 }
 /*
  * GPU scratch registers helpers function.
  */
 /**
  * radeon_scratch_init - Init scratch register driver information.
  *
  * @rdev: radeon_device pointer
  *
  * Init CP scratch register driver information (r1xx-r5xx)
  */
 void radeon_scratch_init(struct radeon_device *rdev)
 {
 	int i;
 	/* FIXME: check this out */
 	if (rdev->family < CHIP_R300) {
 		rdev->scratch.num_reg = 5;
 	} else {
 		rdev->scratch.num_reg = 7;
 	}
 	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 	for (i = 0; i < rdev->scratch.num_reg; i++) {
 		rdev->scratch.free[i] = true;
 		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 	}
 }
 /**
  * radeon_scratch_get - Allocate a scratch register
  *
  * @rdev: radeon_device pointer
  * @reg: scratch register mmio offset
  *
  * Allocate a CP scratch register for use by the driver (all asics).
  * Returns 0 on success or -EINVAL on failure.
  */
 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 {
 	int i;
 	for (i = 0; i < rdev->scratch.num_reg; i++) {
 		if (rdev->scratch.free[i]) {
 			rdev->scratch.free[i] = false;
 			*reg = rdev->scratch.reg[i];
 			return 0;
 		}
 	}
 	return -EINVAL;
 }
 /**
  * radeon_scratch_free - Free a scratch register
  *
  * @rdev: radeon_device pointer
  * @reg: scratch register mmio offset
  *
  * Free a CP scratch register allocated for use by the driver (all asics)
  */
 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 {
 	int i;
 	for (i = 0; i < rdev->scratch.num_reg; i++) {
 		if (rdev->scratch.reg[i] == reg) {
 			rdev->scratch.free[i] = true;
 			return;
 		}
 	}
 }
 /*
  * GPU doorbell aperture helpers function.
  */
 /**
  * radeon_doorbell_init - Init doorbell driver information.
  *
  * @rdev: radeon_device pointer
  *
  * Init doorbell driver information (CIK)
  * Returns 0 on success, error on failure.
  */
 static int radeon_doorbell_init(struct radeon_device *rdev)
 {
 	/* doorbell bar mapping */
 	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
 	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
 	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
 	if (rdev->doorbell.num_doorbells == 0)
 		return -EINVAL;
 	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
 	if (rdev->doorbell.ptr == NULL) {
 		return -ENOMEM;
 	}
 	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
 	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
 	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
 	return 0;
 }
 /**
  * radeon_doorbell_fini - Tear down doorbell driver information.
  *
  * @rdev: radeon_device pointer
  *
  * Tear down doorbell driver information (CIK)
  */
 static void radeon_doorbell_fini(struct radeon_device *rdev)
 {
 	iounmap(rdev->doorbell.ptr);
 	rdev->doorbell.ptr = NULL;
 }
 /**
  * radeon_doorbell_get - Allocate a doorbell entry
  *
  * @rdev: radeon_device pointer
  * @doorbell: doorbell index
  *
  * Allocate a doorbell for use by the driver (all asics).
  * Returns 0 on success or -EINVAL on failure.
  */
 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
 {
 	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
 	if (offset < rdev->doorbell.num_doorbells) {
 		__set_bit(offset, rdev->doorbell.used);
 		*doorbell = offset;
 		return 0;
 	} else {
 		return -EINVAL;
 	}
 }
 /**
  * radeon_doorbell_free - Free a doorbell entry
  *
  * @rdev: radeon_device pointer
  * @doorbell: doorbell index
  *
  * Free a doorbell allocated for use by the driver (all asics)
  */
 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
 {
 	if (doorbell < rdev->doorbell.num_doorbells)
 		__clear_bit(doorbell, rdev->doorbell.used);
 }
 /*
  * radeon_wb_*()
  * Writeback is the the method by which the the GPU updates special pages
  * in memory with the status of certain GPU events (fences, ring pointers,
  * etc.).
  */
 /**
  * radeon_wb_disable - Disable Writeback
  *
  * @rdev: radeon_device pointer
  *
  * Disables Writeback (all asics).  Used for suspend.
  */
 void radeon_wb_disable(struct radeon_device *rdev)
 {
 	rdev->wb.enabled = false;
 }
 /**
  * radeon_wb_fini - Disable Writeback and free memory
  *
  * @rdev: radeon_device pointer
  *
  * Disables Writeback and frees the Writeback memory (all asics).
  * Used at driver shutdown.
  */
 void radeon_wb_fini(struct radeon_device *rdev)
 {
 	radeon_wb_disable(rdev);
 	if (rdev->wb.wb_obj) {
 		if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
 			radeon_bo_kunmap(rdev->wb.wb_obj);
 			radeon_bo_unpin(rdev->wb.wb_obj);
 			radeon_bo_unreserve(rdev->wb.wb_obj);
 		}
 		radeon_bo_unref(&rdev->wb.wb_obj);
 		rdev->wb.wb = NULL;
 		rdev->wb.wb_obj = NULL;
 	}
 }
 /**
  * radeon_wb_init- Init Writeback driver info and allocate memory
  *
  * @rdev: radeon_device pointer
  *
  * Disables Writeback and frees the Writeback memory (all asics).
  * Used at driver startup.
  * Returns 0 on success or an -error on failure.
  */
 int radeon_wb_init(struct radeon_device *rdev)
 {
 	int r;
 	if (rdev->wb.wb_obj == NULL) {
 		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 				     RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
 		if (r) {
 			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 			return r;
 		}
 		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 		if (unlikely(r != 0)) {
 			radeon_wb_fini(rdev);
 			return r;
 		}
 		r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 				&rdev->wb.gpu_addr);
 		if (r) {
 			radeon_bo_unreserve(rdev->wb.wb_obj);
 			dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 			radeon_wb_fini(rdev);
 			return r;
 		}
 		r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 		radeon_bo_unreserve(rdev->wb.wb_obj);
 		if (r) {
 			dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 			radeon_wb_fini(rdev);
 			return r;
 		}
 	}
 	/* clear wb memory */
 	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 	/* disable event_write fences */
 	rdev->wb.use_event = false;
 	/* disabled via module param */
 	if (radeon_no_wb == 1) {
 		rdev->wb.enabled = false;
 	} else {
 		if (rdev->flags & RADEON_IS_AGP) {
 			/* often unreliable on AGP */
 			rdev->wb.enabled = false;
 		} else if (rdev->family < CHIP_R300) {
 			/* often unreliable on pre-r300 */
 			rdev->wb.enabled = false;
 		} else {
 			rdev->wb.enabled = true;
 			/* event_write fences are only available on r600+ */
 			if (rdev->family >= CHIP_R600) {
 				rdev->wb.use_event = true;
 			}
 		}
 	}
 	/* always use writeback/events on NI, APUs */
 	if (rdev->family >= CHIP_PALM) {
 		rdev->wb.enabled = true;
 		rdev->wb.use_event = true;
 	}
 	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 	return 0;
 }
 /**
  * radeon_vram_location - try to find VRAM location
  * @rdev: radeon device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
  * @base: base address at which to put VRAM
  *
  * Function will place try to place VRAM at base address provided
  * as parameter (which is so far either PCI aperture address or
  * for IGP TOM base address).
  *
  * If there is not enough space to fit the unvisible VRAM in the 32bits
  * address space then we limit the VRAM size to the aperture.
  *
  * If we are using AGP and if the AGP aperture doesn't allow us to have
  * room for all the VRAM than we restrict the VRAM to the PCI aperture
  * size and print a warning.
  *
  * This function will never fails, worst case are limiting VRAM.
  *
  * Note: GTT start, end, size should be initialized before calling this
  * function on AGP platform.
  *
  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
  * this shouldn't be a problem as we are using the PCI aperture as a reference.
  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  * not IGP.
  *
  * Note: we use mc_vram_size as on some board we need to program the mc to
  * cover the whole aperture even if VRAM size is inferior to aperture size
  * Novell bug 204882 + along with lots of ubuntu ones
  *
  * Note: when limiting vram it's safe to overwritte real_vram_size because
  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  * ones)
  *
  * Note: IGP TOM addr should be the same as the aperture addr, we don't
  * explicitly check for that thought.
  *
  * FIXME: when reducing VRAM size align new size on power of 2.
  */
 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 {
 	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 	mc->vram_start = base;
 	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
 		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 		mc->real_vram_size = mc->aper_size;
 		mc->mc_vram_size = mc->aper_size;
 	}
 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 		mc->real_vram_size = mc->aper_size;
 		mc->mc_vram_size = mc->aper_size;
 	}
 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 	if (limit && limit < mc->real_vram_size)
 		mc->real_vram_size = limit;
 	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 			mc->mc_vram_size >> 20, mc->vram_start,
 			mc->vram_end, mc->real_vram_size >> 20);
 }
 /**
  * radeon_gtt_location - try to find GTT location
  * @rdev: radeon device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
  *
  * Function will place try to place GTT before or after VRAM.
  *
  * If GTT size is bigger than space left then we ajust GTT size.
  * Thus function will never fails.
  *
  * FIXME: when reducing GTT size align new size on power of 2.
  */
 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 {
 	u64 size_af, size_bf;
 	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 	size_bf = mc->vram_start & ~mc->gtt_base_align;
 	if (size_bf > size_af) {
 		if (mc->gtt_size > size_bf) {
 			dev_warn(rdev->dev, "limiting GTT\n");
 			mc->gtt_size = size_bf;
 		}
 		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 	} else {
 		if (mc->gtt_size > size_af) {
 			dev_warn(rdev->dev, "limiting GTT\n");
 			mc->gtt_size = size_af;
 		}
 		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 	}
 	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 }
 /*
  * GPU helpers function.
  */
 /**
  * radeon_card_posted - check if the hw has already been initialized
  *
  * @rdev: radeon_device pointer
  *
  * Check if the asic has been initialized (all asics).
  * Used at driver startup.
  * Returns true if initialized or false if not.
  */
 bool radeon_card_posted(struct radeon_device *rdev)
 {
 	uint32_t reg;
 	/* required for EFI mode on macbook2,1 which uses an r5xx asic */
 	if (efi_enabled(EFI_BOOT) &&
 	    (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 	    (rdev->family < CHIP_R600))
 		return false;
 	if (ASIC_IS_NODCE(rdev))
 		goto check_memsize;
 	/* first check CRTCs */
 	if (ASIC_IS_DCE4(rdev)) {
 		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 			if (rdev->num_crtc >= 4) {
 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 			}
 			if (rdev->num_crtc >= 6) {
 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 			}
 		if (reg & EVERGREEN_CRTC_MASTER_EN)
 			return true;
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 		      RREG32(AVIVO_D2CRTC_CONTROL);
 		if (reg & AVIVO_CRTC_EN) {
 			return true;
 		}
 	} else {
 		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 		      RREG32(RADEON_CRTC2_GEN_CNTL);
 		if (reg & RADEON_CRTC_EN) {
 			return true;
 		}
 	}
 check_memsize:
 	/* then check MEM_SIZE, in case the crtcs are off */
 	if (rdev->family >= CHIP_R600)
 		reg = RREG32(R600_CONFIG_MEMSIZE);
 	else
 		reg = RREG32(RADEON_CONFIG_MEMSIZE);
 	if (reg)
 		return true;
 	return false;
 }
 /**
  * radeon_update_bandwidth_info - update display bandwidth params
  *
  * @rdev: radeon_device pointer
  *
  * Used when sclk/mclk are switched or display modes are set.
  * params are used to calculate display watermarks (all asics)
  */
 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 {
 	fixed20_12 a;
 	u32 sclk = rdev->pm.current_sclk;
 	u32 mclk = rdev->pm.current_mclk;
 	/* sclk/mclk in Mhz */
 	a.full = dfixed_const(100);
 	rdev->pm.sclk.full = dfixed_const(sclk);
 	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 	rdev->pm.mclk.full = dfixed_const(mclk);
 	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 	if (rdev->flags & RADEON_IS_IGP) {
 		a.full = dfixed_const(16);
 		/* core_bandwidth = sclk(Mhz) * 16 */
 		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 	}
 }
 /**
  * radeon_boot_test_post_card - check and possibly initialize the hw
  *
  * @rdev: radeon_device pointer
  *
  * Check if the asic is initialized and if not, attempt to initialize
  * it (all asics).
  * Returns true if initialized or false if not.
  */
 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 {
 	if (radeon_card_posted(rdev))
 		return true;
 	if (rdev->bios) {
 		DRM_INFO("GPU not posted. posting now...\n");
 		if (rdev->is_atom_bios)
 			atom_asic_init(rdev->mode_info.atom_context);
 		else
 			radeon_combios_asic_init(rdev->ddev);
 		return true;
 	} else {
 		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 		return false;
 	}
 }
 /**
  * radeon_dummy_page_init - init dummy page used by the driver
  *
  * @rdev: radeon_device pointer
  *
  * Allocate the dummy page used by the driver (all asics).
  * This dummy page is used by the driver as a filler for gart entries
  * when pages are taken out of the GART
  * Returns 0 on sucess, -ENOMEM on failure.
  */
 int radeon_dummy_page_init(struct radeon_device *rdev)
 {
 	if (rdev->dummy_page.page)
 		return 0;
 	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 	if (rdev->dummy_page.page == NULL)
 		return -ENOMEM;
 	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 	if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 		dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 		__free_page(rdev->dummy_page.page);
 		rdev->dummy_page.page = NULL;
 		return -ENOMEM;
 	}
 	return 0;
 }
 /**
  * radeon_dummy_page_fini - free dummy page used by the driver
  *
  * @rdev: radeon_device pointer
  *
  * Frees the dummy page used by the driver (all asics).
  */
 void radeon_dummy_page_fini(struct radeon_device *rdev)
 {
 	if (rdev->dummy_page.page == NULL)
 		return;
 	pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 	__free_page(rdev->dummy_page.page);
 	rdev->dummy_page.page = NULL;
 }
 /* ATOM accessor methods */
 /*
  * ATOM is an interpreted byte code stored in tables in the vbios.  The
  * driver registers callbacks to access registers and the interpreter
  * in the driver parses the tables and executes then to program specific
  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
  * atombios.h, and atom.c
  */
 /**
  * cail_pll_read - read PLL register
  *
  * @info: atom card_info pointer
  * @reg: PLL register offset
  *
  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  * Returns the value of the PLL register.
  */
 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	uint32_t r;
 	r = rdev->pll_rreg(rdev, reg);
 	return r;
 }
 /**
  * cail_pll_write - write PLL register
  *
  * @info: atom card_info pointer
  * @reg: PLL register offset
  * @val: value to write to the pll register
  *
  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  */
 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	rdev->pll_wreg(rdev, reg, val);
 }
 /**
  * cail_mc_read - read MC (Memory Controller) register
  *
  * @info: atom card_info pointer
  * @reg: MC register offset
  *
  * Provides an MC register accessor for the atom interpreter (r4xx+).
  * Returns the value of the MC register.
  */
 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	uint32_t r;
 	r = rdev->mc_rreg(rdev, reg);
 	return r;
 }
 /**
  * cail_mc_write - write MC (Memory Controller) register
  *
  * @info: atom card_info pointer
  * @reg: MC register offset
  * @val: value to write to the pll register
  *
  * Provides a MC register accessor for the atom interpreter (r4xx+).
  */
 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	rdev->mc_wreg(rdev, reg, val);
 }
 /**
  * cail_reg_write - write MMIO register
  *
  * @info: atom card_info pointer
  * @reg: MMIO register offset
  * @val: value to write to the pll register
  *
  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
  */
 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	WREG32(reg*4, val);
 }
 /**
  * cail_reg_read - read MMIO register
  *
  * @info: atom card_info pointer
  * @reg: MMIO register offset
  *
  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
  * Returns the value of the MMIO register.
  */
 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	uint32_t r;
 	r = RREG32(reg*4);
 	return r;
 }
 /**
  * cail_ioreg_write - write IO register
  *
  * @info: atom card_info pointer
  * @reg: IO register offset
  * @val: value to write to the pll register
  *
  * Provides a IO register accessor for the atom interpreter (r4xx+).
  */
 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	WREG32_IO(reg*4, val);
 }
 /**
  * cail_ioreg_read - read IO register
  *
  * @info: atom card_info pointer
  * @reg: IO register offset
  *
  * Provides an IO register accessor for the atom interpreter (r4xx+).
  * Returns the value of the IO register.
  */
 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 {
 	struct radeon_device *rdev = info->dev->dev_private;
 	uint32_t r;
 	r = RREG32_IO(reg*4);
 	return r;
 }
 /**
  * radeon_atombios_init - init the driver info and callbacks for atombios
  *
  * @rdev: radeon_device pointer
  *
  * Initializes the driver info and register access callbacks for the
  * ATOM interpreter (r4xx+).
  * Returns 0 on sucess, -ENOMEM on failure.
  * Called at driver startup.
  */
 int radeon_atombios_init(struct radeon_device *rdev)
 {
 	struct card_info *atom_card_info =
 	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
 	if (!atom_card_info)
 		return -ENOMEM;
 	rdev->mode_info.atom_card_info = atom_card_info;
 	atom_card_info->dev = rdev->ddev;
 	atom_card_info->reg_read = cail_reg_read;
 	atom_card_info->reg_write = cail_reg_write;
 	/* needed for iio ops */
 	if (rdev->rio_mem) {
 		atom_card_info->ioreg_read = cail_ioreg_read;
 		atom_card_info->ioreg_write = cail_ioreg_write;
 	} else {
 		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 		atom_card_info->ioreg_read = cail_reg_read;
 		atom_card_info->ioreg_write = cail_reg_write;
 	}
 	atom_card_info->mc_read = cail_mc_read;
 	atom_card_info->mc_write = cail_mc_write;
 	atom_card_info->pll_read = cail_pll_read;
 	atom_card_info->pll_write = cail_pll_write;
 	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 	if (!rdev->mode_info.atom_context) {
 		radeon_atombios_fini(rdev);
 		return -ENOMEM;
 	}
 	mutex_init(&rdev->mode_info.atom_context->mutex);
 	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 	return 0;
 }
 /**
  * radeon_atombios_fini - free the driver info and callbacks for atombios
  *
  * @rdev: radeon_device pointer
  *
  * Frees the driver info and register access callbacks for the ATOM
  * interpreter (r4xx+).
  * Called at driver shutdown.
  */
 void radeon_atombios_fini(struct radeon_device *rdev)
 {
 	if (rdev->mode_info.atom_context) {
 		kfree(rdev->mode_info.atom_context->scratch);
 	}
 	kfree(rdev->mode_info.atom_context);
 	rdev->mode_info.atom_context = NULL;
 	kfree(rdev->mode_info.atom_card_info);
 	rdev->mode_info.atom_card_info = NULL;
 }
 /* COMBIOS */
 /*
  * COMBIOS is the bios format prior to ATOM. It provides
  * command tables similar to ATOM, but doesn't have a unified
  * parser.  See radeon_combios.c
  */
 /**
  * radeon_combios_init - init the driver info for combios
  *
  * @rdev: radeon_device pointer
  *
  * Initializes the driver info for combios (r1xx-r3xx).
  * Returns 0 on sucess.
  * Called at driver startup.
  */
 int radeon_combios_init(struct radeon_device *rdev)
 {
 	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 	return 0;
 }
 /**
  * radeon_combios_fini - free the driver info for combios
  *
  * @rdev: radeon_device pointer
  *
  * Frees the driver info for combios (r1xx-r3xx).
  * Called at driver shutdown.
  */
 void radeon_combios_fini(struct radeon_device *rdev)
 {
 }
 /* if we get transitioned to only one device, take VGA back */
 /**
  * radeon_vga_set_decode - enable/disable vga decode
  *
  * @cookie: radeon_device pointer
  * @state: enable/disable vga decode
  *
  * Enable/disable vga decode (all asics).
  * Returns VGA resource flags.
  */
 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 {
 	struct radeon_device *rdev = cookie;
 	radeon_vga_set_state(rdev, state);
 	if (state)
 		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 	else
 		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 }
 /**
  * radeon_check_pot_argument - check that argument is a power of two
  *
  * @arg: value to check
  *
  * Validates that a certain argument is a power of two (all asics).
  * Returns true if argument is valid.
  */
 static bool radeon_check_pot_argument(int arg)
 {
 	return (arg & (arg - 1)) == 0;
 }
 /**
  * radeon_check_arguments - validate module params
  *
  * @rdev: radeon_device pointer
  *
  * Validates certain module parameters and updates
  * the associated values used by the driver (all asics).
  */
 static void radeon_check_arguments(struct radeon_device *rdev)
 {
 	/* vramlimit must be a power of two */
 	if (!radeon_check_pot_argument(radeon_vram_limit)) {
 		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 				radeon_vram_limit);
 		radeon_vram_limit = 0;
 	}
 	if (radeon_gart_size == -1) {
 		/* default to a larger gart size on newer asics */
 		if (rdev->family >= CHIP_RV770)
 			radeon_gart_size = 1024;
 		else
 			radeon_gart_size = 512;
 	}
 	/* gtt size must be power of two and greater or equal to 32M */
 	if (radeon_gart_size < 32) {
 		dev_warn(rdev->dev, "gart size (%d) too small\n",
 				radeon_gart_size);
 		if (rdev->family >= CHIP_RV770)
 			radeon_gart_size = 1024;
 		else
 			radeon_gart_size = 512;
 	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
 		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 				radeon_gart_size);
 		if (rdev->family >= CHIP_RV770)
 			radeon_gart_size = 1024;
 		else
 			radeon_gart_size = 512;
 	}
 	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
 	/* AGP mode can only be -1, 1, 2, 4, 8 */
 	switch (radeon_agpmode) {
 	case -1:
 	case 0:
 	case 1:
 	case 2:
 	case 4:
 	case 8:
 		break;
 	default:
 		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 		radeon_agpmode = 0;
 		break;
 	}
 }
 /**
  * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
  * needed for waking up.
  *
  * @pdev: pci dev pointer
  */
 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
 {
 	/* 6600m in a macbook pro */
 	if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
 	    pdev->subsystem_device == 0x00e2) {
 		printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
 		return true;
 	}
 	return false;
 }
 /**
  * radeon_switcheroo_set_state - set switcheroo state
  *
  * @pdev: pci dev pointer
  * @state: vga switcheroo state
  *
  * Callback for the switcheroo driver.  Suspends or resumes the
  * the asics before or after it is powered up using ACPI methods.
  */
 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 {
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
 		return;
 	if (state == VGA_SWITCHEROO_ON) {
 		unsigned d3_delay = dev->pdev->d3_delay;
 		printk(KERN_INFO "radeon: switched on\n");
 		/* don't suspend or resume card normally */
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 		if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
 			dev->pdev->d3_delay = 20;
 		radeon_resume_kms(dev, true, true);
 		dev->pdev->d3_delay = d3_delay;
 		dev->switch_power_state = DRM_SWITCH_POWER_ON;
 		drm_kms_helper_poll_enable(dev);
 	} else {
 		printk(KERN_INFO "radeon: switched off\n");
 		drm_kms_helper_poll_disable(dev);
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 		radeon_suspend_kms(dev, true, true);
 		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 	}
 }
 /**
  * radeon_switcheroo_can_switch - see if switcheroo state can change
  *
  * @pdev: pci dev pointer
  *
  * Callback for the switcheroo driver.  Check of the switcheroo
  * state can be changed.
  * Returns true if the state can be changed, false if not.
  */
 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 {
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	bool can_switch;
 	spin_lock(&dev->count_lock);
 	can_switch = (dev->open_count == 0);
 	spin_unlock(&dev->count_lock);
 	return can_switch;
 }
 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
 	.set_gpu_state = radeon_switcheroo_set_state,
 	.reprobe = NULL,
 	.can_switch = radeon_switcheroo_can_switch,
 };
 /**
  * radeon_device_init - initialize the driver
  *
  * @rdev: radeon_device pointer
  * @pdev: drm dev pointer
  * @pdev: pci dev pointer
  * @flags: driver flags
  *
  * Initializes the driver info and hw (all asics).
  * Returns 0 for success or an error on failure.
  * Called at driver startup.
  */
 int radeon_device_init(struct radeon_device *rdev,
 		       struct drm_device *ddev,
 		       struct pci_dev *pdev,
 		       uint32_t flags)
 {
 	int r, i;
 	int dma_bits;
 	bool runtime = false;
 	rdev->shutdown = false;
 	rdev->dev = &pdev->dev;
 	rdev->ddev = ddev;
 	rdev->pdev = pdev;
 	rdev->flags = flags;
 	rdev->family = flags & RADEON_FAMILY_MASK;
 	rdev->is_atom_bios = false;
 	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 	rdev->mc.gtt_size = 512 * 1024 * 1024;
 	rdev->accel_working = false;
 	/* set up ring ids */
 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 		rdev->ring[i].idx = i;
 	}
 	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
 		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
 		pdev->subsystem_vendor, pdev->subsystem_device);
 	/* mutex initialization are all done here so we
 	 * can recall function without having locking issues */
 	mutex_init(&rdev->ring_lock);
 	mutex_init(&rdev->dc_hw_i2c_mutex);
 	atomic_set(&rdev->ih.lock, 0);
 	mutex_init(&rdev->gem.mutex);
 	mutex_init(&rdev->pm.mutex);
 	mutex_init(&rdev->gpu_clock_mutex);
 	mutex_init(&rdev->srbm_mutex);
 	init_rwsem(&rdev->pm.mclk_lock);
 	init_rwsem(&rdev->exclusive_lock);
 	init_waitqueue_head(&rdev->irq.vblank_queue);
 	r = radeon_gem_init(rdev);
 	if (r)
 		return r;
 	/* Adjust VM size here.
 	 * Currently set to 4GB ((1 << 20) 4k pages).
 	 * Max GPUVM size for cayman and SI is 40 bits.
 	 */
 	rdev->vm_manager.max_pfn = 1 << 20;
 	/* Set asic functions */
 	r = radeon_asic_init(rdev);
 	if (r)
 		return r;
 	radeon_check_arguments(rdev);
 	/* all of the newer IGP chips have an internal gart
 	 * However some rs4xx report as AGP, so remove that here.
 	 */
 	if ((rdev->family >= CHIP_RS400) &&
 	    (rdev->flags & RADEON_IS_IGP)) {
 		rdev->flags &= ~RADEON_IS_AGP;
 	}
 	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 		radeon_agp_disable(rdev);
 	}
 	/* Set the internal MC address mask
 	 * This is the max address of the GPU's
 	 * internal address space.
 	 */
 	if (rdev->family >= CHIP_CAYMAN)
 		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 	else if (rdev->family >= CHIP_CEDAR)
 		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
 	else
 		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
 	 * AGP - generally dma32 is safest
 	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 	 */
 	rdev->need_dma32 = false;
 	if (rdev->flags & RADEON_IS_AGP)
 		rdev->need_dma32 = true;
 	if ((rdev->flags & RADEON_IS_PCI) &&
 	    (rdev->family <= CHIP_RS740))
 		rdev->need_dma32 = true;
 	dma_bits = rdev->need_dma32 ? 32 : 40;
 	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 	if (r) {
 		rdev->need_dma32 = true;
 		dma_bits = 32;
 		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 	}
 	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 	if (r) {
 		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
 		printk(KERN_WARNING "radeon: No coherent DMA available.\n");
 	}
 	/* Registers mapping */
 	/* TODO: block userspace mapping of io register */
 	spin_lock_init(&rdev->mmio_idx_lock);
 	spin_lock_init(&rdev->smc_idx_lock);
 	spin_lock_init(&rdev->pll_idx_lock);
 	spin_lock_init(&rdev->mc_idx_lock);
 	spin_lock_init(&rdev->pcie_idx_lock);
 	spin_lock_init(&rdev->pciep_idx_lock);
 	spin_lock_init(&rdev->pif_idx_lock);
 	spin_lock_init(&rdev->cg_idx_lock);
 	spin_lock_init(&rdev->uvd_idx_lock);
 	spin_lock_init(&rdev->rcu_idx_lock);
 	spin_lock_init(&rdev->didt_idx_lock);
 	spin_lock_init(&rdev->end_idx_lock);
 	if (rdev->family >= CHIP_BONAIRE) {
 		rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
 		rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
 	} else {
 		rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 		rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 	}
 	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 	if (rdev->rmmio == NULL) {
 		return -ENOMEM;
 	}
 	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 	/* doorbell bar mapping */
 	if (rdev->family >= CHIP_BONAIRE)
 		radeon_doorbell_init(rdev);
 	/* io port mapping */
 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
 			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
 			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
 			break;
 		}
 	}
 	if (rdev->rio_mem == NULL)
 		DRM_ERROR("Unable to find PCI I/O BAR\n");
 	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
 	/* this will fail for cards that aren't VGA class devices, just
 	 * ignore it */
 	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 	if (rdev->flags & RADEON_IS_PX)
 		runtime = true;
 	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
 	if (runtime)
 		vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
 	r = radeon_init(rdev);
 	if (r)
 		return r;
 	r = radeon_ib_ring_tests(rdev);
 	if (r)
 		DRM_ERROR("ib ring test failed (%d).\n", r);
 	r = radeon_gem_debugfs_init(rdev);
 	if (r) {
 		DRM_ERROR("registering gem debugfs failed (%d).\n", r);
 	}
 	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 		/* Acceleration not working on AGP card try again
 		 * with fallback to PCI or PCIE GART
 		 */
 		radeon_asic_reset(rdev);
 		radeon_fini(rdev);
 		radeon_agp_disable(rdev);
 		r = radeon_init(rdev);
 		if (r)
 			return r;
 	}
 	if ((radeon_testing & 1)) {
 		if (rdev->accel_working)
 			radeon_test_moves(rdev);
 		else
 			DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
 	}
 	if ((radeon_testing & 2)) {
 		if (rdev->accel_working)
 			radeon_test_syncing(rdev);
 		else
 			DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
 	}
 	if (radeon_benchmarking) {
 		if (rdev->accel_working)
 			radeon_benchmark(rdev, radeon_benchmarking);
 		else
 			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
 	}
 	return 0;
 }
 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
 /**
  * radeon_device_fini - tear down the driver
  *
  * @rdev: radeon_device pointer
  *
  * Tear down the driver info (all asics).
  * Called at driver shutdown.
  */
 void radeon_device_fini(struct radeon_device *rdev)
 {
 	DRM_INFO("radeon: finishing device.\n");
 	rdev->shutdown = true;
 	/* evict vram memory */
 	radeon_bo_evict_vram(rdev);
 	radeon_fini(rdev);
 	vga_switcheroo_unregister_client(rdev->pdev);
 	vga_client_register(rdev->pdev, NULL, NULL, NULL);
 	if (rdev->rio_mem)
 		pci_iounmap(rdev->pdev, rdev->rio_mem);
 	rdev->rio_mem = NULL;
 	iounmap(rdev->rmmio);
 	rdev->rmmio = NULL;
 	if (rdev->family >= CHIP_BONAIRE)
 		radeon_doorbell_fini(rdev);
 	radeon_debugfs_remove_files(rdev);
 }
 /*
  * Suspend & resume.
  */
 /**
  * radeon_suspend_kms - initiate device suspend
  *
  * @pdev: drm dev pointer
  * @state: suspend state
  *
  * Puts the hw in the suspend state (all asics).
  * Returns 0 for success or an error on failure.
  * Called at driver suspend.
  */
 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
 {
 	struct radeon_device *rdev;
 	struct drm_crtc *crtc;
 	struct drm_connector *connector;
 	int i, r;
 	bool force_completion = false;
 	if (dev == NULL || dev->dev_private == NULL) {
 		return -ENODEV;
 	}
 	rdev = dev->dev_private;
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	drm_kms_helper_poll_disable(dev);
 	/* turn off display hw */
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
 	}
 	/* unpin the front buffers */
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
 		struct radeon_bo *robj;
 		if (rfb == NULL || rfb->obj == NULL) {
 			continue;
 		}
 		robj = gem_to_radeon_bo(rfb->obj);
 		/* don't unpin kernel fb objects */
 		if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
 			r = radeon_bo_reserve(robj, false);
 			if (r == 0) {
 				radeon_bo_unpin(robj);
 				radeon_bo_unreserve(robj);
 			}
 		}
 	}
 	/* evict vram memory */
 	radeon_bo_evict_vram(rdev);
 	/* wait for gpu to finish processing current batch */
 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 		r = radeon_fence_wait_empty(rdev, i);
 		if (r) {
 			/* delay GPU reset to resume */
 			force_completion = true;
 		}
 	}
 	if (force_completion) {
 		radeon_fence_driver_force_completion(rdev);
 	}
 	radeon_save_bios_scratch_regs(rdev);
 	radeon_suspend(rdev);
 	radeon_hpd_fini(rdev);
 	/* evict remaining vram memory */
 	radeon_bo_evict_vram(rdev);
 	radeon_agp_suspend(rdev);
 	pci_save_state(dev->pdev);
 	if (suspend) {
 		/* Shut down the device */
 		pci_disable_device(dev->pdev);
 		pci_set_power_state(dev->pdev, PCI_D3hot);
 	}
 	if (fbcon) {
 		console_lock();
 		radeon_fbdev_set_suspend(rdev, 1);
 		console_unlock();
 	}
 	return 0;
 }
 /**
  * radeon_resume_kms - initiate device resume
  *
  * @pdev: drm dev pointer
  *
  * Bring the hw back to operating state (all asics).
  * Returns 0 for success or an error on failure.
  * Called at driver resume.
  */
 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
 {
 	struct drm_connector *connector;
 	struct radeon_device *rdev = dev->dev_private;
 	int r;
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	if (fbcon) {
 		console_lock();
 	}
 	if (resume) {
 		pci_set_power_state(dev->pdev, PCI_D0);
 		pci_restore_state(dev->pdev);
 		if (pci_enable_device(dev->pdev)) {
 			if (fbcon)
 				console_unlock();
 			return -1;
 		}
 	}
 	/* resume AGP if in use */
 	radeon_agp_resume(rdev);
 	radeon_resume(rdev);
 	r = radeon_ib_ring_tests(rdev);
 	if (r)
 		DRM_ERROR("ib ring test failed (%d).\n", r);
 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 		/* do dpm late init */
 		r = radeon_pm_late_init(rdev);
 		if (r) {
 			rdev->pm.dpm_enabled = false;
 			DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
 		}
 	} else {
 		/* resume old pm late */
 		radeon_pm_resume(rdev);
 	}
 	radeon_restore_bios_scratch_regs(rdev);
 	/* init dig PHYs, disp eng pll */
 	if (rdev->is_atom_bios) {
 		radeon_atom_encoder_init(rdev);
 		radeon_atom_disp_eng_pll_init(rdev);
 		/* turn on the BL */
 		if (rdev->mode_info.bl_encoder) {
 			u8 bl_level = radeon_get_backlight_level(rdev,
 								 rdev->mode_info.bl_encoder);
 			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
 						   bl_level);
 		}
 	}
 	/* reset hpd state */
 	radeon_hpd_init(rdev);
 	/* blat the mode back in */
 	if (fbcon) {
 		drm_helper_resume_force_mode(dev);
 		/* turn on display hw */
 		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
 		}
 	}
 	drm_kms_helper_poll_enable(dev);
+	/* set the power state here in case we are a PX system or headless */
+	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
+		radeon_pm_compute_clocks(rdev);
 	if (fbcon) {
 		radeon_fbdev_set_suspend(rdev, 0);
 		console_unlock();
 	}
 	return 0;
 }
 /**
  * radeon_gpu_reset - reset the asic
  *
  * @rdev: radeon device pointer
  *
  * Attempt the reset the GPU if it has hung (all asics).
  * Returns 0 for success or an error on failure.
  */
 int radeon_gpu_reset(struct radeon_device *rdev)
 {
 	unsigned ring_sizes[RADEON_NUM_RINGS];
 	uint32_t *ring_data[RADEON_NUM_RINGS];
 	bool saved = false;
 	int i, r;
 	int resched;
 	down_write(&rdev->exclusive_lock);
 	if (!rdev->needs_reset) {
 		up_write(&rdev->exclusive_lock);
 		return 0;
 	}
 	rdev->needs_reset = false;
 	radeon_save_bios_scratch_regs(rdev);
 	/* block TTM */
 	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 	radeon_pm_suspend(rdev);
 	radeon_suspend(rdev);
 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 		ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
 						   &ring_data[i]);
 		if (ring_sizes[i]) {
 			saved = true;
 			dev_info(rdev->dev, "Saved %d dwords of commands "
 				 "on ring %d.\n", ring_sizes[i], i);
 		}
 	}
 retry:
 	r = radeon_asic_reset(rdev);
 	if (!r) {
 		dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
 		radeon_resume(rdev);
 	}
 	radeon_restore_bios_scratch_regs(rdev);
 	if (!r) {
 		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 			radeon_ring_restore(rdev, &rdev->ring[i],
 					    ring_sizes[i], ring_data[i]);
 			ring_sizes[i] = 0;
 			ring_data[i] = NULL;
 		}
 		r = radeon_ib_ring_tests(rdev);
 		if (r) {
 			dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
 			if (saved) {
 				saved = false;
 				radeon_suspend(rdev);
 				goto retry;
 			}
 		}
 	} else {
 		radeon_fence_driver_force_completion(rdev);
 		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 			kfree(ring_data[i]);
 		}
 	}
 	radeon_pm_resume(rdev);
 	drm_helper_resume_force_mode(rdev->ddev);
 	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 	if (r) {
 		/* bad news, how to tell it to userspace ? */
 		dev_info(rdev->dev, "GPU reset failed\n");
 	}
 	up_write(&rdev->exclusive_lock);
 	return r;
 }
 /*
  * Debugfs
  */
 int radeon_debugfs_add_files(struct radeon_device *rdev,
 			     struct drm_info_list *files,
 			     unsigned nfiles)
 {
 	unsigned i;
 	for (i = 0; i < rdev->debugfs_count; i++) {
 		if (rdev->debugfs[i].files == files) {
 			/* Already registered */
 			return 0;
 		}
 	}
 	i = rdev->debugfs_count + 1;
 	if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
 		DRM_ERROR("Reached maximum number of debugfs components.\n");
 		DRM_ERROR("Report so we increase "
 		          "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
 		return -EINVAL;
 	}
 	rdev->debugfs[rdev->debugfs_count].files = files;
 	rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
 	rdev->debugfs_count = i;
 #if defined(CONFIG_DEBUG_FS)
 	drm_debugfs_create_files(files, nfiles,
 				 rdev->ddev->control->debugfs_root,
 				 rdev->ddev->control);
 	drm_debugfs_create_files(files, nfiles,
 				 rdev->ddev->primary->debugfs_root,
 				 rdev->ddev->primary);
 #endif
 	return 0;
 }
 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
 {
 #if defined(CONFIG_DEBUG_FS)
 	unsigned i;
 	for (i = 0; i < rdev->debugfs_count; i++) {
 		drm_debugfs_remove_files(rdev->debugfs[i].files,
 					 rdev->debugfs[i].num_files,
 					 rdev->ddev->control);
 		drm_debugfs_remove_files(rdev->debugfs[i].files,
 					 rdev->debugfs[i].num_files,
 					 rdev->ddev->primary);
 	}
 #endif
 }
 #if defined(CONFIG_DEBUG_FS)
 int radeon_debugfs_init(struct drm_minor *minor)
 {
 	return 0;
 }
 void radeon_debugfs_cleanup(struct drm_minor *minor)
 {
 }
 #endif

drivers/gpu/drm/radeon/radeon_pm.c

Diff comments View file @ 6548be5

 /*
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Rafał Miłecki <zajec5@gmail.com>
  *          Alex Deucher <alexdeucher@gmail.com>
  */
 #include <drm/drmP.h>
 #include "radeon.h"
 #include "avivod.h"
 #include "atom.h"
 #include <linux/power_supply.h>
 #include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
 #define RADEON_IDLE_LOOP_MS 100
 #define RADEON_RECLOCK_DELAY_MS 200
 #define RADEON_WAIT_VBLANK_TIMEOUT 200
 static const char *radeon_pm_state_type_name[5] = {
 	"",
 	"Powersave",
 	"Battery",
 	"Balanced",
 	"Performance",
 };
 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
 static void radeon_pm_update_profile(struct radeon_device *rdev);
 static void radeon_pm_set_clocks(struct radeon_device *rdev);
 int radeon_pm_get_type_index(struct radeon_device *rdev,
 			     enum radeon_pm_state_type ps_type,
 			     int instance)
 {
 	int i;
 	int found_instance = -1;
 	for (i = 0; i < rdev->pm.num_power_states; i++) {
 		if (rdev->pm.power_state[i].type == ps_type) {
 			found_instance++;
 			if (found_instance == instance)
 				return i;
 		}
 	}
 	/* return default if no match */
 	return rdev->pm.default_power_state_index;
 }
 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
 {
 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 		mutex_lock(&rdev->pm.mutex);
 		if (power_supply_is_system_supplied() > 0)
 			rdev->pm.dpm.ac_power = true;
 		else
 			rdev->pm.dpm.ac_power = false;
 		if (rdev->asic->dpm.enable_bapm)
 			radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
 		mutex_unlock(&rdev->pm.mutex);
         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 		if (rdev->pm.profile == PM_PROFILE_AUTO) {
 			mutex_lock(&rdev->pm.mutex);
 			radeon_pm_update_profile(rdev);
 			radeon_pm_set_clocks(rdev);
 			mutex_unlock(&rdev->pm.mutex);
 		}
 	}
 }
 static void radeon_pm_update_profile(struct radeon_device *rdev)
 {
 	switch (rdev->pm.profile) {
 	case PM_PROFILE_DEFAULT:
 		rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
 		break;
 	case PM_PROFILE_AUTO:
 		if (power_supply_is_system_supplied() > 0) {
 			if (rdev->pm.active_crtc_count > 1)
 				rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 			else
 				rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 		} else {
 			if (rdev->pm.active_crtc_count > 1)
 				rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 			else
 				rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 		}
 		break;
 	case PM_PROFILE_LOW:
 		if (rdev->pm.active_crtc_count > 1)
 			rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 		else
 			rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 		break;
 	case PM_PROFILE_MID:
 		if (rdev->pm.active_crtc_count > 1)
 			rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 		else
 			rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 		break;
 	case PM_PROFILE_HIGH:
 		if (rdev->pm.active_crtc_count > 1)
 			rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 		else
 			rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 		break;
 	}
 	if (rdev->pm.active_crtc_count == 0) {
 		rdev->pm.requested_power_state_index =
 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 		rdev->pm.requested_clock_mode_index =
 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 	} else {
 		rdev->pm.requested_power_state_index =
 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 		rdev->pm.requested_clock_mode_index =
 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 	}
 }
 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 {
 	struct radeon_bo *bo, *n;
 	if (list_empty(&rdev->gem.objects))
 		return;
 	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 			ttm_bo_unmap_virtual(&bo->tbo);
 	}
 }
 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 {
 	if (rdev->pm.active_crtcs) {
 		rdev->pm.vblank_sync = false;
 		wait_event_timeout(
 			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 	}
 }
 static void radeon_set_power_state(struct radeon_device *rdev)
 {
 	u32 sclk, mclk;
 	bool misc_after = false;
 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 		return;
 	if (radeon_gui_idle(rdev)) {
 		sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 			clock_info[rdev->pm.requested_clock_mode_index].sclk;
 		if (sclk > rdev->pm.default_sclk)
 			sclk = rdev->pm.default_sclk;
 		/* starting with BTC, there is one state that is used for both
 		 * MH and SH.  Difference is that we always use the high clock index for
 		 * mclk and vddci.
 		 */
 		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 		    (rdev->family >= CHIP_BARTS) &&
 		    rdev->pm.active_crtc_count &&
 		    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 		     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 			mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 				clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 		else
 			mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 				clock_info[rdev->pm.requested_clock_mode_index].mclk;
 		if (mclk > rdev->pm.default_mclk)
 			mclk = rdev->pm.default_mclk;
 		/* upvolt before raising clocks, downvolt after lowering clocks */
 		if (sclk < rdev->pm.current_sclk)
 			misc_after = true;
 		radeon_sync_with_vblank(rdev);
 		if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 			if (!radeon_pm_in_vbl(rdev))
 				return;
 		}
 		radeon_pm_prepare(rdev);
 		if (!misc_after)
 			/* voltage, pcie lanes, etc.*/
 			radeon_pm_misc(rdev);
 		/* set engine clock */
 		if (sclk != rdev->pm.current_sclk) {
 			radeon_pm_debug_check_in_vbl(rdev, false);
 			radeon_set_engine_clock(rdev, sclk);
 			radeon_pm_debug_check_in_vbl(rdev, true);
 			rdev->pm.current_sclk = sclk;
 			DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 		}
 		/* set memory clock */
 		if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 			radeon_pm_debug_check_in_vbl(rdev, false);
 			radeon_set_memory_clock(rdev, mclk);
 			radeon_pm_debug_check_in_vbl(rdev, true);
 			rdev->pm.current_mclk = mclk;
 			DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 		}
 		if (misc_after)
 			/* voltage, pcie lanes, etc.*/
 			radeon_pm_misc(rdev);
 		radeon_pm_finish(rdev);
 		rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 		rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 	} else
 		DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 }
 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 {
 	int i, r;
 	/* no need to take locks, etc. if nothing's going to change */
 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 		return;
 	mutex_lock(&rdev->ddev->struct_mutex);
 	down_write(&rdev->pm.mclk_lock);
 	mutex_lock(&rdev->ring_lock);
 	/* wait for the rings to drain */
 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 		struct radeon_ring *ring = &rdev->ring[i];
 		if (!ring->ready) {
 			continue;
 		}
 		r = radeon_fence_wait_empty(rdev, i);
 		if (r) {
 			/* needs a GPU reset dont reset here */
 			mutex_unlock(&rdev->ring_lock);
 			up_write(&rdev->pm.mclk_lock);
 			mutex_unlock(&rdev->ddev->struct_mutex);
 			return;
 		}
 	}
 	radeon_unmap_vram_bos(rdev);
 	if (rdev->irq.installed) {
 		for (i = 0; i < rdev->num_crtc; i++) {
 			if (rdev->pm.active_crtcs & (1 << i)) {
 				rdev->pm.req_vblank |= (1 << i);
 				drm_vblank_get(rdev->ddev, i);
 			}
 		}
 	}
 	radeon_set_power_state(rdev);
 	if (rdev->irq.installed) {
 		for (i = 0; i < rdev->num_crtc; i++) {
 			if (rdev->pm.req_vblank & (1 << i)) {
 				rdev->pm.req_vblank &= ~(1 << i);
 				drm_vblank_put(rdev->ddev, i);
 			}
 		}
 	}
 	/* update display watermarks based on new power state */
 	radeon_update_bandwidth_info(rdev);
 	if (rdev->pm.active_crtc_count)
 		radeon_bandwidth_update(rdev);
 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 	mutex_unlock(&rdev->ring_lock);
 	up_write(&rdev->pm.mclk_lock);
 	mutex_unlock(&rdev->ddev->struct_mutex);
 }
 static void radeon_pm_print_states(struct radeon_device *rdev)
 {
 	int i, j;
 	struct radeon_power_state *power_state;
 	struct radeon_pm_clock_info *clock_info;
 	DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 	for (i = 0; i < rdev->pm.num_power_states; i++) {
 		power_state = &rdev->pm.power_state[i];
 		DRM_DEBUG_DRIVER("State %d: %s\n", i,
 			radeon_pm_state_type_name[power_state->type]);
 		if (i == rdev->pm.default_power_state_index)
 			DRM_DEBUG_DRIVER("\tDefault");
 		if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 			DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 		if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 			DRM_DEBUG_DRIVER("\tSingle display only\n");
 		DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 		for (j = 0; j < power_state->num_clock_modes; j++) {
 			clock_info = &(power_state->clock_info[j]);
 			if (rdev->flags & RADEON_IS_IGP)
 				DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 						 j,
 						 clock_info->sclk * 10);
 			else
 				DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 						 j,
 						 clock_info->sclk * 10,
 						 clock_info->mclk * 10,
 						 clock_info->voltage.voltage);
 		}
 	}
 }
 static ssize_t radeon_get_pm_profile(struct device *dev,
 				     struct device_attribute *attr,
 				     char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	int cp = rdev->pm.profile;
 	return snprintf(buf, PAGE_SIZE, "%s\n",
 			(cp == PM_PROFILE_AUTO) ? "auto" :
 			(cp == PM_PROFILE_LOW) ? "low" :
 			(cp == PM_PROFILE_MID) ? "mid" :
 			(cp == PM_PROFILE_HIGH) ? "high" : "default");
 }
 static ssize_t radeon_set_pm_profile(struct device *dev,
 				     struct device_attribute *attr,
 				     const char *buf,
 				     size_t count)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	/* Can't set profile when the card is off */
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 	mutex_lock(&rdev->pm.mutex);
 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 		if (strncmp("default", buf, strlen("default")) == 0)
 			rdev->pm.profile = PM_PROFILE_DEFAULT;
 		else if (strncmp("auto", buf, strlen("auto")) == 0)
 			rdev->pm.profile = PM_PROFILE_AUTO;
 		else if (strncmp("low", buf, strlen("low")) == 0)
 			rdev->pm.profile = PM_PROFILE_LOW;
 		else if (strncmp("mid", buf, strlen("mid")) == 0)
 			rdev->pm.profile = PM_PROFILE_MID;
 		else if (strncmp("high", buf, strlen("high")) == 0)
 			rdev->pm.profile = PM_PROFILE_HIGH;
 		else {
 			count = -EINVAL;
 			goto fail;
 		}
 		radeon_pm_update_profile(rdev);
 		radeon_pm_set_clocks(rdev);
 	} else
 		count = -EINVAL;
 fail:
 	mutex_unlock(&rdev->pm.mutex);
 	return count;
 }
 static ssize_t radeon_get_pm_method(struct device *dev,
 				    struct device_attribute *attr,
 				    char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	int pm = rdev->pm.pm_method;
 	return snprintf(buf, PAGE_SIZE, "%s\n",
 			(pm == PM_METHOD_DYNPM) ? "dynpm" :
 			(pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 }
 static ssize_t radeon_set_pm_method(struct device *dev,
 				    struct device_attribute *attr,
 				    const char *buf,
 				    size_t count)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	/* Can't set method when the card is off */
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
 		count = -EINVAL;
 		goto fail;
 	}
 	/* we don't support the legacy modes with dpm */
 	if (rdev->pm.pm_method == PM_METHOD_DPM) {
 		count = -EINVAL;
 		goto fail;
 	}
 	if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 		mutex_lock(&rdev->pm.mutex);
 		rdev->pm.pm_method = PM_METHOD_DYNPM;
 		rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 		mutex_unlock(&rdev->pm.mutex);
 	} else if (strncmp("profile", buf, strlen("profile")) == 0) {
 		mutex_lock(&rdev->pm.mutex);
 		/* disable dynpm */
 		rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 		rdev->pm.pm_method = PM_METHOD_PROFILE;
 		mutex_unlock(&rdev->pm.mutex);
 		cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 	} else {
 		count = -EINVAL;
 		goto fail;
 	}
 	radeon_pm_compute_clocks(rdev);
 fail:
 	return count;
 }
 static ssize_t radeon_get_dpm_state(struct device *dev,
 				    struct device_attribute *attr,
 				    char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return snprintf(buf, PAGE_SIZE, "off\n");
 	return snprintf(buf, PAGE_SIZE, "%s\n",
 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 			(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 }
 static ssize_t radeon_set_dpm_state(struct device *dev,
 				    struct device_attribute *attr,
 				    const char *buf,
 				    size_t count)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	/* Can't set dpm state when the card is off */
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 	mutex_lock(&rdev->pm.mutex);
 	if (strncmp("battery", buf, strlen("battery")) == 0)
 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 	else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 	else if (strncmp("performance", buf, strlen("performance")) == 0)
 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 	else {
 		mutex_unlock(&rdev->pm.mutex);
 		count = -EINVAL;
 		goto fail;
 	}
 	mutex_unlock(&rdev->pm.mutex);
 	radeon_pm_compute_clocks(rdev);
 fail:
 	return count;
 }
 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 						       struct device_attribute *attr,
 						       char *buf)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return snprintf(buf, PAGE_SIZE, "off\n");
 	return snprintf(buf, PAGE_SIZE, "%s\n",
 			(level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 			(level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 }
 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 						       struct device_attribute *attr,
 						       const char *buf,
 						       size_t count)
 {
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct radeon_device *rdev = ddev->dev_private;
 	enum radeon_dpm_forced_level level;
 	int ret = 0;
 	/* Can't force performance level when the card is off */
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 	mutex_lock(&rdev->pm.mutex);
 	if (strncmp("low", buf, strlen("low")) == 0) {
 		level = RADEON_DPM_FORCED_LEVEL_LOW;
 	} else if (strncmp("high", buf, strlen("high")) == 0) {
 		level = RADEON_DPM_FORCED_LEVEL_HIGH;
 	} else if (strncmp("auto", buf, strlen("auto")) == 0) {
 		level = RADEON_DPM_FORCED_LEVEL_AUTO;
 	} else {
 		count = -EINVAL;
 		goto fail;
 	}
 	if (rdev->asic->dpm.force_performance_level) {
 		if (rdev->pm.dpm.thermal_active) {
 			count = -EINVAL;
 			goto fail;
 		}
 		ret = radeon_dpm_force_performance_level(rdev, level);
 		if (ret)
 			count = -EINVAL;
 	}
 fail:
 	mutex_unlock(&rdev->pm.mutex);
 	return count;
 }
 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 		   radeon_get_dpm_forced_performance_level,
 		   radeon_set_dpm_forced_performance_level);
 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 				      struct device_attribute *attr,
 				      char *buf)
 {
 	struct radeon_device *rdev = dev_get_drvdata(dev);
 	struct drm_device *ddev = rdev->ddev;
 	int temp;
 	/* Can't get temperature when the card is off */
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 	if (rdev->asic->pm.get_temperature)
 		temp = radeon_get_temperature(rdev);
 	else
 		temp = 0;
 	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 }
 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
 					     struct device_attribute *attr,
 					     char *buf)
 {
 	struct radeon_device *rdev = dev_get_drvdata(dev);
 	int hyst = to_sensor_dev_attr(attr)->index;
 	int temp;
 	if (hyst)
 		temp = rdev->pm.dpm.thermal.min_temp;
 	else
 		temp = rdev->pm.dpm.thermal.max_temp;
 	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 }
 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
 static struct attribute *hwmon_attributes[] = {
 	&sensor_dev_attr_temp1_input.dev_attr.attr,
 	&sensor_dev_attr_temp1_crit.dev_attr.attr,
 	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 	NULL
 };
 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 					struct attribute *attr, int index)
 {
 	struct device *dev = container_of(kobj, struct device, kobj);
 	struct radeon_device *rdev = dev_get_drvdata(dev);
 	/* Skip limit attributes if DPM is not enabled */
 	if (rdev->pm.pm_method != PM_METHOD_DPM &&
 	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
 		return 0;
 	return attr->mode;
 }
 static const struct attribute_group hwmon_attrgroup = {
 	.attrs = hwmon_attributes,
 	.is_visible = hwmon_attributes_visible,
 };
 static const struct attribute_group *hwmon_groups[] = {
 	&hwmon_attrgroup,
 	NULL
 };
 static int radeon_hwmon_init(struct radeon_device *rdev)
 {
 	int err = 0;
 	switch (rdev->pm.int_thermal_type) {
 	case THERMAL_TYPE_RV6XX:
 	case THERMAL_TYPE_RV770:
 	case THERMAL_TYPE_EVERGREEN:
 	case THERMAL_TYPE_NI:
 	case THERMAL_TYPE_SUMO:
 	case THERMAL_TYPE_SI:
 	case THERMAL_TYPE_CI:
 	case THERMAL_TYPE_KV:
 		if (rdev->asic->pm.get_temperature == NULL)
 			return err;
 		rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
 									   "radeon", rdev,
 									   hwmon_groups);
 		if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 			err = PTR_ERR(rdev->pm.int_hwmon_dev);
 			dev_err(rdev->dev,
 				"Unable to register hwmon device: %d\n", err);
 		}
 		break;
 	default:
 		break;
 	}
 	return err;
 }
 static void radeon_hwmon_fini(struct radeon_device *rdev)
 {
 	if (rdev->pm.int_hwmon_dev)
 		hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 }
 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 {
 	struct radeon_device *rdev =
 		container_of(work, struct radeon_device,
 			     pm.dpm.thermal.work);
 	/* switch to the thermal state */
 	enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 	if (!rdev->pm.dpm_enabled)
 		return;
 	if (rdev->asic->pm.get_temperature) {
 		int temp = radeon_get_temperature(rdev);
 		if (temp < rdev->pm.dpm.thermal.min_temp)
 			/* switch back the user state */
 			dpm_state = rdev->pm.dpm.user_state;
 	} else {
 		if (rdev->pm.dpm.thermal.high_to_low)
 			/* switch back the user state */
 			dpm_state = rdev->pm.dpm.user_state;
 	}
 	mutex_lock(&rdev->pm.mutex);
 	if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 		rdev->pm.dpm.thermal_active = true;
 	else
 		rdev->pm.dpm.thermal_active = false;
 	rdev->pm.dpm.state = dpm_state;
 	mutex_unlock(&rdev->pm.mutex);
 	radeon_pm_compute_clocks(rdev);
 }
 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 						     enum radeon_pm_state_type dpm_state)
 {
 	int i;
 	struct radeon_ps *ps;
 	u32 ui_class;
 	bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 		true : false;
 	/* check if the vblank period is too short to adjust the mclk */
 	if (single_display && rdev->asic->dpm.vblank_too_short) {
 		if (radeon_dpm_vblank_too_short(rdev))
 			single_display = false;
 	}
 	/* certain older asics have a separare 3D performance state,
 	 * so try that first if the user selected performance
 	 */
 	if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 		dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 	/* balanced states don't exist at the moment */
 	if (dpm_state == POWER_STATE_TYPE_BALANCED)
 		dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 restart_search:
 	/* Pick the best power state based on current conditions */
 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 		ps = &rdev->pm.dpm.ps[i];
 		ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 		switch (dpm_state) {
 		/* user states */
 		case POWER_STATE_TYPE_BATTERY:
 			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 					if (single_display)
 						return ps;
 				} else
 					return ps;
 			}
 			break;
 		case POWER_STATE_TYPE_BALANCED:
 			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 					if (single_display)
 						return ps;
 				} else
 					return ps;
 			}
 			break;
 		case POWER_STATE_TYPE_PERFORMANCE:
 			if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 				if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 					if (single_display)
 						return ps;
 				} else
 					return ps;
 			}
 			break;
 		/* internal states */
 		case POWER_STATE_TYPE_INTERNAL_UVD:
 			if (rdev->pm.dpm.uvd_ps)
 				return rdev->pm.dpm.uvd_ps;
 			else
 				break;
 		case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 			if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_BOOT:
 			return rdev->pm.dpm.boot_ps;
 		case POWER_STATE_TYPE_INTERNAL_THERMAL:
 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_ACPI:
 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_ULV:
 			if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 				return ps;
 			break;
 		case POWER_STATE_TYPE_INTERNAL_3DPERF:
 			if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 				return ps;
 			break;
 		default:
 			break;
 		}
 	}
 	/* use a fallback state if we didn't match */
 	switch (dpm_state) {
 	case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 		dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 		goto restart_search;
 	case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 	case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 	case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 		if (rdev->pm.dpm.uvd_ps) {
 			return rdev->pm.dpm.uvd_ps;
 		} else {
 			dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 			goto restart_search;
 		}
 	case POWER_STATE_TYPE_INTERNAL_THERMAL:
 		dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 		goto restart_search;
 	case POWER_STATE_TYPE_INTERNAL_ACPI:
 		dpm_state = POWER_STATE_TYPE_BATTERY;
 		goto restart_search;
 	case POWER_STATE_TYPE_BATTERY:
 	case POWER_STATE_TYPE_BALANCED:
 	case POWER_STATE_TYPE_INTERNAL_3DPERF:
 		dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 		goto restart_search;
 	default:
 		break;
 	}
 	return NULL;
 }
 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 {
 	int i;
 	struct radeon_ps *ps;
 	enum radeon_pm_state_type dpm_state;
 	int ret;
 	/* if dpm init failed */
 	if (!rdev->pm.dpm_enabled)
 		return;
 	if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 		/* add other state override checks here */
 		if ((!rdev->pm.dpm.thermal_active) &&
 		    (!rdev->pm.dpm.uvd_active))
 			rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 	}
 	dpm_state = rdev->pm.dpm.state;
 	ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 	if (ps)
 		rdev->pm.dpm.requested_ps = ps;
 	else
 		return;
 	/* no need to reprogram if nothing changed unless we are on BTC+ */
 	if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 		/* vce just modifies an existing state so force a change */
 		if (ps->vce_active != rdev->pm.dpm.vce_active)
 			goto force;
 		if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 			/* for pre-BTC and APUs if the num crtcs changed but state is the same,
 			 * all we need to do is update the display configuration.
 			 */
 			if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 				/* update display watermarks based on new power state */
 				radeon_bandwidth_update(rdev);
 				/* update displays */
 				radeon_dpm_display_configuration_changed(rdev);
 				rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 				rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 			}
 			return;
 		} else {
 			/* for BTC+ if the num crtcs hasn't changed and state is the same,
 			 * nothing to do, if the num crtcs is > 1 and state is the same,
 			 * update display configuration.
 			 */
 			if (rdev->pm.dpm.new_active_crtcs ==
 			    rdev->pm.dpm.current_active_crtcs) {
 				return;
 			} else {
 				if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 				    (rdev->pm.dpm.new_active_crtc_count > 1)) {
 					/* update display watermarks based on new power state */
 					radeon_bandwidth_update(rdev);
 					/* update displays */
 					radeon_dpm_display_configuration_changed(rdev);
 					rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 					rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 					return;
 				}
 			}
 		}
 	}
 force:
 	if (radeon_dpm == 1) {
 		printk("switching from power state:\n");
 		radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 		printk("switching to power state:\n");
 		radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 	}
 	mutex_lock(&rdev->ddev->struct_mutex);
 	down_write(&rdev->pm.mclk_lock);
 	mutex_lock(&rdev->ring_lock);
 	/* update whether vce is active */
 	ps->vce_active = rdev->pm.dpm.vce_active;
 	ret = radeon_dpm_pre_set_power_state(rdev);
 	if (ret)
 		goto done;
 	/* update display watermarks based on new power state */
 	radeon_bandwidth_update(rdev);
 	/* update displays */
 	radeon_dpm_display_configuration_changed(rdev);
 	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 	/* wait for the rings to drain */
 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 		struct radeon_ring *ring = &rdev->ring[i];
 		if (ring->ready)
 			radeon_fence_wait_empty(rdev, i);
 	}
 	/* program the new power state */
 	radeon_dpm_set_power_state(rdev);
 	/* update current power state */
 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 	radeon_dpm_post_set_power_state(rdev);
 	if (rdev->asic->dpm.force_performance_level) {
 		if (rdev->pm.dpm.thermal_active) {
 			enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 			/* force low perf level for thermal */
 			radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
 			/* save the user's level */
 			rdev->pm.dpm.forced_level = level;
 		} else {
 			/* otherwise, user selected level */
 			radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
 		}
 	}
 done:
 	mutex_unlock(&rdev->ring_lock);
 	up_write(&rdev->pm.mclk_lock);
 	mutex_unlock(&rdev->ddev->struct_mutex);
 }
 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
 {
 	enum radeon_pm_state_type dpm_state;
 	if (rdev->asic->dpm.powergate_uvd) {
 		mutex_lock(&rdev->pm.mutex);
 		/* don't powergate anything if we
 		   have active but pause streams */
 		enable |= rdev->pm.dpm.sd > 0;
 		enable |= rdev->pm.dpm.hd > 0;
 		/* enable/disable UVD */
 		radeon_dpm_powergate_uvd(rdev, !enable);
 		mutex_unlock(&rdev->pm.mutex);
 	} else {
 		if (enable) {
 			mutex_lock(&rdev->pm.mutex);
 			rdev->pm.dpm.uvd_active = true;
 			if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
 			else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 			else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 			else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
 			else
 				dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
 			rdev->pm.dpm.state = dpm_state;
 			mutex_unlock(&rdev->pm.mutex);
 		} else {
 			mutex_lock(&rdev->pm.mutex);
 			rdev->pm.dpm.uvd_active = false;
 			mutex_unlock(&rdev->pm.mutex);
 		}
 		radeon_pm_compute_clocks(rdev);
 	}
 }
 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
 {
 	if (enable) {
 		mutex_lock(&rdev->pm.mutex);
 		rdev->pm.dpm.vce_active = true;
 		/* XXX select vce level based on ring/task */
 		rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
 		mutex_unlock(&rdev->pm.mutex);
 	} else {
 		mutex_lock(&rdev->pm.mutex);
 		rdev->pm.dpm.vce_active = false;
 		mutex_unlock(&rdev->pm.mutex);
 	}
 	radeon_pm_compute_clocks(rdev);
 }
 static void radeon_pm_suspend_old(struct radeon_device *rdev)
 {
 	mutex_lock(&rdev->pm.mutex);
 	if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 		if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 			rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 	}
 	mutex_unlock(&rdev->pm.mutex);
 	cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 }
 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
 {
 	mutex_lock(&rdev->pm.mutex);
 	/* disable dpm */
 	radeon_dpm_disable(rdev);
 	/* reset the power state */
 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 	rdev->pm.dpm_enabled = false;
 	mutex_unlock(&rdev->pm.mutex);
 }
 void radeon_pm_suspend(struct radeon_device *rdev)
 {
 	if (rdev->pm.pm_method == PM_METHOD_DPM)
 		radeon_pm_suspend_dpm(rdev);
 	else
 		radeon_pm_suspend_old(rdev);
 }
 static void radeon_pm_resume_old(struct radeon_device *rdev)
 {
 	/* set up the default clocks if the MC ucode is loaded */
 	if ((rdev->family >= CHIP_BARTS) &&
 	    (rdev->family <= CHIP_CAYMAN) &&
 	    rdev->mc_fw) {
 		if (rdev->pm.default_vddc)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 						SET_VOLTAGE_TYPE_ASIC_VDDC);
 		if (rdev->pm.default_vddci)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 						SET_VOLTAGE_TYPE_ASIC_VDDCI);
 		if (rdev->pm.default_sclk)
 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 		if (rdev->pm.default_mclk)
 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 	}
 	/* asic init will reset the default power state */
 	mutex_lock(&rdev->pm.mutex);
 	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 	rdev->pm.current_clock_mode_index = 0;
 	rdev->pm.current_sclk = rdev->pm.default_sclk;
 	rdev->pm.current_mclk = rdev->pm.default_mclk;
 	if (rdev->pm.power_state) {
 		rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 		rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 	}
 	if (rdev->pm.pm_method == PM_METHOD_DYNPM
 	    && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 		rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 		schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 				      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 	}
 	mutex_unlock(&rdev->pm.mutex);
 	radeon_pm_compute_clocks(rdev);
 }
 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
 {
 	int ret;
 	/* asic init will reset to the boot state */
 	mutex_lock(&rdev->pm.mutex);
 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 	radeon_dpm_setup_asic(rdev);
 	ret = radeon_dpm_enable(rdev);
 	mutex_unlock(&rdev->pm.mutex);
 	if (ret)
 		goto dpm_resume_fail;
 	rdev->pm.dpm_enabled = true;
-	radeon_pm_compute_clocks(rdev);
 	return;
 dpm_resume_fail:
 	DRM_ERROR("radeon: dpm resume failed\n");
 	if ((rdev->family >= CHIP_BARTS) &&
 	    (rdev->family <= CHIP_CAYMAN) &&
 	    rdev->mc_fw) {
 		if (rdev->pm.default_vddc)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 						SET_VOLTAGE_TYPE_ASIC_VDDC);
 		if (rdev->pm.default_vddci)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 						SET_VOLTAGE_TYPE_ASIC_VDDCI);
 		if (rdev->pm.default_sclk)
 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 		if (rdev->pm.default_mclk)
 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 	}
 }
 void radeon_pm_resume(struct radeon_device *rdev)
 {
 	if (rdev->pm.pm_method == PM_METHOD_DPM)
 		radeon_pm_resume_dpm(rdev);
 	else
 		radeon_pm_resume_old(rdev);
 }
 static int radeon_pm_init_old(struct radeon_device *rdev)
 {
 	int ret;
 	rdev->pm.profile = PM_PROFILE_DEFAULT;
 	rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 	rdev->pm.dynpm_can_upclock = true;
 	rdev->pm.dynpm_can_downclock = true;
 	rdev->pm.default_sclk = rdev->clock.default_sclk;
 	rdev->pm.default_mclk = rdev->clock.default_mclk;
 	rdev->pm.current_sclk = rdev->clock.default_sclk;
 	rdev->pm.current_mclk = rdev->clock.default_mclk;
 	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 	if (rdev->bios) {
 		if (rdev->is_atom_bios)
 			radeon_atombios_get_power_modes(rdev);
 		else
 			radeon_combios_get_power_modes(rdev);
 		radeon_pm_print_states(rdev);
 		radeon_pm_init_profile(rdev);
 		/* set up the default clocks if the MC ucode is loaded */
 		if ((rdev->family >= CHIP_BARTS) &&
 		    (rdev->family <= CHIP_CAYMAN) &&
 		    rdev->mc_fw) {
 			if (rdev->pm.default_vddc)
 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 							SET_VOLTAGE_TYPE_ASIC_VDDC);
 			if (rdev->pm.default_vddci)
 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 							SET_VOLTAGE_TYPE_ASIC_VDDCI);
 			if (rdev->pm.default_sclk)
 				radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 			if (rdev->pm.default_mclk)
 				radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 		}
 	}
 	/* set up the internal thermal sensor if applicable */
 	ret = radeon_hwmon_init(rdev);
 	if (ret)
 		return ret;
 	INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 	if (rdev->pm.num_power_states > 1) {
 		/* where's the best place to put these? */
 		ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 		if (ret)
 			DRM_ERROR("failed to create device file for power profile\n");
 		ret = device_create_file(rdev->dev, &dev_attr_power_method);
 		if (ret)
 			DRM_ERROR("failed to create device file for power method\n");
 		if (radeon_debugfs_pm_init(rdev)) {
 			DRM_ERROR("Failed to register debugfs file for PM!\n");
 		}
 		DRM_INFO("radeon: power management initialized\n");
 	}
 	return 0;
 }
 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
 {
 	int i;
 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 		printk("== power state %d ==\n", i);
 		radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
 	}
 }
 static int radeon_pm_init_dpm(struct radeon_device *rdev)
 {
 	int ret;
 	/* default to balanced state */
 	rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
 	rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
 	rdev->pm.default_sclk = rdev->clock.default_sclk;
 	rdev->pm.default_mclk = rdev->clock.default_mclk;
 	rdev->pm.current_sclk = rdev->clock.default_sclk;
 	rdev->pm.current_mclk = rdev->clock.default_mclk;
 	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 	if (rdev->bios && rdev->is_atom_bios)
 		radeon_atombios_get_power_modes(rdev);
 	else
 		return -EINVAL;
 	/* set up the internal thermal sensor if applicable */
 	ret = radeon_hwmon_init(rdev);
 	if (ret)
 		return ret;
 	INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
 	mutex_lock(&rdev->pm.mutex);
 	radeon_dpm_init(rdev);
 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 	if (radeon_dpm == 1)
 		radeon_dpm_print_power_states(rdev);
 	radeon_dpm_setup_asic(rdev);
 	ret = radeon_dpm_enable(rdev);
 	mutex_unlock(&rdev->pm.mutex);
 	if (ret)
 		goto dpm_failed;
 	rdev->pm.dpm_enabled = true;
 	ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
 	if (ret)
 		DRM_ERROR("failed to create device file for dpm state\n");
 	ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
 	if (ret)
 		DRM_ERROR("failed to create device file for dpm state\n");
 	/* XXX: these are noops for dpm but are here for backwards compat */
 	ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 	if (ret)
 		DRM_ERROR("failed to create device file for power profile\n");
 	ret = device_create_file(rdev->dev, &dev_attr_power_method);
 	if (ret)
 		DRM_ERROR("failed to create device file for power method\n");
 	if (radeon_debugfs_pm_init(rdev)) {
 		DRM_ERROR("Failed to register debugfs file for dpm!\n");
 	}
 	DRM_INFO("radeon: dpm initialized\n");
 	return 0;
 dpm_failed:
 	rdev->pm.dpm_enabled = false;
 	if ((rdev->family >= CHIP_BARTS) &&
 	    (rdev->family <= CHIP_CAYMAN) &&
 	    rdev->mc_fw) {
 		if (rdev->pm.default_vddc)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 						SET_VOLTAGE_TYPE_ASIC_VDDC);
 		if (rdev->pm.default_vddci)
 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 						SET_VOLTAGE_TYPE_ASIC_VDDCI);
 		if (rdev->pm.default_sclk)
 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 		if (rdev->pm.default_mclk)
 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 	}
 	DRM_ERROR("radeon: dpm initialization failed\n");
 	return ret;
 }
 int radeon_pm_init(struct radeon_device *rdev)
 {
 	/* enable dpm on rv6xx+ */
 	switch (rdev->family) {
 	case CHIP_RV610:
 	case CHIP_RV630:
 	case CHIP_RV620:
 	case CHIP_RV635:
 	case CHIP_RV670:
 	case CHIP_RS780:
 	case CHIP_RS880:
 	case CHIP_RV770:
 	case CHIP_BARTS:
 	case CHIP_TURKS:
 	case CHIP_CAICOS:
 	case CHIP_CAYMAN:
 		/* DPM requires the RLC, RV770+ dGPU requires SMC */
 		if (!rdev->rlc_fw)
 			rdev->pm.pm_method = PM_METHOD_PROFILE;
 		else if ((rdev->family >= CHIP_RV770) &&
 			 (!(rdev->flags & RADEON_IS_IGP)) &&
 			 (!rdev->smc_fw))
 			rdev->pm.pm_method = PM_METHOD_PROFILE;
 		else if (radeon_dpm == 1)
 			rdev->pm.pm_method = PM_METHOD_DPM;
 		else
 			rdev->pm.pm_method = PM_METHOD_PROFILE;
 		break;
 	case CHIP_RV730:
 	case CHIP_RV710:
 	case CHIP_RV740:
 	case CHIP_CEDAR:
 	case CHIP_REDWOOD:
 	case CHIP_JUNIPER:
 	case CHIP_CYPRESS:
 	case CHIP_HEMLOCK:
 	case CHIP_PALM:
 	case CHIP_SUMO:
 	case CHIP_SUMO2:
 	case CHIP_ARUBA:
 	case CHIP_TAHITI:
 	case CHIP_PITCAIRN:
 	case CHIP_VERDE:
 	case CHIP_OLAND:
 	case CHIP_HAINAN:
 	case CHIP_BONAIRE:
 	case CHIP_KABINI:
 	case CHIP_KAVERI:
 	case CHIP_HAWAII:
 	case CHIP_MULLINS:
 		/* DPM requires the RLC, RV770+ dGPU requires SMC */
 		if (!rdev->rlc_fw)
 			rdev->pm.pm_method = PM_METHOD_PROFILE;
 		else if ((rdev->family >= CHIP_RV770) &&
 			 (!(rdev->flags & RADEON_IS_IGP)) &&
 			 (!rdev->smc_fw))
 			rdev->pm.pm_method = PM_METHOD_PROFILE;
 		else if (radeon_dpm == 0)
 			rdev->pm.pm_method = PM_METHOD_PROFILE;
 		else
 			rdev->pm.pm_method = PM_METHOD_DPM;
 		break;
 	default:
 		/* default to profile method */
 		rdev->pm.pm_method = PM_METHOD_PROFILE;
 		break;
 	}
 	if (rdev->pm.pm_method == PM_METHOD_DPM)
 		return radeon_pm_init_dpm(rdev);
 	else
 		return radeon_pm_init_old(rdev);
 }
 int radeon_pm_late_init(struct radeon_device *rdev)
 {
 	int ret = 0;
 	if (rdev->pm.pm_method == PM_METHOD_DPM) {
 		mutex_lock(&rdev->pm.mutex);
 		ret = radeon_dpm_late_enable(rdev);
 		mutex_unlock(&rdev->pm.mutex);
 	}
 	return ret;
 }
 static void radeon_pm_fini_old(struct radeon_device *rdev)
 {
 	if (rdev->pm.num_power_states > 1) {
 		mutex_lock(&rdev->pm.mutex);
 		if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 			rdev->pm.profile = PM_PROFILE_DEFAULT;
 			radeon_pm_update_profile(rdev);
 			radeon_pm_set_clocks(rdev);
 		} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 			/* reset default clocks */
 			rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 			rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 			radeon_pm_set_clocks(rdev);
 		}
 		mutex_unlock(&rdev->pm.mutex);
 		cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 		device_remove_file(rdev->dev, &dev_attr_power_profile);
 		device_remove_file(rdev->dev, &dev_attr_power_method);
 	}
 	radeon_hwmon_fini(rdev);
 	if (rdev->pm.power_state)
 		kfree(rdev->pm.power_state);
 }
 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
 {
 	if (rdev->pm.num_power_states > 1) {
 		mutex_lock(&rdev->pm.mutex);
 		radeon_dpm_disable(rdev);
 		mutex_unlock(&rdev->pm.mutex);
 		device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
 		device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
 		/* XXX backwards compat */
 		device_remove_file(rdev->dev, &dev_attr_power_profile);
 		device_remove_file(rdev->dev, &dev_attr_power_method);
 	}
 	radeon_dpm_fini(rdev);
 	radeon_hwmon_fini(rdev);
 	if (rdev->pm.power_state)
 		kfree(rdev->pm.power_state);
 }
 void radeon_pm_fini(struct radeon_device *rdev)
 {
 	if (rdev->pm.pm_method == PM_METHOD_DPM)
 		radeon_pm_fini_dpm(rdev);
 	else
 		radeon_pm_fini_old(rdev);
 }
 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
 {
 	struct drm_device *ddev = rdev->ddev;
 	struct drm_crtc *crtc;
 	struct radeon_crtc *radeon_crtc;
 	if (rdev->pm.num_power_states < 2)
 		return;
 	mutex_lock(&rdev->pm.mutex);
 	rdev->pm.active_crtcs = 0;
 	rdev->pm.active_crtc_count = 0;
 	if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
 		list_for_each_entry(crtc,
 				    &ddev->mode_config.crtc_list, head) {
 			radeon_crtc = to_radeon_crtc(crtc);
 			if (radeon_crtc->enabled) {
 				rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 				rdev->pm.active_crtc_count++;
 			}
 		}
 	}
 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 		radeon_pm_update_profile(rdev);
 		radeon_pm_set_clocks(rdev);
 	} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 		if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 			if (rdev->pm.active_crtc_count > 1) {
 				if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 					rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 					radeon_pm_get_dynpm_state(rdev);
 					radeon_pm_set_clocks(rdev);
 					DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 				}
 			} else if (rdev->pm.active_crtc_count == 1) {
 				/* TODO: Increase clocks if needed for current mode */
 				if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 					radeon_pm_get_dynpm_state(rdev);
 					radeon_pm_set_clocks(rdev);
 					schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 							      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 				} else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 					schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 							      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 					DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 				}
 			} else { /* count == 0 */
 				if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 					rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 					radeon_pm_get_dynpm_state(rdev);
 					radeon_pm_set_clocks(rdev);
 				}
 			}
 		}
 	}
 	mutex_unlock(&rdev->pm.mutex);
 }
 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
 {
 	struct drm_device *ddev = rdev->ddev;
 	struct drm_crtc *crtc;
 	struct radeon_crtc *radeon_crtc;
 	if (!rdev->pm.dpm_enabled)
 		return;
 	mutex_lock(&rdev->pm.mutex);
 	/* update active crtc counts */
 	rdev->pm.dpm.new_active_crtcs = 0;
 	rdev->pm.dpm.new_active_crtc_count = 0;
 	if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
 		list_for_each_entry(crtc,
 				    &ddev->mode_config.crtc_list, head) {
 			radeon_crtc = to_radeon_crtc(crtc);
 			if (crtc->enabled) {
 				rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
 				rdev->pm.dpm.new_active_crtc_count++;
 			}
 		}
 	}
 	/* update battery/ac status */
 	if (power_supply_is_system_supplied() > 0)
 		rdev->pm.dpm.ac_power = true;
 	else
 		rdev->pm.dpm.ac_power = false;
 	radeon_dpm_change_power_state_locked(rdev);
 	mutex_unlock(&rdev->pm.mutex);
 }
 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 {
 	if (rdev->pm.pm_method == PM_METHOD_DPM)
 		radeon_pm_compute_clocks_dpm(rdev);
 	else
 		radeon_pm_compute_clocks_old(rdev);
 }
 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 {
 	int  crtc, vpos, hpos, vbl_status;
 	bool in_vbl = true;
 	/* Iterate over all active crtc's. All crtc's must be in vblank,
 	 * otherwise return in_vbl == false.
 	 */
 	for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 		if (rdev->pm.active_crtcs & (1 << crtc)) {
 			vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
 			if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 			    !(vbl_status & DRM_SCANOUTPOS_INVBL))
 				in_vbl = false;
 		}
 	}
 	return in_vbl;
 }
 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 {
 	u32 stat_crtc = 0;
 	bool in_vbl = radeon_pm_in_vbl(rdev);
 	if (in_vbl == false)
 		DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 			 finish ? "exit" : "entry");
 	return in_vbl;
 }
 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 {
 	struct radeon_device *rdev;
 	int resched;
 	rdev = container_of(work, struct radeon_device,
 				pm.dynpm_idle_work.work);
 	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 	mutex_lock(&rdev->pm.mutex);
 	if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 		int not_processed = 0;
 		int i;
 		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 			struct radeon_ring *ring = &rdev->ring[i];
 			if (ring->ready) {
 				not_processed += radeon_fence_count_emitted(rdev, i);
 				if (not_processed >= 3)
 					break;
 			}
 		}
 		if (not_processed >= 3) { /* should upclock */
 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 				   rdev->pm.dynpm_can_upclock) {
 				rdev->pm.dynpm_planned_action =
 					DYNPM_ACTION_UPCLOCK;
 				rdev->pm.dynpm_action_timeout = jiffies +
 				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 			}
 		} else if (not_processed == 0) { /* should downclock */
 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 				   rdev->pm.dynpm_can_downclock) {
 				rdev->pm.dynpm_planned_action =
 					DYNPM_ACTION_DOWNCLOCK;
 				rdev->pm.dynpm_action_timeout = jiffies +
 				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 			}
 		}
 		/* Note, radeon_pm_set_clocks is called with static_switch set
 		 * to false since we want to wait for vbl to avoid flicker.
 		 */
 		if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 		    jiffies > rdev->pm.dynpm_action_timeout) {
 			radeon_pm_get_dynpm_state(rdev);
 			radeon_pm_set_clocks(rdev);
 		}
 		schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 				      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 	}
 	mutex_unlock(&rdev->pm.mutex);
 	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 }
 /*
  * Debugfs info
  */
 #if defined(CONFIG_DEBUG_FS)
 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 {
 	struct drm_info_node *node = (struct drm_info_node *) m->private;
 	struct drm_device *dev = node->minor->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_device *ddev = rdev->ddev;
 	if  ((rdev->flags & RADEON_IS_PX) &&
 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
 		seq_printf(m, "PX asic powered off\n");
 	} else if (rdev->pm.dpm_enabled) {
 		mutex_lock(&rdev->pm.mutex);
 		if (rdev->asic->dpm.debugfs_print_current_performance_level)
 			radeon_dpm_debugfs_print_current_performance_level(rdev, m);
 		else
 			seq_printf(m, "Debugfs support not implemented for this asic\n");
 		mutex_unlock(&rdev->pm.mutex);
 	} else {
 		seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 		/* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
 		if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
 			seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
 		else
 			seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 		seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 		if (rdev->asic->pm.get_memory_clock)
 			seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 		if (rdev->pm.current_vddc)
 			seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 		if (rdev->asic->pm.get_pcie_lanes)
 			seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 	}
 	return 0;
 }
 static struct drm_info_list radeon_pm_info_list[] = {
 	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 };
 #endif
 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 {
 #if defined(CONFIG_DEBUG_FS)
 	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 #else
 	return 0;
 #endif
 }

drivers/gpu/drm/radeon/radeon_vm.c

Diff comments View file @ 6548be5

 /*
  * Copyright 2008 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  * Copyright 2009 Jerome Glisse.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
  */
 #include <drm/drmP.h>
 #include <drm/radeon_drm.h>
 #include "radeon.h"
 #include "radeon_trace.h"
 /*
  * GPUVM
  * GPUVM is similar to the legacy gart on older asics, however
  * rather than there being a single global gart table
  * for the entire GPU, there are multiple VM page tables active
  * at any given time.  The VM page tables can contain a mix
  * vram pages and system memory pages and system memory pages
  * can be mapped as snooped (cached system pages) or unsnooped
  * (uncached system pages).
  * Each VM has an ID associated with it and there is a page table
  * associated with each VMID.  When execting a command buffer,
  * the kernel tells the the ring what VMID to use for that command
  * buffer.  VMIDs are allocated dynamically as commands are submitted.
  * The userspace drivers maintain their own address space and the kernel
  * sets up their pages tables accordingly when they submit their
  * command buffers and a VMID is assigned.
  * Cayman/Trinity support up to 8 active VMs at any given time;
  * SI supports 16.
  */
 /**
  * radeon_vm_num_pde - return the number of page directory entries
  *
  * @rdev: radeon_device pointer
  *
  * Calculate the number of page directory entries (cayman+).
  */
 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
 {
 	return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE;
 }
 /**
  * radeon_vm_directory_size - returns the size of the page directory in bytes
  *
  * @rdev: radeon_device pointer
  *
  * Calculate the size of the page directory in bytes (cayman+).
  */
 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
 {
 	return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
 }
 /**
  * radeon_vm_manager_init - init the vm manager
  *
  * @rdev: radeon_device pointer
  *
  * Init the vm manager (cayman+).
  * Returns 0 for success, error for failure.
  */
 int radeon_vm_manager_init(struct radeon_device *rdev)
 {
 	int r;
 	if (!rdev->vm_manager.enabled) {
 		r = radeon_asic_vm_init(rdev);
 		if (r)
 			return r;
 		rdev->vm_manager.enabled = true;
 	}
 	return 0;
 }
 /**
  * radeon_vm_manager_fini - tear down the vm manager
  *
  * @rdev: radeon_device pointer
  *
  * Tear down the VM manager (cayman+).
  */
 void radeon_vm_manager_fini(struct radeon_device *rdev)
 {
 	int i;
 	if (!rdev->vm_manager.enabled)
 		return;
 	for (i = 0; i < RADEON_NUM_VM; ++i)
 		radeon_fence_unref(&rdev->vm_manager.active[i]);
 	radeon_asic_vm_fini(rdev);
 	rdev->vm_manager.enabled = false;
 }
 /**
  * radeon_vm_get_bos - add the vm BOs to a validation list
  *
  * @vm: vm providing the BOs
  * @head: head of validation list
  *
  * Add the page directory to the list of BOs to
  * validate for command submission (cayman+).
  */
 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
 					  struct radeon_vm *vm,
 					  struct list_head *head)
 {
 	struct radeon_cs_reloc *list;
 	unsigned i, idx;
-	list = kmalloc_array(vm->max_pde_used + 1,
+	list = kmalloc_array(vm->max_pde_used + 2,
 			     sizeof(struct radeon_cs_reloc), GFP_KERNEL);
 	if (!list)
 		return NULL;
 	/* add the vm page table to the list */
 	list[0].gobj = NULL;
 	list[0].robj = vm->page_directory;
 	list[0].domain = RADEON_GEM_DOMAIN_VRAM;
 	list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM;
 	list[0].tv.bo = &vm->page_directory->tbo;
 	list[0].tiling_flags = 0;
 	list[0].handle = 0;
 	list_add(&list[0].tv.head, head);
 	for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
 		if (!vm->page_tables[i].bo)
 			continue;
 		list[idx].gobj = NULL;
 		list[idx].robj = vm->page_tables[i].bo;
 		list[idx].domain = RADEON_GEM_DOMAIN_VRAM;
 		list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM;
 		list[idx].tv.bo = &list[idx].robj->tbo;
 		list[idx].tiling_flags = 0;
 		list[idx].handle = 0;
 		list_add(&list[idx++].tv.head, head);
 	}
 	return list;
 }
 /**
  * radeon_vm_grab_id - allocate the next free VMID
  *
  * @rdev: radeon_device pointer
  * @vm: vm to allocate id for
  * @ring: ring we want to submit job to
  *
  * Allocate an id for the vm (cayman+).
  * Returns the fence we need to sync to (if any).
  *
  * Global and local mutex must be locked!
  */
 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
 				       struct radeon_vm *vm, int ring)
 {
 	struct radeon_fence *best[RADEON_NUM_RINGS] = {};
 	unsigned choices[2] = {};
 	unsigned i;
 	/* check if the id is still valid */
 	if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
 		return NULL;
 	/* we definately need to flush */
 	radeon_fence_unref(&vm->last_flush);
 	/* skip over VMID 0, since it is the system VM */
 	for (i = 1; i < rdev->vm_manager.nvm; ++i) {
 		struct radeon_fence *fence = rdev->vm_manager.active[i];
 		if (fence == NULL) {
 			/* found a free one */
 			vm->id = i;
 			trace_radeon_vm_grab_id(vm->id, ring);
 			return NULL;
 		}
 		if (radeon_fence_is_earlier(fence, best[fence->ring])) {
 			best[fence->ring] = fence;
 			choices[fence->ring == ring ? 0 : 1] = i;
 		}
 	}
 	for (i = 0; i < 2; ++i) {
 		if (choices[i]) {
 			vm->id = choices[i];
 			trace_radeon_vm_grab_id(vm->id, ring);
 			return rdev->vm_manager.active[choices[i]];
 		}
 	}
 	/* should never happen */
 	BUG();
 	return NULL;
 }
 /**
  * radeon_vm_flush - hardware flush the vm
  *
  * @rdev: radeon_device pointer
  * @vm: vm we want to flush
  * @ring: ring to use for flush
  *
  * Flush the vm (cayman+).
  *
  * Global and local mutex must be locked!
  */
 void radeon_vm_flush(struct radeon_device *rdev,
 		     struct radeon_vm *vm,
 		     int ring)
 {
 	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
 	/* if we can't remember our last VM flush then flush now! */
 	/* XXX figure out why we have to flush all the time */
 	if (!vm->last_flush || true || pd_addr != vm->pd_gpu_addr) {
 		vm->pd_gpu_addr = pd_addr;
 		radeon_ring_vm_flush(rdev, ring, vm);
 	}
 }
 /**
  * radeon_vm_fence - remember fence for vm
  *
  * @rdev: radeon_device pointer
  * @vm: vm we want to fence
  * @fence: fence to remember
  *
  * Fence the vm (cayman+).
  * Set the fence used to protect page table and id.
  *
  * Global and local mutex must be locked!
  */
 void radeon_vm_fence(struct radeon_device *rdev,
 		     struct radeon_vm *vm,
 		     struct radeon_fence *fence)
 {
 	radeon_fence_unref(&vm->fence);
 	vm->fence = radeon_fence_ref(fence);
 	radeon_fence_unref(&rdev->vm_manager.active[vm->id]);
 	rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence);
 	radeon_fence_unref(&vm->last_id_use);
 	vm->last_id_use = radeon_fence_ref(fence);
         /* we just flushed the VM, remember that */
         if (!vm->last_flush)
                 vm->last_flush = radeon_fence_ref(fence);
 }
 /**
  * radeon_vm_bo_find - find the bo_va for a specific vm & bo
  *
  * @vm: requested vm
  * @bo: requested buffer object
  *
  * Find @bo inside the requested vm (cayman+).
  * Search inside the @bos vm list for the requested vm
  * Returns the found bo_va or NULL if none is found
  *
  * Object has to be reserved!
  */
 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
 				       struct radeon_bo *bo)
 {
 	struct radeon_bo_va *bo_va;
 	list_for_each_entry(bo_va, &bo->va, bo_list) {
 		if (bo_va->vm == vm) {
 			return bo_va;
 		}
 	}
 	return NULL;
 }
 /**
  * radeon_vm_bo_add - add a bo to a specific vm
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @bo: radeon buffer object
  *
  * Add @bo into the requested vm (cayman+).
  * Add @bo to the list of bos associated with the vm
  * Returns newly added bo_va or NULL for failure
  *
  * Object has to be reserved!
  */
 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
 				      struct radeon_vm *vm,
 				      struct radeon_bo *bo)
 {
 	struct radeon_bo_va *bo_va;
 	bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
 	if (bo_va == NULL) {
 		return NULL;
 	}
 	bo_va->vm = vm;
 	bo_va->bo = bo;
 	bo_va->soffset = 0;
 	bo_va->eoffset = 0;
 	bo_va->flags = 0;
 	bo_va->valid = false;
 	bo_va->ref_count = 1;
 	INIT_LIST_HEAD(&bo_va->bo_list);
 	INIT_LIST_HEAD(&bo_va->vm_list);
 	mutex_lock(&vm->mutex);
 	list_add(&bo_va->vm_list, &vm->va);
 	list_add_tail(&bo_va->bo_list, &bo->va);
 	mutex_unlock(&vm->mutex);
 	return bo_va;
 }
 /**
  * radeon_vm_clear_bo - initially clear the page dir/table
  *
  * @rdev: radeon_device pointer
  * @bo: bo to clear
  */
 static int radeon_vm_clear_bo(struct radeon_device *rdev,
 			      struct radeon_bo *bo)
 {
         struct ttm_validate_buffer tv;
         struct ww_acquire_ctx ticket;
         struct list_head head;
 	struct radeon_ib ib;
 	unsigned entries;
 	uint64_t addr;
 	int r;
         memset(&tv, 0, sizeof(tv));
         tv.bo = &bo->tbo;
         INIT_LIST_HEAD(&head);
         list_add(&tv.head, &head);
         r = ttm_eu_reserve_buffers(&ticket, &head);
         if (r)
 		return r;
         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
         if (r)
                 goto error;
 	addr = radeon_bo_gpu_offset(bo);
 	entries = radeon_bo_size(bo) / 8;
 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib,
 			  NULL, entries * 2 + 64);
 	if (r)
                 goto error;
 	ib.length_dw = 0;
 	radeon_asic_vm_set_page(rdev, &ib, addr, 0, entries, 0, 0);
 	r = radeon_ib_schedule(rdev, &ib, NULL);
 	if (r)
                 goto error;
 	ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 	radeon_ib_free(rdev, &ib);
 	return 0;
 error:
 	ttm_eu_backoff_reservation(&ticket, &head);
 	return r;
 }
 /**
  * radeon_vm_bo_set_addr - set bos virtual address inside a vm
  *
  * @rdev: radeon_device pointer
  * @bo_va: bo_va to store the address
  * @soffset: requested offset of the buffer in the VM address space
  * @flags: attributes of pages (read/write/valid/etc.)
  *
  * Set offset of @bo_va (cayman+).
  * Validate and set the offset requested within the vm address space.
  * Returns 0 for success, error for failure.
  *
  * Object has to be reserved!
  */
 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
 			  struct radeon_bo_va *bo_va,
 			  uint64_t soffset,
 			  uint32_t flags)
 {
 	uint64_t size = radeon_bo_size(bo_va->bo);
 	uint64_t eoffset, last_offset = 0;
 	struct radeon_vm *vm = bo_va->vm;
 	struct radeon_bo_va *tmp;
 	struct list_head *head;
 	unsigned last_pfn, pt_idx;
 	int r;
 	if (soffset) {
 		/* make sure object fit at this offset */
 		eoffset = soffset + size;
 		if (soffset >= eoffset) {
 			return -EINVAL;
 		}
 		last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
 		if (last_pfn > rdev->vm_manager.max_pfn) {
 			dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
 				last_pfn, rdev->vm_manager.max_pfn);
 			return -EINVAL;
 		}
 	} else {
 		eoffset = last_pfn = 0;
 	}
 	mutex_lock(&vm->mutex);
 	head = &vm->va;
 	last_offset = 0;
 	list_for_each_entry(tmp, &vm->va, vm_list) {
 		if (bo_va == tmp) {
 			/* skip over currently modified bo */
 			continue;
 		}
 		if (soffset >= last_offset && eoffset <= tmp->soffset) {
 			/* bo can be added before this one */
 			break;
 		}
 		if (eoffset > tmp->soffset && soffset < tmp->eoffset) {
 			/* bo and tmp overlap, invalid offset */
 			dev_err(rdev->dev, "bo %p va 0x%08X conflict with (bo %p 0x%08X 0x%08X)\n",
 				bo_va->bo, (unsigned)bo_va->soffset, tmp->bo,
 				(unsigned)tmp->soffset, (unsigned)tmp->eoffset);
 			mutex_unlock(&vm->mutex);
 			return -EINVAL;
 		}
 		last_offset = tmp->eoffset;
 		head = &tmp->vm_list;
 	}
 	bo_va->soffset = soffset;
 	bo_va->eoffset = eoffset;
 	bo_va->flags = flags;
 	bo_va->valid = false;
 	list_move(&bo_va->vm_list, head);
 	soffset = (soffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
 	eoffset = (eoffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
 	if (eoffset > vm->max_pde_used)
 		vm->max_pde_used = eoffset;
 	radeon_bo_unreserve(bo_va->bo);
 	/* walk over the address space and allocate the page tables */
 	for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
 		struct radeon_bo *pt;
 		if (vm->page_tables[pt_idx].bo)
 			continue;
 		/* drop mutex to allocate and clear page table */
 		mutex_unlock(&vm->mutex);
 		r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
 				     RADEON_GPU_PAGE_SIZE, false,
 				     RADEON_GEM_DOMAIN_VRAM, NULL, &pt);
 		if (r)
 			return r;
 		r = radeon_vm_clear_bo(rdev, pt);
 		if (r) {
 			radeon_bo_unref(&pt);
 			radeon_bo_reserve(bo_va->bo, false);
 			return r;
 		}
 		/* aquire mutex again */
 		mutex_lock(&vm->mutex);
 		if (vm->page_tables[pt_idx].bo) {
 			/* someone else allocated the pt in the meantime */
 			mutex_unlock(&vm->mutex);
 			radeon_bo_unref(&pt);
 			mutex_lock(&vm->mutex);
 			continue;
 		}
 		vm->page_tables[pt_idx].addr = 0;
 		vm->page_tables[pt_idx].bo = pt;
 	}
 	mutex_unlock(&vm->mutex);
 	return radeon_bo_reserve(bo_va->bo, false);
 }
 /**
  * radeon_vm_map_gart - get the physical address of a gart page
  *
  * @rdev: radeon_device pointer
  * @addr: the unmapped addr
  *
  * Look up the physical address of the page that the pte resolves
  * to (cayman+).
  * Returns the physical address of the page.
  */
 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
 {
 	uint64_t result;
 	/* page table offset */
 	result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
 	/* in case cpu page size != gpu page size*/
 	result |= addr & (~PAGE_MASK);
 	return result;
 }
 /**
  * radeon_vm_page_flags - translate page flags to what the hw uses
  *
  * @flags: flags comming from userspace
  *
  * Translate the flags the userspace ABI uses to hw flags.
  */
 static uint32_t radeon_vm_page_flags(uint32_t flags)
 {
         uint32_t hw_flags = 0;
         hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
         hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
         hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
         if (flags & RADEON_VM_PAGE_SYSTEM) {
                 hw_flags |= R600_PTE_SYSTEM;
                 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
         }
         return hw_flags;
 }
 /**
  * radeon_vm_update_pdes - make sure that page directory is valid
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @start: start of GPU address range
  * @end: end of GPU address range
  *
  * Allocates new page tables if necessary
  * and updates the page directory (cayman+).
  * Returns 0 for success, error for failure.
  *
  * Global and local mutex must be locked!
  */
 int radeon_vm_update_page_directory(struct radeon_device *rdev,
 				    struct radeon_vm *vm)
 {
 	static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
-	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
+	struct radeon_bo *pd = vm->page_directory;
+	uint64_t pd_addr = radeon_bo_gpu_offset(pd);
 	uint64_t last_pde = ~0, last_pt = ~0;
 	unsigned count = 0, pt_idx, ndw;
 	struct radeon_ib ib;
 	int r;
 	/* padding, etc. */
 	ndw = 64;
 	/* assume the worst case */
 	ndw += vm->max_pde_used * 16;
 	/* update too big for an IB */
 	if (ndw > 0xfffff)
 		return -ENOMEM;
 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
 	if (r)
 		return r;
 	ib.length_dw = 0;
 	/* walk over the address space and update the page directory */
 	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
 		struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
 		uint64_t pde, pt;
 		if (bo == NULL)
 			continue;
 		pt = radeon_bo_gpu_offset(bo);
 		if (vm->page_tables[pt_idx].addr == pt)
 			continue;
 		vm->page_tables[pt_idx].addr = pt;
 		pde = pd_addr + pt_idx * 8;
 		if (((last_pde + 8 * count) != pde) ||
 		    ((last_pt + incr * count) != pt)) {
 			if (count) {
 				radeon_asic_vm_set_page(rdev, &ib, last_pde,
 							last_pt, count, incr,
 							R600_PTE_VALID);
 			}
 			count = 1;
 			last_pde = pde;
 			last_pt = pt;
 		} else {
 			++count;
 		}
 	}
 	if (count)
 		radeon_asic_vm_set_page(rdev, &ib, last_pde, last_pt, count,
 					incr, R600_PTE_VALID);
 	if (ib.length_dw != 0) {
+		radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
 		radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
 		r = radeon_ib_schedule(rdev, &ib, NULL);
 		if (r) {
 			radeon_ib_free(rdev, &ib);
 			return r;
 		}
 		radeon_fence_unref(&vm->fence);
 		vm->fence = radeon_fence_ref(ib.fence);
 		radeon_fence_unref(&vm->last_flush);
 	}
 	radeon_ib_free(rdev, &ib);
 	return 0;
 }
 /**
  * radeon_vm_update_ptes - make sure that page tables are valid
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @start: start of GPU address range
  * @end: end of GPU address range
  * @dst: destination address to map to
  * @flags: mapping flags
  *
  * Update the page tables in the range @start - @end (cayman+).
  *
  * Global and local mutex must be locked!
  */
 static void radeon_vm_update_ptes(struct radeon_device *rdev,
 				  struct radeon_vm *vm,
 				  struct radeon_ib *ib,
 				  uint64_t start, uint64_t end,
 				  uint64_t dst, uint32_t flags)
 {
 	static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
 	uint64_t last_pte = ~0, last_dst = ~0;
 	unsigned count = 0;
 	uint64_t addr;
 	start = start / RADEON_GPU_PAGE_SIZE;
 	end = end / RADEON_GPU_PAGE_SIZE;
 	/* walk over the address space and update the page tables */
 	for (addr = start; addr < end; ) {
 		uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
+		struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
 		unsigned nptes;
 		uint64_t pte;
+		radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj);
 		if ((addr & ~mask) == (end & ~mask))
 			nptes = end - addr;
 		else
 			nptes = RADEON_VM_PTE_COUNT - (addr & mask);
-		pte = radeon_bo_gpu_offset(vm->page_tables[pt_idx].bo);
+		pte = radeon_bo_gpu_offset(pt);
 		pte += (addr & mask) * 8;
 		if ((last_pte + 8 * count) != pte) {
 			if (count) {
 				radeon_asic_vm_set_page(rdev, ib, last_pte,
 							last_dst, count,
 							RADEON_GPU_PAGE_SIZE,
 							flags);
 			}
 			count = nptes;
 			last_pte = pte;
 			last_dst = dst;
 		} else {
 			count += nptes;
 		}
 		addr += nptes;
 		dst += nptes * RADEON_GPU_PAGE_SIZE;
 	}
 	if (count) {
 		radeon_asic_vm_set_page(rdev, ib, last_pte,
 					last_dst, count,
 					RADEON_GPU_PAGE_SIZE, flags);
 	}
 }
 /**
  * radeon_vm_bo_update - map a bo into the vm page table
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @bo: radeon buffer object
  * @mem: ttm mem
  *
  * Fill in the page table entries for @bo (cayman+).
  * Returns 0 for success, -EINVAL for failure.
  *
  * Object have to be reserved and mutex must be locked!
  */
 int radeon_vm_bo_update(struct radeon_device *rdev,
 			struct radeon_vm *vm,
 			struct radeon_bo *bo,
 			struct ttm_mem_reg *mem)
 {
 	struct radeon_ib ib;
 	struct radeon_bo_va *bo_va;
 	unsigned nptes, ndw;
 	uint64_t addr;
 	int r;
 	bo_va = radeon_vm_bo_find(vm, bo);
 	if (bo_va == NULL) {
 		dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
 		return -EINVAL;
 	}
 	if (!bo_va->soffset) {
 		dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
 			bo, vm);
 		return -EINVAL;
 	}
 	if ((bo_va->valid && mem) || (!bo_va->valid && mem == NULL))
 		return 0;
 	bo_va->flags &= ~RADEON_VM_PAGE_VALID;
 	bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
 	if (mem) {
 		addr = mem->start << PAGE_SHIFT;
 		if (mem->mem_type != TTM_PL_SYSTEM) {
 			bo_va->flags |= RADEON_VM_PAGE_VALID;
 			bo_va->valid = true;
 		}
 		if (mem->mem_type == TTM_PL_TT) {
 			bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
 		} else {
 			addr += rdev->vm_manager.vram_base_offset;
 		}
 	} else {
 		addr = 0;
 		bo_va->valid = false;
 	}
 	trace_radeon_vm_bo_update(bo_va);
 	nptes = radeon_bo_ngpu_pages(bo);
 	/* padding, etc. */
 	ndw = 64;
 	if (RADEON_VM_BLOCK_SIZE > 11)
 		/* reserve space for one header for every 2k dwords */
 		ndw += (nptes >> 11) * 4;
 	else
 		/* reserve space for one header for
 		    every (1 << BLOCK_SIZE) entries */
 		ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4;
 	/* reserve space for pte addresses */
 	ndw += nptes * 2;
 	/* update too big for an IB */
 	if (ndw > 0xfffff)
 		return -ENOMEM;
 	r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
 	if (r)
 		return r;
 	ib.length_dw = 0;
 	radeon_vm_update_ptes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset,
 			      addr, radeon_vm_page_flags(bo_va->flags));
 	radeon_semaphore_sync_to(ib.semaphore, vm->fence);
 	r = radeon_ib_schedule(rdev, &ib, NULL);
 	if (r) {
 		radeon_ib_free(rdev, &ib);
 		return r;
 	}
 	radeon_fence_unref(&vm->fence);
 	vm->fence = radeon_fence_ref(ib.fence);
 	radeon_ib_free(rdev, &ib);
 	radeon_fence_unref(&vm->last_flush);
 	return 0;
 }
 /**
  * radeon_vm_bo_rmv - remove a bo to a specific vm
  *
  * @rdev: radeon_device pointer
  * @bo_va: requested bo_va
  *
  * Remove @bo_va->bo from the requested vm (cayman+).
  * Remove @bo_va->bo from the list of bos associated with the bo_va->vm and
  * remove the ptes for @bo_va in the page table.
  * Returns 0 for success.
  *
  * Object have to be reserved!
  */
 int radeon_vm_bo_rmv(struct radeon_device *rdev,
 		     struct radeon_bo_va *bo_va)
 {
 	int r = 0;
 	mutex_lock(&bo_va->vm->mutex);
 	if (bo_va->soffset)
 		r = radeon_vm_bo_update(rdev, bo_va->vm, bo_va->bo, NULL);
 	list_del(&bo_va->vm_list);
 	mutex_unlock(&bo_va->vm->mutex);
 	list_del(&bo_va->bo_list);
 	kfree(bo_va);
 	return r;
 }
 /**
  * radeon_vm_bo_invalidate - mark the bo as invalid
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  * @bo: radeon buffer object
  *
  * Mark @bo as invalid (cayman+).
  */
 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
 			     struct radeon_bo *bo)
 {
 	struct radeon_bo_va *bo_va;
 	list_for_each_entry(bo_va, &bo->va, bo_list) {
 		bo_va->valid = false;
 	}
 }
 /**
  * radeon_vm_init - initialize a vm instance
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  *
  * Init @vm fields (cayman+).
  */
 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
 {
 	unsigned pd_size, pd_entries, pts_size;
 	int r;
 	vm->id = 0;
 	vm->fence = NULL;
 	vm->last_flush = NULL;
 	vm->last_id_use = NULL;
 	mutex_init(&vm->mutex);
 	INIT_LIST_HEAD(&vm->va);
 	pd_size = radeon_vm_directory_size(rdev);
 	pd_entries = radeon_vm_num_pdes(rdev);
 	/* allocate page table array */
 	pts_size = pd_entries * sizeof(struct radeon_vm_pt);
 	vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
 	if (vm->page_tables == NULL) {
 		DRM_ERROR("Cannot allocate memory for page table array\n");
 		return -ENOMEM;
 	}
 	r = radeon_bo_create(rdev, pd_size, RADEON_VM_PTB_ALIGN_SIZE, false,
 			     RADEON_GEM_DOMAIN_VRAM, NULL,
 			     &vm->page_directory);
 	if (r)
 		return r;
 	r = radeon_vm_clear_bo(rdev, vm->page_directory);
 	if (r) {
 		radeon_bo_unref(&vm->page_directory);
 		vm->page_directory = NULL;
 		return r;
 	}
 	return 0;
 }
 /**
  * radeon_vm_fini - tear down a vm instance
  *
  * @rdev: radeon_device pointer
  * @vm: requested vm
  *
  * Tear down @vm (cayman+).
  * Unbind the VM and remove all bos from the vm bo list
  */
 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
 {
 	struct radeon_bo_va *bo_va, *tmp;
 	int i, r;
 	if (!list_empty(&vm->va)) {
 		dev_err(rdev->dev, "still active bo inside vm\n");
 	}
 	list_for_each_entry_safe(bo_va, tmp, &vm->va, vm_list) {
 		list_del_init(&bo_va->vm_list);
 		r = radeon_bo_reserve(bo_va->bo, false);
 		if (!r) {
 			list_del_init(&bo_va->bo_list);
 			radeon_bo_unreserve(bo_va->bo);
 			kfree(bo_va);
 		}
 	}
 	for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
 		radeon_bo_unref(&vm->page_tables[i].bo);
 	kfree(vm->page_tables);
 	radeon_bo_unref(&vm->page_directory);
 	radeon_fence_unref(&vm->fence);
 	radeon_fence_unref(&vm->last_flush);
 	radeon_fence_unref(&vm->last_id_use);
 	mutex_destroy(&vm->mutex);
 }