Commit 6ba736dd02e7b3658c344efeb2f4a096a6785d83
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ALSA: hda - Suppress CORBRP clear on Nvidia controller chips
The recent commit (ca460f86521) changed the CORB RP reset procedure to follow the specification with a couple of sanity checks. Unfortunately, Nvidia controller chips seem not following this way, and spew the warning messages like: snd_hda_intel 0000:00:10.1: CORB reset timeout#1, CORBRP = 0 This patch adds the workaround for such chips. It just skips the new reset procedure for the known broken chips. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Showing 3 changed files with 21 additions and 17 deletions Side-by-side Diff
sound/pci/hda/hda_controller.c
| ... | ... | @@ -1059,24 +1059,26 @@ |
| 1059 | 1059 | |
| 1060 | 1060 | /* reset the corb hw read pointer */ |
| 1061 | 1061 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); |
| 1062 | - for (timeout = 1000; timeout > 0; timeout--) { | |
| 1063 | - if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST) | |
| 1064 | - break; | |
| 1065 | - udelay(1); | |
| 1066 | - } | |
| 1067 | - if (timeout <= 0) | |
| 1068 | - dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n", | |
| 1069 | - azx_readw(chip, CORBRP)); | |
| 1062 | + if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) { | |
| 1063 | + for (timeout = 1000; timeout > 0; timeout--) { | |
| 1064 | + if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST) | |
| 1065 | + break; | |
| 1066 | + udelay(1); | |
| 1067 | + } | |
| 1068 | + if (timeout <= 0) | |
| 1069 | + dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n", | |
| 1070 | + azx_readw(chip, CORBRP)); | |
| 1070 | 1071 | |
| 1071 | - azx_writew(chip, CORBRP, 0); | |
| 1072 | - for (timeout = 1000; timeout > 0; timeout--) { | |
| 1073 | - if (azx_readw(chip, CORBRP) == 0) | |
| 1074 | - break; | |
| 1075 | - udelay(1); | |
| 1072 | + azx_writew(chip, CORBRP, 0); | |
| 1073 | + for (timeout = 1000; timeout > 0; timeout--) { | |
| 1074 | + if (azx_readw(chip, CORBRP) == 0) | |
| 1075 | + break; | |
| 1076 | + udelay(1); | |
| 1077 | + } | |
| 1078 | + if (timeout <= 0) | |
| 1079 | + dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n", | |
| 1080 | + azx_readw(chip, CORBRP)); | |
| 1076 | 1081 | } |
| 1077 | - if (timeout <= 0) | |
| 1078 | - dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n", | |
| 1079 | - azx_readw(chip, CORBRP)); | |
| 1080 | 1082 | |
| 1081 | 1083 | /* enable corb dma */ |
| 1082 | 1084 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); |
sound/pci/hda/hda_intel.c
| ... | ... | @@ -249,7 +249,8 @@ |
| 249 | 249 | /* quirks for Nvidia */ |
| 250 | 250 | #define AZX_DCAPS_PRESET_NVIDIA \ |
| 251 | 251 | (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ |
| 252 | - AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT) | |
| 252 | + AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\ | |
| 253 | + AZX_DCAPS_CORBRP_SELF_CLEAR) | |
| 253 | 254 | |
| 254 | 255 | #define AZX_DCAPS_PRESET_CTHDA \ |
| 255 | 256 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) |
sound/pci/hda/hda_priv.h
| ... | ... | @@ -189,6 +189,7 @@ |
| 189 | 189 | #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ |
| 190 | 190 | #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ |
| 191 | 191 | #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */ |
| 192 | +#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */ | |
| 192 | 193 | |
| 193 | 194 | /* position fix mode */ |
| 194 | 195 | enum { |