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Commit 7f3dd4a8e31cdaed5f80f24b798cedcab644830b

Authored by Paul Handrigan
Committed by Mark Brown
1 parent 41df0829ce
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

ASoC: cs42l73: Change VSPIN/VSPOUT to VSPINOUT 

Since VSP only has one power bit, only provide one DAPM widget.

Signed-off-by: Paul Handrigan <Paul.Handrigan@cirrus.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Showing 1 changed file with 13 additions and 19 deletions Inline Diff

sound/soc/codecs/cs42l73.c
Diff comments   View file @ 7f3dd4a
1 /* 1 /*
2 * cs42l73.c -- CS42L73 ALSA Soc Audio driver 2 * cs42l73.c -- CS42L73 ALSA Soc Audio driver
3 * 3 *
4 * Copyright 2011 Cirrus Logic, Inc. 4 * Copyright 2011 Cirrus Logic, Inc.
5 * 5 *
6 * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com> 6 * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>
7 * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com> 7 * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 */ 13 */
14 14
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/moduleparam.h> 16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h> 17 #include <linux/kernel.h>
18 #include <linux/init.h> 18 #include <linux/init.h>
19 #include <linux/delay.h> 19 #include <linux/delay.h>
20 #include <linux/pm.h> 20 #include <linux/pm.h>
21 #include <linux/i2c.h> 21 #include <linux/i2c.h>
22 #include <linux/regmap.h> 22 #include <linux/regmap.h>
23 #include <linux/slab.h> 23 #include <linux/slab.h>
24 #include <sound/core.h> 24 #include <sound/core.h>
25 #include <sound/pcm.h> 25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h> 26 #include <sound/pcm_params.h>
27 #include <sound/soc.h> 27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h> 28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h> 29 #include <sound/initval.h>
30 #include <sound/tlv.h> 30 #include <sound/tlv.h>
31 #include "cs42l73.h" 31 #include "cs42l73.h"
32 32
33 struct sp_config { 33 struct sp_config {
34 u8 spc, mmcc, spfs; 34 u8 spc, mmcc, spfs;
35 u32 srate; 35 u32 srate;
36 }; 36 };
37 struct cs42l73_private { 37 struct cs42l73_private {
38 struct sp_config config[3]; 38 struct sp_config config[3];
39 struct regmap *regmap; 39 struct regmap *regmap;
40 u32 sysclk; 40 u32 sysclk;
41 u8 mclksel; 41 u8 mclksel;
42 u32 mclk; 42 u32 mclk;
43 int shutdwn_delay; 43 int shutdwn_delay;
44 }; 44 };
45 45
46 static const struct reg_default cs42l73_reg_defaults[] = { 46 static const struct reg_default cs42l73_reg_defaults[] = {
47 { 6, 0xF1 }, /* r06 - Power Ctl 1 */ 47 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
48 { 7, 0xDF }, /* r07 - Power Ctl 2 */ 48 { 7, 0xDF }, /* r07 - Power Ctl 2 */
49 { 8, 0x3F }, /* r08 - Power Ctl 3 */ 49 { 8, 0x3F }, /* r08 - Power Ctl 3 */
50 { 9, 0x50 }, /* r09 - Charge Pump Freq */ 50 { 9, 0x50 }, /* r09 - Charge Pump Freq */
51 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */ 51 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
52 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */ 52 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
53 { 12, 0x00 }, /* r0C - Aux PCM Ctl */ 53 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
54 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */ 54 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
55 { 14, 0x00 }, /* r0E - Audio PCM Ctl */ 55 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
56 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */ 56 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
57 { 16, 0x00 }, /* r10 - Voice PCM Ctl */ 57 { 16, 0x00 }, /* r10 - Voice PCM Ctl */
58 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */ 58 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
59 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */ 59 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
60 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */ 60 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
61 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */ 61 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
62 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */ 62 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
63 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */ 63 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
64 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */ 64 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
65 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */ 65 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
66 { 25, 0x00 }, /* r19 - Playback Digital Ctl */ 66 { 25, 0x00 }, /* r19 - Playback Digital Ctl */
67 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */ 67 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
68 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */ 68 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
69 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */ 69 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
70 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */ 70 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
71 { 30, 0x00 }, /* r1E - HP Left Analog Volume */ 71 { 30, 0x00 }, /* r1E - HP Left Analog Volume */
72 { 31, 0x00 }, /* r1F - HP Right Analog Volume */ 72 { 31, 0x00 }, /* r1F - HP Right Analog Volume */
73 { 32, 0x00 }, /* r20 - LO Left Analog Volume */ 73 { 32, 0x00 }, /* r20 - LO Left Analog Volume */
74 { 33, 0x00 }, /* r21 - LO Right Analog Volume */ 74 { 33, 0x00 }, /* r21 - LO Right Analog Volume */
75 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */ 75 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
76 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */ 76 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
77 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */ 77 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
78 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */ 78 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
79 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */ 79 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
80 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */ 80 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
81 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */ 81 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
82 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */ 82 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
83 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */ 83 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
84 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */ 84 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
85 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */ 85 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
86 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */ 86 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
87 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */ 87 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
88 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */ 88 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
89 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */ 89 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
90 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */ 90 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
91 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */ 91 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
92 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */ 92 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
93 { 52, 0x18 }, /* r34 - Mixer Ctl */ 93 { 52, 0x18 }, /* r34 - Mixer Ctl */
94 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */ 94 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
95 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */ 95 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
96 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */ 96 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
97 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */ 97 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
98 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */ 98 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
99 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */ 99 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
100 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */ 100 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
101 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */ 101 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
102 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */ 102 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
103 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */ 103 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
104 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */ 104 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
105 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */ 105 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
106 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */ 106 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
107 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */ 107 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
108 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */ 108 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
109 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */ 109 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
110 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */ 110 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
111 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */ 111 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
112 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */ 112 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
113 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */ 113 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
114 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */ 114 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
115 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */ 115 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
116 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */ 116 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
117 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */ 117 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
118 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */ 118 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
119 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */ 119 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
120 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */ 120 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
121 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */ 121 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
122 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */ 122 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
123 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */ 123 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
124 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */ 124 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
125 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */ 125 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
126 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */ 126 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
127 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */ 127 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
128 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */ 128 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
129 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */ 129 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
130 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */ 130 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
131 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */ 131 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
132 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */ 132 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
133 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */ 133 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
134 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */ 134 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
135 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */ 135 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
136 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */ 136 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
137 }; 137 };
138 138
139 static bool cs42l73_volatile_register(struct device *dev, unsigned int reg) 139 static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
140 { 140 {
141 switch (reg) { 141 switch (reg) {
142 case CS42L73_IS1: 142 case CS42L73_IS1:
143 case CS42L73_IS2: 143 case CS42L73_IS2:
144 return true; 144 return true;
145 default: 145 default:
146 return false; 146 return false;
147 } 147 }
148 } 148 }
149 149
150 static bool cs42l73_readable_register(struct device *dev, unsigned int reg) 150 static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
151 { 151 {
152 switch (reg) { 152 switch (reg) {
153 case CS42L73_DEVID_AB: 153 case CS42L73_DEVID_AB:
154 case CS42L73_DEVID_CD: 154 case CS42L73_DEVID_CD:
155 case CS42L73_DEVID_E: 155 case CS42L73_DEVID_E:
156 case CS42L73_REVID: 156 case CS42L73_REVID:
157 case CS42L73_PWRCTL1: 157 case CS42L73_PWRCTL1:
158 case CS42L73_PWRCTL2: 158 case CS42L73_PWRCTL2:
159 case CS42L73_PWRCTL3: 159 case CS42L73_PWRCTL3:
160 case CS42L73_CPFCHC: 160 case CS42L73_CPFCHC:
161 case CS42L73_OLMBMSDC: 161 case CS42L73_OLMBMSDC:
162 case CS42L73_DMMCC: 162 case CS42L73_DMMCC:
163 case CS42L73_XSPC: 163 case CS42L73_XSPC:
164 case CS42L73_XSPMMCC: 164 case CS42L73_XSPMMCC:
165 case CS42L73_ASPC: 165 case CS42L73_ASPC:
166 case CS42L73_ASPMMCC: 166 case CS42L73_ASPMMCC:
167 case CS42L73_VSPC: 167 case CS42L73_VSPC:
168 case CS42L73_VSPMMCC: 168 case CS42L73_VSPMMCC:
169 case CS42L73_VXSPFS: 169 case CS42L73_VXSPFS:
170 case CS42L73_MIOPC: 170 case CS42L73_MIOPC:
171 case CS42L73_ADCIPC: 171 case CS42L73_ADCIPC:
172 case CS42L73_MICAPREPGAAVOL: 172 case CS42L73_MICAPREPGAAVOL:
173 case CS42L73_MICBPREPGABVOL: 173 case CS42L73_MICBPREPGABVOL:
174 case CS42L73_IPADVOL: 174 case CS42L73_IPADVOL:
175 case CS42L73_IPBDVOL: 175 case CS42L73_IPBDVOL:
176 case CS42L73_PBDC: 176 case CS42L73_PBDC:
177 case CS42L73_HLADVOL: 177 case CS42L73_HLADVOL:
178 case CS42L73_HLBDVOL: 178 case CS42L73_HLBDVOL:
179 case CS42L73_SPKDVOL: 179 case CS42L73_SPKDVOL:
180 case CS42L73_ESLDVOL: 180 case CS42L73_ESLDVOL:
181 case CS42L73_HPAAVOL: 181 case CS42L73_HPAAVOL:
182 case CS42L73_HPBAVOL: 182 case CS42L73_HPBAVOL:
183 case CS42L73_LOAAVOL: 183 case CS42L73_LOAAVOL:
184 case CS42L73_LOBAVOL: 184 case CS42L73_LOBAVOL:
185 case CS42L73_STRINV: 185 case CS42L73_STRINV:
186 case CS42L73_XSPINV: 186 case CS42L73_XSPINV:
187 case CS42L73_ASPINV: 187 case CS42L73_ASPINV:
188 case CS42L73_VSPINV: 188 case CS42L73_VSPINV:
189 case CS42L73_LIMARATEHL: 189 case CS42L73_LIMARATEHL:
190 case CS42L73_LIMRRATEHL: 190 case CS42L73_LIMRRATEHL:
191 case CS42L73_LMAXHL: 191 case CS42L73_LMAXHL:
192 case CS42L73_LIMARATESPK: 192 case CS42L73_LIMARATESPK:
193 case CS42L73_LIMRRATESPK: 193 case CS42L73_LIMRRATESPK:
194 case CS42L73_LMAXSPK: 194 case CS42L73_LMAXSPK:
195 case CS42L73_LIMARATEESL: 195 case CS42L73_LIMARATEESL:
196 case CS42L73_LIMRRATEESL: 196 case CS42L73_LIMRRATEESL:
197 case CS42L73_LMAXESL: 197 case CS42L73_LMAXESL:
198 case CS42L73_ALCARATE: 198 case CS42L73_ALCARATE:
199 case CS42L73_ALCRRATE: 199 case CS42L73_ALCRRATE:
200 case CS42L73_ALCMINMAX: 200 case CS42L73_ALCMINMAX:
201 case CS42L73_NGCAB: 201 case CS42L73_NGCAB:
202 case CS42L73_ALCNGMC: 202 case CS42L73_ALCNGMC:
203 case CS42L73_MIXERCTL: 203 case CS42L73_MIXERCTL:
204 case CS42L73_HLAIPAA: 204 case CS42L73_HLAIPAA:
205 case CS42L73_HLBIPBA: 205 case CS42L73_HLBIPBA:
206 case CS42L73_HLAXSPAA: 206 case CS42L73_HLAXSPAA:
207 case CS42L73_HLBXSPBA: 207 case CS42L73_HLBXSPBA:
208 case CS42L73_HLAASPAA: 208 case CS42L73_HLAASPAA:
209 case CS42L73_HLBASPBA: 209 case CS42L73_HLBASPBA:
210 case CS42L73_HLAVSPMA: 210 case CS42L73_HLAVSPMA:
211 case CS42L73_HLBVSPMA: 211 case CS42L73_HLBVSPMA:
212 case CS42L73_XSPAIPAA: 212 case CS42L73_XSPAIPAA:
213 case CS42L73_XSPBIPBA: 213 case CS42L73_XSPBIPBA:
214 case CS42L73_XSPAXSPAA: 214 case CS42L73_XSPAXSPAA:
215 case CS42L73_XSPBXSPBA: 215 case CS42L73_XSPBXSPBA:
216 case CS42L73_XSPAASPAA: 216 case CS42L73_XSPAASPAA:
217 case CS42L73_XSPAASPBA: 217 case CS42L73_XSPAASPBA:
218 case CS42L73_XSPAVSPMA: 218 case CS42L73_XSPAVSPMA:
219 case CS42L73_XSPBVSPMA: 219 case CS42L73_XSPBVSPMA:
220 case CS42L73_ASPAIPAA: 220 case CS42L73_ASPAIPAA:
221 case CS42L73_ASPBIPBA: 221 case CS42L73_ASPBIPBA:
222 case CS42L73_ASPAXSPAA: 222 case CS42L73_ASPAXSPAA:
223 case CS42L73_ASPBXSPBA: 223 case CS42L73_ASPBXSPBA:
224 case CS42L73_ASPAASPAA: 224 case CS42L73_ASPAASPAA:
225 case CS42L73_ASPBASPBA: 225 case CS42L73_ASPBASPBA:
226 case CS42L73_ASPAVSPMA: 226 case CS42L73_ASPAVSPMA:
227 case CS42L73_ASPBVSPMA: 227 case CS42L73_ASPBVSPMA:
228 case CS42L73_VSPAIPAA: 228 case CS42L73_VSPAIPAA:
229 case CS42L73_VSPBIPBA: 229 case CS42L73_VSPBIPBA:
230 case CS42L73_VSPAXSPAA: 230 case CS42L73_VSPAXSPAA:
231 case CS42L73_VSPBXSPBA: 231 case CS42L73_VSPBXSPBA:
232 case CS42L73_VSPAASPAA: 232 case CS42L73_VSPAASPAA:
233 case CS42L73_VSPBASPBA: 233 case CS42L73_VSPBASPBA:
234 case CS42L73_VSPAVSPMA: 234 case CS42L73_VSPAVSPMA:
235 case CS42L73_VSPBVSPMA: 235 case CS42L73_VSPBVSPMA:
236 case CS42L73_MMIXCTL: 236 case CS42L73_MMIXCTL:
237 case CS42L73_SPKMIPMA: 237 case CS42L73_SPKMIPMA:
238 case CS42L73_SPKMXSPA: 238 case CS42L73_SPKMXSPA:
239 case CS42L73_SPKMASPA: 239 case CS42L73_SPKMASPA:
240 case CS42L73_SPKMVSPMA: 240 case CS42L73_SPKMVSPMA:
241 case CS42L73_ESLMIPMA: 241 case CS42L73_ESLMIPMA:
242 case CS42L73_ESLMXSPA: 242 case CS42L73_ESLMXSPA:
243 case CS42L73_ESLMASPA: 243 case CS42L73_ESLMASPA:
244 case CS42L73_ESLMVSPMA: 244 case CS42L73_ESLMVSPMA:
245 case CS42L73_IM1: 245 case CS42L73_IM1:
246 case CS42L73_IM2: 246 case CS42L73_IM2:
247 return true; 247 return true;
248 default: 248 default:
249 return false; 249 return false;
250 } 250 }
251 } 251 }
252 252
253 static const unsigned int hpaloa_tlv[] = { 253 static const unsigned int hpaloa_tlv[] = {
254 TLV_DB_RANGE_HEAD(2), 254 TLV_DB_RANGE_HEAD(2),
255 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0), 255 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
256 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0), 256 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0),
257 }; 257 };
258 258
259 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0); 259 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
260 260
261 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0); 261 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
262 262
263 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0); 263 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
264 264
265 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0); 265 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
266 266
267 static const unsigned int limiter_tlv[] = { 267 static const unsigned int limiter_tlv[] = {
268 TLV_DB_RANGE_HEAD(2), 268 TLV_DB_RANGE_HEAD(2),
269 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0), 269 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
270 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0), 270 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
271 }; 271 };
272 272
273 static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1); 273 static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
274 274
275 static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" }; 275 static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
276 static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" }; 276 static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
277 277
278 static const struct soc_enum pgaa_enum = 278 static const struct soc_enum pgaa_enum =
279 SOC_ENUM_SINGLE(CS42L73_ADCIPC, 3, 279 SOC_ENUM_SINGLE(CS42L73_ADCIPC, 3,
280 ARRAY_SIZE(cs42l73_pgaa_text), cs42l73_pgaa_text); 280 ARRAY_SIZE(cs42l73_pgaa_text), cs42l73_pgaa_text);
281 281
282 static const struct soc_enum pgab_enum = 282 static const struct soc_enum pgab_enum =
283 SOC_ENUM_SINGLE(CS42L73_ADCIPC, 7, 283 SOC_ENUM_SINGLE(CS42L73_ADCIPC, 7,
284 ARRAY_SIZE(cs42l73_pgab_text), cs42l73_pgab_text); 284 ARRAY_SIZE(cs42l73_pgab_text), cs42l73_pgab_text);
285 285
286 static const struct snd_kcontrol_new pgaa_mux = 286 static const struct snd_kcontrol_new pgaa_mux =
287 SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum); 287 SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
288 288
289 static const struct snd_kcontrol_new pgab_mux = 289 static const struct snd_kcontrol_new pgab_mux =
290 SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum); 290 SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
291 291
292 static const struct snd_kcontrol_new input_left_mixer[] = { 292 static const struct snd_kcontrol_new input_left_mixer[] = {
293 SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1, 293 SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
294 5, 1, 1), 294 5, 1, 1),
295 SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1, 295 SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
296 4, 1, 1), 296 4, 1, 1),
297 }; 297 };
298 298
299 static const struct snd_kcontrol_new input_right_mixer[] = { 299 static const struct snd_kcontrol_new input_right_mixer[] = {
300 SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1, 300 SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
301 7, 1, 1), 301 7, 1, 1),
302 SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1, 302 SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
303 6, 1, 1), 303 6, 1, 1),
304 }; 304 };
305 305
306 static const char * const cs42l73_ng_delay_text[] = { 306 static const char * const cs42l73_ng_delay_text[] = {
307 "50ms", "100ms", "150ms", "200ms" }; 307 "50ms", "100ms", "150ms", "200ms" };
308 308
309 static const struct soc_enum ng_delay_enum = 309 static const struct soc_enum ng_delay_enum =
310 SOC_ENUM_SINGLE(CS42L73_NGCAB, 0, 310 SOC_ENUM_SINGLE(CS42L73_NGCAB, 0,
311 ARRAY_SIZE(cs42l73_ng_delay_text), cs42l73_ng_delay_text); 311 ARRAY_SIZE(cs42l73_ng_delay_text), cs42l73_ng_delay_text);
312 312
313 static const char * const charge_pump_freq_text[] = { 313 static const char * const charge_pump_freq_text[] = {
314 "0", "1", "2", "3", "4", 314 "0", "1", "2", "3", "4",
315 "5", "6", "7", "8", "9", 315 "5", "6", "7", "8", "9",
316 "10", "11", "12", "13", "14", "15" }; 316 "10", "11", "12", "13", "14", "15" };
317 317
318 static const struct soc_enum charge_pump_enum = 318 static const struct soc_enum charge_pump_enum =
319 SOC_ENUM_SINGLE(CS42L73_CPFCHC, 4, 319 SOC_ENUM_SINGLE(CS42L73_CPFCHC, 4,
320 ARRAY_SIZE(charge_pump_freq_text), charge_pump_freq_text); 320 ARRAY_SIZE(charge_pump_freq_text), charge_pump_freq_text);
321 321
322 static const char * const cs42l73_mono_mix_texts[] = { 322 static const char * const cs42l73_mono_mix_texts[] = {
323 "Left", "Right", "Mono Mix"}; 323 "Left", "Right", "Mono Mix"};
324 324
325 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 }; 325 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
326 326
327 static const struct soc_enum spk_asp_enum = 327 static const struct soc_enum spk_asp_enum =
328 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 1, 328 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 1,
329 ARRAY_SIZE(cs42l73_mono_mix_texts), 329 ARRAY_SIZE(cs42l73_mono_mix_texts),
330 cs42l73_mono_mix_texts, 330 cs42l73_mono_mix_texts,
331 cs42l73_mono_mix_values); 331 cs42l73_mono_mix_values);
332 332
333 static const struct snd_kcontrol_new spk_asp_mixer = 333 static const struct snd_kcontrol_new spk_asp_mixer =
334 SOC_DAPM_ENUM("Route", spk_asp_enum); 334 SOC_DAPM_ENUM("Route", spk_asp_enum);
335 335
336 static const struct soc_enum spk_xsp_enum = 336 static const struct soc_enum spk_xsp_enum =
337 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3, 337 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
338 ARRAY_SIZE(cs42l73_mono_mix_texts), 338 ARRAY_SIZE(cs42l73_mono_mix_texts),
339 cs42l73_mono_mix_texts, 339 cs42l73_mono_mix_texts,
340 cs42l73_mono_mix_values); 340 cs42l73_mono_mix_values);
341 341
342 static const struct snd_kcontrol_new spk_xsp_mixer = 342 static const struct snd_kcontrol_new spk_xsp_mixer =
343 SOC_DAPM_ENUM("Route", spk_xsp_enum); 343 SOC_DAPM_ENUM("Route", spk_xsp_enum);
344 344
345 static const struct soc_enum esl_asp_enum = 345 static const struct soc_enum esl_asp_enum =
346 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 5, 346 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 5,
347 ARRAY_SIZE(cs42l73_mono_mix_texts), 347 ARRAY_SIZE(cs42l73_mono_mix_texts),
348 cs42l73_mono_mix_texts, 348 cs42l73_mono_mix_texts,
349 cs42l73_mono_mix_values); 349 cs42l73_mono_mix_values);
350 350
351 static const struct snd_kcontrol_new esl_asp_mixer = 351 static const struct snd_kcontrol_new esl_asp_mixer =
352 SOC_DAPM_ENUM("Route", esl_asp_enum); 352 SOC_DAPM_ENUM("Route", esl_asp_enum);
353 353
354 static const struct soc_enum esl_xsp_enum = 354 static const struct soc_enum esl_xsp_enum =
355 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 7, 355 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 7,
356 ARRAY_SIZE(cs42l73_mono_mix_texts), 356 ARRAY_SIZE(cs42l73_mono_mix_texts),
357 cs42l73_mono_mix_texts, 357 cs42l73_mono_mix_texts,
358 cs42l73_mono_mix_values); 358 cs42l73_mono_mix_values);
359 359
360 static const struct snd_kcontrol_new esl_xsp_mixer = 360 static const struct snd_kcontrol_new esl_xsp_mixer =
361 SOC_DAPM_ENUM("Route", esl_xsp_enum); 361 SOC_DAPM_ENUM("Route", esl_xsp_enum);
362 362
363 static const char * const cs42l73_ip_swap_text[] = { 363 static const char * const cs42l73_ip_swap_text[] = {
364 "Stereo", "Mono A", "Mono B", "Swap A-B"}; 364 "Stereo", "Mono A", "Mono B", "Swap A-B"};
365 365
366 static const struct soc_enum ip_swap_enum = 366 static const struct soc_enum ip_swap_enum =
367 SOC_ENUM_SINGLE(CS42L73_MIOPC, 6, 367 SOC_ENUM_SINGLE(CS42L73_MIOPC, 6,
368 ARRAY_SIZE(cs42l73_ip_swap_text), cs42l73_ip_swap_text); 368 ARRAY_SIZE(cs42l73_ip_swap_text), cs42l73_ip_swap_text);
369 369
370 static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"}; 370 static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
371 371
372 static const struct soc_enum vsp_output_mux_enum = 372 static const struct soc_enum vsp_output_mux_enum =
373 SOC_ENUM_SINGLE(CS42L73_MIXERCTL, 5, 373 SOC_ENUM_SINGLE(CS42L73_MIXERCTL, 5,
374 ARRAY_SIZE(cs42l73_spo_mixer_text), cs42l73_spo_mixer_text); 374 ARRAY_SIZE(cs42l73_spo_mixer_text), cs42l73_spo_mixer_text);
375 375
376 static const struct soc_enum xsp_output_mux_enum = 376 static const struct soc_enum xsp_output_mux_enum =
377 SOC_ENUM_SINGLE(CS42L73_MIXERCTL, 4, 377 SOC_ENUM_SINGLE(CS42L73_MIXERCTL, 4,
378 ARRAY_SIZE(cs42l73_spo_mixer_text), cs42l73_spo_mixer_text); 378 ARRAY_SIZE(cs42l73_spo_mixer_text), cs42l73_spo_mixer_text);
379 379
380 static const struct snd_kcontrol_new vsp_output_mux = 380 static const struct snd_kcontrol_new vsp_output_mux =
381 SOC_DAPM_ENUM("Route", vsp_output_mux_enum); 381 SOC_DAPM_ENUM("Route", vsp_output_mux_enum);
382 382
383 static const struct snd_kcontrol_new xsp_output_mux = 383 static const struct snd_kcontrol_new xsp_output_mux =
384 SOC_DAPM_ENUM("Route", xsp_output_mux_enum); 384 SOC_DAPM_ENUM("Route", xsp_output_mux_enum);
385 385
386 static const struct snd_kcontrol_new hp_amp_ctl = 386 static const struct snd_kcontrol_new hp_amp_ctl =
387 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1); 387 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
388 388
389 static const struct snd_kcontrol_new lo_amp_ctl = 389 static const struct snd_kcontrol_new lo_amp_ctl =
390 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1); 390 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
391 391
392 static const struct snd_kcontrol_new spk_amp_ctl = 392 static const struct snd_kcontrol_new spk_amp_ctl =
393 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1); 393 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
394 394
395 static const struct snd_kcontrol_new spklo_amp_ctl = 395 static const struct snd_kcontrol_new spklo_amp_ctl =
396 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1); 396 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
397 397
398 static const struct snd_kcontrol_new ear_amp_ctl = 398 static const struct snd_kcontrol_new ear_amp_ctl =
399 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1); 399 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
400 400
401 static const struct snd_kcontrol_new cs42l73_snd_controls[] = { 401 static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
402 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume", 402 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
403 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0, 403 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
404 0x41, 0x4B, hpaloa_tlv), 404 0x41, 0x4B, hpaloa_tlv),
405 405
406 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL, 406 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
407 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv), 407 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
408 408
409 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL, 409 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
410 CS42L73_MICBPREPGABVOL, 5, 0x34, 410 CS42L73_MICBPREPGABVOL, 5, 0x34,
411 0x24, micpga_tlv), 411 0x24, micpga_tlv),
412 412
413 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL, 413 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
414 CS42L73_MICBPREPGABVOL, 6, 1, 1), 414 CS42L73_MICBPREPGABVOL, 6, 1, 1),
415 415
416 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL, 416 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
417 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv), 417 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
418 418
419 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume", 419 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
420 CS42L73_HLADVOL, CS42L73_HLBDVOL, 420 CS42L73_HLADVOL, CS42L73_HLBDVOL,
421 0, 0x34, 0xE4, hl_tlv), 421 0, 0x34, 0xE4, hl_tlv),
422 422
423 SOC_SINGLE_TLV("ADC A Boost Volume", 423 SOC_SINGLE_TLV("ADC A Boost Volume",
424 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv), 424 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
425 425
426 SOC_SINGLE_TLV("ADC B Boost Volume", 426 SOC_SINGLE_TLV("ADC B Boost Volume",
427 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv), 427 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
428 428
429 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume", 429 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
430 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv), 430 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
431 431
432 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume", 432 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
433 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv), 433 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
434 434
435 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL, 435 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
436 CS42L73_HPBAVOL, 7, 1, 1), 436 CS42L73_HPBAVOL, 7, 1, 1),
437 437
438 SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL, 438 SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
439 CS42L73_LOBAVOL, 7, 1, 1), 439 CS42L73_LOBAVOL, 7, 1, 1),
440 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1), 440 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
441 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0, 441 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
442 1, 1, 1), 442 1, 1, 1),
443 SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1, 443 SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
444 1), 444 1),
445 SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1, 445 SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
446 1), 446 1),
447 447
448 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0), 448 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
449 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0), 449 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
450 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0), 450 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
451 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0), 451 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
452 452
453 SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1, 453 SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
454 0), 454 0),
455 455
456 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F, 456 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
457 0), 457 0),
458 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0, 458 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
459 0x3F, 0), 459 0x3F, 0),
460 460
461 461
462 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0), 462 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
463 SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1, 463 SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
464 0), 464 0),
465 465
466 SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7, 466 SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
467 1, limiter_tlv), 467 1, limiter_tlv),
468 468
469 SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1, 469 SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
470 limiter_tlv), 470 limiter_tlv),
471 471
472 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0, 472 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
473 0x3F, 0), 473 0x3F, 0),
474 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0, 474 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
475 0x3F, 0), 475 0x3F, 0),
476 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0), 476 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
477 SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK, 477 SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
478 6, 1, 0), 478 6, 1, 0),
479 SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5, 479 SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
480 7, 1, limiter_tlv), 480 7, 1, limiter_tlv),
481 481
482 SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1, 482 SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
483 limiter_tlv), 483 limiter_tlv),
484 484
485 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0, 485 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
486 0x3F, 0), 486 0x3F, 0),
487 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0, 487 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
488 0x3F, 0), 488 0x3F, 0),
489 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0), 489 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
490 SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5, 490 SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
491 7, 1, limiter_tlv), 491 7, 1, limiter_tlv),
492 492
493 SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1, 493 SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
494 limiter_tlv), 494 limiter_tlv),
495 495
496 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0), 496 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
497 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0), 497 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
498 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0), 498 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
499 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0, 499 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
500 limiter_tlv), 500 limiter_tlv),
501 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0, 501 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
502 limiter_tlv), 502 limiter_tlv),
503 503
504 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0), 504 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
505 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0), 505 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
506 /* 506 /*
507 NG Threshold depends on NG_BOOTSAB, which selects 507 NG Threshold depends on NG_BOOTSAB, which selects
508 between two threshold scales in decibels. 508 between two threshold scales in decibels.
509 Set linear values for now .. 509 Set linear values for now ..
510 */ 510 */
511 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0), 511 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
512 SOC_ENUM("NG Delay", ng_delay_enum), 512 SOC_ENUM("NG Delay", ng_delay_enum),
513 513
514 SOC_ENUM("Charge Pump Frequency", charge_pump_enum), 514 SOC_ENUM("Charge Pump Frequency", charge_pump_enum),
515 515
516 SOC_DOUBLE_R_TLV("XSP-IP Volume", 516 SOC_DOUBLE_R_TLV("XSP-IP Volume",
517 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1, 517 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
518 attn_tlv), 518 attn_tlv),
519 SOC_DOUBLE_R_TLV("XSP-XSP Volume", 519 SOC_DOUBLE_R_TLV("XSP-XSP Volume",
520 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1, 520 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
521 attn_tlv), 521 attn_tlv),
522 SOC_DOUBLE_R_TLV("XSP-ASP Volume", 522 SOC_DOUBLE_R_TLV("XSP-ASP Volume",
523 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1, 523 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
524 attn_tlv), 524 attn_tlv),
525 SOC_DOUBLE_R_TLV("XSP-VSP Volume", 525 SOC_DOUBLE_R_TLV("XSP-VSP Volume",
526 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1, 526 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
527 attn_tlv), 527 attn_tlv),
528 528
529 SOC_DOUBLE_R_TLV("ASP-IP Volume", 529 SOC_DOUBLE_R_TLV("ASP-IP Volume",
530 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1, 530 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
531 attn_tlv), 531 attn_tlv),
532 SOC_DOUBLE_R_TLV("ASP-XSP Volume", 532 SOC_DOUBLE_R_TLV("ASP-XSP Volume",
533 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1, 533 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
534 attn_tlv), 534 attn_tlv),
535 SOC_DOUBLE_R_TLV("ASP-ASP Volume", 535 SOC_DOUBLE_R_TLV("ASP-ASP Volume",
536 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1, 536 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
537 attn_tlv), 537 attn_tlv),
538 SOC_DOUBLE_R_TLV("ASP-VSP Volume", 538 SOC_DOUBLE_R_TLV("ASP-VSP Volume",
539 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1, 539 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
540 attn_tlv), 540 attn_tlv),
541 541
542 SOC_DOUBLE_R_TLV("VSP-IP Volume", 542 SOC_DOUBLE_R_TLV("VSP-IP Volume",
543 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1, 543 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
544 attn_tlv), 544 attn_tlv),
545 SOC_DOUBLE_R_TLV("VSP-XSP Volume", 545 SOC_DOUBLE_R_TLV("VSP-XSP Volume",
546 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1, 546 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
547 attn_tlv), 547 attn_tlv),
548 SOC_DOUBLE_R_TLV("VSP-ASP Volume", 548 SOC_DOUBLE_R_TLV("VSP-ASP Volume",
549 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1, 549 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
550 attn_tlv), 550 attn_tlv),
551 SOC_DOUBLE_R_TLV("VSP-VSP Volume", 551 SOC_DOUBLE_R_TLV("VSP-VSP Volume",
552 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1, 552 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
553 attn_tlv), 553 attn_tlv),
554 554
555 SOC_DOUBLE_R_TLV("HL-IP Volume", 555 SOC_DOUBLE_R_TLV("HL-IP Volume",
556 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1, 556 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
557 attn_tlv), 557 attn_tlv),
558 SOC_DOUBLE_R_TLV("HL-XSP Volume", 558 SOC_DOUBLE_R_TLV("HL-XSP Volume",
559 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1, 559 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
560 attn_tlv), 560 attn_tlv),
561 SOC_DOUBLE_R_TLV("HL-ASP Volume", 561 SOC_DOUBLE_R_TLV("HL-ASP Volume",
562 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1, 562 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
563 attn_tlv), 563 attn_tlv),
564 SOC_DOUBLE_R_TLV("HL-VSP Volume", 564 SOC_DOUBLE_R_TLV("HL-VSP Volume",
565 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1, 565 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
566 attn_tlv), 566 attn_tlv),
567 567
568 SOC_SINGLE_TLV("SPK-IP Mono Volume", 568 SOC_SINGLE_TLV("SPK-IP Mono Volume",
569 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv), 569 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
570 SOC_SINGLE_TLV("SPK-XSP Mono Volume", 570 SOC_SINGLE_TLV("SPK-XSP Mono Volume",
571 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv), 571 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
572 SOC_SINGLE_TLV("SPK-ASP Mono Volume", 572 SOC_SINGLE_TLV("SPK-ASP Mono Volume",
573 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv), 573 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
574 SOC_SINGLE_TLV("SPK-VSP Mono Volume", 574 SOC_SINGLE_TLV("SPK-VSP Mono Volume",
575 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv), 575 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
576 576
577 SOC_SINGLE_TLV("ESL-IP Mono Volume", 577 SOC_SINGLE_TLV("ESL-IP Mono Volume",
578 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv), 578 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
579 SOC_SINGLE_TLV("ESL-XSP Mono Volume", 579 SOC_SINGLE_TLV("ESL-XSP Mono Volume",
580 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv), 580 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
581 SOC_SINGLE_TLV("ESL-ASP Mono Volume", 581 SOC_SINGLE_TLV("ESL-ASP Mono Volume",
582 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv), 582 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
583 SOC_SINGLE_TLV("ESL-VSP Mono Volume", 583 SOC_SINGLE_TLV("ESL-VSP Mono Volume",
584 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv), 584 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
585 585
586 SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum), 586 SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
587 587
588 SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum), 588 SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
589 SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum), 589 SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
590 }; 590 };
591 591
592 static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w, 592 static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w,
593 struct snd_kcontrol *kcontrol, int event) 593 struct snd_kcontrol *kcontrol, int event)
594 { 594 {
595 struct snd_soc_codec *codec = w->codec; 595 struct snd_soc_codec *codec = w->codec;
596 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 596 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
597 switch (event) { 597 switch (event) {
598 case SND_SOC_DAPM_POST_PMD: 598 case SND_SOC_DAPM_POST_PMD:
599 /* 150 ms delay between setting PDN and MCLKDIS */ 599 /* 150 ms delay between setting PDN and MCLKDIS */
600 priv->shutdwn_delay = 150; 600 priv->shutdwn_delay = 150;
601 break; 601 break;
602 default: 602 default:
603 pr_err("Invalid event = 0x%x\n", event); 603 pr_err("Invalid event = 0x%x\n", event);
604 } 604 }
605 return 0; 605 return 0;
606 } 606 }
607 607
608 static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w, 608 static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w,
609 struct snd_kcontrol *kcontrol, int event) 609 struct snd_kcontrol *kcontrol, int event)
610 { 610 {
611 struct snd_soc_codec *codec = w->codec; 611 struct snd_soc_codec *codec = w->codec;
612 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 612 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
613 switch (event) { 613 switch (event) {
614 case SND_SOC_DAPM_POST_PMD: 614 case SND_SOC_DAPM_POST_PMD:
615 /* 50 ms delay between setting PDN and MCLKDIS */ 615 /* 50 ms delay between setting PDN and MCLKDIS */
616 if (priv->shutdwn_delay < 50) 616 if (priv->shutdwn_delay < 50)
617 priv->shutdwn_delay = 50; 617 priv->shutdwn_delay = 50;
618 break; 618 break;
619 default: 619 default:
620 pr_err("Invalid event = 0x%x\n", event); 620 pr_err("Invalid event = 0x%x\n", event);
621 } 621 }
622 return 0; 622 return 0;
623 } 623 }
624 624
625 625
626 static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w, 626 static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w,
627 struct snd_kcontrol *kcontrol, int event) 627 struct snd_kcontrol *kcontrol, int event)
628 { 628 {
629 struct snd_soc_codec *codec = w->codec; 629 struct snd_soc_codec *codec = w->codec;
630 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 630 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
631 switch (event) { 631 switch (event) {
632 case SND_SOC_DAPM_POST_PMD: 632 case SND_SOC_DAPM_POST_PMD:
633 /* 30 ms delay between setting PDN and MCLKDIS */ 633 /* 30 ms delay between setting PDN and MCLKDIS */
634 if (priv->shutdwn_delay < 30) 634 if (priv->shutdwn_delay < 30)
635 priv->shutdwn_delay = 30; 635 priv->shutdwn_delay = 30;
636 break; 636 break;
637 default: 637 default:
638 pr_err("Invalid event = 0x%x\n", event); 638 pr_err("Invalid event = 0x%x\n", event);
639 } 639 }
640 return 0; 640 return 0;
641 } 641 }
642 642
643 static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = { 643 static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
644 SND_SOC_DAPM_INPUT("DMICA"), 644 SND_SOC_DAPM_INPUT("DMICA"),
645 SND_SOC_DAPM_INPUT("DMICB"), 645 SND_SOC_DAPM_INPUT("DMICB"),
646 SND_SOC_DAPM_INPUT("LINEINA"), 646 SND_SOC_DAPM_INPUT("LINEINA"),
647 SND_SOC_DAPM_INPUT("LINEINB"), 647 SND_SOC_DAPM_INPUT("LINEINB"),
648 SND_SOC_DAPM_INPUT("MIC1"), 648 SND_SOC_DAPM_INPUT("MIC1"),
649 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0), 649 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
650 SND_SOC_DAPM_INPUT("MIC2"), 650 SND_SOC_DAPM_INPUT("MIC2"),
651 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0), 651 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
652 652
653 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0, 653 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
654 CS42L73_PWRCTL2, 1, 1), 654 CS42L73_PWRCTL2, 1, 1),
655 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0, 655 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
656 CS42L73_PWRCTL2, 1, 1), 656 CS42L73_PWRCTL2, 1, 1),
657 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0, 657 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
658 CS42L73_PWRCTL2, 3, 1), 658 CS42L73_PWRCTL2, 3, 1),
659 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0, 659 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
660 CS42L73_PWRCTL2, 3, 1), 660 CS42L73_PWRCTL2, 3, 1),
661 SND_SOC_DAPM_AIF_OUT("VSPOUTL", NULL, 0, 661 SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
662 CS42L73_PWRCTL2, 4, 1), 662 CS42L73_PWRCTL2, 4, 1),
663 SND_SOC_DAPM_AIF_OUT("VSPOUTR", NULL, 0,
664 CS42L73_PWRCTL2, 4, 1),
665 663
666 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0), 664 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
667 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0), 665 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
668 666
669 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux), 667 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
670 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux), 668 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
671 669
672 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1), 670 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
673 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1), 671 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
674 SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1), 672 SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
675 SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1), 673 SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
676 674
677 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM, 675 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
678 0, 0, input_left_mixer, 676 0, 0, input_left_mixer,
679 ARRAY_SIZE(input_left_mixer)), 677 ARRAY_SIZE(input_left_mixer)),
680 678
681 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM, 679 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
682 0, 0, input_right_mixer, 680 0, 0, input_right_mixer,
683 ARRAY_SIZE(input_right_mixer)), 681 ARRAY_SIZE(input_right_mixer)),
684 682
685 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 683 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
686 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 684 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
687 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 685 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
688 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 686 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
689 SND_SOC_DAPM_MIXER("VSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 687 SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
690 SND_SOC_DAPM_MIXER("VSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
691 688
692 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0, 689 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
693 CS42L73_PWRCTL2, 0, 1), 690 CS42L73_PWRCTL2, 0, 1),
694 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0, 691 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
695 CS42L73_PWRCTL2, 0, 1), 692 CS42L73_PWRCTL2, 0, 1),
696 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0, 693 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
697 CS42L73_PWRCTL2, 0, 1), 694 CS42L73_PWRCTL2, 0, 1),
698 695
699 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0, 696 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
700 CS42L73_PWRCTL2, 2, 1), 697 CS42L73_PWRCTL2, 2, 1),
701 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0, 698 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
702 CS42L73_PWRCTL2, 2, 1), 699 CS42L73_PWRCTL2, 2, 1),
703 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0, 700 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
704 CS42L73_PWRCTL2, 2, 1), 701 CS42L73_PWRCTL2, 2, 1),
705 702
706 SND_SOC_DAPM_AIF_IN("VSPIN", NULL, 0, 703 SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
707 CS42L73_PWRCTL2, 4, 1), 704 CS42L73_PWRCTL2, 4, 1),
708 705
709 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 706 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
710 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 707 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
711 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 708 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
712 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 709 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
713 710
714 SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM, 711 SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
715 0, 0, &esl_xsp_mixer), 712 0, 0, &esl_xsp_mixer),
716 713
717 SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM, 714 SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
718 0, 0, &esl_asp_mixer), 715 0, 0, &esl_asp_mixer),
719 716
720 SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM, 717 SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
721 0, 0, &spk_asp_mixer), 718 0, 0, &spk_asp_mixer),
722 719
723 SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM, 720 SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
724 0, 0, &spk_xsp_mixer), 721 0, 0, &spk_xsp_mixer),
725 722
726 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 723 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
727 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 724 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
728 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 725 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
729 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 726 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
730 727
731 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1, 728 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
732 &hp_amp_ctl, cs42l73_hp_amp_event, 729 &hp_amp_ctl, cs42l73_hp_amp_event,
733 SND_SOC_DAPM_POST_PMD), 730 SND_SOC_DAPM_POST_PMD),
734 SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1, 731 SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
735 &lo_amp_ctl), 732 &lo_amp_ctl),
736 SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1, 733 SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1,
737 &spk_amp_ctl, cs42l73_spklo_spk_amp_event, 734 &spk_amp_ctl, cs42l73_spklo_spk_amp_event,
738 SND_SOC_DAPM_POST_PMD), 735 SND_SOC_DAPM_POST_PMD),
739 SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1, 736 SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1,
740 &ear_amp_ctl, cs42l73_ear_amp_event, 737 &ear_amp_ctl, cs42l73_ear_amp_event,
741 SND_SOC_DAPM_POST_PMD), 738 SND_SOC_DAPM_POST_PMD),
742 SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1, 739 SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
743 &spklo_amp_ctl, cs42l73_spklo_spk_amp_event, 740 &spklo_amp_ctl, cs42l73_spklo_spk_amp_event,
744 SND_SOC_DAPM_POST_PMD), 741 SND_SOC_DAPM_POST_PMD),
745 742
746 SND_SOC_DAPM_OUTPUT("HPOUTA"), 743 SND_SOC_DAPM_OUTPUT("HPOUTA"),
747 SND_SOC_DAPM_OUTPUT("HPOUTB"), 744 SND_SOC_DAPM_OUTPUT("HPOUTB"),
748 SND_SOC_DAPM_OUTPUT("LINEOUTA"), 745 SND_SOC_DAPM_OUTPUT("LINEOUTA"),
749 SND_SOC_DAPM_OUTPUT("LINEOUTB"), 746 SND_SOC_DAPM_OUTPUT("LINEOUTB"),
750 SND_SOC_DAPM_OUTPUT("EAROUT"), 747 SND_SOC_DAPM_OUTPUT("EAROUT"),
751 SND_SOC_DAPM_OUTPUT("SPKOUT"), 748 SND_SOC_DAPM_OUTPUT("SPKOUT"),
752 SND_SOC_DAPM_OUTPUT("SPKLINEOUT"), 749 SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
753 }; 750 };
754 751
755 static const struct snd_soc_dapm_route cs42l73_audio_map[] = { 752 static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
756 753
757 /* SPKLO EARSPK Paths */ 754 /* SPKLO EARSPK Paths */
758 {"EAROUT", NULL, "EAR Amp"}, 755 {"EAROUT", NULL, "EAR Amp"},
759 {"SPKLINEOUT", NULL, "SPKLO Amp"}, 756 {"SPKLINEOUT", NULL, "SPKLO Amp"},
760 757
761 {"EAR Amp", "Switch", "ESL DAC"}, 758 {"EAR Amp", "Switch", "ESL DAC"},
762 {"SPKLO Amp", "Switch", "ESL DAC"}, 759 {"SPKLO Amp", "Switch", "ESL DAC"},
763 760
764 {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"}, 761 {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
765 {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"}, 762 {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
766 {"ESL DAC", "ESL-VSP Mono Volume", "VSPIN"}, 763 {"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"},
767 /* Loopback */ 764 /* Loopback */
768 {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"}, 765 {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
769 {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"}, 766 {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
770 767
771 {"ESL Mixer", NULL, "ESL-ASP Mux"}, 768 {"ESL Mixer", NULL, "ESL-ASP Mux"},
772 {"ESL Mixer", NULL, "ESL-XSP Mux"}, 769 {"ESL Mixer", NULL, "ESL-XSP Mux"},
773 770
774 {"ESL-ASP Mux", "Left", "ASPINL"}, 771 {"ESL-ASP Mux", "Left", "ASPINL"},
775 {"ESL-ASP Mux", "Right", "ASPINR"}, 772 {"ESL-ASP Mux", "Right", "ASPINR"},
776 {"ESL-ASP Mux", "Mono Mix", "ASPINM"}, 773 {"ESL-ASP Mux", "Mono Mix", "ASPINM"},
777 774
778 {"ESL-XSP Mux", "Left", "XSPINL"}, 775 {"ESL-XSP Mux", "Left", "XSPINL"},
779 {"ESL-XSP Mux", "Right", "XSPINR"}, 776 {"ESL-XSP Mux", "Right", "XSPINR"},
780 {"ESL-XSP Mux", "Mono Mix", "XSPINM"}, 777 {"ESL-XSP Mux", "Mono Mix", "XSPINM"},
781 778
782 /* Speakerphone Paths */ 779 /* Speakerphone Paths */
783 {"SPKOUT", NULL, "SPK Amp"}, 780 {"SPKOUT", NULL, "SPK Amp"},
784 {"SPK Amp", "Switch", "SPK DAC"}, 781 {"SPK Amp", "Switch", "SPK DAC"},
785 782
786 {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"}, 783 {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
787 {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"}, 784 {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
788 {"SPK DAC", "SPK-VSP Mono Volume", "VSPIN"}, 785 {"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"},
789 /* Loopback */ 786 /* Loopback */
790 {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"}, 787 {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
791 {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"}, 788 {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
792 789
793 {"SPK Mixer", NULL, "SPK-ASP Mux"}, 790 {"SPK Mixer", NULL, "SPK-ASP Mux"},
794 {"SPK Mixer", NULL, "SPK-XSP Mux"}, 791 {"SPK Mixer", NULL, "SPK-XSP Mux"},
795 792
796 {"SPK-ASP Mux", "Left", "ASPINL"}, 793 {"SPK-ASP Mux", "Left", "ASPINL"},
797 {"SPK-ASP Mux", "Mono Mix", "ASPINM"}, 794 {"SPK-ASP Mux", "Mono Mix", "ASPINM"},
798 {"SPK-ASP Mux", "Right", "ASPINR"}, 795 {"SPK-ASP Mux", "Right", "ASPINR"},
799 796
800 {"SPK-XSP Mux", "Left", "XSPINL"}, 797 {"SPK-XSP Mux", "Left", "XSPINL"},
801 {"SPK-XSP Mux", "Mono Mix", "XSPINM"}, 798 {"SPK-XSP Mux", "Mono Mix", "XSPINM"},
802 {"SPK-XSP Mux", "Right", "XSPINR"}, 799 {"SPK-XSP Mux", "Right", "XSPINR"},
803 800
804 /* HP LineOUT Paths */ 801 /* HP LineOUT Paths */
805 {"HPOUTA", NULL, "HP Amp"}, 802 {"HPOUTA", NULL, "HP Amp"},
806 {"HPOUTB", NULL, "HP Amp"}, 803 {"HPOUTB", NULL, "HP Amp"},
807 {"LINEOUTA", NULL, "LO Amp"}, 804 {"LINEOUTA", NULL, "LO Amp"},
808 {"LINEOUTB", NULL, "LO Amp"}, 805 {"LINEOUTB", NULL, "LO Amp"},
809 806
810 {"HP Amp", "Switch", "HL Left DAC"}, 807 {"HP Amp", "Switch", "HL Left DAC"},
811 {"HP Amp", "Switch", "HL Right DAC"}, 808 {"HP Amp", "Switch", "HL Right DAC"},
812 {"LO Amp", "Switch", "HL Left DAC"}, 809 {"LO Amp", "Switch", "HL Left DAC"},
813 {"LO Amp", "Switch", "HL Right DAC"}, 810 {"LO Amp", "Switch", "HL Right DAC"},
814 811
815 {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"}, 812 {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
816 {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"}, 813 {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
817 {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"}, 814 {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
818 {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"}, 815 {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
819 {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"}, 816 {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
820 {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"}, 817 {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
821 /* Loopback */ 818 /* Loopback */
822 {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"}, 819 {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
823 {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"}, 820 {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
824 {"HL Left Mixer", NULL, "Input Left Capture"}, 821 {"HL Left Mixer", NULL, "Input Left Capture"},
825 {"HL Right Mixer", NULL, "Input Right Capture"}, 822 {"HL Right Mixer", NULL, "Input Right Capture"},
826 823
827 {"HL Left Mixer", NULL, "ASPINL"}, 824 {"HL Left Mixer", NULL, "ASPINL"},
828 {"HL Right Mixer", NULL, "ASPINR"}, 825 {"HL Right Mixer", NULL, "ASPINR"},
829 {"HL Left Mixer", NULL, "XSPINL"}, 826 {"HL Left Mixer", NULL, "XSPINL"},
830 {"HL Right Mixer", NULL, "XSPINR"}, 827 {"HL Right Mixer", NULL, "XSPINR"},
831 {"HL Left Mixer", NULL, "VSPIN"}, 828 {"HL Left Mixer", NULL, "VSPINOUT"},
832 {"HL Right Mixer", NULL, "VSPIN"}, 829 {"HL Right Mixer", NULL, "VSPINOUT"},
833 830
834 {"ASPINL", NULL, "ASP Playback"}, 831 {"ASPINL", NULL, "ASP Playback"},
835 {"ASPINM", NULL, "ASP Playback"}, 832 {"ASPINM", NULL, "ASP Playback"},
836 {"ASPINR", NULL, "ASP Playback"}, 833 {"ASPINR", NULL, "ASP Playback"},
837 {"XSPINL", NULL, "XSP Playback"}, 834 {"XSPINL", NULL, "XSP Playback"},
838 {"XSPINM", NULL, "XSP Playback"}, 835 {"XSPINM", NULL, "XSP Playback"},
839 {"XSPINR", NULL, "XSP Playback"}, 836 {"XSPINR", NULL, "XSP Playback"},
840 {"VSPIN", NULL, "VSP Playback"}, 837 {"VSPINOUT", NULL, "VSP Playback"},
841 838
842 /* Capture Paths */ 839 /* Capture Paths */
843 {"MIC1", NULL, "MIC1 Bias"}, 840 {"MIC1", NULL, "MIC1 Bias"},
844 {"PGA Left Mux", "Mic 1", "MIC1"}, 841 {"PGA Left Mux", "Mic 1", "MIC1"},
845 {"MIC2", NULL, "MIC2 Bias"}, 842 {"MIC2", NULL, "MIC2 Bias"},
846 {"PGA Right Mux", "Mic 2", "MIC2"}, 843 {"PGA Right Mux", "Mic 2", "MIC2"},
847 844
848 {"PGA Left Mux", "Line A", "LINEINA"}, 845 {"PGA Left Mux", "Line A", "LINEINA"},
849 {"PGA Right Mux", "Line B", "LINEINB"}, 846 {"PGA Right Mux", "Line B", "LINEINB"},
850 847
851 {"PGA Left", NULL, "PGA Left Mux"}, 848 {"PGA Left", NULL, "PGA Left Mux"},
852 {"PGA Right", NULL, "PGA Right Mux"}, 849 {"PGA Right", NULL, "PGA Right Mux"},
853 850
854 {"ADC Left", NULL, "PGA Left"}, 851 {"ADC Left", NULL, "PGA Left"},
855 {"ADC Right", NULL, "PGA Right"}, 852 {"ADC Right", NULL, "PGA Right"},
856 {"DMIC Left", NULL, "DMICA"}, 853 {"DMIC Left", NULL, "DMICA"},
857 {"DMIC Right", NULL, "DMICB"}, 854 {"DMIC Right", NULL, "DMICB"},
858 855
859 {"Input Left Capture", "ADC Left Input", "ADC Left"}, 856 {"Input Left Capture", "ADC Left Input", "ADC Left"},
860 {"Input Right Capture", "ADC Right Input", "ADC Right"}, 857 {"Input Right Capture", "ADC Right Input", "ADC Right"},
861 {"Input Left Capture", "DMIC Left Input", "DMIC Left"}, 858 {"Input Left Capture", "DMIC Left Input", "DMIC Left"},
862 {"Input Right Capture", "DMIC Right Input", "DMIC Right"}, 859 {"Input Right Capture", "DMIC Right Input", "DMIC Right"},
863 860
864 /* Audio Capture */ 861 /* Audio Capture */
865 {"ASPL Output Mixer", NULL, "Input Left Capture"}, 862 {"ASPL Output Mixer", NULL, "Input Left Capture"},
866 {"ASPR Output Mixer", NULL, "Input Right Capture"}, 863 {"ASPR Output Mixer", NULL, "Input Right Capture"},
867 864
868 {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"}, 865 {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
869 {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"}, 866 {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
870 867
871 /* Auxillary Capture */ 868 /* Auxillary Capture */
872 {"XSPL Output Mixer", NULL, "Input Left Capture"}, 869 {"XSPL Output Mixer", NULL, "Input Left Capture"},
873 {"XSPR Output Mixer", NULL, "Input Right Capture"}, 870 {"XSPR Output Mixer", NULL, "Input Right Capture"},
874 871
875 {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"}, 872 {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
876 {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"}, 873 {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
877 874
878 {"XSPOUTL", NULL, "XSPL Output Mixer"}, 875 {"XSPOUTL", NULL, "XSPL Output Mixer"},
879 {"XSPOUTR", NULL, "XSPR Output Mixer"}, 876 {"XSPOUTR", NULL, "XSPR Output Mixer"},
880 877
881 /* Voice Capture */ 878 /* Voice Capture */
882 {"VSPL Output Mixer", NULL, "Input Left Capture"}, 879 {"VSP Output Mixer", NULL, "Input Left Capture"},
883 {"VSPR Output Mixer", NULL, "Input Left Capture"}, 880 {"VSP Output Mixer", NULL, "Input Right Capture"},
884 881
885 {"VSPOUTL", "VSP-IP Volume", "VSPL Output Mixer"}, 882 {"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"},
886 {"VSPOUTR", "VSP-IP Volume", "VSPR Output Mixer"},
887 883
888 {"VSPOUTL", NULL, "VSPL Output Mixer"}, 884 {"VSPINOUT", NULL, "VSP Output Mixer"},
889 {"VSPOUTR", NULL, "VSPR Output Mixer"},
890 885
891 {"ASP Capture", NULL, "ASPOUTL"}, 886 {"ASP Capture", NULL, "ASPOUTL"},
892 {"ASP Capture", NULL, "ASPOUTR"}, 887 {"ASP Capture", NULL, "ASPOUTR"},
893 {"XSP Capture", NULL, "XSPOUTL"}, 888 {"XSP Capture", NULL, "XSPOUTL"},
894 {"XSP Capture", NULL, "XSPOUTR"}, 889 {"XSP Capture", NULL, "XSPOUTR"},
895 {"VSP Capture", NULL, "VSPOUTL"}, 890 {"VSP Capture", NULL, "VSPINOUT"},
896 {"VSP Capture", NULL, "VSPOUTR"},
897 }; 891 };
898 892
899 struct cs42l73_mclk_div { 893 struct cs42l73_mclk_div {
900 u32 mclk; 894 u32 mclk;
901 u32 srate; 895 u32 srate;
902 u8 mmcc; 896 u8 mmcc;
903 }; 897 };
904 898
905 static struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = { 899 static struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
906 /* MCLK, Sample Rate, xMMCC[5:0] */ 900 /* MCLK, Sample Rate, xMMCC[5:0] */
907 {5644800, 11025, 0x30}, 901 {5644800, 11025, 0x30},
908 {5644800, 22050, 0x20}, 902 {5644800, 22050, 0x20},
909 {5644800, 44100, 0x10}, 903 {5644800, 44100, 0x10},
910 904
911 {6000000, 8000, 0x39}, 905 {6000000, 8000, 0x39},
912 {6000000, 11025, 0x33}, 906 {6000000, 11025, 0x33},
913 {6000000, 12000, 0x31}, 907 {6000000, 12000, 0x31},
914 {6000000, 16000, 0x29}, 908 {6000000, 16000, 0x29},
915 {6000000, 22050, 0x23}, 909 {6000000, 22050, 0x23},
916 {6000000, 24000, 0x21}, 910 {6000000, 24000, 0x21},
917 {6000000, 32000, 0x19}, 911 {6000000, 32000, 0x19},
918 {6000000, 44100, 0x13}, 912 {6000000, 44100, 0x13},
919 {6000000, 48000, 0x11}, 913 {6000000, 48000, 0x11},
920 914
921 {6144000, 8000, 0x38}, 915 {6144000, 8000, 0x38},
922 {6144000, 12000, 0x30}, 916 {6144000, 12000, 0x30},
923 {6144000, 16000, 0x28}, 917 {6144000, 16000, 0x28},
924 {6144000, 24000, 0x20}, 918 {6144000, 24000, 0x20},
925 {6144000, 32000, 0x18}, 919 {6144000, 32000, 0x18},
926 {6144000, 48000, 0x10}, 920 {6144000, 48000, 0x10},
927 921
928 {6500000, 8000, 0x3C}, 922 {6500000, 8000, 0x3C},
929 {6500000, 11025, 0x35}, 923 {6500000, 11025, 0x35},
930 {6500000, 12000, 0x34}, 924 {6500000, 12000, 0x34},
931 {6500000, 16000, 0x2C}, 925 {6500000, 16000, 0x2C},
932 {6500000, 22050, 0x25}, 926 {6500000, 22050, 0x25},
933 {6500000, 24000, 0x24}, 927 {6500000, 24000, 0x24},
934 {6500000, 32000, 0x1C}, 928 {6500000, 32000, 0x1C},
935 {6500000, 44100, 0x15}, 929 {6500000, 44100, 0x15},
936 {6500000, 48000, 0x14}, 930 {6500000, 48000, 0x14},
937 931
938 {6400000, 8000, 0x3E}, 932 {6400000, 8000, 0x3E},
939 {6400000, 11025, 0x37}, 933 {6400000, 11025, 0x37},
940 {6400000, 12000, 0x36}, 934 {6400000, 12000, 0x36},
941 {6400000, 16000, 0x2E}, 935 {6400000, 16000, 0x2E},
942 {6400000, 22050, 0x27}, 936 {6400000, 22050, 0x27},
943 {6400000, 24000, 0x26}, 937 {6400000, 24000, 0x26},
944 {6400000, 32000, 0x1E}, 938 {6400000, 32000, 0x1E},
945 {6400000, 44100, 0x17}, 939 {6400000, 44100, 0x17},
946 {6400000, 48000, 0x16}, 940 {6400000, 48000, 0x16},
947 }; 941 };
948 942
949 struct cs42l73_mclkx_div { 943 struct cs42l73_mclkx_div {
950 u32 mclkx; 944 u32 mclkx;
951 u8 ratio; 945 u8 ratio;
952 u8 mclkdiv; 946 u8 mclkdiv;
953 }; 947 };
954 948
955 static struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = { 949 static struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
956 {5644800, 1, 0}, /* 5644800 */ 950 {5644800, 1, 0}, /* 5644800 */
957 {6000000, 1, 0}, /* 6000000 */ 951 {6000000, 1, 0}, /* 6000000 */
958 {6144000, 1, 0}, /* 6144000 */ 952 {6144000, 1, 0}, /* 6144000 */
959 {11289600, 2, 2}, /* 5644800 */ 953 {11289600, 2, 2}, /* 5644800 */
960 {12288000, 2, 2}, /* 6144000 */ 954 {12288000, 2, 2}, /* 6144000 */
961 {12000000, 2, 2}, /* 6000000 */ 955 {12000000, 2, 2}, /* 6000000 */
962 {13000000, 2, 2}, /* 6500000 */ 956 {13000000, 2, 2}, /* 6500000 */
963 {19200000, 3, 3}, /* 6400000 */ 957 {19200000, 3, 3}, /* 6400000 */
964 {24000000, 4, 4}, /* 6000000 */ 958 {24000000, 4, 4}, /* 6000000 */
965 {26000000, 4, 4}, /* 6500000 */ 959 {26000000, 4, 4}, /* 6500000 */
966 {38400000, 6, 5} /* 6400000 */ 960 {38400000, 6, 5} /* 6400000 */
967 }; 961 };
968 962
969 static int cs42l73_get_mclkx_coeff(int mclkx) 963 static int cs42l73_get_mclkx_coeff(int mclkx)
970 { 964 {
971 int i; 965 int i;
972 966
973 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) { 967 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
974 if (cs42l73_mclkx_coeffs[i].mclkx == mclkx) 968 if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
975 return i; 969 return i;
976 } 970 }
977 return -EINVAL; 971 return -EINVAL;
978 } 972 }
979 973
980 static int cs42l73_get_mclk_coeff(int mclk, int srate) 974 static int cs42l73_get_mclk_coeff(int mclk, int srate)
981 { 975 {
982 int i; 976 int i;
983 977
984 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) { 978 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
985 if (cs42l73_mclk_coeffs[i].mclk == mclk && 979 if (cs42l73_mclk_coeffs[i].mclk == mclk &&
986 cs42l73_mclk_coeffs[i].srate == srate) 980 cs42l73_mclk_coeffs[i].srate == srate)
987 return i; 981 return i;
988 } 982 }
989 return -EINVAL; 983 return -EINVAL;
990 984
991 } 985 }
992 986
993 static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq) 987 static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
994 { 988 {
995 struct snd_soc_codec *codec = dai->codec; 989 struct snd_soc_codec *codec = dai->codec;
996 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 990 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
997 991
998 int mclkx_coeff; 992 int mclkx_coeff;
999 u32 mclk = 0; 993 u32 mclk = 0;
1000 u8 dmmcc = 0; 994 u8 dmmcc = 0;
1001 995
1002 /* MCLKX -> MCLK */ 996 /* MCLKX -> MCLK */
1003 mclkx_coeff = cs42l73_get_mclkx_coeff(freq); 997 mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
1004 if (mclkx_coeff < 0) 998 if (mclkx_coeff < 0)
1005 return mclkx_coeff; 999 return mclkx_coeff;
1006 1000
1007 mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx / 1001 mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
1008 cs42l73_mclkx_coeffs[mclkx_coeff].ratio; 1002 cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
1009 1003
1010 dev_dbg(codec->dev, "MCLK%u %u <-> internal MCLK %u\n", 1004 dev_dbg(codec->dev, "MCLK%u %u <-> internal MCLK %u\n",
1011 priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx, 1005 priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
1012 mclk); 1006 mclk);
1013 1007
1014 dmmcc = (priv->mclksel << 4) | 1008 dmmcc = (priv->mclksel << 4) |
1015 (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1); 1009 (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
1016 1010
1017 snd_soc_write(codec, CS42L73_DMMCC, dmmcc); 1011 snd_soc_write(codec, CS42L73_DMMCC, dmmcc);
1018 1012
1019 priv->sysclk = mclkx_coeff; 1013 priv->sysclk = mclkx_coeff;
1020 priv->mclk = mclk; 1014 priv->mclk = mclk;
1021 1015
1022 return 0; 1016 return 0;
1023 } 1017 }
1024 1018
1025 static int cs42l73_set_sysclk(struct snd_soc_dai *dai, 1019 static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
1026 int clk_id, unsigned int freq, int dir) 1020 int clk_id, unsigned int freq, int dir)
1027 { 1021 {
1028 struct snd_soc_codec *codec = dai->codec; 1022 struct snd_soc_codec *codec = dai->codec;
1029 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 1023 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
1030 1024
1031 switch (clk_id) { 1025 switch (clk_id) {
1032 case CS42L73_CLKID_MCLK1: 1026 case CS42L73_CLKID_MCLK1:
1033 break; 1027 break;
1034 case CS42L73_CLKID_MCLK2: 1028 case CS42L73_CLKID_MCLK2:
1035 break; 1029 break;
1036 default: 1030 default:
1037 return -EINVAL; 1031 return -EINVAL;
1038 } 1032 }
1039 1033
1040 if ((cs42l73_set_mclk(dai, freq)) < 0) { 1034 if ((cs42l73_set_mclk(dai, freq)) < 0) {
1041 dev_err(codec->dev, "Unable to set MCLK for dai %s\n", 1035 dev_err(codec->dev, "Unable to set MCLK for dai %s\n",
1042 dai->name); 1036 dai->name);
1043 return -EINVAL; 1037 return -EINVAL;
1044 } 1038 }
1045 1039
1046 priv->mclksel = clk_id; 1040 priv->mclksel = clk_id;
1047 1041
1048 return 0; 1042 return 0;
1049 } 1043 }
1050 1044
1051 static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1045 static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1052 { 1046 {
1053 struct snd_soc_codec *codec = codec_dai->codec; 1047 struct snd_soc_codec *codec = codec_dai->codec;
1054 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 1048 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
1055 u8 id = codec_dai->id; 1049 u8 id = codec_dai->id;
1056 unsigned int inv, format; 1050 unsigned int inv, format;
1057 u8 spc, mmcc; 1051 u8 spc, mmcc;
1058 1052
1059 spc = snd_soc_read(codec, CS42L73_SPC(id)); 1053 spc = snd_soc_read(codec, CS42L73_SPC(id));
1060 mmcc = snd_soc_read(codec, CS42L73_MMCC(id)); 1054 mmcc = snd_soc_read(codec, CS42L73_MMCC(id));
1061 1055
1062 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1056 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1063 case SND_SOC_DAIFMT_CBM_CFM: 1057 case SND_SOC_DAIFMT_CBM_CFM:
1064 mmcc |= MS_MASTER; 1058 mmcc |= MS_MASTER;
1065 break; 1059 break;
1066 1060
1067 case SND_SOC_DAIFMT_CBS_CFS: 1061 case SND_SOC_DAIFMT_CBS_CFS:
1068 mmcc &= ~MS_MASTER; 1062 mmcc &= ~MS_MASTER;
1069 break; 1063 break;
1070 1064
1071 default: 1065 default:
1072 return -EINVAL; 1066 return -EINVAL;
1073 } 1067 }
1074 1068
1075 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1069 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1076 inv = (fmt & SND_SOC_DAIFMT_INV_MASK); 1070 inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
1077 1071
1078 switch (format) { 1072 switch (format) {
1079 case SND_SOC_DAIFMT_I2S: 1073 case SND_SOC_DAIFMT_I2S:
1080 spc &= ~SPDIF_PCM; 1074 spc &= ~SPDIF_PCM;
1081 break; 1075 break;
1082 case SND_SOC_DAIFMT_DSP_A: 1076 case SND_SOC_DAIFMT_DSP_A:
1083 case SND_SOC_DAIFMT_DSP_B: 1077 case SND_SOC_DAIFMT_DSP_B:
1084 if (mmcc & MS_MASTER) { 1078 if (mmcc & MS_MASTER) {
1085 dev_err(codec->dev, 1079 dev_err(codec->dev,
1086 "PCM format in slave mode only\n"); 1080 "PCM format in slave mode only\n");
1087 return -EINVAL; 1081 return -EINVAL;
1088 } 1082 }
1089 if (id == CS42L73_ASP) { 1083 if (id == CS42L73_ASP) {
1090 dev_err(codec->dev, 1084 dev_err(codec->dev,
1091 "PCM format is not supported on ASP port\n"); 1085 "PCM format is not supported on ASP port\n");
1092 return -EINVAL; 1086 return -EINVAL;
1093 } 1087 }
1094 spc |= SPDIF_PCM; 1088 spc |= SPDIF_PCM;
1095 break; 1089 break;
1096 default: 1090 default:
1097 return -EINVAL; 1091 return -EINVAL;
1098 } 1092 }
1099 1093
1100 if (spc & SPDIF_PCM) { 1094 if (spc & SPDIF_PCM) {
1101 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */ 1095 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
1102 spc &= ~(PCM_MODE_MASK | PCM_BIT_ORDER); 1096 spc &= ~(PCM_MODE_MASK | PCM_BIT_ORDER);
1103 switch (format) { 1097 switch (format) {
1104 case SND_SOC_DAIFMT_DSP_B: 1098 case SND_SOC_DAIFMT_DSP_B:
1105 if (inv == SND_SOC_DAIFMT_IB_IF) 1099 if (inv == SND_SOC_DAIFMT_IB_IF)
1106 spc |= PCM_MODE0; 1100 spc |= PCM_MODE0;
1107 if (inv == SND_SOC_DAIFMT_IB_NF) 1101 if (inv == SND_SOC_DAIFMT_IB_NF)
1108 spc |= PCM_MODE1; 1102 spc |= PCM_MODE1;
1109 break; 1103 break;
1110 case SND_SOC_DAIFMT_DSP_A: 1104 case SND_SOC_DAIFMT_DSP_A:
1111 if (inv == SND_SOC_DAIFMT_IB_IF) 1105 if (inv == SND_SOC_DAIFMT_IB_IF)
1112 spc |= PCM_MODE1; 1106 spc |= PCM_MODE1;
1113 break; 1107 break;
1114 default: 1108 default:
1115 return -EINVAL; 1109 return -EINVAL;
1116 } 1110 }
1117 } 1111 }
1118 1112
1119 priv->config[id].spc = spc; 1113 priv->config[id].spc = spc;
1120 priv->config[id].mmcc = mmcc; 1114 priv->config[id].mmcc = mmcc;
1121 1115
1122 return 0; 1116 return 0;
1123 } 1117 }
1124 1118
1125 static u32 cs42l73_asrc_rates[] = { 1119 static u32 cs42l73_asrc_rates[] = {
1126 8000, 11025, 12000, 16000, 22050, 1120 8000, 11025, 12000, 16000, 22050,
1127 24000, 32000, 44100, 48000 1121 24000, 32000, 44100, 48000
1128 }; 1122 };
1129 1123
1130 static unsigned int cs42l73_get_xspfs_coeff(u32 rate) 1124 static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
1131 { 1125 {
1132 int i; 1126 int i;
1133 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) { 1127 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
1134 if (cs42l73_asrc_rates[i] == rate) 1128 if (cs42l73_asrc_rates[i] == rate)
1135 return i + 1; 1129 return i + 1;
1136 } 1130 }
1137 return 0; /* 0 = Don't know */ 1131 return 0; /* 0 = Don't know */
1138 } 1132 }
1139 1133
1140 static void cs42l73_update_asrc(struct snd_soc_codec *codec, int id, int srate) 1134 static void cs42l73_update_asrc(struct snd_soc_codec *codec, int id, int srate)
1141 { 1135 {
1142 u8 spfs = 0; 1136 u8 spfs = 0;
1143 1137
1144 if (srate > 0) 1138 if (srate > 0)
1145 spfs = cs42l73_get_xspfs_coeff(srate); 1139 spfs = cs42l73_get_xspfs_coeff(srate);
1146 1140
1147 switch (id) { 1141 switch (id) {
1148 case CS42L73_XSP: 1142 case CS42L73_XSP:
1149 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0x0f, spfs); 1143 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0x0f, spfs);
1150 break; 1144 break;
1151 case CS42L73_ASP: 1145 case CS42L73_ASP:
1152 snd_soc_update_bits(codec, CS42L73_ASPC, 0x3c, spfs << 2); 1146 snd_soc_update_bits(codec, CS42L73_ASPC, 0x3c, spfs << 2);
1153 break; 1147 break;
1154 case CS42L73_VSP: 1148 case CS42L73_VSP:
1155 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0xf0, spfs << 4); 1149 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0xf0, spfs << 4);
1156 break; 1150 break;
1157 default: 1151 default:
1158 break; 1152 break;
1159 } 1153 }
1160 } 1154 }
1161 1155
1162 static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream, 1156 static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1163 struct snd_pcm_hw_params *params, 1157 struct snd_pcm_hw_params *params,
1164 struct snd_soc_dai *dai) 1158 struct snd_soc_dai *dai)
1165 { 1159 {
1166 struct snd_soc_codec *codec = dai->codec; 1160 struct snd_soc_codec *codec = dai->codec;
1167 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 1161 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
1168 int id = dai->id; 1162 int id = dai->id;
1169 int mclk_coeff; 1163 int mclk_coeff;
1170 int srate = params_rate(params); 1164 int srate = params_rate(params);
1171 1165
1172 if (priv->config[id].mmcc & MS_MASTER) { 1166 if (priv->config[id].mmcc & MS_MASTER) {
1173 /* CS42L73 Master */ 1167 /* CS42L73 Master */
1174 /* MCLK -> srate */ 1168 /* MCLK -> srate */
1175 mclk_coeff = 1169 mclk_coeff =
1176 cs42l73_get_mclk_coeff(priv->mclk, srate); 1170 cs42l73_get_mclk_coeff(priv->mclk, srate);
1177 1171
1178 if (mclk_coeff < 0) 1172 if (mclk_coeff < 0)
1179 return -EINVAL; 1173 return -EINVAL;
1180 1174
1181 dev_dbg(codec->dev, 1175 dev_dbg(codec->dev,
1182 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n", 1176 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
1183 id, priv->mclk, srate, 1177 id, priv->mclk, srate,
1184 cs42l73_mclk_coeffs[mclk_coeff].mmcc); 1178 cs42l73_mclk_coeffs[mclk_coeff].mmcc);
1185 1179
1186 priv->config[id].mmcc &= 0xC0; 1180 priv->config[id].mmcc &= 0xC0;
1187 priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc; 1181 priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
1188 priv->config[id].spc &= 0xFC; 1182 priv->config[id].spc &= 0xFC;
1189 priv->config[id].spc |= MCK_SCLK_MCLK; 1183 priv->config[id].spc |= MCK_SCLK_MCLK;
1190 } else { 1184 } else {
1191 /* CS42L73 Slave */ 1185 /* CS42L73 Slave */
1192 priv->config[id].spc &= 0xFC; 1186 priv->config[id].spc &= 0xFC;
1193 priv->config[id].spc |= MCK_SCLK_64FS; 1187 priv->config[id].spc |= MCK_SCLK_64FS;
1194 } 1188 }
1195 /* Update ASRCs */ 1189 /* Update ASRCs */
1196 priv->config[id].srate = srate; 1190 priv->config[id].srate = srate;
1197 1191
1198 snd_soc_write(codec, CS42L73_SPC(id), priv->config[id].spc); 1192 snd_soc_write(codec, CS42L73_SPC(id), priv->config[id].spc);
1199 snd_soc_write(codec, CS42L73_MMCC(id), priv->config[id].mmcc); 1193 snd_soc_write(codec, CS42L73_MMCC(id), priv->config[id].mmcc);
1200 1194
1201 cs42l73_update_asrc(codec, id, srate); 1195 cs42l73_update_asrc(codec, id, srate);
1202 1196
1203 return 0; 1197 return 0;
1204 } 1198 }
1205 1199
1206 static int cs42l73_set_bias_level(struct snd_soc_codec *codec, 1200 static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
1207 enum snd_soc_bias_level level) 1201 enum snd_soc_bias_level level)
1208 { 1202 {
1209 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec); 1203 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);
1210 1204
1211 switch (level) { 1205 switch (level) {
1212 case SND_SOC_BIAS_ON: 1206 case SND_SOC_BIAS_ON:
1213 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0); 1207 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0);
1214 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0); 1208 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0);
1215 break; 1209 break;
1216 1210
1217 case SND_SOC_BIAS_PREPARE: 1211 case SND_SOC_BIAS_PREPARE:
1218 break; 1212 break;
1219 1213
1220 case SND_SOC_BIAS_STANDBY: 1214 case SND_SOC_BIAS_STANDBY:
1221 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1215 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1222 regcache_cache_only(cs42l73->regmap, false); 1216 regcache_cache_only(cs42l73->regmap, false);
1223 regcache_sync(cs42l73->regmap); 1217 regcache_sync(cs42l73->regmap);
1224 } 1218 }
1225 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1); 1219 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
1226 break; 1220 break;
1227 1221
1228 case SND_SOC_BIAS_OFF: 1222 case SND_SOC_BIAS_OFF:
1229 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1); 1223 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
1230 if (cs42l73->shutdwn_delay > 0) { 1224 if (cs42l73->shutdwn_delay > 0) {
1231 mdelay(cs42l73->shutdwn_delay); 1225 mdelay(cs42l73->shutdwn_delay);
1232 cs42l73->shutdwn_delay = 0; 1226 cs42l73->shutdwn_delay = 0;
1233 } else { 1227 } else {
1234 mdelay(15); /* Min amount of time requred to power 1228 mdelay(15); /* Min amount of time requred to power
1235 * down. 1229 * down.
1236 */ 1230 */
1237 } 1231 }
1238 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1); 1232 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1);
1239 break; 1233 break;
1240 } 1234 }
1241 codec->dapm.bias_level = level; 1235 codec->dapm.bias_level = level;
1242 return 0; 1236 return 0;
1243 } 1237 }
1244 1238
1245 static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate) 1239 static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
1246 { 1240 {
1247 struct snd_soc_codec *codec = dai->codec; 1241 struct snd_soc_codec *codec = dai->codec;
1248 int id = dai->id; 1242 int id = dai->id;
1249 1243
1250 return snd_soc_update_bits(codec, CS42L73_SPC(id), 1244 return snd_soc_update_bits(codec, CS42L73_SPC(id),
1251 0x7F, tristate << 7); 1245 0x7F, tristate << 7);
1252 } 1246 }
1253 1247
1254 static struct snd_pcm_hw_constraint_list constraints_12_24 = { 1248 static struct snd_pcm_hw_constraint_list constraints_12_24 = {
1255 .count = ARRAY_SIZE(cs42l73_asrc_rates), 1249 .count = ARRAY_SIZE(cs42l73_asrc_rates),
1256 .list = cs42l73_asrc_rates, 1250 .list = cs42l73_asrc_rates,
1257 }; 1251 };
1258 1252
1259 static int cs42l73_pcm_startup(struct snd_pcm_substream *substream, 1253 static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
1260 struct snd_soc_dai *dai) 1254 struct snd_soc_dai *dai)
1261 { 1255 {
1262 snd_pcm_hw_constraint_list(substream->runtime, 0, 1256 snd_pcm_hw_constraint_list(substream->runtime, 0,
1263 SNDRV_PCM_HW_PARAM_RATE, 1257 SNDRV_PCM_HW_PARAM_RATE,
1264 &constraints_12_24); 1258 &constraints_12_24);
1265 return 0; 1259 return 0;
1266 } 1260 }
1267 1261
1268 /* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */ 1262 /* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
1269 #define CS42L73_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT) 1263 #define CS42L73_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
1270 1264
1271 1265
1272 #define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1266 #define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1273 SNDRV_PCM_FMTBIT_S24_LE) 1267 SNDRV_PCM_FMTBIT_S24_LE)
1274 1268
1275 static const struct snd_soc_dai_ops cs42l73_ops = { 1269 static const struct snd_soc_dai_ops cs42l73_ops = {
1276 .startup = cs42l73_pcm_startup, 1270 .startup = cs42l73_pcm_startup,
1277 .hw_params = cs42l73_pcm_hw_params, 1271 .hw_params = cs42l73_pcm_hw_params,
1278 .set_fmt = cs42l73_set_dai_fmt, 1272 .set_fmt = cs42l73_set_dai_fmt,
1279 .set_sysclk = cs42l73_set_sysclk, 1273 .set_sysclk = cs42l73_set_sysclk,
1280 .set_tristate = cs42l73_set_tristate, 1274 .set_tristate = cs42l73_set_tristate,
1281 }; 1275 };
1282 1276
1283 static struct snd_soc_dai_driver cs42l73_dai[] = { 1277 static struct snd_soc_dai_driver cs42l73_dai[] = {
1284 { 1278 {
1285 .name = "cs42l73-xsp", 1279 .name = "cs42l73-xsp",
1286 .id = CS42L73_XSP, 1280 .id = CS42L73_XSP,
1287 .playback = { 1281 .playback = {
1288 .stream_name = "XSP Playback", 1282 .stream_name = "XSP Playback",
1289 .channels_min = 1, 1283 .channels_min = 1,
1290 .channels_max = 2, 1284 .channels_max = 2,
1291 .rates = CS42L73_RATES, 1285 .rates = CS42L73_RATES,
1292 .formats = CS42L73_FORMATS, 1286 .formats = CS42L73_FORMATS,
1293 }, 1287 },
1294 .capture = { 1288 .capture = {
1295 .stream_name = "XSP Capture", 1289 .stream_name = "XSP Capture",
1296 .channels_min = 1, 1290 .channels_min = 1,
1297 .channels_max = 2, 1291 .channels_max = 2,
1298 .rates = CS42L73_RATES, 1292 .rates = CS42L73_RATES,
1299 .formats = CS42L73_FORMATS, 1293 .formats = CS42L73_FORMATS,
1300 }, 1294 },
1301 .ops = &cs42l73_ops, 1295 .ops = &cs42l73_ops,
1302 .symmetric_rates = 1, 1296 .symmetric_rates = 1,
1303 }, 1297 },
1304 { 1298 {
1305 .name = "cs42l73-asp", 1299 .name = "cs42l73-asp",
1306 .id = CS42L73_ASP, 1300 .id = CS42L73_ASP,
1307 .playback = { 1301 .playback = {
1308 .stream_name = "ASP Playback", 1302 .stream_name = "ASP Playback",
1309 .channels_min = 2, 1303 .channels_min = 2,
1310 .channels_max = 2, 1304 .channels_max = 2,
1311 .rates = CS42L73_RATES, 1305 .rates = CS42L73_RATES,
1312 .formats = CS42L73_FORMATS, 1306 .formats = CS42L73_FORMATS,
1313 }, 1307 },
1314 .capture = { 1308 .capture = {
1315 .stream_name = "ASP Capture", 1309 .stream_name = "ASP Capture",
1316 .channels_min = 2, 1310 .channels_min = 2,
1317 .channels_max = 2, 1311 .channels_max = 2,
1318 .rates = CS42L73_RATES, 1312 .rates = CS42L73_RATES,
1319 .formats = CS42L73_FORMATS, 1313 .formats = CS42L73_FORMATS,
1320 }, 1314 },
1321 .ops = &cs42l73_ops, 1315 .ops = &cs42l73_ops,
1322 .symmetric_rates = 1, 1316 .symmetric_rates = 1,
1323 }, 1317 },
1324 { 1318 {
1325 .name = "cs42l73-vsp", 1319 .name = "cs42l73-vsp",
1326 .id = CS42L73_VSP, 1320 .id = CS42L73_VSP,
1327 .playback = { 1321 .playback = {
1328 .stream_name = "VSP Playback", 1322 .stream_name = "VSP Playback",
1329 .channels_min = 1, 1323 .channels_min = 1,
1330 .channels_max = 2, 1324 .channels_max = 2,
1331 .rates = CS42L73_RATES, 1325 .rates = CS42L73_RATES,
1332 .formats = CS42L73_FORMATS, 1326 .formats = CS42L73_FORMATS,
1333 }, 1327 },
1334 .capture = { 1328 .capture = {
1335 .stream_name = "VSP Capture", 1329 .stream_name = "VSP Capture",
1336 .channels_min = 1, 1330 .channels_min = 1,
1337 .channels_max = 2, 1331 .channels_max = 2,
1338 .rates = CS42L73_RATES, 1332 .rates = CS42L73_RATES,
1339 .formats = CS42L73_FORMATS, 1333 .formats = CS42L73_FORMATS,
1340 }, 1334 },
1341 .ops = &cs42l73_ops, 1335 .ops = &cs42l73_ops,
1342 .symmetric_rates = 1, 1336 .symmetric_rates = 1,
1343 } 1337 }
1344 }; 1338 };
1345 1339
1346 static int cs42l73_suspend(struct snd_soc_codec *codec) 1340 static int cs42l73_suspend(struct snd_soc_codec *codec)
1347 { 1341 {
1348 cs42l73_set_bias_level(codec, SND_SOC_BIAS_OFF); 1342 cs42l73_set_bias_level(codec, SND_SOC_BIAS_OFF);
1349 1343
1350 return 0; 1344 return 0;
1351 } 1345 }
1352 1346
1353 static int cs42l73_resume(struct snd_soc_codec *codec) 1347 static int cs42l73_resume(struct snd_soc_codec *codec)
1354 { 1348 {
1355 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1349 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1356 return 0; 1350 return 0;
1357 } 1351 }
1358 1352
1359 static int cs42l73_probe(struct snd_soc_codec *codec) 1353 static int cs42l73_probe(struct snd_soc_codec *codec)
1360 { 1354 {
1361 int ret; 1355 int ret;
1362 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec); 1356 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);
1363 1357
1364 codec->control_data = cs42l73->regmap; 1358 codec->control_data = cs42l73->regmap;
1365 1359
1366 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 1360 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1367 if (ret < 0) { 1361 if (ret < 0) {
1368 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1362 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1369 return ret; 1363 return ret;
1370 } 1364 }
1371 1365
1372 regcache_cache_only(cs42l73->regmap, true); 1366 regcache_cache_only(cs42l73->regmap, true);
1373 1367
1374 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1368 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1375 1369
1376 cs42l73->mclksel = CS42L73_CLKID_MCLK1; /* MCLK1 as master clk */ 1370 cs42l73->mclksel = CS42L73_CLKID_MCLK1; /* MCLK1 as master clk */
1377 cs42l73->mclk = 0; 1371 cs42l73->mclk = 0;
1378 1372
1379 return ret; 1373 return ret;
1380 } 1374 }
1381 1375
1382 static int cs42l73_remove(struct snd_soc_codec *codec) 1376 static int cs42l73_remove(struct snd_soc_codec *codec)
1383 { 1377 {
1384 cs42l73_set_bias_level(codec, SND_SOC_BIAS_OFF); 1378 cs42l73_set_bias_level(codec, SND_SOC_BIAS_OFF);
1385 return 0; 1379 return 0;
1386 } 1380 }
1387 1381
1388 static struct snd_soc_codec_driver soc_codec_dev_cs42l73 = { 1382 static struct snd_soc_codec_driver soc_codec_dev_cs42l73 = {
1389 .probe = cs42l73_probe, 1383 .probe = cs42l73_probe,
1390 .remove = cs42l73_remove, 1384 .remove = cs42l73_remove,
1391 .suspend = cs42l73_suspend, 1385 .suspend = cs42l73_suspend,
1392 .resume = cs42l73_resume, 1386 .resume = cs42l73_resume,
1393 .set_bias_level = cs42l73_set_bias_level, 1387 .set_bias_level = cs42l73_set_bias_level,
1394 1388
1395 .dapm_widgets = cs42l73_dapm_widgets, 1389 .dapm_widgets = cs42l73_dapm_widgets,
1396 .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets), 1390 .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets),
1397 .dapm_routes = cs42l73_audio_map, 1391 .dapm_routes = cs42l73_audio_map,
1398 .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map), 1392 .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map),
1399 1393
1400 .controls = cs42l73_snd_controls, 1394 .controls = cs42l73_snd_controls,
1401 .num_controls = ARRAY_SIZE(cs42l73_snd_controls), 1395 .num_controls = ARRAY_SIZE(cs42l73_snd_controls),
1402 }; 1396 };
1403 1397
1404 static struct regmap_config cs42l73_regmap = { 1398 static struct regmap_config cs42l73_regmap = {
1405 .reg_bits = 8, 1399 .reg_bits = 8,
1406 .val_bits = 8, 1400 .val_bits = 8,
1407 1401
1408 .max_register = CS42L73_MAX_REGISTER, 1402 .max_register = CS42L73_MAX_REGISTER,
1409 .reg_defaults = cs42l73_reg_defaults, 1403 .reg_defaults = cs42l73_reg_defaults,
1410 .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults), 1404 .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
1411 .volatile_reg = cs42l73_volatile_register, 1405 .volatile_reg = cs42l73_volatile_register,
1412 .readable_reg = cs42l73_readable_register, 1406 .readable_reg = cs42l73_readable_register,
1413 .cache_type = REGCACHE_RBTREE, 1407 .cache_type = REGCACHE_RBTREE,
1414 }; 1408 };
1415 1409
1416 static __devinit int cs42l73_i2c_probe(struct i2c_client *i2c_client, 1410 static __devinit int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1417 const struct i2c_device_id *id) 1411 const struct i2c_device_id *id)
1418 { 1412 {
1419 struct cs42l73_private *cs42l73; 1413 struct cs42l73_private *cs42l73;
1420 int ret; 1414 int ret;
1421 unsigned int devid = 0; 1415 unsigned int devid = 0;
1422 unsigned int reg; 1416 unsigned int reg;
1423 1417
1424 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private), 1418 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private),
1425 GFP_KERNEL); 1419 GFP_KERNEL);
1426 if (!cs42l73) { 1420 if (!cs42l73) {
1427 dev_err(&i2c_client->dev, "could not allocate codec\n"); 1421 dev_err(&i2c_client->dev, "could not allocate codec\n");
1428 return -ENOMEM; 1422 return -ENOMEM;
1429 } 1423 }
1430 1424
1431 i2c_set_clientdata(i2c_client, cs42l73); 1425 i2c_set_clientdata(i2c_client, cs42l73);
1432 1426
1433 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap); 1427 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
1434 if (IS_ERR(cs42l73->regmap)) { 1428 if (IS_ERR(cs42l73->regmap)) {
1435 ret = PTR_ERR(cs42l73->regmap); 1429 ret = PTR_ERR(cs42l73->regmap);
1436 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1430 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1437 return ret; 1431 return ret;
1438 } 1432 }
1439 /* initialize codec */ 1433 /* initialize codec */
1440 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg); 1434 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg);
1441 devid = (reg & 0xFF) << 12; 1435 devid = (reg & 0xFF) << 12;
1442 1436
1443 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, &reg); 1437 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, &reg);
1444 devid |= (reg & 0xFF) << 4; 1438 devid |= (reg & 0xFF) << 4;
1445 1439
1446 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg); 1440 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg);
1447 devid |= (reg & 0xF0) >> 4; 1441 devid |= (reg & 0xF0) >> 4;
1448 1442
1449 1443
1450 if (devid != CS42L73_DEVID) { 1444 if (devid != CS42L73_DEVID) {
1451 ret = -ENODEV; 1445 ret = -ENODEV;
1452 dev_err(&i2c_client->dev, 1446 dev_err(&i2c_client->dev,
1453 "CS42L73 Device ID (%X). Expected %X\n", 1447 "CS42L73 Device ID (%X). Expected %X\n",
1454 devid, CS42L73_DEVID); 1448 devid, CS42L73_DEVID);
1455 return ret; 1449 return ret;
1456 } 1450 }
1457 1451
1458 ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg); 1452 ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg);
1459 if (ret < 0) { 1453 if (ret < 0) {
1460 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1454 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1461 return ret;; 1455 return ret;;
1462 } 1456 }
1463 1457
1464 dev_info(&i2c_client->dev, 1458 dev_info(&i2c_client->dev,
1465 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF); 1459 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
1466 1460
1467 regcache_cache_only(cs42l73->regmap, true); 1461 regcache_cache_only(cs42l73->regmap, true);
1468 1462
1469 ret = snd_soc_register_codec(&i2c_client->dev, 1463 ret = snd_soc_register_codec(&i2c_client->dev,
1470 &soc_codec_dev_cs42l73, cs42l73_dai, 1464 &soc_codec_dev_cs42l73, cs42l73_dai,
1471 ARRAY_SIZE(cs42l73_dai)); 1465 ARRAY_SIZE(cs42l73_dai));
1472 if (ret < 0) 1466 if (ret < 0)
1473 return ret; 1467 return ret;
1474 return 0; 1468 return 0;
1475 } 1469 }
1476 1470
1477 static __devexit int cs42l73_i2c_remove(struct i2c_client *client) 1471 static __devexit int cs42l73_i2c_remove(struct i2c_client *client)
1478 { 1472 {
1479 snd_soc_unregister_codec(&client->dev); 1473 snd_soc_unregister_codec(&client->dev);
1480 return 0; 1474 return 0;
1481 } 1475 }
1482 1476
1483 static const struct i2c_device_id cs42l73_id[] = { 1477 static const struct i2c_device_id cs42l73_id[] = {
1484 {"cs42l73", 0}, 1478 {"cs42l73", 0},
1485 {} 1479 {}
1486 }; 1480 };
1487 1481
1488 MODULE_DEVICE_TABLE(i2c, cs42l73_id); 1482 MODULE_DEVICE_TABLE(i2c, cs42l73_id);
1489 1483
1490 static struct i2c_driver cs42l73_i2c_driver = { 1484 static struct i2c_driver cs42l73_i2c_driver = {
1491 .driver = { 1485 .driver = {
1492 .name = "cs42l73", 1486 .name = "cs42l73",
1493 .owner = THIS_MODULE, 1487 .owner = THIS_MODULE,
1494 }, 1488 },
1495 .id_table = cs42l73_id, 1489 .id_table = cs42l73_id,
1496 .probe = cs42l73_i2c_probe, 1490 .probe = cs42l73_i2c_probe,
1497 .remove = __devexit_p(cs42l73_i2c_remove), 1491 .remove = __devexit_p(cs42l73_i2c_remove),
1498 1492
1499 }; 1493 };
1500 1494
1501 module_i2c_driver(cs42l73_i2c_driver); 1495 module_i2c_driver(cs42l73_i2c_driver);
1502 1496
1503 MODULE_DESCRIPTION("ASoC CS42L73 driver"); 1497 MODULE_DESCRIPTION("ASoC CS42L73 driver");
1504 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>"); 1498 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1505 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 1499 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1506 MODULE_LICENSE("GPL"); 1500 MODULE_LICENSE("GPL");
1507 1501