Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 81d79bec348ab06cba9ae9fc03eb015b6b83703a

Authored by Ahmed S. Darwish 2007-02-10 17:44:30 +0800

Committed by Linus Torvalds 2007-02-12 02:51:24 +0800

[PATCH] V850: user ARRAY_SIZE macro when appropriate

Use ARRAY_SIZE macro already defined in linux/kernel.h

Signed-off-by: Ahmed S. Darwish <darwish.07@gmail.com>
Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 10 changed files with 13 additions and 15 deletions Inline Diff

arch/v850/kernel/anna.c
arch/v850/kernel/as85ep1.c
arch/v850/kernel/fpga85e2c.c
arch/v850/kernel/gbus_int.c
arch/v850/kernel/ma.c
arch/v850/kernel/me2.c
arch/v850/kernel/rte_cb.c
arch/v850/kernel/rte_mb_a_pci.c
arch/v850/kernel/rte_me2_cb.c
arch/v850/kernel/teg.c

arch/v850/kernel/anna.c

Diff comments View file @ 81d79be

1	/*	1	/*
2	* arch/v850/kernel/anna.c -- Anna V850E2 evaluation chip/board	2	* arch/v850/kernel/anna.c -- Anna V850E2 evaluation chip/board
3	*	3	*
4	* Copyright (C) 2002,03 NEC Electronics Corporation	4	* Copyright (C) 2002,03 NEC Electronics Corporation
5	* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>	5	* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
6	*	6	*
7	* This file is subject to the terms and conditions of the GNU General	7	* This file is subject to the terms and conditions of the GNU General
8	* Public License. See the file COPYING in the main directory of this	8	* Public License. See the file COPYING in the main directory of this
9	* archive for more details.	9	* archive for more details.
10	*	10	*
11	* Written by Miles Bader <miles@gnu.org>	11	* Written by Miles Bader <miles@gnu.org>
12	*/	12	*/
13		13
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/module.h>	15	#include <linux/module.h>
16	#include <linux/init.h>	16	#include <linux/init.h>
17	#include <linux/bootmem.h>	17	#include <linux/bootmem.h>
18	#include <linux/major.h>	18	#include <linux/major.h>
19	#include <linux/irq.h>	19	#include <linux/irq.h>
20		20
21	#include <asm/machdep.h>	21	#include <asm/machdep.h>
22	#include <asm/atomic.h>	22	#include <asm/atomic.h>
23	#include <asm/page.h>	23	#include <asm/page.h>
24	#include <asm/v850e_timer_d.h>	24	#include <asm/v850e_timer_d.h>
25	#include <asm/v850e_uart.h>	25	#include <asm/v850e_uart.h>
26		26
27	#include "mach.h"	27	#include "mach.h"
28		28
29		29
30	/* SRAM and SDRAM are vaguely contiguous (with a big hole in between; see	30	/* SRAM and SDRAM are vaguely contiguous (with a big hole in between; see
31	mach_reserve_bootmem for details); use both as one big area. */	31	mach_reserve_bootmem for details); use both as one big area. */
32	#define RAM_START SRAM_ADDR	32	#define RAM_START SRAM_ADDR
33	#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)	33	#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
34		34
35	/* The bits of this port are connected to an 8-LED bar-graph. */	35	/* The bits of this port are connected to an 8-LED bar-graph. */
36	#define LEDS_PORT 0	36	#define LEDS_PORT 0
37		37
38		38
39	static void anna_led_tick (void);	39	static void anna_led_tick (void);
40		40
41		41
42	void __init mach_early_init (void)	42	void __init mach_early_init (void)
43	{	43	{
44	ANNA_ILBEN = 0;	44	ANNA_ILBEN = 0;
45		45
46	V850E2_CSC(0) = 0x402F;	46	V850E2_CSC(0) = 0x402F;
47	V850E2_CSC(1) = 0x4000;	47	V850E2_CSC(1) = 0x4000;
48	V850E2_BPC = 0;	48	V850E2_BPC = 0;
49	V850E2_BSC = 0xAAAA;	49	V850E2_BSC = 0xAAAA;
50	V850E2_BEC = 0;	50	V850E2_BEC = 0;
51		51
52	#if 0	52	#if 0
53	V850E2_BHC = 0xFFFF; /* icache all memory, dcache all */	53	V850E2_BHC = 0xFFFF; /* icache all memory, dcache all */
54	#else	54	#else
55	V850E2_BHC = 0; /* cache no memory */	55	V850E2_BHC = 0; /* cache no memory */
56	#endif	56	#endif
57	V850E2_BCT(0) = 0xB088;	57	V850E2_BCT(0) = 0xB088;
58	V850E2_BCT(1) = 0x0008;	58	V850E2_BCT(1) = 0x0008;
59	V850E2_DWC(0) = 0x0027;	59	V850E2_DWC(0) = 0x0027;
60	V850E2_DWC(1) = 0;	60	V850E2_DWC(1) = 0;
61	V850E2_BCC = 0x0006;	61	V850E2_BCC = 0x0006;
62	V850E2_ASC = 0;	62	V850E2_ASC = 0;
63	V850E2_LBS = 0x0089;	63	V850E2_LBS = 0x0089;
64	V850E2_SCR(3) = 0x21A9;	64	V850E2_SCR(3) = 0x21A9;
65	V850E2_RFS(3) = 0x8121;	65	V850E2_RFS(3) = 0x8121;
66		66
67	v850e_intc_disable_irqs ();	67	v850e_intc_disable_irqs ();
68	}	68	}
69		69
70	void __init mach_setup (char **cmdline)	70	void __init mach_setup (char **cmdline)
71	{	71	{
72	ANNA_PORT_PM (LEDS_PORT) = 0; /* Make all LED pins output pins. */	72	ANNA_PORT_PM (LEDS_PORT) = 0; /* Make all LED pins output pins. */
73	mach_tick = anna_led_tick;	73	mach_tick = anna_led_tick;
74	}	74	}
75		75
76	void __init mach_get_physical_ram (unsigned long *ram_start,	76	void __init mach_get_physical_ram (unsigned long *ram_start,
77	unsigned long *ram_len)	77	unsigned long *ram_len)
78	{	78	{
79	*ram_start = RAM_START;	79	*ram_start = RAM_START;
80	*ram_len = RAM_END - RAM_START;	80	*ram_len = RAM_END - RAM_START;
81	}	81	}
82		82
83	void __init mach_reserve_bootmem ()	83	void __init mach_reserve_bootmem ()
84	{	84	{
85	/* The space between SRAM and SDRAM is filled with duplicate	85	/* The space between SRAM and SDRAM is filled with duplicate
86	images of SRAM. Prevent the kernel from using them. */	86	images of SRAM. Prevent the kernel from using them. */
87	reserve_bootmem (SRAM_ADDR + SRAM_SIZE,	87	reserve_bootmem (SRAM_ADDR + SRAM_SIZE,
88	SDRAM_ADDR - (SRAM_ADDR + SRAM_SIZE));	88	SDRAM_ADDR - (SRAM_ADDR + SRAM_SIZE));
89	}	89	}
90		90
91	void mach_gettimeofday (struct timespec *tv)	91	void mach_gettimeofday (struct timespec *tv)
92	{	92	{
93	tv->tv_sec = 0;	93	tv->tv_sec = 0;
94	tv->tv_nsec = 0;	94	tv->tv_nsec = 0;
95	}	95	}
96		96
97	void __init mach_sched_init (struct irqaction *timer_action)	97	void __init mach_sched_init (struct irqaction *timer_action)
98	{	98	{
99	/* Start hardware timer. */	99	/* Start hardware timer. */
100	v850e_timer_d_configure (0, HZ);	100	v850e_timer_d_configure (0, HZ);
101	/* Install timer interrupt handler. */	101	/* Install timer interrupt handler. */
102	setup_irq (IRQ_INTCMD(0), timer_action);	102	setup_irq (IRQ_INTCMD(0), timer_action);
103	}	103	}
104		104
105	static struct v850e_intc_irq_init irq_inits[] = {	105	static struct v850e_intc_irq_init irq_inits[] = {
106	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },	106	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
107	{ "PIN", IRQ_INTP(0), IRQ_INTP_NUM, 1, 4 },	107	{ "PIN", IRQ_INTP(0), IRQ_INTP_NUM, 1, 4 },
108	{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },	108	{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
109	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },	109	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
110	{ "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },	110	{ "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },
111	{ "DMXER", IRQ_INTDMXER,1, 1, 2 },	111	{ "DMXER", IRQ_INTDMXER,1, 1, 2 },
112	{ "SRE", IRQ_INTSRE(0), IRQ_INTSRE_NUM, 3, 3 },	112	{ "SRE", IRQ_INTSRE(0), IRQ_INTSRE_NUM, 3, 3 },
113	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 3, 4 },	113	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 3, 4 },
114	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 3, 5 },	114	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 3, 5 },
115	{ 0 }	115	{ 0 }
116	};	116	};
117	#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)	117	#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
118		118
119	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];	119	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
120		120
121	void __init mach_init_irqs (void)	121	void __init mach_init_irqs (void)
122	{	122	{
123	v850e_intc_init_irq_types (irq_inits, hw_itypes);	123	v850e_intc_init_irq_types (irq_inits, hw_itypes);
124	}	124	}
125		125
126	void machine_restart (char *__unused)	126	void machine_restart (char *__unused)
127	{	127	{
128	#ifdef CONFIG_RESET_GUARD	128	#ifdef CONFIG_RESET_GUARD
129	disable_reset_guard ();	129	disable_reset_guard ();
130	#endif	130	#endif
131	asm ("jmp r0"); /* Jump to the reset vector. */	131	asm ("jmp r0"); /* Jump to the reset vector. */
132	}	132	}
133		133
134	void machine_halt (void)	134	void machine_halt (void)
135	{	135	{
136	#ifdef CONFIG_RESET_GUARD	136	#ifdef CONFIG_RESET_GUARD
137	disable_reset_guard ();	137	disable_reset_guard ();
138	#endif	138	#endif
139	local_irq_disable (); /* Ignore all interrupts. */	139	local_irq_disable (); /* Ignore all interrupts. */
140	ANNA_PORT_IO(LEDS_PORT) = 0xAA; /* Note that we halted. */	140	ANNA_PORT_IO(LEDS_PORT) = 0xAA; /* Note that we halted. */
141	for (;;)	141	for (;;)
142	asm ("halt; nop; nop; nop; nop; nop");	142	asm ("halt; nop; nop; nop; nop; nop");
143	}	143	}
144		144
145	void machine_power_off (void)	145	void machine_power_off (void)
146	{	146	{
147	machine_halt ();	147	machine_halt ();
148	}	148	}
149		149
150	/* Called before configuring an on-chip UART. */	150	/* Called before configuring an on-chip UART. */
151	void anna_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)	151	void anna_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
152	{	152	{
153	/* The Anna connects some general-purpose I/O pins on the CPU to	153	/* The Anna connects some general-purpose I/O pins on the CPU to
154	the RTS/CTS lines of UART 1's serial connection. I/O pins P07	154	the RTS/CTS lines of UART 1's serial connection. I/O pins P07
155	and P37 are RTS and CTS respectively. */	155	and P37 are RTS and CTS respectively. */
156	if (chan == 1) {	156	if (chan == 1) {
157	ANNA_PORT_PM(0) &= ~0x80; /* P07 in output mode */	157	ANNA_PORT_PM(0) &= ~0x80; /* P07 in output mode */
158	ANNA_PORT_PM(3) \|= 0x80; /* P37 in input mode */	158	ANNA_PORT_PM(3) \|= 0x80; /* P37 in input mode */
159	}	159	}
160	}	160	}
161		161
162	/* Minimum and maximum bounds for the moving upper LED boundary in the	162	/* Minimum and maximum bounds for the moving upper LED boundary in the
163	clock tick display. We can't use the last bit because it's used for	163	clock tick display. We can't use the last bit because it's used for
164	UART0's CTS output. */	164	UART0's CTS output. */
165	#define MIN_MAX_POS 0	165	#define MIN_MAX_POS 0
166	#define MAX_MAX_POS 6	166	#define MAX_MAX_POS 6
167		167
168	/* There are MAX_MAX_POS^2 - MIN_MAX_POS^2 cycles in the animation, so if	168	/* There are MAX_MAX_POS^2 - MIN_MAX_POS^2 cycles in the animation, so if
169	we pick 6 and 0 as above, we get 49 cycles, which is when divided into	169	we pick 6 and 0 as above, we get 49 cycles, which is when divided into
170	the standard 100 value for HZ, gives us an almost 1s total time. */	170	the standard 100 value for HZ, gives us an almost 1s total time. */
171	#define TICKS_PER_FRAME \	171	#define TICKS_PER_FRAME \
172	(HZ / (MAX_MAX_POS * MAX_MAX_POS - MIN_MAX_POS * MIN_MAX_POS))	172	(HZ / (MAX_MAX_POS * MAX_MAX_POS - MIN_MAX_POS * MIN_MAX_POS))
173		173
174	static void anna_led_tick ()	174	static void anna_led_tick ()
175	{	175	{
176	static unsigned counter = 0;	176	static unsigned counter = 0;
177		177
178	if (++counter == TICKS_PER_FRAME) {	178	if (++counter == TICKS_PER_FRAME) {
179	static int pos = 0, max_pos = MAX_MAX_POS, dir = 1;	179	static int pos = 0, max_pos = MAX_MAX_POS, dir = 1;
180		180
181	if (dir > 0 && pos == max_pos) {	181	if (dir > 0 && pos == max_pos) {
182	dir = -1;	182	dir = -1;
183	if (max_pos == MIN_MAX_POS)	183	if (max_pos == MIN_MAX_POS)
184	max_pos = MAX_MAX_POS;	184	max_pos = MAX_MAX_POS;
185	else	185	else
186	max_pos--;	186	max_pos--;
187	} else {	187	} else {
188	if (dir < 0 && pos == 0)	188	if (dir < 0 && pos == 0)
189	dir = 1;	189	dir = 1;
190		190
191	if (pos + dir <= max_pos) {	191	if (pos + dir <= max_pos) {
192	/* Each bit of port 0 has a LED. */	192	/* Each bit of port 0 has a LED. */
193	clear_bit (pos, &ANNA_PORT_IO(LEDS_PORT));	193	clear_bit (pos, &ANNA_PORT_IO(LEDS_PORT));
194	pos += dir;	194	pos += dir;
195	set_bit (pos, &ANNA_PORT_IO(LEDS_PORT));	195	set_bit (pos, &ANNA_PORT_IO(LEDS_PORT));
196	}	196	}
197	}	197	}
198		198
199	counter = 0;	199	counter = 0;
200	}	200	}
201	}	201	}
202		202

arch/v850/kernel/as85ep1.c

Diff comments View file @ 81d79be

1	/*	1	/*
2	* arch/v850/kernel/as85ep1.c -- AS85EP1 V850E evaluation chip/board	2	* arch/v850/kernel/as85ep1.c -- AS85EP1 V850E evaluation chip/board
3	*	3	*
4	* Copyright (C) 2002,03 NEC Electronics Corporation	4	* Copyright (C) 2002,03 NEC Electronics Corporation
5	* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>	5	* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
6	*	6	*
7	* This file is subject to the terms and conditions of the GNU General	7	* This file is subject to the terms and conditions of the GNU General
8	* Public License. See the file COPYING in the main directory of this	8	* Public License. See the file COPYING in the main directory of this
9	* archive for more details.	9	* archive for more details.
10	*	10	*
11	* Written by Miles Bader <miles@gnu.org>	11	* Written by Miles Bader <miles@gnu.org>
12	*/	12	*/
13		13
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/module.h>	15	#include <linux/module.h>
16	#include <linux/init.h>	16	#include <linux/init.h>
17	#include <linux/bootmem.h>	17	#include <linux/bootmem.h>
18	#include <linux/major.h>	18	#include <linux/major.h>
19	#include <linux/irq.h>	19	#include <linux/irq.h>
20		20
21	#include <asm/machdep.h>	21	#include <asm/machdep.h>
22	#include <asm/atomic.h>	22	#include <asm/atomic.h>
23	#include <asm/page.h>	23	#include <asm/page.h>
24	#include <asm/v850e_timer_d.h>	24	#include <asm/v850e_timer_d.h>
25	#include <asm/v850e_uart.h>	25	#include <asm/v850e_uart.h>
26		26
27	#include "mach.h"	27	#include "mach.h"
28		28
29		29
30	/* SRAM and SDRAM are vaguely contiguous (with a big hole in between; see	30	/* SRAM and SDRAM are vaguely contiguous (with a big hole in between; see
31	mach_reserve_bootmem for details); use both as one big area. */	31	mach_reserve_bootmem for details); use both as one big area. */
32	#define RAM_START SRAM_ADDR	32	#define RAM_START SRAM_ADDR
33	#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)	33	#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
34		34
35	/* The bits of this port are connected to an 8-LED bar-graph. */	35	/* The bits of this port are connected to an 8-LED bar-graph. */
36	#define LEDS_PORT 4	36	#define LEDS_PORT 4
37		37
38		38
39	static void as85ep1_led_tick (void);	39	static void as85ep1_led_tick (void);
40		40
41	extern char _intv_copy_src_start, _intv_copy_src_end;	41	extern char _intv_copy_src_start, _intv_copy_src_end;
42	extern char _intv_copy_dst_start;	42	extern char _intv_copy_dst_start;
43		43
44		44
45	void __init mach_early_init (void)	45	void __init mach_early_init (void)
46	{	46	{
47	#ifndef CONFIG_ROM_KERNEL	47	#ifndef CONFIG_ROM_KERNEL
48	const u32 *src;	48	const u32 *src;
49	register u32 *dst asm ("ep");	49	register u32 *dst asm ("ep");
50	#endif	50	#endif
51		51
52	AS85EP1_CSC(0) = 0x0403;	52	AS85EP1_CSC(0) = 0x0403;
53	AS85EP1_BCT(0) = 0xB8B8;	53	AS85EP1_BCT(0) = 0xB8B8;
54	AS85EP1_DWC(0) = 0x0104;	54	AS85EP1_DWC(0) = 0x0104;
55	AS85EP1_BCC = 0x0012;	55	AS85EP1_BCC = 0x0012;
56	AS85EP1_ASC = 0;	56	AS85EP1_ASC = 0;
57	AS85EP1_LBS = 0x00A9;	57	AS85EP1_LBS = 0x00A9;
58		58
59	AS85EP1_PORT_PMC(6) = 0xFF; /* valid A0,A1,A20-A25 */	59	AS85EP1_PORT_PMC(6) = 0xFF; /* valid A0,A1,A20-A25 */
60	AS85EP1_PORT_PMC(7) = 0x0E; /* valid CS1-CS3 */	60	AS85EP1_PORT_PMC(7) = 0x0E; /* valid CS1-CS3 */
61	AS85EP1_PORT_PMC(9) = 0xFF; /* valid D16-D23 */	61	AS85EP1_PORT_PMC(9) = 0xFF; /* valid D16-D23 */
62	AS85EP1_PORT_PMC(10) = 0xFF; /* valid D24-D31 */	62	AS85EP1_PORT_PMC(10) = 0xFF; /* valid D24-D31 */
63		63
64	AS85EP1_RFS(1) = 0x800c;	64	AS85EP1_RFS(1) = 0x800c;
65	AS85EP1_RFS(3) = 0x800c;	65	AS85EP1_RFS(3) = 0x800c;
66	AS85EP1_SCR(1) = 0x20A9;	66	AS85EP1_SCR(1) = 0x20A9;
67	AS85EP1_SCR(3) = 0x20A9;	67	AS85EP1_SCR(3) = 0x20A9;
68		68
69	#ifndef CONFIG_ROM_KERNEL	69	#ifndef CONFIG_ROM_KERNEL
70	/* The early chip we have is buggy, and writing the interrupt	70	/* The early chip we have is buggy, and writing the interrupt
71	vectors into low RAM may screw up, so for non-ROM kernels, we	71	vectors into low RAM may screw up, so for non-ROM kernels, we
72	only rely on the reset vector being downloaded, and copy the	72	only rely on the reset vector being downloaded, and copy the
73	rest of the interrupt vectors into place here. The specific bug	73	rest of the interrupt vectors into place here. The specific bug
74	is that writing address N, where (N & 0x10) == 0x10, will _also_	74	is that writing address N, where (N & 0x10) == 0x10, will _also_
75	write to address (N - 0x10). We avoid this (effectively) by	75	write to address (N - 0x10). We avoid this (effectively) by
76	writing in 16-byte chunks backwards from the end. */	76	writing in 16-byte chunks backwards from the end. */
77		77
78	AS85EP1_IRAMM = 0x3; /* "write-mode" for the internal instruction memory */	78	AS85EP1_IRAMM = 0x3; /* "write-mode" for the internal instruction memory */
79		79
80	src = (u32 *)(((u32)&_intv_copy_src_end - 1) & ~0xF);	80	src = (u32 *)(((u32)&_intv_copy_src_end - 1) & ~0xF);
81	dst = (u32 *)&_intv_copy_dst_start	81	dst = (u32 *)&_intv_copy_dst_start
82	+ (src - (u32 *)&_intv_copy_src_start);	82	+ (src - (u32 *)&_intv_copy_src_start);
83	do {	83	do {
84	u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];	84	u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];
85	dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;	85	dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
86	dst -= 4;	86	dst -= 4;
87	src -= 4;	87	src -= 4;
88	} while (src > (u32 *)&_intv_copy_src_start);	88	} while (src > (u32 *)&_intv_copy_src_start);
89		89
90	AS85EP1_IRAMM = 0x0; /* "read-mode" for the internal instruction memory */	90	AS85EP1_IRAMM = 0x0; /* "read-mode" for the internal instruction memory */
91	#endif /* !CONFIG_ROM_KERNEL */	91	#endif /* !CONFIG_ROM_KERNEL */
92		92
93	v850e_intc_disable_irqs ();	93	v850e_intc_disable_irqs ();
94	}	94	}
95		95
96	void __init mach_setup (char **cmdline)	96	void __init mach_setup (char **cmdline)
97	{	97	{
98	AS85EP1_PORT_PMC (LEDS_PORT) = 0; /* Make the LEDs port an I/O port. */	98	AS85EP1_PORT_PMC (LEDS_PORT) = 0; /* Make the LEDs port an I/O port. */
99	AS85EP1_PORT_PM (LEDS_PORT) = 0; /* Make all the bits output pins. */	99	AS85EP1_PORT_PM (LEDS_PORT) = 0; /* Make all the bits output pins. */
100	mach_tick = as85ep1_led_tick;	100	mach_tick = as85ep1_led_tick;
101	}	101	}
102		102
103	void __init mach_get_physical_ram (unsigned long *ram_start,	103	void __init mach_get_physical_ram (unsigned long *ram_start,
104	unsigned long *ram_len)	104	unsigned long *ram_len)
105	{	105	{
106	*ram_start = RAM_START;	106	*ram_start = RAM_START;
107	*ram_len = RAM_END - RAM_START;	107	*ram_len = RAM_END - RAM_START;
108	}	108	}
109		109
110	/* Convenience macros. */	110	/* Convenience macros. */
111	#define SRAM_END (SRAM_ADDR + SRAM_SIZE)	111	#define SRAM_END (SRAM_ADDR + SRAM_SIZE)
112	#define SDRAM_END (SDRAM_ADDR + SDRAM_SIZE)	112	#define SDRAM_END (SDRAM_ADDR + SDRAM_SIZE)
113		113
114	void __init mach_reserve_bootmem ()	114	void __init mach_reserve_bootmem ()
115	{	115	{
116	if (SDRAM_ADDR < RAM_END && SDRAM_ADDR > RAM_START)	116	if (SDRAM_ADDR < RAM_END && SDRAM_ADDR > RAM_START)
117	/* We can't use the space between SRAM and SDRAM, so	117	/* We can't use the space between SRAM and SDRAM, so
118	prevent the kernel from trying. */	118	prevent the kernel from trying. */
119	reserve_bootmem (SRAM_END, SDRAM_ADDR - SRAM_END);	119	reserve_bootmem (SRAM_END, SDRAM_ADDR - SRAM_END);
120	}	120	}
121		121
122	void mach_gettimeofday (struct timespec *tv)	122	void mach_gettimeofday (struct timespec *tv)
123	{	123	{
124	tv->tv_sec = 0;	124	tv->tv_sec = 0;
125	tv->tv_nsec = 0;	125	tv->tv_nsec = 0;
126	}	126	}
127		127
128	void __init mach_sched_init (struct irqaction *timer_action)	128	void __init mach_sched_init (struct irqaction *timer_action)
129	{	129	{
130	/* Start hardware timer. */	130	/* Start hardware timer. */
131	v850e_timer_d_configure (0, HZ);	131	v850e_timer_d_configure (0, HZ);
132	/* Install timer interrupt handler. */	132	/* Install timer interrupt handler. */
133	setup_irq (IRQ_INTCMD(0), timer_action);	133	setup_irq (IRQ_INTCMD(0), timer_action);
134	}	134	}
135		135
136	static struct v850e_intc_irq_init irq_inits[] = {	136	static struct v850e_intc_irq_init irq_inits[] = {
137	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },	137	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
138	{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },	138	{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
139	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },	139	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
140	{ "SRE", IRQ_INTSRE(0), IRQ_INTSRE_NUM, 3, 3 },	140	{ "SRE", IRQ_INTSRE(0), IRQ_INTSRE_NUM, 3, 3 },
141	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 3, 4 },	141	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 3, 4 },
142	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 3, 5 },	142	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 3, 5 },
143	{ 0 }	143	{ 0 }
144	};	144	};
145	#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)	145	#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
146		146
147	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];	147	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
148		148
149	void __init mach_init_irqs (void)	149	void __init mach_init_irqs (void)
150	{	150	{
151	v850e_intc_init_irq_types (irq_inits, hw_itypes);	151	v850e_intc_init_irq_types (irq_inits, hw_itypes);
152	}	152	}
153		153
154	void machine_restart (char *__unused)	154	void machine_restart (char *__unused)
155	{	155	{
156	#ifdef CONFIG_RESET_GUARD	156	#ifdef CONFIG_RESET_GUARD
157	disable_reset_guard ();	157	disable_reset_guard ();
158	#endif	158	#endif
159	asm ("jmp r0"); /* Jump to the reset vector. */	159	asm ("jmp r0"); /* Jump to the reset vector. */
160	}	160	}
161		161
162	void machine_halt (void)	162	void machine_halt (void)
163	{	163	{
164	#ifdef CONFIG_RESET_GUARD	164	#ifdef CONFIG_RESET_GUARD
165	disable_reset_guard ();	165	disable_reset_guard ();
166	#endif	166	#endif
167	local_irq_disable (); /* Ignore all interrupts. */	167	local_irq_disable (); /* Ignore all interrupts. */
168	AS85EP1_PORT_IO (LEDS_PORT) = 0xAA; /* Note that we halted. */	168	AS85EP1_PORT_IO (LEDS_PORT) = 0xAA; /* Note that we halted. */
169	for (;;)	169	for (;;)
170	asm ("halt; nop; nop; nop; nop; nop");	170	asm ("halt; nop; nop; nop; nop; nop");
171	}	171	}
172		172
173	void machine_power_off (void)	173	void machine_power_off (void)
174	{	174	{
175	machine_halt ();	175	machine_halt ();
176	}	176	}
177		177
178	/* Called before configuring an on-chip UART. */	178	/* Called before configuring an on-chip UART. */
179	void as85ep1_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)	179	void as85ep1_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
180	{	180	{
181	/* Make the shared uart/port pins be uart pins. */	181	/* Make the shared uart/port pins be uart pins. */
182	AS85EP1_PORT_PMC(3) \|= (0x5 << chan);	182	AS85EP1_PORT_PMC(3) \|= (0x5 << chan);
183		183
184	/* The AS85EP1 connects some general-purpose I/O pins on the CPU to	184	/* The AS85EP1 connects some general-purpose I/O pins on the CPU to
185	the RTS/CTS lines of UART 1's serial connection. I/O pins P53	185	the RTS/CTS lines of UART 1's serial connection. I/O pins P53
186	and P54 are RTS and CTS respectively. */	186	and P54 are RTS and CTS respectively. */
187	if (chan == 1) {	187	if (chan == 1) {
188	/* Put P53 & P54 in I/O port mode. */	188	/* Put P53 & P54 in I/O port mode. */
189	AS85EP1_PORT_PMC(5) &= ~0x18;	189	AS85EP1_PORT_PMC(5) &= ~0x18;
190	/* Make P53 an output, and P54 an input. */	190	/* Make P53 an output, and P54 an input. */
191	AS85EP1_PORT_PM(5) \|= 0x10;	191	AS85EP1_PORT_PM(5) \|= 0x10;
192	}	192	}
193	}	193	}
194		194
195	/* Minimum and maximum bounds for the moving upper LED boundary in the	195	/* Minimum and maximum bounds for the moving upper LED boundary in the
196	clock tick display. */	196	clock tick display. */
197	#define MIN_MAX_POS 0	197	#define MIN_MAX_POS 0
198	#define MAX_MAX_POS 7	198	#define MAX_MAX_POS 7
199		199
200	/* There are MAX_MAX_POS^2 - MIN_MAX_POS^2 cycles in the animation, so if	200	/* There are MAX_MAX_POS^2 - MIN_MAX_POS^2 cycles in the animation, so if
201	we pick 6 and 0 as above, we get 49 cycles, which is when divided into	201	we pick 6 and 0 as above, we get 49 cycles, which is when divided into
202	the standard 100 value for HZ, gives us an almost 1s total time. */	202	the standard 100 value for HZ, gives us an almost 1s total time. */
203	#define TICKS_PER_FRAME \	203	#define TICKS_PER_FRAME \
204	(HZ / (MAX_MAX_POS * MAX_MAX_POS - MIN_MAX_POS * MIN_MAX_POS))	204	(HZ / (MAX_MAX_POS * MAX_MAX_POS - MIN_MAX_POS * MIN_MAX_POS))
205		205
206	static void as85ep1_led_tick ()	206	static void as85ep1_led_tick ()
207	{	207	{
208	static unsigned counter = 0;	208	static unsigned counter = 0;
209		209
210	if (++counter == TICKS_PER_FRAME) {	210	if (++counter == TICKS_PER_FRAME) {
211	static int pos = 0, max_pos = MAX_MAX_POS, dir = 1;	211	static int pos = 0, max_pos = MAX_MAX_POS, dir = 1;
212		212
213	if (dir > 0 && pos == max_pos) {	213	if (dir > 0 && pos == max_pos) {
214	dir = -1;	214	dir = -1;
215	if (max_pos == MIN_MAX_POS)	215	if (max_pos == MIN_MAX_POS)
216	max_pos = MAX_MAX_POS;	216	max_pos = MAX_MAX_POS;
217	else	217	else
218	max_pos--;	218	max_pos--;
219	} else {	219	} else {
220	if (dir < 0 && pos == 0)	220	if (dir < 0 && pos == 0)
221	dir = 1;	221	dir = 1;
222		222
223	if (pos + dir <= max_pos) {	223	if (pos + dir <= max_pos) {
224	/* Each bit of port 0 has a LED. */	224	/* Each bit of port 0 has a LED. */
225	set_bit (pos, &AS85EP1_PORT_IO(LEDS_PORT));	225	set_bit (pos, &AS85EP1_PORT_IO(LEDS_PORT));
226	pos += dir;	226	pos += dir;
227	clear_bit (pos, &AS85EP1_PORT_IO(LEDS_PORT));	227	clear_bit (pos, &AS85EP1_PORT_IO(LEDS_PORT));
228	}	228	}
229	}	229	}
230		230
231	counter = 0;	231	counter = 0;
232	}	232	}
233	}	233	}
234		234

arch/v850/kernel/fpga85e2c.c

Diff comments View file @ 81d79be

1	/*	1	/*
2	* arch/v850/kernel/fpga85e2c.h -- Machine-dependent defs for	2	* arch/v850/kernel/fpga85e2c.h -- Machine-dependent defs for
3	* FPGA implementation of V850E2/NA85E2C	3	* FPGA implementation of V850E2/NA85E2C
4	*	4	*
5	* Copyright (C) 2002,03 NEC Electronics Corporation	5	* Copyright (C) 2002,03 NEC Electronics Corporation
6	* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>	6	* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
7	*	7	*
8	* This file is subject to the terms and conditions of the GNU General	8	* This file is subject to the terms and conditions of the GNU General
9	* Public License. See the file COPYING in the main directory of this	9	* Public License. See the file COPYING in the main directory of this
10	* archive for more details.	10	* archive for more details.
11	*	11	*
12	* Written by Miles Bader <miles@gnu.org>	12	* Written by Miles Bader <miles@gnu.org>
13	*/	13	*/
14		14
15	#include <linux/kernel.h>	15	#include <linux/kernel.h>
16	#include <linux/module.h>	16	#include <linux/module.h>
17	#include <linux/init.h>	17	#include <linux/init.h>
18	#include <linux/mm.h>	18	#include <linux/mm.h>
19	#include <linux/swap.h>	19	#include <linux/swap.h>
20	#include <linux/bootmem.h>	20	#include <linux/bootmem.h>
21	#include <linux/irq.h>	21	#include <linux/irq.h>
22	#include <linux/bitops.h>	22	#include <linux/bitops.h>
23		23
24	#include <asm/atomic.h>	24	#include <asm/atomic.h>
25	#include <asm/page.h>	25	#include <asm/page.h>
26	#include <asm/machdep.h>	26	#include <asm/machdep.h>
27		27
28	#include "mach.h"	28	#include "mach.h"
29		29
30	extern void memcons_setup (void);	30	extern void memcons_setup (void);
31		31
32		32
33	#define REG_DUMP_ADDR 0x220000	33	#define REG_DUMP_ADDR 0x220000
34		34
35		35
36	extern struct irqaction reg_snap_action; /* fwd decl */	36	extern struct irqaction reg_snap_action; /* fwd decl */
37		37
38		38
39	void __init mach_early_init (void)	39	void __init mach_early_init (void)
40	{	40	{
41	int i;	41	int i;
42	const u32 *src;	42	const u32 *src;
43	register u32 *dst asm ("ep");	43	register u32 *dst asm ("ep");
44	extern u32 _intv_end, _intv_load_start;	44	extern u32 _intv_end, _intv_load_start;
45		45
46	/* Set bus sizes: CS0 32-bit, CS1 16-bit, CS7 8-bit,	46	/* Set bus sizes: CS0 32-bit, CS1 16-bit, CS7 8-bit,
47	everything else 32-bit. */	47	everything else 32-bit. */
48	V850E2_BSC = 0x2AA6;	48	V850E2_BSC = 0x2AA6;
49	for (i = 2; i <= 6; i++)	49	for (i = 2; i <= 6; i++)
50	CSDEV(i) = 0; /* 32 bit */	50	CSDEV(i) = 0; /* 32 bit */
51		51
52	/* Ensure that the simulator halts on a panic, instead of going	52	/* Ensure that the simulator halts on a panic, instead of going
53	into an infinite loop inside the panic function. */	53	into an infinite loop inside the panic function. */
54	panic_timeout = -1;	54	panic_timeout = -1;
55		55
56	/* Move the interrupt vectors into their real location. Note that	56	/* Move the interrupt vectors into their real location. Note that
57	any relocations there are relative to the real location, so we	57	any relocations there are relative to the real location, so we
58	don't have to fix anything up. We use a loop instead of calling	58	don't have to fix anything up. We use a loop instead of calling
59	memcpy to keep this a leaf function (to avoid a function	59	memcpy to keep this a leaf function (to avoid a function
60	prologue being generated). */	60	prologue being generated). */
61	dst = 0x10; /* &_intv_start + 0x10. */	61	dst = 0x10; /* &_intv_start + 0x10. */
62	src = &_intv_load_start;	62	src = &_intv_load_start;
63	do {	63	do {
64	u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];	64	u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];
65	u32 t4 = src[4], t5 = src[5], t6 = src[6], t7 = src[7];	65	u32 t4 = src[4], t5 = src[5], t6 = src[6], t7 = src[7];
66	dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;	66	dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
67	dst[4] = t4; dst[5] = t5; dst[6] = t6; dst[7] = t7;	67	dst[4] = t4; dst[5] = t5; dst[6] = t6; dst[7] = t7;
68	dst += 8;	68	dst += 8;
69	src += 8;	69	src += 8;
70	} while (dst < &_intv_end);	70	} while (dst < &_intv_end);
71	}	71	}
72		72
73	void __init mach_setup (char **cmdline)	73	void __init mach_setup (char **cmdline)
74	{	74	{
75	memcons_setup ();	75	memcons_setup ();
76		76
77	/* Setup up NMI0 to copy the registers to a known memory location.	77	/* Setup up NMI0 to copy the registers to a known memory location.
78	The FGPA board has a button that produces NMI0 when pressed, so	78	The FGPA board has a button that produces NMI0 when pressed, so
79	this allows us to push the button, and then look at memory to see	79	this allows us to push the button, and then look at memory to see
80	what's in the registers (there's no other way to easily do so).	80	what's in the registers (there's no other way to easily do so).
81	We have to use `setup_irq' instead of `request_irq' because it's	81	We have to use `setup_irq' instead of `request_irq' because it's
82	still too early to do memory allocation. */	82	still too early to do memory allocation. */
83	setup_irq (IRQ_NMI (0), &reg_snap_action);	83	setup_irq (IRQ_NMI (0), &reg_snap_action);
84	}	84	}
85		85
86	void mach_get_physical_ram (unsigned long ram_start, unsigned long ram_len)	86	void mach_get_physical_ram (unsigned long ram_start, unsigned long ram_len)
87	{	87	{
88	*ram_start = ERAM_ADDR;	88	*ram_start = ERAM_ADDR;
89	*ram_len = ERAM_SIZE;	89	*ram_len = ERAM_SIZE;
90	}	90	}
91		91
92	void __init mach_sched_init (struct irqaction *timer_action)	92	void __init mach_sched_init (struct irqaction *timer_action)
93	{	93	{
94	/* Setup up the timer interrupt. The FPGA peripheral control	94	/* Setup up the timer interrupt. The FPGA peripheral control
95	registers _only_ work with single-bit writes (set1/clr1)! */	95	registers _only_ work with single-bit writes (set1/clr1)! */
96	__clear_bit (RPU_GTMC_CE_BIT, &RPU_GTMC);	96	__clear_bit (RPU_GTMC_CE_BIT, &RPU_GTMC);
97	__clear_bit (RPU_GTMC_CLK_BIT, &RPU_GTMC);	97	__clear_bit (RPU_GTMC_CLK_BIT, &RPU_GTMC);
98	__set_bit (RPU_GTMC_CE_BIT, &RPU_GTMC);	98	__set_bit (RPU_GTMC_CE_BIT, &RPU_GTMC);
99		99
100	/* We use the first RPU interrupt, which occurs every 8.192ms. */	100	/* We use the first RPU interrupt, which occurs every 8.192ms. */
101	setup_irq (IRQ_RPU (0), timer_action);	101	setup_irq (IRQ_RPU (0), timer_action);
102	}	102	}
103		103
104		104
105	void mach_gettimeofday (struct timespec *tv)	105	void mach_gettimeofday (struct timespec *tv)
106	{	106	{
107	tv->tv_sec = 0;	107	tv->tv_sec = 0;
108	tv->tv_nsec = 0;	108	tv->tv_nsec = 0;
109	}	109	}
110		110
111	void machine_halt (void) __attribute__ ((noreturn));	111	void machine_halt (void) __attribute__ ((noreturn));
112	void machine_halt (void)	112	void machine_halt (void)
113	{	113	{
114	for (;;) {	114	for (;;) {
115	DWC(0) = 0x7777;	115	DWC(0) = 0x7777;
116	DWC(1) = 0x7777;	116	DWC(1) = 0x7777;
117	ASC = 0xffff;	117	ASC = 0xffff;
118	FLGREG(0) = 1; /* Halt immediately. */	118	FLGREG(0) = 1; /* Halt immediately. */
119	asm ("di; halt; nop; nop; nop; nop; nop");	119	asm ("di; halt; nop; nop; nop; nop; nop");
120	}	120	}
121	}	121	}
122		122
123	void machine_restart (char *__unused)	123	void machine_restart (char *__unused)
124	{	124	{
125	machine_halt ();	125	machine_halt ();
126	}	126	}
127		127
128	void machine_power_off (void)	128	void machine_power_off (void)
129	{	129	{
130	machine_halt ();	130	machine_halt ();
131	}	131	}
132		132
133		133
134	/* Interrupts */	134	/* Interrupts */
135		135
136	struct v850e_intc_irq_init irq_inits[] = {	136	struct v850e_intc_irq_init irq_inits[] = {
137	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },	137	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
138	{ "RPU", IRQ_RPU(0), IRQ_RPU_NUM, 1, 6 },	138	{ "RPU", IRQ_RPU(0), IRQ_RPU_NUM, 1, 6 },
139	{ 0 }	139	{ 0 }
140	};	140	};
141	#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)	141	#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
142		142
143	struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];	143	struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
144		144
145	/* Initialize interrupts. */	145	/* Initialize interrupts. */
146	void __init mach_init_irqs (void)	146	void __init mach_init_irqs (void)
147	{	147	{
148	v850e_intc_init_irq_types (irq_inits, hw_itypes);	148	v850e_intc_init_irq_types (irq_inits, hw_itypes);
149	}	149	}
150		150
151		151
152	/* An interrupt handler that copies the registers to a known memory location,	152	/* An interrupt handler that copies the registers to a known memory location,
153	for debugging purposes. */	153	for debugging purposes. */
154		154
155	static void make_reg_snap (int irq, void dummy, struct pt_regs regs)	155	static void make_reg_snap (int irq, void dummy, struct pt_regs regs)
156	{	156	{
157	((unsigned )REG_DUMP_ADDR)++;	157	((unsigned )REG_DUMP_ADDR)++;
158	((struct pt_regs )(REG_DUMP_ADDR + sizeof (unsigned))) = *regs;	158	((struct pt_regs )(REG_DUMP_ADDR + sizeof (unsigned))) = *regs;
159	}	159	}
160		160
161	static int reg_snap_dev_id;	161	static int reg_snap_dev_id;
162	static struct irqaction reg_snap_action = {	162	static struct irqaction reg_snap_action = {
163	make_reg_snap, 0, CPU_MASK_NONE, "reg_snap", &reg_snap_dev_id, 0	163	make_reg_snap, 0, CPU_MASK_NONE, "reg_snap", &reg_snap_dev_id, 0
164	};	164	};
165		165

arch/v850/kernel/gbus_int.c

Diff comments View file @ 81d79be

 /*
  * arch/v850/kernel/gbus_int.c -- Midas labs GBUS interrupt support
  *
  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
  * archive for more details.
  *
  * Written by Miles Bader <miles@gnu.org>
  */
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/signal.h>
+#include <linux/kernel.h>
 #include <asm/machdep.h>
 /* The number of shared GINT interrupts. */
 #define NUM_GINTS   	4
 /* For each GINT interrupt, how many GBUS interrupts are using it.  */
 static unsigned gint_num_active_irqs[NUM_GINTS] = { 0 };
 /* A table of GINTn interrupts we actually use.
    Note that we don't use GINT0 because all the boards we support treat it
    specially.  */
 struct used_gint {
 	unsigned gint;
 	unsigned priority;
 } used_gint[] = {
 	{ 1, GBUS_INT_PRIORITY_HIGH },
 	{ 3, GBUS_INT_PRIORITY_LOW }
 };
-#define NUM_USED_GINTS	(sizeof used_gint / sizeof used_gint[0])
+#define NUM_USED_GINTS ARRAY_SIZE(used_gint)
 /* A table of which GINT is used by each GBUS interrupts (they are
    assigned based on priority).  */
 static unsigned char gbus_int_gint[IRQ_GBUS_INT_NUM];
 /* Interrupt enabling/disabling.  */
 /* Enable interrupt handling for interrupt IRQ.  */
 void gbus_int_enable_irq (unsigned irq)
 {
 	unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 	GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
 		|= GBUS_INT_IRQ_MASK (irq);
 }
 /* Disable interrupt handling for interrupt IRQ.  Note that any
    interrupts received while disabled will be delivered once the
    interrupt is enabled again, unless they are explicitly cleared using
    `gbus_int_clear_pending_irq'.  */
 void gbus_int_disable_irq (unsigned irq)
 {
 	unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 	GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
 		&= ~GBUS_INT_IRQ_MASK (irq);
 }
 /* Return true if interrupt handling for interrupt IRQ is enabled.  */
 int gbus_int_irq_enabled (unsigned irq)
 {
 	unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 	return (GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
 		& GBUS_INT_IRQ_MASK(irq));
 }
 /* Disable all GBUS irqs.  */
 void gbus_int_disable_irqs ()
 {
 	unsigned w, n;
 	for (w = 0; w < GBUS_INT_NUM_WORDS; w++)
 		for (n = 0; n < IRQ_GINT_NUM; n++)
 			GBUS_INT_ENABLE (w, n) = 0;
 }
 /* Clear any pending interrupts for IRQ.  */
 void gbus_int_clear_pending_irq (unsigned irq)
 {
 	GBUS_INT_CLEAR (GBUS_INT_IRQ_WORD(irq)) = GBUS_INT_IRQ_MASK (irq);
 }
 /* Return true if interrupt IRQ is pending (but disabled).  */
 int gbus_int_irq_pending (unsigned irq)
 {
 	return (GBUS_INT_STATUS (GBUS_INT_IRQ_WORD(irq))
 		& GBUS_INT_IRQ_MASK(irq));
 }
 /* Delegating interrupts.  */
 /* Handle a shared GINT interrupt by passing to the appropriate GBUS
    interrupt handler.  */
 static irqreturn_t gbus_int_handle_irq (int irq, void *dev_id,
 					struct pt_regs *regs)
 {
 	unsigned w;
 	irqreturn_t rval = IRQ_NONE;
 	unsigned gint = irq - IRQ_GINT (0);
 	for (w = 0; w < GBUS_INT_NUM_WORDS; w++) {
 		unsigned status = GBUS_INT_STATUS (w);
 		unsigned enable = GBUS_INT_ENABLE (w, gint);
 		/* Only pay attention to enabled interrupts.  */
 		status &= enable;
 		if (status) {
 			irq = IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
 			do {
 				/* There's an active interrupt in word
 				   W, find out which one, and call its
 				   handler.  */
 				while (! (status & 0x1)) {
 					irq++;
 					status >>= 1;
 				}
 				status &= ~0x1;
 				/* Recursively call handle_irq to handle it. */
 				handle_irq (irq, regs);
 				rval = IRQ_HANDLED;
 			} while (status);
 		}
 	}
 	/* Toggle the `all enable' bit back and forth, which should cause
 	   another edge transition if there are any other interrupts
 	   still pending, and so result in another CPU interrupt.  */
 	GBUS_INT_ENABLE (0, gint) &= ~0x1;
 	GBUS_INT_ENABLE (0, gint) |=  0x1;
 	return rval;
 }
 /* Initialize GBUS interrupt sources.  */
 static void irq_nop (unsigned irq) { }
 static unsigned gbus_int_startup_irq (unsigned irq)
 {
 	unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 	if (gint_num_active_irqs[gint] == 0) {
 		/* First enable the CPU interrupt.  */
 		int rval =
 			request_irq (IRQ_GINT(gint), gbus_int_handle_irq,
 				     IRQF_DISABLED,
 				     "gbus_int_handler",
 				     &gint_num_active_irqs[gint]);
 		if (rval != 0)
 			return rval;
 	}
 	gint_num_active_irqs[gint]++;
 	gbus_int_clear_pending_irq (irq);
 	gbus_int_enable_irq (irq);
 	return 0;
 }
 static void gbus_int_shutdown_irq (unsigned irq)
 {
 	unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
 	gbus_int_disable_irq (irq);
 	if (--gint_num_active_irqs[gint] == 0)
 		/* Disable the CPU interrupt.  */
 		free_irq (IRQ_GINT(gint), &gint_num_active_irqs[gint]);
 }
 /* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
    INITS (which is terminated by an entry with the name field == 0).  */
 void __init gbus_int_init_irq_types (struct gbus_int_irq_init *inits,
 				     struct hw_interrupt_type *hw_irq_types)
 {
 	struct gbus_int_irq_init *init;
 	for (init = inits; init->name; init++) {
 		unsigned i;
 		struct hw_interrupt_type *hwit = hw_irq_types++;
 		hwit->typename = init->name;
 		hwit->startup  = gbus_int_startup_irq;
 		hwit->shutdown = gbus_int_shutdown_irq;
 		hwit->enable   = gbus_int_enable_irq;
 		hwit->disable  = gbus_int_disable_irq;
 		hwit->ack      = irq_nop;
 		hwit->end      = irq_nop;
 		/* Initialize kernel IRQ infrastructure for this interrupt.  */
 		init_irq_handlers(init->base, init->num, init->interval, hwit);
 		/* Set the interrupt priorities.  */
 		for (i = 0; i < init->num; i++) {
 			unsigned j;
 			for (j = 0; j < NUM_USED_GINTS; j++)
 				if (used_gint[j].priority > init->priority)
 					break;
 			/* Wherever we stopped looking is one past the
 			   GINT we want. */
 			gbus_int_gint[init->base + i * init->interval
 				      - GBUS_INT_BASE_IRQ]
 				= used_gint[j > 0 ? j - 1 : 0].gint;
 		}
 	}
 }
 /* Initialize IRQS.  */
 /* Chip interrupts (GINTn) shared among GBUS interrupts.  */
 static struct hw_interrupt_type gint_hw_itypes[NUM_USED_GINTS];
 /* GBUS interrupts themselves.  */
 struct gbus_int_irq_init gbus_irq_inits[] __initdata = {
 	/* First set defaults.  */
 	{ "GBUS_INT", IRQ_GBUS_INT(0), IRQ_GBUS_INT_NUM, 1, 6},
 	{ 0 }
 };
-#define NUM_GBUS_IRQ_INITS  \
+#define NUM_GBUS_IRQ_INITS (ARRAY_SIZE(gbus_irq_inits) - 1)
-   ((sizeof gbus_irq_inits / sizeof gbus_irq_inits[0]) - 1)
 static struct hw_interrupt_type gbus_hw_itypes[NUM_GBUS_IRQ_INITS];
 /* Initialize GBUS interrupts.  */
 void __init gbus_int_init_irqs (void)
 {
 	unsigned i;
 	/* First initialize the shared gint interrupts.  */
 	for (i = 0; i < NUM_USED_GINTS; i++) {
 		unsigned gint = used_gint[i].gint;
 		struct v850e_intc_irq_init gint_irq_init[2];
 		/* We initialize one GINT interrupt at a time.  */
 		gint_irq_init[0].name = "GINT";
 		gint_irq_init[0].base = IRQ_GINT (gint);
 		gint_irq_init[0].num = 1;
 		gint_irq_init[0].interval = 1;
 		gint_irq_init[0].priority = used_gint[i].priority;
 		gint_irq_init[1].name = 0; /* Terminate the vector.  */
 		v850e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
 	}
 	/* Then the GBUS interrupts.  */
 	gbus_int_disable_irqs ();
 	gbus_int_init_irq_types (gbus_irq_inits, gbus_hw_itypes);
 	/* Turn on the `all enable' bits, which are ANDed with
 	   individual interrupt enable bits; we only want to bother with
 	   the latter.  They are the first bit in the first word of each
 	   interrupt-enable area.  */
 	for (i = 0; i < NUM_USED_GINTS; i++)
 		GBUS_INT_ENABLE (0, used_gint[i].gint) = 0x1;
 }

arch/v850/kernel/ma.c

Diff comments View file @ 81d79be

arch/v850/kernel/me2.c

Diff comments View file @ 81d79be

1	/*	1	/*
2	* arch/v850/kernel/me2.c -- V850E/ME2 chip-specific support	2	* arch/v850/kernel/me2.c -- V850E/ME2 chip-specific support
3	*	3	*
4	* Copyright (C) 2003 NEC Corporation	4	* Copyright (C) 2003 NEC Corporation
5	* Copyright (C) 2003 Miles Bader <miles@gnu.org>	5	* Copyright (C) 2003 Miles Bader <miles@gnu.org>
6	*	6	*
7	* This file is subject to the terms and conditions of the GNU General	7	* This file is subject to the terms and conditions of the GNU General
8	* Public License. See the file COPYING in the main directory of this	8	* Public License. See the file COPYING in the main directory of this
9	* archive for more details.	9	* archive for more details.
10	*	10	*
11	* Written by Miles Bader <miles@gnu.org>	11	* Written by Miles Bader <miles@gnu.org>
12	*/	12	*/
13		13
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/init.h>	15	#include <linux/init.h>
16	#include <linux/mm.h>	16	#include <linux/mm.h>
17	#include <linux/swap.h>	17	#include <linux/swap.h>
18	#include <linux/bootmem.h>	18	#include <linux/bootmem.h>
19	#include <linux/irq.h>	19	#include <linux/irq.h>
20		20
21	#include <asm/atomic.h>	21	#include <asm/atomic.h>
22	#include <asm/page.h>	22	#include <asm/page.h>
23	#include <asm/machdep.h>	23	#include <asm/machdep.h>
24	#include <asm/v850e_timer_d.h>	24	#include <asm/v850e_timer_d.h>
25		25
26	#include "mach.h"	26	#include "mach.h"
27		27
28	void __init mach_sched_init (struct irqaction *timer_action)	28	void __init mach_sched_init (struct irqaction *timer_action)
29	{	29	{
30	/* Start hardware timer. */	30	/* Start hardware timer. */
31	v850e_timer_d_configure (0, HZ);	31	v850e_timer_d_configure (0, HZ);
32	/* Install timer interrupt handler. */	32	/* Install timer interrupt handler. */
33	setup_irq (IRQ_INTCMD(0), timer_action);	33	setup_irq (IRQ_INTCMD(0), timer_action);
34	}	34	}
35		35
36	static struct v850e_intc_irq_init irq_inits[] = {	36	static struct v850e_intc_irq_init irq_inits[] = {
37	{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },	37	{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },
38	{ "INTP", IRQ_INTP(0), IRQ_INTP_NUM, 1, 5 },	38	{ "INTP", IRQ_INTP(0), IRQ_INTP_NUM, 1, 5 },
39	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 3 },	39	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 3 },
40	{ "UBTIRE", IRQ_INTUBTIRE(0), IRQ_INTUBTIRE_NUM, 5, 4 },	40	{ "UBTIRE", IRQ_INTUBTIRE(0), IRQ_INTUBTIRE_NUM, 5, 4 },
41	{ "UBTIR", IRQ_INTUBTIR(0), IRQ_INTUBTIR_NUM, 5, 4 },	41	{ "UBTIR", IRQ_INTUBTIR(0), IRQ_INTUBTIR_NUM, 5, 4 },
42	{ "UBTIT", IRQ_INTUBTIT(0), IRQ_INTUBTIT_NUM, 5, 4 },	42	{ "UBTIT", IRQ_INTUBTIT(0), IRQ_INTUBTIT_NUM, 5, 4 },
43	{ "UBTIF", IRQ_INTUBTIF(0), IRQ_INTUBTIF_NUM, 5, 4 },	43	{ "UBTIF", IRQ_INTUBTIF(0), IRQ_INTUBTIF_NUM, 5, 4 },
44	{ "UBTITO", IRQ_INTUBTITO(0), IRQ_INTUBTITO_NUM, 5, 4 },	44	{ "UBTITO", IRQ_INTUBTITO(0), IRQ_INTUBTITO_NUM, 5, 4 },
45	{ 0 }	45	{ 0 }
46	};	46	};
47	#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)	47	#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
48		48
49	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];	49	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
50		50
51	/* Initialize V850E/ME2 chip interrupts. */	51	/* Initialize V850E/ME2 chip interrupts. */
52	void __init me2_init_irqs (void)	52	void __init me2_init_irqs (void)
53	{	53	{
54	v850e_intc_init_irq_types (irq_inits, hw_itypes);	54	v850e_intc_init_irq_types (irq_inits, hw_itypes);
55	}	55	}
56		56
57	/* Called before configuring an on-chip UART. */	57	/* Called before configuring an on-chip UART. */
58	void me2_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)	58	void me2_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
59	{	59	{
60	if (chan == 0) {	60	if (chan == 0) {
61	/* Specify that the relevent pins on the chip should do	61	/* Specify that the relevent pins on the chip should do
62	serial I/O, not direct I/O. */	62	serial I/O, not direct I/O. */
63	ME2_PORT1_PMC \|= 0xC;	63	ME2_PORT1_PMC \|= 0xC;
64	/* Specify that we're using the UART, not the CSI device. */	64	/* Specify that we're using the UART, not the CSI device. */
65	ME2_PORT1_PFC \|= 0xC;	65	ME2_PORT1_PFC \|= 0xC;
66	} else if (chan == 1) {	66	} else if (chan == 1) {
67	/* Specify that the relevent pins on the chip should do	67	/* Specify that the relevent pins on the chip should do
68	serial I/O, not direct I/O. */	68	serial I/O, not direct I/O. */
69	ME2_PORT2_PMC \|= 0x6;	69	ME2_PORT2_PMC \|= 0x6;
70	/* Specify that we're using the UART, not the CSI device. */	70	/* Specify that we're using the UART, not the CSI device. */
71	ME2_PORT2_PFC \|= 0x6;	71	ME2_PORT2_PFC \|= 0x6;
72	}	72	}
73	}	73	}
74		74

arch/v850/kernel/rte_cb.c

Diff comments View file @ 81d79be

 /*
  * include/asm-v850/rte_cb.c -- Midas lab RTE-CB series of evaluation boards
  *
  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
  * archive for more details.
  *
  * Written by Miles Bader <miles@gnu.org>
  */
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/fs.h>
 #include <linux/module.h>
+#include <linux/kernel.h>
 #include <asm/machdep.h>
 #include <asm/v850e_uart.h>
 #include "mach.h"
 static void led_tick (void);
 /* LED access routines.  */
 extern unsigned read_leds (int pos, char *buf, int len);
 extern unsigned write_leds (int pos, const char *buf, int len);
 #ifdef CONFIG_RTE_CB_MULTI
 extern void multi_init (void);
 #endif
 void __init rte_cb_early_init (void)
 {
 	v850e_intc_disable_irqs ();
 #ifdef CONFIG_RTE_CB_MULTI
 	multi_init ();
 #endif
 }
 void __init mach_setup (char **cmdline)
 {
 #ifdef CONFIG_RTE_MB_A_PCI
 	/* Probe for Mother-A, and print a message if we find it.  */
 	*(volatile unsigned long *)MB_A_SRAM_ADDR = 0xDEADBEEF;
 	if (*(volatile unsigned long *)MB_A_SRAM_ADDR == 0xDEADBEEF) {
 		*(volatile unsigned long *)MB_A_SRAM_ADDR = 0x12345678;
 		if (*(volatile unsigned long *)MB_A_SRAM_ADDR == 0x12345678)
 			printk (KERN_INFO
 				"          NEC SolutionGear/Midas lab"
 				" RTE-MOTHER-A motherboard\n");
 	}
 #endif /* CONFIG_RTE_MB_A_PCI */
 	mach_tick = led_tick;
 }
 void machine_restart (char *__unused)
 {
 #ifdef CONFIG_RESET_GUARD
 	disable_reset_guard ();
 #endif
 	asm ("jmp r0"); /* Jump to the reset vector.  */
 }
 /* This says `HALt.' in LEDese.  */
 static unsigned char halt_leds_msg[] = { 0x76, 0x77, 0x38, 0xF8 };
 void machine_halt (void)
 {
 #ifdef CONFIG_RESET_GUARD
 	disable_reset_guard ();
 #endif
 	/* Ignore all interrupts.  */
 	local_irq_disable ();
 	/* Write a little message.  */
 	write_leds (0, halt_leds_msg, sizeof halt_leds_msg);
 	/* Really halt.  */
 	for (;;)
 		asm ("halt; nop; nop; nop; nop; nop");
 }
 void machine_power_off (void)
 {
 	machine_halt ();
 }
 /* Animated LED display for timer tick.  */
 #define TICK_UPD_FREQ	6
 static int tick_frames[][10] = {
 	{ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, -1 },
 	{ 0x63, 0x5c, -1 },
 	{ 0x5c, 0x00, -1 },
 	{ 0x63, 0x00, -1 },
 	{ -1 }
 };
 static void led_tick ()
 {
 	static unsigned counter = 0;
 	if (++counter == (HZ / TICK_UPD_FREQ)) {
 		/* Which frame we're currently displaying for each digit.  */
 		static unsigned frame_nums[LED_NUM_DIGITS] = { 0 };
 		/* Display image.  */
 		static unsigned char image[LED_NUM_DIGITS] = { 0 };
 		unsigned char prev_image[LED_NUM_DIGITS];
 		int write_to_leds = 1; /* true if we should actually display */
 		int digit;
 		/* We check to see if the physical LEDs contains what we last
 		   wrote to them; if not, we suppress display (this is so that
 		   users can write to the LEDs, and not have their output
 		   overwritten).  As a special case, we start writing again if
 		   all the LEDs are blank, or our display image is all zeros
 		   (indicating that this is the initial update, when the actual
 		   LEDs might contain random data).  */
 		read_leds (0, prev_image, LED_NUM_DIGITS);
 		for (digit = 0; digit < LED_NUM_DIGITS; digit++)
 			if (image[digit] != prev_image[digit]
 			    && image[digit] && prev_image[digit])
 			{
 				write_to_leds = 0;
 				break;
 			}
 		/* Update display image.  */
 		for (digit = 0;
 		     digit < LED_NUM_DIGITS && tick_frames[digit][0] >= 0;
 		     digit++)
 		{
 			int frame = tick_frames[digit][frame_nums[digit]];
 			if (frame < 0) {
 				image[digit] = tick_frames[digit][0];
 				frame_nums[digit] = 1;
 			} else {
 				image[digit] = frame;
 				frame_nums[digit]++;
 				break;
 			}
 		}
 		if (write_to_leds)
 			/* Write the display image to the physical LEDs.  */
 			write_leds (0, image, LED_NUM_DIGITS);
 		counter = 0;
 	}
 }
 /* Mother-A interrupts.  */
 #ifdef CONFIG_RTE_GBUS_INT
 #define L GBUS_INT_PRIORITY_LOW
 #define M GBUS_INT_PRIORITY_MEDIUM
 #define H GBUS_INT_PRIORITY_HIGH
 static struct gbus_int_irq_init gbus_irq_inits[] = {
 #ifdef CONFIG_RTE_MB_A_PCI
 	{ "MB_A_LAN",	IRQ_MB_A_LAN,		1,		     1, L },
 	{ "MB_A_PCI1",	IRQ_MB_A_PCI1(0),	IRQ_MB_A_PCI1_NUM,   1, L },
 	{ "MB_A_PCI2",	IRQ_MB_A_PCI2(0),	IRQ_MB_A_PCI2_NUM,   1, L },
 	{ "MB_A_EXT",	IRQ_MB_A_EXT(0),	IRQ_MB_A_EXT_NUM,    1, L },
 	{ "MB_A_USB_OC",IRQ_MB_A_USB_OC(0),	IRQ_MB_A_USB_OC_NUM, 1, L },
 	{ "MB_A_PCMCIA_OC",IRQ_MB_A_PCMCIA_OC,	1,		     1, L },
 #endif
 	{ 0 }
 };
-#define NUM_GBUS_IRQ_INITS  \
+#define NUM_GBUS_IRQ_INITS (ARRAY_SIZE(gbus_irq_inits) - 1)
-   ((sizeof gbus_irq_inits / sizeof gbus_irq_inits[0]) - 1)
 static struct hw_interrupt_type gbus_hw_itypes[NUM_GBUS_IRQ_INITS];
 #endif /* CONFIG_RTE_GBUS_INT */
 void __init rte_cb_init_irqs (void)
 {
 #ifdef CONFIG_RTE_GBUS_INT
 	gbus_int_init_irqs ();
 	gbus_int_init_irq_types (gbus_irq_inits, gbus_hw_itypes);
 #endif /* CONFIG_RTE_GBUS_INT */
 }

arch/v850/kernel/rte_mb_a_pci.c

Diff comments View file @ 81d79be

 /*
  * arch/v850/kernel/mb_a_pci.c -- PCI support for Midas lab RTE-MOTHER-A board
  *
  *  Copyright (C) 2001,02,03,05  NEC Electronics Corporation
  *  Copyright (C) 2001,02,03,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
  * archive for more details.
  *
  * Written by Miles Bader <miles@gnu.org>
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/pci.h>
 #include <asm/machdep.h>
 /* __nomods_init is like __devinit, but is a no-op when modules are enabled.
    This is used by some routines that can be called either during boot
    or by a module.  */
 #ifdef CONFIG_MODULES
 #define __nomods_init /*nothing*/
 #else
 #define __nomods_init __devinit
 #endif
 /* PCI devices on the Mother-A board can only do DMA to/from the MB SRAM
    (the RTE-V850E/MA1-CB cpu board doesn't support PCI access to
    CPU-board memory), and since linux DMA buffers are allocated in
    normal kernel memory, we basically have to copy DMA blocks around
    (this is like a `bounce buffer').  When a DMA block is `mapped', we
    allocate an identically sized block in MB SRAM, and if we're doing
    output to the device, copy the CPU-memory block to the MB-SRAM block.
    When an active block is `unmapped', we will copy the block back to
    CPU memory if necessary, and then deallocate the MB SRAM block.
    Ack.  */
 /* Where the motherboard SRAM is in the PCI-bus address space (the
    first 512K of it is also mapped at PCI address 0).  */
 #define PCI_MB_SRAM_ADDR 0x800000
 /* Convert CPU-view MB SRAM address to/from PCI-view addresses of the
    same memory.  */
 #define MB_SRAM_TO_PCI(mb_sram_addr) \
    ((dma_addr_t)mb_sram_addr - MB_A_SRAM_ADDR + PCI_MB_SRAM_ADDR)
 #define PCI_TO_MB_SRAM(pci_addr)     \
    (void *)(pci_addr - PCI_MB_SRAM_ADDR + MB_A_SRAM_ADDR)
 static void pcibios_assign_resources (void);
 struct mb_pci_dev_irq {
 	unsigned dev;		/* PCI device number */
 	unsigned irq_base;	/* First IRQ  */
 	unsigned query_pin;	/* True if we should read the device's
 				   Interrupt Pin info, and allocate
 				   interrupt IRQ_BASE + PIN.  */
 };
 /* PCI interrupts are mapped statically to GBUS interrupts.  */
 static struct mb_pci_dev_irq mb_pci_dev_irqs[] = {
 	/* Motherboard SB82558 ethernet controller */
 	{ 10,	IRQ_MB_A_LAN,		0 },
 	/* PCI slot 1 */
 	{ 8, 	IRQ_MB_A_PCI1(0),	1 },
 	/* PCI slot 2 */
 	{ 9, 	IRQ_MB_A_PCI2(0),	1 }
 };
-#define NUM_MB_PCI_DEV_IRQS \
+#define NUM_MB_PCI_DEV_IRQS ARRAY_SIZE(mb_pci_dev_irqs)
-  (sizeof mb_pci_dev_irqs / sizeof mb_pci_dev_irqs[0])
 /* PCI configuration primitives.  */
 #define CONFIG_DMCFGA(bus, devfn, offs)					\
    (0x80000000								\
     | ((offs) & ~0x3)							\
     | ((devfn) << 8)							\
     | ((bus)->number << 16))
 static int
 mb_pci_read (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 *rval)
 {
 	u32 addr;
 	int flags;
 	local_irq_save (flags);
 	MB_A_PCI_PCICR = 0x7;
 	MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs);
 	addr = MB_A_PCI_IO_ADDR + (offs & 0x3);
 	switch (size) {
 	case 1:	*rval = *(volatile  u8 *)addr; break;
 	case 2:	*rval = *(volatile u16 *)addr; break;
 	case 4:	*rval = *(volatile u32 *)addr; break;
 	}
         if (MB_A_PCI_PCISR & 0x2000) {
 		MB_A_PCI_PCISR = 0x2000;
 		*rval = ~0;
         }
 	MB_A_PCI_DMCFGA = 0;
 	local_irq_restore (flags);
 	return PCIBIOS_SUCCESSFUL;
 }
 static int
 mb_pci_write (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 val)
 {
 	u32 addr;
 	int flags;
 	local_irq_save (flags);
 	MB_A_PCI_PCICR = 0x7;
 	MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs);
 	addr = MB_A_PCI_IO_ADDR + (offs & 0x3);
 	switch (size) {
 	case 1: *(volatile  u8 *)addr = val; break;
 	case 2: *(volatile u16 *)addr = val; break;
 	case 4: *(volatile u32 *)addr = val; break;
 	}
         if (MB_A_PCI_PCISR & 0x2000)
 		MB_A_PCI_PCISR = 0x2000;
 	MB_A_PCI_DMCFGA = 0;
 	local_irq_restore (flags);
 	return PCIBIOS_SUCCESSFUL;
 }
 static struct pci_ops mb_pci_config_ops = {
 	.read	= mb_pci_read,
 	.write	= mb_pci_write,
 };
 /* PCI Initialization.  */
 static struct pci_bus *mb_pci_bus = 0;
 /* Do initial PCI setup.  */
 static int __devinit pcibios_init (void)
 {
 	u32 id = MB_A_PCI_PCIHIDR;
 	u16 vendor = id & 0xFFFF;
 	u16 device = (id >> 16) & 0xFFFF;
 	if (vendor == PCI_VENDOR_ID_PLX && device == PCI_DEVICE_ID_PLX_9080) {
 		printk (KERN_INFO
 			"PCI: PLX Technology PCI9080 HOST/PCI bridge\n");
 		MB_A_PCI_PCICR = 0x147;
 		MB_A_PCI_PCIBAR0 = 0x007FFF00;
 		MB_A_PCI_PCIBAR1 = 0x0000FF00;
 		MB_A_PCI_PCIBAR2 = 0x00800000;
 		MB_A_PCI_PCILTR = 0x20;
 		MB_A_PCI_PCIPBAM |= 0x3;
 		MB_A_PCI_PCISR =  ~0; /* Clear errors.  */
 		/* Reprogram the motherboard's IO/config address space,
 		   as we don't support the GCS7 address space that the
 		   default uses.  */
 		/* Significant address bits used for decoding PCI GCS5 space
 		   accessess.  */
 		MB_A_PCI_DMRR = ~(MB_A_PCI_MEM_SIZE - 1);
 		/* I don't understand this, but the SolutionGear example code
 		   uses such an offset, and it doesn't work without it.  XXX */
 #if GCS5_SIZE == 0x00800000
 #define GCS5_CFG_OFFS 0x00800000
 #else
 #define GCS5_CFG_OFFS 0
 #endif
 		/* Address bit values for matching.  Note that we have to give
 		   the address from the motherboard's point of view, which is
 		   different than the CPU's.  */
 		/* PCI memory space.  */
 		MB_A_PCI_DMLBAM = GCS5_CFG_OFFS + 0x0;
 		/* PCI I/O space.  */
 		MB_A_PCI_DMLBAI =
 			GCS5_CFG_OFFS + (MB_A_PCI_IO_ADDR - GCS5_ADDR);
 		mb_pci_bus = pci_scan_bus (0, &mb_pci_config_ops, 0);
 		pcibios_assign_resources ();
 	} else
 		printk (KERN_ERR "PCI: HOST/PCI bridge not found\n");
 	return 0;
 }
 subsys_initcall (pcibios_init);
 char __devinit *pcibios_setup (char *option)
 {
 	/* Don't handle any options. */
 	return option;
 }
 int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask)
 {
 	u16 cmd, old_cmd;
 	int idx;
 	struct resource *r;
 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
 	old_cmd = cmd;
 	for (idx = 0; idx < 6; idx++) {
 		r = &dev->resource[idx];
 		if (!r->start && r->end) {
 			printk(KERN_ERR "PCI: Device %s not available because "
 			       "of resource collisions\n", pci_name(dev));
 			return -EINVAL;
 		}
 		if (r->flags & IORESOURCE_IO)
 			cmd |= PCI_COMMAND_IO;
 		if (r->flags & IORESOURCE_MEM)
 			cmd |= PCI_COMMAND_MEMORY;
 	}
 	if (cmd != old_cmd) {
 		printk("PCI: Enabling device %s (%04x -> %04x)\n",
 		       pci_name(dev), old_cmd, cmd);
 		pci_write_config_word(dev, PCI_COMMAND, cmd);
 	}
 	return 0;
 }
 /* Resource allocation.  */
 static void __devinit pcibios_assign_resources (void)
 {
 	struct pci_dev *dev = NULL;
 	struct resource *r;
 	for_each_pci_dev(dev) {
 		unsigned di_num;
 		unsigned class = dev->class >> 8;
 		if (class && class != PCI_CLASS_BRIDGE_HOST) {
 			unsigned r_num;
 			for(r_num = 0; r_num < 6; r_num++) {
 				r = &dev->resource[r_num];
 				if (!r->start && r->end)
 					pci_assign_resource (dev, r_num);
 			}
 		}
 		/* Assign interrupts.  */
 		for (di_num = 0; di_num < NUM_MB_PCI_DEV_IRQS; di_num++) {
 			struct mb_pci_dev_irq *di = &mb_pci_dev_irqs[di_num];
 			if (di->dev == PCI_SLOT (dev->devfn)) {
 				unsigned irq = di->irq_base;
 				if (di->query_pin) {
 					/* Find out which interrupt pin
 					   this device uses (each PCI
 					   slot has 4).  */
 					u8 irq_pin;
 					pci_read_config_byte (dev,
 							     PCI_INTERRUPT_PIN,
 							      &irq_pin);
 					if (irq_pin == 0)
 						/* Doesn't use interrupts.  */
 						continue;
 					else
 						irq += irq_pin - 1;
 				}
 				pcibios_update_irq (dev, irq);
 			}
 		}
 	}
 }
 void __devinit pcibios_update_irq (struct pci_dev *dev, int irq)
 {
 	dev->irq = irq;
 	pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 }
 void __devinit
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 			struct resource *res)
 {
 	unsigned long offset = 0;
 	if (res->flags & IORESOURCE_IO) {
 		offset = MB_A_PCI_IO_ADDR;
 	} else if (res->flags & IORESOURCE_MEM) {
 		offset = MB_A_PCI_MEM_ADDR;
 	}
 	region->start = res->start - offset;
 	region->end = res->end - offset;
 }
 /* Stubs for things we don't use.  */
 /* Called after each bus is probed, but before its children are examined. */
 void pcibios_fixup_bus(struct pci_bus *b)
 {
 }
 void
 pcibios_align_resource (void *data, struct resource *res,
 			resource_size_t size, resource_size_t align)
 {
 }
 void pcibios_set_master (struct pci_dev *dev)
 {
 }
 /* Mother-A SRAM memory allocation.  This is a simple first-fit allocator.  */
 /* A memory free-list node.  */
 struct mb_sram_free_area {
 	void *mem;
 	unsigned long size;
 	struct mb_sram_free_area *next;
 };
 /* The tail of the free-list, which starts out containing all the SRAM.  */
 static struct mb_sram_free_area mb_sram_free_tail = {
 	(void *)MB_A_SRAM_ADDR, MB_A_SRAM_SIZE, 0
 };
 /* The free-list.  */
 static struct mb_sram_free_area *mb_sram_free_areas = &mb_sram_free_tail;
 /* The free-list of free free-list nodes. (:-)  */
 static struct mb_sram_free_area *mb_sram_free_free_areas = 0;
 /* Spinlock protecting the above globals.  */
 static DEFINE_SPINLOCK(mb_sram_lock);
 /* Allocate a memory block at least SIZE bytes long in the Mother-A SRAM
    space.  */
 static void *alloc_mb_sram (size_t size)
 {
 	struct mb_sram_free_area *prev, *fa;
 	unsigned long flags;
 	void *mem = 0;
 	spin_lock_irqsave (mb_sram_lock, flags);
 	/* Look for a free area that can contain SIZE bytes.  */
 	for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next)
 		if (fa->size >= size) {
 			/* Found one!  */
 			mem = fa->mem;
 			if (fa->size == size) {
 				/* In fact, it fits exactly, so remove
 				   this node from the free-list.  */
 				if (prev)
 					prev->next = fa->next;
 				else
 					mb_sram_free_areas = fa->next;
 				/* Put it on the free-list-entry-free-list. */
 				fa->next = mb_sram_free_free_areas;
 				mb_sram_free_free_areas = fa;
 			} else {
 				/* FA is bigger than SIZE, so just
 				   reduce its size to account for this
 				   allocation.  */
 				fa->mem += size;
 				fa->size -= size;
 			}
 			break;
 		}
 	spin_unlock_irqrestore (mb_sram_lock, flags);
 	return mem;
 }
 /* Return the memory area MEM of size SIZE to the MB SRAM free pool.  */
 static void free_mb_sram (void *mem, size_t size)
 {
 	struct mb_sram_free_area *prev, *fa, *new_fa;
 	unsigned long flags;
 	void *end = mem + size;
 	spin_lock_irqsave (mb_sram_lock, flags);
  retry:
 	/* Find an adjacent free-list entry.  */
 	for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next)
 		if (fa->mem == end) {
 			/* FA is just after MEM, grow down to encompass it. */
 			fa->mem = mem;
 			fa->size += size;
 			goto done;
 		} else if (fa->mem + fa->size == mem) {
 			struct mb_sram_free_area *next_fa = fa->next;
 			/* FA is just before MEM, expand to encompass it. */
 			fa->size += size;
 			/* See if FA can now be merged with its successor. */
 			if (next_fa && fa->mem + fa->size == next_fa->mem) {
 				/* Yup; merge NEXT_FA's info into FA.  */
 				fa->size += next_fa->size;
 				fa->next = next_fa->next;
 				/* Free NEXT_FA.  */
 				next_fa->next = mb_sram_free_free_areas;
 				mb_sram_free_free_areas = next_fa;
 			}
 			goto done;
 		} else if (fa->mem > mem)
 			/* We've reached the right spot in the free-list
 			   without finding an adjacent free-area, so add
 			   a new free area to hold mem. */
 			break;
 	/* Make a new free-list entry.  */
 	/* First, get a free-list entry.  */
 	if (! mb_sram_free_free_areas) {
 		/* There are none, so make some.  */
 		void *block;
 		size_t block_size = sizeof (struct mb_sram_free_area) * 8;
 		/* Don't hold the lock while calling kmalloc (I'm not
 		   sure whether it would be a problem, since we use
 		   GFP_ATOMIC, but it makes me nervous).  */
 		spin_unlock_irqrestore (mb_sram_lock, flags);
 		block = kmalloc (block_size, GFP_ATOMIC);
 		if (! block)
 			panic ("free_mb_sram: can't allocate free-list entry");
 		/* Now get the lock back.  */
 		spin_lock_irqsave (mb_sram_lock, flags);
 		/* Add the new free free-list entries.  */
 		while (block_size > 0) {
 			struct mb_sram_free_area *nfa = block;
 			nfa->next = mb_sram_free_free_areas;
 			mb_sram_free_free_areas = nfa;
 			block += sizeof *nfa;
 			block_size -= sizeof *nfa;
 		}
 		/* Since we dropped the lock to call kmalloc, the
 		   free-list could have changed, so retry from the
 		   beginning.  */
 		goto retry;
 	}
 	/* Remove NEW_FA from the free-list of free-list entries.  */
 	new_fa = mb_sram_free_free_areas;
 	mb_sram_free_free_areas = new_fa->next;
 	/* NEW_FA initially holds only MEM.  */
 	new_fa->mem = mem;
 	new_fa->size = size;
 	/* Insert NEW_FA in the free-list between PREV and FA. */
 	new_fa->next = fa;
 	if (prev)
 		prev->next = new_fa;
 	else
 		mb_sram_free_areas = new_fa;
  done:
 	spin_unlock_irqrestore (mb_sram_lock, flags);
 }
 /* Maintainence of CPU -> Mother-A DMA mappings.  */
 struct dma_mapping {
 	void *cpu_addr;
 	void *mb_sram_addr;
 	size_t size;
 	struct dma_mapping *next;
 };
 /* A list of mappings from CPU addresses to MB SRAM addresses for active
    DMA blocks (that have been `granted' to the PCI device).  */
 static struct dma_mapping *active_dma_mappings = 0;
 /* A list of free mapping objects.  */
 static struct dma_mapping *free_dma_mappings = 0;
 /* Spinlock protecting the above globals.  */
 static DEFINE_SPINLOCK(dma_mappings_lock);
 static struct dma_mapping *new_dma_mapping (size_t size)
 {
 	unsigned long flags;
 	struct dma_mapping *mapping;
 	void *mb_sram_block = alloc_mb_sram (size);
 	if (! mb_sram_block)
 		return 0;
 	spin_lock_irqsave (dma_mappings_lock, flags);
 	if (! free_dma_mappings) {
 		/* We're out of mapping structures, make more.  */
 		void *mblock;
 		size_t mblock_size = sizeof (struct dma_mapping) * 8;
 		/* Don't hold the lock while calling kmalloc (I'm not
 		   sure whether it would be a problem, since we use
 		   GFP_ATOMIC, but it makes me nervous).  */
 		spin_unlock_irqrestore (dma_mappings_lock, flags);
 		mblock = kmalloc (mblock_size, GFP_ATOMIC);
 		if (! mblock) {
 			free_mb_sram (mb_sram_block, size);
 			return 0;
 		}
 		/* Get the lock back.  */
 		spin_lock_irqsave (dma_mappings_lock, flags);
 		/* Add the new mapping structures to the free-list.  */
 		while (mblock_size > 0) {
 			struct dma_mapping *fm = mblock;
 			fm->next = free_dma_mappings;
 			free_dma_mappings = fm;
 			mblock += sizeof *fm;
 			mblock_size -= sizeof *fm;
 		}
 	}
 	/* Get a mapping struct from the freelist.  */
 	mapping = free_dma_mappings;
 	free_dma_mappings = mapping->next;
 	/* Initialize the mapping.  Other fields should be filled in by
 	   caller.  */
 	mapping->mb_sram_addr = mb_sram_block;
 	mapping->size = size;
 	/* Add it to the list of active mappings.  */
 	mapping->next = active_dma_mappings;
 	active_dma_mappings = mapping;
 	spin_unlock_irqrestore (dma_mappings_lock, flags);
 	return mapping;
 }
 static struct dma_mapping *find_dma_mapping (void *mb_sram_addr)
 {
 	unsigned long flags;
 	struct dma_mapping *mapping;
 	spin_lock_irqsave (dma_mappings_lock, flags);
 	for (mapping = active_dma_mappings; mapping; mapping = mapping->next)
 		if (mapping->mb_sram_addr == mb_sram_addr) {
 			spin_unlock_irqrestore (dma_mappings_lock, flags);
 			return mapping;
 		}
 	panic ("find_dma_mapping: unmapped PCI DMA addr 0x%x",
 	       MB_SRAM_TO_PCI (mb_sram_addr));
 }
 static struct dma_mapping *deactivate_dma_mapping (void *mb_sram_addr)
 {
 	unsigned long flags;
 	struct dma_mapping *mapping, *prev;
 	spin_lock_irqsave (dma_mappings_lock, flags);
 	for (prev = 0, mapping = active_dma_mappings;
 	     mapping;
 	     prev = mapping, mapping = mapping->next)
 	{
 		if (mapping->mb_sram_addr == mb_sram_addr) {
 			/* This is the MAPPING; deactivate it.  */
 			if (prev)
 				prev->next = mapping->next;
 			else
 				active_dma_mappings = mapping->next;
 			spin_unlock_irqrestore (dma_mappings_lock, flags);
 			return mapping;
 		}
 	}
 	panic ("deactivate_dma_mapping: unmapped PCI DMA addr 0x%x",
 	       MB_SRAM_TO_PCI (mb_sram_addr));
 }
 /* Return MAPPING to the freelist.  */
 static inline void
 free_dma_mapping (struct dma_mapping *mapping)
 {
 	unsigned long flags;
 	free_mb_sram (mapping->mb_sram_addr, mapping->size);
 	spin_lock_irqsave (dma_mappings_lock, flags);
 	mapping->next = free_dma_mappings;
 	free_dma_mappings = mapping;
 	spin_unlock_irqrestore (dma_mappings_lock, flags);
 }
 /* Single PCI DMA mappings.  */
 /* `Grant' to PDEV the memory block at CPU_ADDR, for doing DMA.  The
    32-bit PCI bus mastering address to use is returned.  the device owns
    this memory until either pci_unmap_single or pci_dma_sync_single is
    performed.  */
 dma_addr_t
 pci_map_single (struct pci_dev *pdev, void *cpu_addr, size_t size, int dir)
 {
 	struct dma_mapping *mapping = new_dma_mapping (size);
 	if (! mapping)
 		return 0;
 	mapping->cpu_addr = cpu_addr;
 	if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_TODEVICE)
 		memcpy (mapping->mb_sram_addr, cpu_addr, size);
 	return MB_SRAM_TO_PCI (mapping->mb_sram_addr);
 }
 /* Return to the CPU the PCI DMA memory block previously `granted' to
    PDEV, at DMA_ADDR.  */
 void pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
 		       int dir)
 {
 	void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
 	struct dma_mapping *mapping = deactivate_dma_mapping (mb_sram_addr);
 	if (size != mapping->size)
 		panic ("pci_unmap_single: size (%d) doesn't match"
 		       " size of mapping at PCI DMA addr 0x%x (%d)\n",
 		       size, dma_addr, mapping->size);
 	/* Copy back the DMA'd contents if necessary.  */
 	if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_FROMDEVICE)
 		memcpy (mapping->cpu_addr, mb_sram_addr, size);
 	/* Return mapping to the freelist.  */
 	free_dma_mapping (mapping);
 }
 /* Make physical memory consistent for a single streaming mode DMA
    translation after a transfer.
    If you perform a pci_map_single() but wish to interrogate the
    buffer using the cpu, yet do not wish to teardown the PCI dma
    mapping, you must call this function before doing so.  At the next
    point you give the PCI dma address back to the card, you must first
    perform a pci_dma_sync_for_device, and then the device again owns
    the buffer.  */
 void
 pci_dma_sync_single_for_cpu (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
 		     int dir)
 {
 	void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
 	struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr);
 	/* Synchronize the DMA buffer with the CPU buffer if necessary.  */
 	if (dir == PCI_DMA_FROMDEVICE)
 		memcpy (mapping->cpu_addr, mb_sram_addr, size);
 	else if (dir == PCI_DMA_TODEVICE)
 		; /* nothing to do */
 	else
 		panic("pci_dma_sync_single: unsupported sync dir: %d", dir);
 }
 void
 pci_dma_sync_single_for_device (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
 				int dir)
 {
 	void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
 	struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr);
 	/* Synchronize the DMA buffer with the CPU buffer if necessary.  */
 	if (dir == PCI_DMA_FROMDEVICE)
 		; /* nothing to do */
 	else if (dir == PCI_DMA_TODEVICE)
 		memcpy (mb_sram_addr, mapping->cpu_addr, size);
 	else
 		panic("pci_dma_sync_single: unsupported sync dir: %d", dir);
 }
 /* Scatter-gather PCI DMA mappings.  */
 /* Do multiple DMA mappings at once.  */
 int
 pci_map_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, int dir)
 {
 	BUG ();
 	return 0;
 }
 /* Unmap multiple DMA mappings at once.  */
 void
 pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,int dir)
 {
 	BUG ();
 }
 /* Make physical memory consistent for a set of streaming mode DMA
    translations after a transfer.  The same as pci_dma_sync_single_* but
    for a scatter-gather list, same rules and usage.  */
 void
 pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
 			 struct scatterlist *sg, int sg_len,
 			 int dir)
 {
 	BUG ();
 }
 void
 pci_dma_sync_sg_for_device (struct pci_dev *dev,
 			    struct scatterlist *sg, int sg_len,
 			    int dir)
 {
 	BUG ();
 }
 /* PCI mem mapping.  */
 /* Allocate and map kernel buffer using consistent mode DMA for PCI
    device.  Returns non-NULL cpu-view pointer to the buffer if
    successful and sets *DMA_ADDR to the pci side dma address as well,
    else DMA_ADDR is undefined.  */
 void *
 pci_alloc_consistent (struct pci_dev *pdev, size_t size, dma_addr_t *dma_addr)
 {
 	void *mb_sram_mem = alloc_mb_sram (size);
 	if (mb_sram_mem)
 		*dma_addr = MB_SRAM_TO_PCI (mb_sram_mem);
 	return mb_sram_mem;
 }
 /* Free and unmap a consistent DMA buffer.  CPU_ADDR and DMA_ADDR must
    be values that were returned from pci_alloc_consistent.  SIZE must be
    the same as what as passed into pci_alloc_consistent.  References to
    the memory and mappings assosciated with CPU_ADDR or DMA_ADDR past
    this call are illegal.  */
 void
 pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr,
 		     dma_addr_t dma_addr)
 {
 	void *mb_sram_mem = PCI_TO_MB_SRAM (dma_addr);
 	free_mb_sram (mb_sram_mem, size);
 }
 /* iomap/iomap */
 void __iomem *pci_iomap (struct pci_dev *dev, int bar, unsigned long max)
 {
 	unsigned long start = pci_resource_start (dev, bar);
 	unsigned long len = pci_resource_len (dev, bar);
 	if (!start || len == 0)
 		return 0;
 	/* None of the ioremap functions actually do anything, other than
 	   re-casting their argument, so don't bother differentiating them.  */
 	return ioremap (start, len);
 }
 void pci_iounmap (struct pci_dev *dev, void __iomem *addr)
 {
 	/* nothing */
 }
 /* symbol exports (for modules) */
 EXPORT_SYMBOL (pci_map_single);
 EXPORT_SYMBOL (pci_unmap_single);
 EXPORT_SYMBOL (pci_alloc_consistent);
 EXPORT_SYMBOL (pci_free_consistent);
 EXPORT_SYMBOL (pci_dma_sync_single_for_cpu);
 EXPORT_SYMBOL (pci_dma_sync_single_for_device);
 EXPORT_SYMBOL (pci_iomap);
 EXPORT_SYMBOL (pci_iounmap);

arch/v850/kernel/rte_me2_cb.c

Diff comments View file @ 81d79be

 /*
  * arch/v850/kernel/rte_me2_cb.c -- Midas labs RTE-V850E/ME2-CB board
  *
  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
  * archive for more details.
  *
  * Written by Miles Bader <miles@gnu.org>
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
 #include <linux/irq.h>
 #include <linux/fs.h>
 #include <linux/major.h>
 #include <linux/sched.h>
 #include <linux/delay.h>
 #include <asm/atomic.h>
 #include <asm/page.h>
 #include <asm/me2.h>
 #include <asm/rte_me2_cb.h>
 #include <asm/machdep.h>
 #include <asm/v850e_intc.h>
 #include <asm/v850e_cache.h>
 #include <asm/irq.h>
 #include "mach.h"
 extern unsigned long *_intv_start;
 extern unsigned long *_intv_end;
 /* LED access routines.  */
 extern unsigned read_leds (int pos, char *buf, int len);
 extern unsigned write_leds (int pos, const char *buf, int len);
 /* SDRAM are almost contiguous (with a small hole in between;
    see mach_reserve_bootmem for details), so just use both as one big area.  */
 #define RAM_START 	SDRAM_ADDR
 #define RAM_END		(SDRAM_ADDR + SDRAM_SIZE)
 void __init mach_get_physical_ram (unsigned long *ram_start,
 				   unsigned long *ram_len)
 {
 	*ram_start = RAM_START;
 	*ram_len = RAM_END - RAM_START;
 }
 void mach_gettimeofday (struct timespec *tv)
 {
 	tv->tv_sec = 0;
 	tv->tv_nsec = 0;
 }
 /* Called before configuring an on-chip UART.  */
 void rte_me2_cb_uart_pre_configure (unsigned chan,
 				    unsigned cflags, unsigned baud)
 {
 	/* The RTE-V850E/ME2-CB connects some general-purpose I/O
 	   pins on the CPU to the RTS/CTS lines of UARTB channel 0's
 	   serial connection.
 	   I/O pins P21 and P22 are RTS and CTS respectively.  */
 	if (chan == 0) {
 		/* Put P21 & P22 in I/O port mode.  */
 		ME2_PORT2_PMC &= ~0x6;
 		/* Make P21 and output, and P22 an input.  */
 		ME2_PORT2_PM = (ME2_PORT2_PM & ~0xC) | 0x4;
 	}
 	me2_uart_pre_configure (chan, cflags, baud);
 }
 void __init mach_init_irqs (void)
 {
 	/* Initialize interrupts.  */
 	me2_init_irqs ();
 	rte_me2_cb_init_irqs ();
 }
 #ifdef CONFIG_ROM_KERNEL
 /* Initialization for kernel in ROM.  */
 static inline rom_kernel_init (void)
 {
 	/* If the kernel is in ROM, we have to copy any initialized data
 	   from ROM into RAM.  */
 	extern unsigned long _data_load_start, _sdata, _edata;
 	register unsigned long *src = &_data_load_start;
 	register unsigned long *dst = &_sdata, *end = &_edata;
 	while (dst != end)
 		*dst++ = *src++;
 }
 #endif /* CONFIG_ROM_KERNEL */
 static void install_interrupt_vectors (void)
 {
 	unsigned long *p1, *p2;
 	ME2_IRAMM = 0x03; /* V850E/ME2 iRAM write mode */
 	/* vector copy to iRAM */
 	p1 = (unsigned long *)0; /* v85x vector start */
 	p2 = (unsigned long *)&_intv_start;
 	while (p2 < (unsigned long *)&_intv_end)
 		*p1++ = *p2++;
 	ME2_IRAMM = 0x00; /* V850E/ME2 iRAM read mode */
 }
 /* CompactFlash */
 static void cf_power_on (void)
 {
 	/* CF card detected? */
 	if (CB_CF_STS0 & 0x0030)
 		return;
 	CB_CF_REG0 = 0x0002; /* reest on */
 	mdelay (10);
 	CB_CF_REG0 = 0x0003; /* power on */
 	mdelay (10);
 	CB_CF_REG0 = 0x0001; /* reset off */
 	mdelay (10);
 }
 static void cf_power_off (void)
 {
 	CB_CF_REG0 = 0x0003; /* power on */
 	mdelay (10);
 	CB_CF_REG0 = 0x0002; /* reest on */
 	mdelay (10);
 }
 void __init mach_early_init (void)
 {
 	install_interrupt_vectors ();
 	/* CS1 SDRAM instruction cache enable */
 	v850e_cache_enable (0x04, 0x03, 0);
 	rte_cb_early_init ();
 	/* CompactFlash power on */
 	cf_power_on ();
 #if defined (CONFIG_ROM_KERNEL)
 	rom_kernel_init ();
 #endif
 }
 /* RTE-V850E/ME2-CB Programmable Interrupt Controller.  */
 static struct cb_pic_irq_init cb_pic_irq_inits[] = {
 	{ "CB_EXTTM0",       IRQ_CB_EXTTM0,       1, 1, 6 },
 	{ "CB_EXTSIO",       IRQ_CB_EXTSIO,       1, 1, 6 },
 	{ "CB_TOVER",        IRQ_CB_TOVER,        1, 1, 6 },
 	{ "CB_GINT0",        IRQ_CB_GINT0,        1, 1, 6 },
 	{ "CB_USB",          IRQ_CB_USB,          1, 1, 6 },
 	{ "CB_LANC",         IRQ_CB_LANC,         1, 1, 6 },
 	{ "CB_USB_VBUS_ON",  IRQ_CB_USB_VBUS_ON,  1, 1, 6 },
 	{ "CB_USB_VBUS_OFF", IRQ_CB_USB_VBUS_OFF, 1, 1, 6 },
 	{ "CB_EXTTM1",       IRQ_CB_EXTTM1,       1, 1, 6 },
 	{ "CB_EXTTM2",       IRQ_CB_EXTTM2,       1, 1, 6 },
 	{ 0 }
 };
-#define NUM_CB_PIC_IRQ_INITS  \
+#define NUM_CB_PIC_IRQ_INITS (ARRAY_SIZE(cb_pic_irq_inits) - 1)
-   ((sizeof cb_pic_irq_inits / sizeof cb_pic_irq_inits[0]) - 1)
 static struct hw_interrupt_type cb_pic_hw_itypes[NUM_CB_PIC_IRQ_INITS];
 static unsigned char cb_pic_active_irqs = 0;
 void __init rte_me2_cb_init_irqs (void)
 {
 	cb_pic_init_irq_types (cb_pic_irq_inits, cb_pic_hw_itypes);
 	/* Initalize on board PIC1 (not PIC0) enable */
 	CB_PIC_INT0M  = 0x0000;
 	CB_PIC_INT1M  = 0x0000;
 	CB_PIC_INTR   = 0x0000;
 	CB_PIC_INTEN |= CB_PIC_INT1EN;
 	ME2_PORT2_PMC 	 |= 0x08;	/* INTP23/SCK1 mode */
 	ME2_PORT2_PFC 	 &= ~0x08;	/* INTP23 mode */
 	ME2_INTR(2) 	 &= ~0x08;	/* INTP23 falling-edge detect */
 	ME2_INTF(2) 	 &= ~0x08;	/*   " */
 	rte_cb_init_irqs ();	/* gbus &c */
 }
 /* Enable interrupt handling for interrupt IRQ.  */
 void cb_pic_enable_irq (unsigned irq)
 {
 	CB_PIC_INT1M |= 1 << (irq - CB_PIC_BASE_IRQ);
 }
 void cb_pic_disable_irq (unsigned irq)
 {
 	CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
 }
 void cb_pic_shutdown_irq (unsigned irq)
 {
 	cb_pic_disable_irq (irq);
 	if (--cb_pic_active_irqs == 0)
 		free_irq (IRQ_CB_PIC, 0);
 	CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
 }
 static irqreturn_t cb_pic_handle_irq (int irq, void *dev_id,
 				      struct pt_regs *regs)
 {
 	irqreturn_t rval = IRQ_NONE;
 	unsigned status = CB_PIC_INTR;
 	unsigned enable = CB_PIC_INT1M;
 	/* Only pay attention to enabled interrupts.  */
 	status &= enable;
 	CB_PIC_INTEN &= ~CB_PIC_INT1EN;
 	if (status) {
 		unsigned mask = 1;
 		irq = CB_PIC_BASE_IRQ;
 		do {
 			/* There's an active interrupt, find out which one,
 			   and call its handler.  */
 			while (! (status & mask)) {
 				irq++;
 				mask <<= 1;
 			}
 			status &= ~mask;
 			CB_PIC_INTR = mask;
 			/* Recursively call handle_irq to handle it. */
 			handle_irq (irq, regs);
 			rval = IRQ_HANDLED;
 		} while (status);
 	}
 	CB_PIC_INTEN |= CB_PIC_INT1EN;
 	return rval;
 }
 static void irq_nop (unsigned irq) { }
 static unsigned cb_pic_startup_irq (unsigned irq)
 {
 	int rval;
 	if (cb_pic_active_irqs == 0) {
 		rval = request_irq (IRQ_CB_PIC, cb_pic_handle_irq,
 				    IRQF_DISABLED, "cb_pic_handler", 0);
 		if (rval != 0)
 			return rval;
 	}
 	cb_pic_active_irqs++;
 	cb_pic_enable_irq (irq);
 	return 0;
 }
 /* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
    INITS (which is terminated by an entry with the name field == 0).  */
 void __init cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
 				   struct hw_interrupt_type *hw_irq_types)
 {
 	struct cb_pic_irq_init *init;
 	for (init = inits; init->name; init++) {
 		struct hw_interrupt_type *hwit = hw_irq_types++;
 		hwit->typename = init->name;
 		hwit->startup  = cb_pic_startup_irq;
 		hwit->shutdown = cb_pic_shutdown_irq;
 		hwit->enable   = cb_pic_enable_irq;
 		hwit->disable  = cb_pic_disable_irq;
 		hwit->ack      = irq_nop;
 		hwit->end      = irq_nop;
 		/* Initialize kernel IRQ infrastructure for this interrupt.  */
 		init_irq_handlers(init->base, init->num, init->interval, hwit);
 	}
 }

arch/v850/kernel/teg.c

Diff comments View file @ 81d79be

1	/*	1	/*
2	* arch/v850/kernel/teg.c -- NB85E-TEG cpu chip	2	* arch/v850/kernel/teg.c -- NB85E-TEG cpu chip
3	*	3	*
4	* Copyright (C) 2001,02,03 NEC Electronics Corporation	4	* Copyright (C) 2001,02,03 NEC Electronics Corporation
5	* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>	5	* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
6	*	6	*
7	* This file is subject to the terms and conditions of the GNU General	7	* This file is subject to the terms and conditions of the GNU General
8	* Public License. See the file COPYING in the main directory of this	8	* Public License. See the file COPYING in the main directory of this
9	* archive for more details.	9	* archive for more details.
10	*	10	*
11	* Written by Miles Bader <miles@gnu.org>	11	* Written by Miles Bader <miles@gnu.org>
12	*/	12	*/
13		13
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/init.h>	15	#include <linux/init.h>
16	#include <linux/mm.h>	16	#include <linux/mm.h>
17	#include <linux/swap.h>	17	#include <linux/swap.h>
18	#include <linux/bootmem.h>	18	#include <linux/bootmem.h>
19	#include <linux/irq.h>	19	#include <linux/irq.h>
20		20
21	#include <asm/atomic.h>	21	#include <asm/atomic.h>
22	#include <asm/page.h>	22	#include <asm/page.h>
23	#include <asm/machdep.h>	23	#include <asm/machdep.h>
24	#include <asm/v850e_timer_d.h>	24	#include <asm/v850e_timer_d.h>
25		25
26	#include "mach.h"	26	#include "mach.h"
27		27
28	void __init mach_sched_init (struct irqaction *timer_action)	28	void __init mach_sched_init (struct irqaction *timer_action)
29	{	29	{
30	/* Select timer interrupt instead of external pin. */	30	/* Select timer interrupt instead of external pin. */
31	TEG_ISS \|= 0x1;	31	TEG_ISS \|= 0x1;
32	/* Start hardware timer. */	32	/* Start hardware timer. */
33	v850e_timer_d_configure (0, HZ);	33	v850e_timer_d_configure (0, HZ);
34	/* Install timer interrupt handler. */	34	/* Install timer interrupt handler. */
35	setup_irq (IRQ_INTCMD(0), timer_action);	35	setup_irq (IRQ_INTCMD(0), timer_action);
36	}	36	}
37		37
38	static struct v850e_intc_irq_init irq_inits[] = {	38	static struct v850e_intc_irq_init irq_inits[] = {
39	{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },	39	{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },
40	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },	40	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
41	{ "SER", IRQ_INTSER(0), IRQ_INTSER_NUM, 1, 3 },	41	{ "SER", IRQ_INTSER(0), IRQ_INTSER_NUM, 1, 3 },
42	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 1, 4 },	42	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 1, 4 },
43	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 1, 5 },	43	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 1, 5 },
44	{ 0 }	44	{ 0 }
45	};	45	};
46	#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)	46	#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
47		47
48	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];	48	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
49		49
50	/* Initialize MA chip interrupts. */	50	/* Initialize MA chip interrupts. */
51	void __init teg_init_irqs (void)	51	void __init teg_init_irqs (void)
52	{	52	{
53	v850e_intc_init_irq_types (irq_inits, hw_itypes);	53	v850e_intc_init_irq_types (irq_inits, hw_itypes);
54	}	54	}
55		55
56	/* Called before configuring an on-chip UART. */	56	/* Called before configuring an on-chip UART. */
57	void teg_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)	57	void teg_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
58	{	58	{
59	/* Enable UART I/O pins instead of external interrupt pins, and	59	/* Enable UART I/O pins instead of external interrupt pins, and
60	UART interrupts instead of external pin interrupts. */	60	UART interrupts instead of external pin interrupts. */
61	TEG_ISS \|= 0x4E;	61	TEG_ISS \|= 0x4E;
62	}	62	}
63		63

1	/*	1	/*
2	* arch/v850/kernel/ma.c -- V850E/MA series of cpu chips	2	* arch/v850/kernel/ma.c -- V850E/MA series of cpu chips
3	*	3	*
4	* Copyright (C) 2001,02,03 NEC Electronics Corporation	4	* Copyright (C) 2001,02,03 NEC Electronics Corporation
5	* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>	5	* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
6	*	6	*
7	* This file is subject to the terms and conditions of the GNU General	7	* This file is subject to the terms and conditions of the GNU General
8	* Public License. See the file COPYING in the main directory of this	8	* Public License. See the file COPYING in the main directory of this
9	* archive for more details.	9	* archive for more details.
10	*	10	*
11	* Written by Miles Bader <miles@gnu.org>	11	* Written by Miles Bader <miles@gnu.org>
12	*/	12	*/
13		13
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/init.h>	15	#include <linux/init.h>
16	#include <linux/mm.h>	16	#include <linux/mm.h>
17	#include <linux/swap.h>	17	#include <linux/swap.h>
18	#include <linux/bootmem.h>	18	#include <linux/bootmem.h>
19	#include <linux/irq.h>	19	#include <linux/irq.h>
20		20
21	#include <asm/atomic.h>	21	#include <asm/atomic.h>
22	#include <asm/page.h>	22	#include <asm/page.h>
23	#include <asm/machdep.h>	23	#include <asm/machdep.h>
24	#include <asm/v850e_timer_d.h>	24	#include <asm/v850e_timer_d.h>
25		25
26	#include "mach.h"	26	#include "mach.h"
27		27
28	void __init mach_sched_init (struct irqaction *timer_action)	28	void __init mach_sched_init (struct irqaction *timer_action)
29	{	29	{
30	/* Start hardware timer. */	30	/* Start hardware timer. */
31	v850e_timer_d_configure (0, HZ);	31	v850e_timer_d_configure (0, HZ);
32	/* Install timer interrupt handler. */	32	/* Install timer interrupt handler. */
33	setup_irq (IRQ_INTCMD(0), timer_action);	33	setup_irq (IRQ_INTCMD(0), timer_action);
34	}	34	}
35		35
36	static struct v850e_intc_irq_init irq_inits[] = {	36	static struct v850e_intc_irq_init irq_inits[] = {
37	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },	37	{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
38	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },	38	{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
39	{ "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },	39	{ "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },
40	{ "CSI", IRQ_INTCSI(0), IRQ_INTCSI_NUM, 4, 4 },	40	{ "CSI", IRQ_INTCSI(0), IRQ_INTCSI_NUM, 4, 4 },
41	{ "SER", IRQ_INTSER(0), IRQ_INTSER_NUM, 4, 3 },	41	{ "SER", IRQ_INTSER(0), IRQ_INTSER_NUM, 4, 3 },
42	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 4, 4 },	42	{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 4, 4 },
43	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 4, 5 },	43	{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 4, 5 },
44	{ 0 }	44	{ 0 }
45	};	45	};
46	#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)	46	#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
47		47
48	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];	48	static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
49		49
50	/* Initialize MA chip interrupts. */	50	/* Initialize MA chip interrupts. */
51	void __init ma_init_irqs (void)	51	void __init ma_init_irqs (void)
52	{	52	{
53	v850e_intc_init_irq_types (irq_inits, hw_itypes);	53	v850e_intc_init_irq_types (irq_inits, hw_itypes);
54	}	54	}
55		55
56	/* Called before configuring an on-chip UART. */	56	/* Called before configuring an on-chip UART. */
57	void ma_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)	57	void ma_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
58	{	58	{
59	/* We only know about the first two UART channels (though	59	/* We only know about the first two UART channels (though
60	specific chips may have more). */	60	specific chips may have more). */
61	if (chan < 2) {	61	if (chan < 2) {
62	unsigned bits = 0x3 << (chan * 3);	62	unsigned bits = 0x3 << (chan * 3);
63	/* Specify that the relevant pins on the chip should do	63	/* Specify that the relevant pins on the chip should do
64	serial I/O, not direct I/O. */	64	serial I/O, not direct I/O. */
65	MA_PORT4_PMC \|= bits;	65	MA_PORT4_PMC \|= bits;
66	/* Specify that we're using the UART, not the CSI device. */	66	/* Specify that we're using the UART, not the CSI device. */
67	MA_PORT4_PFC \|= bits;	67	MA_PORT4_PFC \|= bits;
68	}	68	}
69	}	69	}
70		70