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Commit 841f2aa46299b894ce146cd7d2a8fd9a1f6dbdcb

Authored by Marc Zyngier
Committed by Jason Cooper
1 parent ebc6de0056
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

irqchip: atmel-aic: Convert to handle_domain_irq 

Use the new handle_domain_irq method to handle interrupts.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Link: https://lkml.kernel.org/r/1409047421-27649-20-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Showing 1 changed file with 1 additions and 3 deletions Inline Diff

drivers/irqchip/irq-atmel-aic.c
Diff comments   View file @ 841f2aa
1 /* 1 /*
2 * Atmel AT91 AIC (Advanced Interrupt Controller) driver 2 * Atmel AT91 AIC (Advanced Interrupt Controller) driver
3 * 3 *
4 * Copyright (C) 2004 SAN People 4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL 5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson 6 * Copyright (C) Rick Bronson
7 * Copyright (C) 2014 Free Electrons 7 * Copyright (C) 2014 Free Electrons
8 * 8 *
9 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 9 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/module.h> 17 #include <linux/module.h>
18 #include <linux/mm.h> 18 #include <linux/mm.h>
19 #include <linux/bitmap.h> 19 #include <linux/bitmap.h>
20 #include <linux/types.h> 20 #include <linux/types.h>
21 #include <linux/irq.h> 21 #include <linux/irq.h>
22 #include <linux/of.h> 22 #include <linux/of.h>
23 #include <linux/of_address.h> 23 #include <linux/of_address.h>
24 #include <linux/of_irq.h> 24 #include <linux/of_irq.h>
25 #include <linux/irqdomain.h> 25 #include <linux/irqdomain.h>
26 #include <linux/err.h> 26 #include <linux/err.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/io.h> 28 #include <linux/io.h>
29 29
30 #include <asm/exception.h> 30 #include <asm/exception.h>
31 #include <asm/mach/irq.h> 31 #include <asm/mach/irq.h>
32 32
33 #include "irq-atmel-aic-common.h" 33 #include "irq-atmel-aic-common.h"
34 #include "irqchip.h" 34 #include "irqchip.h"
35 35
36 /* Number of irq lines managed by AIC */ 36 /* Number of irq lines managed by AIC */
37 #define NR_AIC_IRQS 32 37 #define NR_AIC_IRQS 32
38 38
39 #define AT91_AIC_SMR(n) ((n) * 4) 39 #define AT91_AIC_SMR(n) ((n) * 4)
40 40
41 #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) 41 #define AT91_AIC_SVR(n) (0x80 + ((n) * 4))
42 #define AT91_AIC_IVR 0x100 42 #define AT91_AIC_IVR 0x100
43 #define AT91_AIC_FVR 0x104 43 #define AT91_AIC_FVR 0x104
44 #define AT91_AIC_ISR 0x108 44 #define AT91_AIC_ISR 0x108
45 45
46 #define AT91_AIC_IPR 0x10c 46 #define AT91_AIC_IPR 0x10c
47 #define AT91_AIC_IMR 0x110 47 #define AT91_AIC_IMR 0x110
48 #define AT91_AIC_CISR 0x114 48 #define AT91_AIC_CISR 0x114
49 49
50 #define AT91_AIC_IECR 0x120 50 #define AT91_AIC_IECR 0x120
51 #define AT91_AIC_IDCR 0x124 51 #define AT91_AIC_IDCR 0x124
52 #define AT91_AIC_ICCR 0x128 52 #define AT91_AIC_ICCR 0x128
53 #define AT91_AIC_ISCR 0x12c 53 #define AT91_AIC_ISCR 0x12c
54 #define AT91_AIC_EOICR 0x130 54 #define AT91_AIC_EOICR 0x130
55 #define AT91_AIC_SPU 0x134 55 #define AT91_AIC_SPU 0x134
56 #define AT91_AIC_DCR 0x138 56 #define AT91_AIC_DCR 0x138
57 57
58 static struct irq_domain *aic_domain; 58 static struct irq_domain *aic_domain;
59 59
60 static asmlinkage void __exception_irq_entry 60 static asmlinkage void __exception_irq_entry
61 aic_handle(struct pt_regs *regs) 61 aic_handle(struct pt_regs *regs)
62 { 62 {
63 struct irq_domain_chip_generic *dgc = aic_domain->gc; 63 struct irq_domain_chip_generic *dgc = aic_domain->gc;
64 struct irq_chip_generic *gc = dgc->gc[0]; 64 struct irq_chip_generic *gc = dgc->gc[0];
65 u32 irqnr; 65 u32 irqnr;
66 u32 irqstat; 66 u32 irqstat;
67 67
68 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR); 68 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR);
69 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR); 69 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR);
70 70
71 irqnr = irq_find_mapping(aic_domain, irqnr);
72
73 if (!irqstat) 71 if (!irqstat)
74 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR); 72 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
75 else 73 else
76 handle_IRQ(irqnr, regs); 74 handle_domain_irq(aic_domain, irqnr, regs);
77 } 75 }
78 76
79 static int aic_retrigger(struct irq_data *d) 77 static int aic_retrigger(struct irq_data *d)
80 { 78 {
81 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
82 80
83 /* Enable interrupt on AIC5 */ 81 /* Enable interrupt on AIC5 */
84 irq_gc_lock(gc); 82 irq_gc_lock(gc);
85 irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR); 83 irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR);
86 irq_gc_unlock(gc); 84 irq_gc_unlock(gc);
87 85
88 return 0; 86 return 0;
89 } 87 }
90 88
91 static int aic_set_type(struct irq_data *d, unsigned type) 89 static int aic_set_type(struct irq_data *d, unsigned type)
92 { 90 {
93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 91 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
94 unsigned int smr; 92 unsigned int smr;
95 int ret; 93 int ret;
96 94
97 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq)); 95 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq));
98 ret = aic_common_set_type(d, type, &smr); 96 ret = aic_common_set_type(d, type, &smr);
99 if (ret) 97 if (ret)
100 return ret; 98 return ret;
101 99
102 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq)); 100 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq));
103 101
104 return 0; 102 return 0;
105 } 103 }
106 104
107 #ifdef CONFIG_PM 105 #ifdef CONFIG_PM
108 static void aic_suspend(struct irq_data *d) 106 static void aic_suspend(struct irq_data *d)
109 { 107 {
110 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 108 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
111 109
112 irq_gc_lock(gc); 110 irq_gc_lock(gc);
113 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR); 111 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR);
114 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR); 112 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR);
115 irq_gc_unlock(gc); 113 irq_gc_unlock(gc);
116 } 114 }
117 115
118 static void aic_resume(struct irq_data *d) 116 static void aic_resume(struct irq_data *d)
119 { 117 {
120 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
121 119
122 irq_gc_lock(gc); 120 irq_gc_lock(gc);
123 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR); 121 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR);
124 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR); 122 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR);
125 irq_gc_unlock(gc); 123 irq_gc_unlock(gc);
126 } 124 }
127 125
128 static void aic_pm_shutdown(struct irq_data *d) 126 static void aic_pm_shutdown(struct irq_data *d)
129 { 127 {
130 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
131 129
132 irq_gc_lock(gc); 130 irq_gc_lock(gc);
133 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR); 131 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
134 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR); 132 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
135 irq_gc_unlock(gc); 133 irq_gc_unlock(gc);
136 } 134 }
137 #else 135 #else
138 #define aic_suspend NULL 136 #define aic_suspend NULL
139 #define aic_resume NULL 137 #define aic_resume NULL
140 #define aic_pm_shutdown NULL 138 #define aic_pm_shutdown NULL
141 #endif /* CONFIG_PM */ 139 #endif /* CONFIG_PM */
142 140
143 static void __init aic_hw_init(struct irq_domain *domain) 141 static void __init aic_hw_init(struct irq_domain *domain)
144 { 142 {
145 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0); 143 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
146 int i; 144 int i;
147 145
148 /* 146 /*
149 * Perform 8 End Of Interrupt Command to make sure AIC 147 * Perform 8 End Of Interrupt Command to make sure AIC
150 * will not Lock out nIRQ 148 * will not Lock out nIRQ
151 */ 149 */
152 for (i = 0; i < 8; i++) 150 for (i = 0; i < 8; i++)
153 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR); 151 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
154 152
155 /* 153 /*
156 * Spurious Interrupt ID in Spurious Vector Register. 154 * Spurious Interrupt ID in Spurious Vector Register.
157 * When there is no current interrupt, the IRQ Vector Register 155 * When there is no current interrupt, the IRQ Vector Register
158 * reads the value stored in AIC_SPU 156 * reads the value stored in AIC_SPU
159 */ 157 */
160 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU); 158 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU);
161 159
162 /* No debugging in AIC: Debug (Protect) Control Register */ 160 /* No debugging in AIC: Debug (Protect) Control Register */
163 irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR); 161 irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR);
164 162
165 /* Disable and clear all interrupts initially */ 163 /* Disable and clear all interrupts initially */
166 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR); 164 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
167 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR); 165 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
168 166
169 for (i = 0; i < 32; i++) 167 for (i = 0; i < 32; i++)
170 irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i)); 168 irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i));
171 } 169 }
172 170
173 static int aic_irq_domain_xlate(struct irq_domain *d, 171 static int aic_irq_domain_xlate(struct irq_domain *d,
174 struct device_node *ctrlr, 172 struct device_node *ctrlr,
175 const u32 *intspec, unsigned int intsize, 173 const u32 *intspec, unsigned int intsize,
176 irq_hw_number_t *out_hwirq, 174 irq_hw_number_t *out_hwirq,
177 unsigned int *out_type) 175 unsigned int *out_type)
178 { 176 {
179 struct irq_domain_chip_generic *dgc = d->gc; 177 struct irq_domain_chip_generic *dgc = d->gc;
180 struct irq_chip_generic *gc; 178 struct irq_chip_generic *gc;
181 unsigned smr; 179 unsigned smr;
182 int idx; 180 int idx;
183 int ret; 181 int ret;
184 182
185 if (!dgc) 183 if (!dgc)
186 return -EINVAL; 184 return -EINVAL;
187 185
188 ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, 186 ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
189 out_hwirq, out_type); 187 out_hwirq, out_type);
190 if (ret) 188 if (ret)
191 return ret; 189 return ret;
192 190
193 idx = intspec[0] / dgc->irqs_per_chip; 191 idx = intspec[0] / dgc->irqs_per_chip;
194 if (idx >= dgc->num_chips) 192 if (idx >= dgc->num_chips)
195 return -EINVAL; 193 return -EINVAL;
196 194
197 gc = dgc->gc[idx]; 195 gc = dgc->gc[idx];
198 196
199 irq_gc_lock(gc); 197 irq_gc_lock(gc);
200 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(*out_hwirq)); 198 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(*out_hwirq));
201 ret = aic_common_set_priority(intspec[2], &smr); 199 ret = aic_common_set_priority(intspec[2], &smr);
202 if (!ret) 200 if (!ret)
203 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(*out_hwirq)); 201 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(*out_hwirq));
204 irq_gc_unlock(gc); 202 irq_gc_unlock(gc);
205 203
206 return ret; 204 return ret;
207 } 205 }
208 206
209 static const struct irq_domain_ops aic_irq_ops = { 207 static const struct irq_domain_ops aic_irq_ops = {
210 .map = irq_map_generic_chip, 208 .map = irq_map_generic_chip,
211 .xlate = aic_irq_domain_xlate, 209 .xlate = aic_irq_domain_xlate,
212 }; 210 };
213 211
214 static void __init at91sam9_aic_irq_fixup(struct device_node *root) 212 static void __init at91sam9_aic_irq_fixup(struct device_node *root)
215 { 213 {
216 aic_common_rtc_irq_fixup(root); 214 aic_common_rtc_irq_fixup(root);
217 } 215 }
218 216
219 static const struct of_device_id __initdata aic_irq_fixups[] = { 217 static const struct of_device_id __initdata aic_irq_fixups[] = {
220 { .compatible = "atmel,at91sam9g45", .data = at91sam9_aic_irq_fixup }, 218 { .compatible = "atmel,at91sam9g45", .data = at91sam9_aic_irq_fixup },
221 { .compatible = "atmel,at91sam9n12", .data = at91sam9_aic_irq_fixup }, 219 { .compatible = "atmel,at91sam9n12", .data = at91sam9_aic_irq_fixup },
222 { .compatible = "atmel,at91sam9rl", .data = at91sam9_aic_irq_fixup }, 220 { .compatible = "atmel,at91sam9rl", .data = at91sam9_aic_irq_fixup },
223 { .compatible = "atmel,at91sam9x5", .data = at91sam9_aic_irq_fixup }, 221 { .compatible = "atmel,at91sam9x5", .data = at91sam9_aic_irq_fixup },
224 { /* sentinel */ }, 222 { /* sentinel */ },
225 }; 223 };
226 224
227 static int __init aic_of_init(struct device_node *node, 225 static int __init aic_of_init(struct device_node *node,
228 struct device_node *parent) 226 struct device_node *parent)
229 { 227 {
230 struct irq_chip_generic *gc; 228 struct irq_chip_generic *gc;
231 struct irq_domain *domain; 229 struct irq_domain *domain;
232 230
233 if (aic_domain) 231 if (aic_domain)
234 return -EEXIST; 232 return -EEXIST;
235 233
236 domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic", 234 domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
237 NR_AIC_IRQS); 235 NR_AIC_IRQS);
238 if (IS_ERR(domain)) 236 if (IS_ERR(domain))
239 return PTR_ERR(domain); 237 return PTR_ERR(domain);
240 238
241 aic_common_irq_fixup(aic_irq_fixups); 239 aic_common_irq_fixup(aic_irq_fixups);
242 240
243 aic_domain = domain; 241 aic_domain = domain;
244 gc = irq_get_domain_generic_chip(domain, 0); 242 gc = irq_get_domain_generic_chip(domain, 0);
245 243
246 gc->chip_types[0].regs.eoi = AT91_AIC_EOICR; 244 gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
247 gc->chip_types[0].regs.enable = AT91_AIC_IECR; 245 gc->chip_types[0].regs.enable = AT91_AIC_IECR;
248 gc->chip_types[0].regs.disable = AT91_AIC_IDCR; 246 gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
249 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; 247 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
250 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; 248 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
251 gc->chip_types[0].chip.irq_retrigger = aic_retrigger; 249 gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
252 gc->chip_types[0].chip.irq_set_type = aic_set_type; 250 gc->chip_types[0].chip.irq_set_type = aic_set_type;
253 gc->chip_types[0].chip.irq_suspend = aic_suspend; 251 gc->chip_types[0].chip.irq_suspend = aic_suspend;
254 gc->chip_types[0].chip.irq_resume = aic_resume; 252 gc->chip_types[0].chip.irq_resume = aic_resume;
255 gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown; 253 gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
256 254
257 aic_hw_init(domain); 255 aic_hw_init(domain);
258 set_handle_irq(aic_handle); 256 set_handle_irq(aic_handle);
259 257
260 return 0; 258 return 0;
261 } 259 }
262 IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init); 260 IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);
263 261