Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 842dfc11ea9a21f9825167c8a4f2834b205b0a79

Authored by Manuel Lauss 2014-11-07 21:13:54 +0800

Committed by Ralf Baechle 2014-11-07 22:07:36 +0800

Exists in ti-lsk-linux-4.1.y and in 10 other branches

MIPS: Fix build with binutils 2.24.51+

Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:

{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
  LD      arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
 uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
 arch/mips/alchemy/common/sleeper.o uses -mhard-float

To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS;  but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 14 changed files with 118 additions and 17 deletions Inline Diff

arch/mips/Makefile
arch/mips/include/asm/asmmacro-32.h
arch/mips/include/asm/asmmacro.h
arch/mips/include/asm/fpregdef.h
arch/mips/include/asm/fpu.h
arch/mips/include/asm/mipsregs.h
arch/mips/kernel/branch.c
arch/mips/kernel/genex.S
arch/mips/kernel/r2300_fpu.S
arch/mips/kernel/r2300_switch.S
arch/mips/kernel/r4k_fpu.S
arch/mips/kernel/r4k_switch.S
arch/mips/kernel/r6000_fpu.S
arch/mips/math-emu/cp1emu.c

arch/mips/Makefile

Diff comments View file @ 842dfc1

 #
 # This file is subject to the terms and conditions of the GNU General Public
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
 # Copyright (C) 1994, 95, 96, 2003 by Ralf Baechle
 # DECStation modifications by Paul M. Antoine, 1996
 # Copyright (C) 2002, 2003, 2004  Maciej W. Rozycki
 #
 # This file is included by the global makefile so that you can add your own
 # architecture-specific flags and dependencies. Remember to do have actions
 # for "archclean" cleaning up for this architecture.
 #
 KBUILD_DEFCONFIG := ip22_defconfig
 #
 # Select the object file format to substitute into the linker script.
 #
 ifdef CONFIG_CPU_LITTLE_ENDIAN
 32bit-tool-archpref	= mipsel
 64bit-tool-archpref	= mips64el
 32bit-bfd		= elf32-tradlittlemips
 64bit-bfd		= elf64-tradlittlemips
 32bit-emul		= elf32ltsmip
 64bit-emul		= elf64ltsmip
 else
 32bit-tool-archpref	= mips
 64bit-tool-archpref	= mips64
 32bit-bfd		= elf32-tradbigmips
 64bit-bfd		= elf64-tradbigmips
 32bit-emul		= elf32btsmip
 64bit-emul		= elf64btsmip
 endif
 ifdef CONFIG_32BIT
 tool-archpref		= $(32bit-tool-archpref)
 UTS_MACHINE		:= mips
 endif
 ifdef CONFIG_64BIT
 tool-archpref		= $(64bit-tool-archpref)
 UTS_MACHINE		:= mips64
 endif
 ifneq ($(SUBARCH),$(ARCH))
   ifeq ($(CROSS_COMPILE),)
     CROSS_COMPILE := $(call cc-cross-prefix, $(tool-archpref)-linux-  $(tool-archpref)-linux-gnu-  $(tool-archpref)-unknown-linux-gnu-)
   endif
 endif
 ifdef CONFIG_FUNCTION_GRAPH_TRACER
   ifndef KBUILD_MCOUNT_RA_ADDRESS
     ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
       cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
     endif
   endif
 endif
 cflags-y += $(call cc-option, -mno-check-zero-division)
 ifdef CONFIG_32BIT
 ld-emul			= $(32bit-emul)
 vmlinux-32		= vmlinux
 vmlinux-64		= vmlinux.64
 cflags-y		+= -mabi=32
 endif
 ifdef CONFIG_64BIT
 ld-emul			= $(64bit-emul)
 vmlinux-32		= vmlinux.32
 vmlinux-64		= vmlinux
 cflags-y		+= -mabi=64
 endif
 all-$(CONFIG_BOOT_ELF32)	:= $(vmlinux-32)
 all-$(CONFIG_BOOT_ELF64)	:= $(vmlinux-64)
 all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
 #
 # GCC uses -G 0 -mabicalls -fpic as default.  We don't want PIC in the kernel
 # code since it only slows down the whole thing.  At some point we might make
 # use of global pointer optimizations but their use of $28 conflicts with
 # the current pointer optimization.
 #
 # The DECStation requires an ECOFF kernel for remote booting, other MIPS
 # machines may also.  Since BFD is incredibly buggy with respect to
 # crossformat linking we rely on the elf2ecoff tool for format conversion.
 #
 cflags-y			+= -G 0 -mno-abicalls -fno-pic -pipe
 cflags-y			+= -msoft-float
 LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
 KBUILD_AFLAGS_MODULE		+= -mlong-calls
 KBUILD_CFLAGS_MODULE		+= -mlong-calls
+#
+# pass -msoft-float to GAS if it supports it.  However on newer binutils
+# (specifically newer than 2.24.51.20140728) we then also need to explicitly
+# set ".set hardfloat" in all files which manipulate floating point registers.
+#
+ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
+	cflags-y		+= -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
+endif
 cflags-y += -ffreestanding
 #
 # We explicitly add the endianness specifier if needed, this allows
 # to compile kernels with a toolchain for the other endianness. We
 # carefully avoid to add it redundantly because gcc 3.3/3.4 complains
 # when fed the toolchain default!
 #
 # Certain gcc versions up to gcc 4.1.1 (probably 4.2-subversion as of
 # 2006-10-10 don't properly change the predefined symbols if -EB / -EL
 # are used, so we kludge that here.  A bug has been filed at
 # http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413.
 #
 undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__
 undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__
 predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__
 predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
 cflags-$(CONFIG_CPU_BIG_ENDIAN)		+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
 cflags-$(CONFIG_CPU_LITTLE_ENDIAN)	+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
 # For smartmips configurations, there are hundreds of warnings due to ISA overrides
 # in assembly and header files. smartmips is only supported for MIPS32r1 onwards
 # and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
 # similar directives in the kernel will spam the build logs with the following warnings:
 # Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
 # or
 # Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
 # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
 # been fixed properly.
 cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= $(call cc-option,-msmartmips) -Wa,--no-warn
 cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
 cflags-$(CONFIG_SB1XXX_CORELIS)	+= $(call cc-option,-mno-sched-prolog) \
 				   -fno-omit-frame-pointer
 ifeq ($(CONFIG_CPU_HAS_MSA),y)
 toolchain-msa	:= $(call cc-option-yn,-mhard-float -mfp64 -Wa$(comma)-mmsa)
 cflags-$(toolchain-msa)		+= -DTOOLCHAIN_SUPPORTS_MSA
 endif
 #
 # CPU-dependent compiler/assembler options for optimization.
 #
 cflags-$(CONFIG_CPU_R3000)	+= -march=r3000
 cflags-$(CONFIG_CPU_TX39XX)	+= -march=r3900
 cflags-$(CONFIG_CPU_R6000)	+= -march=r6000 -Wa,--trap
 cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R1)	+= $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
 			-Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)	+= $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
 			-Wa,-mips32r2 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R1)	+= $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
 			-Wa,-mips64 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R2)	+= $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
 			-Wa,-mips64r2 -Wa,--trap
 cflags-$(CONFIG_CPU_R5000)	+= -march=r5000 -Wa,--trap
 cflags-$(CONFIG_CPU_R5432)	+= $(call cc-option,-march=r5400,-march=r5000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_R5500)	+= $(call cc-option,-march=r5500,-march=r5000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=r5000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=r5000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=r5000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mdmx)
 cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mips3d)
 cflags-$(CONFIG_CPU_R8000)	+= -march=r8000 -Wa,--trap
 cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
 ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)
 cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)
 ifdef CONFIG_CPU_SB1
 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds
 KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
 endif
 endif
 #
 # Firmware support
 #
 libs-$(CONFIG_FW_ARC)		+= arch/mips/fw/arc/
 libs-$(CONFIG_FW_CFE)		+= arch/mips/fw/cfe/
 libs-$(CONFIG_FW_SNIPROM)	+= arch/mips/fw/sni/
 libs-y				+= arch/mips/fw/lib/
 #
 # Kernel compression
 #
 ifdef SYS_SUPPORTS_ZBOOT
 COMPRESSION_FNAME		= vmlinuz
 else
 COMPRESSION_FNAME		= vmlinux
 endif
 #
 # Board-dependent options and extra files
 #
 include $(srctree)/arch/mips/Kbuild.platforms
 ifdef CONFIG_PHYSICAL_START
 load-y					= $(CONFIG_PHYSICAL_START)
 endif
 entry-y				= 0x$(shell $(NM) vmlinux 2>/dev/null \
 					| grep "\bkernel_entry\b" | cut -f1 -d \ )
 cflags-y			+= -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)		+= arch/mips/pci/
 #
 # Automatically detect the build format. By default we choose
 # the elf format according to the load address.
 # We can always force a build with a 64-bits symbol format by
 # passing 'KBUILD_SYM32=no' option to the make's command line.
 #
 ifdef CONFIG_64BIT
   ifndef KBUILD_SYM32
     ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0)
       KBUILD_SYM32 = y
     endif
   endif
   ifeq ($(KBUILD_SYM32)$(call cc-option-yn,-msym32), yy)
     cflags-y += -msym32 -DKBUILD_64BIT_SYM32
   else
     ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y)
       $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32)
     endif
   endif
 endif
 KBUILD_AFLAGS	+= $(cflags-y)
 KBUILD_CFLAGS	+= $(cflags-y)
 KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
 KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
 bootvars-y	= VMLINUX_LOAD_ADDRESS=$(load-y) \
 		  VMLINUX_ENTRY_ADDRESS=$(entry-y)
 LDFLAGS			+= -m $(ld-emul)
 ifdef CONFIG_MIPS
 CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
 	egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \
 	sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/")
 ifdef CONFIG_64BIT
 CHECKFLAGS		+= -m64
 endif
 endif
 OBJCOPYFLAGS		+= --remove-section=.reginfo
 head-y := arch/mips/kernel/head.o
 libs-y			+= arch/mips/lib/
 libs-y			+= arch/mips/math-emu/
 # See arch/mips/Kbuild for content of core part of the kernel
 core-y += arch/mips/
 drivers-$(CONFIG_OPROFILE)	+= arch/mips/oprofile/
 # suspend and hibernation support
 drivers-$(CONFIG_PM)	+= arch/mips/power/
 # boot image targets (arch/mips/boot/)
 boot-y			:= vmlinux.bin
 boot-y			+= vmlinux.ecoff
 boot-y			+= vmlinux.srec
 ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
 boot-y			+= uImage
 boot-y			+= uImage.gz
 endif
 # compressed boot image targets (arch/mips/boot/compressed/)
 bootz-y			:= vmlinuz
 bootz-y			+= vmlinuz.bin
 bootz-y			+= vmlinuz.ecoff
 bootz-y			+= vmlinuz.srec
 ifdef CONFIG_LASAT
 rom.bin rom.sw: vmlinux
 	$(Q)$(MAKE) $(build)=arch/mips/lasat/image \
 		$(bootvars-y) $@
 endif
 #
 # Some machines like the Indy need 32-bit ELF binaries for booting purposes.
 # Other need ECOFF, so we build a 32-bit ELF binary for them which we then
 # convert to ECOFF using elf2ecoff.
 #
 quiet_cmd_32 = OBJCOPY $@
 	cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 vmlinux.32: vmlinux
 	$(call cmd,32)
 #
 # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
 # ELF files from 32-bit files by conversion.
 #
 quiet_cmd_64 = OBJCOPY $@
 	cmd_64 = $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
 vmlinux.64: vmlinux
 	$(call cmd,64)
 all:	$(all-y)
 # boot
 $(boot-y): $(vmlinux-32) FORCE
 	$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
 		$(bootvars-y) arch/mips/boot/$@
 ifdef CONFIG_SYS_SUPPORTS_ZBOOT
 # boot/compressed
 $(bootz-y): $(vmlinux-32) FORCE
 	$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
 		$(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
 else
 vmlinuz: FORCE
 	@echo '   CONFIG_SYS_SUPPORTS_ZBOOT is not enabled'
 	/bin/false
 endif
 CLEAN_FILES += vmlinux.32 vmlinux.64
 # device-trees
 core-$(CONFIG_BUILTIN_DTB) += arch/mips/boot/dts/
 %.dtb %.dtb.S %.dtb.o: | scripts
 	$(Q)$(MAKE) $(build)=arch/mips/boot/dts arch/mips/boot/dts/$@
 PHONY += dtbs
 dtbs: scripts
 	$(Q)$(MAKE) $(build)=arch/mips/boot/dts dtbs
 archprepare:
 ifdef CONFIG_MIPS32_N32
 	@echo '  Checking missing-syscalls for N32'
 	$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=n32"
 endif
 ifdef CONFIG_MIPS32_O32
 	@echo '  Checking missing-syscalls for O32'
 	$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=32"
 endif
 install:
 	$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
 ifdef CONFIG_SYS_SUPPORTS_ZBOOT
 	$(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
 endif
 	$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
 	$(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
 archclean:
 	$(Q)$(MAKE) $(clean)=arch/mips/boot
 	$(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
 	$(Q)$(MAKE) $(clean)=arch/mips/lasat
 define archhelp
 	echo '  install              - install kernel into $(INSTALL_PATH)'
 	echo '  vmlinux.ecoff        - ECOFF boot image'
 	echo '  vmlinux.bin          - Raw binary boot image'
 	echo '  vmlinux.srec         - SREC boot image'
 	echo '  vmlinuz              - Compressed boot(zboot) image'
 	echo '  vmlinuz.ecoff        - ECOFF zboot image'
 	echo '  vmlinuz.bin          - Raw binary zboot image'
 	echo '  vmlinuz.srec         - SREC zboot image'
 	echo '  uImage               - U-Boot image'
 	echo '  uImage.gz            - U-Boot image (gzip)'
 	echo '  dtbs                 - Device-tree blobs for enabled boards'
 	echo
 	echo '  These will be default as appropriate for a configured platform.'
 endef

arch/mips/include/asm/asmmacro-32.h

Diff comments View file @ 842dfc1

 /*
  * asmmacro.h: Assembler macros to make things easier to read.
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1998, 1999, 2003 Ralf Baechle
  */
 #ifndef _ASM_ASMMACRO_32_H
 #define _ASM_ASMMACRO_32_H
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 	.macro	fpu_save_single thread tmp=t0
+	.set push
+	SET_HARDFLOAT
 	cfc1	\tmp,  fcr31
 	swc1	$f0,  THREAD_FPR0_LS64(\thread)
 	swc1	$f1,  THREAD_FPR1_LS64(\thread)
 	swc1	$f2,  THREAD_FPR2_LS64(\thread)
 	swc1	$f3,  THREAD_FPR3_LS64(\thread)
 	swc1	$f4,  THREAD_FPR4_LS64(\thread)
 	swc1	$f5,  THREAD_FPR5_LS64(\thread)
 	swc1	$f6,  THREAD_FPR6_LS64(\thread)
 	swc1	$f7,  THREAD_FPR7_LS64(\thread)
 	swc1	$f8,  THREAD_FPR8_LS64(\thread)
 	swc1	$f9,  THREAD_FPR9_LS64(\thread)
 	swc1	$f10, THREAD_FPR10_LS64(\thread)
 	swc1	$f11, THREAD_FPR11_LS64(\thread)
 	swc1	$f12, THREAD_FPR12_LS64(\thread)
 	swc1	$f13, THREAD_FPR13_LS64(\thread)
 	swc1	$f14, THREAD_FPR14_LS64(\thread)
 	swc1	$f15, THREAD_FPR15_LS64(\thread)
 	swc1	$f16, THREAD_FPR16_LS64(\thread)
 	swc1	$f17, THREAD_FPR17_LS64(\thread)
 	swc1	$f18, THREAD_FPR18_LS64(\thread)
 	swc1	$f19, THREAD_FPR19_LS64(\thread)
 	swc1	$f20, THREAD_FPR20_LS64(\thread)
 	swc1	$f21, THREAD_FPR21_LS64(\thread)
 	swc1	$f22, THREAD_FPR22_LS64(\thread)
 	swc1	$f23, THREAD_FPR23_LS64(\thread)
 	swc1	$f24, THREAD_FPR24_LS64(\thread)
 	swc1	$f25, THREAD_FPR25_LS64(\thread)
 	swc1	$f26, THREAD_FPR26_LS64(\thread)
 	swc1	$f27, THREAD_FPR27_LS64(\thread)
 	swc1	$f28, THREAD_FPR28_LS64(\thread)
 	swc1	$f29, THREAD_FPR29_LS64(\thread)
 	swc1	$f30, THREAD_FPR30_LS64(\thread)
 	swc1	$f31, THREAD_FPR31_LS64(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set pop
 	.endm
 	.macro	fpu_restore_single thread tmp=t0
+	.set push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	lwc1	$f0,  THREAD_FPR0_LS64(\thread)
 	lwc1	$f1,  THREAD_FPR1_LS64(\thread)
 	lwc1	$f2,  THREAD_FPR2_LS64(\thread)
 	lwc1	$f3,  THREAD_FPR3_LS64(\thread)
 	lwc1	$f4,  THREAD_FPR4_LS64(\thread)
 	lwc1	$f5,  THREAD_FPR5_LS64(\thread)
 	lwc1	$f6,  THREAD_FPR6_LS64(\thread)
 	lwc1	$f7,  THREAD_FPR7_LS64(\thread)
 	lwc1	$f8,  THREAD_FPR8_LS64(\thread)
 	lwc1	$f9,  THREAD_FPR9_LS64(\thread)
 	lwc1	$f10, THREAD_FPR10_LS64(\thread)
 	lwc1	$f11, THREAD_FPR11_LS64(\thread)
 	lwc1	$f12, THREAD_FPR12_LS64(\thread)
 	lwc1	$f13, THREAD_FPR13_LS64(\thread)
 	lwc1	$f14, THREAD_FPR14_LS64(\thread)
 	lwc1	$f15, THREAD_FPR15_LS64(\thread)
 	lwc1	$f16, THREAD_FPR16_LS64(\thread)
 	lwc1	$f17, THREAD_FPR17_LS64(\thread)
 	lwc1	$f18, THREAD_FPR18_LS64(\thread)
 	lwc1	$f19, THREAD_FPR19_LS64(\thread)
 	lwc1	$f20, THREAD_FPR20_LS64(\thread)
 	lwc1	$f21, THREAD_FPR21_LS64(\thread)
 	lwc1	$f22, THREAD_FPR22_LS64(\thread)
 	lwc1	$f23, THREAD_FPR23_LS64(\thread)
 	lwc1	$f24, THREAD_FPR24_LS64(\thread)
 	lwc1	$f25, THREAD_FPR25_LS64(\thread)
 	lwc1	$f26, THREAD_FPR26_LS64(\thread)
 	lwc1	$f27, THREAD_FPR27_LS64(\thread)
 	lwc1	$f28, THREAD_FPR28_LS64(\thread)
 	lwc1	$f29, THREAD_FPR29_LS64(\thread)
 	lwc1	$f30, THREAD_FPR30_LS64(\thread)
 	lwc1	$f31, THREAD_FPR31_LS64(\thread)
 	ctc1	\tmp, fcr31
+	.set pop
 	.endm
 	.macro	cpu_save_nonscratch thread
 	LONG_S	s0, THREAD_REG16(\thread)
 	LONG_S	s1, THREAD_REG17(\thread)
 	LONG_S	s2, THREAD_REG18(\thread)
 	LONG_S	s3, THREAD_REG19(\thread)
 	LONG_S	s4, THREAD_REG20(\thread)
 	LONG_S	s5, THREAD_REG21(\thread)
 	LONG_S	s6, THREAD_REG22(\thread)
 	LONG_S	s7, THREAD_REG23(\thread)
 	LONG_S	sp, THREAD_REG29(\thread)
 	LONG_S	fp, THREAD_REG30(\thread)
 	.endm
 	.macro	cpu_restore_nonscratch thread
 	LONG_L	s0, THREAD_REG16(\thread)
 	LONG_L	s1, THREAD_REG17(\thread)
 	LONG_L	s2, THREAD_REG18(\thread)
 	LONG_L	s3, THREAD_REG19(\thread)
 	LONG_L	s4, THREAD_REG20(\thread)
 	LONG_L	s5, THREAD_REG21(\thread)
 	LONG_L	s6, THREAD_REG22(\thread)
 	LONG_L	s7, THREAD_REG23(\thread)
 	LONG_L	sp, THREAD_REG29(\thread)
 	LONG_L	fp, THREAD_REG30(\thread)
 	LONG_L	ra, THREAD_REG31(\thread)
 	.endm
 #endif /* _ASM_ASMMACRO_32_H */

arch/mips/include/asm/asmmacro.h

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 2003 Ralf Baechle
  */
 #ifndef _ASM_ASMMACRO_H
 #define _ASM_ASMMACRO_H
 #include <asm/hazards.h>
 #include <asm/asm-offsets.h>
 #include <asm/msa.h>
 #ifdef CONFIG_32BIT
 #include <asm/asmmacro-32.h>
 #endif
 #ifdef CONFIG_64BIT
 #include <asm/asmmacro-64.h>
 #endif
 #ifdef CONFIG_CPU_MIPSR2
 	.macro	local_irq_enable reg=t0
 	ei
 	irq_enable_hazard
 	.endm
 	.macro	local_irq_disable reg=t0
 	di
 	irq_disable_hazard
 	.endm
 #else
 	.macro	local_irq_enable reg=t0
 	mfc0	\reg, CP0_STATUS
 	ori	\reg, \reg, 1
 	mtc0	\reg, CP0_STATUS
 	irq_enable_hazard
 	.endm
 	.macro	local_irq_disable reg=t0
 #ifdef CONFIG_PREEMPT
 	lw      \reg, TI_PRE_COUNT($28)
 	addi    \reg, \reg, 1
 	sw      \reg, TI_PRE_COUNT($28)
 #endif
 	mfc0	\reg, CP0_STATUS
 	ori	\reg, \reg, 1
 	xori	\reg, \reg, 1
 	mtc0	\reg, CP0_STATUS
 	irq_disable_hazard
 #ifdef CONFIG_PREEMPT
 	lw      \reg, TI_PRE_COUNT($28)
 	addi    \reg, \reg, -1
 	sw      \reg, TI_PRE_COUNT($28)
 #endif
 	.endm
 #endif /* CONFIG_CPU_MIPSR2 */
 	.macro	fpu_save_16even thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	cfc1	\tmp, fcr31
 	sdc1	$f0,  THREAD_FPR0_LS64(\thread)
 	sdc1	$f2,  THREAD_FPR2_LS64(\thread)
 	sdc1	$f4,  THREAD_FPR4_LS64(\thread)
 	sdc1	$f6,  THREAD_FPR6_LS64(\thread)
 	sdc1	$f8,  THREAD_FPR8_LS64(\thread)
 	sdc1	$f10, THREAD_FPR10_LS64(\thread)
 	sdc1	$f12, THREAD_FPR12_LS64(\thread)
 	sdc1	$f14, THREAD_FPR14_LS64(\thread)
 	sdc1	$f16, THREAD_FPR16_LS64(\thread)
 	sdc1	$f18, THREAD_FPR18_LS64(\thread)
 	sdc1	$f20, THREAD_FPR20_LS64(\thread)
 	sdc1	$f22, THREAD_FPR22_LS64(\thread)
 	sdc1	$f24, THREAD_FPR24_LS64(\thread)
 	sdc1	$f26, THREAD_FPR26_LS64(\thread)
 	sdc1	$f28, THREAD_FPR28_LS64(\thread)
 	sdc1	$f30, THREAD_FPR30_LS64(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set	pop
 	.endm
 	.macro	fpu_save_16odd thread
 	.set	push
 	.set	mips64r2
+	SET_HARDFLOAT
 	sdc1	$f1,  THREAD_FPR1_LS64(\thread)
 	sdc1	$f3,  THREAD_FPR3_LS64(\thread)
 	sdc1	$f5,  THREAD_FPR5_LS64(\thread)
 	sdc1	$f7,  THREAD_FPR7_LS64(\thread)
 	sdc1	$f9,  THREAD_FPR9_LS64(\thread)
 	sdc1	$f11, THREAD_FPR11_LS64(\thread)
 	sdc1	$f13, THREAD_FPR13_LS64(\thread)
 	sdc1	$f15, THREAD_FPR15_LS64(\thread)
 	sdc1	$f17, THREAD_FPR17_LS64(\thread)
 	sdc1	$f19, THREAD_FPR19_LS64(\thread)
 	sdc1	$f21, THREAD_FPR21_LS64(\thread)
 	sdc1	$f23, THREAD_FPR23_LS64(\thread)
 	sdc1	$f25, THREAD_FPR25_LS64(\thread)
 	sdc1	$f27, THREAD_FPR27_LS64(\thread)
 	sdc1	$f29, THREAD_FPR29_LS64(\thread)
 	sdc1	$f31, THREAD_FPR31_LS64(\thread)
 	.set	pop
 	.endm
 	.macro	fpu_save_double thread status tmp
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	sll	\tmp, \status, 5
 	bgez	\tmp, 10f
 	fpu_save_16odd \thread
 10:
 #endif
 	fpu_save_16even \thread \tmp
 	.endm
 	.macro	fpu_restore_16even thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	ldc1	$f0,  THREAD_FPR0_LS64(\thread)
 	ldc1	$f2,  THREAD_FPR2_LS64(\thread)
 	ldc1	$f4,  THREAD_FPR4_LS64(\thread)
 	ldc1	$f6,  THREAD_FPR6_LS64(\thread)
 	ldc1	$f8,  THREAD_FPR8_LS64(\thread)
 	ldc1	$f10, THREAD_FPR10_LS64(\thread)
 	ldc1	$f12, THREAD_FPR12_LS64(\thread)
 	ldc1	$f14, THREAD_FPR14_LS64(\thread)
 	ldc1	$f16, THREAD_FPR16_LS64(\thread)
 	ldc1	$f18, THREAD_FPR18_LS64(\thread)
 	ldc1	$f20, THREAD_FPR20_LS64(\thread)
 	ldc1	$f22, THREAD_FPR22_LS64(\thread)
 	ldc1	$f24, THREAD_FPR24_LS64(\thread)
 	ldc1	$f26, THREAD_FPR26_LS64(\thread)
 	ldc1	$f28, THREAD_FPR28_LS64(\thread)
 	ldc1	$f30, THREAD_FPR30_LS64(\thread)
 	ctc1	\tmp, fcr31
 	.endm
 	.macro	fpu_restore_16odd thread
 	.set	push
 	.set	mips64r2
+	SET_HARDFLOAT
 	ldc1	$f1,  THREAD_FPR1_LS64(\thread)
 	ldc1	$f3,  THREAD_FPR3_LS64(\thread)
 	ldc1	$f5,  THREAD_FPR5_LS64(\thread)
 	ldc1	$f7,  THREAD_FPR7_LS64(\thread)
 	ldc1	$f9,  THREAD_FPR9_LS64(\thread)
 	ldc1	$f11, THREAD_FPR11_LS64(\thread)
 	ldc1	$f13, THREAD_FPR13_LS64(\thread)
 	ldc1	$f15, THREAD_FPR15_LS64(\thread)
 	ldc1	$f17, THREAD_FPR17_LS64(\thread)
 	ldc1	$f19, THREAD_FPR19_LS64(\thread)
 	ldc1	$f21, THREAD_FPR21_LS64(\thread)
 	ldc1	$f23, THREAD_FPR23_LS64(\thread)
 	ldc1	$f25, THREAD_FPR25_LS64(\thread)
 	ldc1	$f27, THREAD_FPR27_LS64(\thread)
 	ldc1	$f29, THREAD_FPR29_LS64(\thread)
 	ldc1	$f31, THREAD_FPR31_LS64(\thread)
 	.set	pop
 	.endm
 	.macro	fpu_restore_double thread status tmp
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	sll	\tmp, \status, 5
 	bgez	\tmp, 10f				# 16 register mode?
 	fpu_restore_16odd \thread
 10:
 #endif
 	fpu_restore_16even \thread \tmp
 	.endm
 #ifdef CONFIG_CPU_MIPSR2
 	.macro	_EXT	rd, rs, p, s
 	ext	\rd, \rs, \p, \s
 	.endm
 #else /* !CONFIG_CPU_MIPSR2 */
 	.macro	_EXT	rd, rs, p, s
 	srl	\rd, \rs, \p
 	andi	\rd, \rd, (1 << \s) - 1
 	.endm
 #endif /* !CONFIG_CPU_MIPSR2 */
 /*
  * Temporary until all gas have MT ASE support
  */
 	.macro	DMT	reg=0
 	.word	0x41600bc1 | (\reg << 16)
 	.endm
 	.macro	EMT	reg=0
 	.word	0x41600be1 | (\reg << 16)
 	.endm
 	.macro	DVPE	reg=0
 	.word	0x41600001 | (\reg << 16)
 	.endm
 	.macro	EVPE	reg=0
 	.word	0x41600021 | (\reg << 16)
 	.endm
 	.macro	MFTR	rt=0, rd=0, u=0, sel=0
 	 .word	0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 	.endm
 	.macro	MTTR	rt=0, rd=0, u=0, sel=0
 	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 	.endm
 #ifdef TOOLCHAIN_SUPPORTS_MSA
 	.macro	ld_d	wd, off, base
 	.set	push
 	.set	mips32r2
 	.set	msa
 	ld.d	$w\wd, \off(\base)
 	.set	pop
 	.endm
 	.macro	st_d	wd, off, base
 	.set	push
 	.set	mips32r2
 	.set	msa
 	st.d	$w\wd, \off(\base)
 	.set	pop
 	.endm
 	.macro	copy_u_w	rd, ws, n
 	.set	push
 	.set	mips32r2
 	.set	msa
 	copy_u.w \rd, $w\ws[\n]
 	.set	pop
 	.endm
 	.macro	copy_u_d	rd, ws, n
 	.set	push
 	.set	mips64r2
 	.set	msa
 	copy_u.d \rd, $w\ws[\n]
 	.set	pop
 	.endm
 	.macro	insert_w	wd, n, rs
 	.set	push
 	.set	mips32r2
 	.set	msa
 	insert.w $w\wd[\n], \rs
 	.set	pop
 	.endm
 	.macro	insert_d	wd, n, rs
 	.set	push
 	.set	mips64r2
 	.set	msa
 	insert.d $w\wd[\n], \rs
 	.set	pop
 	.endm
 #else
 #ifdef CONFIG_CPU_MICROMIPS
 #define CFC_MSA_INSN		0x587e0056
 #define CTC_MSA_INSN		0x583e0816
 #define LDD_MSA_INSN		0x58000837
 #define STD_MSA_INSN		0x5800083f
 #define COPY_UW_MSA_INSN	0x58f00056
 #define COPY_UD_MSA_INSN	0x58f80056
 #define INSERT_W_MSA_INSN	0x59300816
 #define INSERT_D_MSA_INSN	0x59380816
 #else
 #define CFC_MSA_INSN		0x787e0059
 #define CTC_MSA_INSN		0x783e0819
 #define LDD_MSA_INSN		0x78000823
 #define STD_MSA_INSN		0x78000827
 #define COPY_UW_MSA_INSN	0x78f00059
 #define COPY_UD_MSA_INSN	0x78f80059
 #define INSERT_W_MSA_INSN	0x79300819
 #define INSERT_D_MSA_INSN	0x79380819
 #endif
 	/*
 	 * Temporary until all toolchains in use include MSA support.
 	 */
 	.macro	cfcmsa	rd, cs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	CFC_MSA_INSN | (\cs << 11)
 	move	\rd, $1
 	.set	pop
 	.endm
 	.macro	ctcmsa	cd, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	move	$1, \rs
 	.word	CTC_MSA_INSN | (\cd << 6)
 	.set	pop
 	.endm
 	.macro	ld_d	wd, off, base
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	add	$1, \base, \off
 	.word	LDD_MSA_INSN | (\wd << 6)
 	.set	pop
 	.endm
 	.macro	st_d	wd, off, base
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	add	$1, \base, \off
 	.word	STD_MSA_INSN | (\wd << 6)
 	.set	pop
 	.endm
 	.macro	copy_u_w	rd, ws, n
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
 	/* move triggers an assembler bug... */
 	or	\rd, $1, zero
 	.set	pop
 	.endm
 	.macro	copy_u_d	rd, ws, n
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
 	/* move triggers an assembler bug... */
 	or	\rd, $1, zero
 	.set	pop
 	.endm
 	.macro	insert_w	wd, n, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	/* move triggers an assembler bug... */
 	or	$1, \rs, zero
 	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
 	.set	pop
 	.endm
 	.macro	insert_d	wd, n, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	/* move triggers an assembler bug... */
 	or	$1, \rs, zero
 	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
 	.set	pop
 	.endm
 #endif
 	.macro	msa_save_all	thread
 	st_d	0, THREAD_FPR0, \thread
 	st_d	1, THREAD_FPR1, \thread
 	st_d	2, THREAD_FPR2, \thread
 	st_d	3, THREAD_FPR3, \thread
 	st_d	4, THREAD_FPR4, \thread
 	st_d	5, THREAD_FPR5, \thread
 	st_d	6, THREAD_FPR6, \thread
 	st_d	7, THREAD_FPR7, \thread
 	st_d	8, THREAD_FPR8, \thread
 	st_d	9, THREAD_FPR9, \thread
 	st_d	10, THREAD_FPR10, \thread
 	st_d	11, THREAD_FPR11, \thread
 	st_d	12, THREAD_FPR12, \thread
 	st_d	13, THREAD_FPR13, \thread
 	st_d	14, THREAD_FPR14, \thread
 	st_d	15, THREAD_FPR15, \thread
 	st_d	16, THREAD_FPR16, \thread
 	st_d	17, THREAD_FPR17, \thread
 	st_d	18, THREAD_FPR18, \thread
 	st_d	19, THREAD_FPR19, \thread
 	st_d	20, THREAD_FPR20, \thread
 	st_d	21, THREAD_FPR21, \thread
 	st_d	22, THREAD_FPR22, \thread
 	st_d	23, THREAD_FPR23, \thread
 	st_d	24, THREAD_FPR24, \thread
 	st_d	25, THREAD_FPR25, \thread
 	st_d	26, THREAD_FPR26, \thread
 	st_d	27, THREAD_FPR27, \thread
 	st_d	28, THREAD_FPR28, \thread
 	st_d	29, THREAD_FPR29, \thread
 	st_d	30, THREAD_FPR30, \thread
 	st_d	31, THREAD_FPR31, \thread
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	cfcmsa	$1, MSA_CSR
 	sw	$1, THREAD_MSA_CSR(\thread)
 	.set	pop
 	.endm
 	.macro	msa_restore_all	thread
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	lw	$1, THREAD_MSA_CSR(\thread)
 	ctcmsa	MSA_CSR, $1
 	.set	pop
 	ld_d	0, THREAD_FPR0, \thread
 	ld_d	1, THREAD_FPR1, \thread
 	ld_d	2, THREAD_FPR2, \thread
 	ld_d	3, THREAD_FPR3, \thread
 	ld_d	4, THREAD_FPR4, \thread
 	ld_d	5, THREAD_FPR5, \thread
 	ld_d	6, THREAD_FPR6, \thread
 	ld_d	7, THREAD_FPR7, \thread
 	ld_d	8, THREAD_FPR8, \thread
 	ld_d	9, THREAD_FPR9, \thread
 	ld_d	10, THREAD_FPR10, \thread
 	ld_d	11, THREAD_FPR11, \thread
 	ld_d	12, THREAD_FPR12, \thread
 	ld_d	13, THREAD_FPR13, \thread
 	ld_d	14, THREAD_FPR14, \thread
 	ld_d	15, THREAD_FPR15, \thread
 	ld_d	16, THREAD_FPR16, \thread
 	ld_d	17, THREAD_FPR17, \thread
 	ld_d	18, THREAD_FPR18, \thread
 	ld_d	19, THREAD_FPR19, \thread
 	ld_d	20, THREAD_FPR20, \thread
 	ld_d	21, THREAD_FPR21, \thread
 	ld_d	22, THREAD_FPR22, \thread
 	ld_d	23, THREAD_FPR23, \thread
 	ld_d	24, THREAD_FPR24, \thread
 	ld_d	25, THREAD_FPR25, \thread
 	ld_d	26, THREAD_FPR26, \thread
 	ld_d	27, THREAD_FPR27, \thread
 	ld_d	28, THREAD_FPR28, \thread
 	ld_d	29, THREAD_FPR29, \thread
 	ld_d	30, THREAD_FPR30, \thread
 	ld_d	31, THREAD_FPR31, \thread
 	.endm
 	.macro	msa_init_upper wd
 #ifdef CONFIG_64BIT
 	insert_d \wd, 1
 #else
 	insert_w \wd, 2
 	insert_w \wd, 3
 #endif
 	.if	31-\wd
 	msa_init_upper	(\wd+1)
 	.endif
 	.endm
 	.macro	msa_init_all_upper
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	not	$1, zero
 	msa_init_upper	0
 	.set	pop
 	.endm
 #endif /* _ASM_ASMMACRO_H */

arch/mips/include/asm/fpregdef.h

Diff comments View file @ 842dfc1

 /*
  * Definitions for the FPU register names
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1995, 1999 Ralf Baechle
  * Copyright (C) 1985 MIPS Computer Systems, Inc.
  * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
  */
 #ifndef _ASM_FPREGDEF_H
 #define _ASM_FPREGDEF_H
 #include <asm/sgidefs.h>
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 /*
  * These definitions only cover the R3000-ish 16/32 register model.
  * But we're trying to be R3000 friendly anyway ...
  */
 #define fv0	$f0	 /* return value */
 #define fv0f	$f1
 #define fv1	$f2
 #define fv1f	$f3
 #define fa0	$f12	 /* argument registers */
 #define fa0f	$f13
 #define fa1	$f14
 #define fa1f	$f15
 #define ft0	$f4	 /* caller saved */
 #define ft0f	$f5
 #define ft1	$f6
 #define ft1f	$f7
 #define ft2	$f8
 #define ft2f	$f9
 #define ft3	$f10
 #define ft3f	$f11
 #define ft4	$f16
 #define ft4f	$f17
 #define ft5	$f18
 #define ft5f	$f19
 #define fs0	$f20	 /* callee saved */
 #define fs0f	$f21
 #define fs1	$f22
 #define fs1f	$f23
 #define fs2	$f24
 #define fs2f	$f25
 #define fs3	$f26
 #define fs3f	$f27
 #define fs4	$f28
 #define fs4f	$f29
 #define fs5	$f30
 #define fs5f	$f31
 #define fcr31	$31	 /* FPU status register */
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 #define fv0	$f0	/* return value */
 #define fv1	$f2
 #define fa0	$f12	/* argument registers */
 #define fa1	$f13
 #define fa2	$f14
 #define fa3	$f15
 #define fa4	$f16
 #define fa5	$f17
 #define fa6	$f18
 #define fa7	$f19
 #define ft0	$f4	/* caller saved */
 #define ft1	$f5
 #define ft2	$f6
 #define ft3	$f7
 #define ft4	$f8
 #define ft5	$f9
 #define ft6	$f10
 #define ft7	$f11
 #define ft8	$f20
 #define ft9	$f21
 #define ft10	$f22
 #define ft11	$f23
 #define ft12	$f1
 #define ft13	$f3
 #define fs0	$f24	/* callee saved */
 #define fs1	$f25
 #define fs2	$f26
 #define fs3	$f27
 #define fs4	$f28
 #define fs5	$f29
 #define fs6	$f30
 #define fs7	$f31
 #define fcr31	$31
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
 #endif /* _ASM_FPREGDEF_H */

arch/mips/include/asm/fpu.h

Diff comments View file @ 842dfc1

1	/*	1	/*
2	* Copyright (C) 2002 MontaVista Software Inc.	2	* Copyright (C) 2002 MontaVista Software Inc.
3	* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net	3	* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4	*	4	*
5	* This program is free software; you can redistribute it and/or modify it	5	* This program is free software; you can redistribute it and/or modify it
6	* under the terms of the GNU General Public License as published by the	6	* under the terms of the GNU General Public License as published by the
7	* Free Software Foundation; either version 2 of the License, or (at your	7	* Free Software Foundation; either version 2 of the License, or (at your
8	* option) any later version.	8	* option) any later version.
9	*/	9	*/
10	#ifndef _ASM_FPU_H	10	#ifndef _ASM_FPU_H
11	#define _ASM_FPU_H	11	#define _ASM_FPU_H
12		12
13	#include <linux/sched.h>	13	#include <linux/sched.h>
14	#include <linux/thread_info.h>	14	#include <linux/thread_info.h>
15	#include <linux/bitops.h>	15	#include <linux/bitops.h>
16		16
17	#include <asm/mipsregs.h>	17	#include <asm/mipsregs.h>
18	#include <asm/cpu.h>	18	#include <asm/cpu.h>
19	#include <asm/cpu-features.h>	19	#include <asm/cpu-features.h>
20	#include <asm/fpu_emulator.h>	20	#include <asm/fpu_emulator.h>
21	#include <asm/hazards.h>	21	#include <asm/hazards.h>
22	#include <asm/processor.h>	22	#include <asm/processor.h>
23	#include <asm/current.h>	23	#include <asm/current.h>
24	#include <asm/msa.h>	24	#include <asm/msa.h>
25		25
26	#ifdef CONFIG_MIPS_MT_FPAFF	26	#ifdef CONFIG_MIPS_MT_FPAFF
27	#include <asm/mips_mt.h>	27	#include <asm/mips_mt.h>
28	#endif	28	#endif
29		29
30	struct sigcontext;	30	struct sigcontext;
31	struct sigcontext32;	31	struct sigcontext32;
32		32
33	extern void _init_fpu(void);	33	extern void _init_fpu(void);
34	extern void _save_fp(struct task_struct *);	34	extern void _save_fp(struct task_struct *);
35	extern void _restore_fp(struct task_struct *);	35	extern void _restore_fp(struct task_struct *);
36		36
37	/*	37	/*
38	* This enum specifies a mode in which we want the FPU to operate, for cores	38	* This enum specifies a mode in which we want the FPU to operate, for cores
39	* which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT	39	* which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT
40	* purposefully have the values 0 & 1 respectively, so that an integer value	40	* purposefully have the values 0 & 1 respectively, so that an integer value
41	* of Status.FR can be trivially casted to the corresponding enum fpu_mode.	41	* of Status.FR can be trivially casted to the corresponding enum fpu_mode.
42	*/	42	*/
43	enum fpu_mode {	43	enum fpu_mode {
44	FPU_32BIT = 0, /* FR = 0 */	44	FPU_32BIT = 0, /* FR = 0 */
45	FPU_64BIT, /* FR = 1 */	45	FPU_64BIT, /* FR = 1 */
46	FPU_AS_IS,	46	FPU_AS_IS,
47	};	47	};
48		48
49	static inline int __enable_fpu(enum fpu_mode mode)	49	static inline int __enable_fpu(enum fpu_mode mode)
50	{	50	{
51	int fr;	51	int fr;
52		52
53	switch (mode) {	53	switch (mode) {
54	case FPU_AS_IS:	54	case FPU_AS_IS:
55	/* just enable the FPU in its current mode */	55	/* just enable the FPU in its current mode */
56	set_c0_status(ST0_CU1);	56	set_c0_status(ST0_CU1);
57	enable_fpu_hazard();	57	enable_fpu_hazard();
58	return 0;	58	return 0;
59		59
60	case FPU_64BIT:	60	case FPU_64BIT:
61	#if !(defined(CONFIG_CPU_MIPS32_R2) \|\| defined(CONFIG_64BIT))	61	#if !(defined(CONFIG_CPU_MIPS32_R2) \|\| defined(CONFIG_64BIT))
62	/* we only have a 32-bit FPU */	62	/* we only have a 32-bit FPU */
63	return SIGFPE;	63	return SIGFPE;
64	#endif	64	#endif
65	/* fall through */	65	/* fall through */
66	case FPU_32BIT:	66	case FPU_32BIT:
67	/* set CU1 & change FR appropriately */	67	/* set CU1 & change FR appropriately */
68	fr = (int)mode;	68	fr = (int)mode;
69	change_c0_status(ST0_CU1 \| ST0_FR, ST0_CU1 \| (fr ? ST0_FR : 0));	69	change_c0_status(ST0_CU1 \| ST0_FR, ST0_CU1 \| (fr ? ST0_FR : 0));
70	enable_fpu_hazard();	70	enable_fpu_hazard();
71		71
72	/* check FR has the desired value */	72	/* check FR has the desired value */
73	return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;	73	return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
74		74
75	default:	75	default:
76	BUG();	76	BUG();
77	}	77	}
78		78
79	return SIGFPE;	79	return SIGFPE;
80	}	80	}
81		81
82	#define __disable_fpu() \	82	#define __disable_fpu() \
83	do { \	83	do { \
84	clear_c0_status(ST0_CU1); \	84	clear_c0_status(ST0_CU1); \
85	disable_fpu_hazard(); \	85	disable_fpu_hazard(); \
86	} while (0)	86	} while (0)
87		87
88	#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)	88	#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
89		89
90	static inline int __is_fpu_owner(void)	90	static inline int __is_fpu_owner(void)
91	{	91	{
92	return test_thread_flag(TIF_USEDFPU);	92	return test_thread_flag(TIF_USEDFPU);
93	}	93	}
94		94
95	static inline int is_fpu_owner(void)	95	static inline int is_fpu_owner(void)
96	{	96	{
97	return cpu_has_fpu && __is_fpu_owner();	97	return cpu_has_fpu && __is_fpu_owner();
98	}	98	}
99		99
100	static inline int __own_fpu(void)	100	static inline int __own_fpu(void)
101	{	101	{
102	enum fpu_mode mode;	102	enum fpu_mode mode;
103	int ret;	103	int ret;
104		104
105	mode = !test_thread_flag(TIF_32BIT_FPREGS);	105	mode = !test_thread_flag(TIF_32BIT_FPREGS);
106	ret = __enable_fpu(mode);	106	ret = __enable_fpu(mode);
107	if (ret)	107	if (ret)
108	return ret;	108	return ret;
109		109
110	KSTK_STATUS(current) \|= ST0_CU1;	110	KSTK_STATUS(current) \|= ST0_CU1;
111	if (mode == FPU_64BIT)	111	if (mode == FPU_64BIT)
112	KSTK_STATUS(current) \|= ST0_FR;	112	KSTK_STATUS(current) \|= ST0_FR;
113	else /* mode == FPU_32BIT */	113	else /* mode == FPU_32BIT */
114	KSTK_STATUS(current) &= ~ST0_FR;	114	KSTK_STATUS(current) &= ~ST0_FR;
115		115
116	set_thread_flag(TIF_USEDFPU);	116	set_thread_flag(TIF_USEDFPU);
117	return 0;	117	return 0;
118	}	118	}
119		119
120	static inline int own_fpu_inatomic(int restore)	120	static inline int own_fpu_inatomic(int restore)
121	{	121	{
122	int ret = 0;	122	int ret = 0;
123		123
124	if (cpu_has_fpu && !__is_fpu_owner()) {	124	if (cpu_has_fpu && !__is_fpu_owner()) {
125	ret = __own_fpu();	125	ret = __own_fpu();
126	if (restore && !ret)	126	if (restore && !ret)
127	_restore_fp(current);	127	_restore_fp(current);
128	}	128	}
129	return ret;	129	return ret;
130	}	130	}
131		131
132	static inline int own_fpu(int restore)	132	static inline int own_fpu(int restore)
133	{	133	{
134	int ret;	134	int ret;
135		135
136	preempt_disable();	136	preempt_disable();
137	ret = own_fpu_inatomic(restore);	137	ret = own_fpu_inatomic(restore);
138	preempt_enable();	138	preempt_enable();
139	return ret;	139	return ret;
140	}	140	}
141		141
142	static inline void lose_fpu(int save)	142	static inline void lose_fpu(int save)
143	{	143	{
144	preempt_disable();	144	preempt_disable();
145	if (is_msa_enabled()) {	145	if (is_msa_enabled()) {
146	if (save) {	146	if (save) {
147	save_msa(current);	147	save_msa(current);
148	asm volatile("cfc1 %0, $31"	148	current->thread.fpu.fcr31 =
149	: "=r"(current->thread.fpu.fcr31));	149	read_32bit_cp1_register(CP1_STATUS);
150	}	150	}
151	disable_msa();	151	disable_msa();
152	clear_thread_flag(TIF_USEDMSA);	152	clear_thread_flag(TIF_USEDMSA);
153	} else if (is_fpu_owner()) {	153	} else if (is_fpu_owner()) {
154	if (save)	154	if (save)
155	_save_fp(current);	155	_save_fp(current);
156	__disable_fpu();	156	__disable_fpu();
157	}	157	}
158	KSTK_STATUS(current) &= ~ST0_CU1;	158	KSTK_STATUS(current) &= ~ST0_CU1;
159	clear_thread_flag(TIF_USEDFPU);	159	clear_thread_flag(TIF_USEDFPU);
160	preempt_enable();	160	preempt_enable();
161	}	161	}
162		162
163	static inline int init_fpu(void)	163	static inline int init_fpu(void)
164	{	164	{
165	int ret = 0;	165	int ret = 0;
166		166
167	if (cpu_has_fpu) {	167	if (cpu_has_fpu) {
168	ret = __own_fpu();	168	ret = __own_fpu();
169	if (!ret)	169	if (!ret)
170	_init_fpu();	170	_init_fpu();
171	} else	171	} else
172	fpu_emulator_init_fpu();	172	fpu_emulator_init_fpu();
173		173
174	return ret;	174	return ret;
175	}	175	}
176		176
177	static inline void save_fp(struct task_struct *tsk)	177	static inline void save_fp(struct task_struct *tsk)
178	{	178	{
179	if (cpu_has_fpu)	179	if (cpu_has_fpu)
180	_save_fp(tsk);	180	_save_fp(tsk);
181	}	181	}
182		182
183	static inline void restore_fp(struct task_struct *tsk)	183	static inline void restore_fp(struct task_struct *tsk)
184	{	184	{
185	if (cpu_has_fpu)	185	if (cpu_has_fpu)
186	_restore_fp(tsk);	186	_restore_fp(tsk);
187	}	187	}
188		188
189	static inline union fpureg get_fpu_regs(struct task_struct tsk)	189	static inline union fpureg get_fpu_regs(struct task_struct tsk)
190	{	190	{
191	if (tsk == current) {	191	if (tsk == current) {
192	preempt_disable();	192	preempt_disable();
193	if (is_fpu_owner())	193	if (is_fpu_owner())
194	_save_fp(current);	194	_save_fp(current);
195	preempt_enable();	195	preempt_enable();
196	}	196	}
197		197
198	return tsk->thread.fpu.fpr;	198	return tsk->thread.fpu.fpr;
199	}	199	}
200		200
201	#endif /* _ASM_FPU_H */	201	#endif /* _ASM_FPU_H */
202		202

arch/mips/include/asm/mipsregs.h

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
  * Copyright (C) 2000 Silicon Graphics, Inc.
  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_MIPSREGS_H
 #define _ASM_MIPSREGS_H
 #include <linux/linkage.h>
 #include <linux/types.h>
 #include <asm/hazards.h>
 #include <asm/war.h>
 /*
  * The following macros are especially useful for __asm__
  * inline assembler.
  */
 #ifndef __STR
 #define __STR(x) #x
 #endif
 #ifndef STR
 #define STR(x) __STR(x)
 #endif
 /*
  *  Configure language
  */
 #ifdef __ASSEMBLY__
 #define _ULCAST_
 #else
 #define _ULCAST_ (unsigned long)
 #endif
 /*
  * Coprocessor 0 register names
  */
 #define CP0_INDEX $0
 #define CP0_RANDOM $1
 #define CP0_ENTRYLO0 $2
 #define CP0_ENTRYLO1 $3
 #define CP0_CONF $3
 #define CP0_CONTEXT $4
 #define CP0_PAGEMASK $5
 #define CP0_WIRED $6
 #define CP0_INFO $7
 #define CP0_BADVADDR $8
 #define CP0_COUNT $9
 #define CP0_ENTRYHI $10
 #define CP0_COMPARE $11
 #define CP0_STATUS $12
 #define CP0_CAUSE $13
 #define CP0_EPC $14
 #define CP0_PRID $15
 #define CP0_CONFIG $16
 #define CP0_LLADDR $17
 #define CP0_WATCHLO $18
 #define CP0_WATCHHI $19
 #define CP0_XCONTEXT $20
 #define CP0_FRAMEMASK $21
 #define CP0_DIAGNOSTIC $22
 #define CP0_DEBUG $23
 #define CP0_DEPC $24
 #define CP0_PERFORMANCE $25
 #define CP0_ECC $26
 #define CP0_CACHEERR $27
 #define CP0_TAGLO $28
 #define CP0_TAGHI $29
 #define CP0_ERROREPC $30
 #define CP0_DESAVE $31
 /*
  * R4640/R4650 cp0 register names.  These registers are listed
  * here only for completeness; without MMU these CPUs are not useable
  * by Linux.  A future ELKS port might take make Linux run on them
  * though ...
  */
 #define CP0_IBASE $0
 #define CP0_IBOUND $1
 #define CP0_DBASE $2
 #define CP0_DBOUND $3
 #define CP0_CALG $17
 #define CP0_IWATCH $18
 #define CP0_DWATCH $19
 /*
  * Coprocessor 0 Set 1 register names
  */
 #define CP0_S1_DERRADDR0  $26
 #define CP0_S1_DERRADDR1  $27
 #define CP0_S1_INTCONTROL $20
 /*
  * Coprocessor 0 Set 2 register names
  */
 #define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
 /*
  * Coprocessor 0 Set 3 register names
  */
 #define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
 /*
  *  TX39 Series
  */
 #define CP0_TX39_CACHE	$7
 /*
  * Coprocessor 1 (FPU) register names
  */
 #define CP1_REVISION   $0
 #define CP1_STATUS     $31
 /*
  * FPU Status Register Values
  */
 /*
  * Status Register Values
  */
 #define FPU_CSR_FLUSH	0x01000000	/* flush denormalised results to 0 */
 #define FPU_CSR_COND	0x00800000	/* $fcc0 */
 #define FPU_CSR_COND0	0x00800000	/* $fcc0 */
 #define FPU_CSR_COND1	0x02000000	/* $fcc1 */
 #define FPU_CSR_COND2	0x04000000	/* $fcc2 */
 #define FPU_CSR_COND3	0x08000000	/* $fcc3 */
 #define FPU_CSR_COND4	0x10000000	/* $fcc4 */
 #define FPU_CSR_COND5	0x20000000	/* $fcc5 */
 #define FPU_CSR_COND6	0x40000000	/* $fcc6 */
 #define FPU_CSR_COND7	0x80000000	/* $fcc7 */
 /*
  * Bits 18 - 20 of the FPU Status Register will be read as 0,
  * and should be written as zero.
  */
 #define FPU_CSR_RSVD	0x001c0000
 /*
  * X the exception cause indicator
  * E the exception enable
  * S the sticky/flag bit
 */
 #define FPU_CSR_ALL_X	0x0003f000
 #define FPU_CSR_UNI_X	0x00020000
 #define FPU_CSR_INV_X	0x00010000
 #define FPU_CSR_DIV_X	0x00008000
 #define FPU_CSR_OVF_X	0x00004000
 #define FPU_CSR_UDF_X	0x00002000
 #define FPU_CSR_INE_X	0x00001000
 #define FPU_CSR_ALL_E	0x00000f80
 #define FPU_CSR_INV_E	0x00000800
 #define FPU_CSR_DIV_E	0x00000400
 #define FPU_CSR_OVF_E	0x00000200
 #define FPU_CSR_UDF_E	0x00000100
 #define FPU_CSR_INE_E	0x00000080
 #define FPU_CSR_ALL_S	0x0000007c
 #define FPU_CSR_INV_S	0x00000040
 #define FPU_CSR_DIV_S	0x00000020
 #define FPU_CSR_OVF_S	0x00000010
 #define FPU_CSR_UDF_S	0x00000008
 #define FPU_CSR_INE_S	0x00000004
 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 #define FPU_CSR_RM	0x00000003
 #define FPU_CSR_RN	0x0	/* nearest */
 #define FPU_CSR_RZ	0x1	/* towards zero */
 #define FPU_CSR_RU	0x2	/* towards +Infinity */
 #define FPU_CSR_RD	0x3	/* towards -Infinity */
 /*
  * Values for PageMask register
  */
 #ifdef CONFIG_CPU_VR41XX
 /* Why doesn't stupidity hurt ... */
 #define PM_1K		0x00000000
 #define PM_4K		0x00001800
 #define PM_16K		0x00007800
 #define PM_64K		0x0001f800
 #define PM_256K		0x0007f800
 #else
 #define PM_4K		0x00000000
 #define PM_8K		0x00002000
 #define PM_16K		0x00006000
 #define PM_32K		0x0000e000
 #define PM_64K		0x0001e000
 #define PM_128K		0x0003e000
 #define PM_256K		0x0007e000
 #define PM_512K		0x000fe000
 #define PM_1M		0x001fe000
 #define PM_2M		0x003fe000
 #define PM_4M		0x007fe000
 #define PM_8M		0x00ffe000
 #define PM_16M		0x01ffe000
 #define PM_32M		0x03ffe000
 #define PM_64M		0x07ffe000
 #define PM_256M		0x1fffe000
 #define PM_1G		0x7fffe000
 #endif
 /*
  * Default page size for a given kernel configuration
  */
 #ifdef CONFIG_PAGE_SIZE_4KB
 #define PM_DEFAULT_MASK PM_4K
 #elif defined(CONFIG_PAGE_SIZE_8KB)
 #define PM_DEFAULT_MASK PM_8K
 #elif defined(CONFIG_PAGE_SIZE_16KB)
 #define PM_DEFAULT_MASK PM_16K
 #elif defined(CONFIG_PAGE_SIZE_32KB)
 #define PM_DEFAULT_MASK PM_32K
 #elif defined(CONFIG_PAGE_SIZE_64KB)
 #define PM_DEFAULT_MASK PM_64K
 #else
 #error Bad page size configuration!
 #endif
 /*
  * Default huge tlb size for a given kernel configuration
  */
 #ifdef CONFIG_PAGE_SIZE_4KB
 #define PM_HUGE_MASK	PM_1M
 #elif defined(CONFIG_PAGE_SIZE_8KB)
 #define PM_HUGE_MASK	PM_4M
 #elif defined(CONFIG_PAGE_SIZE_16KB)
 #define PM_HUGE_MASK	PM_16M
 #elif defined(CONFIG_PAGE_SIZE_32KB)
 #define PM_HUGE_MASK	PM_64M
 #elif defined(CONFIG_PAGE_SIZE_64KB)
 #define PM_HUGE_MASK	PM_256M
 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 #error Bad page size configuration for hugetlbfs!
 #endif
 /*
  * Values used for computation of new tlb entries
  */
 #define PL_4K		12
 #define PL_16K		14
 #define PL_64K		16
 #define PL_256K		18
 #define PL_1M		20
 #define PL_4M		22
 #define PL_16M		24
 #define PL_64M		26
 #define PL_256M		28
 /*
  * PageGrain bits
  */
 #define PG_RIE		(_ULCAST_(1) <<	 31)
 #define PG_XIE		(_ULCAST_(1) <<	 30)
 #define PG_ELPA		(_ULCAST_(1) <<	 29)
 #define PG_ESP		(_ULCAST_(1) <<	 28)
 #define PG_IEC		(_ULCAST_(1) <<  27)
 /*
  * R4x00 interrupt enable / cause bits
  */
 #define IE_SW0		(_ULCAST_(1) <<	 8)
 #define IE_SW1		(_ULCAST_(1) <<	 9)
 #define IE_IRQ0		(_ULCAST_(1) << 10)
 #define IE_IRQ1		(_ULCAST_(1) << 11)
 #define IE_IRQ2		(_ULCAST_(1) << 12)
 #define IE_IRQ3		(_ULCAST_(1) << 13)
 #define IE_IRQ4		(_ULCAST_(1) << 14)
 #define IE_IRQ5		(_ULCAST_(1) << 15)
 /*
  * R4x00 interrupt cause bits
  */
 #define C_SW0		(_ULCAST_(1) <<	 8)
 #define C_SW1		(_ULCAST_(1) <<	 9)
 #define C_IRQ0		(_ULCAST_(1) << 10)
 #define C_IRQ1		(_ULCAST_(1) << 11)
 #define C_IRQ2		(_ULCAST_(1) << 12)
 #define C_IRQ3		(_ULCAST_(1) << 13)
 #define C_IRQ4		(_ULCAST_(1) << 14)
 #define C_IRQ5		(_ULCAST_(1) << 15)
 /*
  * Bitfields in the R4xx0 cp0 status register
  */
 #define ST0_IE			0x00000001
 #define ST0_EXL			0x00000002
 #define ST0_ERL			0x00000004
 #define ST0_KSU			0x00000018
 #  define KSU_USER		0x00000010
 #  define KSU_SUPERVISOR	0x00000008
 #  define KSU_KERNEL		0x00000000
 #define ST0_UX			0x00000020
 #define ST0_SX			0x00000040
 #define ST0_KX			0x00000080
 #define ST0_DE			0x00010000
 #define ST0_CE			0x00020000
 /*
  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
  * processors.
  */
 #define ST0_CO			0x08000000
 /*
  * Bitfields in the R[23]000 cp0 status register.
  */
 #define ST0_IEC			0x00000001
 #define ST0_KUC			0x00000002
 #define ST0_IEP			0x00000004
 #define ST0_KUP			0x00000008
 #define ST0_IEO			0x00000010
 #define ST0_KUO			0x00000020
 /* bits 6 & 7 are reserved on R[23]000 */
 #define ST0_ISC			0x00010000
 #define ST0_SWC			0x00020000
 #define ST0_CM			0x00080000
 /*
  * Bits specific to the R4640/R4650
  */
 #define ST0_UM			(_ULCAST_(1) <<	 4)
 #define ST0_IL			(_ULCAST_(1) << 23)
 #define ST0_DL			(_ULCAST_(1) << 24)
 /*
  * Enable the MIPS MDMX and DSP ASEs
  */
 #define ST0_MX			0x01000000
 /*
  * Bitfields in the TX39 family CP0 Configuration Register 3
  */
 #define TX39_CONF_ICS_SHIFT	19
 #define TX39_CONF_ICS_MASK	0x00380000
 #define TX39_CONF_ICS_1KB	0x00000000
 #define TX39_CONF_ICS_2KB	0x00080000
 #define TX39_CONF_ICS_4KB	0x00100000
 #define TX39_CONF_ICS_8KB	0x00180000
 #define TX39_CONF_ICS_16KB	0x00200000
 #define TX39_CONF_DCS_SHIFT	16
 #define TX39_CONF_DCS_MASK	0x00070000
 #define TX39_CONF_DCS_1KB	0x00000000
 #define TX39_CONF_DCS_2KB	0x00010000
 #define TX39_CONF_DCS_4KB	0x00020000
 #define TX39_CONF_DCS_8KB	0x00030000
 #define TX39_CONF_DCS_16KB	0x00040000
 #define TX39_CONF_CWFON		0x00004000
 #define TX39_CONF_WBON		0x00002000
 #define TX39_CONF_RF_SHIFT	10
 #define TX39_CONF_RF_MASK	0x00000c00
 #define TX39_CONF_DOZE		0x00000200
 #define TX39_CONF_HALT		0x00000100
 #define TX39_CONF_LOCK		0x00000080
 #define TX39_CONF_ICE		0x00000020
 #define TX39_CONF_DCE		0x00000010
 #define TX39_CONF_IRSIZE_SHIFT	2
 #define TX39_CONF_IRSIZE_MASK	0x0000000c
 #define TX39_CONF_DRSIZE_SHIFT	0
 #define TX39_CONF_DRSIZE_MASK	0x00000003
 /*
  * Status register bits available in all MIPS CPUs.
  */
 #define ST0_IM			0x0000ff00
 #define	 STATUSB_IP0		8
 #define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
 #define	 STATUSB_IP1		9
 #define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
 #define	 STATUSB_IP2		10
 #define	 STATUSF_IP2		(_ULCAST_(1) << 10)
 #define	 STATUSB_IP3		11
 #define	 STATUSF_IP3		(_ULCAST_(1) << 11)
 #define	 STATUSB_IP4		12
 #define	 STATUSF_IP4		(_ULCAST_(1) << 12)
 #define	 STATUSB_IP5		13
 #define	 STATUSF_IP5		(_ULCAST_(1) << 13)
 #define	 STATUSB_IP6		14
 #define	 STATUSF_IP6		(_ULCAST_(1) << 14)
 #define	 STATUSB_IP7		15
 #define	 STATUSF_IP7		(_ULCAST_(1) << 15)
 #define	 STATUSB_IP8		0
 #define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
 #define	 STATUSB_IP9		1
 #define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
 #define	 STATUSB_IP10		2
 #define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
 #define	 STATUSB_IP11		3
 #define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
 #define	 STATUSB_IP12		4
 #define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
 #define	 STATUSB_IP13		5
 #define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
 #define	 STATUSB_IP14		6
 #define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
 #define	 STATUSB_IP15		7
 #define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
 #define ST0_CH			0x00040000
 #define ST0_NMI			0x00080000
 #define ST0_SR			0x00100000
 #define ST0_TS			0x00200000
 #define ST0_BEV			0x00400000
 #define ST0_RE			0x02000000
 #define ST0_FR			0x04000000
 #define ST0_CU			0xf0000000
 #define ST0_CU0			0x10000000
 #define ST0_CU1			0x20000000
 #define ST0_CU2			0x40000000
 #define ST0_CU3			0x80000000
 #define ST0_XX			0x80000000	/* MIPS IV naming */
 /*
  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
  *
  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  */
 #define INTCTLB_IPPCI		26
 #define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
 #define INTCTLB_IPTI		29
 #define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)
 /*
  * Bitfields and bit numbers in the coprocessor 0 cause register.
  *
  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  */
 #define	 CAUSEB_EXCCODE		2
 #define	 CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
 #define	 CAUSEB_IP		8
 #define	 CAUSEF_IP		(_ULCAST_(255) <<  8)
 #define	 CAUSEB_IP0		8
 #define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
 #define	 CAUSEB_IP1		9
 #define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
 #define	 CAUSEB_IP2		10
 #define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
 #define	 CAUSEB_IP3		11
 #define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
 #define	 CAUSEB_IP4		12
 #define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
 #define	 CAUSEB_IP5		13
 #define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
 #define	 CAUSEB_IP6		14
 #define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
 #define	 CAUSEB_IP7		15
 #define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
 #define	 CAUSEB_IV		23
 #define	 CAUSEF_IV		(_ULCAST_(1)   << 23)
 #define	 CAUSEB_PCI		26
 #define	 CAUSEF_PCI		(_ULCAST_(1)   << 26)
 #define	 CAUSEB_CE		28
 #define	 CAUSEF_CE		(_ULCAST_(3)   << 28)
 #define	 CAUSEB_TI		30
 #define	 CAUSEF_TI		(_ULCAST_(1)   << 30)
 #define	 CAUSEB_BD		31
 #define	 CAUSEF_BD		(_ULCAST_(1)   << 31)
 /*
  * Bits in the coprocessor 0 config register.
  */
 /* Generic bits.  */
 #define CONF_CM_CACHABLE_NO_WA		0
 #define CONF_CM_CACHABLE_WA		1
 #define CONF_CM_UNCACHED		2
 #define CONF_CM_CACHABLE_NONCOHERENT	3
 #define CONF_CM_CACHABLE_CE		4
 #define CONF_CM_CACHABLE_COW		5
 #define CONF_CM_CACHABLE_CUW		6
 #define CONF_CM_CACHABLE_ACCELERATED	7
 #define CONF_CM_CMASK			7
 #define CONF_BE			(_ULCAST_(1) << 15)
 /* Bits common to various processors.  */
 #define CONF_CU			(_ULCAST_(1) <<	 3)
 #define CONF_DB			(_ULCAST_(1) <<	 4)
 #define CONF_IB			(_ULCAST_(1) <<	 5)
 #define CONF_DC			(_ULCAST_(7) <<	 6)
 #define CONF_IC			(_ULCAST_(7) <<	 9)
 #define CONF_EB			(_ULCAST_(1) << 13)
 #define CONF_EM			(_ULCAST_(1) << 14)
 #define CONF_SM			(_ULCAST_(1) << 16)
 #define CONF_SC			(_ULCAST_(1) << 17)
 #define CONF_EW			(_ULCAST_(3) << 18)
 #define CONF_EP			(_ULCAST_(15)<< 24)
 #define CONF_EC			(_ULCAST_(7) << 28)
 #define CONF_CM			(_ULCAST_(1) << 31)
 /* Bits specific to the R4xx0.	*/
 #define R4K_CONF_SW		(_ULCAST_(1) << 20)
 #define R4K_CONF_SS		(_ULCAST_(1) << 21)
 #define R4K_CONF_SB		(_ULCAST_(3) << 22)
 /* Bits specific to the R5000.	*/
 #define R5K_CONF_SE		(_ULCAST_(1) << 12)
 #define R5K_CONF_SS		(_ULCAST_(3) << 20)
 /* Bits specific to the RM7000.	 */
 #define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
 #define RM7K_CONF_TE		(_ULCAST_(1) << 12)
 #define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
 #define RM7K_CONF_TC		(_ULCAST_(1) << 17)
 #define RM7K_CONF_SI		(_ULCAST_(3) << 20)
 #define RM7K_CONF_SC		(_ULCAST_(1) << 31)
 /* Bits specific to the R10000.	 */
 #define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
 #define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
 #define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
 #define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
 #define R10K_CONF_EC		(_ULCAST_(15)<<	 9)
 #define R10K_CONF_SB		(_ULCAST_(1) << 13)
 #define R10K_CONF_SK		(_ULCAST_(1) << 14)
 #define R10K_CONF_SS		(_ULCAST_(7) << 16)
 #define R10K_CONF_SC		(_ULCAST_(7) << 19)
 #define R10K_CONF_DC		(_ULCAST_(7) << 26)
 #define R10K_CONF_IC		(_ULCAST_(7) << 29)
 /* Bits specific to the VR41xx.	 */
 #define VR41_CONF_CS		(_ULCAST_(1) << 12)
 #define VR41_CONF_P4K		(_ULCAST_(1) << 13)
 #define VR41_CONF_BP		(_ULCAST_(1) << 16)
 #define VR41_CONF_M16		(_ULCAST_(1) << 20)
 #define VR41_CONF_AD		(_ULCAST_(1) << 23)
 /* Bits specific to the R30xx.	*/
 #define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
 #define R30XX_CONF_REV		(_ULCAST_(1) << 22)
 #define R30XX_CONF_AC		(_ULCAST_(1) << 23)
 #define R30XX_CONF_RF		(_ULCAST_(1) << 24)
 #define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
 #define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
 #define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
 #define R30XX_CONF_SB		(_ULCAST_(1) << 30)
 #define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
 /* Bits specific to the TX49.  */
 #define TX49_CONF_DC		(_ULCAST_(1) << 16)
 #define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 #define TX49_CONF_HALT		(_ULCAST_(1) << 18)
 #define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
 /* Bits specific to the MIPS32/64 PRA.	*/
 #define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
 #define MIPS_CONF_AR		(_ULCAST_(7) << 10)
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
 #define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
 #define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
 #define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
 #define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
 #define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
 #define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
 #define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
 #define MIPS_CONF1_DA_SHF	7
 #define MIPS_CONF1_DA_SZ	3
 #define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
 #define MIPS_CONF1_DL_SHF	10
 #define MIPS_CONF1_DL_SZ	3
 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
 #define MIPS_CONF1_DS_SHF	13
 #define MIPS_CONF1_DS_SZ	3
 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
 #define MIPS_CONF1_IA_SHF	16
 #define MIPS_CONF1_IA_SZ	3
 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
 #define MIPS_CONF1_IL_SHF	19
 #define MIPS_CONF1_IL_SZ	3
 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
 #define MIPS_CONF1_IS_SHF	22
 #define MIPS_CONF1_IS_SZ	3
 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
 #define MIPS_CONF1_TLBS_SHIFT   (25)
 #define MIPS_CONF1_TLBS_SIZE    (6)
 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 #define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)
 #define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
 #define MIPS_CONF2_SS		(_ULCAST_(15)<<	 8)
 #define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
 #define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
 #define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
 #define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
 #define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
 #define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
 #define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
 #define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
 #define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
 #define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
 #define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
 #define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
 #define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
 #define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
 #define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
 #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
 #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
 #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
 #define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
 #define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
 #define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
 #define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
 #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
 #define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
 #define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
 #define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
 #define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
 #define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
 #define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
 #define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
 #define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
 #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
 #define MIPS_CONF4_FTLBSETS_SHIFT	(0)
 #define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 #define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
 #define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
 /* bits 10:8 in FTLB-only configurations */
 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 /* bits 12:8 in VTLB-FTLB only configurations */
 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 #define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
 #define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << 16)
 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
 #define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 #define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
 #define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
 #define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
 #define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
 #define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
 #define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
 #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
 #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
 #define MIPS_CONF5_K		(_ULCAST_(1) << 30)
 #define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
 /* proAptiv FTLB on/off bit */
 #define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
 /* MAAR bit definitions */
 #define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 #define MIPS_MAAR_ADDR_SHIFT	12
 #define MIPS_MAAR_S		(_ULCAST_(1) << 1)
 #define MIPS_MAAR_V		(_ULCAST_(1) << 0)
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 /* CMGCRBase bit definitions */
 #define MIPS_CMGCRB_BASE	11
 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
 #define MIPS_FPIR_S		(_ULCAST_(1) << 16)
 #define MIPS_FPIR_D		(_ULCAST_(1) << 17)
 #define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
 #define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
 #define MIPS_FPIR_W		(_ULCAST_(1) << 20)
 #define MIPS_FPIR_L		(_ULCAST_(1) << 21)
 #define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
 /*
  * Bits in the MIPS32 Memory Segmentation registers.
  */
 #define MIPS_SEGCFG_PA_SHIFT	9
 #define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 #define MIPS_SEGCFG_AM_SHIFT	4
 #define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 #define MIPS_SEGCFG_EU_SHIFT	3
 #define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 #define MIPS_SEGCFG_C_SHIFT	0
 #define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 #define MIPS_SEGCFG_UUSK	_ULCAST_(7)
 #define MIPS_SEGCFG_USK		_ULCAST_(5)
 #define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
 #define MIPS_SEGCFG_MUSK	_ULCAST_(3)
 #define MIPS_SEGCFG_MSK		_ULCAST_(2)
 #define MIPS_SEGCFG_MK		_ULCAST_(1)
 #define MIPS_SEGCFG_UK		_ULCAST_(0)
 #define MIPS_PWFIELD_GDI_SHIFT	24
 #define MIPS_PWFIELD_GDI_MASK	0x3f000000
 #define MIPS_PWFIELD_UDI_SHIFT	18
 #define MIPS_PWFIELD_UDI_MASK	0x00fc0000
 #define MIPS_PWFIELD_MDI_SHIFT	12
 #define MIPS_PWFIELD_MDI_MASK	0x0003f000
 #define MIPS_PWFIELD_PTI_SHIFT	6
 #define MIPS_PWFIELD_PTI_MASK	0x00000fc0
 #define MIPS_PWFIELD_PTEI_SHIFT	0
 #define MIPS_PWFIELD_PTEI_MASK	0x0000003f
 #define MIPS_PWSIZE_GDW_SHIFT	24
 #define MIPS_PWSIZE_GDW_MASK	0x3f000000
 #define MIPS_PWSIZE_UDW_SHIFT	18
 #define MIPS_PWSIZE_UDW_MASK	0x00fc0000
 #define MIPS_PWSIZE_MDW_SHIFT	12
 #define MIPS_PWSIZE_MDW_MASK	0x0003f000
 #define MIPS_PWSIZE_PTW_SHIFT	6
 #define MIPS_PWSIZE_PTW_MASK	0x00000fc0
 #define MIPS_PWSIZE_PTEW_SHIFT	0
 #define MIPS_PWSIZE_PTEW_MASK	0x0000003f
 #define MIPS_PWCTL_PWEN_SHIFT	31
 #define MIPS_PWCTL_PWEN_MASK	0x80000000
 #define MIPS_PWCTL_DPH_SHIFT	7
 #define MIPS_PWCTL_DPH_MASK	0x00000080
 #define MIPS_PWCTL_HUGEPG_SHIFT	6
 #define MIPS_PWCTL_HUGEPG_MASK	0x00000060
 #define MIPS_PWCTL_PSN_SHIFT	0
 #define MIPS_PWCTL_PSN_MASK	0x0000003f
 #ifndef __ASSEMBLY__
 /*
  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
  */
 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 #define get_isa16_mode(x)		((x) & 0x1)
 #define msk_isa16_mode(x)		((x) & ~0x1)
 #define set_isa16_mode(x)		do { (x) |= 0x1; } while(0)
 #else
 #define get_isa16_mode(x)		0
 #define msk_isa16_mode(x)		(x)
 #define set_isa16_mode(x)		do { } while(0)
 #endif
 /*
  * microMIPS instructions can be 16-bit or 32-bit in length. This
  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
  */
 static inline int mm_insn_16bit(u16 insn)
 {
 	u16 opcode = (insn >> 10) & 0x7;
 	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 }
 /*
  * TLB Invalidate Flush
  */
 static inline void tlbinvf(void)
 {
 	__asm__ __volatile__(
 		".set push\n\t"
 		".set noreorder\n\t"
 		".word 0x42000004\n\t" /* tlbinvf */
 		".set pop");
 }
 /*
  * Functions to access the R10000 performance counters.	 These are basically
  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
  * performance counter number encoded into bits 1 ... 5 of the instruction.
  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
  * disassembler these will look like an access to sel 0 or 1.
  */
 #define read_r10k_perf_cntr(counter)				\
 ({								\
 	unsigned int __res;					\
 	__asm__ __volatile__(					\
 	"mfpc\t%0, %1"						\
 	: "=r" (__res)						\
 	: "i" (counter));					\
 								\
 	__res;							\
 })
 #define write_r10k_perf_cntr(counter,val)			\
 do {								\
 	__asm__ __volatile__(					\
 	"mtpc\t%0, %1"						\
 	:							\
 	: "r" (val), "i" (counter));				\
 } while (0)
 #define read_r10k_perf_event(counter)				\
 ({								\
 	unsigned int __res;					\
 	__asm__ __volatile__(					\
 	"mfps\t%0, %1"						\
 	: "=r" (__res)						\
 	: "i" (counter));					\
 								\
 	__res;							\
 })
 #define write_r10k_perf_cntl(counter,val)			\
 do {								\
 	__asm__ __volatile__(					\
 	"mtps\t%0, %1"						\
 	:							\
 	: "r" (val), "i" (counter));				\
 } while (0)
 /*
  * Macros to access the system control coprocessor
  */
 #define __read_32bit_c0_register(source, sel)				\
 ({ int __res;								\
 	if (sel == 0)							\
 		__asm__ __volatile__(					\
 			"mfc0\t%0, " #source "\n\t"			\
 			: "=r" (__res));				\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips32\n\t"				\
 			"mfc0\t%0, " #source ", " #sel "\n\t"		\
 			".set\tmips0\n\t"				\
 			: "=r" (__res));				\
 	__res;								\
 })
 #define __read_64bit_c0_register(source, sel)				\
 ({ unsigned long long __res;						\
 	if (sizeof(unsigned long) == 4)					\
 		__res = __read_64bit_c0_split(source, sel);		\
 	else if (sel == 0)						\
 		__asm__ __volatile__(					\
 			".set\tmips3\n\t"				\
 			"dmfc0\t%0, " #source "\n\t"			\
 			".set\tmips0"					\
 			: "=r" (__res));				\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
 			".set\tmips0"					\
 			: "=r" (__res));				\
 	__res;								\
 })
 #define __write_32bit_c0_register(register, sel, value)			\
 do {									\
 	if (sel == 0)							\
 		__asm__ __volatile__(					\
 			"mtc0\t%z0, " #register "\n\t"			\
 			: : "Jr" ((unsigned int)(value)));		\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips32\n\t"				\
 			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
 			".set\tmips0"					\
 			: : "Jr" ((unsigned int)(value)));		\
 } while (0)
 #define __write_64bit_c0_register(register, sel, value)			\
 do {									\
 	if (sizeof(unsigned long) == 4)					\
 		__write_64bit_c0_split(register, sel, value);		\
 	else if (sel == 0)						\
 		__asm__ __volatile__(					\
 			".set\tmips3\n\t"				\
 			"dmtc0\t%z0, " #register "\n\t"			\
 			".set\tmips0"					\
 			: : "Jr" (value));				\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
 			".set\tmips0"					\
 			: : "Jr" (value));				\
 } while (0)
 #define __read_ulong_c0_register(reg, sel)				\
 	((sizeof(unsigned long) == 4) ?					\
 	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
 	(unsigned long) __read_64bit_c0_register(reg, sel))
 #define __write_ulong_c0_register(reg, sel, val)			\
 do {									\
 	if (sizeof(unsigned long) == 4)					\
 		__write_32bit_c0_register(reg, sel, val);		\
 	else								\
 		__write_64bit_c0_register(reg, sel, val);		\
 } while (0)
 /*
  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
  */
 #define __read_32bit_c0_ctrl_register(source)				\
 ({ int __res;								\
 	__asm__ __volatile__(						\
 		"cfc0\t%0, " #source "\n\t"				\
 		: "=r" (__res));					\
 	__res;								\
 })
 #define __write_32bit_c0_ctrl_register(register, value)			\
 do {									\
 	__asm__ __volatile__(						\
 		"ctc0\t%z0, " #register "\n\t"				\
 		: : "Jr" ((unsigned int)(value)));			\
 } while (0)
 /*
  * These versions are only needed for systems with more than 38 bits of
  * physical address space running the 32-bit kernel.  That's none atm :-)
  */
 #define __read_64bit_c0_split(source, sel)				\
 ({									\
 	unsigned long long __val;					\
 	unsigned long __flags;						\
 									\
 	local_irq_save(__flags);					\
 	if (sel == 0)							\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dmfc0\t%M0, " #source "\n\t"			\
 			"dsll\t%L0, %M0, 32\n\t"			\
 			"dsra\t%M0, %M0, 32\n\t"			\
 			"dsra\t%L0, %L0, 32\n\t"			\
 			".set\tmips0"					\
 			: "=r" (__val));				\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
 			"dsll\t%L0, %M0, 32\n\t"			\
 			"dsra\t%M0, %M0, 32\n\t"			\
 			"dsra\t%L0, %L0, 32\n\t"			\
 			".set\tmips0"					\
 			: "=r" (__val));				\
 	local_irq_restore(__flags);					\
 									\
 	__val;								\
 })
 #define __write_64bit_c0_split(source, sel, val)			\
 do {									\
 	unsigned long __flags;						\
 									\
 	local_irq_save(__flags);					\
 	if (sel == 0)							\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dsll\t%L0, %L0, 32\n\t"			\
 			"dsrl\t%L0, %L0, 32\n\t"			\
 			"dsll\t%M0, %M0, 32\n\t"			\
 			"or\t%L0, %L0, %M0\n\t"				\
 			"dmtc0\t%L0, " #source "\n\t"			\
 			".set\tmips0"					\
 			: : "r" (val));					\
 	else								\
 		__asm__ __volatile__(					\
 			".set\tmips64\n\t"				\
 			"dsll\t%L0, %L0, 32\n\t"			\
 			"dsrl\t%L0, %L0, 32\n\t"			\
 			"dsll\t%M0, %M0, 32\n\t"			\
 			"or\t%L0, %L0, %M0\n\t"				\
 			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
 			".set\tmips0"					\
 			: : "r" (val));					\
 	local_irq_restore(__flags);					\
 } while (0)
 #define read_c0_index()		__read_32bit_c0_register($0, 0)
 #define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
 #define read_c0_random()	__read_32bit_c0_register($1, 0)
 #define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
 #define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
 #define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
 #define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
 #define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
 #define read_c0_conf()		__read_32bit_c0_register($3, 0)
 #define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
 #define read_c0_context()	__read_ulong_c0_register($4, 0)
 #define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
 #define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 #define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
 #define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
 #define read_c0_wired()		__read_32bit_c0_register($6, 0)
 #define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
 #define read_c0_info()		__read_32bit_c0_register($7, 0)
 #define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
 #define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
 #define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
 #define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
 #define read_c0_count()		__read_32bit_c0_register($9, 0)
 #define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
 #define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
 #define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
 #define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
 #define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
 #define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
 #define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
 #define read_c0_compare()	__read_32bit_c0_register($11, 0)
 #define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
 #define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
 #define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
 #define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
 #define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
 #define read_c0_status()	__read_32bit_c0_register($12, 0)
 #define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
 #define read_c0_cause()		__read_32bit_c0_register($13, 0)
 #define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
 #define read_c0_epc()		__read_ulong_c0_register($14, 0)
 #define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
 #define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
 #define read_c0_config()	__read_32bit_c0_register($16, 0)
 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
 #define read_c0_config3()	__read_32bit_c0_register($16, 3)
 #define read_c0_config4()	__read_32bit_c0_register($16, 4)
 #define read_c0_config5()	__read_32bit_c0_register($16, 5)
 #define read_c0_config6()	__read_32bit_c0_register($16, 6)
 #define read_c0_config7()	__read_32bit_c0_register($16, 7)
 #define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
 #define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
 #define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
 #define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
 #define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
 #define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
 #define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
 #define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
 #define read_c0_maar()		__read_ulong_c0_register($17, 1)
 #define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
 #define read_c0_maari()		__read_32bit_c0_register($17, 2)
 #define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
 /*
  * The WatchLo register.  There may be up to 8 of them.
  */
 #define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
 #define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
 #define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
 #define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
 #define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
 #define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
 #define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
 #define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
 #define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
 #define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
 #define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
 #define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
 #define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
 #define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
 #define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
 #define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
 /*
  * The WatchHi register.  There may be up to 8 of them.
  */
 #define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
 #define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
 #define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
 #define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
 #define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
 #define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
 #define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
 #define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
 #define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
 #define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
 #define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
 #define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
 #define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
 #define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
 #define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
 #define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
 #define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
 #define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
 #define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 #define read_c0_framemask()	__read_32bit_c0_register($21, 0)
 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 #define read_c0_diag()		__read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
 #define read_c0_diag1()		__read_32bit_c0_register($22, 1)
 #define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
 #define read_c0_diag2()		__read_32bit_c0_register($22, 2)
 #define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
 #define read_c0_diag3()		__read_32bit_c0_register($22, 3)
 #define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
 #define read_c0_diag4()		__read_32bit_c0_register($22, 4)
 #define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
 #define read_c0_depc()		__read_ulong_c0_register($24, 0)
 #define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
 /*
  * MIPS32 / MIPS64 performance counters
  */
 #define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 #define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
 #define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
 #define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 #define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
 #define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
 #define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 #define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
 #define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
 #define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 #define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
 #define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
 #define read_c0_ecc()		__read_32bit_c0_register($26, 0)
 #define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
 #define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
 #define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
 #define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
 #define read_c0_taglo()		__read_32bit_c0_register($28, 0)
 #define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
 #define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
 #define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
 #define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
 #define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)
 #define read_c0_staglo()	__read_32bit_c0_register($28, 4)
 #define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)
 #define read_c0_taghi()		__read_32bit_c0_register($29, 0)
 #define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
 #define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
 #define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
 /* MIPSR2 */
 #define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
 #define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
 #define read_c0_intctl()	__read_32bit_c0_register($12, 1)
 #define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
 #define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
 #define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
 #define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
 #define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
 #define read_c0_ebase()		__read_32bit_c0_register($15, 1)
 #define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
 /* MIPSR3 */
 #define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
 #define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
 #define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
 #define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
 #define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
 #define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
 /* Hardware Page Table Walker */
 #define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
 #define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)
 #define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
 #define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)
 #define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
 #define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)
 #define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
 #define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)
 /* Cavium OCTEON (cnMIPS) */
 #define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
 #define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)
 #define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
 #define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)
 #define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
 /*
  * The cacheerr registers are not standardized.	 On OCTEON, they are
  * 64 bits wide.
  */
 #define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
 #define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)
 #define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
 #define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)
 /* BMIPS3300 */
 #define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
 #define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
 #define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
 #define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
 #define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
 #define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
 /* BMIPS43xx */
 #define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
 #define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
 #define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
 #define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
 #define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
 #define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
 #define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
 #define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
 #define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
 #define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
 /* BMIPS5000 */
 #define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
 #define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
 #define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
 #define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
 #define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
 #define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
 #define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
 #define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
 #define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
 #define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
 #define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
 #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
 /*
  * Macros to access the floating point coprocessor control registers
  */
-#define read_32bit_cp1_register(source)					\
+#define _read_32bit_cp1_register(source, gas_hardfloat)			\
 ({									\
 	int __res;							\
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	reorder					\n"	\
 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
 	"	# like Octeon.					\n"	\
 	"	.set	mips1					\n"	\
+	"	"STR(gas_hardfloat)"				\n"	\
 	"	cfc1	%0,"STR(source)"			\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__res));						\
 	__res;								\
 })
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, )
+#endif
 #ifdef HAVE_AS_DSP
 #define rddsp(mask)							\
 ({									\
 	unsigned int __dspctl;						\
 									\
 	__asm__ __volatile__(						\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	rddsp	%0, %x1					\n"	\
 	"	.set pop					\n"	\
 	: "=r" (__dspctl)						\
 	: "i" (mask));							\
 	__dspctl;							\
 })
 #define wrdsp(val, mask)						\
 do {									\
 	__asm__ __volatile__(						\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	wrdsp	%0, %x1					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (val), "i" (mask));					\
 } while (0)
 #define mflo0()								\
 ({									\
 	long mflo0;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac0					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mflo0)); 						\
 	mflo0;								\
 })
 #define mflo1()								\
 ({									\
 	long mflo1;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac1					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mflo1)); 						\
 	mflo1;								\
 })
 #define mflo2()								\
 ({									\
 	long mflo2;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac2					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mflo2)); 						\
 	mflo2;								\
 })
 #define mflo3()								\
 ({									\
 	long mflo3;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac3					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mflo3)); 						\
 	mflo3;								\
 })
 #define mfhi0()								\
 ({									\
 	long mfhi0;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac0					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mfhi0)); 						\
 	mfhi0;								\
 })
 #define mfhi1()								\
 ({									\
 	long mfhi1;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac1					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mfhi1)); 						\
 	mfhi1;								\
 })
 #define mfhi2()								\
 ({									\
 	long mfhi2;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac2					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mfhi2)); 						\
 	mfhi2;								\
 })
 #define mfhi3()								\
 ({									\
 	long mfhi3;							\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac3					\n"	\
 	"	.set pop					\n" 	\
 	: "=r" (mfhi3)); 						\
 	mfhi3;								\
 })
 #define mtlo0(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mtlo %0, $ac0					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mtlo1(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mtlo %0, $ac1					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mtlo2(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mtlo %0, $ac2					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mtlo3(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mtlo %0, $ac3					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mthi0(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mthi %0, $ac0					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mthi1(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mthi %0, $ac1					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mthi2(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mthi %0, $ac2					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #define mthi3(x)							\
 ({									\
 	__asm__(							\
 	"	.set push					\n"	\
 	"	.set dsp					\n"	\
 	"	mthi %0, $ac3					\n"	\
 	"	.set pop					\n"	\
 	:								\
 	: "r" (x));							\
 })
 #else
 #ifdef CONFIG_CPU_MICROMIPS
 #define rddsp(mask)							\
 ({									\
 	unsigned int __res;						\
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	# rddsp $1, %x1					\n"	\
 	"	.hword	((0x0020067c | (%x1 << 14)) >> 16)	\n"	\
 	"	.hword	((0x0020067c | (%x1 << 14)) & 0xffff)	\n"	\
 	"	move	%0, $1					\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__res)							\
 	: "i" (mask));							\
 	__res;								\
 })
 #define wrdsp(val, mask)						\
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	# wrdsp $1, %x1					\n"	\
 	"	.hword	((0x0020167c | (%x1 << 14)) >> 16)	\n"	\
 	"	.hword	((0x0020167c | (%x1 << 14)) & 0xffff)	\n"	\
 	"	.set	pop					\n"	\
 	:								\
 	: "r" (val), "i" (mask));					\
 } while (0)
 #define _umips_dsp_mfxxx(ins)						\
 ({									\
 	unsigned long __treg;						\
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	.hword	0x0001					\n"	\
 	"	.hword	%x1					\n"	\
 	"	move	%0, $1					\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__treg)							\
 	: "i" (ins));							\
 	__treg;								\
 })
 #define _umips_dsp_mtxxx(val, ins)					\
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	.hword	0x0001					\n"	\
 	"	.hword	%x1					\n"	\
 	"	.set	pop					\n"	\
 	:								\
 	: "r" (val), "i" (ins));					\
 } while (0)
 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
 #define mflo0() _umips_dsp_mflo(0)
 #define mflo1() _umips_dsp_mflo(1)
 #define mflo2() _umips_dsp_mflo(2)
 #define mflo3() _umips_dsp_mflo(3)
 #define mfhi0() _umips_dsp_mfhi(0)
 #define mfhi1() _umips_dsp_mfhi(1)
 #define mfhi2() _umips_dsp_mfhi(2)
 #define mfhi3() _umips_dsp_mfhi(3)
 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
 #define mthi0(x) _umips_dsp_mthi(x, 0)
 #define mthi1(x) _umips_dsp_mthi(x, 1)
 #define mthi2(x) _umips_dsp_mthi(x, 2)
 #define mthi3(x) _umips_dsp_mthi(x, 3)
 #else  /* !CONFIG_CPU_MICROMIPS */
 #define rddsp(mask)							\
 ({									\
 	unsigned int __res;						\
 									\
 	__asm__ __volatile__(						\
 	"	.set	push				\n"		\
 	"	.set	noat				\n"		\
 	"	# rddsp $1, %x1				\n"		\
 	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
 	"	move	%0, $1				\n"		\
 	"	.set	pop				\n"		\
 	: "=r" (__res)							\
 	: "i" (mask));							\
 	__res;								\
 })
 #define wrdsp(val, mask)						\
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	# wrdsp $1, %x1					\n"	\
 	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
 	"	.set	pop					\n"	\
         :								\
 	: "r" (val), "i" (mask));					\
 } while (0)
 #define _dsp_mfxxx(ins)							\
 ({									\
 	unsigned long __treg;						\
 									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	.word	(0x00000810 | %1)			\n"	\
 	"	move	%0, $1					\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__treg)							\
 	: "i" (ins));							\
 	__treg;								\
 })
 #define _dsp_mtxxx(val, ins)						\
 do {									\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noat					\n"	\
 	"	move	$1, %0					\n"	\
 	"	.word	(0x00200011 | %1)			\n"	\
 	"	.set	pop					\n"	\
 	:								\
 	: "r" (val), "i" (ins));					\
 } while (0)
 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
 #define mflo0() _dsp_mflo(0)
 #define mflo1() _dsp_mflo(1)
 #define mflo2() _dsp_mflo(2)
 #define mflo3() _dsp_mflo(3)
 #define mfhi0() _dsp_mfhi(0)
 #define mfhi1() _dsp_mfhi(1)
 #define mfhi2() _dsp_mfhi(2)
 #define mfhi3() _dsp_mfhi(3)
 #define mtlo0(x) _dsp_mtlo(x, 0)
 #define mtlo1(x) _dsp_mtlo(x, 1)
 #define mtlo2(x) _dsp_mtlo(x, 2)
 #define mtlo3(x) _dsp_mtlo(x, 3)
 #define mthi0(x) _dsp_mthi(x, 0)
 #define mthi1(x) _dsp_mthi(x, 1)
 #define mthi2(x) _dsp_mthi(x, 2)
 #define mthi3(x) _dsp_mthi(x, 3)
 #endif /* CONFIG_CPU_MICROMIPS */
 #endif
 /*
  * TLB operations.
  *
  * It is responsibility of the caller to take care of any TLB hazards.
  */
 static inline void tlb_probe(void)
 {
 	__asm__ __volatile__(
 		".set noreorder\n\t"
 		"tlbp\n\t"
 		".set reorder");
 }
 static inline void tlb_read(void)
 {
 #if MIPS34K_MISSED_ITLB_WAR
 	int res = 0;
 	__asm__ __volatile__(
 	"	.set	push					\n"
 	"	.set	noreorder				\n"
 	"	.set	noat					\n"
 	"	.set	mips32r2				\n"
 	"	.word	0x41610001		# dvpe $1	\n"
 	"	move	%0, $1					\n"
 	"	ehb						\n"
 	"	.set	pop					\n"
 	: "=r" (res));
 	instruction_hazard();
 #endif
 	__asm__ __volatile__(
 		".set noreorder\n\t"
 		"tlbr\n\t"
 		".set reorder");
 #if MIPS34K_MISSED_ITLB_WAR
 	if ((res & _ULCAST_(1)))
 		__asm__ __volatile__(
 		"	.set	push				\n"
 		"	.set	noreorder			\n"
 		"	.set	noat				\n"
 		"	.set	mips32r2			\n"
 		"	.word	0x41600021	# evpe		\n"
 		"	ehb					\n"
 		"	.set	pop				\n");
 #endif
 }
 static inline void tlb_write_indexed(void)
 {
 	__asm__ __volatile__(
 		".set noreorder\n\t"
 		"tlbwi\n\t"
 		".set reorder");
 }
 static inline void tlb_write_random(void)
 {
 	__asm__ __volatile__(
 		".set noreorder\n\t"
 		"tlbwr\n\t"
 		".set reorder");
 }
 /*
  * Manipulate bits in a c0 register.
  */
 #define __BUILD_SET_C0(name)					\
 static inline unsigned int					\
 set_c0_##name(unsigned int set)					\
 {								\
 	unsigned int res, new;					\
 								\
 	res = read_c0_##name();					\
 	new = res | set;					\
 	write_c0_##name(new);					\
 								\
 	return res;						\
 }								\
 								\
 static inline unsigned int					\
 clear_c0_##name(unsigned int clear)				\
 {								\
 	unsigned int res, new;					\
 								\
 	res = read_c0_##name();					\
 	new = res & ~clear;					\
 	write_c0_##name(new);					\
 								\
 	return res;						\
 }								\
 								\
 static inline unsigned int					\
 change_c0_##name(unsigned int change, unsigned int val)		\
 {								\
 	unsigned int res, new;					\
 								\
 	res = read_c0_##name();					\
 	new = res & ~change;					\
 	new |= (val & change);					\
 	write_c0_##name(new);					\
 								\
 	return res;						\
 }
 __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
 __BUILD_SET_C0(brcm_config_0)
 __BUILD_SET_C0(brcm_bus_pll)
 __BUILD_SET_C0(brcm_reset)
 __BUILD_SET_C0(brcm_cmt_intr)
 __BUILD_SET_C0(brcm_cmt_ctrl)
 __BUILD_SET_C0(brcm_config)
 __BUILD_SET_C0(brcm_mode)
 /*
  * Return low 10 bits of ebase.
  * Note that under KVM (MIPSVZ) this returns vcpu id.
  */
 static inline unsigned int get_ebase_cpunum(void)
 {
 	return read_c0_ebase() & 0x3ff;
 }
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_MIPSREGS_H */

arch/mips/kernel/branch.c

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
  * Copyright (C) 2001 MIPS Technologies, Inc.
  */
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <linux/module.h>
 #include <asm/branch.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
 #include <asm/fpu.h>
 #include <asm/fpu_emulator.h>
 #include <asm/inst.h>
 #include <asm/ptrace.h>
 #include <asm/uaccess.h>
 /*
  * Calculate and return exception PC in case of branch delay slot
  * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
  */
 int __isa_exception_epc(struct pt_regs *regs)
 {
 	unsigned short inst;
 	long epc = regs->cp0_epc;
 	/* Calculate exception PC in branch delay slot. */
 	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
 		/* This should never happen because delay slot was checked. */
 		force_sig(SIGSEGV, current);
 		return epc;
 	}
 	if (cpu_has_mips16) {
 		if (((union mips16e_instruction)inst).ri.opcode
 				== MIPS16e_jal_op)
 			epc += 4;
 		else
 			epc += 2;
 	} else if (mm_insn_16bit(inst))
 		epc += 2;
 	else
 		epc += 4;
 	return epc;
 }
 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
 int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 		       unsigned long *contpc)
 {
 	union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 	int bc_false = 0;
 	unsigned int fcr31;
 	unsigned int bit;
 	if (!cpu_has_mmips)
 		return 0;
 	switch (insn.mm_i_format.opcode) {
 	case mm_pool32a_op:
 		if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
 		    mm_pool32axf_op) {
 			switch (insn.mm_i_format.simmediate >>
 				MM_POOL32A_MINOR_SHIFT) {
 			case mm_jalr_op:
 			case mm_jalrhb_op:
 			case mm_jalrs_op:
 			case mm_jalrshb_op:
 				if (insn.mm_i_format.rt != 0)	/* Not mm_jr */
 					regs->regs[insn.mm_i_format.rt] =
 						regs->cp0_epc +
 						dec_insn.pc_inc +
 						dec_insn.next_pc_inc;
 				*contpc = regs->regs[insn.mm_i_format.rs];
 				return 1;
 			}
 		}
 		break;
 	case mm_pool32i_op:
 		switch (insn.mm_i_format.rt) {
 		case mm_bltzals_op:
 		case mm_bltzal_op:
 			regs->regs[31] = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 			/* Fall through */
 		case mm_bltz_op:
 			if ((long)regs->regs[insn.mm_i_format.rs] < 0)
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.mm_i_format.simmediate << 1);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			return 1;
 		case mm_bgezals_op:
 		case mm_bgezal_op:
 			regs->regs[31] = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			/* Fall through */
 		case mm_bgez_op:
 			if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.mm_i_format.simmediate << 1);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			return 1;
 		case mm_blez_op:
 			if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.mm_i_format.simmediate << 1);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			return 1;
 		case mm_bgtz_op:
 			if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.mm_i_format.simmediate << 1);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			return 1;
 		case mm_bc2f_op:
 		case mm_bc1f_op:
 			bc_false = 1;
 			/* Fall through */
 		case mm_bc2t_op:
 		case mm_bc1t_op:
 			preempt_disable();
 			if (is_fpu_owner())
-				asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+			        fcr31 = read_32bit_cp1_register(CP1_STATUS);
 			else
 				fcr31 = current->thread.fpu.fcr31;
 			preempt_enable();
 			if (bc_false)
 				fcr31 = ~fcr31;
 			bit = (insn.mm_i_format.rs >> 2);
 			bit += (bit != 0);
 			bit += 23;
 			if (fcr31 & (1 << bit))
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.mm_i_format.simmediate << 1);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc + dec_insn.next_pc_inc;
 			return 1;
 		}
 		break;
 	case mm_pool16c_op:
 		switch (insn.mm_i_format.rt) {
 		case mm_jalr16_op:
 		case mm_jalrs16_op:
 			regs->regs[31] = regs->cp0_epc +
 				dec_insn.pc_inc + dec_insn.next_pc_inc;
 			/* Fall through */
 		case mm_jr16_op:
 			*contpc = regs->regs[insn.mm_i_format.rs];
 			return 1;
 		}
 		break;
 	case mm_beqz16_op:
 		if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.mm_b1_format.simmediate << 1);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc + dec_insn.next_pc_inc;
 		return 1;
 	case mm_bnez16_op:
 		if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.mm_b1_format.simmediate << 1);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc + dec_insn.next_pc_inc;
 		return 1;
 	case mm_b16_op:
 		*contpc = regs->cp0_epc + dec_insn.pc_inc +
 			 (insn.mm_b0_format.simmediate << 1);
 		return 1;
 	case mm_beq32_op:
 		if (regs->regs[insn.mm_i_format.rs] ==
 		    regs->regs[insn.mm_i_format.rt])
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.mm_i_format.simmediate << 1);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 		return 1;
 	case mm_bne32_op:
 		if (regs->regs[insn.mm_i_format.rs] !=
 		    regs->regs[insn.mm_i_format.rt])
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.mm_i_format.simmediate << 1);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc + dec_insn.next_pc_inc;
 		return 1;
 	case mm_jalx32_op:
 		regs->regs[31] = regs->cp0_epc +
 			dec_insn.pc_inc + dec_insn.next_pc_inc;
 		*contpc = regs->cp0_epc + dec_insn.pc_inc;
 		*contpc >>= 28;
 		*contpc <<= 28;
 		*contpc |= (insn.j_format.target << 2);
 		return 1;
 	case mm_jals32_op:
 	case mm_jal32_op:
 		regs->regs[31] = regs->cp0_epc +
 			dec_insn.pc_inc + dec_insn.next_pc_inc;
 		/* Fall through */
 	case mm_j32_op:
 		*contpc = regs->cp0_epc + dec_insn.pc_inc;
 		*contpc >>= 27;
 		*contpc <<= 27;
 		*contpc |= (insn.j_format.target << 1);
 		set_isa16_mode(*contpc);
 		return 1;
 	}
 	return 0;
 }
 /*
  * Compute return address and emulate branch in microMIPS mode after an
  * exception only. It does not handle compact branches/jumps and cannot
  * be used in interrupt context. (Compact branches/jumps do not cause
  * exceptions.)
  */
 int __microMIPS_compute_return_epc(struct pt_regs *regs)
 {
 	u16 __user *pc16;
 	u16 halfword;
 	unsigned int word;
 	unsigned long contpc;
 	struct mm_decoded_insn mminsn = { 0 };
 	mminsn.micro_mips_mode = 1;
 	/* This load never faults. */
 	pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
 	__get_user(halfword, pc16);
 	pc16++;
 	contpc = regs->cp0_epc + 2;
 	word = ((unsigned int)halfword << 16);
 	mminsn.pc_inc = 2;
 	if (!mm_insn_16bit(halfword)) {
 		__get_user(halfword, pc16);
 		pc16++;
 		contpc = regs->cp0_epc + 4;
 		mminsn.pc_inc = 4;
 		word |= halfword;
 	}
 	mminsn.insn = word;
 	if (get_user(halfword, pc16))
 		goto sigsegv;
 	mminsn.next_pc_inc = 2;
 	word = ((unsigned int)halfword << 16);
 	if (!mm_insn_16bit(halfword)) {
 		pc16++;
 		if (get_user(halfword, pc16))
 			goto sigsegv;
 		mminsn.next_pc_inc = 4;
 		word |= halfword;
 	}
 	mminsn.next_insn = word;
 	mm_isBranchInstr(regs, mminsn, &contpc);
 	regs->cp0_epc = contpc;
 	return 0;
 sigsegv:
 	force_sig(SIGSEGV, current);
 	return -EFAULT;
 }
 /*
  * Compute return address and emulate branch in MIPS16e mode after an
  * exception only. It does not handle compact branches/jumps and cannot
  * be used in interrupt context. (Compact branches/jumps do not cause
  * exceptions.)
  */
 int __MIPS16e_compute_return_epc(struct pt_regs *regs)
 {
 	u16 __user *addr;
 	union mips16e_instruction inst;
 	u16 inst2;
 	u32 fullinst;
 	long epc;
 	epc = regs->cp0_epc;
 	/* Read the instruction. */
 	addr = (u16 __user *)msk_isa16_mode(epc);
 	if (__get_user(inst.full, addr)) {
 		force_sig(SIGSEGV, current);
 		return -EFAULT;
 	}
 	switch (inst.ri.opcode) {
 	case MIPS16e_extend_op:
 		regs->cp0_epc += 4;
 		return 0;
 		/*
 		 *  JAL and JALX in MIPS16e mode
 		 */
 	case MIPS16e_jal_op:
 		addr += 1;
 		if (__get_user(inst2, addr)) {
 			force_sig(SIGSEGV, current);
 			return -EFAULT;
 		}
 		fullinst = ((unsigned)inst.full << 16) | inst2;
 		regs->regs[31] = epc + 6;
 		epc += 4;
 		epc >>= 28;
 		epc <<= 28;
 		/*
 		 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
 		 *
 		 * ......TARGET[15:0].................TARGET[20:16]...........
 		 * ......TARGET[25:21]
 		 */
 		epc |=
 		    ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
 		    ((fullinst & 0x1f0000) << 7);
 		if (!inst.jal.x)
 			set_isa16_mode(epc);	/* Set ISA mode bit. */
 		regs->cp0_epc = epc;
 		return 0;
 		/*
 		 *  J(AL)R(C)
 		 */
 	case MIPS16e_rr_op:
 		if (inst.rr.func == MIPS16e_jr_func) {
 			if (inst.rr.ra)
 				regs->cp0_epc = regs->regs[31];
 			else
 				regs->cp0_epc =
 				    regs->regs[reg16to32[inst.rr.rx]];
 			if (inst.rr.l) {
 				if (inst.rr.nd)
 					regs->regs[31] = epc + 2;
 				else
 					regs->regs[31] = epc + 4;
 			}
 			return 0;
 		}
 		break;
 	}
 	/*
 	 * All other cases have no branch delay slot and are 16-bits.
 	 * Branches do not cause an exception.
 	 */
 	regs->cp0_epc += 2;
 	return 0;
 }
 /**
  * __compute_return_epc_for_insn - Computes the return address and do emulate
  *				    branch simulation, if required.
  *
  * @regs:	Pointer to pt_regs
  * @insn:	branch instruction to decode
  * @returns:	-EFAULT on error and forces SIGBUS, and on success
  *		returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
  *		evaluating the branch.
  */
 int __compute_return_epc_for_insn(struct pt_regs *regs,
 				   union mips_instruction insn)
 {
 	unsigned int bit, fcr31, dspcontrol;
 	long epc = regs->cp0_epc;
 	int ret = 0;
 	switch (insn.i_format.opcode) {
 	/*
 	 * jr and jalr are in r_format format.
 	 */
 	case spec_op:
 		switch (insn.r_format.func) {
 		case jalr_op:
 			regs->regs[insn.r_format.rd] = epc + 8;
 			/* Fall through */
 		case jr_op:
 			regs->cp0_epc = regs->regs[insn.r_format.rs];
 			break;
 		}
 		break;
 	/*
 	 * This group contains:
 	 * bltz_op, bgez_op, bltzl_op, bgezl_op,
 	 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
 	 */
 	case bcond_op:
 		switch (insn.i_format.rt) {
 		case bltz_op:
 		case bltzl_op:
 			if ((long)regs->regs[insn.i_format.rs] < 0) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 				if (insn.i_format.rt == bltzl_op)
 					ret = BRANCH_LIKELY_TAKEN;
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		case bgez_op:
 		case bgezl_op:
 			if ((long)regs->regs[insn.i_format.rs] >= 0) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 				if (insn.i_format.rt == bgezl_op)
 					ret = BRANCH_LIKELY_TAKEN;
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		case bltzal_op:
 		case bltzall_op:
 			regs->regs[31] = epc + 8;
 			if ((long)regs->regs[insn.i_format.rs] < 0) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 				if (insn.i_format.rt == bltzall_op)
 					ret = BRANCH_LIKELY_TAKEN;
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		case bgezal_op:
 		case bgezall_op:
 			regs->regs[31] = epc + 8;
 			if ((long)regs->regs[insn.i_format.rs] >= 0) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 				if (insn.i_format.rt == bgezall_op)
 					ret = BRANCH_LIKELY_TAKEN;
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		case bposge32_op:
 			if (!cpu_has_dsp)
 				goto sigill;
 			dspcontrol = rddsp(0x01);
 			if (dspcontrol >= 32) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		}
 		break;
 	/*
 	 * These are unconditional and in j_format.
 	 */
 	case jal_op:
 		regs->regs[31] = regs->cp0_epc + 8;
 	case j_op:
 		epc += 4;
 		epc >>= 28;
 		epc <<= 28;
 		epc |= (insn.j_format.target << 2);
 		regs->cp0_epc = epc;
 		if (insn.i_format.opcode == jalx_op)
 			set_isa16_mode(regs->cp0_epc);
 		break;
 	/*
 	 * These are conditional and in i_format.
 	 */
 	case beq_op:
 	case beql_op:
 		if (regs->regs[insn.i_format.rs] ==
 		    regs->regs[insn.i_format.rt]) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 			if (insn.i_format.opcode == beql_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	case bne_op:
 	case bnel_op:
 		if (regs->regs[insn.i_format.rs] !=
 		    regs->regs[insn.i_format.rt]) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 			if (insn.i_format.opcode == bnel_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	case blez_op: /* not really i_format */
 	case blezl_op:
 		/* rt field assumed to be zero */
 		if ((long)regs->regs[insn.i_format.rs] <= 0) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 			if (insn.i_format.opcode == blezl_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	case bgtz_op:
 	case bgtzl_op:
 		/* rt field assumed to be zero */
 		if ((long)regs->regs[insn.i_format.rs] > 0) {
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 			if (insn.i_format.opcode == bgtzl_op)
 				ret = BRANCH_LIKELY_TAKEN;
 		} else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	/*
 	 * And now the FPA/cp1 branch instructions.
 	 */
 	case cop1_op:
 		preempt_disable();
 		if (is_fpu_owner())
-			asm volatile(
+		        fcr31 = read_32bit_cp1_register(CP1_STATUS);
-				".set push\n"
-				"\t.set mips1\n"
-				"\tcfc1\t%0,$31\n"
-				"\t.set pop" : "=r" (fcr31));
 		else
 			fcr31 = current->thread.fpu.fcr31;
 		preempt_enable();
 		bit = (insn.i_format.rt >> 2);
 		bit += (bit != 0);
 		bit += 23;
 		switch (insn.i_format.rt & 3) {
 		case 0: /* bc1f */
 		case 2: /* bc1fl */
 			if (~fcr31 & (1 << bit)) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 				if (insn.i_format.rt == 2)
 					ret = BRANCH_LIKELY_TAKEN;
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		case 1: /* bc1t */
 		case 3: /* bc1tl */
 			if (fcr31 & (1 << bit)) {
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 				if (insn.i_format.rt == 3)
 					ret = BRANCH_LIKELY_TAKEN;
 			} else
 				epc += 8;
 			regs->cp0_epc = epc;
 			break;
 		}
 		break;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	case lwc2_op: /* This is bbit0 on Octeon */
 		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 		     == 0)
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	case ldc2_op: /* This is bbit032 on Octeon */
 		if ((regs->regs[insn.i_format.rs] &
 		    (1ull<<(insn.i_format.rt+32))) == 0)
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	case swc2_op: /* This is bbit1 on Octeon */
 		if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 	case sdc2_op: /* This is bbit132 on Octeon */
 		if (regs->regs[insn.i_format.rs] &
 		    (1ull<<(insn.i_format.rt+32)))
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		regs->cp0_epc = epc;
 		break;
 #endif
 	}
 	return ret;
 sigill:
 	printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
 	force_sig(SIGBUS, current);
 	return -EFAULT;
 }
 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
 int __compute_return_epc(struct pt_regs *regs)
 {
 	unsigned int __user *addr;
 	long epc;
 	union mips_instruction insn;
 	epc = regs->cp0_epc;
 	if (epc & 3)
 		goto unaligned;
 	/*
 	 * Read the instruction
 	 */
 	addr = (unsigned int __user *) epc;
 	if (__get_user(insn.word, addr)) {
 		force_sig(SIGSEGV, current);
 		return -EFAULT;
 	}
 	return __compute_return_epc_for_insn(regs, insn);
 unaligned:
 	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
 	force_sig(SIGBUS, current);
 	return -EFAULT;
 }

arch/mips/kernel/genex.S

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 2002, 2007  Maciej W. Rozycki
  * Copyright (C) 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
  */
 #include <linux/init.h>
 #include <asm/asm.h>
 #include <asm/asmmacro.h>
 #include <asm/cacheops.h>
 #include <asm/irqflags.h>
 #include <asm/regdef.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
 #include <asm/war.h>
 #include <asm/thread_info.h>
 	__INIT
 /*
  * General exception vector for all other CPUs.
  *
  * Be careful when changing this, it has to be at most 128 bytes
  * to fit into space reserved for the exception handler.
  */
 NESTED(except_vec3_generic, 0, sp)
 	.set	push
 	.set	noat
 #if R5432_CP0_INTERRUPT_WAR
 	mfc0	k0, CP0_INDEX
 #endif
 	mfc0	k1, CP0_CAUSE
 	andi	k1, k1, 0x7c
 #ifdef CONFIG_64BIT
 	dsll	k1, k1, 1
 #endif
 	PTR_L	k0, exception_handlers(k1)
 	jr	k0
 	.set	pop
 	END(except_vec3_generic)
 /*
  * General exception handler for CPUs with virtual coherency exception.
  *
  * Be careful when changing this, it has to be at most 256 (as a special
  * exception) bytes to fit into space reserved for the exception handler.
  */
 NESTED(except_vec3_r4000, 0, sp)
 	.set	push
 	.set	arch=r4000
 	.set	noat
 	mfc0	k1, CP0_CAUSE
 	li	k0, 31<<2
 	andi	k1, k1, 0x7c
 	.set	push
 	.set	noreorder
 	.set	nomacro
 	beq	k1, k0, handle_vced
 	 li	k0, 14<<2
 	beq	k1, k0, handle_vcei
 #ifdef CONFIG_64BIT
 	 dsll	k1, k1, 1
 #endif
 	.set	pop
 	PTR_L	k0, exception_handlers(k1)
 	jr	k0
 	/*
 	 * Big shit, we now may have two dirty primary cache lines for the same
 	 * physical address.  We can safely invalidate the line pointed to by
 	 * c0_badvaddr because after return from this exception handler the
 	 * load / store will be re-executed.
 	 */
 handle_vced:
 	MFC0	k0, CP0_BADVADDR
 	li	k1, -4					# Is this ...
 	and	k0, k1					# ... really needed?
 	mtc0	zero, CP0_TAGLO
 	cache	Index_Store_Tag_D, (k0)
 	cache	Hit_Writeback_Inv_SD, (k0)
 #ifdef CONFIG_PROC_FS
 	PTR_LA	k0, vced_count
 	lw	k1, (k0)
 	addiu	k1, 1
 	sw	k1, (k0)
 #endif
 	eret
 handle_vcei:
 	MFC0	k0, CP0_BADVADDR
 	cache	Hit_Writeback_Inv_SD, (k0)		# also cleans pi
 #ifdef CONFIG_PROC_FS
 	PTR_LA	k0, vcei_count
 	lw	k1, (k0)
 	addiu	k1, 1
 	sw	k1, (k0)
 #endif
 	eret
 	.set	pop
 	END(except_vec3_r4000)
 	__FINIT
 	.align	5	/* 32 byte rollback region */
 LEAF(__r4k_wait)
 	.set	push
 	.set	noreorder
 	/* start of rollback region */
 	LONG_L	t0, TI_FLAGS($28)
 	nop
 	andi	t0, _TIF_NEED_RESCHED
 	bnez	t0, 1f
 	 nop
 	nop
 	nop
 #ifdef CONFIG_CPU_MICROMIPS
 	nop
 	nop
 	nop
 	nop
 #endif
 	.set	arch=r4000
 	wait
 	/* end of rollback region (the region size must be power of two) */
 1:
 	jr	ra
 	nop
 	.set	pop
 	END(__r4k_wait)
 	.macro	BUILD_ROLLBACK_PROLOGUE handler
 	FEXPORT(rollback_\handler)
 	.set	push
 	.set	noat
 	MFC0	k0, CP0_EPC
 	PTR_LA	k1, __r4k_wait
 	ori	k0, 0x1f	/* 32 byte rollback region */
 	xori	k0, 0x1f
 	bne	k0, k1, 9f
 	MTC0	k0, CP0_EPC
 9:
 	.set pop
 	.endm
 	.align	5
 BUILD_ROLLBACK_PROLOGUE handle_int
 NESTED(handle_int, PT_SIZE, sp)
 #ifdef CONFIG_TRACE_IRQFLAGS
 	/*
 	 * Check to see if the interrupted code has just disabled
 	 * interrupts and ignore this interrupt for now if so.
 	 *
 	 * local_irq_disable() disables interrupts and then calls
 	 * trace_hardirqs_off() to track the state. If an interrupt is taken
 	 * after interrupts are disabled but before the state is updated
 	 * it will appear to restore_all that it is incorrectly returning with
 	 * interrupts disabled
 	 */
 	.set	push
 	.set	noat
 	mfc0	k0, CP0_STATUS
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 	and	k0, ST0_IEP
 	bnez	k0, 1f
 	mfc0	k0, CP0_EPC
 	.set	noreorder
 	j	k0
 	rfe
 #else
 	and	k0, ST0_IE
 	bnez	k0, 1f
 	eret
 #endif
 1:
 	.set pop
 #endif
 	SAVE_ALL
 	CLI
 	TRACE_IRQS_OFF
 	LONG_L	s0, TI_REGS($28)
 	LONG_S	sp, TI_REGS($28)
 	PTR_LA	ra, ret_from_irq
 	PTR_LA  v0, plat_irq_dispatch
 	jr	v0
 #ifdef CONFIG_CPU_MICROMIPS
 	nop
 #endif
 	END(handle_int)
 	__INIT
 /*
  * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
  * This is a dedicated interrupt exception vector which reduces the
  * interrupt processing overhead.  The jump instruction will be replaced
  * at the initialization time.
  *
  * Be careful when changing this, it has to be at most 128 bytes
  * to fit into space reserved for the exception handler.
  */
 NESTED(except_vec4, 0, sp)
 1:	j	1b			/* Dummy, will be replaced */
 	END(except_vec4)
 /*
  * EJTAG debug exception handler.
  * The EJTAG debug exception entry point is 0xbfc00480, which
  * normally is in the boot PROM, so the boot PROM must do an
  * unconditional jump to this vector.
  */
 NESTED(except_vec_ejtag_debug, 0, sp)
 	j	ejtag_debug_handler
 #ifdef CONFIG_CPU_MICROMIPS
 	 nop
 #endif
 	END(except_vec_ejtag_debug)
 	__FINIT
 /*
  * Vectored interrupt handler.
  * This prototype is copied to ebase + n*IntCtl.VS and patched
  * to invoke the handler
  */
 BUILD_ROLLBACK_PROLOGUE except_vec_vi
 NESTED(except_vec_vi, 0, sp)
 	SAVE_SOME
 	SAVE_AT
 	.set	push
 	.set	noreorder
 	PTR_LA	v1, except_vec_vi_handler
 FEXPORT(except_vec_vi_lui)
 	lui	v0, 0		/* Patched */
 	jr	v1
 FEXPORT(except_vec_vi_ori)
 	 ori	v0, 0		/* Patched */
 	.set	pop
 	END(except_vec_vi)
 EXPORT(except_vec_vi_end)
 /*
  * Common Vectored Interrupt code
  * Complete the register saves and invoke the handler which is passed in $v0
  */
 NESTED(except_vec_vi_handler, 0, sp)
 	SAVE_TEMP
 	SAVE_STATIC
 	CLI
 #ifdef CONFIG_TRACE_IRQFLAGS
 	move	s0, v0
 	TRACE_IRQS_OFF
 	move	v0, s0
 #endif
 	LONG_L	s0, TI_REGS($28)
 	LONG_S	sp, TI_REGS($28)
 	PTR_LA	ra, ret_from_irq
 	jr	v0
 	END(except_vec_vi_handler)
 /*
  * EJTAG debug exception handler.
  */
 NESTED(ejtag_debug_handler, PT_SIZE, sp)
 	.set	push
 	.set	noat
 	MTC0	k0, CP0_DESAVE
 	mfc0	k0, CP0_DEBUG
 	sll	k0, k0, 30	# Check for SDBBP.
 	bgez	k0, ejtag_return
 	PTR_LA	k0, ejtag_debug_buffer
 	LONG_S	k1, 0(k0)
 	SAVE_ALL
 	move	a0, sp
 	jal	ejtag_exception_handler
 	RESTORE_ALL
 	PTR_LA	k0, ejtag_debug_buffer
 	LONG_L	k1, 0(k0)
 ejtag_return:
 	MFC0	k0, CP0_DESAVE
 	.set	mips32
 	deret
 	.set pop
 	END(ejtag_debug_handler)
 /*
  * This buffer is reserved for the use of the EJTAG debug
  * handler.
  */
 	.data
 EXPORT(ejtag_debug_buffer)
 	.fill	LONGSIZE
 	.previous
 	__INIT
 /*
  * NMI debug exception handler for MIPS reference boards.
  * The NMI debug exception entry point is 0xbfc00000, which
  * normally is in the boot PROM, so the boot PROM must do a
  * unconditional jump to this vector.
  */
 NESTED(except_vec_nmi, 0, sp)
 	j	nmi_handler
 #ifdef CONFIG_CPU_MICROMIPS
 	 nop
 #endif
 	END(except_vec_nmi)
 	__FINIT
 NESTED(nmi_handler, PT_SIZE, sp)
 	.set	push
 	.set	noat
 	/*
 	 * Clear ERL - restore segment mapping
 	 * Clear BEV - required for page fault exception handler to work
 	 */
 	mfc0	k0, CP0_STATUS
 	ori     k0, k0, ST0_EXL
 	li	k1, ~(ST0_BEV | ST0_ERL)
 	and     k0, k0, k1
 	mtc0    k0, CP0_STATUS
 	_ehb
 	SAVE_ALL
 	move	a0, sp
 	jal	nmi_exception_handler
 	/* nmi_exception_handler never returns */
 	.set	pop
 	END(nmi_handler)
 	.macro	__build_clear_none
 	.endm
 	.macro	__build_clear_sti
 	TRACE_IRQS_ON
 	STI
 	.endm
 	.macro	__build_clear_cli
 	CLI
 	TRACE_IRQS_OFF
 	.endm
 	.macro	__build_clear_fpe
 	.set	push
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
 	.set	mips1
+	SET_HARDFLOAT
 	cfc1	a1, fcr31
 	li	a2, ~(0x3f << 12)
 	and	a2, a1
 	ctc1	a2, fcr31
 	.set	pop
 	TRACE_IRQS_ON
 	STI
 	.endm
 	.macro	__build_clear_ade
 	MFC0	t0, CP0_BADVADDR
 	PTR_S	t0, PT_BVADDR(sp)
 	KMODE
 	.endm
 	.macro	__BUILD_silent exception
 	.endm
 	/* Gas tries to parse the PRINT argument as a string containing
 	   string escapes and emits bogus warnings if it believes to
 	   recognize an unknown escape code.  So make the arguments
 	   start with an n and gas will believe \n is ok ...  */
 	.macro	__BUILD_verbose nexception
 	LONG_L	a1, PT_EPC(sp)
 #ifdef CONFIG_32BIT
 	PRINT("Got \nexception at %08lx\012")
 #endif
 #ifdef CONFIG_64BIT
 	PRINT("Got \nexception at %016lx\012")
 #endif
 	.endm
 	.macro	__BUILD_count exception
 	LONG_L	t0,exception_count_\exception
 	LONG_ADDIU t0, 1
 	LONG_S	t0,exception_count_\exception
 	.comm	exception_count\exception, 8, 8
 	.endm
 	.macro	__BUILD_HANDLER exception handler clear verbose ext
 	.align	5
 	NESTED(handle_\exception, PT_SIZE, sp)
 	.set	noat
 	SAVE_ALL
 	FEXPORT(handle_\exception\ext)
 	__BUILD_clear_\clear
 	.set	at
 	__BUILD_\verbose \exception
 	move	a0, sp
 	PTR_LA	ra, ret_from_exception
 	j	do_\handler
 	END(handle_\exception)
 	.endm
 	.macro	BUILD_HANDLER exception handler clear verbose
 	__BUILD_HANDLER \exception \handler \clear \verbose _int
 	.endm
 	BUILD_HANDLER adel ade ade silent		/* #4  */
 	BUILD_HANDLER ades ade ade silent		/* #5  */
 	BUILD_HANDLER ibe be cli silent			/* #6  */
 	BUILD_HANDLER dbe be cli silent			/* #7  */
 	BUILD_HANDLER bp bp sti silent			/* #9  */
 	BUILD_HANDLER ri ri sti silent			/* #10 */
 	BUILD_HANDLER cpu cpu sti silent		/* #11 */
 	BUILD_HANDLER ov ov sti silent			/* #12 */
 	BUILD_HANDLER tr tr sti silent			/* #13 */
 	BUILD_HANDLER msa_fpe msa_fpe sti silent	/* #14 */
 	BUILD_HANDLER fpe fpe fpe silent		/* #15 */
 	BUILD_HANDLER ftlb ftlb none silent		/* #16 */
 	BUILD_HANDLER msa msa sti silent		/* #21 */
 	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */
 #ifdef	CONFIG_HARDWARE_WATCHPOINTS
 	/*
 	 * For watch, interrupts will be enabled after the watch
 	 * registers are read.
 	 */
 	BUILD_HANDLER watch watch cli silent		/* #23 */
 #else
 	BUILD_HANDLER watch watch sti verbose		/* #23 */
 #endif
 	BUILD_HANDLER mcheck mcheck cli verbose		/* #24 */
 	BUILD_HANDLER mt mt sti silent			/* #25 */
 	BUILD_HANDLER dsp dsp sti silent		/* #26 */
 	BUILD_HANDLER reserved reserved sti verbose	/* others */
 	.align	5
 	LEAF(handle_ri_rdhwr_vivt)
 	.set	push
 	.set	noat
 	.set	noreorder
 	/* check if TLB contains a entry for EPC */
 	MFC0	k1, CP0_ENTRYHI
 	andi	k1, 0xff	/* ASID_MASK */
 	MFC0	k0, CP0_EPC
 	PTR_SRL k0, _PAGE_SHIFT + 1
 	PTR_SLL k0, _PAGE_SHIFT + 1
 	or	k1, k0
 	MTC0	k1, CP0_ENTRYHI
 	mtc0_tlbw_hazard
 	tlbp
 	tlb_probe_hazard
 	mfc0	k1, CP0_INDEX
 	.set	pop
 	bltz	k1, handle_ri	/* slow path */
 	/* fall thru */
 	END(handle_ri_rdhwr_vivt)
 	LEAF(handle_ri_rdhwr)
 	.set	push
 	.set	noat
 	.set	noreorder
 	/* MIPS32:    0x7c03e83b: rdhwr v1,$29 */
 	/* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
 	MFC0	k1, CP0_EPC
 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
 	and     k0, k1, 1
 	beqz    k0, 1f
 	xor     k1, k0
 	lhu     k0, (k1)
 	lhu     k1, 2(k1)
 	ins     k1, k0, 16, 16
 	lui     k0, 0x007d
 	b       docheck
 	ori     k0, 0x6b3c
 1:
 	lui     k0, 0x7c03
 	lw      k1, (k1)
 	ori     k0, 0xe83b
 #else
 	andi    k0, k1, 1
 	bnez    k0, handle_ri
 	lui     k0, 0x7c03
 	lw      k1, (k1)
 	ori     k0, 0xe83b
 #endif
 	.set    reorder
 docheck:
 	bne	k0, k1, handle_ri	/* if not ours */
 isrdhwr:
 	/* The insn is rdhwr.  No need to check CAUSE.BD here. */
 	get_saved_sp	/* k1 := current_thread_info */
 	.set	noreorder
 	MFC0	k0, CP0_EPC
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 	ori	k1, _THREAD_MASK
 	xori	k1, _THREAD_MASK
 	LONG_L	v1, TI_TP_VALUE(k1)
 	LONG_ADDIU	k0, 4
 	jr	k0
 	 rfe
 #else
 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
 	LONG_ADDIU	k0, 4		/* stall on $k0 */
 #else
 	.set	at=v1
 	LONG_ADDIU	k0, 4
 	.set	noat
 #endif
 	MTC0	k0, CP0_EPC
 	/* I hope three instructions between MTC0 and ERET are enough... */
 	ori	k1, _THREAD_MASK
 	xori	k1, _THREAD_MASK
 	LONG_L	v1, TI_TP_VALUE(k1)
 	.set	arch=r4000
 	eret
 	.set	mips0
 #endif
 	.set	pop
 	END(handle_ri_rdhwr)
 #ifdef CONFIG_64BIT
 /* A temporary overflow handler used by check_daddi(). */
 	__INIT
 	BUILD_HANDLER  daddi_ov daddi_ov none silent	/* #12 */
 #endif

arch/mips/kernel/r2300_fpu.S

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996, 1998 by Ralf Baechle
  *
  * Multi-arch abstraction and asm macros for easier reading:
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  *
  * Further modifications to make this work:
  * Copyright (c) 1998 Harald Koerfgen
  */
 #include <asm/asm.h>
 #include <asm/errno.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 #define EX(a,b)							\
 9:	a,##b;							\
 	.section __ex_table,"a";				\
 	PTR	9b,bad_stack;					\
 	.previous
 	.set	noreorder
 	.set	mips1
 	/* Save floating point context */
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	li	v0, 0					# assume success
 	cfc1	t1,fcr31
 	EX(swc1 $f0,(SC_FPREGS+0)(a0))
 	EX(swc1 $f1,(SC_FPREGS+8)(a0))
 	EX(swc1 $f2,(SC_FPREGS+16)(a0))
 	EX(swc1 $f3,(SC_FPREGS+24)(a0))
 	EX(swc1 $f4,(SC_FPREGS+32)(a0))
 	EX(swc1 $f5,(SC_FPREGS+40)(a0))
 	EX(swc1 $f6,(SC_FPREGS+48)(a0))
 	EX(swc1 $f7,(SC_FPREGS+56)(a0))
 	EX(swc1 $f8,(SC_FPREGS+64)(a0))
 	EX(swc1 $f9,(SC_FPREGS+72)(a0))
 	EX(swc1 $f10,(SC_FPREGS+80)(a0))
 	EX(swc1 $f11,(SC_FPREGS+88)(a0))
 	EX(swc1 $f12,(SC_FPREGS+96)(a0))
 	EX(swc1 $f13,(SC_FPREGS+104)(a0))
 	EX(swc1 $f14,(SC_FPREGS+112)(a0))
 	EX(swc1 $f15,(SC_FPREGS+120)(a0))
 	EX(swc1 $f16,(SC_FPREGS+128)(a0))
 	EX(swc1 $f17,(SC_FPREGS+136)(a0))
 	EX(swc1 $f18,(SC_FPREGS+144)(a0))
 	EX(swc1 $f19,(SC_FPREGS+152)(a0))
 	EX(swc1 $f20,(SC_FPREGS+160)(a0))
 	EX(swc1 $f21,(SC_FPREGS+168)(a0))
 	EX(swc1 $f22,(SC_FPREGS+176)(a0))
 	EX(swc1 $f23,(SC_FPREGS+184)(a0))
 	EX(swc1 $f24,(SC_FPREGS+192)(a0))
 	EX(swc1 $f25,(SC_FPREGS+200)(a0))
 	EX(swc1 $f26,(SC_FPREGS+208)(a0))
 	EX(swc1 $f27,(SC_FPREGS+216)(a0))
 	EX(swc1 $f28,(SC_FPREGS+224)(a0))
 	EX(swc1 $f29,(SC_FPREGS+232)(a0))
 	EX(swc1 $f30,(SC_FPREGS+240)(a0))
 	EX(swc1 $f31,(SC_FPREGS+248)(a0))
 	EX(sw	t1,(SC_FPC_CSR)(a0))
 	cfc1	t0,$0				# implementation/version
 	jr	ra
+	.set	pop
 	.set	nomacro
 	 EX(sw	t0,(SC_FPC_EIR)(a0))
 	.set	macro
 	END(_save_fp_context)
 /*
  * Restore FPU state:
  *  - fp gp registers
  *  - cp1 status/control register
  *
  * We base the decision which registers to restore from the signal stack
  * frame on the current content of c0_status, not on the content of the
  * stack frame which might have been changed by the user.
  */
 LEAF(_restore_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	li	v0, 0					# assume success
 	EX(lw t0,(SC_FPC_CSR)(a0))
 	EX(lwc1 $f0,(SC_FPREGS+0)(a0))
 	EX(lwc1 $f1,(SC_FPREGS+8)(a0))
 	EX(lwc1 $f2,(SC_FPREGS+16)(a0))
 	EX(lwc1 $f3,(SC_FPREGS+24)(a0))
 	EX(lwc1 $f4,(SC_FPREGS+32)(a0))
 	EX(lwc1 $f5,(SC_FPREGS+40)(a0))
 	EX(lwc1 $f6,(SC_FPREGS+48)(a0))
 	EX(lwc1 $f7,(SC_FPREGS+56)(a0))
 	EX(lwc1 $f8,(SC_FPREGS+64)(a0))
 	EX(lwc1 $f9,(SC_FPREGS+72)(a0))
 	EX(lwc1 $f10,(SC_FPREGS+80)(a0))
 	EX(lwc1 $f11,(SC_FPREGS+88)(a0))
 	EX(lwc1 $f12,(SC_FPREGS+96)(a0))
 	EX(lwc1 $f13,(SC_FPREGS+104)(a0))
 	EX(lwc1 $f14,(SC_FPREGS+112)(a0))
 	EX(lwc1 $f15,(SC_FPREGS+120)(a0))
 	EX(lwc1 $f16,(SC_FPREGS+128)(a0))
 	EX(lwc1 $f17,(SC_FPREGS+136)(a0))
 	EX(lwc1 $f18,(SC_FPREGS+144)(a0))
 	EX(lwc1 $f19,(SC_FPREGS+152)(a0))
 	EX(lwc1 $f20,(SC_FPREGS+160)(a0))
 	EX(lwc1 $f21,(SC_FPREGS+168)(a0))
 	EX(lwc1 $f22,(SC_FPREGS+176)(a0))
 	EX(lwc1 $f23,(SC_FPREGS+184)(a0))
 	EX(lwc1 $f24,(SC_FPREGS+192)(a0))
 	EX(lwc1 $f25,(SC_FPREGS+200)(a0))
 	EX(lwc1 $f26,(SC_FPREGS+208)(a0))
 	EX(lwc1 $f27,(SC_FPREGS+216)(a0))
 	EX(lwc1 $f28,(SC_FPREGS+224)(a0))
 	EX(lwc1 $f29,(SC_FPREGS+232)(a0))
 	EX(lwc1 $f30,(SC_FPREGS+240)(a0))
 	EX(lwc1 $f31,(SC_FPREGS+248)(a0))
 	jr	ra
 	 ctc1	t0,fcr31
+	.set	pop
 	END(_restore_fp_context)
 	.set	reorder
 	.type	fault@function
 	.ent	fault
 fault:	li	v0, -EFAULT
 	jr	ra
 	.end	fault

arch/mips/kernel/r2300_switch.S

Diff comments View file @ 842dfc1

 /*
  * r2300_switch.S: R2300 specific task switching code.
  *
  * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
  * Copyright (C) 1994, 1995, 1996 by Andreas Busse
  *
  * Multi-cpu abstraction and macros for easier reading:
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  *
  * Further modifications to make this work:
  * Copyright (c) 1998-2000 Harald Koerfgen
  */
 #include <asm/asm.h>
 #include <asm/cachectl.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 #include <asm/thread_info.h>
 #include <asm/asmmacro.h>
 	.set	mips1
 	.align	5
 /*
  * Offset to the current process status flags, the first 32 bytes of the
  * stack are not used.
  */
 #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
 /*
  * FPU context is saved iff the process has used it's FPU in the current
  * time slice as indicated by TIF_USEDFPU.  In any case, the CU1 bit for user
  * space STATUS register should be 0, so that a process *always* starts its
  * userland with FPU disabled after each context switch.
  *
  * FPU will be enabled as soon as the process accesses FPU again, through
  * do_cpu() trap.
  */
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
  *		       struct thread_info *next_ti, int usedfpu)
  */
 LEAF(resume)
 	mfc0	t1, CP0_STATUS
 	sw	t1, THREAD_STATUS(a0)
 	cpu_save_nonscratch a0
 	sw	ra, THREAD_REG31(a0)
 	beqz	a3, 1f
 	PTR_L	t3, TASK_THREAD_INFO(a0)
 	/*
 	 * clear saved user stack CU1 bit
 	 */
 	lw	t0, ST_OFF(t3)
 	li	t1, ~ST0_CU1
 	and	t0, t0, t1
 	sw	t0, ST_OFF(t3)
 	fpu_save_single a0, t0			# clobbers t0
 1:
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	PTR_LA	t8, __stack_chk_guard
 	LONG_L	t9, TASK_STACK_CANARY(a1)
 	LONG_S	t9, 0(t8)
 #endif
 	/*
 	 * The order of restoring the registers takes care of the race
 	 * updating $28, $29 and kernelsp without disabling ints.
 	 */
 	move	$28, a2
 	cpu_restore_nonscratch a1
 	addiu	t1, $28, _THREAD_SIZE - 32
 	sw	t1, kernelsp
 	mfc0	t1, CP0_STATUS		/* Do we really need this? */
 	li	a3, 0xff01
 	and	t1, a3
 	lw	a2, THREAD_STATUS(a1)
 	nor	a3, $0, a3
 	and	a2, a3
 	or	a2, t1
 	mtc0	a2, CP0_STATUS
 	move	v0, a0
 	jr	ra
 	END(resume)
 /*
  * Save a thread's fp context.
  */
 LEAF(_save_fp)
 	fpu_save_single a0, t1			# clobbers t1
 	jr	ra
 	END(_save_fp)
 /*
  * Restore a thread's fp context.
  */
 LEAF(_restore_fp)
 	fpu_restore_single a0, t1		# clobbers t1
 	jr	ra
 	END(_restore_fp)
 /*
  * Load the FPU with signalling NANS.  This bit pattern we're using has
  * the property that no matter whether considered as single or as double
  * precision represents signaling NANS.
  *
  * We initialize fcr31 to rounding to nearest, no exceptions.
  */
 #define FPU_DEFAULT  0x00000000
+	.set push
+	SET_HARDFLOAT
 LEAF(_init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, ST0_CU1
 	or	t0, t1
 	mtc0	t0, CP0_STATUS
 	li	t1, FPU_DEFAULT
 	ctc1	t1, fcr31
 	li	t0, -1
 	mtc1	t0, $f0
 	mtc1	t0, $f1
 	mtc1	t0, $f2
 	mtc1	t0, $f3
 	mtc1	t0, $f4
 	mtc1	t0, $f5
 	mtc1	t0, $f6
 	mtc1	t0, $f7
 	mtc1	t0, $f8
 	mtc1	t0, $f9
 	mtc1	t0, $f10
 	mtc1	t0, $f11
 	mtc1	t0, $f12
 	mtc1	t0, $f13
 	mtc1	t0, $f14
 	mtc1	t0, $f15
 	mtc1	t0, $f16
 	mtc1	t0, $f17
 	mtc1	t0, $f18
 	mtc1	t0, $f19
 	mtc1	t0, $f20
 	mtc1	t0, $f21
 	mtc1	t0, $f22
 	mtc1	t0, $f23
 	mtc1	t0, $f24
 	mtc1	t0, $f25
 	mtc1	t0, $f26
 	mtc1	t0, $f27
 	mtc1	t0, $f28
 	mtc1	t0, $f29
 	mtc1	t0, $f30
 	mtc1	t0, $f31
 	jr	ra
 	END(_init_fpu)
+	.set pop

arch/mips/kernel/r4k_fpu.S

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
  *
  * Multi-arch abstraction and asm macros for easier reading:
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  *
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.
  * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
  */
 #include <asm/asm.h>
 #include <asm/errno.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
 	.macro	EX insn, reg, src
 	.set	push
+	SET_HARDFLOAT
 	.set	nomacro
 .ex\@:	\insn	\reg, \src
 	.set	pop
 	.section __ex_table,"a"
 	PTR	.ex\@, fault
 	.previous
 	.endm
 	.set	noreorder
 	.set	arch=r4000
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
+	.set	pop
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
+	SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-	.set	mips64r2
+	.set	mips32r2
+	.set	fp=64
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip storing odd if FR=0
 	 nop
 #endif
 	/* Store the 16 odd double precision registers */
 	EX	sdc1 $f1, SC_FPREGS+8(a0)
 	EX	sdc1 $f3, SC_FPREGS+24(a0)
 	EX	sdc1 $f5, SC_FPREGS+40(a0)
 	EX	sdc1 $f7, SC_FPREGS+56(a0)
 	EX	sdc1 $f9, SC_FPREGS+72(a0)
 	EX	sdc1 $f11, SC_FPREGS+88(a0)
 	EX	sdc1 $f13, SC_FPREGS+104(a0)
 	EX	sdc1 $f15, SC_FPREGS+120(a0)
 	EX	sdc1 $f17, SC_FPREGS+136(a0)
 	EX	sdc1 $f19, SC_FPREGS+152(a0)
 	EX	sdc1 $f21, SC_FPREGS+168(a0)
 	EX	sdc1 $f23, SC_FPREGS+184(a0)
 	EX	sdc1 $f25, SC_FPREGS+200(a0)
 	EX	sdc1 $f27, SC_FPREGS+216(a0)
 	EX	sdc1 $f29, SC_FPREGS+232(a0)
 	EX	sdc1 $f31, SC_FPREGS+248(a0)
 1:	.set	pop
 #endif
+	.set push
+	SET_HARDFLOAT
 	/* Store the 16 even double precision registers */
 	EX	sdc1 $f0, SC_FPREGS+0(a0)
 	EX	sdc1 $f2, SC_FPREGS+16(a0)
 	EX	sdc1 $f4, SC_FPREGS+32(a0)
 	EX	sdc1 $f6, SC_FPREGS+48(a0)
 	EX	sdc1 $f8, SC_FPREGS+64(a0)
 	EX	sdc1 $f10, SC_FPREGS+80(a0)
 	EX	sdc1 $f12, SC_FPREGS+96(a0)
 	EX	sdc1 $f14, SC_FPREGS+112(a0)
 	EX	sdc1 $f16, SC_FPREGS+128(a0)
 	EX	sdc1 $f18, SC_FPREGS+144(a0)
 	EX	sdc1 $f20, SC_FPREGS+160(a0)
 	EX	sdc1 $f22, SC_FPREGS+176(a0)
 	EX	sdc1 $f24, SC_FPREGS+192(a0)
 	EX	sdc1 $f26, SC_FPREGS+208(a0)
 	EX	sdc1 $f28, SC_FPREGS+224(a0)
 	EX	sdc1 $f30, SC_FPREGS+240(a0)
 	EX	sw t1, SC_FPC_CSR(a0)
 	jr	ra
 	 li	v0, 0					# success
+	.set pop
 	END(_save_fp_context)
 #ifdef CONFIG_MIPS32_COMPAT
 	/* Save 32-bit process floating point context */
 LEAF(_save_fp_context32)
+	.set push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip storing odd if FR=0
 	 nop
 	/* Store the 16 odd double precision registers */
 	EX      sdc1 $f1, SC32_FPREGS+8(a0)
 	EX      sdc1 $f3, SC32_FPREGS+24(a0)
 	EX      sdc1 $f5, SC32_FPREGS+40(a0)
 	EX      sdc1 $f7, SC32_FPREGS+56(a0)
 	EX      sdc1 $f9, SC32_FPREGS+72(a0)
 	EX      sdc1 $f11, SC32_FPREGS+88(a0)
 	EX      sdc1 $f13, SC32_FPREGS+104(a0)
 	EX      sdc1 $f15, SC32_FPREGS+120(a0)
 	EX      sdc1 $f17, SC32_FPREGS+136(a0)
 	EX      sdc1 $f19, SC32_FPREGS+152(a0)
 	EX      sdc1 $f21, SC32_FPREGS+168(a0)
 	EX      sdc1 $f23, SC32_FPREGS+184(a0)
 	EX      sdc1 $f25, SC32_FPREGS+200(a0)
 	EX      sdc1 $f27, SC32_FPREGS+216(a0)
 	EX      sdc1 $f29, SC32_FPREGS+232(a0)
 	EX      sdc1 $f31, SC32_FPREGS+248(a0)
 	/* Store the 16 even double precision registers */
 1:	EX	sdc1 $f0, SC32_FPREGS+0(a0)
 	EX	sdc1 $f2, SC32_FPREGS+16(a0)
 	EX	sdc1 $f4, SC32_FPREGS+32(a0)
 	EX	sdc1 $f6, SC32_FPREGS+48(a0)
 	EX	sdc1 $f8, SC32_FPREGS+64(a0)
 	EX	sdc1 $f10, SC32_FPREGS+80(a0)
 	EX	sdc1 $f12, SC32_FPREGS+96(a0)
 	EX	sdc1 $f14, SC32_FPREGS+112(a0)
 	EX	sdc1 $f16, SC32_FPREGS+128(a0)
 	EX	sdc1 $f18, SC32_FPREGS+144(a0)
 	EX	sdc1 $f20, SC32_FPREGS+160(a0)
 	EX	sdc1 $f22, SC32_FPREGS+176(a0)
 	EX	sdc1 $f24, SC32_FPREGS+192(a0)
 	EX	sdc1 $f26, SC32_FPREGS+208(a0)
 	EX	sdc1 $f28, SC32_FPREGS+224(a0)
 	EX	sdc1 $f30, SC32_FPREGS+240(a0)
 	EX	sw t1, SC32_FPC_CSR(a0)
 	cfc1	t0, $0				# implementation/version
 	EX	sw t0, SC32_FPC_EIR(a0)
+	.set pop
 	jr	ra
 	 li	v0, 0					# success
 	END(_save_fp_context32)
 #endif
 /*
  * Restore FPU state:
  *  - fp gp registers
  *  - cp1 status/control register
  */
 LEAF(_restore_fp_context)
 	EX	lw t1, SC_FPC_CSR(a0)
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
+	SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-	.set	mips64r2
+	.set	mips32r2
+	.set	fp=64
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip loading odd if FR=0
 	 nop
 #endif
 	EX	ldc1 $f1, SC_FPREGS+8(a0)
 	EX	ldc1 $f3, SC_FPREGS+24(a0)
 	EX	ldc1 $f5, SC_FPREGS+40(a0)
 	EX	ldc1 $f7, SC_FPREGS+56(a0)
 	EX	ldc1 $f9, SC_FPREGS+72(a0)
 	EX	ldc1 $f11, SC_FPREGS+88(a0)
 	EX	ldc1 $f13, SC_FPREGS+104(a0)
 	EX	ldc1 $f15, SC_FPREGS+120(a0)
 	EX	ldc1 $f17, SC_FPREGS+136(a0)
 	EX	ldc1 $f19, SC_FPREGS+152(a0)
 	EX	ldc1 $f21, SC_FPREGS+168(a0)
 	EX	ldc1 $f23, SC_FPREGS+184(a0)
 	EX	ldc1 $f25, SC_FPREGS+200(a0)
 	EX	ldc1 $f27, SC_FPREGS+216(a0)
 	EX	ldc1 $f29, SC_FPREGS+232(a0)
 	EX	ldc1 $f31, SC_FPREGS+248(a0)
 1:	.set pop
 #endif
+	.set push
+	SET_HARDFLOAT
 	EX	ldc1 $f0, SC_FPREGS+0(a0)
 	EX	ldc1 $f2, SC_FPREGS+16(a0)
 	EX	ldc1 $f4, SC_FPREGS+32(a0)
 	EX	ldc1 $f6, SC_FPREGS+48(a0)
 	EX	ldc1 $f8, SC_FPREGS+64(a0)
 	EX	ldc1 $f10, SC_FPREGS+80(a0)
 	EX	ldc1 $f12, SC_FPREGS+96(a0)
 	EX	ldc1 $f14, SC_FPREGS+112(a0)
 	EX	ldc1 $f16, SC_FPREGS+128(a0)
 	EX	ldc1 $f18, SC_FPREGS+144(a0)
 	EX	ldc1 $f20, SC_FPREGS+160(a0)
 	EX	ldc1 $f22, SC_FPREGS+176(a0)
 	EX	ldc1 $f24, SC_FPREGS+192(a0)
 	EX	ldc1 $f26, SC_FPREGS+208(a0)
 	EX	ldc1 $f28, SC_FPREGS+224(a0)
 	EX	ldc1 $f30, SC_FPREGS+240(a0)
 	ctc1	t1, fcr31
+	.set pop
 	jr	ra
 	 li	v0, 0					# success
 	END(_restore_fp_context)
 #ifdef CONFIG_MIPS32_COMPAT
 LEAF(_restore_fp_context32)
 	/* Restore an o32 sigcontext.  */
+	.set push
+	SET_HARDFLOAT
 	EX	lw t1, SC32_FPC_CSR(a0)
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip loading odd if FR=0
 	 nop
 	EX      ldc1 $f1, SC32_FPREGS+8(a0)
 	EX      ldc1 $f3, SC32_FPREGS+24(a0)
 	EX      ldc1 $f5, SC32_FPREGS+40(a0)
 	EX      ldc1 $f7, SC32_FPREGS+56(a0)
 	EX      ldc1 $f9, SC32_FPREGS+72(a0)
 	EX      ldc1 $f11, SC32_FPREGS+88(a0)
 	EX      ldc1 $f13, SC32_FPREGS+104(a0)
 	EX      ldc1 $f15, SC32_FPREGS+120(a0)
 	EX      ldc1 $f17, SC32_FPREGS+136(a0)
 	EX      ldc1 $f19, SC32_FPREGS+152(a0)
 	EX      ldc1 $f21, SC32_FPREGS+168(a0)
 	EX      ldc1 $f23, SC32_FPREGS+184(a0)
 	EX      ldc1 $f25, SC32_FPREGS+200(a0)
 	EX      ldc1 $f27, SC32_FPREGS+216(a0)
 	EX      ldc1 $f29, SC32_FPREGS+232(a0)
 	EX      ldc1 $f31, SC32_FPREGS+248(a0)
 1:	EX	ldc1 $f0, SC32_FPREGS+0(a0)
 	EX	ldc1 $f2, SC32_FPREGS+16(a0)
 	EX	ldc1 $f4, SC32_FPREGS+32(a0)
 	EX	ldc1 $f6, SC32_FPREGS+48(a0)
 	EX	ldc1 $f8, SC32_FPREGS+64(a0)
 	EX	ldc1 $f10, SC32_FPREGS+80(a0)
 	EX	ldc1 $f12, SC32_FPREGS+96(a0)
 	EX	ldc1 $f14, SC32_FPREGS+112(a0)
 	EX	ldc1 $f16, SC32_FPREGS+128(a0)
 	EX	ldc1 $f18, SC32_FPREGS+144(a0)
 	EX	ldc1 $f20, SC32_FPREGS+160(a0)
 	EX	ldc1 $f22, SC32_FPREGS+176(a0)
 	EX	ldc1 $f24, SC32_FPREGS+192(a0)
 	EX	ldc1 $f26, SC32_FPREGS+208(a0)
 	EX	ldc1 $f28, SC32_FPREGS+224(a0)
 	EX	ldc1 $f30, SC32_FPREGS+240(a0)
 	ctc1	t1, fcr31
 	jr	ra
 	 li	v0, 0					# success
+	.set pop
 	END(_restore_fp_context32)
 #endif
 	.set	reorder
 	.type	fault@function
 	.ent	fault
 fault:	li	v0, -EFAULT				# failure
 	jr	ra
 	.end	fault

arch/mips/kernel/r4k_switch.S

Diff comments View file @ 842dfc1

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1994, 1995, 1996, by Andreas Busse
  * Copyright (C) 1999 Silicon Graphics, Inc.
  * Copyright (C) 2000 MIPS Technologies, Inc.
  *    written by Carsten Langgaard, carstenl@mips.com
  */
 #include <asm/asm.h>
 #include <asm/cachectl.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/pgtable-bits.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 #include <asm/thread_info.h>
 #include <asm/asmmacro.h>
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
 /*
  * Offset to the current process status flags, the first 32 bytes of the
  * stack are not used.
  */
 #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
 #ifndef USE_ALTERNATE_RESUME_IMPL
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
  *		       struct thread_info *next_ti, s32 fp_save)
  */
 	.align	5
 	LEAF(resume)
 	mfc0	t1, CP0_STATUS
 	LONG_S	t1, THREAD_STATUS(a0)
 	cpu_save_nonscratch a0
 	LONG_S	ra, THREAD_REG31(a0)
 	/*
 	 * Check whether we need to save any FP context. FP context is saved
 	 * iff the process has used the context with the scalar FPU or the MSA
 	 * ASE in the current time slice, as indicated by _TIF_USEDFPU and
 	 * _TIF_USEDMSA respectively. switch_to will have set fp_save
 	 * accordingly to an FP_SAVE_ enum value.
 	 */
 	beqz	a3, 2f
 	/*
 	 * We do. Clear the saved CU1 bit for prev, such that next time it is
 	 * scheduled it will start in userland with the FPU disabled. If the
 	 * task uses the FPU then it will be enabled again via the do_cpu trap.
 	 * This allows us to lazily restore the FP context.
 	 */
 	PTR_L	t3, TASK_THREAD_INFO(a0)
 	LONG_L	t0, ST_OFF(t3)
 	li	t1, ~ST0_CU1
 	and	t0, t0, t1
 	LONG_S	t0, ST_OFF(t3)
 	/* Check whether we're saving scalar or vector context. */
 	bgtz	a3, 1f
 	/* Save 128b MSA vector context + scalar FP control & status. */
+	.set push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 	msa_save_all	a0
+	.set pop	/* SET_HARDFLOAT */
 	sw	t1, THREAD_FCR31(a0)
 	b	2f
 1:	/* Save 32b/64b scalar FP context. */
 	fpu_save_double a0 t0 t1		# c0_status passed in t0
 						# clobbers t1
 2:
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 	PTR_LA	t8, __stack_chk_guard
 	LONG_L	t9, TASK_STACK_CANARY(a1)
 	LONG_S	t9, 0(t8)
 #endif
 	/*
 	 * The order of restoring the registers takes care of the race
 	 * updating $28, $29 and kernelsp without disabling ints.
 	 */
 	move	$28, a2
 	cpu_restore_nonscratch a1
 	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
 	set_saved_sp	t0, t1, t2
 	mfc0	t1, CP0_STATUS		/* Do we really need this? */
 	li	a3, 0xff01
 	and	t1, a3
 	LONG_L	a2, THREAD_STATUS(a1)
 	nor	a3, $0, a3
 	and	a2, a3
 	or	a2, t1
 	mtc0	a2, CP0_STATUS
 	move	v0, a0
 	jr	ra
 	END(resume)
 #endif /* USE_ALTERNATE_RESUME_IMPL */
 /*
  * Save a thread's fp context.
  */
 LEAF(_save_fp)
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	mfc0	t0, CP0_STATUS
 #endif
 	fpu_save_double a0 t0 t1		# clobbers t1
 	jr	ra
 	END(_save_fp)
 /*
  * Restore a thread's fp context.
  */
 LEAF(_restore_fp)
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	mfc0	t0, CP0_STATUS
 #endif
 	fpu_restore_double a0 t0 t1		# clobbers t1
 	jr	ra
 	END(_restore_fp)
 #ifdef CONFIG_CPU_HAS_MSA
 /*
  * Save a thread's MSA vector context.
  */
 LEAF(_save_msa)
 	msa_save_all	a0
 	jr	ra
 	END(_save_msa)
 /*
  * Restore a thread's MSA vector context.
  */
 LEAF(_restore_msa)
 	msa_restore_all	a0
 	jr	ra
 	END(_restore_msa)
 LEAF(_init_msa_upper)
 	msa_init_all_upper
 	jr	ra
 	END(_init_msa_upper)
 #endif
 /*
  * Load the FPU with signalling NANS.  This bit pattern we're using has
  * the property that no matter whether considered as single or as double
  * precision represents signaling NANS.
  *
  * We initialize fcr31 to rounding to nearest, no exceptions.
  */
 #define FPU_DEFAULT  0x00000000
+	.set push
+	SET_HARDFLOAT
 LEAF(_init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, ST0_CU1
 	or	t0, t1
 	mtc0	t0, CP0_STATUS
 	enable_fpu_hazard
 	li	t1, FPU_DEFAULT
 	ctc1	t1, fcr31
 	li	t1, -1				# SNaN
 #ifdef CONFIG_64BIT
 	sll	t0, t0, 5
 	bgez	t0, 1f				# 16 / 32 register mode?
 	dmtc1	t1, $f1
 	dmtc1	t1, $f3
 	dmtc1	t1, $f5
 	dmtc1	t1, $f7
 	dmtc1	t1, $f9
 	dmtc1	t1, $f11
 	dmtc1	t1, $f13
 	dmtc1	t1, $f15
 	dmtc1	t1, $f17
 	dmtc1	t1, $f19
 	dmtc1	t1, $f21
 	dmtc1	t1, $f23
 	dmtc1	t1, $f25
 	dmtc1	t1, $f27
 	dmtc1	t1, $f29
 	dmtc1	t1, $f31
 1:
 #endif
 #ifdef CONFIG_CPU_MIPS32
 	mtc1	t1, $f0
 	mtc1	t1, $f1
 	mtc1	t1, $f2
 	mtc1	t1, $f3
 	mtc1	t1, $f4
 	mtc1	t1, $f5
 	mtc1	t1, $f6
 	mtc1	t1, $f7
 	mtc1	t1, $f8
 	mtc1	t1, $f9
 	mtc1	t1, $f10
 	mtc1	t1, $f11
 	mtc1	t1, $f12
 	mtc1	t1, $f13
 	mtc1	t1, $f14
 	mtc1	t1, $f15
 	mtc1	t1, $f16
 	mtc1	t1, $f17
 	mtc1	t1, $f18
 	mtc1	t1, $f19
 	mtc1	t1, $f20
 	mtc1	t1, $f21
 	mtc1	t1, $f22
 	mtc1	t1, $f23
 	mtc1	t1, $f24
 	mtc1	t1, $f25
 	mtc1	t1, $f26
 	mtc1	t1, $f27
 	mtc1	t1, $f28
 	mtc1	t1, $f29
 	mtc1	t1, $f30
 	mtc1	t1, $f31
 #ifdef CONFIG_CPU_MIPS32_R2
 	.set    push
-	.set    mips64r2
+	.set    mips32r2
+	.set	fp=64
 	sll     t0, t0, 5			# is Status.FR set?
 	bgez    t0, 1f				# no: skip setting upper 32b
 	mthc1   t1, $f0
 	mthc1   t1, $f1
 	mthc1   t1, $f2
 	mthc1   t1, $f3
 	mthc1   t1, $f4
 	mthc1   t1, $f5
 	mthc1   t1, $f6
 	mthc1   t1, $f7
 	mthc1   t1, $f8
 	mthc1   t1, $f9
 	mthc1   t1, $f10
 	mthc1   t1, $f11
 	mthc1   t1, $f12
 	mthc1   t1, $f13
 	mthc1   t1, $f14
 	mthc1   t1, $f15
 	mthc1   t1, $f16
 	mthc1   t1, $f17
 	mthc1   t1, $f18
 	mthc1   t1, $f19
 	mthc1   t1, $f20
 	mthc1   t1, $f21
 	mthc1   t1, $f22
 	mthc1   t1, $f23
 	mthc1   t1, $f24
 	mthc1   t1, $f25
 	mthc1   t1, $f26
 	mthc1   t1, $f27
 	mthc1   t1, $f28
 	mthc1   t1, $f29
 	mthc1   t1, $f30
 	mthc1   t1, $f31
 1:	.set    pop
 #endif /* CONFIG_CPU_MIPS32_R2 */
 #else
 	.set	arch=r4000
 	dmtc1	t1, $f0
 	dmtc1	t1, $f2
 	dmtc1	t1, $f4
 	dmtc1	t1, $f6
 	dmtc1	t1, $f8
 	dmtc1	t1, $f10
 	dmtc1	t1, $f12
 	dmtc1	t1, $f14
 	dmtc1	t1, $f16
 	dmtc1	t1, $f18
 	dmtc1	t1, $f20
 	dmtc1	t1, $f22
 	dmtc1	t1, $f24
 	dmtc1	t1, $f26
 	dmtc1	t1, $f28
 	dmtc1	t1, $f30
 #endif
 	jr	ra
 	END(_init_fpu)
+	.set pop	/* SET_HARDFLOAT */

arch/mips/kernel/r6000_fpu.S

Diff comments View file @ 842dfc1

 /*
  * r6000_fpu.S: Save/restore floating point context for signal handlers.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996 by Ralf Baechle
  *
  * Multi-arch abstraction and asm macros for easier reading:
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  */
 #include <asm/asm.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 	.set	noreorder
 	.set	mips2
+	.set	push
+	SET_HARDFLOAT
 	/* Save floating point context */
 	LEAF(_save_fp_context)
 	mfc0	t0,CP0_STATUS
 	sll	t0,t0,2
 	bgez	t0,1f
 	 nop
 	cfc1	t1,fcr31
 	/* Store the 16 double precision registers */
 	sdc1	$f0,(SC_FPREGS+0)(a0)
 	sdc1	$f2,(SC_FPREGS+16)(a0)
 	sdc1	$f4,(SC_FPREGS+32)(a0)
 	sdc1	$f6,(SC_FPREGS+48)(a0)
 	sdc1	$f8,(SC_FPREGS+64)(a0)
 	sdc1	$f10,(SC_FPREGS+80)(a0)
 	sdc1	$f12,(SC_FPREGS+96)(a0)
 	sdc1	$f14,(SC_FPREGS+112)(a0)
 	sdc1	$f16,(SC_FPREGS+128)(a0)
 	sdc1	$f18,(SC_FPREGS+144)(a0)
 	sdc1	$f20,(SC_FPREGS+160)(a0)
 	sdc1	$f22,(SC_FPREGS+176)(a0)
 	sdc1	$f24,(SC_FPREGS+192)(a0)
 	sdc1	$f26,(SC_FPREGS+208)(a0)
 	sdc1	$f28,(SC_FPREGS+224)(a0)
 	sdc1	$f30,(SC_FPREGS+240)(a0)
 	jr	ra
 	 sw	t0,SC_FPC_CSR(a0)
 1:	jr	ra
 	 nop
 	END(_save_fp_context)
 /* Restore FPU state:
  *  - fp gp registers
  *  - cp1 status/control register
  *
  * We base the decision which registers to restore from the signal stack
  * frame on the current content of c0_status, not on the content of the
  * stack frame which might have been changed by the user.
  */
 	LEAF(_restore_fp_context)
 	mfc0	t0,CP0_STATUS
 	sll	t0,t0,2
 	bgez	t0,1f
 	 lw	t0,SC_FPC_CSR(a0)
 	/* Restore the 16 double precision registers */
 	ldc1	$f0,(SC_FPREGS+0)(a0)
 	ldc1	$f2,(SC_FPREGS+16)(a0)
 	ldc1	$f4,(SC_FPREGS+32)(a0)
 	ldc1	$f6,(SC_FPREGS+48)(a0)
 	ldc1	$f8,(SC_FPREGS+64)(a0)
 	ldc1	$f10,(SC_FPREGS+80)(a0)
 	ldc1	$f12,(SC_FPREGS+96)(a0)
 	ldc1	$f14,(SC_FPREGS+112)(a0)
 	ldc1	$f16,(SC_FPREGS+128)(a0)
 	ldc1	$f18,(SC_FPREGS+144)(a0)
 	ldc1	$f20,(SC_FPREGS+160)(a0)
 	ldc1	$f22,(SC_FPREGS+176)(a0)
 	ldc1	$f24,(SC_FPREGS+192)(a0)
 	ldc1	$f26,(SC_FPREGS+208)(a0)
 	ldc1	$f28,(SC_FPREGS+224)(a0)
 	ldc1	$f30,(SC_FPREGS+240)(a0)
 	jr	ra
 	 ctc1	t0,fcr31
 1:	jr	ra
 	 nop
 	END(_restore_fp_context)
+	.set pop	/* SET_HARDFLOAT */

arch/mips/math-emu/cp1emu.c

Diff comments View file @ 842dfc1

 /*
  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
  *
  * MIPS floating point support
  * Copyright (C) 1994-2000 Algorithmics Ltd.
  *
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000  MIPS Technologies, Inc.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
  *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  *
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  *
  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  * required for #float(switch) or #float(trap), where it catches all
  * COP1 instructions via the "CoProcessor Unusable" exception.
  *
  * More surprisingly it is also required for #float(ieee), to help out
  * the hardware FPU at the boundaries of the IEEE-754 representation
  * (denormalised values, infinities, underflow, etc).  It is made
  * quite nasty because emulation of some non-COP1 instructions is
  * required, e.g. in branch delay slots.
  *
  * Note if you know that you won't have an FPU, then you'll get much
  * better performance by compiling with -msoft-float!
  */
 #include <linux/sched.h>
 #include <linux/debugfs.h>
 #include <linux/kconfig.h>
 #include <linux/percpu-defs.h>
 #include <linux/perf_event.h>
 #include <asm/branch.h>
 #include <asm/inst.h>
 #include <asm/ptrace.h>
 #include <asm/signal.h>
 #include <asm/uaccess.h>
 #include <asm/processor.h>
 #include <asm/fpu_emulator.h>
 #include <asm/fpu.h>
 #include "ieee754.h"
 /* Function which emulates a floating point instruction. */
 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
 	mips_instruction);
 static int fpux_emu(struct pt_regs *,
 	struct mips_fpu_struct *, mips_instruction, void *__user *);
 /* Control registers */
 #define FPCREG_RID	0	/* $0  = revision id */
 #define FPCREG_CSR	31	/* $31 = csr */
 /* Determine rounding mode from the RM bits of the FCSR */
 #define modeindex(v) ((v) & FPU_CSR_RM)
 /* convert condition code register number to csr bit */
 static const unsigned int fpucondbit[8] = {
 	FPU_CSR_COND0,
 	FPU_CSR_COND1,
 	FPU_CSR_COND2,
 	FPU_CSR_COND3,
 	FPU_CSR_COND4,
 	FPU_CSR_COND5,
 	FPU_CSR_COND6,
 	FPU_CSR_COND7
 };
 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
 /*
  * This functions translates a 32-bit microMIPS instruction
  * into a 32-bit MIPS32 instruction. Returns 0 on success
  * and SIGILL otherwise.
  */
 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
 {
 	union mips_instruction insn = *insn_ptr;
 	union mips_instruction mips32_insn = insn;
 	int func, fmt, op;
 	switch (insn.mm_i_format.opcode) {
 	case mm_ldc132_op:
 		mips32_insn.mm_i_format.opcode = ldc1_op;
 		mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 		mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 		break;
 	case mm_lwc132_op:
 		mips32_insn.mm_i_format.opcode = lwc1_op;
 		mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 		mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 		break;
 	case mm_sdc132_op:
 		mips32_insn.mm_i_format.opcode = sdc1_op;
 		mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 		mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 		break;
 	case mm_swc132_op:
 		mips32_insn.mm_i_format.opcode = swc1_op;
 		mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 		mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 		break;
 	case mm_pool32i_op:
 		/* NOTE: offset is << by 1 if in microMIPS mode. */
 		if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 		    (insn.mm_i_format.rt == mm_bc1t_op)) {
 			mips32_insn.fb_format.opcode = cop1_op;
 			mips32_insn.fb_format.bc = bc_op;
 			mips32_insn.fb_format.flag =
 				(insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 		} else
 			return SIGILL;
 		break;
 	case mm_pool32f_op:
 		switch (insn.mm_fp0_format.func) {
 		case mm_32f_01_op:
 		case mm_32f_11_op:
 		case mm_32f_02_op:
 		case mm_32f_12_op:
 		case mm_32f_41_op:
 		case mm_32f_51_op:
 		case mm_32f_42_op:
 		case mm_32f_52_op:
 			op = insn.mm_fp0_format.func;
 			if (op == mm_32f_01_op)
 				func = madd_s_op;
 			else if (op == mm_32f_11_op)
 				func = madd_d_op;
 			else if (op == mm_32f_02_op)
 				func = nmadd_s_op;
 			else if (op == mm_32f_12_op)
 				func = nmadd_d_op;
 			else if (op == mm_32f_41_op)
 				func = msub_s_op;
 			else if (op == mm_32f_51_op)
 				func = msub_d_op;
 			else if (op == mm_32f_42_op)
 				func = nmsub_s_op;
 			else
 				func = nmsub_d_op;
 			mips32_insn.fp6_format.opcode = cop1x_op;
 			mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 			mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 			mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 			mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 			mips32_insn.fp6_format.func = func;
 			break;
 		case mm_32f_10_op:
 			func = -1;	/* Invalid */
 			op = insn.mm_fp5_format.op & 0x7;
 			if (op == mm_ldxc1_op)
 				func = ldxc1_op;
 			else if (op == mm_sdxc1_op)
 				func = sdxc1_op;
 			else if (op == mm_lwxc1_op)
 				func = lwxc1_op;
 			else if (op == mm_swxc1_op)
 				func = swxc1_op;
 			if (func != -1) {
 				mips32_insn.r_format.opcode = cop1x_op;
 				mips32_insn.r_format.rs =
 					insn.mm_fp5_format.base;
 				mips32_insn.r_format.rt =
 					insn.mm_fp5_format.index;
 				mips32_insn.r_format.rd = 0;
 				mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 				mips32_insn.r_format.func = func;
 			} else
 				return SIGILL;
 			break;
 		case mm_32f_40_op:
 			op = -1;	/* Invalid */
 			if (insn.mm_fp2_format.op == mm_fmovt_op)
 				op = 1;
 			else if (insn.mm_fp2_format.op == mm_fmovf_op)
 				op = 0;
 			if (op != -1) {
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt =
 					sdps_format[insn.mm_fp2_format.fmt];
 				mips32_insn.fp0_format.ft =
 					(insn.mm_fp2_format.cc<<2) + op;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp2_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp2_format.fd;
 				mips32_insn.fp0_format.func = fmovc_op;
 			} else
 				return SIGILL;
 			break;
 		case mm_32f_60_op:
 			func = -1;	/* Invalid */
 			if (insn.mm_fp0_format.op == mm_fadd_op)
 				func = fadd_op;
 			else if (insn.mm_fp0_format.op == mm_fsub_op)
 				func = fsub_op;
 			else if (insn.mm_fp0_format.op == mm_fmul_op)
 				func = fmul_op;
 			else if (insn.mm_fp0_format.op == mm_fdiv_op)
 				func = fdiv_op;
 			if (func != -1) {
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt =
 					sdps_format[insn.mm_fp0_format.fmt];
 				mips32_insn.fp0_format.ft =
 					insn.mm_fp0_format.ft;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp0_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp0_format.fd;
 				mips32_insn.fp0_format.func = func;
 			} else
 				return SIGILL;
 			break;
 		case mm_32f_70_op:
 			func = -1;	/* Invalid */
 			if (insn.mm_fp0_format.op == mm_fmovn_op)
 				func = fmovn_op;
 			else if (insn.mm_fp0_format.op == mm_fmovz_op)
 				func = fmovz_op;
 			if (func != -1) {
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt =
 					sdps_format[insn.mm_fp0_format.fmt];
 				mips32_insn.fp0_format.ft =
 					insn.mm_fp0_format.ft;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp0_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp0_format.fd;
 				mips32_insn.fp0_format.func = func;
 			} else
 				return SIGILL;
 			break;
 		case mm_32f_73_op:    /* POOL32FXF */
 			switch (insn.mm_fp1_format.op) {
 			case mm_movf0_op:
 			case mm_movf1_op:
 			case mm_movt0_op:
 			case mm_movt1_op:
 				if ((insn.mm_fp1_format.op & 0x7f) ==
 				    mm_movf0_op)
 					op = 0;
 				else
 					op = 1;
 				mips32_insn.r_format.opcode = spec_op;
 				mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 				mips32_insn.r_format.rt =
 					(insn.mm_fp4_format.cc << 2) + op;
 				mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 				mips32_insn.r_format.re = 0;
 				mips32_insn.r_format.func = movc_op;
 				break;
 			case mm_fcvtd0_op:
 			case mm_fcvtd1_op:
 			case mm_fcvts0_op:
 			case mm_fcvts1_op:
 				if ((insn.mm_fp1_format.op & 0x7f) ==
 				    mm_fcvtd0_op) {
 					func = fcvtd_op;
 					fmt = swl_format[insn.mm_fp3_format.fmt];
 				} else {
 					func = fcvts_op;
 					fmt = dwl_format[insn.mm_fp3_format.fmt];
 				}
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt = fmt;
 				mips32_insn.fp0_format.ft = 0;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp3_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp3_format.rt;
 				mips32_insn.fp0_format.func = func;
 				break;
 			case mm_fmov0_op:
 			case mm_fmov1_op:
 			case mm_fabs0_op:
 			case mm_fabs1_op:
 			case mm_fneg0_op:
 			case mm_fneg1_op:
 				if ((insn.mm_fp1_format.op & 0x7f) ==
 				    mm_fmov0_op)
 					func = fmov_op;
 				else if ((insn.mm_fp1_format.op & 0x7f) ==
 					 mm_fabs0_op)
 					func = fabs_op;
 				else
 					func = fneg_op;
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt =
 					sdps_format[insn.mm_fp3_format.fmt];
 				mips32_insn.fp0_format.ft = 0;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp3_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp3_format.rt;
 				mips32_insn.fp0_format.func = func;
 				break;
 			case mm_ffloorl_op:
 			case mm_ffloorw_op:
 			case mm_fceill_op:
 			case mm_fceilw_op:
 			case mm_ftruncl_op:
 			case mm_ftruncw_op:
 			case mm_froundl_op:
 			case mm_froundw_op:
 			case mm_fcvtl_op:
 			case mm_fcvtw_op:
 				if (insn.mm_fp1_format.op == mm_ffloorl_op)
 					func = ffloorl_op;
 				else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 					func = ffloor_op;
 				else if (insn.mm_fp1_format.op == mm_fceill_op)
 					func = fceill_op;
 				else if (insn.mm_fp1_format.op == mm_fceilw_op)
 					func = fceil_op;
 				else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 					func = ftruncl_op;
 				else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 					func = ftrunc_op;
 				else if (insn.mm_fp1_format.op == mm_froundl_op)
 					func = froundl_op;
 				else if (insn.mm_fp1_format.op == mm_froundw_op)
 					func = fround_op;
 				else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 					func = fcvtl_op;
 				else
 					func = fcvtw_op;
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt =
 					sd_format[insn.mm_fp1_format.fmt];
 				mips32_insn.fp0_format.ft = 0;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp1_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp1_format.rt;
 				mips32_insn.fp0_format.func = func;
 				break;
 			case mm_frsqrt_op:
 			case mm_fsqrt_op:
 			case mm_frecip_op:
 				if (insn.mm_fp1_format.op == mm_frsqrt_op)
 					func = frsqrt_op;
 				else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 					func = fsqrt_op;
 				else
 					func = frecip_op;
 				mips32_insn.fp0_format.opcode = cop1_op;
 				mips32_insn.fp0_format.fmt =
 					sdps_format[insn.mm_fp1_format.fmt];
 				mips32_insn.fp0_format.ft = 0;
 				mips32_insn.fp0_format.fs =
 					insn.mm_fp1_format.fs;
 				mips32_insn.fp0_format.fd =
 					insn.mm_fp1_format.rt;
 				mips32_insn.fp0_format.func = func;
 				break;
 			case mm_mfc1_op:
 			case mm_mtc1_op:
 			case mm_cfc1_op:
 			case mm_ctc1_op:
 			case mm_mfhc1_op:
 			case mm_mthc1_op:
 				if (insn.mm_fp1_format.op == mm_mfc1_op)
 					op = mfc_op;
 				else if (insn.mm_fp1_format.op == mm_mtc1_op)
 					op = mtc_op;
 				else if (insn.mm_fp1_format.op == mm_cfc1_op)
 					op = cfc_op;
 				else if (insn.mm_fp1_format.op == mm_ctc1_op)
 					op = ctc_op;
 				else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 					op = mfhc_op;
 				else
 					op = mthc_op;
 				mips32_insn.fp1_format.opcode = cop1_op;
 				mips32_insn.fp1_format.op = op;
 				mips32_insn.fp1_format.rt =
 					insn.mm_fp1_format.rt;
 				mips32_insn.fp1_format.fs =
 					insn.mm_fp1_format.fs;
 				mips32_insn.fp1_format.fd = 0;
 				mips32_insn.fp1_format.func = 0;
 				break;
 			default:
 				return SIGILL;
 			}
 			break;
 		case mm_32f_74_op:	/* c.cond.fmt */
 			mips32_insn.fp0_format.opcode = cop1_op;
 			mips32_insn.fp0_format.fmt =
 				sdps_format[insn.mm_fp4_format.fmt];
 			mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 			mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 			mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 			mips32_insn.fp0_format.func =
 				insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 			break;
 		default:
 			return SIGILL;
 		}
 		break;
 	default:
 		return SIGILL;
 	}
 	*insn_ptr = mips32_insn;
 	return 0;
 }
 /*
  * Redundant with logic already in kernel/branch.c,
  * embedded in compute_return_epc.  At some point,
  * a single subroutine should be used across both
  * modules.
  */
 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 			 unsigned long *contpc)
 {
 	union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 	unsigned int fcr31;
 	unsigned int bit = 0;
 	switch (insn.i_format.opcode) {
 	case spec_op:
 		switch (insn.r_format.func) {
 		case jalr_op:
 			regs->regs[insn.r_format.rd] =
 				regs->cp0_epc + dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 			/* Fall through */
 		case jr_op:
 			*contpc = regs->regs[insn.r_format.rs];
 			return 1;
 		}
 		break;
 	case bcond_op:
 		switch (insn.i_format.rt) {
 		case bltzal_op:
 		case bltzall_op:
 			regs->regs[31] = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 			/* Fall through */
 		case bltz_op:
 		case bltzl_op:
 			if ((long)regs->regs[insn.i_format.rs] < 0)
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.i_format.simmediate << 2);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			return 1;
 		case bgezal_op:
 		case bgezall_op:
 			regs->regs[31] = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 			/* Fall through */
 		case bgez_op:
 		case bgezl_op:
 			if ((long)regs->regs[insn.i_format.rs] >= 0)
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					(insn.i_format.simmediate << 2);
 			else
 				*contpc = regs->cp0_epc +
 					dec_insn.pc_inc +
 					dec_insn.next_pc_inc;
 			return 1;
 		}
 		break;
 	case jalx_op:
 		set_isa16_mode(bit);
 	case jal_op:
 		regs->regs[31] = regs->cp0_epc +
 			dec_insn.pc_inc +
 			dec_insn.next_pc_inc;
 		/* Fall through */
 	case j_op:
 		*contpc = regs->cp0_epc + dec_insn.pc_inc;
 		*contpc >>= 28;
 		*contpc <<= 28;
 		*contpc |= (insn.j_format.target << 2);
 		/* Set microMIPS mode bit: XOR for jalx. */
 		*contpc ^= bit;
 		return 1;
 	case beq_op:
 	case beql_op:
 		if (regs->regs[insn.i_format.rs] ==
 		    regs->regs[insn.i_format.rt])
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 		return 1;
 	case bne_op:
 	case bnel_op:
 		if (regs->regs[insn.i_format.rs] !=
 		    regs->regs[insn.i_format.rt])
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 		return 1;
 	case blez_op:
 	case blezl_op:
 		if ((long)regs->regs[insn.i_format.rs] <= 0)
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 		return 1;
 	case bgtz_op:
 	case bgtzl_op:
 		if ((long)regs->regs[insn.i_format.rs] > 0)
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				(insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc +
 				dec_insn.pc_inc +
 				dec_insn.next_pc_inc;
 		return 1;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	case lwc2_op: /* This is bbit0 on Octeon */
 		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc + 8;
 		return 1;
 	case ldc2_op: /* This is bbit032 on Octeon */
 		if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc + 8;
 		return 1;
 	case swc2_op: /* This is bbit1 on Octeon */
 		if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc + 8;
 		return 1;
 	case sdc2_op: /* This is bbit132 on Octeon */
 		if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			*contpc = regs->cp0_epc + 8;
 		return 1;
 #endif
 	case cop0_op:
 	case cop1_op:
 	case cop2_op:
 	case cop1x_op:
 		if (insn.i_format.rs == bc_op) {
 			preempt_disable();
 			if (is_fpu_owner())
-				asm volatile(
+			        fcr31 = read_32bit_cp1_register(CP1_STATUS);
-					".set push\n"
-					"\t.set mips1\n"
-					"\tcfc1\t%0,$31\n"
-					"\t.set pop" : "=r" (fcr31));
 			else
 				fcr31 = current->thread.fpu.fcr31;
 			preempt_enable();
 			bit = (insn.i_format.rt >> 2);
 			bit += (bit != 0);
 			bit += 23;
 			switch (insn.i_format.rt & 3) {
 			case 0:	/* bc1f */
 			case 2:	/* bc1fl */
 				if (~fcr31 & (1 << bit))
 					*contpc = regs->cp0_epc +
 						dec_insn.pc_inc +
 						(insn.i_format.simmediate << 2);
 				else
 					*contpc = regs->cp0_epc +
 						dec_insn.pc_inc +
 						dec_insn.next_pc_inc;
 				return 1;
 			case 1:	/* bc1t */
 			case 3:	/* bc1tl */
 				if (fcr31 & (1 << bit))
 					*contpc = regs->cp0_epc +
 						dec_insn.pc_inc +
 						(insn.i_format.simmediate << 2);
 				else
 					*contpc = regs->cp0_epc +
 						dec_insn.pc_inc +
 						dec_insn.next_pc_inc;
 				return 1;
 			}
 		}
 		break;
 	}
 	return 0;
 }
 /*
  * In the Linux kernel, we support selection of FPR format on the
  * basis of the Status.FR bit.	If an FPU is not present, the FR bit
  * is hardwired to zero, which would imply a 32-bit FPU even for
  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
  * FPU emu is slow and bulky and optimizing this function offers fairly
  * sizeable benefits so we try to be clever and make this function return
  * a constant whenever possible, that is on 64-bit kernels without O32
  * compatibility enabled and on 32-bit without 64-bit FPU support.
  */
 static inline int cop1_64bit(struct pt_regs *xcp)
 {
 	if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 		return 1;
 	else if (config_enabled(CONFIG_32BIT) &&
 		 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 		return 0;
 	return !test_thread_flag(TIF_32BIT_FPREGS);
 }
 #define SIFROMREG(si, x)						\
 do {									\
 	if (cop1_64bit(xcp))						\
 		(si) = (int)get_fpr32(&ctx->fpr[x], 0);			\
 	else								\
 		(si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);	\
 } while (0)
 #define SITOREG(si, x)							\
 do {									\
 	if (cop1_64bit(xcp)) {						\
 		unsigned i;						\
 		set_fpr32(&ctx->fpr[x], 0, si);				\
 		for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)	\
 			set_fpr32(&ctx->fpr[x], i, 0);			\
 	} else {							\
 		set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);		\
 	}								\
 } while (0)
 #define SIFROMHREG(si, x)	((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 #define SITOHREG(si, x)							\
 do {									\
 	unsigned i;							\
 	set_fpr32(&ctx->fpr[x], 1, si);					\
 	for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)		\
 		set_fpr32(&ctx->fpr[x], i, 0);				\
 } while (0)
 #define DIFROMREG(di, x)						\
 	((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 #define DITOREG(di, x)							\
 do {									\
 	unsigned fpr, i;						\
 	fpr = (x) & ~(cop1_64bit(xcp) == 0);				\
 	set_fpr64(&ctx->fpr[fpr], 0, di);				\
 	for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)		\
 		set_fpr64(&ctx->fpr[fpr], i, 0);			\
 } while (0)
 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 #define SPTOREG(sp, x)	SITOREG((sp).bits, x)
 #define DPFROMREG(dp, x)	DIFROMREG((dp).bits, x)
 #define DPTOREG(dp, x)	DITOREG((dp).bits, x)
 /*
  * Emulate the single floating point instruction pointed at by EPC.
  * Two instructions if the instruction is in a branch delay slot.
  */
 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 		struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 {
 	unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 	unsigned int cond, cbit;
 	mips_instruction ir;
 	int likely, pc_inc;
 	u32 __user *wva;
 	u64 __user *dva;
 	u32 value;
 	u32 wval;
 	u64 dval;
 	int sig;
 	/*
 	 * These are giving gcc a gentle hint about what to expect in
 	 * dec_inst in order to do better optimization.
 	 */
 	if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 		unreachable();
 	/* XXX NEC Vr54xx bug workaround */
 	if (delay_slot(xcp)) {
 		if (dec_insn.micro_mips_mode) {
 			if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 				clear_delay_slot(xcp);
 		} else {
 			if (!isBranchInstr(xcp, dec_insn, &contpc))
 				clear_delay_slot(xcp);
 		}
 	}
 	if (delay_slot(xcp)) {
 		/*
 		 * The instruction to be emulated is in a branch delay slot
 		 * which means that we have to	emulate the branch instruction
 		 * BEFORE we do the cop1 instruction.
 		 *
 		 * This branch could be a COP1 branch, but in that case we
 		 * would have had a trap for that instruction, and would not
 		 * come through this route.
 		 *
 		 * Linux MIPS branch emulator operates on context, updating the
 		 * cp0_epc.
 		 */
 		ir = dec_insn.next_insn;  /* process delay slot instr */
 		pc_inc = dec_insn.next_pc_inc;
 	} else {
 		ir = dec_insn.insn;       /* process current instr */
 		pc_inc = dec_insn.pc_inc;
 	}
 	/*
 	 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 	 * instructions, we want to convert microMIPS FPU instructions
 	 * into MIPS32 instructions so that we could reuse all of the
 	 * FPU emulation code.
 	 *
 	 * NOTE: We cannot do this for branch instructions since they
 	 *       are not a subset. Example: Cannot emulate a 16-bit
 	 *       aligned target address with a MIPS32 instruction.
 	 */
 	if (dec_insn.micro_mips_mode) {
 		/*
 		 * If next instruction is a 16-bit instruction, then it
 		 * it cannot be a FPU instruction. This could happen
 		 * since we can be called for non-FPU instructions.
 		 */
 		if ((pc_inc == 2) ||
 			(microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 			 == SIGILL))
 			return SIGILL;
 	}
 emul:
 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 	MIPS_FPU_EMU_INC_STATS(emulated);
 	switch (MIPSInst_OPCODE(ir)) {
 	case ldc1_op:
 		dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 				     MIPSInst_SIMM(ir));
 		MIPS_FPU_EMU_INC_STATS(loads);
 		if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = dva;
 			return SIGBUS;
 		}
 		if (__get_user(dval, dva)) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = dva;
 			return SIGSEGV;
 		}
 		DITOREG(dval, MIPSInst_RT(ir));
 		break;
 	case sdc1_op:
 		dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 				      MIPSInst_SIMM(ir));
 		MIPS_FPU_EMU_INC_STATS(stores);
 		DIFROMREG(dval, MIPSInst_RT(ir));
 		if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = dva;
 			return SIGBUS;
 		}
 		if (__put_user(dval, dva)) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = dva;
 			return SIGSEGV;
 		}
 		break;
 	case lwc1_op:
 		wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 				      MIPSInst_SIMM(ir));
 		MIPS_FPU_EMU_INC_STATS(loads);
 		if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = wva;
 			return SIGBUS;
 		}
 		if (__get_user(wval, wva)) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = wva;
 			return SIGSEGV;
 		}
 		SITOREG(wval, MIPSInst_RT(ir));
 		break;
 	case swc1_op:
 		wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 				      MIPSInst_SIMM(ir));
 		MIPS_FPU_EMU_INC_STATS(stores);
 		SIFROMREG(wval, MIPSInst_RT(ir));
 		if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = wva;
 			return SIGBUS;
 		}
 		if (__put_user(wval, wva)) {
 			MIPS_FPU_EMU_INC_STATS(errors);
 			*fault_addr = wva;
 			return SIGSEGV;
 		}
 		break;
 	case cop1_op:
 		switch (MIPSInst_RS(ir)) {
 		case dmfc_op:
 			if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			/* copregister fs -> gpr[rt] */
 			if (MIPSInst_RT(ir) != 0) {
 				DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 					MIPSInst_RD(ir));
 			}
 			break;
 		case dmtc_op:
 			if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			/* copregister fs <- rt */
 			DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 			break;
 		case mfhc_op:
 			if (!cpu_has_mips_r2)
 				goto sigill;
 			/* copregister rd -> gpr[rt] */
 			if (MIPSInst_RT(ir) != 0) {
 				SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
 					MIPSInst_RD(ir));
 			}
 			break;
 		case mthc_op:
 			if (!cpu_has_mips_r2)
 				goto sigill;
 			/* copregister rd <- gpr[rt] */
 			SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 			break;
 		case mfc_op:
 			/* copregister rd -> gpr[rt] */
 			if (MIPSInst_RT(ir) != 0) {
 				SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 					MIPSInst_RD(ir));
 			}
 			break;
 		case mtc_op:
 			/* copregister rd <- rt */
 			SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 			break;
 		case cfc_op:
 			/* cop control register rd -> gpr[rt] */
 			if (MIPSInst_RD(ir) == FPCREG_CSR) {
 				value = ctx->fcr31;
 				value = (value & ~FPU_CSR_RM) | modeindex(value);
 				pr_debug("%p gpr[%d]<-csr=%08x\n",
 					 (void *) (xcp->cp0_epc),
 					 MIPSInst_RT(ir), value);
 			}
 			else if (MIPSInst_RD(ir) == FPCREG_RID)
 				value = 0;
 			else
 				value = 0;
 			if (MIPSInst_RT(ir))
 				xcp->regs[MIPSInst_RT(ir)] = value;
 			break;
 		case ctc_op:
 			/* copregister rd <- rt */
 			if (MIPSInst_RT(ir) == 0)
 				value = 0;
 			else
 				value = xcp->regs[MIPSInst_RT(ir)];
 			/* we only have one writable control reg
 			 */
 			if (MIPSInst_RD(ir) == FPCREG_CSR) {
 				pr_debug("%p gpr[%d]->csr=%08x\n",
 					 (void *) (xcp->cp0_epc),
 					 MIPSInst_RT(ir), value);
 				/*
 				 * Don't write reserved bits,
 				 * and convert to ieee library modes
 				 */
 				ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
 					     modeindex(value);
 			}
 			if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 				return SIGFPE;
 			}
 			break;
 		case bc_op:
 			if (delay_slot(xcp))
 				return SIGILL;
 			if (cpu_has_mips_4_5_r)
 				cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
 			else
 				cbit = FPU_CSR_COND;
 			cond = ctx->fcr31 & cbit;
 			likely = 0;
 			switch (MIPSInst_RT(ir) & 3) {
 			case bcfl_op:
 				likely = 1;
 			case bcf_op:
 				cond = !cond;
 				break;
 			case bctl_op:
 				likely = 1;
 			case bct_op:
 				break;
 			default:
 				/* thats an illegal instruction */
 				return SIGILL;
 			}
 			set_delay_slot(xcp);
 			if (cond) {
 				/*
 				 * Branch taken: emulate dslot instruction
 				 */
 				xcp->cp0_epc += dec_insn.pc_inc;
 				contpc = MIPSInst_SIMM(ir);
 				ir = dec_insn.next_insn;
 				if (dec_insn.micro_mips_mode) {
 					contpc = (xcp->cp0_epc + (contpc << 1));
 					/* If 16-bit instruction, not FPU. */
 					if ((dec_insn.next_pc_inc == 2) ||
 						(microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
 						/*
 						 * Since this instruction will
 						 * be put on the stack with
 						 * 32-bit words, get around
 						 * this problem by putting a
 						 * NOP16 as the second one.
 						 */
 						if (dec_insn.next_pc_inc == 2)
 							ir = (ir & (~0xffff)) | MM_NOP16;
 						/*
 						 * Single step the non-CP1
 						 * instruction in the dslot.
 						 */
 						return mips_dsemul(xcp, ir, contpc);
 					}
 				} else
 					contpc = (xcp->cp0_epc + (contpc << 2));
 				switch (MIPSInst_OPCODE(ir)) {
 				case lwc1_op:
 					goto emul;
 				case swc1_op:
 					goto emul;
 				case ldc1_op:
 				case sdc1_op:
 					if (cpu_has_mips_2_3_4_5 ||
 					    cpu_has_mips64)
 						goto emul;
 					return SIGILL;
 					goto emul;
 				case cop1_op:
 					goto emul;
 				case cop1x_op:
 					if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
 						/* its one of ours */
 						goto emul;
 					return SIGILL;
 				case spec_op:
 					if (!cpu_has_mips_4_5_r)
 						return SIGILL;
 					if (MIPSInst_FUNC(ir) == movc_op)
 						goto emul;
 					break;
 				}
 				/*
 				 * Single step the non-cp1
 				 * instruction in the dslot
 				 */
 				return mips_dsemul(xcp, ir, contpc);
 			} else if (likely) {	/* branch not taken */
 					/*
 					 * branch likely nullifies
 					 * dslot if not taken
 					 */
 					xcp->cp0_epc += dec_insn.pc_inc;
 					contpc += dec_insn.pc_inc;
 					/*
 					 * else continue & execute
 					 * dslot as normal insn
 					 */
 				}
 			break;
 		default:
 			if (!(MIPSInst_RS(ir) & 0x10))
 				return SIGILL;
 			/* a real fpu computation instruction */
 			if ((sig = fpu_emu(xcp, ctx, ir)))
 				return sig;
 		}
 		break;
 	case cop1x_op:
 		if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
 			return SIGILL;
 		sig = fpux_emu(xcp, ctx, ir, fault_addr);
 		if (sig)
 			return sig;
 		break;
 	case spec_op:
 		if (!cpu_has_mips_4_5_r)
 			return SIGILL;
 		if (MIPSInst_FUNC(ir) != movc_op)
 			return SIGILL;
 		cond = fpucondbit[MIPSInst_RT(ir) >> 2];
 		if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
 			xcp->regs[MIPSInst_RD(ir)] =
 				xcp->regs[MIPSInst_RS(ir)];
 		break;
 	default:
 sigill:
 		return SIGILL;
 	}
 	/* we did it !! */
 	xcp->cp0_epc = contpc;
 	clear_delay_slot(xcp);
 	return 0;
 }
 /*
  * Conversion table from MIPS compare ops 48-63
  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
  */
 static const unsigned char cmptab[8] = {
 	0,			/* cmp_0 (sig) cmp_sf */
 	IEEE754_CUN,		/* cmp_un (sig) cmp_ngle */
 	IEEE754_CEQ,		/* cmp_eq (sig) cmp_seq */
 	IEEE754_CEQ | IEEE754_CUN,	/* cmp_ueq (sig) cmp_ngl  */
 	IEEE754_CLT,		/* cmp_olt (sig) cmp_lt */
 	IEEE754_CLT | IEEE754_CUN,	/* cmp_ult (sig) cmp_nge */
 	IEEE754_CLT | IEEE754_CEQ,	/* cmp_ole (sig) cmp_le */
 	IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,	/* cmp_ule (sig) cmp_ngt */
 };
 /*
  * Additional MIPS4 instructions
  */
 #define DEF3OP(name, p, f1, f2, f3)					\
 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,		\
 	union ieee754##p s, union ieee754##p t)				\
 {									\
 	struct _ieee754_csr ieee754_csr_save;				\
 	s = f1(s, t);							\
 	ieee754_csr_save = ieee754_csr;					\
 	s = f2(s, r);							\
 	ieee754_csr_save.cx |= ieee754_csr.cx;				\
 	ieee754_csr_save.sx |= ieee754_csr.sx;				\
 	s = f3(s);							\
 	ieee754_csr.cx |= ieee754_csr_save.cx;				\
 	ieee754_csr.sx |= ieee754_csr_save.sx;				\
 	return s;							\
 }
 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
 {
 	return ieee754dp_div(ieee754dp_one(0), d);
 }
 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
 {
 	return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
 }
 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
 {
 	return ieee754sp_div(ieee754sp_one(0), s);
 }
 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
 {
 	return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
 }
 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 	mips_instruction ir, void *__user *fault_addr)
 {
 	unsigned rcsr = 0;	/* resulting csr */
 	MIPS_FPU_EMU_INC_STATS(cp1xops);
 	switch (MIPSInst_FMA_FFMT(ir)) {
 	case s_fmt:{		/* 0 */
 		union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
 		union ieee754sp fd, fr, fs, ft;
 		u32 __user *va;
 		u32 val;
 		switch (MIPSInst_FUNC(ir)) {
 		case lwxc1_op:
 			va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
 				xcp->regs[MIPSInst_FT(ir)]);
 			MIPS_FPU_EMU_INC_STATS(loads);
 			if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGBUS;
 			}
 			if (__get_user(val, va)) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGSEGV;
 			}
 			SITOREG(val, MIPSInst_FD(ir));
 			break;
 		case swxc1_op:
 			va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
 				xcp->regs[MIPSInst_FT(ir)]);
 			MIPS_FPU_EMU_INC_STATS(stores);
 			SIFROMREG(val, MIPSInst_FS(ir));
 			if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGBUS;
 			}
 			if (put_user(val, va)) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGSEGV;
 			}
 			break;
 		case madd_s_op:
 			handler = fpemu_sp_madd;
 			goto scoptop;
 		case msub_s_op:
 			handler = fpemu_sp_msub;
 			goto scoptop;
 		case nmadd_s_op:
 			handler = fpemu_sp_nmadd;
 			goto scoptop;
 		case nmsub_s_op:
 			handler = fpemu_sp_nmsub;
 			goto scoptop;
 		      scoptop:
 			SPFROMREG(fr, MIPSInst_FR(ir));
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			SPFROMREG(ft, MIPSInst_FT(ir));
 			fd = (*handler) (fr, fs, ft);
 			SPTOREG(fd, MIPSInst_FD(ir));
 		      copcsr:
 			if (ieee754_cxtest(IEEE754_INEXACT)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
 				rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
 			}
 			if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
 				rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
 			}
 			if (ieee754_cxtest(IEEE754_OVERFLOW)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
 				rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
 			}
 			if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
 				rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
 			}
 			ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
 			if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 				/*printk ("SIGFPE: FPU csr = %08x\n",
 				   ctx->fcr31); */
 				return SIGFPE;
 			}
 			break;
 		default:
 			return SIGILL;
 		}
 		break;
 	}
 	case d_fmt:{		/* 1 */
 		union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
 		union ieee754dp fd, fr, fs, ft;
 		u64 __user *va;
 		u64 val;
 		switch (MIPSInst_FUNC(ir)) {
 		case ldxc1_op:
 			va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
 				xcp->regs[MIPSInst_FT(ir)]);
 			MIPS_FPU_EMU_INC_STATS(loads);
 			if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGBUS;
 			}
 			if (__get_user(val, va)) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGSEGV;
 			}
 			DITOREG(val, MIPSInst_FD(ir));
 			break;
 		case sdxc1_op:
 			va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
 				xcp->regs[MIPSInst_FT(ir)]);
 			MIPS_FPU_EMU_INC_STATS(stores);
 			DIFROMREG(val, MIPSInst_FS(ir));
 			if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGBUS;
 			}
 			if (__put_user(val, va)) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				*fault_addr = va;
 				return SIGSEGV;
 			}
 			break;
 		case madd_d_op:
 			handler = fpemu_dp_madd;
 			goto dcoptop;
 		case msub_d_op:
 			handler = fpemu_dp_msub;
 			goto dcoptop;
 		case nmadd_d_op:
 			handler = fpemu_dp_nmadd;
 			goto dcoptop;
 		case nmsub_d_op:
 			handler = fpemu_dp_nmsub;
 			goto dcoptop;
 		      dcoptop:
 			DPFROMREG(fr, MIPSInst_FR(ir));
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			DPFROMREG(ft, MIPSInst_FT(ir));
 			fd = (*handler) (fr, fs, ft);
 			DPTOREG(fd, MIPSInst_FD(ir));
 			goto copcsr;
 		default:
 			return SIGILL;
 		}
 		break;
 	}
 	case 0x3:
 		if (MIPSInst_FUNC(ir) != pfetch_op)
 			return SIGILL;
 		/* ignore prefx operation */
 		break;
 	default:
 		return SIGILL;
 	}
 	return 0;
 }
 /*
  * Emulate a single COP1 arithmetic instruction.
  */
 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 	mips_instruction ir)
 {
 	int rfmt;		/* resulting format */
 	unsigned rcsr = 0;	/* resulting csr */
 	unsigned int oldrm;
 	unsigned int cbit;
 	unsigned cond;
 	union {
 		union ieee754dp d;
 		union ieee754sp s;
 		int w;
 		s64 l;
 	} rv;			/* resulting value */
 	u64 bits;
 	MIPS_FPU_EMU_INC_STATS(cp1ops);
 	switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
 	case s_fmt: {		/* 0 */
 		union {
 			union ieee754sp(*b) (union ieee754sp, union ieee754sp);
 			union ieee754sp(*u) (union ieee754sp);
 		} handler;
 		union ieee754sp fs, ft;
 		switch (MIPSInst_FUNC(ir)) {
 			/* binary ops */
 		case fadd_op:
 			handler.b = ieee754sp_add;
 			goto scopbop;
 		case fsub_op:
 			handler.b = ieee754sp_sub;
 			goto scopbop;
 		case fmul_op:
 			handler.b = ieee754sp_mul;
 			goto scopbop;
 		case fdiv_op:
 			handler.b = ieee754sp_div;
 			goto scopbop;
 			/* unary  ops */
 		case fsqrt_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			handler.u = ieee754sp_sqrt;
 			goto scopuop;
 		/*
 		 * Note that on some MIPS IV implementations such as the
 		 * R5000 and R8000 the FSQRT and FRECIP instructions do not
 		 * achieve full IEEE-754 accuracy - however this emulator does.
 		 */
 		case frsqrt_op:
 			if (!cpu_has_mips_4_5_r2)
 				return SIGILL;
 			handler.u = fpemu_sp_rsqrt;
 			goto scopuop;
 		case frecip_op:
 			if (!cpu_has_mips_4_5_r2)
 				return SIGILL;
 			handler.u = fpemu_sp_recip;
 			goto scopuop;
 		case fmovc_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			cond = fpucondbit[MIPSInst_FT(ir) >> 2];
 			if (((ctx->fcr31 & cond) != 0) !=
 				((MIPSInst_FT(ir) & 1) != 0))
 				return 0;
 			SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 		case fmovz_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			if (xcp->regs[MIPSInst_FT(ir)] != 0)
 				return 0;
 			SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 		case fmovn_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			if (xcp->regs[MIPSInst_FT(ir)] == 0)
 				return 0;
 			SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 		case fabs_op:
 			handler.u = ieee754sp_abs;
 			goto scopuop;
 		case fneg_op:
 			handler.u = ieee754sp_neg;
 			goto scopuop;
 		case fmov_op:
 			/* an easy one */
 			SPFROMREG(rv.s, MIPSInst_FS(ir));
 			goto copcsr;
 			/* binary op on handler */
 scopbop:
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			SPFROMREG(ft, MIPSInst_FT(ir));
 			rv.s = (*handler.b) (fs, ft);
 			goto copcsr;
 scopuop:
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = (*handler.u) (fs);
 			goto copcsr;
 copcsr:
 			if (ieee754_cxtest(IEEE754_INEXACT)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
 				rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
 			}
 			if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
 				rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
 			}
 			if (ieee754_cxtest(IEEE754_OVERFLOW)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
 				rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
 			}
 			if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
 				rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
 			}
 			if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
 				MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
 				rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
 			}
 			break;
 			/* unary conv ops */
 		case fcvts_op:
 			return SIGILL;	/* not defined */
 		case fcvtd_op:
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = ieee754dp_fsp(fs);
 			rfmt = d_fmt;
 			goto copcsr;
 		case fcvtw_op:
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.w = ieee754sp_tint(fs);
 			rfmt = w_fmt;
 			goto copcsr;
 		case fround_op:
 		case ftrunc_op:
 		case fceil_op:
 		case ffloor_op:
 			if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			oldrm = ieee754_csr.rm;
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
 			rv.w = ieee754sp_tint(fs);
 			ieee754_csr.rm = oldrm;
 			rfmt = w_fmt;
 			goto copcsr;
 		case fcvtl_op:
 			if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.l = ieee754sp_tlong(fs);
 			rfmt = l_fmt;
 			goto copcsr;
 		case froundl_op:
 		case ftruncl_op:
 		case fceill_op:
 		case ffloorl_op:
 			if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			oldrm = ieee754_csr.rm;
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
 			rv.l = ieee754sp_tlong(fs);
 			ieee754_csr.rm = oldrm;
 			rfmt = l_fmt;
 			goto copcsr;
 		default:
 			if (MIPSInst_FUNC(ir) >= fcmp_op) {
 				unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
 				union ieee754sp fs, ft;
 				SPFROMREG(fs, MIPSInst_FS(ir));
 				SPFROMREG(ft, MIPSInst_FT(ir));
 				rv.w = ieee754sp_cmp(fs, ft,
 					cmptab[cmpop & 0x7], cmpop & 0x8);
 				rfmt = -1;
 				if ((cmpop & 0x8) && ieee754_cxtest
 					(IEEE754_INVALID_OPERATION))
 					rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
 				else
 					goto copcsr;
 			} else
 				return SIGILL;
 			break;
 		}
 		break;
 	}
 	case d_fmt: {
 		union ieee754dp fs, ft;
 		union {
 			union ieee754dp(*b) (union ieee754dp, union ieee754dp);
 			union ieee754dp(*u) (union ieee754dp);
 		} handler;
 		switch (MIPSInst_FUNC(ir)) {
 			/* binary ops */
 		case fadd_op:
 			handler.b = ieee754dp_add;
 			goto dcopbop;
 		case fsub_op:
 			handler.b = ieee754dp_sub;
 			goto dcopbop;
 		case fmul_op:
 			handler.b = ieee754dp_mul;
 			goto dcopbop;
 		case fdiv_op:
 			handler.b = ieee754dp_div;
 			goto dcopbop;
 			/* unary  ops */
 		case fsqrt_op:
 			if (!cpu_has_mips_2_3_4_5_r)
 				return SIGILL;
 			handler.u = ieee754dp_sqrt;
 			goto dcopuop;
 		/*
 		 * Note that on some MIPS IV implementations such as the
 		 * R5000 and R8000 the FSQRT and FRECIP instructions do not
 		 * achieve full IEEE-754 accuracy - however this emulator does.
 		 */
 		case frsqrt_op:
 			if (!cpu_has_mips_4_5_r2)
 				return SIGILL;
 			handler.u = fpemu_dp_rsqrt;
 			goto dcopuop;
 		case frecip_op:
 			if (!cpu_has_mips_4_5_r2)
 				return SIGILL;
 			handler.u = fpemu_dp_recip;
 			goto dcopuop;
 		case fmovc_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			cond = fpucondbit[MIPSInst_FT(ir) >> 2];
 			if (((ctx->fcr31 & cond) != 0) !=
 				((MIPSInst_FT(ir) & 1) != 0))
 				return 0;
 			DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 		case fmovz_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			if (xcp->regs[MIPSInst_FT(ir)] != 0)
 				return 0;
 			DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 		case fmovn_op:
 			if (!cpu_has_mips_4_5_r)
 				return SIGILL;
 			if (xcp->regs[MIPSInst_FT(ir)] == 0)
 				return 0;
 			DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 		case fabs_op:
 			handler.u = ieee754dp_abs;
 			goto dcopuop;
 		case fneg_op:
 			handler.u = ieee754dp_neg;
 			goto dcopuop;
 		case fmov_op:
 			/* an easy one */
 			DPFROMREG(rv.d, MIPSInst_FS(ir));
 			goto copcsr;
 			/* binary op on handler */
 dcopbop:
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			DPFROMREG(ft, MIPSInst_FT(ir));
 			rv.d = (*handler.b) (fs, ft);
 			goto copcsr;
 dcopuop:
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = (*handler.u) (fs);
 			goto copcsr;
 		/*
 		 * unary conv ops
 		 */
 		case fcvts_op:
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = ieee754sp_fdp(fs);
 			rfmt = s_fmt;
 			goto copcsr;
 		case fcvtd_op:
 			return SIGILL;	/* not defined */
 		case fcvtw_op:
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.w = ieee754dp_tint(fs);	/* wrong */
 			rfmt = w_fmt;
 			goto copcsr;
 		case fround_op:
 		case ftrunc_op:
 		case fceil_op:
 		case ffloor_op:
 			if (!cpu_has_mips_2_3_4_5_r)
 				return SIGILL;
 			oldrm = ieee754_csr.rm;
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
 			rv.w = ieee754dp_tint(fs);
 			ieee754_csr.rm = oldrm;
 			rfmt = w_fmt;
 			goto copcsr;
 		case fcvtl_op:
 			if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			rv.l = ieee754dp_tlong(fs);
 			rfmt = l_fmt;
 			goto copcsr;
 		case froundl_op:
 		case ftruncl_op:
 		case fceill_op:
 		case ffloorl_op:
 			if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 				return SIGILL;
 			oldrm = ieee754_csr.rm;
 			DPFROMREG(fs, MIPSInst_FS(ir));
 			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
 			rv.l = ieee754dp_tlong(fs);
 			ieee754_csr.rm = oldrm;
 			rfmt = l_fmt;
 			goto copcsr;
 		default:
 			if (MIPSInst_FUNC(ir) >= fcmp_op) {
 				unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
 				union ieee754dp fs, ft;
 				DPFROMREG(fs, MIPSInst_FS(ir));
 				DPFROMREG(ft, MIPSInst_FT(ir));
 				rv.w = ieee754dp_cmp(fs, ft,
 					cmptab[cmpop & 0x7], cmpop & 0x8);
 				rfmt = -1;
 				if ((cmpop & 0x8)
 					&&
 					ieee754_cxtest
 					(IEEE754_INVALID_OPERATION))
 					rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
 				else
 					goto copcsr;
 			}
 			else {
 				return SIGILL;
 			}
 			break;
 		}
 		break;
 	case w_fmt:
 		switch (MIPSInst_FUNC(ir)) {
 		case fcvts_op:
 			/* convert word to single precision real */
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.s = ieee754sp_fint(fs.bits);
 			rfmt = s_fmt;
 			goto copcsr;
 		case fcvtd_op:
 			/* convert word to double precision real */
 			SPFROMREG(fs, MIPSInst_FS(ir));
 			rv.d = ieee754dp_fint(fs.bits);
 			rfmt = d_fmt;
 			goto copcsr;
 		default:
 			return SIGILL;
 		}
 		break;
 	}
 	case l_fmt:
 		if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 			return SIGILL;
 		DIFROMREG(bits, MIPSInst_FS(ir));
 		switch (MIPSInst_FUNC(ir)) {
 		case fcvts_op:
 			/* convert long to single precision real */
 			rv.s = ieee754sp_flong(bits);
 			rfmt = s_fmt;
 			goto copcsr;
 		case fcvtd_op:
 			/* convert long to double precision real */
 			rv.d = ieee754dp_flong(bits);
 			rfmt = d_fmt;
 			goto copcsr;
 		default:
 			return SIGILL;
 		}
 		break;
 	default:
 		return SIGILL;
 	}
 	/*
 	 * Update the fpu CSR register for this operation.
 	 * If an exception is required, generate a tidy SIGFPE exception,
 	 * without updating the result register.
 	 * Note: cause exception bits do not accumulate, they are rewritten
 	 * for each op; only the flag/sticky bits accumulate.
 	 */
 	ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
 	if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 		/*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
 		return SIGFPE;
 	}
 	/*
 	 * Now we can safely write the result back to the register file.
 	 */
 	switch (rfmt) {
 	case -1:
 		if (cpu_has_mips_4_5_r)
 			cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
 		else
 			cbit = FPU_CSR_COND;
 		if (rv.w)
 			ctx->fcr31 |= cbit;
 		else
 			ctx->fcr31 &= ~cbit;
 		break;
 	case d_fmt:
 		DPTOREG(rv.d, MIPSInst_FD(ir));
 		break;
 	case s_fmt:
 		SPTOREG(rv.s, MIPSInst_FD(ir));
 		break;
 	case w_fmt:
 		SITOREG(rv.w, MIPSInst_FD(ir));
 		break;
 	case l_fmt:
 		if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 			return SIGILL;
 		DITOREG(rv.l, MIPSInst_FD(ir));
 		break;
 	default:
 		return SIGILL;
 	}
 	return 0;
 }
 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 	int has_fpu, void *__user *fault_addr)
 {
 	unsigned long oldepc, prevepc;
 	struct mm_decoded_insn dec_insn;
 	u16 instr[4];
 	u16 *instr_ptr;
 	int sig = 0;
 	oldepc = xcp->cp0_epc;
 	do {
 		prevepc = xcp->cp0_epc;
 		if (get_isa16_mode(prevepc) && cpu_has_mmips) {
 			/*
 			 * Get next 2 microMIPS instructions and convert them
 			 * into 32-bit instructions.
 			 */
 			if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
 			    (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
 			    (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
 			    (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				return SIGBUS;
 			}
 			instr_ptr = instr;
 			/* Get first instruction. */
 			if (mm_insn_16bit(*instr_ptr)) {
 				/* Duplicate the half-word. */
 				dec_insn.insn = (*instr_ptr << 16) |
 					(*instr_ptr);
 				/* 16-bit instruction. */
 				dec_insn.pc_inc = 2;
 				instr_ptr += 1;
 			} else {
 				dec_insn.insn = (*instr_ptr << 16) |
 					*(instr_ptr+1);
 				/* 32-bit instruction. */
 				dec_insn.pc_inc = 4;
 				instr_ptr += 2;
 			}
 			/* Get second instruction. */
 			if (mm_insn_16bit(*instr_ptr)) {
 				/* Duplicate the half-word. */
 				dec_insn.next_insn = (*instr_ptr << 16) |
 					(*instr_ptr);
 				/* 16-bit instruction. */
 				dec_insn.next_pc_inc = 2;
 			} else {
 				dec_insn.next_insn = (*instr_ptr << 16) |
 					*(instr_ptr+1);
 				/* 32-bit instruction. */
 				dec_insn.next_pc_inc = 4;
 			}
 			dec_insn.micro_mips_mode = 1;
 		} else {
 			if ((get_user(dec_insn.insn,
 			    (mips_instruction __user *) xcp->cp0_epc)) ||
 			    (get_user(dec_insn.next_insn,
 			    (mips_instruction __user *)(xcp->cp0_epc+4)))) {
 				MIPS_FPU_EMU_INC_STATS(errors);
 				return SIGBUS;
 			}
 			dec_insn.pc_inc = 4;
 			dec_insn.next_pc_inc = 4;
 			dec_insn.micro_mips_mode = 0;
 		}
 		if ((dec_insn.insn == 0) ||
 		   ((dec_insn.pc_inc == 2) &&
 		   ((dec_insn.insn & 0xffff) == MM_NOP16)))
 			xcp->cp0_epc += dec_insn.pc_inc;	/* Skip NOPs */
 		else {
 			/*
 			 * The 'ieee754_csr' is an alias of
 			 * ctx->fcr31.	No need to copy ctx->fcr31 to
 			 * ieee754_csr.	 But ieee754_csr.rm is ieee
 			 * library modes. (not mips rounding mode)
 			 */
 			sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
 		}
 		if (has_fpu)
 			break;
 		if (sig)
 			break;
 		cond_resched();
 	} while (xcp->cp0_epc > prevepc);
 	/* SIGILL indicates a non-fpu instruction */
 	if (sig == SIGILL && xcp->cp0_epc != oldepc)
 		/* but if EPC has advanced, then ignore it */
 		sig = 0;
 	return sig;
 }

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