Eric Lee / smarc-ti-linux-kernel

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Commit 8598066cddd186809c4edf5aae5f018c00079e8c

Authored by Felipe Balbi
Committed by Tony Lindgren
1 parent eaacabc0d9
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

arm: omap: irq: move irq.c to drivers/irqchip/ 

Just move the code over as it has no dependencies
on arch/arm/ anymore.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Showing 6 changed files with 402 additions and 395 deletions Inline Diff

arch/arm/mach-omap2/Kconfig
Diff comments   View file @ 8598066
1 menu "TI OMAP/AM/DM/DRA Family" 1 menu "TI OMAP/AM/DM/DRA Family"
2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
3 3
4 config ARCH_OMAP 4 config ARCH_OMAP
5 bool 5 bool
6 6
7 config ARCH_OMAP2 7 config ARCH_OMAP2
8 bool "TI OMAP2" 8 bool "TI OMAP2"
9 depends on ARCH_MULTI_V6 9 depends on ARCH_MULTI_V6
10 select ARCH_OMAP2PLUS 10 select ARCH_OMAP2PLUS
11 select CPU_V6 11 select CPU_V6
12 select SOC_HAS_OMAP2_SDRC 12 select SOC_HAS_OMAP2_SDRC
13 13
14 config ARCH_OMAP3 14 config ARCH_OMAP3
15 bool "TI OMAP3" 15 bool "TI OMAP3"
16 depends on ARCH_MULTI_V7 16 depends on ARCH_MULTI_V7
17 select ARCH_OMAP2PLUS 17 select ARCH_OMAP2PLUS
18 select ARM_CPU_SUSPEND if PM 18 select ARM_CPU_SUSPEND if PM
19 select OMAP_INTERCONNECT 19 select OMAP_INTERCONNECT
20 select PM_OPP if PM 20 select PM_OPP if PM
21 select PM_RUNTIME if CPU_IDLE 21 select PM_RUNTIME if CPU_IDLE
22 select SOC_HAS_OMAP2_SDRC 22 select SOC_HAS_OMAP2_SDRC
23 23
24 config ARCH_OMAP4 24 config ARCH_OMAP4
25 bool "TI OMAP4" 25 bool "TI OMAP4"
26 depends on ARCH_MULTI_V7 26 depends on ARCH_MULTI_V7
27 select ARCH_OMAP2PLUS 27 select ARCH_OMAP2PLUS
28 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 28 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
29 select ARM_CPU_SUSPEND if PM 29 select ARM_CPU_SUSPEND if PM
30 select ARM_ERRATA_720789 30 select ARM_ERRATA_720789
31 select ARM_GIC 31 select ARM_GIC
32 select HAVE_ARM_SCU if SMP 32 select HAVE_ARM_SCU if SMP
33 select HAVE_ARM_TWD if SMP 33 select HAVE_ARM_TWD if SMP
34 select OMAP_INTERCONNECT 34 select OMAP_INTERCONNECT
35 select PL310_ERRATA_588369 if CACHE_L2X0 35 select PL310_ERRATA_588369 if CACHE_L2X0
36 select PL310_ERRATA_727915 if CACHE_L2X0 36 select PL310_ERRATA_727915 if CACHE_L2X0
37 select PM_OPP if PM 37 select PM_OPP if PM
38 select PM_RUNTIME if CPU_IDLE 38 select PM_RUNTIME if CPU_IDLE
39 select ARM_ERRATA_754322 39 select ARM_ERRATA_754322
40 select ARM_ERRATA_775420 40 select ARM_ERRATA_775420
41 41
42 config SOC_OMAP5 42 config SOC_OMAP5
43 bool "TI OMAP5" 43 bool "TI OMAP5"
44 depends on ARCH_MULTI_V7 44 depends on ARCH_MULTI_V7
45 select ARCH_OMAP2PLUS 45 select ARCH_OMAP2PLUS
46 select ARM_CPU_SUSPEND if PM 46 select ARM_CPU_SUSPEND if PM
47 select ARM_GIC 47 select ARM_GIC
48 select HAVE_ARM_SCU if SMP 48 select HAVE_ARM_SCU if SMP
49 select HAVE_ARM_TWD if SMP 49 select HAVE_ARM_TWD if SMP
50 select HAVE_ARM_ARCH_TIMER 50 select HAVE_ARM_ARCH_TIMER
51 select ARM_ERRATA_798181 if SMP 51 select ARM_ERRATA_798181 if SMP
52 52
53 config SOC_AM33XX 53 config SOC_AM33XX
54 bool "TI AM33XX" 54 bool "TI AM33XX"
55 depends on ARCH_MULTI_V7 55 depends on ARCH_MULTI_V7
56 select ARCH_OMAP2PLUS 56 select ARCH_OMAP2PLUS
57 select ARM_CPU_SUSPEND if PM 57 select ARM_CPU_SUSPEND if PM
58 58
59 config SOC_AM43XX 59 config SOC_AM43XX
60 bool "TI AM43x" 60 bool "TI AM43x"
61 depends on ARCH_MULTI_V7 61 depends on ARCH_MULTI_V7
62 select ARCH_OMAP2PLUS 62 select ARCH_OMAP2PLUS
63 select ARM_GIC 63 select ARM_GIC
64 select MACH_OMAP_GENERIC 64 select MACH_OMAP_GENERIC
65 select MIGHT_HAVE_CACHE_L2X0 65 select MIGHT_HAVE_CACHE_L2X0
66 66
67 config SOC_DRA7XX 67 config SOC_DRA7XX
68 bool "TI DRA7XX" 68 bool "TI DRA7XX"
69 depends on ARCH_MULTI_V7 69 depends on ARCH_MULTI_V7
70 select ARCH_OMAP2PLUS 70 select ARCH_OMAP2PLUS
71 select ARM_CPU_SUSPEND if PM 71 select ARM_CPU_SUSPEND if PM
72 select ARM_GIC 72 select ARM_GIC
73 select HAVE_ARM_ARCH_TIMER 73 select HAVE_ARM_ARCH_TIMER
74 select IRQ_CROSSBAR 74 select IRQ_CROSSBAR
75 75
76 config ARCH_OMAP2PLUS 76 config ARCH_OMAP2PLUS
77 bool 77 bool
78 select ARCH_HAS_BANDGAP 78 select ARCH_HAS_BANDGAP
79 select ARCH_HAS_HOLES_MEMORYMODEL 79 select ARCH_HAS_HOLES_MEMORYMODEL
80 select ARCH_OMAP 80 select ARCH_OMAP
81 select ARCH_REQUIRE_GPIOLIB 81 select ARCH_REQUIRE_GPIOLIB
82 select CLKSRC_MMIO 82 select CLKSRC_MMIO
83 select GENERIC_IRQ_CHIP 83 select GENERIC_IRQ_CHIP
84 select MACH_OMAP_GENERIC 84 select MACH_OMAP_GENERIC
85 select OMAP_DM_TIMER 85 select OMAP_DM_TIMER
86 select PINCTRL 86 select PINCTRL
87 select SOC_BUS 87 select SOC_BUS
88 select TI_PRIV_EDMA 88 select TI_PRIV_EDMA
89 select OMAP_IRQCHIP
89 help 90 help
90 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 91 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
91 92
92 93
93 if ARCH_OMAP2PLUS 94 if ARCH_OMAP2PLUS
94 95
95 menu "TI OMAP2/3/4 Specific Features" 96 menu "TI OMAP2/3/4 Specific Features"
96 97
97 config ARCH_OMAP2PLUS_TYPICAL 98 config ARCH_OMAP2PLUS_TYPICAL
98 bool "Typical OMAP configuration" 99 bool "Typical OMAP configuration"
99 default y 100 default y
100 select AEABI 101 select AEABI
101 select HIGHMEM 102 select HIGHMEM
102 select I2C 103 select I2C
103 select I2C_OMAP 104 select I2C_OMAP
104 select MENELAUS if ARCH_OMAP2 105 select MENELAUS if ARCH_OMAP2
105 select NEON if CPU_V7 106 select NEON if CPU_V7
106 select PM_RUNTIME 107 select PM_RUNTIME
107 select REGULATOR 108 select REGULATOR
108 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 109 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
109 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 110 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
110 select VFP 111 select VFP
111 help 112 help
112 Compile a kernel suitable for booting most boards 113 Compile a kernel suitable for booting most boards
113 114
114 config SOC_HAS_OMAP2_SDRC 115 config SOC_HAS_OMAP2_SDRC
115 bool "OMAP2 SDRAM Controller support" 116 bool "OMAP2 SDRAM Controller support"
116 117
117 config SOC_HAS_REALTIME_COUNTER 118 config SOC_HAS_REALTIME_COUNTER
118 bool "Real time free running counter" 119 bool "Real time free running counter"
119 depends on SOC_OMAP5 || SOC_DRA7XX 120 depends on SOC_OMAP5 || SOC_DRA7XX
120 default y 121 default y
121 122
122 comment "OMAP Core Type" 123 comment "OMAP Core Type"
123 depends on ARCH_OMAP2 124 depends on ARCH_OMAP2
124 125
125 config SOC_OMAP2420 126 config SOC_OMAP2420
126 bool "OMAP2420 support" 127 bool "OMAP2420 support"
127 depends on ARCH_OMAP2 128 depends on ARCH_OMAP2
128 default y 129 default y
129 select OMAP_DM_TIMER 130 select OMAP_DM_TIMER
130 select SOC_HAS_OMAP2_SDRC 131 select SOC_HAS_OMAP2_SDRC
131 132
132 config SOC_OMAP2430 133 config SOC_OMAP2430
133 bool "OMAP2430 support" 134 bool "OMAP2430 support"
134 depends on ARCH_OMAP2 135 depends on ARCH_OMAP2
135 default y 136 default y
136 select SOC_HAS_OMAP2_SDRC 137 select SOC_HAS_OMAP2_SDRC
137 138
138 config SOC_OMAP3430 139 config SOC_OMAP3430
139 bool "OMAP3430 support" 140 bool "OMAP3430 support"
140 depends on ARCH_OMAP3 141 depends on ARCH_OMAP3
141 default y 142 default y
142 select SOC_HAS_OMAP2_SDRC 143 select SOC_HAS_OMAP2_SDRC
143 144
144 config SOC_TI81XX 145 config SOC_TI81XX
145 bool "TI81XX support" 146 bool "TI81XX support"
146 depends on ARCH_OMAP3 147 depends on ARCH_OMAP3
147 default y 148 default y
148 149
149 config OMAP_PACKAGE_CBC 150 config OMAP_PACKAGE_CBC
150 bool 151 bool
151 152
152 config OMAP_PACKAGE_CBB 153 config OMAP_PACKAGE_CBB
153 bool 154 bool
154 155
155 config OMAP_PACKAGE_CUS 156 config OMAP_PACKAGE_CUS
156 bool 157 bool
157 158
158 config OMAP_PACKAGE_CBP 159 config OMAP_PACKAGE_CBP
159 bool 160 bool
160 161
161 comment "OMAP Legacy Platform Data Board Type" 162 comment "OMAP Legacy Platform Data Board Type"
162 depends on ARCH_OMAP2PLUS 163 depends on ARCH_OMAP2PLUS
163 164
164 config MACH_OMAP_GENERIC 165 config MACH_OMAP_GENERIC
165 bool 166 bool
166 167
167 config MACH_OMAP2_TUSB6010 168 config MACH_OMAP2_TUSB6010
168 bool 169 bool
169 depends on ARCH_OMAP2 && SOC_OMAP2420 170 depends on ARCH_OMAP2 && SOC_OMAP2420
170 default y if MACH_NOKIA_N8X0 171 default y if MACH_NOKIA_N8X0
171 172
172 config MACH_OMAP3_BEAGLE 173 config MACH_OMAP3_BEAGLE
173 bool "OMAP3 BEAGLE board" 174 bool "OMAP3 BEAGLE board"
174 depends on ARCH_OMAP3 175 depends on ARCH_OMAP3
175 default y 176 default y
176 select OMAP_PACKAGE_CBB 177 select OMAP_PACKAGE_CBB
177 178
178 config MACH_DEVKIT8000 179 config MACH_DEVKIT8000
179 bool "DEVKIT8000 board" 180 bool "DEVKIT8000 board"
180 depends on ARCH_OMAP3 181 depends on ARCH_OMAP3
181 default y 182 default y
182 select OMAP_PACKAGE_CUS 183 select OMAP_PACKAGE_CUS
183 184
184 config MACH_OMAP_LDP 185 config MACH_OMAP_LDP
185 bool "OMAP3 LDP board" 186 bool "OMAP3 LDP board"
186 depends on ARCH_OMAP3 187 depends on ARCH_OMAP3
187 default y 188 default y
188 select OMAP_PACKAGE_CBB 189 select OMAP_PACKAGE_CBB
189 190
190 config MACH_OMAP3530_LV_SOM 191 config MACH_OMAP3530_LV_SOM
191 bool "OMAP3 Logic 3530 LV SOM board" 192 bool "OMAP3 Logic 3530 LV SOM board"
192 depends on ARCH_OMAP3 193 depends on ARCH_OMAP3
193 default y 194 default y
194 select OMAP_PACKAGE_CBB 195 select OMAP_PACKAGE_CBB
195 help 196 help
196 Support for the LogicPD OMAP3530 SOM Development kit 197 Support for the LogicPD OMAP3530 SOM Development kit
197 for full description please see the products webpage at 198 for full description please see the products webpage at
198 http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit 199 http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
199 200
200 config MACH_OMAP3_TORPEDO 201 config MACH_OMAP3_TORPEDO
201 bool "OMAP3 Logic 35x Torpedo board" 202 bool "OMAP3 Logic 35x Torpedo board"
202 depends on ARCH_OMAP3 203 depends on ARCH_OMAP3
203 default y 204 default y
204 select OMAP_PACKAGE_CBB 205 select OMAP_PACKAGE_CBB
205 help 206 help
206 Support for the LogicPD OMAP35x Torpedo Development kit 207 Support for the LogicPD OMAP35x Torpedo Development kit
207 for full description please see the products webpage at 208 for full description please see the products webpage at
208 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit 209 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
209 210
210 config MACH_OVERO 211 config MACH_OVERO
211 bool "Gumstix Overo board" 212 bool "Gumstix Overo board"
212 depends on ARCH_OMAP3 213 depends on ARCH_OMAP3
213 default y 214 default y
214 select OMAP_PACKAGE_CBB 215 select OMAP_PACKAGE_CBB
215 216
216 config MACH_OMAP3517EVM 217 config MACH_OMAP3517EVM
217 bool "OMAP3517/ AM3517 EVM board" 218 bool "OMAP3517/ AM3517 EVM board"
218 depends on ARCH_OMAP3 219 depends on ARCH_OMAP3
219 default y 220 default y
220 select OMAP_PACKAGE_CBB 221 select OMAP_PACKAGE_CBB
221 222
222 config MACH_CRANEBOARD 223 config MACH_CRANEBOARD
223 bool "AM3517/05 CRANE board" 224 bool "AM3517/05 CRANE board"
224 depends on ARCH_OMAP3 225 depends on ARCH_OMAP3
225 select OMAP_PACKAGE_CBB 226 select OMAP_PACKAGE_CBB
226 227
227 config MACH_OMAP3_PANDORA 228 config MACH_OMAP3_PANDORA
228 bool "OMAP3 Pandora" 229 bool "OMAP3 Pandora"
229 depends on ARCH_OMAP3 230 depends on ARCH_OMAP3
230 default y 231 default y
231 select OMAP_PACKAGE_CBB 232 select OMAP_PACKAGE_CBB
232 select REGULATOR_FIXED_VOLTAGE if REGULATOR 233 select REGULATOR_FIXED_VOLTAGE if REGULATOR
233 234
234 config MACH_TOUCHBOOK 235 config MACH_TOUCHBOOK
235 bool "OMAP3 Touch Book" 236 bool "OMAP3 Touch Book"
236 depends on ARCH_OMAP3 237 depends on ARCH_OMAP3
237 default y 238 default y
238 select OMAP_PACKAGE_CBB 239 select OMAP_PACKAGE_CBB
239 240
240 config MACH_OMAP_3430SDP 241 config MACH_OMAP_3430SDP
241 bool "OMAP 3430 SDP board" 242 bool "OMAP 3430 SDP board"
242 depends on ARCH_OMAP3 243 depends on ARCH_OMAP3
243 default y 244 default y
244 select OMAP_PACKAGE_CBB 245 select OMAP_PACKAGE_CBB
245 246
246 config MACH_NOKIA_N810 247 config MACH_NOKIA_N810
247 bool 248 bool
248 249
249 config MACH_NOKIA_N810_WIMAX 250 config MACH_NOKIA_N810_WIMAX
250 bool 251 bool
251 252
252 config MACH_NOKIA_N8X0 253 config MACH_NOKIA_N8X0
253 bool "Nokia N800/N810" 254 bool "Nokia N800/N810"
254 depends on SOC_OMAP2420 255 depends on SOC_OMAP2420
255 default y 256 default y
256 select MACH_NOKIA_N810 257 select MACH_NOKIA_N810
257 select MACH_NOKIA_N810_WIMAX 258 select MACH_NOKIA_N810_WIMAX
258 259
259 config MACH_NOKIA_RX51 260 config MACH_NOKIA_RX51
260 bool "Nokia N900 (RX-51) phone" 261 bool "Nokia N900 (RX-51) phone"
261 depends on ARCH_OMAP3 262 depends on ARCH_OMAP3
262 default y 263 default y
263 select OMAP_PACKAGE_CBB 264 select OMAP_PACKAGE_CBB
264 265
265 config MACH_CM_T35 266 config MACH_CM_T35
266 bool "CompuLab CM-T35/CM-T3730 modules" 267 bool "CompuLab CM-T35/CM-T3730 modules"
267 depends on ARCH_OMAP3 268 depends on ARCH_OMAP3
268 default y 269 default y
269 select MACH_CM_T3730 270 select MACH_CM_T3730
270 select OMAP_PACKAGE_CUS 271 select OMAP_PACKAGE_CUS
271 272
272 config MACH_CM_T3517 273 config MACH_CM_T3517
273 bool "CompuLab CM-T3517 module" 274 bool "CompuLab CM-T3517 module"
274 depends on ARCH_OMAP3 275 depends on ARCH_OMAP3
275 default y 276 default y
276 select OMAP_PACKAGE_CBB 277 select OMAP_PACKAGE_CBB
277 278
278 config MACH_CM_T3730 279 config MACH_CM_T3730
279 bool 280 bool
280 281
281 config MACH_SBC3530 282 config MACH_SBC3530
282 bool "OMAP3 SBC STALKER board" 283 bool "OMAP3 SBC STALKER board"
283 depends on ARCH_OMAP3 284 depends on ARCH_OMAP3
284 default y 285 default y
285 select OMAP_PACKAGE_CUS 286 select OMAP_PACKAGE_CUS
286 287
287 config MACH_TI8168EVM 288 config MACH_TI8168EVM
288 bool "TI8168 Evaluation Module" 289 bool "TI8168 Evaluation Module"
289 depends on SOC_TI81XX 290 depends on SOC_TI81XX
290 default y 291 default y
291 292
292 config MACH_TI8148EVM 293 config MACH_TI8148EVM
293 bool "TI8148 Evaluation Module" 294 bool "TI8148 Evaluation Module"
294 depends on SOC_TI81XX 295 depends on SOC_TI81XX
295 default y 296 default y
296 297
297 config OMAP3_EMU 298 config OMAP3_EMU
298 bool "OMAP3 debugging peripherals" 299 bool "OMAP3 debugging peripherals"
299 depends on ARCH_OMAP3 300 depends on ARCH_OMAP3
300 select ARM_AMBA 301 select ARM_AMBA
301 select OC_ETM 302 select OC_ETM
302 help 303 help
303 Say Y here to enable debugging hardware of omap3 304 Say Y here to enable debugging hardware of omap3
304 305
305 config OMAP3_SDRC_AC_TIMING 306 config OMAP3_SDRC_AC_TIMING
306 bool "Enable SDRC AC timing register changes" 307 bool "Enable SDRC AC timing register changes"
307 depends on ARCH_OMAP3 308 depends on ARCH_OMAP3
308 default n 309 default n
309 help 310 help
310 If you know that none of your system initiators will attempt to 311 If you know that none of your system initiators will attempt to
311 access SDRAM during CORE DVFS, select Y here. This should boost 312 access SDRAM during CORE DVFS, select Y here. This should boost
312 SDRAM performance at lower CORE OPPs. There are relatively few 313 SDRAM performance at lower CORE OPPs. There are relatively few
313 users who will wish to say yes at this point - almost everyone will 314 users who will wish to say yes at this point - almost everyone will
314 wish to say no. Selecting yes without understanding what is 315 wish to say no. Selecting yes without understanding what is
315 going on could result in system crashes; 316 going on could result in system crashes;
316 317
317 config OMAP4_ERRATA_I688 318 config OMAP4_ERRATA_I688
318 bool "OMAP4 errata: Async Bridge Corruption" 319 bool "OMAP4 errata: Async Bridge Corruption"
319 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM 320 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
320 select ARCH_HAS_BARRIERS 321 select ARCH_HAS_BARRIERS
321 help 322 help
322 If a data is stalled inside asynchronous bridge because of back 323 If a data is stalled inside asynchronous bridge because of back
323 pressure, it may be accepted multiple times, creating pointer 324 pressure, it may be accepted multiple times, creating pointer
324 misalignment that will corrupt next transfers on that data path 325 misalignment that will corrupt next transfers on that data path
325 until next reset of the system (No recovery procedure once the 326 until next reset of the system (No recovery procedure once the
326 issue is hit, the path remains consistently broken). Async bridge 327 issue is hit, the path remains consistently broken). Async bridge
327 can be found on path between MPU to EMIF and MPU to L3 interconnect. 328 can be found on path between MPU to EMIF and MPU to L3 interconnect.
328 This situation can happen only when the idle is initiated by a 329 This situation can happen only when the idle is initiated by a
329 Master Request Disconnection (which is trigged by software when 330 Master Request Disconnection (which is trigged by software when
330 executing WFI on CPU). 331 executing WFI on CPU).
331 The work-around for this errata needs all the initiators connected 332 The work-around for this errata needs all the initiators connected
332 through async bridge must ensure that data path is properly drained 333 through async bridge must ensure that data path is properly drained
333 before issuing WFI. This condition will be met if one Strongly ordered 334 before issuing WFI. This condition will be met if one Strongly ordered
334 access is performed to the target right before executing the WFI. 335 access is performed to the target right before executing the WFI.
335 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. 336 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
336 IO barrier ensure that there is no synchronisation loss on initiators 337 IO barrier ensure that there is no synchronisation loss on initiators
337 operating on both interconnect port simultaneously. 338 operating on both interconnect port simultaneously.
338 endmenu 339 endmenu
339 340
340 endif 341 endif
341 342
342 endmenu 343 endmenu
343 344
arch/arm/mach-omap2/Makefile
Diff comments   View file @ 8598066
1 # 1 #
2 # Makefile for the linux kernel. 2 # Makefile for the linux kernel.
3 # 3 #
4 4
5 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ 5 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
6 -I$(srctree)/arch/arm/plat-omap/include 6 -I$(srctree)/arch/arm/plat-omap/include
7 7
8 # Common support 8 # Common support
9 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \ 9 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
11 omap_device.o sram.o drm.o 11 omap_device.o sram.o drm.o
12 12
13 omap-2-3-common = irq.o
14 hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ 13 hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
15 omap_hwmod_common_data.o 14 omap_hwmod_common_data.o
16 clock-common = clock.o clock_common_data.o \ 15 clock-common = clock.o clock_common_data.o \
17 clkt_dpll.o clkt_clksel.o 16 clkt_dpll.o clkt_clksel.o
18 secure-common = omap-smc.o omap-secure.o 17 secure-common = omap-smc.o omap-secure.o
19 18
20 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) 19 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
21 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 20 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22 obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) 21 obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
23 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 22 obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common)
24 obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) 23 obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
25 obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) 24 obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26 obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) 25 obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
27 26
28 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 27 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
29 obj-y += mcbsp.o 28 obj-y += mcbsp.o
30 endif 29 endif
31 30
32 obj-$(CONFIG_TWL4030_CORE) += omap_twl.o 31 obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
33 obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o 32 obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
34 33
35 # SMP support ONLY available for OMAP4 34 # SMP support ONLY available for OMAP4
36 35
37 smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o 36 smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
38 smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 37 smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
39 omap-4-5-common = omap4-common.o omap-wakeupgen.o 38 omap-4-5-common = omap4-common.o omap-wakeupgen.o
40 obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o 39 obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
41 obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o 40 obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
42 obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) 41 obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
43 obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o 42 obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
44 43
45 plus_sec := $(call as-instr,.arch_extension sec,+sec) 44 plus_sec := $(call as-instr,.arch_extension sec,+sec)
46 AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 45 AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
47 AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec) 46 AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec)
48 AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec) 47 AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
49 48
50 # Functions loaded to SRAM 49 # Functions loaded to SRAM
51 obj-$(CONFIG_SOC_OMAP2420) += sram242x.o 50 obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
52 obj-$(CONFIG_SOC_OMAP2430) += sram243x.o 51 obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
53 obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o 52 obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
54 53
55 AFLAGS_sram242x.o :=-Wa,-march=armv6 54 AFLAGS_sram242x.o :=-Wa,-march=armv6
56 AFLAGS_sram243x.o :=-Wa,-march=armv6 55 AFLAGS_sram243x.o :=-Wa,-march=armv6
57 AFLAGS_sram34xx.o :=-Wa,-march=armv7-a 56 AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
58 57
59 # Restart code (OMAP4/5 currently in omap4-common.c) 58 # Restart code (OMAP4/5 currently in omap4-common.c)
60 obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o 59 obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
61 obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o 60 obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
62 obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o 61 obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
63 obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o 62 obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o
64 obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 63 obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
65 obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o 64 obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
66 obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 65 obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
67 obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o 66 obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
68 67
69 # Pin multiplexing 68 # Pin multiplexing
70 obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 69 obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
71 70
72 # SMS/SDRC 71 # SMS/SDRC
73 obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 72 obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
74 # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o 73 # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
75 74
76 # OPP table initialization 75 # OPP table initialization
77 ifeq ($(CONFIG_PM_OPP),y) 76 ifeq ($(CONFIG_PM_OPP),y)
78 obj-y += opp.o 77 obj-y += opp.o
79 obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o 78 obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o
80 obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o 79 obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o
81 endif 80 endif
82 81
83 # Power Management 82 # Power Management
84 obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o 83 obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
85 84
86 ifeq ($(CONFIG_PM),y) 85 ifeq ($(CONFIG_PM),y)
87 obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o 86 obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
88 obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o 87 obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
89 obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 88 obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
90 obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 89 obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
91 obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o 90 obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
92 obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o 91 obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
93 obj-$(CONFIG_PM_DEBUG) += pm-debug.o 92 obj-$(CONFIG_PM_DEBUG) += pm-debug.o
94 93
95 obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o 94 obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
96 obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o 95 obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
97 96
98 AFLAGS_sleep24xx.o :=-Wa,-march=armv6 97 AFLAGS_sleep24xx.o :=-Wa,-march=armv6
99 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) 98 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
100 99
101 endif 100 endif
102 101
103 ifeq ($(CONFIG_CPU_IDLE),y) 102 ifeq ($(CONFIG_CPU_IDLE),y)
104 obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o 103 obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
105 obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o 104 obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
106 endif 105 endif
107 106
108 # PRCM 107 # PRCM
109 obj-y += prm_common.o cm_common.o 108 obj-y += prm_common.o cm_common.o
110 obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o 109 obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
111 obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o 110 obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
112 obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 111 obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
113 omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 112 omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
114 prcm_mpu44xx.o prminst44xx.o \ 113 prcm_mpu44xx.o prminst44xx.o \
115 vc44xx_data.o vp44xx_data.o 114 vc44xx_data.o vp44xx_data.o
116 obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 115 obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
117 obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) 116 obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
118 obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) 117 obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
119 am33xx-43xx-prcm-common += prm33xx.o cm33xx.o 118 am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
120 obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common) 119 obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
121 obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \ 120 obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
122 $(am33xx-43xx-prcm-common) 121 $(am33xx-43xx-prcm-common)
123 122
124 # OMAP voltage domains 123 # OMAP voltage domains
125 voltagedomain-common := voltage.o vc.o vp.o 124 voltagedomain-common := voltage.o vc.o vp.o
126 obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) 125 obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
127 obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o 126 obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
128 obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) 127 obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
129 obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o 128 obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
130 obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) 129 obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
131 obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 130 obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
132 obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) 131 obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
133 obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common) 132 obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common)
134 obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) 133 obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
135 obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o 134 obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
136 obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common) 135 obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
137 136
138 # OMAP powerdomain framework 137 # OMAP powerdomain framework
139 powerdomain-common += powerdomain.o powerdomain-common.o 138 powerdomain-common += powerdomain.o powerdomain-common.o
140 obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) 139 obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
141 obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o 140 obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
142 obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o 141 obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
143 obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) 142 obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
144 obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o 143 obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
145 obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o 144 obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
146 obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) 145 obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
147 obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 146 obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
148 obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) 147 obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
149 obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 148 obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
150 obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) 149 obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
151 obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o 150 obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o
152 obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 151 obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
153 obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o 152 obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
154 obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) 153 obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
155 obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o 154 obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
156 155
157 # PRCM clockdomain control 156 # PRCM clockdomain control
158 clockdomain-common += clockdomain.o 157 clockdomain-common += clockdomain.o
159 obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) 158 obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
160 obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o 159 obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
161 obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o 160 obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
162 obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o 161 obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
163 obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) 162 obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
164 obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o 163 obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
165 obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o 164 obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
166 obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) 165 obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
167 obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 166 obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
168 obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) 167 obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
169 obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 168 obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
170 obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) 169 obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
171 obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o 170 obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
172 obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 171 obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
173 obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o 172 obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
174 obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) 173 obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
175 obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o 174 obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
176 175
177 # Clock framework 176 # Clock framework
178 obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 177 obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
179 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o 178 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
180 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 179 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
181 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o 180 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
182 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o 181 obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
183 obj-$(CONFIG_SOC_OMAP2430) += clock2430.o 182 obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
184 obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 183 obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
185 obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 184 obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
186 obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 185 obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
187 obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o 186 obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
188 obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 187 obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
189 obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 188 obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
190 obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 189 obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
191 obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o 190 obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
192 obj-$(CONFIG_SOC_OMAP5) += $(clock-common) 191 obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
193 obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o 192 obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
194 obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) 193 obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
195 obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o 194 obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
196 obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o 195 obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o
197 196
198 # OMAP2 clock rate set data (old "OPP" data) 197 # OMAP2 clock rate set data (old "OPP" data)
199 obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o 198 obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
200 obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o 199 obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
201 200
202 # hwmod data 201 # hwmod data
203 obj-y += omap_hwmod_common_ipblock_data.o 202 obj-y += omap_hwmod_common_ipblock_data.o
204 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o 203 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
205 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o 204 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
206 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o 205 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
207 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_interconnect_data.o 206 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_interconnect_data.o
208 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o 207 obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
209 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o 208 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o
210 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o 209 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o
211 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o 210 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
212 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_interconnect_data.o 211 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_interconnect_data.o
213 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o 212 obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
214 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o 213 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
215 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o 214 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
216 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 215 obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
217 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 216 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
218 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o 217 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o
219 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o 218 obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o
220 obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o 219 obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o
221 obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o 220 obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o
222 obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o 221 obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o
223 obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 222 obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
224 obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o 223 obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
225 obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o 224 obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
226 225
227 # EMU peripherals 226 # EMU peripherals
228 obj-$(CONFIG_OMAP3_EMU) += emu.o 227 obj-$(CONFIG_OMAP3_EMU) += emu.o
229 obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o 228 obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
230 229
231 iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 230 iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
232 obj-y += $(iommu-m) $(iommu-y) 231 obj-y += $(iommu-m) $(iommu-y)
233 232
234 # OMAP2420 MSDI controller integration support ("MMC") 233 # OMAP2420 MSDI controller integration support ("MMC")
235 obj-$(CONFIG_SOC_OMAP2420) += msdi.o 234 obj-$(CONFIG_SOC_OMAP2420) += msdi.o
236 235
237 # Specific board support 236 # Specific board support
238 obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o 237 obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
239 obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 238 obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
240 obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o 239 obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
241 obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 240 obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
242 obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o 241 obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
243 obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o 242 obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
244 obj-$(CONFIG_MACH_OVERO) += board-overo.o 243 obj-$(CONFIG_MACH_OVERO) += board-overo.o
245 obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o 244 obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
246 obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o 245 obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o
247 obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o 246 obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
248 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o 247 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
249 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o 248 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
250 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o 249 obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
251 obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o 250 obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
252 obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o 251 obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
253 obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o 252 obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
254 253
255 obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 254 obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
256 255
257 obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o 256 obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
258 257
259 obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o 258 obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
260 obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o 259 obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
261 obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o 260 obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o
262 261
263 # Platform specific device init code 262 # Platform specific device init code
264 263
265 omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o 264 omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o
266 omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o 265 omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o
267 obj-y += $(omap-flash-y) $(omap-flash-m) 266 obj-y += $(omap-flash-y) $(omap-flash-m)
268 267
269 omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o 268 omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
270 obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) 269 obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
271 270
272 obj-y += usb-musb.o 271 obj-y += usb-musb.o
273 obj-y += omap_phy_internal.o 272 obj-y += omap_phy_internal.o
274 273
275 obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o 274 obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
276 obj-y += usb-host.o 275 obj-y += usb-host.o
277 276
278 onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o 277 onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
279 obj-y += $(onenand-m) $(onenand-y) 278 obj-y += $(onenand-m) $(onenand-y)
280 279
281 nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o 280 nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
282 obj-y += $(nand-m) $(nand-y) 281 obj-y += $(nand-m) $(nand-y)
283 282
284 smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o 283 smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o
285 obj-y += $(smc91x-m) $(smc91x-y) 284 obj-y += $(smc91x-m) $(smc91x-y)
286 285
287 smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o 286 smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
288 obj-y += $(smsc911x-m) $(smsc911x-y) 287 obj-y += $(smsc911x-m) $(smsc911x-y)
289 ifneq ($(CONFIG_HWSPINLOCK_OMAP),) 288 ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
290 obj-y += hwspinlock.o 289 obj-y += hwspinlock.o
291 endif 290 endif
292 291
293 emac-$(CONFIG_TI_DAVINCI_EMAC) := am35xx-emac.o 292 emac-$(CONFIG_TI_DAVINCI_EMAC) := am35xx-emac.o
294 obj-y += $(emac-m) $(emac-y) 293 obj-y += $(emac-m) $(emac-y)
295 294
296 obj-y += common-board-devices.o twl-common.o dss-common.o 295 obj-y += common-board-devices.o twl-common.o dss-common.o
297 296
arch/arm/mach-omap2/irq.c
View file @ 8598066
1 /* File was deleted
2 * linux/arch/arm/mach-omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18
19 #include <asm/exception.h>
20 #include <asm/mach/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25
26 #include "soc.h"
27 #include "common.h"
28 #include "../../drivers/irqchip/irqchip.h"
29
30 /* selected INTC register offsets */
31
32 #define INTC_REVISION 0x0000
33 #define INTC_SYSCONFIG 0x0010
34 #define INTC_SYSSTATUS 0x0014
35 #define INTC_SIR 0x0040
36 #define INTC_CONTROL 0x0048
37 #define INTC_PROTECTION 0x004C
38 #define INTC_IDLE 0x0050
39 #define INTC_THRESHOLD 0x0068
40 #define INTC_MIR0 0x0084
41 #define INTC_MIR_CLEAR0 0x0088
42 #define INTC_MIR_SET0 0x008c
43 #define INTC_PENDING_IRQ0 0x0098
44 #define INTC_PENDING_IRQ1 0x00b8
45 #define INTC_PENDING_IRQ2 0x00d8
46 #define INTC_PENDING_IRQ3 0x00f8
47 #define INTC_ILR0 0x0100
48
49 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
50 #define INTCPS_NR_ILR_REGS 128
51 #define INTCPS_NR_MIR_REGS 3
52
53 /*
54 * OMAP2 has a number of different interrupt controllers, each interrupt
55 * controller is identified as its own "bank". Register definitions are
56 * fairly consistent for each bank, but not all registers are implemented
57 * for each bank.. when in doubt, consult the TRM.
58 */
59
60 /* Structure to save interrupt controller context */
61 struct omap_intc_regs {
62 u32 sysconfig;
63 u32 protection;
64 u32 idle;
65 u32 threshold;
66 u32 ilr[INTCPS_NR_ILR_REGS];
67 u32 mir[INTCPS_NR_MIR_REGS];
68 };
69 static struct omap_intc_regs intc_context;
70
71 static struct irq_domain *domain;
72 static void __iomem *omap_irq_base;
73 static int omap_nr_pending = 3;
74 static int omap_nr_irqs = 96;
75
76 /* INTC bank register get/set */
77 static void intc_writel(u32 reg, u32 val)
78 {
79 writel_relaxed(val, omap_irq_base + reg);
80 }
81
82 static u32 intc_readl(u32 reg)
83 {
84 return readl_relaxed(omap_irq_base + reg);
85 }
86
87 void omap_intc_save_context(void)
88 {
89 int i;
90
91 intc_context.sysconfig =
92 intc_readl(INTC_SYSCONFIG);
93 intc_context.protection =
94 intc_readl(INTC_PROTECTION);
95 intc_context.idle =
96 intc_readl(INTC_IDLE);
97 intc_context.threshold =
98 intc_readl(INTC_THRESHOLD);
99
100 for (i = 0; i < omap_nr_irqs; i++)
101 intc_context.ilr[i] =
102 intc_readl((INTC_ILR0 + 0x4 * i));
103 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
104 intc_context.mir[i] =
105 intc_readl(INTC_MIR0 + (0x20 * i));
106 }
107
108 void omap_intc_restore_context(void)
109 {
110 int i;
111
112 intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
113 intc_writel(INTC_PROTECTION, intc_context.protection);
114 intc_writel(INTC_IDLE, intc_context.idle);
115 intc_writel(INTC_THRESHOLD, intc_context.threshold);
116
117 for (i = 0; i < omap_nr_irqs; i++)
118 intc_writel(INTC_ILR0 + 0x4 * i,
119 intc_context.ilr[i]);
120
121 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
122 intc_writel(INTC_MIR0 + 0x20 * i,
123 intc_context.mir[i]);
124 /* MIRs are saved and restore with other PRCM registers */
125 }
126
127 void omap3_intc_prepare_idle(void)
128 {
129 /*
130 * Disable autoidle as it can stall interrupt controller,
131 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
132 */
133 intc_writel(INTC_SYSCONFIG, 0);
134 }
135
136 void omap3_intc_resume_idle(void)
137 {
138 /* Re-enable autoidle */
139 intc_writel(INTC_SYSCONFIG, 1);
140 }
141
142 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
143 static void omap_ack_irq(struct irq_data *d)
144 {
145 intc_writel(INTC_CONTROL, 0x1);
146 }
147
148 static void omap_mask_ack_irq(struct irq_data *d)
149 {
150 irq_gc_mask_disable_reg(d);
151 omap_ack_irq(d);
152 }
153
154 static void __init omap_irq_soft_reset(void)
155 {
156 unsigned long tmp;
157
158 tmp = intc_readl(INTC_REVISION) & 0xff;
159
160 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
161 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
162
163 tmp = intc_readl(INTC_SYSCONFIG);
164 tmp |= 1 << 1; /* soft reset */
165 intc_writel(INTC_SYSCONFIG, tmp);
166
167 while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
168 /* Wait for reset to complete */;
169
170 /* Enable autoidle */
171 intc_writel(INTC_SYSCONFIG, 1 << 0);
172 }
173
174 int omap_irq_pending(void)
175 {
176 int irq;
177
178 for (irq = 0; irq < omap_nr_irqs; irq += 32)
179 if (intc_readl(INTC_PENDING_IRQ0 +
180 ((irq >> 5) << 5)))
181 return 1;
182 return 0;
183 }
184
185 void omap3_intc_suspend(void)
186 {
187 /* A pending interrupt would prevent OMAP from entering suspend */
188 omap_ack_irq(NULL);
189 }
190
191 static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
192 {
193 int ret;
194 int i;
195
196 ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
197 handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
198 IRQ_LEVEL, 0);
199 if (ret) {
200 pr_warn("Failed to allocate irq chips\n");
201 return ret;
202 }
203
204 for (i = 0; i < omap_nr_pending; i++) {
205 struct irq_chip_generic *gc;
206 struct irq_chip_type *ct;
207
208 gc = irq_get_domain_generic_chip(d, 32 * i);
209 gc->reg_base = base;
210 ct = gc->chip_types;
211
212 ct->type = IRQ_TYPE_LEVEL_MASK;
213 ct->handler = handle_level_irq;
214
215 ct->chip.irq_ack = omap_mask_ack_irq;
216 ct->chip.irq_mask = irq_gc_mask_disable_reg;
217 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
218
219 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
220
221 ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
222 ct->regs.disable = INTC_MIR_SET0 + 32 * i;
223 }
224
225 return 0;
226 }
227
228 static void __init omap_alloc_gc_legacy(void __iomem *base,
229 unsigned int irq_start, unsigned int num)
230 {
231 struct irq_chip_generic *gc;
232 struct irq_chip_type *ct;
233
234 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
235 handle_level_irq);
236 ct = gc->chip_types;
237 ct->chip.irq_ack = omap_mask_ack_irq;
238 ct->chip.irq_mask = irq_gc_mask_disable_reg;
239 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
240 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
241
242 ct->regs.enable = INTC_MIR_CLEAR0;
243 ct->regs.disable = INTC_MIR_SET0;
244 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
245 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
246 }
247
248 static int __init omap_init_irq_of(struct device_node *node)
249 {
250 int ret;
251
252 omap_irq_base = of_iomap(node, 0);
253 if (WARN_ON(!omap_irq_base))
254 return -ENOMEM;
255
256 domain = irq_domain_add_linear(node, omap_nr_irqs,
257 &irq_generic_chip_ops, NULL);
258
259 omap_irq_soft_reset();
260
261 ret = omap_alloc_gc_of(domain, omap_irq_base);
262 if (ret < 0)
263 irq_domain_remove(domain);
264
265 return ret;
266 }
267
268 static int __init omap_init_irq_legacy(u32 base)
269 {
270 int j, irq_base;
271
272 omap_irq_base = ioremap(base, SZ_4K);
273 if (WARN_ON(!omap_irq_base))
274 return -ENOMEM;
275
276 irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
277 if (irq_base < 0) {
278 pr_warn("Couldn't allocate IRQ numbers\n");
279 irq_base = 0;
280 }
281
282 domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
283 &irq_domain_simple_ops, NULL);
284
285 omap_irq_soft_reset();
286
287 for (j = 0; j < omap_nr_irqs; j += 32)
288 omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
289
290 return 0;
291 }
292
293 static int __init omap_init_irq(u32 base, struct device_node *node)
294 {
295 if (node)
296 return omap_init_irq_of(node);
297 else
298 return omap_init_irq_legacy(base);
299 }
300
301 static asmlinkage void __exception_irq_entry
302 omap_intc_handle_irq(struct pt_regs *regs)
303 {
304 u32 irqnr = 0;
305 int handled_irq = 0;
306 int i;
307
308 do {
309 for (i = 0; i < omap_nr_pending; i++) {
310 irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
311 if (irqnr)
312 goto out;
313 }
314
315 out:
316 if (!irqnr)
317 break;
318
319 irqnr = intc_readl(INTC_SIR);
320 irqnr &= ACTIVEIRQ_MASK;
321
322 if (irqnr) {
323 irqnr = irq_find_mapping(domain, irqnr);
324 handle_IRQ(irqnr, regs);
325 handled_irq = 1;
326 }
327 } while (irqnr);
328
329 /* If an irq is masked or deasserted while active, we will
330 * keep ending up here with no irq handled. So remove it from
331 * the INTC with an ack.*/
332 if (!handled_irq)
333 omap_ack_irq(NULL);
334 }
335
336 void __init omap2_init_irq(void)
337 {
338 omap_nr_irqs = 96;
339 omap_nr_pending = 3;
340 omap_init_irq(OMAP24XX_IC_BASE, NULL);
341 set_handle_irq(omap_intc_handle_irq);
342 }
343
344 void __init omap3_init_irq(void)
345 {
346 omap_nr_irqs = 96;
347 omap_nr_pending = 3;
348 omap_init_irq(OMAP34XX_IC_BASE, NULL);
349 set_handle_irq(omap_intc_handle_irq);
350 }
351
352 void __init ti81xx_init_irq(void)
353 {
354 omap_nr_irqs = 96;
355 omap_nr_pending = 4;
356 omap_init_irq(OMAP34XX_IC_BASE, NULL);
357 set_handle_irq(omap_intc_handle_irq);
358 }
359
360 static int __init intc_of_init(struct device_node *node,
361 struct device_node *parent)
362 {
363 struct resource res;
364 int ret;
365
366 omap_nr_pending = 3;
367 omap_nr_irqs = 96;
368
369 if (WARN_ON(!node))
370 return -ENODEV;
371
372 if (of_address_to_resource(node, 0, &res)) {
373 WARN(1, "unable to get intc registers\n");
374 return -EINVAL;
375 }
376
377 if (of_device_is_compatible(node, "ti,am33xx-intc")) {
378 omap_nr_irqs = 128;
379 omap_nr_pending = 4;
380 }
381
382 ret = omap_init_irq(-1, of_node_get(node));
383 if (ret < 0)
384 return ret;
385
386 set_handle_irq(omap_intc_handle_irq);
387
388 return 0;
389 }
390
391 IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
392 IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
393 IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
394 1 /*
drivers/irqchip/Kconfig
Diff comments   View file @ 8598066
1 config IRQCHIP 1 config IRQCHIP
2 def_bool y 2 def_bool y
3 depends on OF_IRQ 3 depends on OF_IRQ
4 4
5 config ARM_GIC 5 config ARM_GIC
6 bool 6 bool
7 select IRQ_DOMAIN 7 select IRQ_DOMAIN
8 select MULTI_IRQ_HANDLER 8 select MULTI_IRQ_HANDLER
9 9
10 config GIC_NON_BANKED 10 config GIC_NON_BANKED
11 bool 11 bool
12 12
13 config ARM_GIC_V3 13 config ARM_GIC_V3
14 bool 14 bool
15 select IRQ_DOMAIN 15 select IRQ_DOMAIN
16 select MULTI_IRQ_HANDLER 16 select MULTI_IRQ_HANDLER
17 17
18 config ARM_NVIC 18 config ARM_NVIC
19 bool 19 bool
20 select IRQ_DOMAIN 20 select IRQ_DOMAIN
21 select GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_CHIP
22 22
23 config ARM_VIC 23 config ARM_VIC
24 bool 24 bool
25 select IRQ_DOMAIN 25 select IRQ_DOMAIN
26 select MULTI_IRQ_HANDLER 26 select MULTI_IRQ_HANDLER
27 27
28 config ARM_VIC_NR 28 config ARM_VIC_NR
29 int 29 int
30 default 4 if ARCH_S5PV210 30 default 4 if ARCH_S5PV210
31 default 2 31 default 2
32 depends on ARM_VIC 32 depends on ARM_VIC
33 help 33 help
34 The maximum number of VICs available in the system, for 34 The maximum number of VICs available in the system, for
35 power management. 35 power management.
36 36
37 config ATMEL_AIC_IRQ 37 config ATMEL_AIC_IRQ
38 bool 38 bool
39 select GENERIC_IRQ_CHIP 39 select GENERIC_IRQ_CHIP
40 select IRQ_DOMAIN 40 select IRQ_DOMAIN
41 select MULTI_IRQ_HANDLER 41 select MULTI_IRQ_HANDLER
42 select SPARSE_IRQ 42 select SPARSE_IRQ
43 43
44 config ATMEL_AIC5_IRQ 44 config ATMEL_AIC5_IRQ
45 bool 45 bool
46 select GENERIC_IRQ_CHIP 46 select GENERIC_IRQ_CHIP
47 select IRQ_DOMAIN 47 select IRQ_DOMAIN
48 select MULTI_IRQ_HANDLER 48 select MULTI_IRQ_HANDLER
49 select SPARSE_IRQ 49 select SPARSE_IRQ
50 50
51 config BRCMSTB_L2_IRQ 51 config BRCMSTB_L2_IRQ
52 bool 52 bool
53 depends on ARM 53 depends on ARM
54 select GENERIC_IRQ_CHIP 54 select GENERIC_IRQ_CHIP
55 select IRQ_DOMAIN 55 select IRQ_DOMAIN
56 56
57 config DW_APB_ICTL 57 config DW_APB_ICTL
58 bool 58 bool
59 select IRQ_DOMAIN 59 select IRQ_DOMAIN
60 60
61 config IMGPDC_IRQ 61 config IMGPDC_IRQ
62 bool 62 bool
63 select GENERIC_IRQ_CHIP 63 select GENERIC_IRQ_CHIP
64 select IRQ_DOMAIN 64 select IRQ_DOMAIN
65 65
66 config CLPS711X_IRQCHIP 66 config CLPS711X_IRQCHIP
67 bool 67 bool
68 depends on ARCH_CLPS711X 68 depends on ARCH_CLPS711X
69 select IRQ_DOMAIN 69 select IRQ_DOMAIN
70 select MULTI_IRQ_HANDLER 70 select MULTI_IRQ_HANDLER
71 select SPARSE_IRQ 71 select SPARSE_IRQ
72 default y 72 default y
73 73
74 config OR1K_PIC 74 config OR1K_PIC
75 bool 75 bool
76 select IRQ_DOMAIN 76 select IRQ_DOMAIN
77 77
78 config OMAP_IRQCHIP
79 bool
80 select GENERIC_IRQ_CHIP
81 select IRQ_DOMAIN
82
78 config ORION_IRQCHIP 83 config ORION_IRQCHIP
79 bool 84 bool
80 select IRQ_DOMAIN 85 select IRQ_DOMAIN
81 select MULTI_IRQ_HANDLER 86 select MULTI_IRQ_HANDLER
82 87
83 config RENESAS_INTC_IRQPIN 88 config RENESAS_INTC_IRQPIN
84 bool 89 bool
85 select IRQ_DOMAIN 90 select IRQ_DOMAIN
86 91
87 config RENESAS_IRQC 92 config RENESAS_IRQC
88 bool 93 bool
89 select IRQ_DOMAIN 94 select IRQ_DOMAIN
90 95
91 config TB10X_IRQC 96 config TB10X_IRQC
92 bool 97 bool
93 select IRQ_DOMAIN 98 select IRQ_DOMAIN
94 select GENERIC_IRQ_CHIP 99 select GENERIC_IRQ_CHIP
95 100
96 config VERSATILE_FPGA_IRQ 101 config VERSATILE_FPGA_IRQ
97 bool 102 bool
98 select IRQ_DOMAIN 103 select IRQ_DOMAIN
99 104
100 config VERSATILE_FPGA_IRQ_NR 105 config VERSATILE_FPGA_IRQ_NR
101 int 106 int
102 default 4 107 default 4
103 depends on VERSATILE_FPGA_IRQ 108 depends on VERSATILE_FPGA_IRQ
104 109
105 config XTENSA_MX 110 config XTENSA_MX
106 bool 111 bool
107 select IRQ_DOMAIN 112 select IRQ_DOMAIN
108 113
109 config IRQ_CROSSBAR 114 config IRQ_CROSSBAR
110 bool 115 bool
111 help 116 help
112 Support for a CROSSBAR ip that preceeds the main interrupt controller. 117 Support for a CROSSBAR ip that preceeds the main interrupt controller.
113 The primary irqchip invokes the crossbar's callback which inturn allocates 118 The primary irqchip invokes the crossbar's callback which inturn allocates
114 a free irq and configures the IP. Thus the peripheral interrupts are 119 a free irq and configures the IP. Thus the peripheral interrupts are
115 routed to one of the free irqchip interrupt lines. 120 routed to one of the free irqchip interrupt lines.
116 121
drivers/irqchip/Makefile
Diff comments   View file @ 8598066
1 obj-$(CONFIG_IRQCHIP) += irqchip.o 1 obj-$(CONFIG_IRQCHIP) += irqchip.o
2 2
3 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 3 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
4 obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o 4 obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
5 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o 5 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
6 obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o 6 obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
7 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o 7 obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
8 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o 8 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
9 obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o 9 obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
10 obj-$(CONFIG_METAG) += irq-metag-ext.o 10 obj-$(CONFIG_METAG) += irq-metag-ext.o
11 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o 11 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
12 obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o 12 obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
13 obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o 13 obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
14 obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o 14 obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
15 obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o 15 obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
16 obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
16 obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o 17 obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
17 obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o 18 obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
18 obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 19 obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
19 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o 20 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
20 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o 21 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
21 obj-$(CONFIG_ARM_NVIC) += irq-nvic.o 22 obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
22 obj-$(CONFIG_ARM_VIC) += irq-vic.o 23 obj-$(CONFIG_ARM_VIC) += irq-vic.o
23 obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o 24 obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
24 obj-$(CONFIG_ATMEL_AIC5_IRQ) += irq-atmel-aic-common.o irq-atmel-aic5.o 25 obj-$(CONFIG_ATMEL_AIC5_IRQ) += irq-atmel-aic-common.o irq-atmel-aic5.o
25 obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o 26 obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
26 obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o 27 obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
27 obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o 28 obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
28 obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o 29 obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
29 obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o 30 obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
30 obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o 31 obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
31 obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o 32 obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
32 obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o 33 obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
33 obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o 34 obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
34 obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o 35 obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
35 obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o 36 obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
36 obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o 37 obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
37 38
drivers/irqchip/irq-omap-intc.c
Diff comments   View file @ 8598066
File was created 1 /*
2 * linux/arch/arm/mach-omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18
19 #include <asm/exception.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24
25 #include "irqchip.h"
26
27 /* Define these here for now until we drop all board-files */
28 #define OMAP24XX_IC_BASE 0x480fe000
29 #define OMAP34XX_IC_BASE 0x48200000
30
31 /* selected INTC register offsets */
32
33 #define INTC_REVISION 0x0000
34 #define INTC_SYSCONFIG 0x0010
35 #define INTC_SYSSTATUS 0x0014
36 #define INTC_SIR 0x0040
37 #define INTC_CONTROL 0x0048
38 #define INTC_PROTECTION 0x004C
39 #define INTC_IDLE 0x0050
40 #define INTC_THRESHOLD 0x0068
41 #define INTC_MIR0 0x0084
42 #define INTC_MIR_CLEAR0 0x0088
43 #define INTC_MIR_SET0 0x008c
44 #define INTC_PENDING_IRQ0 0x0098
45 #define INTC_PENDING_IRQ1 0x00b8
46 #define INTC_PENDING_IRQ2 0x00d8
47 #define INTC_PENDING_IRQ3 0x00f8
48 #define INTC_ILR0 0x0100
49
50 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
51 #define INTCPS_NR_ILR_REGS 128
52 #define INTCPS_NR_MIR_REGS 3
53
54 /*
55 * OMAP2 has a number of different interrupt controllers, each interrupt
56 * controller is identified as its own "bank". Register definitions are
57 * fairly consistent for each bank, but not all registers are implemented
58 * for each bank.. when in doubt, consult the TRM.
59 */
60
61 /* Structure to save interrupt controller context */
62 struct omap_intc_regs {
63 u32 sysconfig;
64 u32 protection;
65 u32 idle;
66 u32 threshold;
67 u32 ilr[INTCPS_NR_ILR_REGS];
68 u32 mir[INTCPS_NR_MIR_REGS];
69 };
70 static struct omap_intc_regs intc_context;
71
72 static struct irq_domain *domain;
73 static void __iomem *omap_irq_base;
74 static int omap_nr_pending = 3;
75 static int omap_nr_irqs = 96;
76
77 /* INTC bank register get/set */
78 static void intc_writel(u32 reg, u32 val)
79 {
80 writel_relaxed(val, omap_irq_base + reg);
81 }
82
83 static u32 intc_readl(u32 reg)
84 {
85 return readl_relaxed(omap_irq_base + reg);
86 }
87
88 void omap_intc_save_context(void)
89 {
90 int i;
91
92 intc_context.sysconfig =
93 intc_readl(INTC_SYSCONFIG);
94 intc_context.protection =
95 intc_readl(INTC_PROTECTION);
96 intc_context.idle =
97 intc_readl(INTC_IDLE);
98 intc_context.threshold =
99 intc_readl(INTC_THRESHOLD);
100
101 for (i = 0; i < omap_nr_irqs; i++)
102 intc_context.ilr[i] =
103 intc_readl((INTC_ILR0 + 0x4 * i));
104 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
105 intc_context.mir[i] =
106 intc_readl(INTC_MIR0 + (0x20 * i));
107 }
108
109 void omap_intc_restore_context(void)
110 {
111 int i;
112
113 intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
114 intc_writel(INTC_PROTECTION, intc_context.protection);
115 intc_writel(INTC_IDLE, intc_context.idle);
116 intc_writel(INTC_THRESHOLD, intc_context.threshold);
117
118 for (i = 0; i < omap_nr_irqs; i++)
119 intc_writel(INTC_ILR0 + 0x4 * i,
120 intc_context.ilr[i]);
121
122 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
123 intc_writel(INTC_MIR0 + 0x20 * i,
124 intc_context.mir[i]);
125 /* MIRs are saved and restore with other PRCM registers */
126 }
127
128 void omap3_intc_prepare_idle(void)
129 {
130 /*
131 * Disable autoidle as it can stall interrupt controller,
132 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
133 */
134 intc_writel(INTC_SYSCONFIG, 0);
135 }
136
137 void omap3_intc_resume_idle(void)
138 {
139 /* Re-enable autoidle */
140 intc_writel(INTC_SYSCONFIG, 1);
141 }
142
143 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
144 static void omap_ack_irq(struct irq_data *d)
145 {
146 intc_writel(INTC_CONTROL, 0x1);
147 }
148
149 static void omap_mask_ack_irq(struct irq_data *d)
150 {
151 irq_gc_mask_disable_reg(d);
152 omap_ack_irq(d);
153 }
154
155 static void __init omap_irq_soft_reset(void)
156 {
157 unsigned long tmp;
158
159 tmp = intc_readl(INTC_REVISION) & 0xff;
160
161 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
162 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
163
164 tmp = intc_readl(INTC_SYSCONFIG);
165 tmp |= 1 << 1; /* soft reset */
166 intc_writel(INTC_SYSCONFIG, tmp);
167
168 while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
169 /* Wait for reset to complete */;
170
171 /* Enable autoidle */
172 intc_writel(INTC_SYSCONFIG, 1 << 0);
173 }
174
175 int omap_irq_pending(void)
176 {
177 int irq;
178
179 for (irq = 0; irq < omap_nr_irqs; irq += 32)
180 if (intc_readl(INTC_PENDING_IRQ0 +
181 ((irq >> 5) << 5)))
182 return 1;
183 return 0;
184 }
185
186 void omap3_intc_suspend(void)
187 {
188 /* A pending interrupt would prevent OMAP from entering suspend */
189 omap_ack_irq(NULL);
190 }
191
192 static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
193 {
194 int ret;
195 int i;
196
197 ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
198 handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
199 IRQ_LEVEL, 0);
200 if (ret) {
201 pr_warn("Failed to allocate irq chips\n");
202 return ret;
203 }
204
205 for (i = 0; i < omap_nr_pending; i++) {
206 struct irq_chip_generic *gc;
207 struct irq_chip_type *ct;
208
209 gc = irq_get_domain_generic_chip(d, 32 * i);
210 gc->reg_base = base;
211 ct = gc->chip_types;
212
213 ct->type = IRQ_TYPE_LEVEL_MASK;
214 ct->handler = handle_level_irq;
215
216 ct->chip.irq_ack = omap_mask_ack_irq;
217 ct->chip.irq_mask = irq_gc_mask_disable_reg;
218 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
219
220 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
221
222 ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
223 ct->regs.disable = INTC_MIR_SET0 + 32 * i;
224 }
225
226 return 0;
227 }
228
229 static void __init omap_alloc_gc_legacy(void __iomem *base,
230 unsigned int irq_start, unsigned int num)
231 {
232 struct irq_chip_generic *gc;
233 struct irq_chip_type *ct;
234
235 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
236 handle_level_irq);
237 ct = gc->chip_types;
238 ct->chip.irq_ack = omap_mask_ack_irq;
239 ct->chip.irq_mask = irq_gc_mask_disable_reg;
240 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
241 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
242
243 ct->regs.enable = INTC_MIR_CLEAR0;
244 ct->regs.disable = INTC_MIR_SET0;
245 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
246 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
247 }
248
249 static int __init omap_init_irq_of(struct device_node *node)
250 {
251 int ret;
252
253 omap_irq_base = of_iomap(node, 0);
254 if (WARN_ON(!omap_irq_base))
255 return -ENOMEM;
256
257 domain = irq_domain_add_linear(node, omap_nr_irqs,
258 &irq_generic_chip_ops, NULL);
259
260 omap_irq_soft_reset();
261
262 ret = omap_alloc_gc_of(domain, omap_irq_base);
263 if (ret < 0)
264 irq_domain_remove(domain);
265
266 return ret;
267 }
268
269 static int __init omap_init_irq_legacy(u32 base)
270 {
271 int j, irq_base;
272
273 omap_irq_base = ioremap(base, SZ_4K);
274 if (WARN_ON(!omap_irq_base))
275 return -ENOMEM;
276
277 irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
278 if (irq_base < 0) {
279 pr_warn("Couldn't allocate IRQ numbers\n");
280 irq_base = 0;
281 }
282
283 domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
284 &irq_domain_simple_ops, NULL);
285
286 omap_irq_soft_reset();
287
288 for (j = 0; j < omap_nr_irqs; j += 32)
289 omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
290
291 return 0;
292 }
293
294 static int __init omap_init_irq(u32 base, struct device_node *node)
295 {
296 if (node)
297 return omap_init_irq_of(node);
298 else
299 return omap_init_irq_legacy(base);
300 }
301
302 static asmlinkage void __exception_irq_entry
303 omap_intc_handle_irq(struct pt_regs *regs)
304 {
305 u32 irqnr = 0;
306 int handled_irq = 0;
307 int i;
308
309 do {
310 for (i = 0; i < omap_nr_pending; i++) {
311 irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
312 if (irqnr)
313 goto out;
314 }
315
316 out:
317 if (!irqnr)
318 break;
319
320 irqnr = intc_readl(INTC_SIR);
321 irqnr &= ACTIVEIRQ_MASK;
322
323 if (irqnr) {
324 irqnr = irq_find_mapping(domain, irqnr);
325 handle_IRQ(irqnr, regs);
326 handled_irq = 1;
327 }
328 } while (irqnr);
329
330 /* If an irq is masked or deasserted while active, we will
331 * keep ending up here with no irq handled. So remove it from
332 * the INTC with an ack.*/
333 if (!handled_irq)
334 omap_ack_irq(NULL);
335 }
336
337 void __init omap2_init_irq(void)
338 {
339 omap_nr_irqs = 96;
340 omap_nr_pending = 3;
341 omap_init_irq(OMAP24XX_IC_BASE, NULL);
342 set_handle_irq(omap_intc_handle_irq);
343 }
344
345 void __init omap3_init_irq(void)
346 {
347 omap_nr_irqs = 96;
348 omap_nr_pending = 3;
349 omap_init_irq(OMAP34XX_IC_BASE, NULL);
350 set_handle_irq(omap_intc_handle_irq);
351 }
352
353 void __init ti81xx_init_irq(void)
354 {
355 omap_nr_irqs = 96;
356 omap_nr_pending = 4;
357 omap_init_irq(OMAP34XX_IC_BASE, NULL);
358 set_handle_irq(omap_intc_handle_irq);
359 }
360
361 static int __init intc_of_init(struct device_node *node,
362 struct device_node *parent)
363 {
364 struct resource res;
365 int ret;
366
367 omap_nr_pending = 3;
368 omap_nr_irqs = 96;
369
370 if (WARN_ON(!node))
371 return -ENODEV;
372
373 if (of_address_to_resource(node, 0, &res)) {
374 WARN(1, "unable to get intc registers\n");
375 return -EINVAL;
376 }
377
378 if (of_device_is_compatible(node, "ti,am33xx-intc")) {
379 omap_nr_irqs = 128;
380 omap_nr_pending = 4;
381 }
382
383 ret = omap_init_irq(-1, of_node_get(node));
384 if (ret < 0)
385 return ret;
386
387 set_handle_irq(omap_intc_handle_irq);
388
389 return 0;
390 }
391
392 IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
393 IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
394 IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
395