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Commit 9299566c1d4fa25c69bf0f4b23abe02cb03d9039

Authored by Joel Fernandes
Committed by Tero Kristo
1 parent 691c76e7d8
Exists in smarct4x-processor-sdk-linux-03.00.00.04 and in 2 other branches dlt-processor-sdk-linux-03.00.00.04, smarct3x-processor-sdk-linux-03.00.00.04

ARM: DRA7: hwmod: Add data for DES IP 

Adding hwmod data for DES.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>

Showing 1 changed file with 37 additions and 0 deletions Inline Diff

arch/arm/mach-omap2/omap_hwmod_7xx_data.c
Diff comments   View file @ 9299566
1 /* 1 /*
2 * Hardware modules present on the DRA7xx chips 2 * Hardware modules present on the DRA7xx chips
3 * 3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * 5 *
6 * Paul Walmsley 6 * Paul Walmsley
7 * Benoit Cousson 7 * Benoit Cousson
8 * 8 *
9 * This file is automatically generated from the OMAP hardware databases. 9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated 10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the 11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept 12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents. 13 * up-to-date with the file contents.
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as 16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18 */ 18 */
19 19
20 #include <linux/io.h> 20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h> 21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h> 22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h> 23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h> 24 #include <linux/i2c-omap.h>
25 25
26 #include <linux/omap-dma.h> 26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h> 27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h> 28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h> 29 #include <plat/dmtimer.h>
30 30
31 #include "omap_hwmod.h" 31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h" 32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h" 33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h" 34 #include "cm2_7xx.h"
35 #include "prm7xx.h" 35 #include "prm7xx.h"
36 #include "i2c.h" 36 #include "i2c.h"
37 #include "wd_timer.h" 37 #include "wd_timer.h"
38 #include "soc.h" 38 #include "soc.h"
39 39
40 /* Base offset for all DRA7XX interrupts external to MPUSS */ 40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32 41 #define DRA7XX_IRQ_GIC_START 32
42 42
43 /* Base offset for all DRA7XX dma requests */ 43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1 44 #define DRA7XX_DMA_REQ_START 1
45 45
46 46
47 /* 47 /*
48 * IP blocks 48 * IP blocks
49 */ 49 */
50 50
51 /* 51 /*
52 * 'dmm' class 52 * 'dmm' class
53 * instance(s): dmm 53 * instance(s): dmm
54 */ 54 */
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = { 55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm", 56 .name = "dmm",
57 }; 57 };
58 58
59 /* dmm */ 59 /* dmm */
60 static struct omap_hwmod dra7xx_dmm_hwmod = { 60 static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm", 61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class, 62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm", 63 .clkdm_name = "emif_clkdm",
64 .prcm = { 64 .prcm = {
65 .omap4 = { 65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET, 66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET, 67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 }, 68 },
69 }, 69 },
70 }; 70 };
71 71
72 /* 72 /*
73 * 'l3' class 73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2 74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */ 75 */
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = { 76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3", 77 .name = "l3",
78 }; 78 };
79 79
80 /* l3_instr */ 80 /* l3_instr */
81 static struct omap_hwmod dra7xx_l3_instr_hwmod = { 81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr", 82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class, 83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm", 84 .clkdm_name = "l3instr_clkdm",
85 .prcm = { 85 .prcm = {
86 .omap4 = { 86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, 87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, 88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL, 89 .modulemode = MODULEMODE_HWCTRL,
90 }, 90 },
91 }, 91 },
92 }; 92 };
93 93
94 /* l3_main_1 */ 94 /* l3_main_1 */
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = { 95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1", 96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class, 97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm", 98 .clkdm_name = "l3main1_clkdm",
99 .prcm = { 99 .prcm = {
100 .omap4 = { 100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, 101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, 102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 }, 103 },
104 }, 104 },
105 }; 105 };
106 106
107 /* l3_main_2 */ 107 /* l3_main_2 */
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = { 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2", 109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class, 110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm", 111 .clkdm_name = "l3instr_clkdm",
112 .prcm = { 112 .prcm = {
113 .omap4 = { 113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET, 114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET, 115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL, 116 .modulemode = MODULEMODE_HWCTRL,
117 }, 117 },
118 }, 118 },
119 }; 119 };
120 120
121 /* 121 /*
122 * 'l4' class 122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup 123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */ 124 */
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = { 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4", 126 .name = "l4",
127 }; 127 };
128 128
129 /* l4_cfg */ 129 /* l4_cfg */
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = { 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg", 131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class, 132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm", 133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = { 134 .prcm = {
135 .omap4 = { 135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, 136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, 137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 }, 138 },
139 }, 139 },
140 }; 140 };
141 141
142 /* l4_per1 */ 142 /* l4_per1 */
143 static struct omap_hwmod dra7xx_l4_per1_hwmod = { 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1", 144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class, 145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm", 146 .clkdm_name = "l4per_clkdm",
147 .prcm = { 147 .prcm = {
148 .omap4 = { 148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET, 149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 }, 151 },
152 }, 152 },
153 }; 153 };
154 154
155 /* l4_per2 */ 155 /* l4_per2 */
156 static struct omap_hwmod dra7xx_l4_per2_hwmod = { 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2", 157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class, 158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm", 159 .clkdm_name = "l4per2_clkdm",
160 .prcm = { 160 .prcm = {
161 .omap4 = { 161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, 162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 }, 164 },
165 }, 165 },
166 }; 166 };
167 167
168 /* l4_per3 */ 168 /* l4_per3 */
169 static struct omap_hwmod dra7xx_l4_per3_hwmod = { 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3", 170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class, 171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm", 172 .clkdm_name = "l4per3_clkdm",
173 .prcm = { 173 .prcm = {
174 .omap4 = { 174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET, 175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 }, 177 },
178 }, 178 },
179 }; 179 };
180 180
181 /* l4_wkup */ 181 /* l4_wkup */
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = { 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup", 183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class, 184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm", 185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = { 186 .prcm = {
187 .omap4 = { 187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, 188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, 189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 }, 190 },
191 }, 191 },
192 }; 192 };
193 193
194 /* 194 /*
195 * 'atl' class 195 * 'atl' class
196 * 196 *
197 */ 197 */
198 198
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = { 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl", 200 .name = "atl",
201 }; 201 };
202 202
203 /* atl */ 203 /* atl */
204 static struct omap_hwmod dra7xx_atl_hwmod = { 204 static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl", 205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class, 206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm", 207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux", 208 .main_clk = "atl_gfclk_mux",
209 .prcm = { 209 .prcm = {
210 .omap4 = { 210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, 211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, 212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL, 213 .modulemode = MODULEMODE_SWCTRL,
214 }, 214 },
215 }, 215 },
216 }; 216 };
217 217
218 /* 218 /*
219 * 'bb2d' class 219 * 'bb2d' class
220 * 220 *
221 */ 221 */
222 222
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = { 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d", 224 .name = "bb2d",
225 }; 225 };
226 226
227 /* bb2d */ 227 /* bb2d */
228 static struct omap_hwmod dra7xx_bb2d_hwmod = { 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d", 229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class, 230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm", 231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck", 232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = { 233 .prcm = {
234 .omap4 = { 234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET, 235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET, 236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL, 237 .modulemode = MODULEMODE_SWCTRL,
238 }, 238 },
239 }, 239 },
240 }; 240 };
241 241
242 /* 242 /*
243 * 'counter' class 243 * 'counter' class
244 * 244 *
245 */ 245 */
246 246
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = { 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000, 248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010, 249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE, 250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP), 252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1, 253 .sysc_fields = &omap_hwmod_sysc_type1,
254 }; 254 };
255 255
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = { 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter", 257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc, 258 .sysc = &dra7xx_counter_sysc,
259 }; 259 };
260 260
261 /* counter_32k */ 261 /* counter_32k */
262 static struct omap_hwmod dra7xx_counter_32k_hwmod = { 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k", 263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class, 264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm", 265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE, 266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux", 267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = { 268 .prcm = {
269 .omap4 = { 269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, 270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, 271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 }, 272 },
273 }, 273 },
274 }; 274 };
275 275
276 /* 276 /*
277 * 'ctrl_module' class 277 * 'ctrl_module' class
278 * 278 *
279 */ 279 */
280 280
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = { 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module", 282 .name = "ctrl_module",
283 }; 283 };
284 284
285 /* ctrl_module_wkup */ 285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup", 287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class, 288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm", 289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = { 290 .prcm = {
291 .omap4 = { 291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 }, 293 },
294 }, 294 },
295 }; 295 };
296 296
297 /* 297 /*
298 * 'gmac' class 298 * 'gmac' class
299 * cpsw/gmac sub system 299 * cpsw/gmac sub system
300 */ 300 */
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = { 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0, 302 .rev_offs = 0x0,
303 .sysc_offs = 0x8, 303 .sysc_offs = 0x8,
304 .syss_offs = 0x4, 304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS), 306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | 307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO), 308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3, 309 .sysc_fields = &omap_hwmod_sysc_type3,
310 }; 310 };
311 311
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = { 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac", 313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc, 314 .sysc = &dra7xx_gmac_sysc,
315 }; 315 };
316 316
317 static struct omap_hwmod dra7xx_gmac_hwmod = { 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac", 318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class, 319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm", 320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck", 322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1, 323 .mpu_rt_idx = 1,
324 .prcm = { 324 .prcm = {
325 .omap4 = { 325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET, 326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET, 327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL, 328 .modulemode = MODULEMODE_SWCTRL,
329 }, 329 },
330 }, 330 },
331 }; 331 };
332 332
333 /* 333 /*
334 * 'mdio' class 334 * 'mdio' class
335 */ 335 */
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = { 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio", 337 .name = "davinci_mdio",
338 }; 338 };
339 339
340 static struct omap_hwmod dra7xx_mdio_hwmod = { 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio", 341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class, 342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm", 343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck", 344 .main_clk = "dpll_gmac_ck",
345 }; 345 };
346 346
347 /* 347 /*
348 * 'dcan' class 348 * 'dcan' class
349 * 349 *
350 */ 350 */
351 351
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = { 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan", 353 .name = "dcan",
354 }; 354 };
355 355
356 /* dcan1 */ 356 /* dcan1 */
357 static struct omap_hwmod dra7xx_dcan1_hwmod = { 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1", 358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class, 359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm", 360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux", 361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = { 362 .prcm = {
363 .omap4 = { 363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET, 364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET, 365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL, 366 .modulemode = MODULEMODE_SWCTRL,
367 }, 367 },
368 }, 368 },
369 }; 369 };
370 370
371 /* dcan2 */ 371 /* dcan2 */
372 static struct omap_hwmod dra7xx_dcan2_hwmod = { 372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2", 373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class, 374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm", 375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1", 376 .main_clk = "sys_clkin1",
377 .prcm = { 377 .prcm = {
378 .omap4 = { 378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET, 379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET, 380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL, 381 .modulemode = MODULEMODE_SWCTRL,
382 }, 382 },
383 }, 383 },
384 }; 384 };
385 385
386 /* 386 /*
387 * 'dma' class 387 * 'dma' class
388 * 388 *
389 */ 389 */
390 390
391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = { 391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000, 392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c, 393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028, 394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | 396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS), 398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1, 402 .sysc_fields = &omap_hwmod_sysc_type1,
403 }; 403 };
404 404
405 static struct omap_hwmod_class dra7xx_dma_hwmod_class = { 405 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma", 406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc, 407 .sysc = &dra7xx_dma_sysc,
408 }; 408 };
409 409
410 /* dma dev_attr */ 410 /* dma dev_attr */
411 static struct omap_dma_dev_attr dma_dev_attr = { 411 static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32, 414 .lch_count = 32,
415 }; 415 };
416 416
417 /* dma_system */ 417 /* dma_system */
418 static struct omap_hwmod dra7xx_dma_system_hwmod = { 418 static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system", 419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class, 420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm", 421 .clkdm_name = "dma_clkdm",
422 .main_clk = "l3_iclk_div", 422 .main_clk = "l3_iclk_div",
423 .prcm = { 423 .prcm = {
424 .omap4 = { 424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, 425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, 426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 }, 427 },
428 }, 428 },
429 .dev_attr = &dma_dev_attr, 429 .dev_attr = &dma_dev_attr,
430 }; 430 };
431 431
432 /* 432 /*
433 * 'tpcc' class 433 * 'tpcc' class
434 * 434 *
435 */ 435 */
436 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = { 436 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
437 .name = "tpcc", 437 .name = "tpcc",
438 }; 438 };
439 439
440 static struct omap_hwmod dra7xx_tpcc_hwmod = { 440 static struct omap_hwmod dra7xx_tpcc_hwmod = {
441 .name = "tpcc", 441 .name = "tpcc",
442 .class = &dra7xx_tpcc_hwmod_class, 442 .class = &dra7xx_tpcc_hwmod_class,
443 .clkdm_name = "l3main1_clkdm", 443 .clkdm_name = "l3main1_clkdm",
444 .main_clk = "l3_iclk_div", 444 .main_clk = "l3_iclk_div",
445 .prcm = { 445 .prcm = {
446 .omap4 = { 446 .omap4 = {
447 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET, 447 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
448 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET, 448 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
449 }, 449 },
450 }, 450 },
451 }; 451 };
452 452
453 /* 453 /*
454 * 'tptc' class 454 * 'tptc' class
455 * 455 *
456 */ 456 */
457 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = { 457 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
458 .name = "tptc", 458 .name = "tptc",
459 }; 459 };
460 460
461 /* tptc0 */ 461 /* tptc0 */
462 static struct omap_hwmod dra7xx_tptc0_hwmod = { 462 static struct omap_hwmod dra7xx_tptc0_hwmod = {
463 .name = "tptc0", 463 .name = "tptc0",
464 .class = &dra7xx_tptc_hwmod_class, 464 .class = &dra7xx_tptc_hwmod_class,
465 .clkdm_name = "l3main1_clkdm", 465 .clkdm_name = "l3main1_clkdm",
466 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 466 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
467 .main_clk = "l3_iclk_div", 467 .main_clk = "l3_iclk_div",
468 .prcm = { 468 .prcm = {
469 .omap4 = { 469 .omap4 = {
470 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET, 470 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
471 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET, 471 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
472 .modulemode = MODULEMODE_HWCTRL, 472 .modulemode = MODULEMODE_HWCTRL,
473 }, 473 },
474 }, 474 },
475 }; 475 };
476 476
477 /* tptc1 */ 477 /* tptc1 */
478 static struct omap_hwmod dra7xx_tptc1_hwmod = { 478 static struct omap_hwmod dra7xx_tptc1_hwmod = {
479 .name = "tptc1", 479 .name = "tptc1",
480 .class = &dra7xx_tptc_hwmod_class, 480 .class = &dra7xx_tptc_hwmod_class,
481 .clkdm_name = "l3main1_clkdm", 481 .clkdm_name = "l3main1_clkdm",
482 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 482 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
483 .main_clk = "l3_iclk_div", 483 .main_clk = "l3_iclk_div",
484 .prcm = { 484 .prcm = {
485 .omap4 = { 485 .omap4 = {
486 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET, 486 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
487 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET, 487 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
488 .modulemode = MODULEMODE_HWCTRL, 488 .modulemode = MODULEMODE_HWCTRL,
489 }, 489 },
490 }, 490 },
491 }; 491 };
492 492
493 /* 493 /*
494 * 'dss' class 494 * 'dss' class
495 * 495 *
496 */ 496 */
497 497
498 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = { 498 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
499 .rev_offs = 0x0000, 499 .rev_offs = 0x0000,
500 .syss_offs = 0x0014, 500 .syss_offs = 0x0014,
501 .sysc_flags = SYSS_HAS_RESET_STATUS, 501 .sysc_flags = SYSS_HAS_RESET_STATUS,
502 }; 502 };
503 503
504 static struct omap_hwmod_class dra7xx_dss_hwmod_class = { 504 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
505 .name = "dss", 505 .name = "dss",
506 .sysc = &dra7xx_dss_sysc, 506 .sysc = &dra7xx_dss_sysc,
507 .reset = omap_dss_reset, 507 .reset = omap_dss_reset,
508 }; 508 };
509 509
510 /* dss */ 510 /* dss */
511 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = { 511 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
512 { .dma_req = 75 + DRA7XX_DMA_REQ_START }, 512 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
513 { .dma_req = -1 } 513 { .dma_req = -1 }
514 }; 514 };
515 515
516 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 516 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
517 { .role = "dss_clk", .clk = "dss_dss_clk" }, 517 { .role = "dss_clk", .clk = "dss_dss_clk" },
518 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, 518 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
519 { .role = "32khz_clk", .clk = "dss_32khz_clk" }, 519 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
520 { .role = "video2_clk", .clk = "dss_video2_clk" }, 520 { .role = "video2_clk", .clk = "dss_video2_clk" },
521 { .role = "video1_clk", .clk = "dss_video1_clk" }, 521 { .role = "video1_clk", .clk = "dss_video1_clk" },
522 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, 522 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
523 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" }, 523 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
524 }; 524 };
525 525
526 static struct omap_hwmod dra7xx_dss_hwmod = { 526 static struct omap_hwmod dra7xx_dss_hwmod = {
527 .name = "dss_core", 527 .name = "dss_core",
528 .class = &dra7xx_dss_hwmod_class, 528 .class = &dra7xx_dss_hwmod_class,
529 .clkdm_name = "dss_clkdm", 529 .clkdm_name = "dss_clkdm",
530 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 530 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
531 .sdma_reqs = dra7xx_dss_sdma_reqs, 531 .sdma_reqs = dra7xx_dss_sdma_reqs,
532 .main_clk = "dss_dss_clk", 532 .main_clk = "dss_dss_clk",
533 .prcm = { 533 .prcm = {
534 .omap4 = { 534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, 535 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET, 536 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
537 .modulemode = MODULEMODE_SWCTRL, 537 .modulemode = MODULEMODE_SWCTRL,
538 }, 538 },
539 }, 539 },
540 .opt_clks = dss_opt_clks, 540 .opt_clks = dss_opt_clks,
541 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 541 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
542 }; 542 };
543 543
544 /* 544 /*
545 * 'dispc' class 545 * 'dispc' class
546 * display controller 546 * display controller
547 */ 547 */
548 548
549 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = { 549 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
550 .rev_offs = 0x0000, 550 .rev_offs = 0x0000,
551 .sysc_offs = 0x0010, 551 .sysc_offs = 0x0010,
552 .syss_offs = 0x0014, 552 .syss_offs = 0x0014,
553 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 553 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
554 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | 554 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
555 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 555 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
556 SYSS_HAS_RESET_STATUS), 556 SYSS_HAS_RESET_STATUS),
557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
558 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 558 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
559 .sysc_fields = &omap_hwmod_sysc_type1, 559 .sysc_fields = &omap_hwmod_sysc_type1,
560 }; 560 };
561 561
562 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = { 562 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
563 .name = "dispc", 563 .name = "dispc",
564 .sysc = &dra7xx_dispc_sysc, 564 .sysc = &dra7xx_dispc_sysc,
565 }; 565 };
566 566
567 /* dss_dispc */ 567 /* dss_dispc */
568 /* dss_dispc dev_attr */ 568 /* dss_dispc dev_attr */
569 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = { 569 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
570 .has_framedonetv_irq = 1, 570 .has_framedonetv_irq = 1,
571 .manager_count = 4, 571 .manager_count = 4,
572 }; 572 };
573 573
574 static struct omap_hwmod dra7xx_dss_dispc_hwmod = { 574 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
575 .name = "dss_dispc", 575 .name = "dss_dispc",
576 .class = &dra7xx_dispc_hwmod_class, 576 .class = &dra7xx_dispc_hwmod_class,
577 .clkdm_name = "dss_clkdm", 577 .clkdm_name = "dss_clkdm",
578 .main_clk = "dss_dss_clk", 578 .main_clk = "dss_dss_clk",
579 .prcm = { 579 .prcm = {
580 .omap4 = { 580 .omap4 = {
581 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, 581 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
582 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 582 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
583 }, 583 },
584 }, 584 },
585 .dev_attr = &dss_dispc_dev_attr, 585 .dev_attr = &dss_dispc_dev_attr,
586 .parent_hwmod = &dra7xx_dss_hwmod, 586 .parent_hwmod = &dra7xx_dss_hwmod,
587 }; 587 };
588 588
589 /* 589 /*
590 * 'hdmi' class 590 * 'hdmi' class
591 * hdmi controller 591 * hdmi controller
592 */ 592 */
593 593
594 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = { 594 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
595 .rev_offs = 0x0000, 595 .rev_offs = 0x0000,
596 .sysc_offs = 0x0010, 596 .sysc_offs = 0x0010,
597 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 597 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
598 SYSC_HAS_SOFTRESET), 598 SYSC_HAS_SOFTRESET),
599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
600 SIDLE_SMART_WKUP), 600 SIDLE_SMART_WKUP),
601 .sysc_fields = &omap_hwmod_sysc_type2, 601 .sysc_fields = &omap_hwmod_sysc_type2,
602 }; 602 };
603 603
604 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = { 604 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
605 .name = "hdmi", 605 .name = "hdmi",
606 .sysc = &dra7xx_hdmi_sysc, 606 .sysc = &dra7xx_hdmi_sysc,
607 }; 607 };
608 608
609 /* dss_hdmi */ 609 /* dss_hdmi */
610 610
611 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { 611 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
612 { .role = "sys_clk", .clk = "dss_hdmi_clk" }, 612 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
613 }; 613 };
614 614
615 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { 615 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
616 .name = "dss_hdmi", 616 .name = "dss_hdmi",
617 .class = &dra7xx_hdmi_hwmod_class, 617 .class = &dra7xx_hdmi_hwmod_class,
618 .clkdm_name = "dss_clkdm", 618 .clkdm_name = "dss_clkdm",
619 .main_clk = "dss_48mhz_clk", 619 .main_clk = "dss_48mhz_clk",
620 .prcm = { 620 .prcm = {
621 .omap4 = { 621 .omap4 = {
622 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, 622 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
623 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 623 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
624 }, 624 },
625 }, 625 },
626 .opt_clks = dss_hdmi_opt_clks, 626 .opt_clks = dss_hdmi_opt_clks,
627 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), 627 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
628 .parent_hwmod = &dra7xx_dss_hwmod, 628 .parent_hwmod = &dra7xx_dss_hwmod,
629 }; 629 };
630 630
631 /* 631 /*
632 * 'elm' class 632 * 'elm' class
633 * 633 *
634 */ 634 */
635 635
636 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = { 636 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
637 .rev_offs = 0x0000, 637 .rev_offs = 0x0000,
638 .sysc_offs = 0x0010, 638 .sysc_offs = 0x0010,
639 .syss_offs = 0x0014, 639 .syss_offs = 0x0014,
640 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 640 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
641 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 641 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
642 SYSS_HAS_RESET_STATUS), 642 SYSS_HAS_RESET_STATUS),
643 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 643 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
644 SIDLE_SMART_WKUP), 644 SIDLE_SMART_WKUP),
645 .sysc_fields = &omap_hwmod_sysc_type1, 645 .sysc_fields = &omap_hwmod_sysc_type1,
646 }; 646 };
647 647
648 static struct omap_hwmod_class dra7xx_elm_hwmod_class = { 648 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
649 .name = "elm", 649 .name = "elm",
650 .sysc = &dra7xx_elm_sysc, 650 .sysc = &dra7xx_elm_sysc,
651 }; 651 };
652 652
653 /* elm */ 653 /* elm */
654 654
655 static struct omap_hwmod dra7xx_elm_hwmod = { 655 static struct omap_hwmod dra7xx_elm_hwmod = {
656 .name = "elm", 656 .name = "elm",
657 .class = &dra7xx_elm_hwmod_class, 657 .class = &dra7xx_elm_hwmod_class,
658 .clkdm_name = "l4per_clkdm", 658 .clkdm_name = "l4per_clkdm",
659 .main_clk = "l3_iclk_div", 659 .main_clk = "l3_iclk_div",
660 .prcm = { 660 .prcm = {
661 .omap4 = { 661 .omap4 = {
662 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET, 662 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
663 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET, 663 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
664 }, 664 },
665 }, 665 },
666 }; 666 };
667 667
668 /* 668 /*
669 * 'gpio' class 669 * 'gpio' class
670 * 670 *
671 */ 671 */
672 672
673 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = { 673 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
674 .rev_offs = 0x0000, 674 .rev_offs = 0x0000,
675 .sysc_offs = 0x0010, 675 .sysc_offs = 0x0010,
676 .syss_offs = 0x0114, 676 .syss_offs = 0x0114,
677 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 677 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
678 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 678 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
679 SYSS_HAS_RESET_STATUS), 679 SYSS_HAS_RESET_STATUS),
680 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 680 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
681 SIDLE_SMART_WKUP), 681 SIDLE_SMART_WKUP),
682 .sysc_fields = &omap_hwmod_sysc_type1, 682 .sysc_fields = &omap_hwmod_sysc_type1,
683 }; 683 };
684 684
685 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = { 685 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
686 .name = "gpio", 686 .name = "gpio",
687 .sysc = &dra7xx_gpio_sysc, 687 .sysc = &dra7xx_gpio_sysc,
688 .rev = 2, 688 .rev = 2,
689 }; 689 };
690 690
691 /* gpio dev_attr */ 691 /* gpio dev_attr */
692 static struct omap_gpio_dev_attr gpio_dev_attr = { 692 static struct omap_gpio_dev_attr gpio_dev_attr = {
693 .bank_width = 32, 693 .bank_width = 32,
694 .dbck_flag = true, 694 .dbck_flag = true,
695 }; 695 };
696 696
697 /* gpio1 */ 697 /* gpio1 */
698 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 698 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
699 { .role = "dbclk", .clk = "gpio1_dbclk" }, 699 { .role = "dbclk", .clk = "gpio1_dbclk" },
700 }; 700 };
701 701
702 static struct omap_hwmod dra7xx_gpio1_hwmod = { 702 static struct omap_hwmod dra7xx_gpio1_hwmod = {
703 .name = "gpio1", 703 .name = "gpio1",
704 .class = &dra7xx_gpio_hwmod_class, 704 .class = &dra7xx_gpio_hwmod_class,
705 .clkdm_name = "wkupaon_clkdm", 705 .clkdm_name = "wkupaon_clkdm",
706 .main_clk = "wkupaon_iclk_mux", 706 .main_clk = "wkupaon_iclk_mux",
707 .prcm = { 707 .prcm = {
708 .omap4 = { 708 .omap4 = {
709 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, 709 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
710 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, 710 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
711 .modulemode = MODULEMODE_HWCTRL, 711 .modulemode = MODULEMODE_HWCTRL,
712 }, 712 },
713 }, 713 },
714 .opt_clks = gpio1_opt_clks, 714 .opt_clks = gpio1_opt_clks,
715 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 715 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
716 .dev_attr = &gpio_dev_attr, 716 .dev_attr = &gpio_dev_attr,
717 }; 717 };
718 718
719 /* gpio2 */ 719 /* gpio2 */
720 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 720 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
721 { .role = "dbclk", .clk = "gpio2_dbclk" }, 721 { .role = "dbclk", .clk = "gpio2_dbclk" },
722 }; 722 };
723 723
724 static struct omap_hwmod dra7xx_gpio2_hwmod = { 724 static struct omap_hwmod dra7xx_gpio2_hwmod = {
725 .name = "gpio2", 725 .name = "gpio2",
726 .class = &dra7xx_gpio_hwmod_class, 726 .class = &dra7xx_gpio_hwmod_class,
727 .clkdm_name = "l4per_clkdm", 727 .clkdm_name = "l4per_clkdm",
728 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 728 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
729 .main_clk = "l3_iclk_div", 729 .main_clk = "l3_iclk_div",
730 .prcm = { 730 .prcm = {
731 .omap4 = { 731 .omap4 = {
732 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, 732 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
733 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, 733 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
734 .modulemode = MODULEMODE_HWCTRL, 734 .modulemode = MODULEMODE_HWCTRL,
735 }, 735 },
736 }, 736 },
737 .opt_clks = gpio2_opt_clks, 737 .opt_clks = gpio2_opt_clks,
738 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 738 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
739 .dev_attr = &gpio_dev_attr, 739 .dev_attr = &gpio_dev_attr,
740 }; 740 };
741 741
742 /* gpio3 */ 742 /* gpio3 */
743 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 743 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
744 { .role = "dbclk", .clk = "gpio3_dbclk" }, 744 { .role = "dbclk", .clk = "gpio3_dbclk" },
745 }; 745 };
746 746
747 static struct omap_hwmod dra7xx_gpio3_hwmod = { 747 static struct omap_hwmod dra7xx_gpio3_hwmod = {
748 .name = "gpio3", 748 .name = "gpio3",
749 .class = &dra7xx_gpio_hwmod_class, 749 .class = &dra7xx_gpio_hwmod_class,
750 .clkdm_name = "l4per_clkdm", 750 .clkdm_name = "l4per_clkdm",
751 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 751 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
752 .main_clk = "l3_iclk_div", 752 .main_clk = "l3_iclk_div",
753 .prcm = { 753 .prcm = {
754 .omap4 = { 754 .omap4 = {
755 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, 755 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
756 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, 756 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
757 .modulemode = MODULEMODE_HWCTRL, 757 .modulemode = MODULEMODE_HWCTRL,
758 }, 758 },
759 }, 759 },
760 .opt_clks = gpio3_opt_clks, 760 .opt_clks = gpio3_opt_clks,
761 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 761 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
762 .dev_attr = &gpio_dev_attr, 762 .dev_attr = &gpio_dev_attr,
763 }; 763 };
764 764
765 /* gpio4 */ 765 /* gpio4 */
766 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 766 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
767 { .role = "dbclk", .clk = "gpio4_dbclk" }, 767 { .role = "dbclk", .clk = "gpio4_dbclk" },
768 }; 768 };
769 769
770 static struct omap_hwmod dra7xx_gpio4_hwmod = { 770 static struct omap_hwmod dra7xx_gpio4_hwmod = {
771 .name = "gpio4", 771 .name = "gpio4",
772 .class = &dra7xx_gpio_hwmod_class, 772 .class = &dra7xx_gpio_hwmod_class,
773 .clkdm_name = "l4per_clkdm", 773 .clkdm_name = "l4per_clkdm",
774 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 774 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
775 .main_clk = "l3_iclk_div", 775 .main_clk = "l3_iclk_div",
776 .prcm = { 776 .prcm = {
777 .omap4 = { 777 .omap4 = {
778 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, 778 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
779 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, 779 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
780 .modulemode = MODULEMODE_HWCTRL, 780 .modulemode = MODULEMODE_HWCTRL,
781 }, 781 },
782 }, 782 },
783 .opt_clks = gpio4_opt_clks, 783 .opt_clks = gpio4_opt_clks,
784 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 784 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
785 .dev_attr = &gpio_dev_attr, 785 .dev_attr = &gpio_dev_attr,
786 }; 786 };
787 787
788 /* gpio5 */ 788 /* gpio5 */
789 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 789 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
790 { .role = "dbclk", .clk = "gpio5_dbclk" }, 790 { .role = "dbclk", .clk = "gpio5_dbclk" },
791 }; 791 };
792 792
793 static struct omap_hwmod dra7xx_gpio5_hwmod = { 793 static struct omap_hwmod dra7xx_gpio5_hwmod = {
794 .name = "gpio5", 794 .name = "gpio5",
795 .class = &dra7xx_gpio_hwmod_class, 795 .class = &dra7xx_gpio_hwmod_class,
796 .clkdm_name = "l4per_clkdm", 796 .clkdm_name = "l4per_clkdm",
797 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 797 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
798 .main_clk = "l3_iclk_div", 798 .main_clk = "l3_iclk_div",
799 .prcm = { 799 .prcm = {
800 .omap4 = { 800 .omap4 = {
801 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, 801 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
802 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, 802 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
803 .modulemode = MODULEMODE_HWCTRL, 803 .modulemode = MODULEMODE_HWCTRL,
804 }, 804 },
805 }, 805 },
806 .opt_clks = gpio5_opt_clks, 806 .opt_clks = gpio5_opt_clks,
807 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 807 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
808 .dev_attr = &gpio_dev_attr, 808 .dev_attr = &gpio_dev_attr,
809 }; 809 };
810 810
811 /* gpio6 */ 811 /* gpio6 */
812 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 812 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
813 { .role = "dbclk", .clk = "gpio6_dbclk" }, 813 { .role = "dbclk", .clk = "gpio6_dbclk" },
814 }; 814 };
815 815
816 static struct omap_hwmod dra7xx_gpio6_hwmod = { 816 static struct omap_hwmod dra7xx_gpio6_hwmod = {
817 .name = "gpio6", 817 .name = "gpio6",
818 .class = &dra7xx_gpio_hwmod_class, 818 .class = &dra7xx_gpio_hwmod_class,
819 .clkdm_name = "l4per_clkdm", 819 .clkdm_name = "l4per_clkdm",
820 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 820 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
821 .main_clk = "l3_iclk_div", 821 .main_clk = "l3_iclk_div",
822 .prcm = { 822 .prcm = {
823 .omap4 = { 823 .omap4 = {
824 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, 824 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
825 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, 825 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
826 .modulemode = MODULEMODE_HWCTRL, 826 .modulemode = MODULEMODE_HWCTRL,
827 }, 827 },
828 }, 828 },
829 .opt_clks = gpio6_opt_clks, 829 .opt_clks = gpio6_opt_clks,
830 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 830 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
831 .dev_attr = &gpio_dev_attr, 831 .dev_attr = &gpio_dev_attr,
832 }; 832 };
833 833
834 /* gpio7 */ 834 /* gpio7 */
835 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { 835 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
836 { .role = "dbclk", .clk = "gpio7_dbclk" }, 836 { .role = "dbclk", .clk = "gpio7_dbclk" },
837 }; 837 };
838 838
839 static struct omap_hwmod dra7xx_gpio7_hwmod = { 839 static struct omap_hwmod dra7xx_gpio7_hwmod = {
840 .name = "gpio7", 840 .name = "gpio7",
841 .class = &dra7xx_gpio_hwmod_class, 841 .class = &dra7xx_gpio_hwmod_class,
842 .clkdm_name = "l4per_clkdm", 842 .clkdm_name = "l4per_clkdm",
843 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 843 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
844 .main_clk = "l3_iclk_div", 844 .main_clk = "l3_iclk_div",
845 .prcm = { 845 .prcm = {
846 .omap4 = { 846 .omap4 = {
847 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, 847 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
848 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, 848 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
849 .modulemode = MODULEMODE_HWCTRL, 849 .modulemode = MODULEMODE_HWCTRL,
850 }, 850 },
851 }, 851 },
852 .opt_clks = gpio7_opt_clks, 852 .opt_clks = gpio7_opt_clks,
853 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), 853 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
854 .dev_attr = &gpio_dev_attr, 854 .dev_attr = &gpio_dev_attr,
855 }; 855 };
856 856
857 /* gpio8 */ 857 /* gpio8 */
858 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { 858 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
859 { .role = "dbclk", .clk = "gpio8_dbclk" }, 859 { .role = "dbclk", .clk = "gpio8_dbclk" },
860 }; 860 };
861 861
862 static struct omap_hwmod dra7xx_gpio8_hwmod = { 862 static struct omap_hwmod dra7xx_gpio8_hwmod = {
863 .name = "gpio8", 863 .name = "gpio8",
864 .class = &dra7xx_gpio_hwmod_class, 864 .class = &dra7xx_gpio_hwmod_class,
865 .clkdm_name = "l4per_clkdm", 865 .clkdm_name = "l4per_clkdm",
866 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 866 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
867 .main_clk = "l3_iclk_div", 867 .main_clk = "l3_iclk_div",
868 .prcm = { 868 .prcm = {
869 .omap4 = { 869 .omap4 = {
870 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, 870 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
871 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, 871 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
872 .modulemode = MODULEMODE_HWCTRL, 872 .modulemode = MODULEMODE_HWCTRL,
873 }, 873 },
874 }, 874 },
875 .opt_clks = gpio8_opt_clks, 875 .opt_clks = gpio8_opt_clks,
876 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), 876 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
877 .dev_attr = &gpio_dev_attr, 877 .dev_attr = &gpio_dev_attr,
878 }; 878 };
879 879
880 /* 880 /*
881 * 'gpmc' class 881 * 'gpmc' class
882 * 882 *
883 */ 883 */
884 884
885 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { 885 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
886 .rev_offs = 0x0000, 886 .rev_offs = 0x0000,
887 .sysc_offs = 0x0010, 887 .sysc_offs = 0x0010,
888 .syss_offs = 0x0014, 888 .syss_offs = 0x0014,
889 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 889 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
890 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 890 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
891 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 891 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
892 .sysc_fields = &omap_hwmod_sysc_type1, 892 .sysc_fields = &omap_hwmod_sysc_type1,
893 }; 893 };
894 894
895 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { 895 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
896 .name = "gpmc", 896 .name = "gpmc",
897 .sysc = &dra7xx_gpmc_sysc, 897 .sysc = &dra7xx_gpmc_sysc,
898 }; 898 };
899 899
900 /* gpmc */ 900 /* gpmc */
901 901
902 static struct omap_hwmod dra7xx_gpmc_hwmod = { 902 static struct omap_hwmod dra7xx_gpmc_hwmod = {
903 .name = "gpmc", 903 .name = "gpmc",
904 .class = &dra7xx_gpmc_hwmod_class, 904 .class = &dra7xx_gpmc_hwmod_class,
905 .clkdm_name = "l3main1_clkdm", 905 .clkdm_name = "l3main1_clkdm",
906 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 906 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
907 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 907 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
908 .main_clk = "l3_iclk_div", 908 .main_clk = "l3_iclk_div",
909 .prcm = { 909 .prcm = {
910 .omap4 = { 910 .omap4 = {
911 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, 911 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
912 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, 912 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
913 .modulemode = MODULEMODE_HWCTRL, 913 .modulemode = MODULEMODE_HWCTRL,
914 }, 914 },
915 }, 915 },
916 }; 916 };
917 917
918 /* 918 /*
919 * 'hdq1w' class 919 * 'hdq1w' class
920 * 920 *
921 */ 921 */
922 922
923 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = { 923 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
924 .rev_offs = 0x0000, 924 .rev_offs = 0x0000,
925 .sysc_offs = 0x0014, 925 .sysc_offs = 0x0014,
926 .syss_offs = 0x0018, 926 .syss_offs = 0x0018,
927 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | 927 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
928 SYSS_HAS_RESET_STATUS), 928 SYSS_HAS_RESET_STATUS),
929 .sysc_fields = &omap_hwmod_sysc_type1, 929 .sysc_fields = &omap_hwmod_sysc_type1,
930 }; 930 };
931 931
932 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = { 932 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
933 .name = "hdq1w", 933 .name = "hdq1w",
934 .sysc = &dra7xx_hdq1w_sysc, 934 .sysc = &dra7xx_hdq1w_sysc,
935 }; 935 };
936 936
937 /* hdq1w */ 937 /* hdq1w */
938 938
939 static struct omap_hwmod dra7xx_hdq1w_hwmod = { 939 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
940 .name = "hdq1w", 940 .name = "hdq1w",
941 .class = &dra7xx_hdq1w_hwmod_class, 941 .class = &dra7xx_hdq1w_hwmod_class,
942 .clkdm_name = "l4per_clkdm", 942 .clkdm_name = "l4per_clkdm",
943 .flags = HWMOD_INIT_NO_RESET, 943 .flags = HWMOD_INIT_NO_RESET,
944 .main_clk = "func_12m_fclk", 944 .main_clk = "func_12m_fclk",
945 .prcm = { 945 .prcm = {
946 .omap4 = { 946 .omap4 = {
947 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, 947 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
948 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET, 948 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
949 .modulemode = MODULEMODE_SWCTRL, 949 .modulemode = MODULEMODE_SWCTRL,
950 }, 950 },
951 }, 951 },
952 }; 952 };
953 953
954 /* 954 /*
955 * 'i2c' class 955 * 'i2c' class
956 * 956 *
957 */ 957 */
958 958
959 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = { 959 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
960 .sysc_offs = 0x0010, 960 .sysc_offs = 0x0010,
961 .syss_offs = 0x0090, 961 .syss_offs = 0x0090,
962 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 962 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
963 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 963 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
964 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 964 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
965 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 965 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
966 SIDLE_SMART_WKUP), 966 SIDLE_SMART_WKUP),
967 .clockact = CLOCKACT_TEST_ICLK, 967 .clockact = CLOCKACT_TEST_ICLK,
968 .sysc_fields = &omap_hwmod_sysc_type1, 968 .sysc_fields = &omap_hwmod_sysc_type1,
969 }; 969 };
970 970
971 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = { 971 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
972 .name = "i2c", 972 .name = "i2c",
973 .sysc = &dra7xx_i2c_sysc, 973 .sysc = &dra7xx_i2c_sysc,
974 .reset = &omap_i2c_reset, 974 .reset = &omap_i2c_reset,
975 .rev = OMAP_I2C_IP_VERSION_2, 975 .rev = OMAP_I2C_IP_VERSION_2,
976 }; 976 };
977 977
978 /* i2c dev_attr */ 978 /* i2c dev_attr */
979 static struct omap_i2c_dev_attr i2c_dev_attr = { 979 static struct omap_i2c_dev_attr i2c_dev_attr = {
980 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, 980 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
981 }; 981 };
982 982
983 /* i2c1 */ 983 /* i2c1 */
984 static struct omap_hwmod dra7xx_i2c1_hwmod = { 984 static struct omap_hwmod dra7xx_i2c1_hwmod = {
985 .name = "i2c1", 985 .name = "i2c1",
986 .class = &dra7xx_i2c_hwmod_class, 986 .class = &dra7xx_i2c_hwmod_class,
987 .clkdm_name = "l4per_clkdm", 987 .clkdm_name = "l4per_clkdm",
988 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 988 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
989 .main_clk = "func_96m_fclk", 989 .main_clk = "func_96m_fclk",
990 .prcm = { 990 .prcm = {
991 .omap4 = { 991 .omap4 = {
992 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, 992 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
993 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET, 993 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
994 .modulemode = MODULEMODE_SWCTRL, 994 .modulemode = MODULEMODE_SWCTRL,
995 }, 995 },
996 }, 996 },
997 .dev_attr = &i2c_dev_attr, 997 .dev_attr = &i2c_dev_attr,
998 }; 998 };
999 999
1000 /* i2c2 */ 1000 /* i2c2 */
1001 static struct omap_hwmod dra7xx_i2c2_hwmod = { 1001 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1002 .name = "i2c2", 1002 .name = "i2c2",
1003 .class = &dra7xx_i2c_hwmod_class, 1003 .class = &dra7xx_i2c_hwmod_class,
1004 .clkdm_name = "l4per_clkdm", 1004 .clkdm_name = "l4per_clkdm",
1005 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1005 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1006 .main_clk = "func_96m_fclk", 1006 .main_clk = "func_96m_fclk",
1007 .prcm = { 1007 .prcm = {
1008 .omap4 = { 1008 .omap4 = {
1009 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, 1009 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1010 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET, 1010 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1011 .modulemode = MODULEMODE_SWCTRL, 1011 .modulemode = MODULEMODE_SWCTRL,
1012 }, 1012 },
1013 }, 1013 },
1014 .dev_attr = &i2c_dev_attr, 1014 .dev_attr = &i2c_dev_attr,
1015 }; 1015 };
1016 1016
1017 /* i2c3 */ 1017 /* i2c3 */
1018 static struct omap_hwmod dra7xx_i2c3_hwmod = { 1018 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1019 .name = "i2c3", 1019 .name = "i2c3",
1020 .class = &dra7xx_i2c_hwmod_class, 1020 .class = &dra7xx_i2c_hwmod_class,
1021 .clkdm_name = "l4per_clkdm", 1021 .clkdm_name = "l4per_clkdm",
1022 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1022 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1023 .main_clk = "func_96m_fclk", 1023 .main_clk = "func_96m_fclk",
1024 .prcm = { 1024 .prcm = {
1025 .omap4 = { 1025 .omap4 = {
1026 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, 1026 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1027 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET, 1027 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1028 .modulemode = MODULEMODE_SWCTRL, 1028 .modulemode = MODULEMODE_SWCTRL,
1029 }, 1029 },
1030 }, 1030 },
1031 .dev_attr = &i2c_dev_attr, 1031 .dev_attr = &i2c_dev_attr,
1032 }; 1032 };
1033 1033
1034 /* i2c4 */ 1034 /* i2c4 */
1035 static struct omap_hwmod dra7xx_i2c4_hwmod = { 1035 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1036 .name = "i2c4", 1036 .name = "i2c4",
1037 .class = &dra7xx_i2c_hwmod_class, 1037 .class = &dra7xx_i2c_hwmod_class,
1038 .clkdm_name = "l4per_clkdm", 1038 .clkdm_name = "l4per_clkdm",
1039 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1039 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1040 .main_clk = "func_96m_fclk", 1040 .main_clk = "func_96m_fclk",
1041 .prcm = { 1041 .prcm = {
1042 .omap4 = { 1042 .omap4 = {
1043 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, 1043 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1044 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET, 1044 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1045 .modulemode = MODULEMODE_SWCTRL, 1045 .modulemode = MODULEMODE_SWCTRL,
1046 }, 1046 },
1047 }, 1047 },
1048 .dev_attr = &i2c_dev_attr, 1048 .dev_attr = &i2c_dev_attr,
1049 }; 1049 };
1050 1050
1051 /* i2c5 */ 1051 /* i2c5 */
1052 static struct omap_hwmod dra7xx_i2c5_hwmod = { 1052 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1053 .name = "i2c5", 1053 .name = "i2c5",
1054 .class = &dra7xx_i2c_hwmod_class, 1054 .class = &dra7xx_i2c_hwmod_class,
1055 .clkdm_name = "ipu_clkdm", 1055 .clkdm_name = "ipu_clkdm",
1056 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1056 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1057 .main_clk = "func_96m_fclk", 1057 .main_clk = "func_96m_fclk",
1058 .prcm = { 1058 .prcm = {
1059 .omap4 = { 1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET, 1060 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET, 1061 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1062 .modulemode = MODULEMODE_SWCTRL, 1062 .modulemode = MODULEMODE_SWCTRL,
1063 }, 1063 },
1064 }, 1064 },
1065 .dev_attr = &i2c_dev_attr, 1065 .dev_attr = &i2c_dev_attr,
1066 }; 1066 };
1067 1067
1068 /* 1068 /*
1069 * 'mailbox' class 1069 * 'mailbox' class
1070 * 1070 *
1071 */ 1071 */
1072 1072
1073 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { 1073 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1074 .rev_offs = 0x0000, 1074 .rev_offs = 0x0000,
1075 .sysc_offs = 0x0010, 1075 .sysc_offs = 0x0010,
1076 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 1076 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1077 SYSC_HAS_SOFTRESET), 1077 SYSC_HAS_SOFTRESET),
1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1079 .sysc_fields = &omap_hwmod_sysc_type2, 1079 .sysc_fields = &omap_hwmod_sysc_type2,
1080 }; 1080 };
1081 1081
1082 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { 1082 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1083 .name = "mailbox", 1083 .name = "mailbox",
1084 .sysc = &dra7xx_mailbox_sysc, 1084 .sysc = &dra7xx_mailbox_sysc,
1085 }; 1085 };
1086 1086
1087 /* mailbox1 */ 1087 /* mailbox1 */
1088 static struct omap_hwmod dra7xx_mailbox1_hwmod = { 1088 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1089 .name = "mailbox1", 1089 .name = "mailbox1",
1090 .class = &dra7xx_mailbox_hwmod_class, 1090 .class = &dra7xx_mailbox_hwmod_class,
1091 .clkdm_name = "l4cfg_clkdm", 1091 .clkdm_name = "l4cfg_clkdm",
1092 .prcm = { 1092 .prcm = {
1093 .omap4 = { 1093 .omap4 = {
1094 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET, 1094 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1095 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET, 1095 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1096 }, 1096 },
1097 }, 1097 },
1098 }; 1098 };
1099 1099
1100 /* mailbox2 */ 1100 /* mailbox2 */
1101 static struct omap_hwmod dra7xx_mailbox2_hwmod = { 1101 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1102 .name = "mailbox2", 1102 .name = "mailbox2",
1103 .class = &dra7xx_mailbox_hwmod_class, 1103 .class = &dra7xx_mailbox_hwmod_class,
1104 .clkdm_name = "l4cfg_clkdm", 1104 .clkdm_name = "l4cfg_clkdm",
1105 .prcm = { 1105 .prcm = {
1106 .omap4 = { 1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET, 1107 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET, 1108 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1109 }, 1109 },
1110 }, 1110 },
1111 }; 1111 };
1112 1112
1113 /* mailbox3 */ 1113 /* mailbox3 */
1114 static struct omap_hwmod dra7xx_mailbox3_hwmod = { 1114 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1115 .name = "mailbox3", 1115 .name = "mailbox3",
1116 .class = &dra7xx_mailbox_hwmod_class, 1116 .class = &dra7xx_mailbox_hwmod_class,
1117 .clkdm_name = "l4cfg_clkdm", 1117 .clkdm_name = "l4cfg_clkdm",
1118 .prcm = { 1118 .prcm = {
1119 .omap4 = { 1119 .omap4 = {
1120 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET, 1120 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1121 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET, 1121 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1122 }, 1122 },
1123 }, 1123 },
1124 }; 1124 };
1125 1125
1126 /* mailbox4 */ 1126 /* mailbox4 */
1127 static struct omap_hwmod dra7xx_mailbox4_hwmod = { 1127 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1128 .name = "mailbox4", 1128 .name = "mailbox4",
1129 .class = &dra7xx_mailbox_hwmod_class, 1129 .class = &dra7xx_mailbox_hwmod_class,
1130 .clkdm_name = "l4cfg_clkdm", 1130 .clkdm_name = "l4cfg_clkdm",
1131 .prcm = { 1131 .prcm = {
1132 .omap4 = { 1132 .omap4 = {
1133 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET, 1133 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1134 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET, 1134 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1135 }, 1135 },
1136 }, 1136 },
1137 }; 1137 };
1138 1138
1139 /* mailbox5 */ 1139 /* mailbox5 */
1140 static struct omap_hwmod dra7xx_mailbox5_hwmod = { 1140 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1141 .name = "mailbox5", 1141 .name = "mailbox5",
1142 .class = &dra7xx_mailbox_hwmod_class, 1142 .class = &dra7xx_mailbox_hwmod_class,
1143 .clkdm_name = "l4cfg_clkdm", 1143 .clkdm_name = "l4cfg_clkdm",
1144 .prcm = { 1144 .prcm = {
1145 .omap4 = { 1145 .omap4 = {
1146 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET, 1146 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1147 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET, 1147 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1148 }, 1148 },
1149 }, 1149 },
1150 }; 1150 };
1151 1151
1152 /* mailbox6 */ 1152 /* mailbox6 */
1153 static struct omap_hwmod dra7xx_mailbox6_hwmod = { 1153 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1154 .name = "mailbox6", 1154 .name = "mailbox6",
1155 .class = &dra7xx_mailbox_hwmod_class, 1155 .class = &dra7xx_mailbox_hwmod_class,
1156 .clkdm_name = "l4cfg_clkdm", 1156 .clkdm_name = "l4cfg_clkdm",
1157 .prcm = { 1157 .prcm = {
1158 .omap4 = { 1158 .omap4 = {
1159 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET, 1159 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1160 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET, 1160 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1161 }, 1161 },
1162 }, 1162 },
1163 }; 1163 };
1164 1164
1165 /* mailbox7 */ 1165 /* mailbox7 */
1166 static struct omap_hwmod dra7xx_mailbox7_hwmod = { 1166 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1167 .name = "mailbox7", 1167 .name = "mailbox7",
1168 .class = &dra7xx_mailbox_hwmod_class, 1168 .class = &dra7xx_mailbox_hwmod_class,
1169 .clkdm_name = "l4cfg_clkdm", 1169 .clkdm_name = "l4cfg_clkdm",
1170 .prcm = { 1170 .prcm = {
1171 .omap4 = { 1171 .omap4 = {
1172 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET, 1172 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1173 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET, 1173 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1174 }, 1174 },
1175 }, 1175 },
1176 }; 1176 };
1177 1177
1178 /* mailbox8 */ 1178 /* mailbox8 */
1179 static struct omap_hwmod dra7xx_mailbox8_hwmod = { 1179 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1180 .name = "mailbox8", 1180 .name = "mailbox8",
1181 .class = &dra7xx_mailbox_hwmod_class, 1181 .class = &dra7xx_mailbox_hwmod_class,
1182 .clkdm_name = "l4cfg_clkdm", 1182 .clkdm_name = "l4cfg_clkdm",
1183 .prcm = { 1183 .prcm = {
1184 .omap4 = { 1184 .omap4 = {
1185 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET, 1185 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1186 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET, 1186 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1187 }, 1187 },
1188 }, 1188 },
1189 }; 1189 };
1190 1190
1191 /* mailbox9 */ 1191 /* mailbox9 */
1192 static struct omap_hwmod dra7xx_mailbox9_hwmod = { 1192 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1193 .name = "mailbox9", 1193 .name = "mailbox9",
1194 .class = &dra7xx_mailbox_hwmod_class, 1194 .class = &dra7xx_mailbox_hwmod_class,
1195 .clkdm_name = "l4cfg_clkdm", 1195 .clkdm_name = "l4cfg_clkdm",
1196 .prcm = { 1196 .prcm = {
1197 .omap4 = { 1197 .omap4 = {
1198 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET, 1198 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1199 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET, 1199 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1200 }, 1200 },
1201 }, 1201 },
1202 }; 1202 };
1203 1203
1204 /* mailbox10 */ 1204 /* mailbox10 */
1205 static struct omap_hwmod dra7xx_mailbox10_hwmod = { 1205 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1206 .name = "mailbox10", 1206 .name = "mailbox10",
1207 .class = &dra7xx_mailbox_hwmod_class, 1207 .class = &dra7xx_mailbox_hwmod_class,
1208 .clkdm_name = "l4cfg_clkdm", 1208 .clkdm_name = "l4cfg_clkdm",
1209 .prcm = { 1209 .prcm = {
1210 .omap4 = { 1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET, 1211 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET, 1212 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1213 }, 1213 },
1214 }, 1214 },
1215 }; 1215 };
1216 1216
1217 /* mailbox11 */ 1217 /* mailbox11 */
1218 static struct omap_hwmod dra7xx_mailbox11_hwmod = { 1218 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1219 .name = "mailbox11", 1219 .name = "mailbox11",
1220 .class = &dra7xx_mailbox_hwmod_class, 1220 .class = &dra7xx_mailbox_hwmod_class,
1221 .clkdm_name = "l4cfg_clkdm", 1221 .clkdm_name = "l4cfg_clkdm",
1222 .prcm = { 1222 .prcm = {
1223 .omap4 = { 1223 .omap4 = {
1224 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET, 1224 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1225 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET, 1225 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1226 }, 1226 },
1227 }, 1227 },
1228 }; 1228 };
1229 1229
1230 /* mailbox12 */ 1230 /* mailbox12 */
1231 static struct omap_hwmod dra7xx_mailbox12_hwmod = { 1231 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1232 .name = "mailbox12", 1232 .name = "mailbox12",
1233 .class = &dra7xx_mailbox_hwmod_class, 1233 .class = &dra7xx_mailbox_hwmod_class,
1234 .clkdm_name = "l4cfg_clkdm", 1234 .clkdm_name = "l4cfg_clkdm",
1235 .prcm = { 1235 .prcm = {
1236 .omap4 = { 1236 .omap4 = {
1237 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET, 1237 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1238 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET, 1238 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1239 }, 1239 },
1240 }, 1240 },
1241 }; 1241 };
1242 1242
1243 /* mailbox13 */ 1243 /* mailbox13 */
1244 static struct omap_hwmod dra7xx_mailbox13_hwmod = { 1244 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1245 .name = "mailbox13", 1245 .name = "mailbox13",
1246 .class = &dra7xx_mailbox_hwmod_class, 1246 .class = &dra7xx_mailbox_hwmod_class,
1247 .clkdm_name = "l4cfg_clkdm", 1247 .clkdm_name = "l4cfg_clkdm",
1248 .prcm = { 1248 .prcm = {
1249 .omap4 = { 1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET, 1250 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET, 1251 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1252 }, 1252 },
1253 }, 1253 },
1254 }; 1254 };
1255 1255
1256 /* 1256 /*
1257 * 'mcspi' class 1257 * 'mcspi' class
1258 * 1258 *
1259 */ 1259 */
1260 1260
1261 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = { 1261 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1262 .rev_offs = 0x0000, 1262 .rev_offs = 0x0000,
1263 .sysc_offs = 0x0010, 1263 .sysc_offs = 0x0010,
1264 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 1264 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1265 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1265 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1266 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1266 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1267 SIDLE_SMART_WKUP), 1267 SIDLE_SMART_WKUP),
1268 .sysc_fields = &omap_hwmod_sysc_type2, 1268 .sysc_fields = &omap_hwmod_sysc_type2,
1269 }; 1269 };
1270 1270
1271 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = { 1271 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1272 .name = "mcspi", 1272 .name = "mcspi",
1273 .sysc = &dra7xx_mcspi_sysc, 1273 .sysc = &dra7xx_mcspi_sysc,
1274 .rev = OMAP4_MCSPI_REV, 1274 .rev = OMAP4_MCSPI_REV,
1275 }; 1275 };
1276 1276
1277 /* mcspi1 */ 1277 /* mcspi1 */
1278 /* mcspi1 dev_attr */ 1278 /* mcspi1 dev_attr */
1279 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { 1279 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1280 .num_chipselect = 4, 1280 .num_chipselect = 4,
1281 }; 1281 };
1282 1282
1283 static struct omap_hwmod dra7xx_mcspi1_hwmod = { 1283 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1284 .name = "mcspi1", 1284 .name = "mcspi1",
1285 .class = &dra7xx_mcspi_hwmod_class, 1285 .class = &dra7xx_mcspi_hwmod_class,
1286 .clkdm_name = "l4per_clkdm", 1286 .clkdm_name = "l4per_clkdm",
1287 .main_clk = "func_48m_fclk", 1287 .main_clk = "func_48m_fclk",
1288 .prcm = { 1288 .prcm = {
1289 .omap4 = { 1289 .omap4 = {
1290 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, 1290 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1291 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, 1291 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1292 .modulemode = MODULEMODE_SWCTRL, 1292 .modulemode = MODULEMODE_SWCTRL,
1293 }, 1293 },
1294 }, 1294 },
1295 .dev_attr = &mcspi1_dev_attr, 1295 .dev_attr = &mcspi1_dev_attr,
1296 }; 1296 };
1297 1297
1298 /* mcspi2 */ 1298 /* mcspi2 */
1299 /* mcspi2 dev_attr */ 1299 /* mcspi2 dev_attr */
1300 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { 1300 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1301 .num_chipselect = 2, 1301 .num_chipselect = 2,
1302 }; 1302 };
1303 1303
1304 static struct omap_hwmod dra7xx_mcspi2_hwmod = { 1304 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1305 .name = "mcspi2", 1305 .name = "mcspi2",
1306 .class = &dra7xx_mcspi_hwmod_class, 1306 .class = &dra7xx_mcspi_hwmod_class,
1307 .clkdm_name = "l4per_clkdm", 1307 .clkdm_name = "l4per_clkdm",
1308 .main_clk = "func_48m_fclk", 1308 .main_clk = "func_48m_fclk",
1309 .prcm = { 1309 .prcm = {
1310 .omap4 = { 1310 .omap4 = {
1311 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, 1311 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1312 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, 1312 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1313 .modulemode = MODULEMODE_SWCTRL, 1313 .modulemode = MODULEMODE_SWCTRL,
1314 }, 1314 },
1315 }, 1315 },
1316 .dev_attr = &mcspi2_dev_attr, 1316 .dev_attr = &mcspi2_dev_attr,
1317 }; 1317 };
1318 1318
1319 /* mcspi3 */ 1319 /* mcspi3 */
1320 /* mcspi3 dev_attr */ 1320 /* mcspi3 dev_attr */
1321 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { 1321 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1322 .num_chipselect = 2, 1322 .num_chipselect = 2,
1323 }; 1323 };
1324 1324
1325 static struct omap_hwmod dra7xx_mcspi3_hwmod = { 1325 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1326 .name = "mcspi3", 1326 .name = "mcspi3",
1327 .class = &dra7xx_mcspi_hwmod_class, 1327 .class = &dra7xx_mcspi_hwmod_class,
1328 .clkdm_name = "l4per_clkdm", 1328 .clkdm_name = "l4per_clkdm",
1329 .main_clk = "func_48m_fclk", 1329 .main_clk = "func_48m_fclk",
1330 .prcm = { 1330 .prcm = {
1331 .omap4 = { 1331 .omap4 = {
1332 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, 1332 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1333 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, 1333 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1334 .modulemode = MODULEMODE_SWCTRL, 1334 .modulemode = MODULEMODE_SWCTRL,
1335 }, 1335 },
1336 }, 1336 },
1337 .dev_attr = &mcspi3_dev_attr, 1337 .dev_attr = &mcspi3_dev_attr,
1338 }; 1338 };
1339 1339
1340 /* mcspi4 */ 1340 /* mcspi4 */
1341 /* mcspi4 dev_attr */ 1341 /* mcspi4 dev_attr */
1342 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { 1342 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1343 .num_chipselect = 1, 1343 .num_chipselect = 1,
1344 }; 1344 };
1345 1345
1346 static struct omap_hwmod dra7xx_mcspi4_hwmod = { 1346 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1347 .name = "mcspi4", 1347 .name = "mcspi4",
1348 .class = &dra7xx_mcspi_hwmod_class, 1348 .class = &dra7xx_mcspi_hwmod_class,
1349 .clkdm_name = "l4per_clkdm", 1349 .clkdm_name = "l4per_clkdm",
1350 .main_clk = "func_48m_fclk", 1350 .main_clk = "func_48m_fclk",
1351 .prcm = { 1351 .prcm = {
1352 .omap4 = { 1352 .omap4 = {
1353 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, 1353 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1354 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, 1354 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1355 .modulemode = MODULEMODE_SWCTRL, 1355 .modulemode = MODULEMODE_SWCTRL,
1356 }, 1356 },
1357 }, 1357 },
1358 .dev_attr = &mcspi4_dev_attr, 1358 .dev_attr = &mcspi4_dev_attr,
1359 }; 1359 };
1360 1360
1361 /* 1361 /*
1362 * 'mcasp' class 1362 * 'mcasp' class
1363 * 1363 *
1364 */ 1364 */
1365 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = { 1365 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1366 .sysc_offs = 0x0004, 1366 .sysc_offs = 0x0004,
1367 .sysc_flags = SYSC_HAS_SIDLEMODE, 1367 .sysc_flags = SYSC_HAS_SIDLEMODE,
1368 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1368 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1369 .sysc_fields = &omap_hwmod_sysc_type3, 1369 .sysc_fields = &omap_hwmod_sysc_type3,
1370 }; 1370 };
1371 1371
1372 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { 1372 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1373 .name = "mcasp", 1373 .name = "mcasp",
1374 .sysc = &dra7xx_mcasp_sysc, 1374 .sysc = &dra7xx_mcasp_sysc,
1375 }; 1375 };
1376 1376
1377 /* mcasp1 */ 1377 /* mcasp1 */
1378 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = { 1378 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1379 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" }, 1379 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1380 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" }, 1380 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1381 }; 1381 };
1382 1382
1383 static struct omap_hwmod dra7xx_mcasp1_hwmod = { 1383 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1384 .name = "mcasp1", 1384 .name = "mcasp1",
1385 .class = &dra7xx_mcasp_hwmod_class, 1385 .class = &dra7xx_mcasp_hwmod_class,
1386 .clkdm_name = "ipu_clkdm", 1386 .clkdm_name = "ipu_clkdm",
1387 .main_clk = "mcasp1_aux_gfclk_mux", 1387 .main_clk = "mcasp1_aux_gfclk_mux",
1388 .flags = HWMOD_OPT_CLKS_NEEDED, 1388 .flags = HWMOD_OPT_CLKS_NEEDED,
1389 .prcm = { 1389 .prcm = {
1390 .omap4 = { 1390 .omap4 = {
1391 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET, 1391 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1392 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET, 1392 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1393 .modulemode = MODULEMODE_SWCTRL, 1393 .modulemode = MODULEMODE_SWCTRL,
1394 }, 1394 },
1395 }, 1395 },
1396 .opt_clks = mcasp1_opt_clks, 1396 .opt_clks = mcasp1_opt_clks,
1397 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks), 1397 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1398 }; 1398 };
1399 1399
1400 /* mcasp2 */ 1400 /* mcasp2 */
1401 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = { 1401 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1402 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" }, 1402 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1403 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" }, 1403 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1404 }; 1404 };
1405 1405
1406 static struct omap_hwmod dra7xx_mcasp2_hwmod = { 1406 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1407 .name = "mcasp2", 1407 .name = "mcasp2",
1408 .class = &dra7xx_mcasp_hwmod_class, 1408 .class = &dra7xx_mcasp_hwmod_class,
1409 .clkdm_name = "l4per2_clkdm", 1409 .clkdm_name = "l4per2_clkdm",
1410 .main_clk = "mcasp2_aux_gfclk_mux", 1410 .main_clk = "mcasp2_aux_gfclk_mux",
1411 .flags = HWMOD_OPT_CLKS_NEEDED, 1411 .flags = HWMOD_OPT_CLKS_NEEDED,
1412 .prcm = { 1412 .prcm = {
1413 .omap4 = { 1413 .omap4 = {
1414 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, 1414 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1415 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, 1415 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1416 .modulemode = MODULEMODE_SWCTRL, 1416 .modulemode = MODULEMODE_SWCTRL,
1417 }, 1417 },
1418 }, 1418 },
1419 .opt_clks = mcasp2_opt_clks, 1419 .opt_clks = mcasp2_opt_clks,
1420 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks), 1420 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1421 }; 1421 };
1422 1422
1423 /* mcasp3 */ 1423 /* mcasp3 */
1424 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = { 1424 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1425 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" }, 1425 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1426 }; 1426 };
1427 1427
1428 static struct omap_hwmod dra7xx_mcasp3_hwmod = { 1428 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1429 .name = "mcasp3", 1429 .name = "mcasp3",
1430 .class = &dra7xx_mcasp_hwmod_class, 1430 .class = &dra7xx_mcasp_hwmod_class,
1431 .clkdm_name = "l4per2_clkdm", 1431 .clkdm_name = "l4per2_clkdm",
1432 .main_clk = "mcasp3_aux_gfclk_mux", 1432 .main_clk = "mcasp3_aux_gfclk_mux",
1433 .flags = HWMOD_OPT_CLKS_NEEDED, 1433 .flags = HWMOD_OPT_CLKS_NEEDED,
1434 .prcm = { 1434 .prcm = {
1435 .omap4 = { 1435 .omap4 = {
1436 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET, 1436 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1437 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET, 1437 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1438 .modulemode = MODULEMODE_SWCTRL, 1438 .modulemode = MODULEMODE_SWCTRL,
1439 }, 1439 },
1440 }, 1440 },
1441 .opt_clks = mcasp3_opt_clks, 1441 .opt_clks = mcasp3_opt_clks,
1442 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks), 1442 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1443 }; 1443 };
1444 1444
1445 /* mcasp4 */ 1445 /* mcasp4 */
1446 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = { 1446 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1447 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" }, 1447 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1448 }; 1448 };
1449 1449
1450 static struct omap_hwmod dra7xx_mcasp4_hwmod = { 1450 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1451 .name = "mcasp4", 1451 .name = "mcasp4",
1452 .class = &dra7xx_mcasp_hwmod_class, 1452 .class = &dra7xx_mcasp_hwmod_class,
1453 .clkdm_name = "l4per2_clkdm", 1453 .clkdm_name = "l4per2_clkdm",
1454 .main_clk = "mcasp4_aux_gfclk_mux", 1454 .main_clk = "mcasp4_aux_gfclk_mux",
1455 .flags = HWMOD_OPT_CLKS_NEEDED, 1455 .flags = HWMOD_OPT_CLKS_NEEDED,
1456 .prcm = { 1456 .prcm = {
1457 .omap4 = { 1457 .omap4 = {
1458 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET, 1458 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1459 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET, 1459 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1460 .modulemode = MODULEMODE_SWCTRL, 1460 .modulemode = MODULEMODE_SWCTRL,
1461 }, 1461 },
1462 }, 1462 },
1463 .opt_clks = mcasp4_opt_clks, 1463 .opt_clks = mcasp4_opt_clks,
1464 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks), 1464 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1465 }; 1465 };
1466 1466
1467 /* mcasp5 */ 1467 /* mcasp5 */
1468 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = { 1468 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1469 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" }, 1469 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1470 }; 1470 };
1471 1471
1472 static struct omap_hwmod dra7xx_mcasp5_hwmod = { 1472 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1473 .name = "mcasp5", 1473 .name = "mcasp5",
1474 .class = &dra7xx_mcasp_hwmod_class, 1474 .class = &dra7xx_mcasp_hwmod_class,
1475 .clkdm_name = "l4per2_clkdm", 1475 .clkdm_name = "l4per2_clkdm",
1476 .main_clk = "mcasp5_aux_gfclk_mux", 1476 .main_clk = "mcasp5_aux_gfclk_mux",
1477 .flags = HWMOD_OPT_CLKS_NEEDED, 1477 .flags = HWMOD_OPT_CLKS_NEEDED,
1478 .prcm = { 1478 .prcm = {
1479 .omap4 = { 1479 .omap4 = {
1480 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET, 1480 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1481 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET, 1481 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1482 .modulemode = MODULEMODE_SWCTRL, 1482 .modulemode = MODULEMODE_SWCTRL,
1483 }, 1483 },
1484 }, 1484 },
1485 .opt_clks = mcasp5_opt_clks, 1485 .opt_clks = mcasp5_opt_clks,
1486 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks), 1486 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1487 }; 1487 };
1488 1488
1489 /* mcasp6 */ 1489 /* mcasp6 */
1490 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = { 1490 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1491 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" }, 1491 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1492 }; 1492 };
1493 1493
1494 static struct omap_hwmod dra7xx_mcasp6_hwmod = { 1494 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1495 .name = "mcasp6", 1495 .name = "mcasp6",
1496 .class = &dra7xx_mcasp_hwmod_class, 1496 .class = &dra7xx_mcasp_hwmod_class,
1497 .clkdm_name = "l4per2_clkdm", 1497 .clkdm_name = "l4per2_clkdm",
1498 .main_clk = "mcasp6_aux_gfclk_mux", 1498 .main_clk = "mcasp6_aux_gfclk_mux",
1499 .flags = HWMOD_OPT_CLKS_NEEDED, 1499 .flags = HWMOD_OPT_CLKS_NEEDED,
1500 .prcm = { 1500 .prcm = {
1501 .omap4 = { 1501 .omap4 = {
1502 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, 1502 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1503 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, 1503 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1504 .modulemode = MODULEMODE_SWCTRL, 1504 .modulemode = MODULEMODE_SWCTRL,
1505 }, 1505 },
1506 }, 1506 },
1507 .opt_clks = mcasp6_opt_clks, 1507 .opt_clks = mcasp6_opt_clks,
1508 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks), 1508 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1509 }; 1509 };
1510 1510
1511 /* mcasp7 */ 1511 /* mcasp7 */
1512 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = { 1512 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1513 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" }, 1513 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1514 }; 1514 };
1515 1515
1516 static struct omap_hwmod dra7xx_mcasp7_hwmod = { 1516 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1517 .name = "mcasp7", 1517 .name = "mcasp7",
1518 .class = &dra7xx_mcasp_hwmod_class, 1518 .class = &dra7xx_mcasp_hwmod_class,
1519 .clkdm_name = "l4per2_clkdm", 1519 .clkdm_name = "l4per2_clkdm",
1520 .main_clk = "mcasp7_aux_gfclk_mux", 1520 .main_clk = "mcasp7_aux_gfclk_mux",
1521 .flags = HWMOD_OPT_CLKS_NEEDED, 1521 .flags = HWMOD_OPT_CLKS_NEEDED,
1522 .prcm = { 1522 .prcm = {
1523 .omap4 = { 1523 .omap4 = {
1524 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET, 1524 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1525 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET, 1525 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1526 .modulemode = MODULEMODE_SWCTRL, 1526 .modulemode = MODULEMODE_SWCTRL,
1527 }, 1527 },
1528 }, 1528 },
1529 .opt_clks = mcasp7_opt_clks, 1529 .opt_clks = mcasp7_opt_clks,
1530 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks), 1530 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1531 }; 1531 };
1532 1532
1533 /* mcasp8 */ 1533 /* mcasp8 */
1534 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = { 1534 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1535 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" }, 1535 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1536 }; 1536 };
1537 1537
1538 static struct omap_hwmod dra7xx_mcasp8_hwmod = { 1538 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1539 .name = "mcasp8", 1539 .name = "mcasp8",
1540 .class = &dra7xx_mcasp_hwmod_class, 1540 .class = &dra7xx_mcasp_hwmod_class,
1541 .clkdm_name = "l4per2_clkdm", 1541 .clkdm_name = "l4per2_clkdm",
1542 .main_clk = "mcasp8_aux_gfclk_mux", 1542 .main_clk = "mcasp8_aux_gfclk_mux",
1543 .flags = HWMOD_OPT_CLKS_NEEDED, 1543 .flags = HWMOD_OPT_CLKS_NEEDED,
1544 .prcm = { 1544 .prcm = {
1545 .omap4 = { 1545 .omap4 = {
1546 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET, 1546 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1547 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET, 1547 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1548 .modulemode = MODULEMODE_SWCTRL, 1548 .modulemode = MODULEMODE_SWCTRL,
1549 }, 1549 },
1550 }, 1550 },
1551 .opt_clks = mcasp8_opt_clks, 1551 .opt_clks = mcasp8_opt_clks,
1552 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks), 1552 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1553 }; 1553 };
1554 1554
1555 /* 1555 /*
1556 * 'mmc' class 1556 * 'mmc' class
1557 * 1557 *
1558 */ 1558 */
1559 1559
1560 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = { 1560 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1561 .rev_offs = 0x0000, 1561 .rev_offs = 0x0000,
1562 .sysc_offs = 0x0010, 1562 .sysc_offs = 0x0010,
1563 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | 1563 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1564 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 1564 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1565 SYSC_HAS_SOFTRESET), 1565 SYSC_HAS_SOFTRESET),
1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1567 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 1567 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1568 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 1568 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1569 .sysc_fields = &omap_hwmod_sysc_type2, 1569 .sysc_fields = &omap_hwmod_sysc_type2,
1570 }; 1570 };
1571 1571
1572 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = { 1572 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1573 .name = "mmc", 1573 .name = "mmc",
1574 .sysc = &dra7xx_mmc_sysc, 1574 .sysc = &dra7xx_mmc_sysc,
1575 }; 1575 };
1576 1576
1577 /* mmc1 */ 1577 /* mmc1 */
1578 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { 1578 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1579 { .role = "clk32k", .clk = "mmc1_clk32k" }, 1579 { .role = "clk32k", .clk = "mmc1_clk32k" },
1580 }; 1580 };
1581 1581
1582 /* mmc1 dev_attr */ 1582 /* mmc1 dev_attr */
1583 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 1583 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1584 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1584 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1585 }; 1585 };
1586 1586
1587 static struct omap_hwmod dra7xx_mmc1_hwmod = { 1587 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1588 .name = "mmc1", 1588 .name = "mmc1",
1589 .class = &dra7xx_mmc_hwmod_class, 1589 .class = &dra7xx_mmc_hwmod_class,
1590 .clkdm_name = "l3init_clkdm", 1590 .clkdm_name = "l3init_clkdm",
1591 .main_clk = "mmc1_fclk_div", 1591 .main_clk = "mmc1_fclk_div",
1592 .prcm = { 1592 .prcm = {
1593 .omap4 = { 1593 .omap4 = {
1594 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, 1594 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1595 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, 1595 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1596 .modulemode = MODULEMODE_SWCTRL, 1596 .modulemode = MODULEMODE_SWCTRL,
1597 }, 1597 },
1598 }, 1598 },
1599 .opt_clks = mmc1_opt_clks, 1599 .opt_clks = mmc1_opt_clks,
1600 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), 1600 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1601 .dev_attr = &mmc1_dev_attr, 1601 .dev_attr = &mmc1_dev_attr,
1602 }; 1602 };
1603 1603
1604 /* mmc2 */ 1604 /* mmc2 */
1605 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = { 1605 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1606 { .role = "clk32k", .clk = "mmc2_clk32k" }, 1606 { .role = "clk32k", .clk = "mmc2_clk32k" },
1607 }; 1607 };
1608 1608
1609 static struct omap_hwmod dra7xx_mmc2_hwmod = { 1609 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1610 .name = "mmc2", 1610 .name = "mmc2",
1611 .class = &dra7xx_mmc_hwmod_class, 1611 .class = &dra7xx_mmc_hwmod_class,
1612 .clkdm_name = "l3init_clkdm", 1612 .clkdm_name = "l3init_clkdm",
1613 .main_clk = "mmc2_fclk_div", 1613 .main_clk = "mmc2_fclk_div",
1614 .prcm = { 1614 .prcm = {
1615 .omap4 = { 1615 .omap4 = {
1616 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, 1616 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1617 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, 1617 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1618 .modulemode = MODULEMODE_SWCTRL, 1618 .modulemode = MODULEMODE_SWCTRL,
1619 }, 1619 },
1620 }, 1620 },
1621 .opt_clks = mmc2_opt_clks, 1621 .opt_clks = mmc2_opt_clks,
1622 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks), 1622 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1623 }; 1623 };
1624 1624
1625 /* mmc3 */ 1625 /* mmc3 */
1626 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = { 1626 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1627 { .role = "clk32k", .clk = "mmc3_clk32k" }, 1627 { .role = "clk32k", .clk = "mmc3_clk32k" },
1628 }; 1628 };
1629 1629
1630 static struct omap_hwmod dra7xx_mmc3_hwmod = { 1630 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1631 .name = "mmc3", 1631 .name = "mmc3",
1632 .class = &dra7xx_mmc_hwmod_class, 1632 .class = &dra7xx_mmc_hwmod_class,
1633 .clkdm_name = "l4per_clkdm", 1633 .clkdm_name = "l4per_clkdm",
1634 .main_clk = "mmc3_gfclk_div", 1634 .main_clk = "mmc3_gfclk_div",
1635 .prcm = { 1635 .prcm = {
1636 .omap4 = { 1636 .omap4 = {
1637 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, 1637 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1638 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET, 1638 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1639 .modulemode = MODULEMODE_SWCTRL, 1639 .modulemode = MODULEMODE_SWCTRL,
1640 }, 1640 },
1641 }, 1641 },
1642 .opt_clks = mmc3_opt_clks, 1642 .opt_clks = mmc3_opt_clks,
1643 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks), 1643 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1644 }; 1644 };
1645 1645
1646 /* mmc4 */ 1646 /* mmc4 */
1647 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = { 1647 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1648 { .role = "clk32k", .clk = "mmc4_clk32k" }, 1648 { .role = "clk32k", .clk = "mmc4_clk32k" },
1649 }; 1649 };
1650 1650
1651 static struct omap_hwmod dra7xx_mmc4_hwmod = { 1651 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1652 .name = "mmc4", 1652 .name = "mmc4",
1653 .class = &dra7xx_mmc_hwmod_class, 1653 .class = &dra7xx_mmc_hwmod_class,
1654 .clkdm_name = "l4per_clkdm", 1654 .clkdm_name = "l4per_clkdm",
1655 .main_clk = "mmc4_gfclk_div", 1655 .main_clk = "mmc4_gfclk_div",
1656 .prcm = { 1656 .prcm = {
1657 .omap4 = { 1657 .omap4 = {
1658 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, 1658 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1659 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET, 1659 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL, 1660 .modulemode = MODULEMODE_SWCTRL,
1661 }, 1661 },
1662 }, 1662 },
1663 .opt_clks = mmc4_opt_clks, 1663 .opt_clks = mmc4_opt_clks,
1664 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks), 1664 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1665 }; 1665 };
1666 1666
1667 /* 1667 /*
1668 * 'mpu' class 1668 * 'mpu' class
1669 * 1669 *
1670 */ 1670 */
1671 1671
1672 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = { 1672 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1673 .name = "mpu", 1673 .name = "mpu",
1674 }; 1674 };
1675 1675
1676 /* mpu */ 1676 /* mpu */
1677 static struct omap_hwmod dra7xx_mpu_hwmod = { 1677 static struct omap_hwmod dra7xx_mpu_hwmod = {
1678 .name = "mpu", 1678 .name = "mpu",
1679 .class = &dra7xx_mpu_hwmod_class, 1679 .class = &dra7xx_mpu_hwmod_class,
1680 .clkdm_name = "mpu_clkdm", 1680 .clkdm_name = "mpu_clkdm",
1681 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 1681 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1682 .main_clk = "dpll_mpu_m2_ck", 1682 .main_clk = "dpll_mpu_m2_ck",
1683 .prcm = { 1683 .prcm = {
1684 .omap4 = { 1684 .omap4 = {
1685 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET, 1685 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1686 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET, 1686 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1687 }, 1687 },
1688 }, 1688 },
1689 }; 1689 };
1690 1690
1691 /* 1691 /*
1692 * 'ocp2scp' class 1692 * 'ocp2scp' class
1693 * 1693 *
1694 */ 1694 */
1695 1695
1696 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = { 1696 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1697 .rev_offs = 0x0000, 1697 .rev_offs = 0x0000,
1698 .sysc_offs = 0x0010, 1698 .sysc_offs = 0x0010,
1699 .syss_offs = 0x0014, 1699 .syss_offs = 0x0014,
1700 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 1700 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1701 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1701 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1702 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1702 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1703 .sysc_fields = &omap_hwmod_sysc_type1, 1703 .sysc_fields = &omap_hwmod_sysc_type1,
1704 }; 1704 };
1705 1705
1706 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = { 1706 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1707 .name = "ocp2scp", 1707 .name = "ocp2scp",
1708 .sysc = &dra7xx_ocp2scp_sysc, 1708 .sysc = &dra7xx_ocp2scp_sysc,
1709 }; 1709 };
1710 1710
1711 /* ocp2scp1 */ 1711 /* ocp2scp1 */
1712 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { 1712 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1713 .name = "ocp2scp1", 1713 .name = "ocp2scp1",
1714 .class = &dra7xx_ocp2scp_hwmod_class, 1714 .class = &dra7xx_ocp2scp_hwmod_class,
1715 .clkdm_name = "l3init_clkdm", 1715 .clkdm_name = "l3init_clkdm",
1716 .main_clk = "l4_root_clk_div", 1716 .main_clk = "l4_root_clk_div",
1717 .prcm = { 1717 .prcm = {
1718 .omap4 = { 1718 .omap4 = {
1719 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, 1719 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1720 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, 1720 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1721 .modulemode = MODULEMODE_HWCTRL, 1721 .modulemode = MODULEMODE_HWCTRL,
1722 }, 1722 },
1723 }, 1723 },
1724 }; 1724 };
1725 1725
1726 /* ocp2scp3 */ 1726 /* ocp2scp3 */
1727 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { 1727 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1728 .name = "ocp2scp3", 1728 .name = "ocp2scp3",
1729 .class = &dra7xx_ocp2scp_hwmod_class, 1729 .class = &dra7xx_ocp2scp_hwmod_class,
1730 .clkdm_name = "l3init_clkdm", 1730 .clkdm_name = "l3init_clkdm",
1731 .main_clk = "l4_root_clk_div", 1731 .main_clk = "l4_root_clk_div",
1732 .prcm = { 1732 .prcm = {
1733 .omap4 = { 1733 .omap4 = {
1734 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, 1734 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1735 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, 1735 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1736 .modulemode = MODULEMODE_HWCTRL, 1736 .modulemode = MODULEMODE_HWCTRL,
1737 }, 1737 },
1738 }, 1738 },
1739 }; 1739 };
1740 1740
1741 /* 1741 /*
1742 * 'PCIE' class 1742 * 'PCIE' class
1743 * 1743 *
1744 */ 1744 */
1745 1745
1746 /* 1746 /*
1747 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset 1747 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1748 * functionality of OMAP HWMOD layer does not deassert the hardreset lines 1748 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1749 * associated with an IP automatically leaving the driver to handle that 1749 * associated with an IP automatically leaving the driver to handle that
1750 * by itself. This does not work for PCIeSS which needs the reset lines 1750 * by itself. This does not work for PCIeSS which needs the reset lines
1751 * deasserted for the driver to start accessing registers. 1751 * deasserted for the driver to start accessing registers.
1752 * 1752 *
1753 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset 1753 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1754 * lines after asserting them. 1754 * lines after asserting them.
1755 */ 1755 */
1756 static int dra7xx_pciess_reset(struct omap_hwmod *oh) 1756 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1757 { 1757 {
1758 int i; 1758 int i;
1759 1759
1760 for (i = 0; i < oh->rst_lines_cnt; i++) { 1760 for (i = 0; i < oh->rst_lines_cnt; i++) {
1761 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name); 1761 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1762 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name); 1762 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1763 } 1763 }
1764 1764
1765 return 0; 1765 return 0;
1766 } 1766 }
1767 1767
1768 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { 1768 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1769 .name = "pcie", 1769 .name = "pcie",
1770 .reset = dra7xx_pciess_reset, 1770 .reset = dra7xx_pciess_reset,
1771 }; 1771 };
1772 1772
1773 /* pcie1 */ 1773 /* pcie1 */
1774 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = { 1774 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1775 { .name = "pcie", .rst_shift = 0 }, 1775 { .name = "pcie", .rst_shift = 0 },
1776 }; 1776 };
1777 1777
1778 static struct omap_hwmod dra7xx_pciess1_hwmod = { 1778 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1779 .name = "pcie1", 1779 .name = "pcie1",
1780 .class = &dra7xx_pciess_hwmod_class, 1780 .class = &dra7xx_pciess_hwmod_class,
1781 .clkdm_name = "pcie_clkdm", 1781 .clkdm_name = "pcie_clkdm",
1782 .rst_lines = dra7xx_pciess1_resets, 1782 .rst_lines = dra7xx_pciess1_resets,
1783 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets), 1783 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1784 .main_clk = "l4_root_clk_div", 1784 .main_clk = "l4_root_clk_div",
1785 .prcm = { 1785 .prcm = {
1786 .omap4 = { 1786 .omap4 = {
1787 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, 1787 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1788 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, 1788 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1789 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, 1789 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1790 .modulemode = MODULEMODE_SWCTRL, 1790 .modulemode = MODULEMODE_SWCTRL,
1791 }, 1791 },
1792 }, 1792 },
1793 }; 1793 };
1794 1794
1795 /* pcie2 */ 1795 /* pcie2 */
1796 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = { 1796 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1797 { .name = "pcie", .rst_shift = 1 }, 1797 { .name = "pcie", .rst_shift = 1 },
1798 }; 1798 };
1799 1799
1800 /* pcie2 */ 1800 /* pcie2 */
1801 static struct omap_hwmod dra7xx_pciess2_hwmod = { 1801 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1802 .name = "pcie2", 1802 .name = "pcie2",
1803 .class = &dra7xx_pciess_hwmod_class, 1803 .class = &dra7xx_pciess_hwmod_class,
1804 .clkdm_name = "pcie_clkdm", 1804 .clkdm_name = "pcie_clkdm",
1805 .rst_lines = dra7xx_pciess2_resets, 1805 .rst_lines = dra7xx_pciess2_resets,
1806 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets), 1806 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1807 .main_clk = "l4_root_clk_div", 1807 .main_clk = "l4_root_clk_div",
1808 .prcm = { 1808 .prcm = {
1809 .omap4 = { 1809 .omap4 = {
1810 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, 1810 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1811 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, 1811 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1812 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, 1812 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1813 .modulemode = MODULEMODE_SWCTRL, 1813 .modulemode = MODULEMODE_SWCTRL,
1814 }, 1814 },
1815 }, 1815 },
1816 }; 1816 };
1817 1817
1818 /* 1818 /*
1819 * 'qspi' class 1819 * 'qspi' class
1820 * 1820 *
1821 */ 1821 */
1822 1822
1823 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = { 1823 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1824 .sysc_offs = 0x0010, 1824 .sysc_offs = 0x0010,
1825 .sysc_flags = SYSC_HAS_SIDLEMODE, 1825 .sysc_flags = SYSC_HAS_SIDLEMODE,
1826 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1826 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1827 SIDLE_SMART_WKUP), 1827 SIDLE_SMART_WKUP),
1828 .sysc_fields = &omap_hwmod_sysc_type2, 1828 .sysc_fields = &omap_hwmod_sysc_type2,
1829 }; 1829 };
1830 1830
1831 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = { 1831 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1832 .name = "qspi", 1832 .name = "qspi",
1833 .sysc = &dra7xx_qspi_sysc, 1833 .sysc = &dra7xx_qspi_sysc,
1834 }; 1834 };
1835 1835
1836 /* qspi */ 1836 /* qspi */
1837 static struct omap_hwmod dra7xx_qspi_hwmod = { 1837 static struct omap_hwmod dra7xx_qspi_hwmod = {
1838 .name = "qspi", 1838 .name = "qspi",
1839 .class = &dra7xx_qspi_hwmod_class, 1839 .class = &dra7xx_qspi_hwmod_class,
1840 .clkdm_name = "l4per2_clkdm", 1840 .clkdm_name = "l4per2_clkdm",
1841 .main_clk = "qspi_gfclk_div", 1841 .main_clk = "qspi_gfclk_div",
1842 .prcm = { 1842 .prcm = {
1843 .omap4 = { 1843 .omap4 = {
1844 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET, 1844 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1845 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET, 1845 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1846 .modulemode = MODULEMODE_SWCTRL, 1846 .modulemode = MODULEMODE_SWCTRL,
1847 }, 1847 },
1848 }, 1848 },
1849 }; 1849 };
1850 1850
1851 /* 1851 /*
1852 * 'rtcss' class 1852 * 'rtcss' class
1853 * 1853 *
1854 */ 1854 */
1855 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { 1855 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1856 .sysc_offs = 0x0078, 1856 .sysc_offs = 0x0078,
1857 .sysc_flags = SYSC_HAS_SIDLEMODE, 1857 .sysc_flags = SYSC_HAS_SIDLEMODE,
1858 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1858 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1859 SIDLE_SMART_WKUP), 1859 SIDLE_SMART_WKUP),
1860 .sysc_fields = &omap_hwmod_sysc_type3, 1860 .sysc_fields = &omap_hwmod_sysc_type3,
1861 }; 1861 };
1862 1862
1863 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { 1863 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1864 .name = "rtcss", 1864 .name = "rtcss",
1865 .sysc = &dra7xx_rtcss_sysc, 1865 .sysc = &dra7xx_rtcss_sysc,
1866 .unlock = &omap_hwmod_rtc_unlock, 1866 .unlock = &omap_hwmod_rtc_unlock,
1867 .lock = &omap_hwmod_rtc_lock, 1867 .lock = &omap_hwmod_rtc_lock,
1868 }; 1868 };
1869 1869
1870 /* rtcss */ 1870 /* rtcss */
1871 static struct omap_hwmod dra7xx_rtcss_hwmod = { 1871 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1872 .name = "rtcss", 1872 .name = "rtcss",
1873 .class = &dra7xx_rtcss_hwmod_class, 1873 .class = &dra7xx_rtcss_hwmod_class,
1874 .clkdm_name = "rtc_clkdm", 1874 .clkdm_name = "rtc_clkdm",
1875 .main_clk = "sys_32k_ck", 1875 .main_clk = "sys_32k_ck",
1876 .prcm = { 1876 .prcm = {
1877 .omap4 = { 1877 .omap4 = {
1878 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET, 1878 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1879 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET, 1879 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL, 1880 .modulemode = MODULEMODE_SWCTRL,
1881 }, 1881 },
1882 }, 1882 },
1883 }; 1883 };
1884 1884
1885 /* 1885 /*
1886 * 'sata' class 1886 * 'sata' class
1887 * 1887 *
1888 */ 1888 */
1889 1889
1890 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = { 1890 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1891 .sysc_offs = 0x0000, 1891 .sysc_offs = 0x0000,
1892 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), 1892 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1893 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1893 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1894 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 1894 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1895 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 1895 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1896 .sysc_fields = &omap_hwmod_sysc_type2, 1896 .sysc_fields = &omap_hwmod_sysc_type2,
1897 }; 1897 };
1898 1898
1899 static struct omap_hwmod_class dra7xx_sata_hwmod_class = { 1899 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1900 .name = "sata", 1900 .name = "sata",
1901 .sysc = &dra7xx_sata_sysc, 1901 .sysc = &dra7xx_sata_sysc,
1902 }; 1902 };
1903 1903
1904 /* sata */ 1904 /* sata */
1905 1905
1906 static struct omap_hwmod dra7xx_sata_hwmod = { 1906 static struct omap_hwmod dra7xx_sata_hwmod = {
1907 .name = "sata", 1907 .name = "sata",
1908 .class = &dra7xx_sata_hwmod_class, 1908 .class = &dra7xx_sata_hwmod_class,
1909 .clkdm_name = "l3init_clkdm", 1909 .clkdm_name = "l3init_clkdm",
1910 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1910 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1911 .main_clk = "func_48m_fclk", 1911 .main_clk = "func_48m_fclk",
1912 .mpu_rt_idx = 1, 1912 .mpu_rt_idx = 1,
1913 .prcm = { 1913 .prcm = {
1914 .omap4 = { 1914 .omap4 = {
1915 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, 1915 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1916 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET, 1916 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1917 .modulemode = MODULEMODE_SWCTRL, 1917 .modulemode = MODULEMODE_SWCTRL,
1918 }, 1918 },
1919 }, 1919 },
1920 }; 1920 };
1921 1921
1922 /* 1922 /*
1923 * 'smartreflex' class 1923 * 'smartreflex' class
1924 * 1924 *
1925 */ 1925 */
1926 1926
1927 /* The IP is not compliant to type1 / type2 scheme */ 1927 /* The IP is not compliant to type1 / type2 scheme */
1928 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { 1928 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1929 .sidle_shift = 24, 1929 .sidle_shift = 24,
1930 .enwkup_shift = 26, 1930 .enwkup_shift = 26,
1931 }; 1931 };
1932 1932
1933 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = { 1933 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1934 .sysc_offs = 0x0038, 1934 .sysc_offs = 0x0038,
1935 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), 1935 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937 SIDLE_SMART_WKUP), 1937 SIDLE_SMART_WKUP),
1938 .sysc_fields = &omap_hwmod_sysc_type_smartreflex, 1938 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1939 }; 1939 };
1940 1940
1941 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = { 1941 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1942 .name = "smartreflex", 1942 .name = "smartreflex",
1943 .sysc = &dra7xx_smartreflex_sysc, 1943 .sysc = &dra7xx_smartreflex_sysc,
1944 .rev = 2, 1944 .rev = 2,
1945 }; 1945 };
1946 1946
1947 /* smartreflex_core */ 1947 /* smartreflex_core */
1948 /* smartreflex_core dev_attr */ 1948 /* smartreflex_core dev_attr */
1949 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { 1949 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1950 .sensor_voltdm_name = "core", 1950 .sensor_voltdm_name = "core",
1951 }; 1951 };
1952 1952
1953 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = { 1953 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1954 .name = "smartreflex_core", 1954 .name = "smartreflex_core",
1955 .class = &dra7xx_smartreflex_hwmod_class, 1955 .class = &dra7xx_smartreflex_hwmod_class,
1956 .clkdm_name = "coreaon_clkdm", 1956 .clkdm_name = "coreaon_clkdm",
1957 .main_clk = "wkupaon_iclk_mux", 1957 .main_clk = "wkupaon_iclk_mux",
1958 .prcm = { 1958 .prcm = {
1959 .omap4 = { 1959 .omap4 = {
1960 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET, 1960 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1961 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET, 1961 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1962 .modulemode = MODULEMODE_SWCTRL, 1962 .modulemode = MODULEMODE_SWCTRL,
1963 }, 1963 },
1964 }, 1964 },
1965 .dev_attr = &smartreflex_core_dev_attr, 1965 .dev_attr = &smartreflex_core_dev_attr,
1966 }; 1966 };
1967 1967
1968 /* smartreflex_mpu */ 1968 /* smartreflex_mpu */
1969 /* smartreflex_mpu dev_attr */ 1969 /* smartreflex_mpu dev_attr */
1970 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { 1970 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1971 .sensor_voltdm_name = "mpu", 1971 .sensor_voltdm_name = "mpu",
1972 }; 1972 };
1973 1973
1974 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = { 1974 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1975 .name = "smartreflex_mpu", 1975 .name = "smartreflex_mpu",
1976 .class = &dra7xx_smartreflex_hwmod_class, 1976 .class = &dra7xx_smartreflex_hwmod_class,
1977 .clkdm_name = "coreaon_clkdm", 1977 .clkdm_name = "coreaon_clkdm",
1978 .main_clk = "wkupaon_iclk_mux", 1978 .main_clk = "wkupaon_iclk_mux",
1979 .prcm = { 1979 .prcm = {
1980 .omap4 = { 1980 .omap4 = {
1981 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET, 1981 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1982 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET, 1982 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1983 .modulemode = MODULEMODE_SWCTRL, 1983 .modulemode = MODULEMODE_SWCTRL,
1984 }, 1984 },
1985 }, 1985 },
1986 .dev_attr = &smartreflex_mpu_dev_attr, 1986 .dev_attr = &smartreflex_mpu_dev_attr,
1987 }; 1987 };
1988 1988
1989 /* 1989 /*
1990 * 'spinlock' class 1990 * 'spinlock' class
1991 * 1991 *
1992 */ 1992 */
1993 1993
1994 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = { 1994 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1995 .rev_offs = 0x0000, 1995 .rev_offs = 0x0000,
1996 .sysc_offs = 0x0010, 1996 .sysc_offs = 0x0010,
1997 .syss_offs = 0x0014, 1997 .syss_offs = 0x0014,
1998 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 1998 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1999 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1999 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2000 SYSS_HAS_RESET_STATUS), 2000 SYSS_HAS_RESET_STATUS),
2001 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2001 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2002 .sysc_fields = &omap_hwmod_sysc_type1, 2002 .sysc_fields = &omap_hwmod_sysc_type1,
2003 }; 2003 };
2004 2004
2005 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = { 2005 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2006 .name = "spinlock", 2006 .name = "spinlock",
2007 .sysc = &dra7xx_spinlock_sysc, 2007 .sysc = &dra7xx_spinlock_sysc,
2008 }; 2008 };
2009 2009
2010 /* spinlock */ 2010 /* spinlock */
2011 static struct omap_hwmod dra7xx_spinlock_hwmod = { 2011 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2012 .name = "spinlock", 2012 .name = "spinlock",
2013 .class = &dra7xx_spinlock_hwmod_class, 2013 .class = &dra7xx_spinlock_hwmod_class,
2014 .clkdm_name = "l4cfg_clkdm", 2014 .clkdm_name = "l4cfg_clkdm",
2015 .main_clk = "l3_iclk_div", 2015 .main_clk = "l3_iclk_div",
2016 .prcm = { 2016 .prcm = {
2017 .omap4 = { 2017 .omap4 = {
2018 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, 2018 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2019 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, 2019 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2020 }, 2020 },
2021 }, 2021 },
2022 }; 2022 };
2023 2023
2024 /* 2024 /*
2025 * 'timer' class 2025 * 'timer' class
2026 * 2026 *
2027 * This class contains several variants: ['timer_1ms', 'timer_secure', 2027 * This class contains several variants: ['timer_1ms', 'timer_secure',
2028 * 'timer'] 2028 * 'timer']
2029 */ 2029 */
2030 2030
2031 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = { 2031 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2032 .rev_offs = 0x0000, 2032 .rev_offs = 0x0000,
2033 .sysc_offs = 0x0010, 2033 .sysc_offs = 0x0010,
2034 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 2034 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2035 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2035 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2036 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2036 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2037 SIDLE_SMART_WKUP), 2037 SIDLE_SMART_WKUP),
2038 .sysc_fields = &omap_hwmod_sysc_type2, 2038 .sysc_fields = &omap_hwmod_sysc_type2,
2039 }; 2039 };
2040 2040
2041 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = { 2041 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2042 .name = "timer", 2042 .name = "timer",
2043 .sysc = &dra7xx_timer_1ms_sysc, 2043 .sysc = &dra7xx_timer_1ms_sysc,
2044 }; 2044 };
2045 2045
2046 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = { 2046 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2047 .rev_offs = 0x0000, 2047 .rev_offs = 0x0000,
2048 .sysc_offs = 0x0010, 2048 .sysc_offs = 0x0010,
2049 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 2049 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2050 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2050 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2051 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2051 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2052 SIDLE_SMART_WKUP), 2052 SIDLE_SMART_WKUP),
2053 .sysc_fields = &omap_hwmod_sysc_type2, 2053 .sysc_fields = &omap_hwmod_sysc_type2,
2054 }; 2054 };
2055 2055
2056 static struct omap_hwmod_class dra7xx_timer_hwmod_class = { 2056 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2057 .name = "timer", 2057 .name = "timer",
2058 .sysc = &dra7xx_timer_sysc, 2058 .sysc = &dra7xx_timer_sysc,
2059 }; 2059 };
2060 2060
2061 /* timer1 */ 2061 /* timer1 */
2062 static struct omap_hwmod dra7xx_timer1_hwmod = { 2062 static struct omap_hwmod dra7xx_timer1_hwmod = {
2063 .name = "timer1", 2063 .name = "timer1",
2064 .class = &dra7xx_timer_1ms_hwmod_class, 2064 .class = &dra7xx_timer_1ms_hwmod_class,
2065 .clkdm_name = "wkupaon_clkdm", 2065 .clkdm_name = "wkupaon_clkdm",
2066 .main_clk = "timer1_gfclk_mux", 2066 .main_clk = "timer1_gfclk_mux",
2067 .prcm = { 2067 .prcm = {
2068 .omap4 = { 2068 .omap4 = {
2069 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, 2069 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2070 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, 2070 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2071 .modulemode = MODULEMODE_SWCTRL, 2071 .modulemode = MODULEMODE_SWCTRL,
2072 }, 2072 },
2073 }, 2073 },
2074 }; 2074 };
2075 2075
2076 /* timer2 */ 2076 /* timer2 */
2077 static struct omap_hwmod dra7xx_timer2_hwmod = { 2077 static struct omap_hwmod dra7xx_timer2_hwmod = {
2078 .name = "timer2", 2078 .name = "timer2",
2079 .class = &dra7xx_timer_1ms_hwmod_class, 2079 .class = &dra7xx_timer_1ms_hwmod_class,
2080 .clkdm_name = "l4per_clkdm", 2080 .clkdm_name = "l4per_clkdm",
2081 .main_clk = "timer2_gfclk_mux", 2081 .main_clk = "timer2_gfclk_mux",
2082 .prcm = { 2082 .prcm = {
2083 .omap4 = { 2083 .omap4 = {
2084 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, 2084 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2085 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, 2085 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2086 .modulemode = MODULEMODE_SWCTRL, 2086 .modulemode = MODULEMODE_SWCTRL,
2087 }, 2087 },
2088 }, 2088 },
2089 }; 2089 };
2090 2090
2091 /* timer3 */ 2091 /* timer3 */
2092 static struct omap_hwmod dra7xx_timer3_hwmod = { 2092 static struct omap_hwmod dra7xx_timer3_hwmod = {
2093 .name = "timer3", 2093 .name = "timer3",
2094 .class = &dra7xx_timer_hwmod_class, 2094 .class = &dra7xx_timer_hwmod_class,
2095 .clkdm_name = "l4per_clkdm", 2095 .clkdm_name = "l4per_clkdm",
2096 .main_clk = "timer3_gfclk_mux", 2096 .main_clk = "timer3_gfclk_mux",
2097 .prcm = { 2097 .prcm = {
2098 .omap4 = { 2098 .omap4 = {
2099 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, 2099 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2100 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, 2100 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2101 .modulemode = MODULEMODE_SWCTRL, 2101 .modulemode = MODULEMODE_SWCTRL,
2102 }, 2102 },
2103 }, 2103 },
2104 }; 2104 };
2105 2105
2106 /* timer4 */ 2106 /* timer4 */
2107 static struct omap_hwmod dra7xx_timer4_hwmod = { 2107 static struct omap_hwmod dra7xx_timer4_hwmod = {
2108 .name = "timer4", 2108 .name = "timer4",
2109 .class = &dra7xx_timer_hwmod_class, 2109 .class = &dra7xx_timer_hwmod_class,
2110 .clkdm_name = "l4per_clkdm", 2110 .clkdm_name = "l4per_clkdm",
2111 .main_clk = "timer4_gfclk_mux", 2111 .main_clk = "timer4_gfclk_mux",
2112 .prcm = { 2112 .prcm = {
2113 .omap4 = { 2113 .omap4 = {
2114 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, 2114 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2115 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, 2115 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2116 .modulemode = MODULEMODE_SWCTRL, 2116 .modulemode = MODULEMODE_SWCTRL,
2117 }, 2117 },
2118 }, 2118 },
2119 }; 2119 };
2120 2120
2121 /* timer5 */ 2121 /* timer5 */
2122 static struct omap_hwmod dra7xx_timer5_hwmod = { 2122 static struct omap_hwmod dra7xx_timer5_hwmod = {
2123 .name = "timer5", 2123 .name = "timer5",
2124 .class = &dra7xx_timer_hwmod_class, 2124 .class = &dra7xx_timer_hwmod_class,
2125 .clkdm_name = "ipu_clkdm", 2125 .clkdm_name = "ipu_clkdm",
2126 .main_clk = "timer5_gfclk_mux", 2126 .main_clk = "timer5_gfclk_mux",
2127 .prcm = { 2127 .prcm = {
2128 .omap4 = { 2128 .omap4 = {
2129 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET, 2129 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2130 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET, 2130 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2131 .modulemode = MODULEMODE_SWCTRL, 2131 .modulemode = MODULEMODE_SWCTRL,
2132 }, 2132 },
2133 }, 2133 },
2134 }; 2134 };
2135 2135
2136 /* timer6 */ 2136 /* timer6 */
2137 static struct omap_hwmod dra7xx_timer6_hwmod = { 2137 static struct omap_hwmod dra7xx_timer6_hwmod = {
2138 .name = "timer6", 2138 .name = "timer6",
2139 .class = &dra7xx_timer_hwmod_class, 2139 .class = &dra7xx_timer_hwmod_class,
2140 .clkdm_name = "ipu_clkdm", 2140 .clkdm_name = "ipu_clkdm",
2141 .main_clk = "timer6_gfclk_mux", 2141 .main_clk = "timer6_gfclk_mux",
2142 .prcm = { 2142 .prcm = {
2143 .omap4 = { 2143 .omap4 = {
2144 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET, 2144 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2145 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET, 2145 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2146 .modulemode = MODULEMODE_SWCTRL, 2146 .modulemode = MODULEMODE_SWCTRL,
2147 }, 2147 },
2148 }, 2148 },
2149 }; 2149 };
2150 2150
2151 /* timer7 */ 2151 /* timer7 */
2152 static struct omap_hwmod dra7xx_timer7_hwmod = { 2152 static struct omap_hwmod dra7xx_timer7_hwmod = {
2153 .name = "timer7", 2153 .name = "timer7",
2154 .class = &dra7xx_timer_hwmod_class, 2154 .class = &dra7xx_timer_hwmod_class,
2155 .clkdm_name = "ipu_clkdm", 2155 .clkdm_name = "ipu_clkdm",
2156 .main_clk = "timer7_gfclk_mux", 2156 .main_clk = "timer7_gfclk_mux",
2157 .prcm = { 2157 .prcm = {
2158 .omap4 = { 2158 .omap4 = {
2159 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET, 2159 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2160 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET, 2160 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2161 .modulemode = MODULEMODE_SWCTRL, 2161 .modulemode = MODULEMODE_SWCTRL,
2162 }, 2162 },
2163 }, 2163 },
2164 }; 2164 };
2165 2165
2166 /* timer8 */ 2166 /* timer8 */
2167 static struct omap_hwmod dra7xx_timer8_hwmod = { 2167 static struct omap_hwmod dra7xx_timer8_hwmod = {
2168 .name = "timer8", 2168 .name = "timer8",
2169 .class = &dra7xx_timer_hwmod_class, 2169 .class = &dra7xx_timer_hwmod_class,
2170 .clkdm_name = "ipu_clkdm", 2170 .clkdm_name = "ipu_clkdm",
2171 .main_clk = "timer8_gfclk_mux", 2171 .main_clk = "timer8_gfclk_mux",
2172 .prcm = { 2172 .prcm = {
2173 .omap4 = { 2173 .omap4 = {
2174 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET, 2174 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2175 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET, 2175 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2176 .modulemode = MODULEMODE_SWCTRL, 2176 .modulemode = MODULEMODE_SWCTRL,
2177 }, 2177 },
2178 }, 2178 },
2179 }; 2179 };
2180 2180
2181 /* timer9 */ 2181 /* timer9 */
2182 static struct omap_hwmod dra7xx_timer9_hwmod = { 2182 static struct omap_hwmod dra7xx_timer9_hwmod = {
2183 .name = "timer9", 2183 .name = "timer9",
2184 .class = &dra7xx_timer_hwmod_class, 2184 .class = &dra7xx_timer_hwmod_class,
2185 .clkdm_name = "l4per_clkdm", 2185 .clkdm_name = "l4per_clkdm",
2186 .main_clk = "timer9_gfclk_mux", 2186 .main_clk = "timer9_gfclk_mux",
2187 .prcm = { 2187 .prcm = {
2188 .omap4 = { 2188 .omap4 = {
2189 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, 2189 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2190 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, 2190 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2191 .modulemode = MODULEMODE_SWCTRL, 2191 .modulemode = MODULEMODE_SWCTRL,
2192 }, 2192 },
2193 }, 2193 },
2194 }; 2194 };
2195 2195
2196 /* timer10 */ 2196 /* timer10 */
2197 static struct omap_hwmod dra7xx_timer10_hwmod = { 2197 static struct omap_hwmod dra7xx_timer10_hwmod = {
2198 .name = "timer10", 2198 .name = "timer10",
2199 .class = &dra7xx_timer_1ms_hwmod_class, 2199 .class = &dra7xx_timer_1ms_hwmod_class,
2200 .clkdm_name = "l4per_clkdm", 2200 .clkdm_name = "l4per_clkdm",
2201 .main_clk = "timer10_gfclk_mux", 2201 .main_clk = "timer10_gfclk_mux",
2202 .prcm = { 2202 .prcm = {
2203 .omap4 = { 2203 .omap4 = {
2204 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, 2204 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2205 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, 2205 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2206 .modulemode = MODULEMODE_SWCTRL, 2206 .modulemode = MODULEMODE_SWCTRL,
2207 }, 2207 },
2208 }, 2208 },
2209 }; 2209 };
2210 2210
2211 /* timer11 */ 2211 /* timer11 */
2212 static struct omap_hwmod dra7xx_timer11_hwmod = { 2212 static struct omap_hwmod dra7xx_timer11_hwmod = {
2213 .name = "timer11", 2213 .name = "timer11",
2214 .class = &dra7xx_timer_hwmod_class, 2214 .class = &dra7xx_timer_hwmod_class,
2215 .clkdm_name = "l4per_clkdm", 2215 .clkdm_name = "l4per_clkdm",
2216 .main_clk = "timer11_gfclk_mux", 2216 .main_clk = "timer11_gfclk_mux",
2217 .prcm = { 2217 .prcm = {
2218 .omap4 = { 2218 .omap4 = {
2219 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, 2219 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2220 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, 2220 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2221 .modulemode = MODULEMODE_SWCTRL, 2221 .modulemode = MODULEMODE_SWCTRL,
2222 }, 2222 },
2223 }, 2223 },
2224 }; 2224 };
2225 2225
2226 /* timer12 */ 2226 /* timer12 */
2227 static struct omap_hwmod dra7xx_timer12_hwmod = { 2227 static struct omap_hwmod dra7xx_timer12_hwmod = {
2228 .name = "timer12", 2228 .name = "timer12",
2229 .class = &dra7xx_timer_hwmod_class, 2229 .class = &dra7xx_timer_hwmod_class,
2230 .clkdm_name = "wkupaon_clkdm", 2230 .clkdm_name = "wkupaon_clkdm",
2231 .main_clk = "secure_32k_clk_src_ck", 2231 .main_clk = "secure_32k_clk_src_ck",
2232 .prcm = { 2232 .prcm = {
2233 .omap4 = { 2233 .omap4 = {
2234 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, 2234 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2235 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, 2235 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2236 }, 2236 },
2237 }, 2237 },
2238 }; 2238 };
2239 2239
2240 /* timer13 */ 2240 /* timer13 */
2241 static struct omap_hwmod dra7xx_timer13_hwmod = { 2241 static struct omap_hwmod dra7xx_timer13_hwmod = {
2242 .name = "timer13", 2242 .name = "timer13",
2243 .class = &dra7xx_timer_hwmod_class, 2243 .class = &dra7xx_timer_hwmod_class,
2244 .clkdm_name = "l4per3_clkdm", 2244 .clkdm_name = "l4per3_clkdm",
2245 .main_clk = "timer13_gfclk_mux", 2245 .main_clk = "timer13_gfclk_mux",
2246 .prcm = { 2246 .prcm = {
2247 .omap4 = { 2247 .omap4 = {
2248 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET, 2248 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2249 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET, 2249 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2250 .modulemode = MODULEMODE_SWCTRL, 2250 .modulemode = MODULEMODE_SWCTRL,
2251 }, 2251 },
2252 }, 2252 },
2253 }; 2253 };
2254 2254
2255 /* timer14 */ 2255 /* timer14 */
2256 static struct omap_hwmod dra7xx_timer14_hwmod = { 2256 static struct omap_hwmod dra7xx_timer14_hwmod = {
2257 .name = "timer14", 2257 .name = "timer14",
2258 .class = &dra7xx_timer_hwmod_class, 2258 .class = &dra7xx_timer_hwmod_class,
2259 .clkdm_name = "l4per3_clkdm", 2259 .clkdm_name = "l4per3_clkdm",
2260 .main_clk = "timer14_gfclk_mux", 2260 .main_clk = "timer14_gfclk_mux",
2261 .prcm = { 2261 .prcm = {
2262 .omap4 = { 2262 .omap4 = {
2263 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET, 2263 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2264 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET, 2264 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2265 .modulemode = MODULEMODE_SWCTRL, 2265 .modulemode = MODULEMODE_SWCTRL,
2266 }, 2266 },
2267 }, 2267 },
2268 }; 2268 };
2269 2269
2270 /* timer15 */ 2270 /* timer15 */
2271 static struct omap_hwmod dra7xx_timer15_hwmod = { 2271 static struct omap_hwmod dra7xx_timer15_hwmod = {
2272 .name = "timer15", 2272 .name = "timer15",
2273 .class = &dra7xx_timer_hwmod_class, 2273 .class = &dra7xx_timer_hwmod_class,
2274 .clkdm_name = "l4per3_clkdm", 2274 .clkdm_name = "l4per3_clkdm",
2275 .main_clk = "timer15_gfclk_mux", 2275 .main_clk = "timer15_gfclk_mux",
2276 .prcm = { 2276 .prcm = {
2277 .omap4 = { 2277 .omap4 = {
2278 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET, 2278 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2279 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET, 2279 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2280 .modulemode = MODULEMODE_SWCTRL, 2280 .modulemode = MODULEMODE_SWCTRL,
2281 }, 2281 },
2282 }, 2282 },
2283 }; 2283 };
2284 2284
2285 /* timer16 */ 2285 /* timer16 */
2286 static struct omap_hwmod dra7xx_timer16_hwmod = { 2286 static struct omap_hwmod dra7xx_timer16_hwmod = {
2287 .name = "timer16", 2287 .name = "timer16",
2288 .class = &dra7xx_timer_hwmod_class, 2288 .class = &dra7xx_timer_hwmod_class,
2289 .clkdm_name = "l4per3_clkdm", 2289 .clkdm_name = "l4per3_clkdm",
2290 .main_clk = "timer16_gfclk_mux", 2290 .main_clk = "timer16_gfclk_mux",
2291 .prcm = { 2291 .prcm = {
2292 .omap4 = { 2292 .omap4 = {
2293 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET, 2293 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2294 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET, 2294 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2295 .modulemode = MODULEMODE_SWCTRL, 2295 .modulemode = MODULEMODE_SWCTRL,
2296 }, 2296 },
2297 }, 2297 },
2298 }; 2298 };
2299 2299
2300 /* 2300 /*
2301 * 'uart' class 2301 * 'uart' class
2302 * 2302 *
2303 */ 2303 */
2304 2304
2305 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = { 2305 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2306 .rev_offs = 0x0050, 2306 .rev_offs = 0x0050,
2307 .sysc_offs = 0x0054, 2307 .sysc_offs = 0x0054,
2308 .syss_offs = 0x0058, 2308 .syss_offs = 0x0058,
2309 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 2309 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2311 SYSS_HAS_RESET_STATUS), 2311 SYSS_HAS_RESET_STATUS),
2312 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2312 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2313 SIDLE_SMART_WKUP), 2313 SIDLE_SMART_WKUP),
2314 .sysc_fields = &omap_hwmod_sysc_type1, 2314 .sysc_fields = &omap_hwmod_sysc_type1,
2315 }; 2315 };
2316 2316
2317 static struct omap_hwmod_class dra7xx_uart_hwmod_class = { 2317 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2318 .name = "uart", 2318 .name = "uart",
2319 .sysc = &dra7xx_uart_sysc, 2319 .sysc = &dra7xx_uart_sysc,
2320 }; 2320 };
2321 2321
2322 /* uart1 */ 2322 /* uart1 */
2323 static struct omap_hwmod dra7xx_uart1_hwmod = { 2323 static struct omap_hwmod dra7xx_uart1_hwmod = {
2324 .name = "uart1", 2324 .name = "uart1",
2325 .class = &dra7xx_uart_hwmod_class, 2325 .class = &dra7xx_uart_hwmod_class,
2326 .clkdm_name = "l4per_clkdm", 2326 .clkdm_name = "l4per_clkdm",
2327 .main_clk = "uart1_gfclk_mux", 2327 .main_clk = "uart1_gfclk_mux",
2328 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS, 2328 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2329 .prcm = { 2329 .prcm = {
2330 .omap4 = { 2330 .omap4 = {
2331 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET, 2331 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2332 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET, 2332 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2333 .modulemode = MODULEMODE_SWCTRL, 2333 .modulemode = MODULEMODE_SWCTRL,
2334 }, 2334 },
2335 }, 2335 },
2336 }; 2336 };
2337 2337
2338 /* uart2 */ 2338 /* uart2 */
2339 static struct omap_hwmod dra7xx_uart2_hwmod = { 2339 static struct omap_hwmod dra7xx_uart2_hwmod = {
2340 .name = "uart2", 2340 .name = "uart2",
2341 .class = &dra7xx_uart_hwmod_class, 2341 .class = &dra7xx_uart_hwmod_class,
2342 .clkdm_name = "l4per_clkdm", 2342 .clkdm_name = "l4per_clkdm",
2343 .main_clk = "uart2_gfclk_mux", 2343 .main_clk = "uart2_gfclk_mux",
2344 .flags = HWMOD_SWSUP_SIDLE_ACT, 2344 .flags = HWMOD_SWSUP_SIDLE_ACT,
2345 .prcm = { 2345 .prcm = {
2346 .omap4 = { 2346 .omap4 = {
2347 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET, 2347 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2348 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET, 2348 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2349 .modulemode = MODULEMODE_SWCTRL, 2349 .modulemode = MODULEMODE_SWCTRL,
2350 }, 2350 },
2351 }, 2351 },
2352 }; 2352 };
2353 2353
2354 /* uart3 */ 2354 /* uart3 */
2355 static struct omap_hwmod dra7xx_uart3_hwmod = { 2355 static struct omap_hwmod dra7xx_uart3_hwmod = {
2356 .name = "uart3", 2356 .name = "uart3",
2357 .class = &dra7xx_uart_hwmod_class, 2357 .class = &dra7xx_uart_hwmod_class,
2358 .clkdm_name = "l4per_clkdm", 2358 .clkdm_name = "l4per_clkdm",
2359 .main_clk = "uart3_gfclk_mux", 2359 .main_clk = "uart3_gfclk_mux",
2360 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS, 2360 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2361 .prcm = { 2361 .prcm = {
2362 .omap4 = { 2362 .omap4 = {
2363 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET, 2363 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2364 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET, 2364 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2365 .modulemode = MODULEMODE_SWCTRL, 2365 .modulemode = MODULEMODE_SWCTRL,
2366 }, 2366 },
2367 }, 2367 },
2368 }; 2368 };
2369 2369
2370 /* uart4 */ 2370 /* uart4 */
2371 static struct omap_hwmod dra7xx_uart4_hwmod = { 2371 static struct omap_hwmod dra7xx_uart4_hwmod = {
2372 .name = "uart4", 2372 .name = "uart4",
2373 .class = &dra7xx_uart_hwmod_class, 2373 .class = &dra7xx_uart_hwmod_class,
2374 .clkdm_name = "l4per_clkdm", 2374 .clkdm_name = "l4per_clkdm",
2375 .main_clk = "uart4_gfclk_mux", 2375 .main_clk = "uart4_gfclk_mux",
2376 .flags = HWMOD_SWSUP_SIDLE_ACT, 2376 .flags = HWMOD_SWSUP_SIDLE_ACT,
2377 .prcm = { 2377 .prcm = {
2378 .omap4 = { 2378 .omap4 = {
2379 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET, 2379 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2380 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET, 2380 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2381 .modulemode = MODULEMODE_SWCTRL, 2381 .modulemode = MODULEMODE_SWCTRL,
2382 }, 2382 },
2383 }, 2383 },
2384 }; 2384 };
2385 2385
2386 /* uart5 */ 2386 /* uart5 */
2387 static struct omap_hwmod dra7xx_uart5_hwmod = { 2387 static struct omap_hwmod dra7xx_uart5_hwmod = {
2388 .name = "uart5", 2388 .name = "uart5",
2389 .class = &dra7xx_uart_hwmod_class, 2389 .class = &dra7xx_uart_hwmod_class,
2390 .clkdm_name = "l4per_clkdm", 2390 .clkdm_name = "l4per_clkdm",
2391 .main_clk = "uart5_gfclk_mux", 2391 .main_clk = "uart5_gfclk_mux",
2392 .flags = HWMOD_SWSUP_SIDLE_ACT, 2392 .flags = HWMOD_SWSUP_SIDLE_ACT,
2393 .prcm = { 2393 .prcm = {
2394 .omap4 = { 2394 .omap4 = {
2395 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET, 2395 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2396 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET, 2396 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2397 .modulemode = MODULEMODE_SWCTRL, 2397 .modulemode = MODULEMODE_SWCTRL,
2398 }, 2398 },
2399 }, 2399 },
2400 }; 2400 };
2401 2401
2402 /* uart6 */ 2402 /* uart6 */
2403 static struct omap_hwmod dra7xx_uart6_hwmod = { 2403 static struct omap_hwmod dra7xx_uart6_hwmod = {
2404 .name = "uart6", 2404 .name = "uart6",
2405 .class = &dra7xx_uart_hwmod_class, 2405 .class = &dra7xx_uart_hwmod_class,
2406 .clkdm_name = "ipu_clkdm", 2406 .clkdm_name = "ipu_clkdm",
2407 .main_clk = "uart6_gfclk_mux", 2407 .main_clk = "uart6_gfclk_mux",
2408 .flags = HWMOD_SWSUP_SIDLE_ACT, 2408 .flags = HWMOD_SWSUP_SIDLE_ACT,
2409 .prcm = { 2409 .prcm = {
2410 .omap4 = { 2410 .omap4 = {
2411 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET, 2411 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2412 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET, 2412 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2413 .modulemode = MODULEMODE_SWCTRL, 2413 .modulemode = MODULEMODE_SWCTRL,
2414 }, 2414 },
2415 }, 2415 },
2416 }; 2416 };
2417 2417
2418 /* uart7 */ 2418 /* uart7 */
2419 static struct omap_hwmod dra7xx_uart7_hwmod = { 2419 static struct omap_hwmod dra7xx_uart7_hwmod = {
2420 .name = "uart7", 2420 .name = "uart7",
2421 .class = &dra7xx_uart_hwmod_class, 2421 .class = &dra7xx_uart_hwmod_class,
2422 .clkdm_name = "l4per2_clkdm", 2422 .clkdm_name = "l4per2_clkdm",
2423 .main_clk = "uart7_gfclk_mux", 2423 .main_clk = "uart7_gfclk_mux",
2424 .flags = HWMOD_SWSUP_SIDLE_ACT, 2424 .flags = HWMOD_SWSUP_SIDLE_ACT,
2425 .prcm = { 2425 .prcm = {
2426 .omap4 = { 2426 .omap4 = {
2427 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET, 2427 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2428 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET, 2428 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2429 .modulemode = MODULEMODE_SWCTRL, 2429 .modulemode = MODULEMODE_SWCTRL,
2430 }, 2430 },
2431 }, 2431 },
2432 }; 2432 };
2433 2433
2434 /* uart8 */ 2434 /* uart8 */
2435 static struct omap_hwmod dra7xx_uart8_hwmod = { 2435 static struct omap_hwmod dra7xx_uart8_hwmod = {
2436 .name = "uart8", 2436 .name = "uart8",
2437 .class = &dra7xx_uart_hwmod_class, 2437 .class = &dra7xx_uart_hwmod_class,
2438 .clkdm_name = "l4per2_clkdm", 2438 .clkdm_name = "l4per2_clkdm",
2439 .main_clk = "uart8_gfclk_mux", 2439 .main_clk = "uart8_gfclk_mux",
2440 .flags = HWMOD_SWSUP_SIDLE_ACT, 2440 .flags = HWMOD_SWSUP_SIDLE_ACT,
2441 .prcm = { 2441 .prcm = {
2442 .omap4 = { 2442 .omap4 = {
2443 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET, 2443 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2444 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET, 2444 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2445 .modulemode = MODULEMODE_SWCTRL, 2445 .modulemode = MODULEMODE_SWCTRL,
2446 }, 2446 },
2447 }, 2447 },
2448 }; 2448 };
2449 2449
2450 /* uart9 */ 2450 /* uart9 */
2451 static struct omap_hwmod dra7xx_uart9_hwmod = { 2451 static struct omap_hwmod dra7xx_uart9_hwmod = {
2452 .name = "uart9", 2452 .name = "uart9",
2453 .class = &dra7xx_uart_hwmod_class, 2453 .class = &dra7xx_uart_hwmod_class,
2454 .clkdm_name = "l4per2_clkdm", 2454 .clkdm_name = "l4per2_clkdm",
2455 .main_clk = "uart9_gfclk_mux", 2455 .main_clk = "uart9_gfclk_mux",
2456 .flags = HWMOD_SWSUP_SIDLE_ACT, 2456 .flags = HWMOD_SWSUP_SIDLE_ACT,
2457 .prcm = { 2457 .prcm = {
2458 .omap4 = { 2458 .omap4 = {
2459 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET, 2459 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2460 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET, 2460 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2461 .modulemode = MODULEMODE_SWCTRL, 2461 .modulemode = MODULEMODE_SWCTRL,
2462 }, 2462 },
2463 }, 2463 },
2464 }; 2464 };
2465 2465
2466 /* uart10 */ 2466 /* uart10 */
2467 static struct omap_hwmod dra7xx_uart10_hwmod = { 2467 static struct omap_hwmod dra7xx_uart10_hwmod = {
2468 .name = "uart10", 2468 .name = "uart10",
2469 .class = &dra7xx_uart_hwmod_class, 2469 .class = &dra7xx_uart_hwmod_class,
2470 .clkdm_name = "wkupaon_clkdm", 2470 .clkdm_name = "wkupaon_clkdm",
2471 .main_clk = "uart10_gfclk_mux", 2471 .main_clk = "uart10_gfclk_mux",
2472 .flags = HWMOD_SWSUP_SIDLE_ACT, 2472 .flags = HWMOD_SWSUP_SIDLE_ACT,
2473 .prcm = { 2473 .prcm = {
2474 .omap4 = { 2474 .omap4 = {
2475 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET, 2475 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2476 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET, 2476 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2477 .modulemode = MODULEMODE_SWCTRL, 2477 .modulemode = MODULEMODE_SWCTRL,
2478 }, 2478 },
2479 }, 2479 },
2480 }; 2480 };
2481 2481
2482 /* DES (the 'P' (public) device) */
2483 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2484 .rev_offs = 0x0030,
2485 .sysc_offs = 0x0034,
2486 .syss_offs = 0x0038,
2487 .sysc_flags = SYSS_HAS_RESET_STATUS,
2488 };
2489
2490 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2491 .name = "des",
2492 .sysc = &dra7xx_des_sysc,
2493 };
2494
2495 /* DES */
2496 static struct omap_hwmod dra7xx_des_hwmod = {
2497 .name = "des",
2498 .class = &dra7xx_des_hwmod_class,
2499 .clkdm_name = "l4sec_clkdm",
2500 .main_clk = "l3_iclk_div",
2501 .prcm = {
2502 .omap4 = {
2503 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2504 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2505 .modulemode = MODULEMODE_HWCTRL,
2506 },
2507 },
2508 };
2509
2482 /* 2510 /*
2483 * 'usb_otg_ss' class 2511 * 'usb_otg_ss' class
2484 * 2512 *
2485 */ 2513 */
2486 2514
2487 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = { 2515 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2488 .rev_offs = 0x0000, 2516 .rev_offs = 0x0000,
2489 .sysc_offs = 0x0010, 2517 .sysc_offs = 0x0010,
2490 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | 2518 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2491 SYSC_HAS_SIDLEMODE), 2519 SYSC_HAS_SIDLEMODE),
2492 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2520 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2493 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2521 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2494 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 2522 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2495 .sysc_fields = &omap_hwmod_sysc_type2, 2523 .sysc_fields = &omap_hwmod_sysc_type2,
2496 }; 2524 };
2497 2525
2498 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { 2526 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2499 .name = "usb_otg_ss", 2527 .name = "usb_otg_ss",
2500 .sysc = &dra7xx_usb_otg_ss_sysc, 2528 .sysc = &dra7xx_usb_otg_ss_sysc,
2501 }; 2529 };
2502 2530
2503 /* usb_otg_ss1 */ 2531 /* usb_otg_ss1 */
2504 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = { 2532 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2505 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" }, 2533 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2506 }; 2534 };
2507 2535
2508 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = { 2536 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2509 .name = "usb_otg_ss1", 2537 .name = "usb_otg_ss1",
2510 .class = &dra7xx_usb_otg_ss_hwmod_class, 2538 .class = &dra7xx_usb_otg_ss_hwmod_class,
2511 .clkdm_name = "l3init_clkdm", 2539 .clkdm_name = "l3init_clkdm",
2512 .main_clk = "dpll_core_h13x2_ck", 2540 .main_clk = "dpll_core_h13x2_ck",
2513 .flags = HWMOD_CLKDM_NOAUTO, 2541 .flags = HWMOD_CLKDM_NOAUTO,
2514 .prcm = { 2542 .prcm = {
2515 .omap4 = { 2543 .omap4 = {
2516 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET, 2544 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2517 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET, 2545 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2518 .modulemode = MODULEMODE_HWCTRL, 2546 .modulemode = MODULEMODE_HWCTRL,
2519 }, 2547 },
2520 }, 2548 },
2521 .opt_clks = usb_otg_ss1_opt_clks, 2549 .opt_clks = usb_otg_ss1_opt_clks,
2522 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks), 2550 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2523 }; 2551 };
2524 2552
2525 /* usb_otg_ss2 */ 2553 /* usb_otg_ss2 */
2526 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = { 2554 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2527 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" }, 2555 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2528 }; 2556 };
2529 2557
2530 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = { 2558 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2531 .name = "usb_otg_ss2", 2559 .name = "usb_otg_ss2",
2532 .class = &dra7xx_usb_otg_ss_hwmod_class, 2560 .class = &dra7xx_usb_otg_ss_hwmod_class,
2533 .clkdm_name = "l3init_clkdm", 2561 .clkdm_name = "l3init_clkdm",
2534 .main_clk = "dpll_core_h13x2_ck", 2562 .main_clk = "dpll_core_h13x2_ck",
2535 .flags = HWMOD_CLKDM_NOAUTO, 2563 .flags = HWMOD_CLKDM_NOAUTO,
2536 .prcm = { 2564 .prcm = {
2537 .omap4 = { 2565 .omap4 = {
2538 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET, 2566 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2539 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET, 2567 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2540 .modulemode = MODULEMODE_HWCTRL, 2568 .modulemode = MODULEMODE_HWCTRL,
2541 }, 2569 },
2542 }, 2570 },
2543 .opt_clks = usb_otg_ss2_opt_clks, 2571 .opt_clks = usb_otg_ss2_opt_clks,
2544 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks), 2572 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2545 }; 2573 };
2546 2574
2547 /* usb_otg_ss3 */ 2575 /* usb_otg_ss3 */
2548 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = { 2576 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2549 .name = "usb_otg_ss3", 2577 .name = "usb_otg_ss3",
2550 .class = &dra7xx_usb_otg_ss_hwmod_class, 2578 .class = &dra7xx_usb_otg_ss_hwmod_class,
2551 .clkdm_name = "l3init_clkdm", 2579 .clkdm_name = "l3init_clkdm",
2552 .main_clk = "dpll_core_h13x2_ck", 2580 .main_clk = "dpll_core_h13x2_ck",
2553 .prcm = { 2581 .prcm = {
2554 .omap4 = { 2582 .omap4 = {
2555 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET, 2583 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2556 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET, 2584 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2557 .modulemode = MODULEMODE_HWCTRL, 2585 .modulemode = MODULEMODE_HWCTRL,
2558 }, 2586 },
2559 }, 2587 },
2560 }; 2588 };
2561 2589
2562 /* usb_otg_ss4 */ 2590 /* usb_otg_ss4 */
2563 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = { 2591 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2564 .name = "usb_otg_ss4", 2592 .name = "usb_otg_ss4",
2565 .class = &dra7xx_usb_otg_ss_hwmod_class, 2593 .class = &dra7xx_usb_otg_ss_hwmod_class,
2566 .clkdm_name = "l3init_clkdm", 2594 .clkdm_name = "l3init_clkdm",
2567 .main_clk = "dpll_core_h13x2_ck", 2595 .main_clk = "dpll_core_h13x2_ck",
2568 .prcm = { 2596 .prcm = {
2569 .omap4 = { 2597 .omap4 = {
2570 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET, 2598 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2571 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET, 2599 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2572 .modulemode = MODULEMODE_HWCTRL, 2600 .modulemode = MODULEMODE_HWCTRL,
2573 }, 2601 },
2574 }, 2602 },
2575 }; 2603 };
2576 2604
2577 /* 2605 /*
2578 * 'vcp' class 2606 * 'vcp' class
2579 * 2607 *
2580 */ 2608 */
2581 2609
2582 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = { 2610 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2583 .name = "vcp", 2611 .name = "vcp",
2584 }; 2612 };
2585 2613
2586 /* vcp1 */ 2614 /* vcp1 */
2587 static struct omap_hwmod dra7xx_vcp1_hwmod = { 2615 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2588 .name = "vcp1", 2616 .name = "vcp1",
2589 .class = &dra7xx_vcp_hwmod_class, 2617 .class = &dra7xx_vcp_hwmod_class,
2590 .clkdm_name = "l3main1_clkdm", 2618 .clkdm_name = "l3main1_clkdm",
2591 .main_clk = "l3_iclk_div", 2619 .main_clk = "l3_iclk_div",
2592 .prcm = { 2620 .prcm = {
2593 .omap4 = { 2621 .omap4 = {
2594 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET, 2622 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2595 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET, 2623 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2596 }, 2624 },
2597 }, 2625 },
2598 }; 2626 };
2599 2627
2600 /* vcp2 */ 2628 /* vcp2 */
2601 static struct omap_hwmod dra7xx_vcp2_hwmod = { 2629 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2602 .name = "vcp2", 2630 .name = "vcp2",
2603 .class = &dra7xx_vcp_hwmod_class, 2631 .class = &dra7xx_vcp_hwmod_class,
2604 .clkdm_name = "l3main1_clkdm", 2632 .clkdm_name = "l3main1_clkdm",
2605 .main_clk = "l3_iclk_div", 2633 .main_clk = "l3_iclk_div",
2606 .prcm = { 2634 .prcm = {
2607 .omap4 = { 2635 .omap4 = {
2608 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET, 2636 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2609 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET, 2637 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2610 }, 2638 },
2611 }, 2639 },
2612 }; 2640 };
2613 2641
2614 /* 2642 /*
2615 * 'wd_timer' class 2643 * 'wd_timer' class
2616 * 2644 *
2617 */ 2645 */
2618 2646
2619 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = { 2647 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2620 .rev_offs = 0x0000, 2648 .rev_offs = 0x0000,
2621 .sysc_offs = 0x0010, 2649 .sysc_offs = 0x0010,
2622 .syss_offs = 0x0014, 2650 .syss_offs = 0x0014,
2623 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | 2651 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2624 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2652 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2625 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2626 SIDLE_SMART_WKUP), 2654 SIDLE_SMART_WKUP),
2627 .sysc_fields = &omap_hwmod_sysc_type1, 2655 .sysc_fields = &omap_hwmod_sysc_type1,
2628 }; 2656 };
2629 2657
2630 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = { 2658 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2631 .name = "wd_timer", 2659 .name = "wd_timer",
2632 .sysc = &dra7xx_wd_timer_sysc, 2660 .sysc = &dra7xx_wd_timer_sysc,
2633 .pre_shutdown = &omap2_wd_timer_disable, 2661 .pre_shutdown = &omap2_wd_timer_disable,
2634 .reset = &omap2_wd_timer_reset, 2662 .reset = &omap2_wd_timer_reset,
2635 }; 2663 };
2636 2664
2637 /* wd_timer2 */ 2665 /* wd_timer2 */
2638 static struct omap_hwmod dra7xx_wd_timer2_hwmod = { 2666 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2639 .name = "wd_timer2", 2667 .name = "wd_timer2",
2640 .class = &dra7xx_wd_timer_hwmod_class, 2668 .class = &dra7xx_wd_timer_hwmod_class,
2641 .clkdm_name = "wkupaon_clkdm", 2669 .clkdm_name = "wkupaon_clkdm",
2642 .main_clk = "sys_32k_ck", 2670 .main_clk = "sys_32k_ck",
2643 .prcm = { 2671 .prcm = {
2644 .omap4 = { 2672 .omap4 = {
2645 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, 2673 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2646 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, 2674 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2647 .modulemode = MODULEMODE_SWCTRL, 2675 .modulemode = MODULEMODE_SWCTRL,
2648 }, 2676 },
2649 }, 2677 },
2650 }; 2678 };
2651 2679
2652 2680
2653 /* 2681 /*
2654 * Interfaces 2682 * Interfaces
2655 */ 2683 */
2656 2684
2657 /* l3_main_1 -> dmm */ 2685 /* l3_main_1 -> dmm */
2658 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = { 2686 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2659 .master = &dra7xx_l3_main_1_hwmod, 2687 .master = &dra7xx_l3_main_1_hwmod,
2660 .slave = &dra7xx_dmm_hwmod, 2688 .slave = &dra7xx_dmm_hwmod,
2661 .clk = "l3_iclk_div", 2689 .clk = "l3_iclk_div",
2662 .user = OCP_USER_SDMA, 2690 .user = OCP_USER_SDMA,
2663 }; 2691 };
2664 2692
2665 /* l3_main_2 -> l3_instr */ 2693 /* l3_main_2 -> l3_instr */
2666 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { 2694 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2667 .master = &dra7xx_l3_main_2_hwmod, 2695 .master = &dra7xx_l3_main_2_hwmod,
2668 .slave = &dra7xx_l3_instr_hwmod, 2696 .slave = &dra7xx_l3_instr_hwmod,
2669 .clk = "l3_iclk_div", 2697 .clk = "l3_iclk_div",
2670 .user = OCP_USER_MPU | OCP_USER_SDMA, 2698 .user = OCP_USER_MPU | OCP_USER_SDMA,
2671 }; 2699 };
2672 2700
2673 /* l4_cfg -> l3_main_1 */ 2701 /* l4_cfg -> l3_main_1 */
2674 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = { 2702 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2675 .master = &dra7xx_l4_cfg_hwmod, 2703 .master = &dra7xx_l4_cfg_hwmod,
2676 .slave = &dra7xx_l3_main_1_hwmod, 2704 .slave = &dra7xx_l3_main_1_hwmod,
2677 .clk = "l3_iclk_div", 2705 .clk = "l3_iclk_div",
2678 .user = OCP_USER_MPU | OCP_USER_SDMA, 2706 .user = OCP_USER_MPU | OCP_USER_SDMA,
2679 }; 2707 };
2680 2708
2681 /* mpu -> l3_main_1 */ 2709 /* mpu -> l3_main_1 */
2682 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = { 2710 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2683 .master = &dra7xx_mpu_hwmod, 2711 .master = &dra7xx_mpu_hwmod,
2684 .slave = &dra7xx_l3_main_1_hwmod, 2712 .slave = &dra7xx_l3_main_1_hwmod,
2685 .clk = "l3_iclk_div", 2713 .clk = "l3_iclk_div",
2686 .user = OCP_USER_MPU, 2714 .user = OCP_USER_MPU,
2687 }; 2715 };
2688 2716
2689 /* l3_main_1 -> l3_main_2 */ 2717 /* l3_main_1 -> l3_main_2 */
2690 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = { 2718 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2691 .master = &dra7xx_l3_main_1_hwmod, 2719 .master = &dra7xx_l3_main_1_hwmod,
2692 .slave = &dra7xx_l3_main_2_hwmod, 2720 .slave = &dra7xx_l3_main_2_hwmod,
2693 .clk = "l3_iclk_div", 2721 .clk = "l3_iclk_div",
2694 .user = OCP_USER_MPU, 2722 .user = OCP_USER_MPU,
2695 }; 2723 };
2696 2724
2697 /* l4_cfg -> l3_main_2 */ 2725 /* l4_cfg -> l3_main_2 */
2698 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = { 2726 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2699 .master = &dra7xx_l4_cfg_hwmod, 2727 .master = &dra7xx_l4_cfg_hwmod,
2700 .slave = &dra7xx_l3_main_2_hwmod, 2728 .slave = &dra7xx_l3_main_2_hwmod,
2701 .clk = "l3_iclk_div", 2729 .clk = "l3_iclk_div",
2702 .user = OCP_USER_MPU | OCP_USER_SDMA, 2730 .user = OCP_USER_MPU | OCP_USER_SDMA,
2703 }; 2731 };
2704 2732
2705 /* l3_main_1 -> l4_cfg */ 2733 /* l3_main_1 -> l4_cfg */
2706 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { 2734 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2707 .master = &dra7xx_l3_main_1_hwmod, 2735 .master = &dra7xx_l3_main_1_hwmod,
2708 .slave = &dra7xx_l4_cfg_hwmod, 2736 .slave = &dra7xx_l4_cfg_hwmod,
2709 .clk = "l3_iclk_div", 2737 .clk = "l3_iclk_div",
2710 .user = OCP_USER_MPU | OCP_USER_SDMA, 2738 .user = OCP_USER_MPU | OCP_USER_SDMA,
2711 }; 2739 };
2712 2740
2713 /* l3_main_1 -> l4_per1 */ 2741 /* l3_main_1 -> l4_per1 */
2714 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { 2742 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2715 .master = &dra7xx_l3_main_1_hwmod, 2743 .master = &dra7xx_l3_main_1_hwmod,
2716 .slave = &dra7xx_l4_per1_hwmod, 2744 .slave = &dra7xx_l4_per1_hwmod,
2717 .clk = "l3_iclk_div", 2745 .clk = "l3_iclk_div",
2718 .user = OCP_USER_MPU | OCP_USER_SDMA, 2746 .user = OCP_USER_MPU | OCP_USER_SDMA,
2719 }; 2747 };
2720 2748
2721 /* l3_main_1 -> l4_per2 */ 2749 /* l3_main_1 -> l4_per2 */
2722 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { 2750 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2723 .master = &dra7xx_l3_main_1_hwmod, 2751 .master = &dra7xx_l3_main_1_hwmod,
2724 .slave = &dra7xx_l4_per2_hwmod, 2752 .slave = &dra7xx_l4_per2_hwmod,
2725 .clk = "l3_iclk_div", 2753 .clk = "l3_iclk_div",
2726 .user = OCP_USER_MPU | OCP_USER_SDMA, 2754 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727 }; 2755 };
2728 2756
2729 /* l3_main_1 -> l4_per3 */ 2757 /* l3_main_1 -> l4_per3 */
2730 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { 2758 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2731 .master = &dra7xx_l3_main_1_hwmod, 2759 .master = &dra7xx_l3_main_1_hwmod,
2732 .slave = &dra7xx_l4_per3_hwmod, 2760 .slave = &dra7xx_l4_per3_hwmod,
2733 .clk = "l3_iclk_div", 2761 .clk = "l3_iclk_div",
2734 .user = OCP_USER_MPU | OCP_USER_SDMA, 2762 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735 }; 2763 };
2736 2764
2737 /* l3_main_1 -> l4_wkup */ 2765 /* l3_main_1 -> l4_wkup */
2738 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = { 2766 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2739 .master = &dra7xx_l3_main_1_hwmod, 2767 .master = &dra7xx_l3_main_1_hwmod,
2740 .slave = &dra7xx_l4_wkup_hwmod, 2768 .slave = &dra7xx_l4_wkup_hwmod,
2741 .clk = "wkupaon_iclk_mux", 2769 .clk = "wkupaon_iclk_mux",
2742 .user = OCP_USER_MPU | OCP_USER_SDMA, 2770 .user = OCP_USER_MPU | OCP_USER_SDMA,
2743 }; 2771 };
2744 2772
2745 /* l4_per2 -> atl */ 2773 /* l4_per2 -> atl */
2746 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { 2774 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2747 .master = &dra7xx_l4_per2_hwmod, 2775 .master = &dra7xx_l4_per2_hwmod,
2748 .slave = &dra7xx_atl_hwmod, 2776 .slave = &dra7xx_atl_hwmod,
2749 .clk = "l3_iclk_div", 2777 .clk = "l3_iclk_div",
2750 .user = OCP_USER_MPU | OCP_USER_SDMA, 2778 .user = OCP_USER_MPU | OCP_USER_SDMA,
2751 }; 2779 };
2752 2780
2753 /* l3_main_1 -> bb2d */ 2781 /* l3_main_1 -> bb2d */
2754 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { 2782 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2755 .master = &dra7xx_l3_main_1_hwmod, 2783 .master = &dra7xx_l3_main_1_hwmod,
2756 .slave = &dra7xx_bb2d_hwmod, 2784 .slave = &dra7xx_bb2d_hwmod,
2757 .clk = "l3_iclk_div", 2785 .clk = "l3_iclk_div",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA, 2786 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759 }; 2787 };
2760 2788
2761 /* l4_wkup -> counter_32k */ 2789 /* l4_wkup -> counter_32k */
2762 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = { 2790 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2763 .master = &dra7xx_l4_wkup_hwmod, 2791 .master = &dra7xx_l4_wkup_hwmod,
2764 .slave = &dra7xx_counter_32k_hwmod, 2792 .slave = &dra7xx_counter_32k_hwmod,
2765 .clk = "wkupaon_iclk_mux", 2793 .clk = "wkupaon_iclk_mux",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA, 2794 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767 }; 2795 };
2768 2796
2769 /* l4_wkup -> ctrl_module_wkup */ 2797 /* l4_wkup -> ctrl_module_wkup */
2770 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { 2798 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2771 .master = &dra7xx_l4_wkup_hwmod, 2799 .master = &dra7xx_l4_wkup_hwmod,
2772 .slave = &dra7xx_ctrl_module_wkup_hwmod, 2800 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2773 .clk = "wkupaon_iclk_mux", 2801 .clk = "wkupaon_iclk_mux",
2774 .user = OCP_USER_MPU | OCP_USER_SDMA, 2802 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775 }; 2803 };
2776 2804
2777 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = { 2805 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2778 .master = &dra7xx_l4_per2_hwmod, 2806 .master = &dra7xx_l4_per2_hwmod,
2779 .slave = &dra7xx_gmac_hwmod, 2807 .slave = &dra7xx_gmac_hwmod,
2780 .clk = "dpll_gmac_ck", 2808 .clk = "dpll_gmac_ck",
2781 .user = OCP_USER_MPU, 2809 .user = OCP_USER_MPU,
2782 }; 2810 };
2783 2811
2784 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = { 2812 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2785 .master = &dra7xx_gmac_hwmod, 2813 .master = &dra7xx_gmac_hwmod,
2786 .slave = &dra7xx_mdio_hwmod, 2814 .slave = &dra7xx_mdio_hwmod,
2787 .user = OCP_USER_MPU, 2815 .user = OCP_USER_MPU,
2788 }; 2816 };
2789 2817
2790 /* l4_wkup -> dcan1 */ 2818 /* l4_wkup -> dcan1 */
2791 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { 2819 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2792 .master = &dra7xx_l4_wkup_hwmod, 2820 .master = &dra7xx_l4_wkup_hwmod,
2793 .slave = &dra7xx_dcan1_hwmod, 2821 .slave = &dra7xx_dcan1_hwmod,
2794 .clk = "wkupaon_iclk_mux", 2822 .clk = "wkupaon_iclk_mux",
2795 .user = OCP_USER_MPU | OCP_USER_SDMA, 2823 .user = OCP_USER_MPU | OCP_USER_SDMA,
2796 }; 2824 };
2797 2825
2798 /* l4_per2 -> dcan2 */ 2826 /* l4_per2 -> dcan2 */
2799 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = { 2827 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2800 .master = &dra7xx_l4_per2_hwmod, 2828 .master = &dra7xx_l4_per2_hwmod,
2801 .slave = &dra7xx_dcan2_hwmod, 2829 .slave = &dra7xx_dcan2_hwmod,
2802 .clk = "l3_iclk_div", 2830 .clk = "l3_iclk_div",
2803 .user = OCP_USER_MPU | OCP_USER_SDMA, 2831 .user = OCP_USER_MPU | OCP_USER_SDMA,
2804 }; 2832 };
2805 2833
2806 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = { 2834 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2807 { 2835 {
2808 .pa_start = 0x4a056000, 2836 .pa_start = 0x4a056000,
2809 .pa_end = 0x4a056fff, 2837 .pa_end = 0x4a056fff,
2810 .flags = ADDR_TYPE_RT 2838 .flags = ADDR_TYPE_RT
2811 }, 2839 },
2812 { } 2840 { }
2813 }; 2841 };
2814 2842
2815 /* l4_cfg -> dma_system */ 2843 /* l4_cfg -> dma_system */
2816 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = { 2844 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2817 .master = &dra7xx_l4_cfg_hwmod, 2845 .master = &dra7xx_l4_cfg_hwmod,
2818 .slave = &dra7xx_dma_system_hwmod, 2846 .slave = &dra7xx_dma_system_hwmod,
2819 .clk = "l3_iclk_div", 2847 .clk = "l3_iclk_div",
2820 .addr = dra7xx_dma_system_addrs, 2848 .addr = dra7xx_dma_system_addrs,
2821 .user = OCP_USER_MPU | OCP_USER_SDMA, 2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822 }; 2850 };
2823 2851
2824 /* l3_main_1 -> tpcc */ 2852 /* l3_main_1 -> tpcc */
2825 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = { 2853 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2826 .master = &dra7xx_l3_main_1_hwmod, 2854 .master = &dra7xx_l3_main_1_hwmod,
2827 .slave = &dra7xx_tpcc_hwmod, 2855 .slave = &dra7xx_tpcc_hwmod,
2828 .clk = "l3_iclk_div", 2856 .clk = "l3_iclk_div",
2829 .user = OCP_USER_MPU, 2857 .user = OCP_USER_MPU,
2830 }; 2858 };
2831 2859
2832 /* l3_main_1 -> tptc0 */ 2860 /* l3_main_1 -> tptc0 */
2833 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = { 2861 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2834 .master = &dra7xx_l3_main_1_hwmod, 2862 .master = &dra7xx_l3_main_1_hwmod,
2835 .slave = &dra7xx_tptc0_hwmod, 2863 .slave = &dra7xx_tptc0_hwmod,
2836 .clk = "l3_iclk_div", 2864 .clk = "l3_iclk_div",
2837 .user = OCP_USER_MPU, 2865 .user = OCP_USER_MPU,
2838 }; 2866 };
2839 2867
2840 /* l3_main_1 -> tptc1 */ 2868 /* l3_main_1 -> tptc1 */
2841 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = { 2869 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2842 .master = &dra7xx_l3_main_1_hwmod, 2870 .master = &dra7xx_l3_main_1_hwmod,
2843 .slave = &dra7xx_tptc1_hwmod, 2871 .slave = &dra7xx_tptc1_hwmod,
2844 .clk = "l3_iclk_div", 2872 .clk = "l3_iclk_div",
2845 .user = OCP_USER_MPU, 2873 .user = OCP_USER_MPU,
2846 }; 2874 };
2847 2875
2848 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = { 2876 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2849 { 2877 {
2850 .name = "family", 2878 .name = "family",
2851 .pa_start = 0x58000000, 2879 .pa_start = 0x58000000,
2852 .pa_end = 0x5800007f, 2880 .pa_end = 0x5800007f,
2853 .flags = ADDR_TYPE_RT 2881 .flags = ADDR_TYPE_RT
2854 }, 2882 },
2855 }; 2883 };
2856 2884
2857 /* l3_main_1 -> dss */ 2885 /* l3_main_1 -> dss */
2858 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { 2886 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2859 .master = &dra7xx_l3_main_1_hwmod, 2887 .master = &dra7xx_l3_main_1_hwmod,
2860 .slave = &dra7xx_dss_hwmod, 2888 .slave = &dra7xx_dss_hwmod,
2861 .clk = "l3_iclk_div", 2889 .clk = "l3_iclk_div",
2862 .addr = dra7xx_dss_addrs, 2890 .addr = dra7xx_dss_addrs,
2863 .user = OCP_USER_MPU | OCP_USER_SDMA, 2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2864 }; 2892 };
2865 2893
2866 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = { 2894 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2867 { 2895 {
2868 .name = "dispc", 2896 .name = "dispc",
2869 .pa_start = 0x58001000, 2897 .pa_start = 0x58001000,
2870 .pa_end = 0x58001fff, 2898 .pa_end = 0x58001fff,
2871 .flags = ADDR_TYPE_RT 2899 .flags = ADDR_TYPE_RT
2872 }, 2900 },
2873 }; 2901 };
2874 2902
2875 /* l3_main_1 -> dispc */ 2903 /* l3_main_1 -> dispc */
2876 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = { 2904 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2877 .master = &dra7xx_l3_main_1_hwmod, 2905 .master = &dra7xx_l3_main_1_hwmod,
2878 .slave = &dra7xx_dss_dispc_hwmod, 2906 .slave = &dra7xx_dss_dispc_hwmod,
2879 .clk = "l3_iclk_div", 2907 .clk = "l3_iclk_div",
2880 .addr = dra7xx_dss_dispc_addrs, 2908 .addr = dra7xx_dss_dispc_addrs,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA, 2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882 }; 2910 };
2883 2911
2884 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = { 2912 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2885 { 2913 {
2886 .name = "hdmi_wp", 2914 .name = "hdmi_wp",
2887 .pa_start = 0x58040000, 2915 .pa_start = 0x58040000,
2888 .pa_end = 0x580400ff, 2916 .pa_end = 0x580400ff,
2889 .flags = ADDR_TYPE_RT 2917 .flags = ADDR_TYPE_RT
2890 }, 2918 },
2891 { } 2919 { }
2892 }; 2920 };
2893 2921
2894 /* l3_main_1 -> dispc */ 2922 /* l3_main_1 -> dispc */
2895 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { 2923 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2896 .master = &dra7xx_l3_main_1_hwmod, 2924 .master = &dra7xx_l3_main_1_hwmod,
2897 .slave = &dra7xx_dss_hdmi_hwmod, 2925 .slave = &dra7xx_dss_hdmi_hwmod,
2898 .clk = "l3_iclk_div", 2926 .clk = "l3_iclk_div",
2899 .addr = dra7xx_dss_hdmi_addrs, 2927 .addr = dra7xx_dss_hdmi_addrs,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA, 2928 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 }; 2929 };
2902 2930
2903 /* l4_per2 -> mcasp1 */ 2931 /* l4_per2 -> mcasp1 */
2904 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { 2932 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2905 .master = &dra7xx_l4_per2_hwmod, 2933 .master = &dra7xx_l4_per2_hwmod,
2906 .slave = &dra7xx_mcasp1_hwmod, 2934 .slave = &dra7xx_mcasp1_hwmod,
2907 .clk = "l4_root_clk_div", 2935 .clk = "l4_root_clk_div",
2908 .user = OCP_USER_MPU | OCP_USER_SDMA, 2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2909 }; 2937 };
2910 2938
2911 /* l3_main_1 -> mcasp1 */ 2939 /* l3_main_1 -> mcasp1 */
2912 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = { 2940 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2913 .master = &dra7xx_l3_main_1_hwmod, 2941 .master = &dra7xx_l3_main_1_hwmod,
2914 .slave = &dra7xx_mcasp1_hwmod, 2942 .slave = &dra7xx_mcasp1_hwmod,
2915 .clk = "l3_iclk_div", 2943 .clk = "l3_iclk_div",
2916 .user = OCP_USER_MPU | OCP_USER_SDMA, 2944 .user = OCP_USER_MPU | OCP_USER_SDMA,
2917 }; 2945 };
2918 2946
2919 /* l4_per2 -> mcasp2 */ 2947 /* l4_per2 -> mcasp2 */
2920 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { 2948 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2921 .master = &dra7xx_l4_per2_hwmod, 2949 .master = &dra7xx_l4_per2_hwmod,
2922 .slave = &dra7xx_mcasp2_hwmod, 2950 .slave = &dra7xx_mcasp2_hwmod,
2923 .clk = "l4_root_clk_div", 2951 .clk = "l4_root_clk_div",
2924 .user = OCP_USER_MPU | OCP_USER_SDMA, 2952 .user = OCP_USER_MPU | OCP_USER_SDMA,
2925 }; 2953 };
2926 2954
2927 /* l3_main_1 -> mcasp2 */ 2955 /* l3_main_1 -> mcasp2 */
2928 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = { 2956 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2929 .master = &dra7xx_l3_main_1_hwmod, 2957 .master = &dra7xx_l3_main_1_hwmod,
2930 .slave = &dra7xx_mcasp2_hwmod, 2958 .slave = &dra7xx_mcasp2_hwmod,
2931 .clk = "l3_iclk_div", 2959 .clk = "l3_iclk_div",
2932 .user = OCP_USER_MPU | OCP_USER_SDMA, 2960 .user = OCP_USER_MPU | OCP_USER_SDMA,
2933 }; 2961 };
2934 2962
2935 /* l4_per2 -> mcasp3 */ 2963 /* l4_per2 -> mcasp3 */
2936 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { 2964 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2937 .master = &dra7xx_l4_per2_hwmod, 2965 .master = &dra7xx_l4_per2_hwmod,
2938 .slave = &dra7xx_mcasp3_hwmod, 2966 .slave = &dra7xx_mcasp3_hwmod,
2939 .clk = "l4_root_clk_div", 2967 .clk = "l4_root_clk_div",
2940 .user = OCP_USER_MPU | OCP_USER_SDMA, 2968 .user = OCP_USER_MPU | OCP_USER_SDMA,
2941 }; 2969 };
2942 2970
2943 /* l3_main_1 -> mcasp3 */ 2971 /* l3_main_1 -> mcasp3 */
2944 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = { 2972 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2945 .master = &dra7xx_l3_main_1_hwmod, 2973 .master = &dra7xx_l3_main_1_hwmod,
2946 .slave = &dra7xx_mcasp3_hwmod, 2974 .slave = &dra7xx_mcasp3_hwmod,
2947 .clk = "l3_iclk_div", 2975 .clk = "l3_iclk_div",
2948 .user = OCP_USER_MPU | OCP_USER_SDMA, 2976 .user = OCP_USER_MPU | OCP_USER_SDMA,
2949 }; 2977 };
2950 2978
2951 /* l4_per2 -> mcasp4 */ 2979 /* l4_per2 -> mcasp4 */
2952 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = { 2980 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
2953 .master = &dra7xx_l4_per2_hwmod, 2981 .master = &dra7xx_l4_per2_hwmod,
2954 .slave = &dra7xx_mcasp4_hwmod, 2982 .slave = &dra7xx_mcasp4_hwmod,
2955 .clk = "l4_root_clk_div", 2983 .clk = "l4_root_clk_div",
2956 .user = OCP_USER_MPU | OCP_USER_SDMA, 2984 .user = OCP_USER_MPU | OCP_USER_SDMA,
2957 }; 2985 };
2958 2986
2959 /* l4_per2 -> mcasp5 */ 2987 /* l4_per2 -> mcasp5 */
2960 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = { 2988 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
2961 .master = &dra7xx_l4_per2_hwmod, 2989 .master = &dra7xx_l4_per2_hwmod,
2962 .slave = &dra7xx_mcasp5_hwmod, 2990 .slave = &dra7xx_mcasp5_hwmod,
2963 .clk = "l4_root_clk_div", 2991 .clk = "l4_root_clk_div",
2964 .user = OCP_USER_MPU | OCP_USER_SDMA, 2992 .user = OCP_USER_MPU | OCP_USER_SDMA,
2965 }; 2993 };
2966 2994
2967 /* l4_per2 -> mcasp6 */ 2995 /* l4_per2 -> mcasp6 */
2968 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { 2996 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
2969 .master = &dra7xx_l4_per2_hwmod, 2997 .master = &dra7xx_l4_per2_hwmod,
2970 .slave = &dra7xx_mcasp6_hwmod, 2998 .slave = &dra7xx_mcasp6_hwmod,
2971 .clk = "l4_root_clk_div", 2999 .clk = "l4_root_clk_div",
2972 .user = OCP_USER_MPU | OCP_USER_SDMA, 3000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2973 }; 3001 };
2974 3002
2975 /* l4_per2 -> mcasp7 */ 3003 /* l4_per2 -> mcasp7 */
2976 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = { 3004 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
2977 .master = &dra7xx_l4_per2_hwmod, 3005 .master = &dra7xx_l4_per2_hwmod,
2978 .slave = &dra7xx_mcasp7_hwmod, 3006 .slave = &dra7xx_mcasp7_hwmod,
2979 .clk = "l4_root_clk_div", 3007 .clk = "l4_root_clk_div",
2980 .user = OCP_USER_MPU | OCP_USER_SDMA, 3008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981 }; 3009 };
2982 3010
2983 /* l4_per2 -> mcasp8 */ 3011 /* l4_per2 -> mcasp8 */
2984 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = { 3012 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
2985 .master = &dra7xx_l4_per2_hwmod, 3013 .master = &dra7xx_l4_per2_hwmod,
2986 .slave = &dra7xx_mcasp8_hwmod, 3014 .slave = &dra7xx_mcasp8_hwmod,
2987 .clk = "l4_root_clk_div", 3015 .clk = "l4_root_clk_div",
2988 .user = OCP_USER_MPU | OCP_USER_SDMA, 3016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989 }; 3017 };
2990 3018
2991 /* l4_per1 -> elm */ 3019 /* l4_per1 -> elm */
2992 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { 3020 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2993 .master = &dra7xx_l4_per1_hwmod, 3021 .master = &dra7xx_l4_per1_hwmod,
2994 .slave = &dra7xx_elm_hwmod, 3022 .slave = &dra7xx_elm_hwmod,
2995 .clk = "l3_iclk_div", 3023 .clk = "l3_iclk_div",
2996 .user = OCP_USER_MPU | OCP_USER_SDMA, 3024 .user = OCP_USER_MPU | OCP_USER_SDMA,
2997 }; 3025 };
2998 3026
2999 /* l4_wkup -> gpio1 */ 3027 /* l4_wkup -> gpio1 */
3000 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = { 3028 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3001 .master = &dra7xx_l4_wkup_hwmod, 3029 .master = &dra7xx_l4_wkup_hwmod,
3002 .slave = &dra7xx_gpio1_hwmod, 3030 .slave = &dra7xx_gpio1_hwmod,
3003 .clk = "wkupaon_iclk_mux", 3031 .clk = "wkupaon_iclk_mux",
3004 .user = OCP_USER_MPU | OCP_USER_SDMA, 3032 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 }; 3033 };
3006 3034
3007 /* l4_per1 -> gpio2 */ 3035 /* l4_per1 -> gpio2 */
3008 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = { 3036 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3009 .master = &dra7xx_l4_per1_hwmod, 3037 .master = &dra7xx_l4_per1_hwmod,
3010 .slave = &dra7xx_gpio2_hwmod, 3038 .slave = &dra7xx_gpio2_hwmod,
3011 .clk = "l3_iclk_div", 3039 .clk = "l3_iclk_div",
3012 .user = OCP_USER_MPU | OCP_USER_SDMA, 3040 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013 }; 3041 };
3014 3042
3015 /* l4_per1 -> gpio3 */ 3043 /* l4_per1 -> gpio3 */
3016 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = { 3044 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3017 .master = &dra7xx_l4_per1_hwmod, 3045 .master = &dra7xx_l4_per1_hwmod,
3018 .slave = &dra7xx_gpio3_hwmod, 3046 .slave = &dra7xx_gpio3_hwmod,
3019 .clk = "l3_iclk_div", 3047 .clk = "l3_iclk_div",
3020 .user = OCP_USER_MPU | OCP_USER_SDMA, 3048 .user = OCP_USER_MPU | OCP_USER_SDMA,
3021 }; 3049 };
3022 3050
3023 /* l4_per1 -> gpio4 */ 3051 /* l4_per1 -> gpio4 */
3024 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = { 3052 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3025 .master = &dra7xx_l4_per1_hwmod, 3053 .master = &dra7xx_l4_per1_hwmod,
3026 .slave = &dra7xx_gpio4_hwmod, 3054 .slave = &dra7xx_gpio4_hwmod,
3027 .clk = "l3_iclk_div", 3055 .clk = "l3_iclk_div",
3028 .user = OCP_USER_MPU | OCP_USER_SDMA, 3056 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029 }; 3057 };
3030 3058
3031 /* l4_per1 -> gpio5 */ 3059 /* l4_per1 -> gpio5 */
3032 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = { 3060 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3033 .master = &dra7xx_l4_per1_hwmod, 3061 .master = &dra7xx_l4_per1_hwmod,
3034 .slave = &dra7xx_gpio5_hwmod, 3062 .slave = &dra7xx_gpio5_hwmod,
3035 .clk = "l3_iclk_div", 3063 .clk = "l3_iclk_div",
3036 .user = OCP_USER_MPU | OCP_USER_SDMA, 3064 .user = OCP_USER_MPU | OCP_USER_SDMA,
3037 }; 3065 };
3038 3066
3039 /* l4_per1 -> gpio6 */ 3067 /* l4_per1 -> gpio6 */
3040 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = { 3068 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3041 .master = &dra7xx_l4_per1_hwmod, 3069 .master = &dra7xx_l4_per1_hwmod,
3042 .slave = &dra7xx_gpio6_hwmod, 3070 .slave = &dra7xx_gpio6_hwmod,
3043 .clk = "l3_iclk_div", 3071 .clk = "l3_iclk_div",
3044 .user = OCP_USER_MPU | OCP_USER_SDMA, 3072 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045 }; 3073 };
3046 3074
3047 /* l4_per1 -> gpio7 */ 3075 /* l4_per1 -> gpio7 */
3048 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = { 3076 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3049 .master = &dra7xx_l4_per1_hwmod, 3077 .master = &dra7xx_l4_per1_hwmod,
3050 .slave = &dra7xx_gpio7_hwmod, 3078 .slave = &dra7xx_gpio7_hwmod,
3051 .clk = "l3_iclk_div", 3079 .clk = "l3_iclk_div",
3052 .user = OCP_USER_MPU | OCP_USER_SDMA, 3080 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053 }; 3081 };
3054 3082
3055 /* l4_per1 -> gpio8 */ 3083 /* l4_per1 -> gpio8 */
3056 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = { 3084 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3057 .master = &dra7xx_l4_per1_hwmod, 3085 .master = &dra7xx_l4_per1_hwmod,
3058 .slave = &dra7xx_gpio8_hwmod, 3086 .slave = &dra7xx_gpio8_hwmod,
3059 .clk = "l3_iclk_div", 3087 .clk = "l3_iclk_div",
3060 .user = OCP_USER_MPU | OCP_USER_SDMA, 3088 .user = OCP_USER_MPU | OCP_USER_SDMA,
3061 }; 3089 };
3062 3090
3063 /* l3_main_1 -> gpmc */ 3091 /* l3_main_1 -> gpmc */
3064 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { 3092 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3065 .master = &dra7xx_l3_main_1_hwmod, 3093 .master = &dra7xx_l3_main_1_hwmod,
3066 .slave = &dra7xx_gpmc_hwmod, 3094 .slave = &dra7xx_gpmc_hwmod,
3067 .clk = "l3_iclk_div", 3095 .clk = "l3_iclk_div",
3068 .user = OCP_USER_MPU | OCP_USER_SDMA, 3096 .user = OCP_USER_MPU | OCP_USER_SDMA,
3069 }; 3097 };
3070 3098
3071 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { 3099 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3072 { 3100 {
3073 .pa_start = 0x480b2000, 3101 .pa_start = 0x480b2000,
3074 .pa_end = 0x480b201f, 3102 .pa_end = 0x480b201f,
3075 .flags = ADDR_TYPE_RT 3103 .flags = ADDR_TYPE_RT
3076 }, 3104 },
3077 { } 3105 { }
3078 }; 3106 };
3079 3107
3080 /* l4_per1 -> hdq1w */ 3108 /* l4_per1 -> hdq1w */
3081 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = { 3109 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3082 .master = &dra7xx_l4_per1_hwmod, 3110 .master = &dra7xx_l4_per1_hwmod,
3083 .slave = &dra7xx_hdq1w_hwmod, 3111 .slave = &dra7xx_hdq1w_hwmod,
3084 .clk = "l3_iclk_div", 3112 .clk = "l3_iclk_div",
3085 .addr = dra7xx_hdq1w_addrs, 3113 .addr = dra7xx_hdq1w_addrs,
3086 .user = OCP_USER_MPU | OCP_USER_SDMA, 3114 .user = OCP_USER_MPU | OCP_USER_SDMA,
3087 }; 3115 };
3088 3116
3089 /* l4_per1 -> i2c1 */ 3117 /* l4_per1 -> i2c1 */
3090 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = { 3118 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3091 .master = &dra7xx_l4_per1_hwmod, 3119 .master = &dra7xx_l4_per1_hwmod,
3092 .slave = &dra7xx_i2c1_hwmod, 3120 .slave = &dra7xx_i2c1_hwmod,
3093 .clk = "l3_iclk_div", 3121 .clk = "l3_iclk_div",
3094 .user = OCP_USER_MPU | OCP_USER_SDMA, 3122 .user = OCP_USER_MPU | OCP_USER_SDMA,
3095 }; 3123 };
3096 3124
3097 /* l4_per1 -> i2c2 */ 3125 /* l4_per1 -> i2c2 */
3098 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = { 3126 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3099 .master = &dra7xx_l4_per1_hwmod, 3127 .master = &dra7xx_l4_per1_hwmod,
3100 .slave = &dra7xx_i2c2_hwmod, 3128 .slave = &dra7xx_i2c2_hwmod,
3101 .clk = "l3_iclk_div", 3129 .clk = "l3_iclk_div",
3102 .user = OCP_USER_MPU | OCP_USER_SDMA, 3130 .user = OCP_USER_MPU | OCP_USER_SDMA,
3103 }; 3131 };
3104 3132
3105 /* l4_per1 -> i2c3 */ 3133 /* l4_per1 -> i2c3 */
3106 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = { 3134 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3107 .master = &dra7xx_l4_per1_hwmod, 3135 .master = &dra7xx_l4_per1_hwmod,
3108 .slave = &dra7xx_i2c3_hwmod, 3136 .slave = &dra7xx_i2c3_hwmod,
3109 .clk = "l3_iclk_div", 3137 .clk = "l3_iclk_div",
3110 .user = OCP_USER_MPU | OCP_USER_SDMA, 3138 .user = OCP_USER_MPU | OCP_USER_SDMA,
3111 }; 3139 };
3112 3140
3113 /* l4_per1 -> i2c4 */ 3141 /* l4_per1 -> i2c4 */
3114 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = { 3142 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3115 .master = &dra7xx_l4_per1_hwmod, 3143 .master = &dra7xx_l4_per1_hwmod,
3116 .slave = &dra7xx_i2c4_hwmod, 3144 .slave = &dra7xx_i2c4_hwmod,
3117 .clk = "l3_iclk_div", 3145 .clk = "l3_iclk_div",
3118 .user = OCP_USER_MPU | OCP_USER_SDMA, 3146 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119 }; 3147 };
3120 3148
3121 /* l4_per1 -> i2c5 */ 3149 /* l4_per1 -> i2c5 */
3122 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { 3150 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3123 .master = &dra7xx_l4_per1_hwmod, 3151 .master = &dra7xx_l4_per1_hwmod,
3124 .slave = &dra7xx_i2c5_hwmod, 3152 .slave = &dra7xx_i2c5_hwmod,
3125 .clk = "l3_iclk_div", 3153 .clk = "l3_iclk_div",
3126 .user = OCP_USER_MPU | OCP_USER_SDMA, 3154 .user = OCP_USER_MPU | OCP_USER_SDMA,
3127 }; 3155 };
3128 3156
3129 /* l4_cfg -> mailbox1 */ 3157 /* l4_cfg -> mailbox1 */
3130 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { 3158 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3131 .master = &dra7xx_l4_cfg_hwmod, 3159 .master = &dra7xx_l4_cfg_hwmod,
3132 .slave = &dra7xx_mailbox1_hwmod, 3160 .slave = &dra7xx_mailbox1_hwmod,
3133 .clk = "l3_iclk_div", 3161 .clk = "l3_iclk_div",
3134 .user = OCP_USER_MPU | OCP_USER_SDMA, 3162 .user = OCP_USER_MPU | OCP_USER_SDMA,
3135 }; 3163 };
3136 3164
3137 /* l4_per3 -> mailbox2 */ 3165 /* l4_per3 -> mailbox2 */
3138 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { 3166 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3139 .master = &dra7xx_l4_per3_hwmod, 3167 .master = &dra7xx_l4_per3_hwmod,
3140 .slave = &dra7xx_mailbox2_hwmod, 3168 .slave = &dra7xx_mailbox2_hwmod,
3141 .clk = "l3_iclk_div", 3169 .clk = "l3_iclk_div",
3142 .user = OCP_USER_MPU | OCP_USER_SDMA, 3170 .user = OCP_USER_MPU | OCP_USER_SDMA,
3143 }; 3171 };
3144 3172
3145 /* l4_per3 -> mailbox3 */ 3173 /* l4_per3 -> mailbox3 */
3146 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { 3174 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3147 .master = &dra7xx_l4_per3_hwmod, 3175 .master = &dra7xx_l4_per3_hwmod,
3148 .slave = &dra7xx_mailbox3_hwmod, 3176 .slave = &dra7xx_mailbox3_hwmod,
3149 .clk = "l3_iclk_div", 3177 .clk = "l3_iclk_div",
3150 .user = OCP_USER_MPU | OCP_USER_SDMA, 3178 .user = OCP_USER_MPU | OCP_USER_SDMA,
3151 }; 3179 };
3152 3180
3153 /* l4_per3 -> mailbox4 */ 3181 /* l4_per3 -> mailbox4 */
3154 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { 3182 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3155 .master = &dra7xx_l4_per3_hwmod, 3183 .master = &dra7xx_l4_per3_hwmod,
3156 .slave = &dra7xx_mailbox4_hwmod, 3184 .slave = &dra7xx_mailbox4_hwmod,
3157 .clk = "l3_iclk_div", 3185 .clk = "l3_iclk_div",
3158 .user = OCP_USER_MPU | OCP_USER_SDMA, 3186 .user = OCP_USER_MPU | OCP_USER_SDMA,
3159 }; 3187 };
3160 3188
3161 /* l4_per3 -> mailbox5 */ 3189 /* l4_per3 -> mailbox5 */
3162 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { 3190 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3163 .master = &dra7xx_l4_per3_hwmod, 3191 .master = &dra7xx_l4_per3_hwmod,
3164 .slave = &dra7xx_mailbox5_hwmod, 3192 .slave = &dra7xx_mailbox5_hwmod,
3165 .clk = "l3_iclk_div", 3193 .clk = "l3_iclk_div",
3166 .user = OCP_USER_MPU | OCP_USER_SDMA, 3194 .user = OCP_USER_MPU | OCP_USER_SDMA,
3167 }; 3195 };
3168 3196
3169 /* l4_per3 -> mailbox6 */ 3197 /* l4_per3 -> mailbox6 */
3170 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { 3198 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3171 .master = &dra7xx_l4_per3_hwmod, 3199 .master = &dra7xx_l4_per3_hwmod,
3172 .slave = &dra7xx_mailbox6_hwmod, 3200 .slave = &dra7xx_mailbox6_hwmod,
3173 .clk = "l3_iclk_div", 3201 .clk = "l3_iclk_div",
3174 .user = OCP_USER_MPU | OCP_USER_SDMA, 3202 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175 }; 3203 };
3176 3204
3177 /* l4_per3 -> mailbox7 */ 3205 /* l4_per3 -> mailbox7 */
3178 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { 3206 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3179 .master = &dra7xx_l4_per3_hwmod, 3207 .master = &dra7xx_l4_per3_hwmod,
3180 .slave = &dra7xx_mailbox7_hwmod, 3208 .slave = &dra7xx_mailbox7_hwmod,
3181 .clk = "l3_iclk_div", 3209 .clk = "l3_iclk_div",
3182 .user = OCP_USER_MPU | OCP_USER_SDMA, 3210 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183 }; 3211 };
3184 3212
3185 /* l4_per3 -> mailbox8 */ 3213 /* l4_per3 -> mailbox8 */
3186 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { 3214 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3187 .master = &dra7xx_l4_per3_hwmod, 3215 .master = &dra7xx_l4_per3_hwmod,
3188 .slave = &dra7xx_mailbox8_hwmod, 3216 .slave = &dra7xx_mailbox8_hwmod,
3189 .clk = "l3_iclk_div", 3217 .clk = "l3_iclk_div",
3190 .user = OCP_USER_MPU | OCP_USER_SDMA, 3218 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191 }; 3219 };
3192 3220
3193 /* l4_per3 -> mailbox9 */ 3221 /* l4_per3 -> mailbox9 */
3194 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { 3222 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3195 .master = &dra7xx_l4_per3_hwmod, 3223 .master = &dra7xx_l4_per3_hwmod,
3196 .slave = &dra7xx_mailbox9_hwmod, 3224 .slave = &dra7xx_mailbox9_hwmod,
3197 .clk = "l3_iclk_div", 3225 .clk = "l3_iclk_div",
3198 .user = OCP_USER_MPU | OCP_USER_SDMA, 3226 .user = OCP_USER_MPU | OCP_USER_SDMA,
3199 }; 3227 };
3200 3228
3201 /* l4_per3 -> mailbox10 */ 3229 /* l4_per3 -> mailbox10 */
3202 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { 3230 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3203 .master = &dra7xx_l4_per3_hwmod, 3231 .master = &dra7xx_l4_per3_hwmod,
3204 .slave = &dra7xx_mailbox10_hwmod, 3232 .slave = &dra7xx_mailbox10_hwmod,
3205 .clk = "l3_iclk_div", 3233 .clk = "l3_iclk_div",
3206 .user = OCP_USER_MPU | OCP_USER_SDMA, 3234 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207 }; 3235 };
3208 3236
3209 /* l4_per3 -> mailbox11 */ 3237 /* l4_per3 -> mailbox11 */
3210 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { 3238 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3211 .master = &dra7xx_l4_per3_hwmod, 3239 .master = &dra7xx_l4_per3_hwmod,
3212 .slave = &dra7xx_mailbox11_hwmod, 3240 .slave = &dra7xx_mailbox11_hwmod,
3213 .clk = "l3_iclk_div", 3241 .clk = "l3_iclk_div",
3214 .user = OCP_USER_MPU | OCP_USER_SDMA, 3242 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215 }; 3243 };
3216 3244
3217 /* l4_per3 -> mailbox12 */ 3245 /* l4_per3 -> mailbox12 */
3218 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { 3246 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3219 .master = &dra7xx_l4_per3_hwmod, 3247 .master = &dra7xx_l4_per3_hwmod,
3220 .slave = &dra7xx_mailbox12_hwmod, 3248 .slave = &dra7xx_mailbox12_hwmod,
3221 .clk = "l3_iclk_div", 3249 .clk = "l3_iclk_div",
3222 .user = OCP_USER_MPU | OCP_USER_SDMA, 3250 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223 }; 3251 };
3224 3252
3225 /* l4_per3 -> mailbox13 */ 3253 /* l4_per3 -> mailbox13 */
3226 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { 3254 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3227 .master = &dra7xx_l4_per3_hwmod, 3255 .master = &dra7xx_l4_per3_hwmod,
3228 .slave = &dra7xx_mailbox13_hwmod, 3256 .slave = &dra7xx_mailbox13_hwmod,
3229 .clk = "l3_iclk_div", 3257 .clk = "l3_iclk_div",
3230 .user = OCP_USER_MPU | OCP_USER_SDMA, 3258 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231 }; 3259 };
3232 3260
3233 /* l4_per1 -> mcspi1 */ 3261 /* l4_per1 -> mcspi1 */
3234 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { 3262 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3235 .master = &dra7xx_l4_per1_hwmod, 3263 .master = &dra7xx_l4_per1_hwmod,
3236 .slave = &dra7xx_mcspi1_hwmod, 3264 .slave = &dra7xx_mcspi1_hwmod,
3237 .clk = "l3_iclk_div", 3265 .clk = "l3_iclk_div",
3238 .user = OCP_USER_MPU | OCP_USER_SDMA, 3266 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239 }; 3267 };
3240 3268
3241 /* l4_per1 -> mcspi2 */ 3269 /* l4_per1 -> mcspi2 */
3242 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = { 3270 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3243 .master = &dra7xx_l4_per1_hwmod, 3271 .master = &dra7xx_l4_per1_hwmod,
3244 .slave = &dra7xx_mcspi2_hwmod, 3272 .slave = &dra7xx_mcspi2_hwmod,
3245 .clk = "l3_iclk_div", 3273 .clk = "l3_iclk_div",
3246 .user = OCP_USER_MPU | OCP_USER_SDMA, 3274 .user = OCP_USER_MPU | OCP_USER_SDMA,
3247 }; 3275 };
3248 3276
3249 /* l4_per1 -> mcspi3 */ 3277 /* l4_per1 -> mcspi3 */
3250 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = { 3278 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3251 .master = &dra7xx_l4_per1_hwmod, 3279 .master = &dra7xx_l4_per1_hwmod,
3252 .slave = &dra7xx_mcspi3_hwmod, 3280 .slave = &dra7xx_mcspi3_hwmod,
3253 .clk = "l3_iclk_div", 3281 .clk = "l3_iclk_div",
3254 .user = OCP_USER_MPU | OCP_USER_SDMA, 3282 .user = OCP_USER_MPU | OCP_USER_SDMA,
3255 }; 3283 };
3256 3284
3257 /* l4_per1 -> mcspi4 */ 3285 /* l4_per1 -> mcspi4 */
3258 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = { 3286 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3259 .master = &dra7xx_l4_per1_hwmod, 3287 .master = &dra7xx_l4_per1_hwmod,
3260 .slave = &dra7xx_mcspi4_hwmod, 3288 .slave = &dra7xx_mcspi4_hwmod,
3261 .clk = "l3_iclk_div", 3289 .clk = "l3_iclk_div",
3262 .user = OCP_USER_MPU | OCP_USER_SDMA, 3290 .user = OCP_USER_MPU | OCP_USER_SDMA,
3263 }; 3291 };
3264 3292
3265 /* l4_per1 -> mmc1 */ 3293 /* l4_per1 -> mmc1 */
3266 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = { 3294 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3267 .master = &dra7xx_l4_per1_hwmod, 3295 .master = &dra7xx_l4_per1_hwmod,
3268 .slave = &dra7xx_mmc1_hwmod, 3296 .slave = &dra7xx_mmc1_hwmod,
3269 .clk = "l3_iclk_div", 3297 .clk = "l3_iclk_div",
3270 .user = OCP_USER_MPU | OCP_USER_SDMA, 3298 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271 }; 3299 };
3272 3300
3273 /* l4_per1 -> mmc2 */ 3301 /* l4_per1 -> mmc2 */
3274 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = { 3302 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3275 .master = &dra7xx_l4_per1_hwmod, 3303 .master = &dra7xx_l4_per1_hwmod,
3276 .slave = &dra7xx_mmc2_hwmod, 3304 .slave = &dra7xx_mmc2_hwmod,
3277 .clk = "l3_iclk_div", 3305 .clk = "l3_iclk_div",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA, 3306 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279 }; 3307 };
3280 3308
3281 /* l4_per1 -> mmc3 */ 3309 /* l4_per1 -> mmc3 */
3282 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = { 3310 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3283 .master = &dra7xx_l4_per1_hwmod, 3311 .master = &dra7xx_l4_per1_hwmod,
3284 .slave = &dra7xx_mmc3_hwmod, 3312 .slave = &dra7xx_mmc3_hwmod,
3285 .clk = "l3_iclk_div", 3313 .clk = "l3_iclk_div",
3286 .user = OCP_USER_MPU | OCP_USER_SDMA, 3314 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287 }; 3315 };
3288 3316
3289 /* l4_per1 -> mmc4 */ 3317 /* l4_per1 -> mmc4 */
3290 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = { 3318 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3291 .master = &dra7xx_l4_per1_hwmod, 3319 .master = &dra7xx_l4_per1_hwmod,
3292 .slave = &dra7xx_mmc4_hwmod, 3320 .slave = &dra7xx_mmc4_hwmod,
3293 .clk = "l3_iclk_div", 3321 .clk = "l3_iclk_div",
3294 .user = OCP_USER_MPU | OCP_USER_SDMA, 3322 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295 }; 3323 };
3296 3324
3297 /* l4_cfg -> mpu */ 3325 /* l4_cfg -> mpu */
3298 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { 3326 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3299 .master = &dra7xx_l4_cfg_hwmod, 3327 .master = &dra7xx_l4_cfg_hwmod,
3300 .slave = &dra7xx_mpu_hwmod, 3328 .slave = &dra7xx_mpu_hwmod,
3301 .clk = "l3_iclk_div", 3329 .clk = "l3_iclk_div",
3302 .user = OCP_USER_MPU | OCP_USER_SDMA, 3330 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303 }; 3331 };
3304 3332
3305 /* l4_cfg -> ocp2scp1 */ 3333 /* l4_cfg -> ocp2scp1 */
3306 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { 3334 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3307 .master = &dra7xx_l4_cfg_hwmod, 3335 .master = &dra7xx_l4_cfg_hwmod,
3308 .slave = &dra7xx_ocp2scp1_hwmod, 3336 .slave = &dra7xx_ocp2scp1_hwmod,
3309 .clk = "l4_root_clk_div", 3337 .clk = "l4_root_clk_div",
3310 .user = OCP_USER_MPU | OCP_USER_SDMA, 3338 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311 }; 3339 };
3312 3340
3313 /* l4_cfg -> ocp2scp3 */ 3341 /* l4_cfg -> ocp2scp3 */
3314 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { 3342 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3315 .master = &dra7xx_l4_cfg_hwmod, 3343 .master = &dra7xx_l4_cfg_hwmod,
3316 .slave = &dra7xx_ocp2scp3_hwmod, 3344 .slave = &dra7xx_ocp2scp3_hwmod,
3317 .clk = "l4_root_clk_div", 3345 .clk = "l4_root_clk_div",
3318 .user = OCP_USER_MPU | OCP_USER_SDMA, 3346 .user = OCP_USER_MPU | OCP_USER_SDMA,
3319 }; 3347 };
3320 3348
3321 /* l3_main_1 -> pciess1 */ 3349 /* l3_main_1 -> pciess1 */
3322 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = { 3350 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3323 .master = &dra7xx_l3_main_1_hwmod, 3351 .master = &dra7xx_l3_main_1_hwmod,
3324 .slave = &dra7xx_pciess1_hwmod, 3352 .slave = &dra7xx_pciess1_hwmod,
3325 .clk = "l3_iclk_div", 3353 .clk = "l3_iclk_div",
3326 .user = OCP_USER_MPU | OCP_USER_SDMA, 3354 .user = OCP_USER_MPU | OCP_USER_SDMA,
3327 }; 3355 };
3328 3356
3329 /* l4_cfg -> pciess1 */ 3357 /* l4_cfg -> pciess1 */
3330 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = { 3358 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3331 .master = &dra7xx_l4_cfg_hwmod, 3359 .master = &dra7xx_l4_cfg_hwmod,
3332 .slave = &dra7xx_pciess1_hwmod, 3360 .slave = &dra7xx_pciess1_hwmod,
3333 .clk = "l4_root_clk_div", 3361 .clk = "l4_root_clk_div",
3334 .user = OCP_USER_MPU | OCP_USER_SDMA, 3362 .user = OCP_USER_MPU | OCP_USER_SDMA,
3335 }; 3363 };
3336 3364
3337 /* l3_main_1 -> pciess2 */ 3365 /* l3_main_1 -> pciess2 */
3338 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = { 3366 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3339 .master = &dra7xx_l3_main_1_hwmod, 3367 .master = &dra7xx_l3_main_1_hwmod,
3340 .slave = &dra7xx_pciess2_hwmod, 3368 .slave = &dra7xx_pciess2_hwmod,
3341 .clk = "l3_iclk_div", 3369 .clk = "l3_iclk_div",
3342 .user = OCP_USER_MPU | OCP_USER_SDMA, 3370 .user = OCP_USER_MPU | OCP_USER_SDMA,
3343 }; 3371 };
3344 3372
3345 /* l4_cfg -> pciess2 */ 3373 /* l4_cfg -> pciess2 */
3346 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = { 3374 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3347 .master = &dra7xx_l4_cfg_hwmod, 3375 .master = &dra7xx_l4_cfg_hwmod,
3348 .slave = &dra7xx_pciess2_hwmod, 3376 .slave = &dra7xx_pciess2_hwmod,
3349 .clk = "l4_root_clk_div", 3377 .clk = "l4_root_clk_div",
3350 .user = OCP_USER_MPU | OCP_USER_SDMA, 3378 .user = OCP_USER_MPU | OCP_USER_SDMA,
3351 }; 3379 };
3352 3380
3353 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { 3381 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3354 { 3382 {
3355 .pa_start = 0x4b300000, 3383 .pa_start = 0x4b300000,
3356 .pa_end = 0x4b30007f, 3384 .pa_end = 0x4b30007f,
3357 .flags = ADDR_TYPE_RT 3385 .flags = ADDR_TYPE_RT
3358 }, 3386 },
3359 { } 3387 { }
3360 }; 3388 };
3361 3389
3362 /* l3_main_1 -> qspi */ 3390 /* l3_main_1 -> qspi */
3363 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { 3391 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3364 .master = &dra7xx_l3_main_1_hwmod, 3392 .master = &dra7xx_l3_main_1_hwmod,
3365 .slave = &dra7xx_qspi_hwmod, 3393 .slave = &dra7xx_qspi_hwmod,
3366 .clk = "l3_iclk_div", 3394 .clk = "l3_iclk_div",
3367 .addr = dra7xx_qspi_addrs, 3395 .addr = dra7xx_qspi_addrs,
3368 .user = OCP_USER_MPU | OCP_USER_SDMA, 3396 .user = OCP_USER_MPU | OCP_USER_SDMA,
3369 }; 3397 };
3370 3398
3371 /* l4_per3 -> rtcss */ 3399 /* l4_per3 -> rtcss */
3372 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { 3400 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3373 .master = &dra7xx_l4_per3_hwmod, 3401 .master = &dra7xx_l4_per3_hwmod,
3374 .slave = &dra7xx_rtcss_hwmod, 3402 .slave = &dra7xx_rtcss_hwmod,
3375 .clk = "l4_root_clk_div", 3403 .clk = "l4_root_clk_div",
3376 .user = OCP_USER_MPU | OCP_USER_SDMA, 3404 .user = OCP_USER_MPU | OCP_USER_SDMA,
3377 }; 3405 };
3378 3406
3379 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { 3407 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3380 { 3408 {
3381 .name = "sysc", 3409 .name = "sysc",
3382 .pa_start = 0x4a141100, 3410 .pa_start = 0x4a141100,
3383 .pa_end = 0x4a141107, 3411 .pa_end = 0x4a141107,
3384 .flags = ADDR_TYPE_RT 3412 .flags = ADDR_TYPE_RT
3385 }, 3413 },
3386 { } 3414 { }
3387 }; 3415 };
3388 3416
3389 /* l4_cfg -> sata */ 3417 /* l4_cfg -> sata */
3390 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { 3418 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3391 .master = &dra7xx_l4_cfg_hwmod, 3419 .master = &dra7xx_l4_cfg_hwmod,
3392 .slave = &dra7xx_sata_hwmod, 3420 .slave = &dra7xx_sata_hwmod,
3393 .clk = "l3_iclk_div", 3421 .clk = "l3_iclk_div",
3394 .addr = dra7xx_sata_addrs, 3422 .addr = dra7xx_sata_addrs,
3395 .user = OCP_USER_MPU | OCP_USER_SDMA, 3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3396 }; 3424 };
3397 3425
3398 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = { 3426 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3399 { 3427 {
3400 .pa_start = 0x4a0dd000, 3428 .pa_start = 0x4a0dd000,
3401 .pa_end = 0x4a0dd07f, 3429 .pa_end = 0x4a0dd07f,
3402 .flags = ADDR_TYPE_RT 3430 .flags = ADDR_TYPE_RT
3403 }, 3431 },
3404 { } 3432 { }
3405 }; 3433 };
3406 3434
3407 /* l4_cfg -> smartreflex_core */ 3435 /* l4_cfg -> smartreflex_core */
3408 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = { 3436 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3409 .master = &dra7xx_l4_cfg_hwmod, 3437 .master = &dra7xx_l4_cfg_hwmod,
3410 .slave = &dra7xx_smartreflex_core_hwmod, 3438 .slave = &dra7xx_smartreflex_core_hwmod,
3411 .clk = "l4_root_clk_div", 3439 .clk = "l4_root_clk_div",
3412 .addr = dra7xx_smartreflex_core_addrs, 3440 .addr = dra7xx_smartreflex_core_addrs,
3413 .user = OCP_USER_MPU | OCP_USER_SDMA, 3441 .user = OCP_USER_MPU | OCP_USER_SDMA,
3414 }; 3442 };
3415 3443
3416 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = { 3444 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3417 { 3445 {
3418 .pa_start = 0x4a0d9000, 3446 .pa_start = 0x4a0d9000,
3419 .pa_end = 0x4a0d907f, 3447 .pa_end = 0x4a0d907f,
3420 .flags = ADDR_TYPE_RT 3448 .flags = ADDR_TYPE_RT
3421 }, 3449 },
3422 { } 3450 { }
3423 }; 3451 };
3424 3452
3425 /* l4_cfg -> smartreflex_mpu */ 3453 /* l4_cfg -> smartreflex_mpu */
3426 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = { 3454 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3427 .master = &dra7xx_l4_cfg_hwmod, 3455 .master = &dra7xx_l4_cfg_hwmod,
3428 .slave = &dra7xx_smartreflex_mpu_hwmod, 3456 .slave = &dra7xx_smartreflex_mpu_hwmod,
3429 .clk = "l4_root_clk_div", 3457 .clk = "l4_root_clk_div",
3430 .addr = dra7xx_smartreflex_mpu_addrs, 3458 .addr = dra7xx_smartreflex_mpu_addrs,
3431 .user = OCP_USER_MPU | OCP_USER_SDMA, 3459 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 }; 3460 };
3433 3461
3434 /* l4_cfg -> spinlock */ 3462 /* l4_cfg -> spinlock */
3435 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = { 3463 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3436 .master = &dra7xx_l4_cfg_hwmod, 3464 .master = &dra7xx_l4_cfg_hwmod,
3437 .slave = &dra7xx_spinlock_hwmod, 3465 .slave = &dra7xx_spinlock_hwmod,
3438 .clk = "l3_iclk_div", 3466 .clk = "l3_iclk_div",
3439 .user = OCP_USER_MPU | OCP_USER_SDMA, 3467 .user = OCP_USER_MPU | OCP_USER_SDMA,
3440 }; 3468 };
3441 3469
3442 /* l4_wkup -> timer1 */ 3470 /* l4_wkup -> timer1 */
3443 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { 3471 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3444 .master = &dra7xx_l4_wkup_hwmod, 3472 .master = &dra7xx_l4_wkup_hwmod,
3445 .slave = &dra7xx_timer1_hwmod, 3473 .slave = &dra7xx_timer1_hwmod,
3446 .clk = "wkupaon_iclk_mux", 3474 .clk = "wkupaon_iclk_mux",
3447 .user = OCP_USER_MPU | OCP_USER_SDMA, 3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3448 }; 3476 };
3449 3477
3450 /* l4_per1 -> timer2 */ 3478 /* l4_per1 -> timer2 */
3451 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = { 3479 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3452 .master = &dra7xx_l4_per1_hwmod, 3480 .master = &dra7xx_l4_per1_hwmod,
3453 .slave = &dra7xx_timer2_hwmod, 3481 .slave = &dra7xx_timer2_hwmod,
3454 .clk = "l3_iclk_div", 3482 .clk = "l3_iclk_div",
3455 .user = OCP_USER_MPU | OCP_USER_SDMA, 3483 .user = OCP_USER_MPU | OCP_USER_SDMA,
3456 }; 3484 };
3457 3485
3458 /* l4_per1 -> timer3 */ 3486 /* l4_per1 -> timer3 */
3459 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = { 3487 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3460 .master = &dra7xx_l4_per1_hwmod, 3488 .master = &dra7xx_l4_per1_hwmod,
3461 .slave = &dra7xx_timer3_hwmod, 3489 .slave = &dra7xx_timer3_hwmod,
3462 .clk = "l3_iclk_div", 3490 .clk = "l3_iclk_div",
3463 .user = OCP_USER_MPU | OCP_USER_SDMA, 3491 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464 }; 3492 };
3465 3493
3466 /* l4_per1 -> timer4 */ 3494 /* l4_per1 -> timer4 */
3467 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { 3495 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3468 .master = &dra7xx_l4_per1_hwmod, 3496 .master = &dra7xx_l4_per1_hwmod,
3469 .slave = &dra7xx_timer4_hwmod, 3497 .slave = &dra7xx_timer4_hwmod,
3470 .clk = "l3_iclk_div", 3498 .clk = "l3_iclk_div",
3471 .user = OCP_USER_MPU | OCP_USER_SDMA, 3499 .user = OCP_USER_MPU | OCP_USER_SDMA,
3472 }; 3500 };
3473 3501
3474 /* l4_per3 -> timer5 */ 3502 /* l4_per3 -> timer5 */
3475 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = { 3503 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3476 .master = &dra7xx_l4_per3_hwmod, 3504 .master = &dra7xx_l4_per3_hwmod,
3477 .slave = &dra7xx_timer5_hwmod, 3505 .slave = &dra7xx_timer5_hwmod,
3478 .clk = "l3_iclk_div", 3506 .clk = "l3_iclk_div",
3479 .user = OCP_USER_MPU | OCP_USER_SDMA, 3507 .user = OCP_USER_MPU | OCP_USER_SDMA,
3480 }; 3508 };
3481 3509
3482 /* l4_per3 -> timer6 */ 3510 /* l4_per3 -> timer6 */
3483 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = { 3511 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3484 .master = &dra7xx_l4_per3_hwmod, 3512 .master = &dra7xx_l4_per3_hwmod,
3485 .slave = &dra7xx_timer6_hwmod, 3513 .slave = &dra7xx_timer6_hwmod,
3486 .clk = "l3_iclk_div", 3514 .clk = "l3_iclk_div",
3487 .user = OCP_USER_MPU | OCP_USER_SDMA, 3515 .user = OCP_USER_MPU | OCP_USER_SDMA,
3488 }; 3516 };
3489 3517
3490 /* l4_per3 -> timer7 */ 3518 /* l4_per3 -> timer7 */
3491 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = { 3519 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3492 .master = &dra7xx_l4_per3_hwmod, 3520 .master = &dra7xx_l4_per3_hwmod,
3493 .slave = &dra7xx_timer7_hwmod, 3521 .slave = &dra7xx_timer7_hwmod,
3494 .clk = "l3_iclk_div", 3522 .clk = "l3_iclk_div",
3495 .user = OCP_USER_MPU | OCP_USER_SDMA, 3523 .user = OCP_USER_MPU | OCP_USER_SDMA,
3496 }; 3524 };
3497 3525
3498 /* l4_per3 -> timer8 */ 3526 /* l4_per3 -> timer8 */
3499 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = { 3527 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3500 .master = &dra7xx_l4_per3_hwmod, 3528 .master = &dra7xx_l4_per3_hwmod,
3501 .slave = &dra7xx_timer8_hwmod, 3529 .slave = &dra7xx_timer8_hwmod,
3502 .clk = "l3_iclk_div", 3530 .clk = "l3_iclk_div",
3503 .user = OCP_USER_MPU | OCP_USER_SDMA, 3531 .user = OCP_USER_MPU | OCP_USER_SDMA,
3504 }; 3532 };
3505 3533
3506 /* l4_per1 -> timer9 */ 3534 /* l4_per1 -> timer9 */
3507 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = { 3535 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3508 .master = &dra7xx_l4_per1_hwmod, 3536 .master = &dra7xx_l4_per1_hwmod,
3509 .slave = &dra7xx_timer9_hwmod, 3537 .slave = &dra7xx_timer9_hwmod,
3510 .clk = "l3_iclk_div", 3538 .clk = "l3_iclk_div",
3511 .user = OCP_USER_MPU | OCP_USER_SDMA, 3539 .user = OCP_USER_MPU | OCP_USER_SDMA,
3512 }; 3540 };
3513 3541
3514 /* l4_per1 -> timer10 */ 3542 /* l4_per1 -> timer10 */
3515 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = { 3543 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3516 .master = &dra7xx_l4_per1_hwmod, 3544 .master = &dra7xx_l4_per1_hwmod,
3517 .slave = &dra7xx_timer10_hwmod, 3545 .slave = &dra7xx_timer10_hwmod,
3518 .clk = "l3_iclk_div", 3546 .clk = "l3_iclk_div",
3519 .user = OCP_USER_MPU | OCP_USER_SDMA, 3547 .user = OCP_USER_MPU | OCP_USER_SDMA,
3520 }; 3548 };
3521 3549
3522 /* l4_per1 -> timer11 */ 3550 /* l4_per1 -> timer11 */
3523 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { 3551 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3524 .master = &dra7xx_l4_per1_hwmod, 3552 .master = &dra7xx_l4_per1_hwmod,
3525 .slave = &dra7xx_timer11_hwmod, 3553 .slave = &dra7xx_timer11_hwmod,
3526 .clk = "l3_iclk_div", 3554 .clk = "l3_iclk_div",
3527 .user = OCP_USER_MPU | OCP_USER_SDMA, 3555 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528 }; 3556 };
3529 3557
3530 /* l4_wkup -> timer12 */ 3558 /* l4_wkup -> timer12 */
3531 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { 3559 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3532 .master = &dra7xx_l4_wkup_hwmod, 3560 .master = &dra7xx_l4_wkup_hwmod,
3533 .slave = &dra7xx_timer12_hwmod, 3561 .slave = &dra7xx_timer12_hwmod,
3534 .clk = "wkupaon_iclk_mux", 3562 .clk = "wkupaon_iclk_mux",
3535 .user = OCP_USER_MPU | OCP_USER_SDMA, 3563 .user = OCP_USER_MPU | OCP_USER_SDMA,
3536 }; 3564 };
3537 3565
3538 /* l4_per3 -> timer13 */ 3566 /* l4_per3 -> timer13 */
3539 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { 3567 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3540 .master = &dra7xx_l4_per3_hwmod, 3568 .master = &dra7xx_l4_per3_hwmod,
3541 .slave = &dra7xx_timer13_hwmod, 3569 .slave = &dra7xx_timer13_hwmod,
3542 .clk = "l3_iclk_div", 3570 .clk = "l3_iclk_div",
3543 .user = OCP_USER_MPU | OCP_USER_SDMA, 3571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3544 }; 3572 };
3545 3573
3546 /* l4_per3 -> timer14 */ 3574 /* l4_per3 -> timer14 */
3547 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = { 3575 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3548 .master = &dra7xx_l4_per3_hwmod, 3576 .master = &dra7xx_l4_per3_hwmod,
3549 .slave = &dra7xx_timer14_hwmod, 3577 .slave = &dra7xx_timer14_hwmod,
3550 .clk = "l3_iclk_div", 3578 .clk = "l3_iclk_div",
3551 .user = OCP_USER_MPU | OCP_USER_SDMA, 3579 .user = OCP_USER_MPU | OCP_USER_SDMA,
3552 }; 3580 };
3553 3581
3554 /* l4_per3 -> timer15 */ 3582 /* l4_per3 -> timer15 */
3555 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = { 3583 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3556 .master = &dra7xx_l4_per3_hwmod, 3584 .master = &dra7xx_l4_per3_hwmod,
3557 .slave = &dra7xx_timer15_hwmod, 3585 .slave = &dra7xx_timer15_hwmod,
3558 .clk = "l3_iclk_div", 3586 .clk = "l3_iclk_div",
3559 .user = OCP_USER_MPU | OCP_USER_SDMA, 3587 .user = OCP_USER_MPU | OCP_USER_SDMA,
3560 }; 3588 };
3561 3589
3562 /* l4_per3 -> timer16 */ 3590 /* l4_per3 -> timer16 */
3563 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = { 3591 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3564 .master = &dra7xx_l4_per3_hwmod, 3592 .master = &dra7xx_l4_per3_hwmod,
3565 .slave = &dra7xx_timer16_hwmod, 3593 .slave = &dra7xx_timer16_hwmod,
3566 .clk = "l3_iclk_div", 3594 .clk = "l3_iclk_div",
3567 .user = OCP_USER_MPU | OCP_USER_SDMA, 3595 .user = OCP_USER_MPU | OCP_USER_SDMA,
3568 }; 3596 };
3569 3597
3570 /* l4_per1 -> uart1 */ 3598 /* l4_per1 -> uart1 */
3571 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = { 3599 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3572 .master = &dra7xx_l4_per1_hwmod, 3600 .master = &dra7xx_l4_per1_hwmod,
3573 .slave = &dra7xx_uart1_hwmod, 3601 .slave = &dra7xx_uart1_hwmod,
3574 .clk = "l3_iclk_div", 3602 .clk = "l3_iclk_div",
3575 .user = OCP_USER_MPU | OCP_USER_SDMA, 3603 .user = OCP_USER_MPU | OCP_USER_SDMA,
3576 }; 3604 };
3577 3605
3578 /* l4_per1 -> uart2 */ 3606 /* l4_per1 -> uart2 */
3579 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = { 3607 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3580 .master = &dra7xx_l4_per1_hwmod, 3608 .master = &dra7xx_l4_per1_hwmod,
3581 .slave = &dra7xx_uart2_hwmod, 3609 .slave = &dra7xx_uart2_hwmod,
3582 .clk = "l3_iclk_div", 3610 .clk = "l3_iclk_div",
3583 .user = OCP_USER_MPU | OCP_USER_SDMA, 3611 .user = OCP_USER_MPU | OCP_USER_SDMA,
3584 }; 3612 };
3585 3613
3586 /* l4_per1 -> uart3 */ 3614 /* l4_per1 -> uart3 */
3587 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = { 3615 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3588 .master = &dra7xx_l4_per1_hwmod, 3616 .master = &dra7xx_l4_per1_hwmod,
3589 .slave = &dra7xx_uart3_hwmod, 3617 .slave = &dra7xx_uart3_hwmod,
3590 .clk = "l3_iclk_div", 3618 .clk = "l3_iclk_div",
3591 .user = OCP_USER_MPU | OCP_USER_SDMA, 3619 .user = OCP_USER_MPU | OCP_USER_SDMA,
3592 }; 3620 };
3593 3621
3594 /* l4_per1 -> uart4 */ 3622 /* l4_per1 -> uart4 */
3595 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = { 3623 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3596 .master = &dra7xx_l4_per1_hwmod, 3624 .master = &dra7xx_l4_per1_hwmod,
3597 .slave = &dra7xx_uart4_hwmod, 3625 .slave = &dra7xx_uart4_hwmod,
3598 .clk = "l3_iclk_div", 3626 .clk = "l3_iclk_div",
3599 .user = OCP_USER_MPU | OCP_USER_SDMA, 3627 .user = OCP_USER_MPU | OCP_USER_SDMA,
3600 }; 3628 };
3601 3629
3602 /* l4_per1 -> uart5 */ 3630 /* l4_per1 -> uart5 */
3603 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = { 3631 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3604 .master = &dra7xx_l4_per1_hwmod, 3632 .master = &dra7xx_l4_per1_hwmod,
3605 .slave = &dra7xx_uart5_hwmod, 3633 .slave = &dra7xx_uart5_hwmod,
3606 .clk = "l3_iclk_div", 3634 .clk = "l3_iclk_div",
3607 .user = OCP_USER_MPU | OCP_USER_SDMA, 3635 .user = OCP_USER_MPU | OCP_USER_SDMA,
3608 }; 3636 };
3609 3637
3610 /* l4_per1 -> uart6 */ 3638 /* l4_per1 -> uart6 */
3611 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = { 3639 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3612 .master = &dra7xx_l4_per1_hwmod, 3640 .master = &dra7xx_l4_per1_hwmod,
3613 .slave = &dra7xx_uart6_hwmod, 3641 .slave = &dra7xx_uart6_hwmod,
3614 .clk = "l3_iclk_div", 3642 .clk = "l3_iclk_div",
3615 .user = OCP_USER_MPU | OCP_USER_SDMA, 3643 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616 }; 3644 };
3617 3645
3618 /* l4_per2 -> uart7 */ 3646 /* l4_per2 -> uart7 */
3619 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = { 3647 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3620 .master = &dra7xx_l4_per2_hwmod, 3648 .master = &dra7xx_l4_per2_hwmod,
3621 .slave = &dra7xx_uart7_hwmod, 3649 .slave = &dra7xx_uart7_hwmod,
3622 .clk = "l3_iclk_div", 3650 .clk = "l3_iclk_div",
3623 .user = OCP_USER_MPU | OCP_USER_SDMA, 3651 .user = OCP_USER_MPU | OCP_USER_SDMA,
3624 }; 3652 };
3625 3653
3654 /* l4_per1 -> des */
3655 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3656 .master = &dra7xx_l4_per1_hwmod,
3657 .slave = &dra7xx_des_hwmod,
3658 .clk = "l3_iclk_div",
3659 .user = OCP_USER_MPU | OCP_USER_SDMA,
3660 };
3661
3626 /* l4_per2 -> uart8 */ 3662 /* l4_per2 -> uart8 */
3627 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = { 3663 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3628 .master = &dra7xx_l4_per2_hwmod, 3664 .master = &dra7xx_l4_per2_hwmod,
3629 .slave = &dra7xx_uart8_hwmod, 3665 .slave = &dra7xx_uart8_hwmod,
3630 .clk = "l3_iclk_div", 3666 .clk = "l3_iclk_div",
3631 .user = OCP_USER_MPU | OCP_USER_SDMA, 3667 .user = OCP_USER_MPU | OCP_USER_SDMA,
3632 }; 3668 };
3633 3669
3634 /* l4_per2 -> uart9 */ 3670 /* l4_per2 -> uart9 */
3635 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = { 3671 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3636 .master = &dra7xx_l4_per2_hwmod, 3672 .master = &dra7xx_l4_per2_hwmod,
3637 .slave = &dra7xx_uart9_hwmod, 3673 .slave = &dra7xx_uart9_hwmod,
3638 .clk = "l3_iclk_div", 3674 .clk = "l3_iclk_div",
3639 .user = OCP_USER_MPU | OCP_USER_SDMA, 3675 .user = OCP_USER_MPU | OCP_USER_SDMA,
3640 }; 3676 };
3641 3677
3642 /* l4_wkup -> uart10 */ 3678 /* l4_wkup -> uart10 */
3643 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = { 3679 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3644 .master = &dra7xx_l4_wkup_hwmod, 3680 .master = &dra7xx_l4_wkup_hwmod,
3645 .slave = &dra7xx_uart10_hwmod, 3681 .slave = &dra7xx_uart10_hwmod,
3646 .clk = "wkupaon_iclk_mux", 3682 .clk = "wkupaon_iclk_mux",
3647 .user = OCP_USER_MPU | OCP_USER_SDMA, 3683 .user = OCP_USER_MPU | OCP_USER_SDMA,
3648 }; 3684 };
3649 3685
3650 /* l4_per3 -> usb_otg_ss1 */ 3686 /* l4_per3 -> usb_otg_ss1 */
3651 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { 3687 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3652 .master = &dra7xx_l4_per3_hwmod, 3688 .master = &dra7xx_l4_per3_hwmod,
3653 .slave = &dra7xx_usb_otg_ss1_hwmod, 3689 .slave = &dra7xx_usb_otg_ss1_hwmod,
3654 .clk = "dpll_core_h13x2_ck", 3690 .clk = "dpll_core_h13x2_ck",
3655 .user = OCP_USER_MPU | OCP_USER_SDMA, 3691 .user = OCP_USER_MPU | OCP_USER_SDMA,
3656 }; 3692 };
3657 3693
3658 /* l4_per3 -> usb_otg_ss2 */ 3694 /* l4_per3 -> usb_otg_ss2 */
3659 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = { 3695 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3660 .master = &dra7xx_l4_per3_hwmod, 3696 .master = &dra7xx_l4_per3_hwmod,
3661 .slave = &dra7xx_usb_otg_ss2_hwmod, 3697 .slave = &dra7xx_usb_otg_ss2_hwmod,
3662 .clk = "dpll_core_h13x2_ck", 3698 .clk = "dpll_core_h13x2_ck",
3663 .user = OCP_USER_MPU | OCP_USER_SDMA, 3699 .user = OCP_USER_MPU | OCP_USER_SDMA,
3664 }; 3700 };
3665 3701
3666 /* l4_per3 -> usb_otg_ss3 */ 3702 /* l4_per3 -> usb_otg_ss3 */
3667 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = { 3703 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3668 .master = &dra7xx_l4_per3_hwmod, 3704 .master = &dra7xx_l4_per3_hwmod,
3669 .slave = &dra7xx_usb_otg_ss3_hwmod, 3705 .slave = &dra7xx_usb_otg_ss3_hwmod,
3670 .clk = "dpll_core_h13x2_ck", 3706 .clk = "dpll_core_h13x2_ck",
3671 .user = OCP_USER_MPU | OCP_USER_SDMA, 3707 .user = OCP_USER_MPU | OCP_USER_SDMA,
3672 }; 3708 };
3673 3709
3674 /* l4_per3 -> usb_otg_ss4 */ 3710 /* l4_per3 -> usb_otg_ss4 */
3675 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = { 3711 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3676 .master = &dra7xx_l4_per3_hwmod, 3712 .master = &dra7xx_l4_per3_hwmod,
3677 .slave = &dra7xx_usb_otg_ss4_hwmod, 3713 .slave = &dra7xx_usb_otg_ss4_hwmod,
3678 .clk = "dpll_core_h13x2_ck", 3714 .clk = "dpll_core_h13x2_ck",
3679 .user = OCP_USER_MPU | OCP_USER_SDMA, 3715 .user = OCP_USER_MPU | OCP_USER_SDMA,
3680 }; 3716 };
3681 3717
3682 /* l3_main_1 -> vcp1 */ 3718 /* l3_main_1 -> vcp1 */
3683 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { 3719 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3684 .master = &dra7xx_l3_main_1_hwmod, 3720 .master = &dra7xx_l3_main_1_hwmod,
3685 .slave = &dra7xx_vcp1_hwmod, 3721 .slave = &dra7xx_vcp1_hwmod,
3686 .clk = "l3_iclk_div", 3722 .clk = "l3_iclk_div",
3687 .user = OCP_USER_MPU | OCP_USER_SDMA, 3723 .user = OCP_USER_MPU | OCP_USER_SDMA,
3688 }; 3724 };
3689 3725
3690 /* l4_per2 -> vcp1 */ 3726 /* l4_per2 -> vcp1 */
3691 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { 3727 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3692 .master = &dra7xx_l4_per2_hwmod, 3728 .master = &dra7xx_l4_per2_hwmod,
3693 .slave = &dra7xx_vcp1_hwmod, 3729 .slave = &dra7xx_vcp1_hwmod,
3694 .clk = "l3_iclk_div", 3730 .clk = "l3_iclk_div",
3695 .user = OCP_USER_MPU | OCP_USER_SDMA, 3731 .user = OCP_USER_MPU | OCP_USER_SDMA,
3696 }; 3732 };
3697 3733
3698 /* l3_main_1 -> vcp2 */ 3734 /* l3_main_1 -> vcp2 */
3699 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { 3735 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3700 .master = &dra7xx_l3_main_1_hwmod, 3736 .master = &dra7xx_l3_main_1_hwmod,
3701 .slave = &dra7xx_vcp2_hwmod, 3737 .slave = &dra7xx_vcp2_hwmod,
3702 .clk = "l3_iclk_div", 3738 .clk = "l3_iclk_div",
3703 .user = OCP_USER_MPU | OCP_USER_SDMA, 3739 .user = OCP_USER_MPU | OCP_USER_SDMA,
3704 }; 3740 };
3705 3741
3706 /* l4_per2 -> vcp2 */ 3742 /* l4_per2 -> vcp2 */
3707 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { 3743 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3708 .master = &dra7xx_l4_per2_hwmod, 3744 .master = &dra7xx_l4_per2_hwmod,
3709 .slave = &dra7xx_vcp2_hwmod, 3745 .slave = &dra7xx_vcp2_hwmod,
3710 .clk = "l3_iclk_div", 3746 .clk = "l3_iclk_div",
3711 .user = OCP_USER_MPU | OCP_USER_SDMA, 3747 .user = OCP_USER_MPU | OCP_USER_SDMA,
3712 }; 3748 };
3713 3749
3714 /* l4_wkup -> wd_timer2 */ 3750 /* l4_wkup -> wd_timer2 */
3715 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { 3751 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3716 .master = &dra7xx_l4_wkup_hwmod, 3752 .master = &dra7xx_l4_wkup_hwmod,
3717 .slave = &dra7xx_wd_timer2_hwmod, 3753 .slave = &dra7xx_wd_timer2_hwmod,
3718 .clk = "wkupaon_iclk_mux", 3754 .clk = "wkupaon_iclk_mux",
3719 .user = OCP_USER_MPU | OCP_USER_SDMA, 3755 .user = OCP_USER_MPU | OCP_USER_SDMA,
3720 }; 3756 };
3721 3757
3722 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { 3758 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3723 &dra7xx_l3_main_1__dmm, 3759 &dra7xx_l3_main_1__dmm,
3724 &dra7xx_l3_main_2__l3_instr, 3760 &dra7xx_l3_main_2__l3_instr,
3725 &dra7xx_l4_cfg__l3_main_1, 3761 &dra7xx_l4_cfg__l3_main_1,
3726 &dra7xx_mpu__l3_main_1, 3762 &dra7xx_mpu__l3_main_1,
3727 &dra7xx_l3_main_1__l3_main_2, 3763 &dra7xx_l3_main_1__l3_main_2,
3728 &dra7xx_l4_cfg__l3_main_2, 3764 &dra7xx_l4_cfg__l3_main_2,
3729 &dra7xx_l3_main_1__l4_cfg, 3765 &dra7xx_l3_main_1__l4_cfg,
3730 &dra7xx_l3_main_1__l4_per1, 3766 &dra7xx_l3_main_1__l4_per1,
3731 &dra7xx_l3_main_1__l4_per2, 3767 &dra7xx_l3_main_1__l4_per2,
3732 &dra7xx_l3_main_1__l4_per3, 3768 &dra7xx_l3_main_1__l4_per3,
3733 &dra7xx_l3_main_1__l4_wkup, 3769 &dra7xx_l3_main_1__l4_wkup,
3734 &dra7xx_l4_per2__atl, 3770 &dra7xx_l4_per2__atl,
3735 &dra7xx_l3_main_1__bb2d, 3771 &dra7xx_l3_main_1__bb2d,
3736 &dra7xx_l4_wkup__counter_32k, 3772 &dra7xx_l4_wkup__counter_32k,
3737 &dra7xx_l4_wkup__ctrl_module_wkup, 3773 &dra7xx_l4_wkup__ctrl_module_wkup,
3738 &dra7xx_l4_wkup__dcan1, 3774 &dra7xx_l4_wkup__dcan1,
3739 &dra7xx_l4_per2__dcan2, 3775 &dra7xx_l4_per2__dcan2,
3740 &dra7xx_l4_per2__cpgmac0, 3776 &dra7xx_l4_per2__cpgmac0,
3741 &dra7xx_l4_per2__mcasp1, 3777 &dra7xx_l4_per2__mcasp1,
3742 &dra7xx_l3_main_1__mcasp1, 3778 &dra7xx_l3_main_1__mcasp1,
3743 &dra7xx_l4_per2__mcasp2, 3779 &dra7xx_l4_per2__mcasp2,
3744 &dra7xx_l3_main_1__mcasp2, 3780 &dra7xx_l3_main_1__mcasp2,
3745 &dra7xx_l4_per2__mcasp3, 3781 &dra7xx_l4_per2__mcasp3,
3746 &dra7xx_l3_main_1__mcasp3, 3782 &dra7xx_l3_main_1__mcasp3,
3747 &dra7xx_l4_per2__mcasp4, 3783 &dra7xx_l4_per2__mcasp4,
3748 &dra7xx_l4_per2__mcasp5, 3784 &dra7xx_l4_per2__mcasp5,
3749 &dra7xx_l4_per2__mcasp6, 3785 &dra7xx_l4_per2__mcasp6,
3750 &dra7xx_l4_per2__mcasp7, 3786 &dra7xx_l4_per2__mcasp7,
3751 &dra7xx_l4_per2__mcasp8, 3787 &dra7xx_l4_per2__mcasp8,
3752 &dra7xx_gmac__mdio, 3788 &dra7xx_gmac__mdio,
3753 &dra7xx_l4_cfg__dma_system, 3789 &dra7xx_l4_cfg__dma_system,
3754 &dra7xx_l3_main_1__tpcc, 3790 &dra7xx_l3_main_1__tpcc,
3755 &dra7xx_l3_main_1__tptc0, 3791 &dra7xx_l3_main_1__tptc0,
3756 &dra7xx_l3_main_1__tptc1, 3792 &dra7xx_l3_main_1__tptc1,
3757 &dra7xx_l3_main_1__dss, 3793 &dra7xx_l3_main_1__dss,
3758 &dra7xx_l3_main_1__dispc, 3794 &dra7xx_l3_main_1__dispc,
3759 &dra7xx_l3_main_1__hdmi, 3795 &dra7xx_l3_main_1__hdmi,
3760 &dra7xx_l4_per1__elm, 3796 &dra7xx_l4_per1__elm,
3761 &dra7xx_l4_wkup__gpio1, 3797 &dra7xx_l4_wkup__gpio1,
3762 &dra7xx_l4_per1__gpio2, 3798 &dra7xx_l4_per1__gpio2,
3763 &dra7xx_l4_per1__gpio3, 3799 &dra7xx_l4_per1__gpio3,
3764 &dra7xx_l4_per1__gpio4, 3800 &dra7xx_l4_per1__gpio4,
3765 &dra7xx_l4_per1__gpio5, 3801 &dra7xx_l4_per1__gpio5,
3766 &dra7xx_l4_per1__gpio6, 3802 &dra7xx_l4_per1__gpio6,
3767 &dra7xx_l4_per1__gpio7, 3803 &dra7xx_l4_per1__gpio7,
3768 &dra7xx_l4_per1__gpio8, 3804 &dra7xx_l4_per1__gpio8,
3769 &dra7xx_l3_main_1__gpmc, 3805 &dra7xx_l3_main_1__gpmc,
3770 &dra7xx_l4_per1__hdq1w, 3806 &dra7xx_l4_per1__hdq1w,
3771 &dra7xx_l4_per1__i2c1, 3807 &dra7xx_l4_per1__i2c1,
3772 &dra7xx_l4_per1__i2c2, 3808 &dra7xx_l4_per1__i2c2,
3773 &dra7xx_l4_per1__i2c3, 3809 &dra7xx_l4_per1__i2c3,
3774 &dra7xx_l4_per1__i2c4, 3810 &dra7xx_l4_per1__i2c4,
3775 &dra7xx_l4_per1__i2c5, 3811 &dra7xx_l4_per1__i2c5,
3776 &dra7xx_l4_cfg__mailbox1, 3812 &dra7xx_l4_cfg__mailbox1,
3777 &dra7xx_l4_per3__mailbox2, 3813 &dra7xx_l4_per3__mailbox2,
3778 &dra7xx_l4_per3__mailbox3, 3814 &dra7xx_l4_per3__mailbox3,
3779 &dra7xx_l4_per3__mailbox4, 3815 &dra7xx_l4_per3__mailbox4,
3780 &dra7xx_l4_per3__mailbox5, 3816 &dra7xx_l4_per3__mailbox5,
3781 &dra7xx_l4_per3__mailbox6, 3817 &dra7xx_l4_per3__mailbox6,
3782 &dra7xx_l4_per3__mailbox7, 3818 &dra7xx_l4_per3__mailbox7,
3783 &dra7xx_l4_per3__mailbox8, 3819 &dra7xx_l4_per3__mailbox8,
3784 &dra7xx_l4_per3__mailbox9, 3820 &dra7xx_l4_per3__mailbox9,
3785 &dra7xx_l4_per3__mailbox10, 3821 &dra7xx_l4_per3__mailbox10,
3786 &dra7xx_l4_per3__mailbox11, 3822 &dra7xx_l4_per3__mailbox11,
3787 &dra7xx_l4_per3__mailbox12, 3823 &dra7xx_l4_per3__mailbox12,
3788 &dra7xx_l4_per3__mailbox13, 3824 &dra7xx_l4_per3__mailbox13,
3789 &dra7xx_l4_per1__mcspi1, 3825 &dra7xx_l4_per1__mcspi1,
3790 &dra7xx_l4_per1__mcspi2, 3826 &dra7xx_l4_per1__mcspi2,
3791 &dra7xx_l4_per1__mcspi3, 3827 &dra7xx_l4_per1__mcspi3,
3792 &dra7xx_l4_per1__mcspi4, 3828 &dra7xx_l4_per1__mcspi4,
3793 &dra7xx_l4_per1__mmc1, 3829 &dra7xx_l4_per1__mmc1,
3794 &dra7xx_l4_per1__mmc2, 3830 &dra7xx_l4_per1__mmc2,
3795 &dra7xx_l4_per1__mmc3, 3831 &dra7xx_l4_per1__mmc3,
3796 &dra7xx_l4_per1__mmc4, 3832 &dra7xx_l4_per1__mmc4,
3797 &dra7xx_l4_cfg__mpu, 3833 &dra7xx_l4_cfg__mpu,
3798 &dra7xx_l4_cfg__ocp2scp1, 3834 &dra7xx_l4_cfg__ocp2scp1,
3799 &dra7xx_l4_cfg__ocp2scp3, 3835 &dra7xx_l4_cfg__ocp2scp3,
3800 &dra7xx_l3_main_1__pciess1, 3836 &dra7xx_l3_main_1__pciess1,
3801 &dra7xx_l4_cfg__pciess1, 3837 &dra7xx_l4_cfg__pciess1,
3802 &dra7xx_l3_main_1__pciess2, 3838 &dra7xx_l3_main_1__pciess2,
3803 &dra7xx_l4_cfg__pciess2, 3839 &dra7xx_l4_cfg__pciess2,
3804 &dra7xx_l3_main_1__qspi, 3840 &dra7xx_l3_main_1__qspi,
3805 &dra7xx_l4_per3__rtcss, 3841 &dra7xx_l4_per3__rtcss,
3806 &dra7xx_l4_cfg__sata, 3842 &dra7xx_l4_cfg__sata,
3807 &dra7xx_l4_cfg__smartreflex_core, 3843 &dra7xx_l4_cfg__smartreflex_core,
3808 &dra7xx_l4_cfg__smartreflex_mpu, 3844 &dra7xx_l4_cfg__smartreflex_mpu,
3809 &dra7xx_l4_cfg__spinlock, 3845 &dra7xx_l4_cfg__spinlock,
3810 &dra7xx_l4_wkup__timer1, 3846 &dra7xx_l4_wkup__timer1,
3811 &dra7xx_l4_per1__timer2, 3847 &dra7xx_l4_per1__timer2,
3812 &dra7xx_l4_per1__timer3, 3848 &dra7xx_l4_per1__timer3,
3813 &dra7xx_l4_per1__timer4, 3849 &dra7xx_l4_per1__timer4,
3814 &dra7xx_l4_per3__timer5, 3850 &dra7xx_l4_per3__timer5,
3815 &dra7xx_l4_per3__timer6, 3851 &dra7xx_l4_per3__timer6,
3816 &dra7xx_l4_per3__timer7, 3852 &dra7xx_l4_per3__timer7,
3817 &dra7xx_l4_per3__timer8, 3853 &dra7xx_l4_per3__timer8,
3818 &dra7xx_l4_per1__timer9, 3854 &dra7xx_l4_per1__timer9,
3819 &dra7xx_l4_per1__timer10, 3855 &dra7xx_l4_per1__timer10,
3820 &dra7xx_l4_per1__timer11, 3856 &dra7xx_l4_per1__timer11,
3821 &dra7xx_l4_per3__timer13, 3857 &dra7xx_l4_per3__timer13,
3822 &dra7xx_l4_per3__timer14, 3858 &dra7xx_l4_per3__timer14,
3823 &dra7xx_l4_per3__timer15, 3859 &dra7xx_l4_per3__timer15,
3824 &dra7xx_l4_per3__timer16, 3860 &dra7xx_l4_per3__timer16,
3825 &dra7xx_l4_per1__uart1, 3861 &dra7xx_l4_per1__uart1,
3826 &dra7xx_l4_per1__uart2, 3862 &dra7xx_l4_per1__uart2,
3827 &dra7xx_l4_per1__uart3, 3863 &dra7xx_l4_per1__uart3,
3828 &dra7xx_l4_per1__uart4, 3864 &dra7xx_l4_per1__uart4,
3829 &dra7xx_l4_per1__uart5, 3865 &dra7xx_l4_per1__uart5,
3830 &dra7xx_l4_per1__uart6, 3866 &dra7xx_l4_per1__uart6,
3831 &dra7xx_l4_per2__uart7, 3867 &dra7xx_l4_per2__uart7,
3832 &dra7xx_l4_per2__uart8, 3868 &dra7xx_l4_per2__uart8,
3833 &dra7xx_l4_per2__uart9, 3869 &dra7xx_l4_per2__uart9,
3834 &dra7xx_l4_wkup__uart10, 3870 &dra7xx_l4_wkup__uart10,
3871 &dra7xx_l4_per1__des,
3835 &dra7xx_l4_per3__usb_otg_ss1, 3872 &dra7xx_l4_per3__usb_otg_ss1,
3836 &dra7xx_l4_per3__usb_otg_ss2, 3873 &dra7xx_l4_per3__usb_otg_ss2,
3837 &dra7xx_l4_per3__usb_otg_ss3, 3874 &dra7xx_l4_per3__usb_otg_ss3,
3838 &dra7xx_l3_main_1__vcp1, 3875 &dra7xx_l3_main_1__vcp1,
3839 &dra7xx_l4_per2__vcp1, 3876 &dra7xx_l4_per2__vcp1,
3840 &dra7xx_l3_main_1__vcp2, 3877 &dra7xx_l3_main_1__vcp2,
3841 &dra7xx_l4_per2__vcp2, 3878 &dra7xx_l4_per2__vcp2,
3842 &dra7xx_l4_wkup__wd_timer2, 3879 &dra7xx_l4_wkup__wd_timer2,
3843 NULL, 3880 NULL,
3844 }; 3881 };
3845 3882
3846 /* GP-only hwmod links */ 3883 /* GP-only hwmod links */
3847 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { 3884 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3848 &dra7xx_l4_wkup__timer12, 3885 &dra7xx_l4_wkup__timer12,
3849 NULL, 3886 NULL,
3850 }; 3887 };
3851 3888
3852 /* SoC variant specific hwmod links */ 3889 /* SoC variant specific hwmod links */
3853 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { 3890 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3854 &dra7xx_l4_per3__usb_otg_ss4, 3891 &dra7xx_l4_per3__usb_otg_ss4,
3855 NULL, 3892 NULL,
3856 }; 3893 };
3857 3894
3858 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { 3895 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3859 NULL, 3896 NULL,
3860 }; 3897 };
3861 3898
3862 int __init dra7xx_hwmod_init(void) 3899 int __init dra7xx_hwmod_init(void)
3863 { 3900 {
3864 int ret; 3901 int ret;
3865 3902
3866 omap_hwmod_init(); 3903 omap_hwmod_init();
3867 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); 3904 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3868 3905
3869 if (!ret && soc_is_dra74x()) 3906 if (!ret && soc_is_dra74x())
3870 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); 3907 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3871 else if (!ret && soc_is_dra72x()) 3908 else if (!ret && soc_is_dra72x())
3872 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); 3909 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3873 3910
3874 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) 3911 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
3875 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); 3912 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
3876 3913
3877 return ret; 3914 return ret;
3878 } 3915 }
3879 3916