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Commit 9c0b8420369cb5d7fd2fea51d4705cbd0ea52743

Authored by Ricardo Neri
Committed by Tomi Valkeinen
1 parent 38137c8f0c
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

OMAPDSS: Provide an interface for audio support 

There exist several display technologies and standards that support audio as
well. Hence, it is relevant to update the DSS device driver to provide an audio
interface that may be used by an audio driver or any other driver interested in
the functionality.

The audio_enable function is intended to prepare the relevant
IP for playback (e.g., enabling an audio FIFO, taking in/out of reset
some IP, enabling companion chips, etc). It is intended to be called before
audio_start. The audio_disable function performs the reverse operation and is
intended to be called after audio_stop.

While a given DSS device driver may support audio, it is possible that for
certain configurations audio is not supported (e.g., an HDMI display using a
VESA video timing). The audio_supported function is intended to query whether
the current configuration of the display supports audio.

The audio_config function is intended to configure all the relevant audio
parameters of the display. In order to make the function independent of any
specific DSS device driver, a struct omap_dss_audio is defined. Its purpose
is to contain all the required parameters for audio configuration. At the
moment, such structure contains pointers to IEC-60958 channel status word and
CEA-861 audio infoframe structures. This should be enough to support HDMI and
DisplayPort, as both are based on CEA-861 and IEC-60958. The omap_dss_audio
structure may be extended in the future if required.

The audio_enable/disable, audio_config and audio_supported functions could be
implemented as functions that may sleep. Hence, they should not be called
while holding a spinlock or a readlock.

The audio_start/audio_stop function is intended to effectively start/stop audio
playback after the configuration has taken place. These functions are designed
to be used in an atomic context. Hence, audio_start should return quickly and be
called only after all the needed resources for audio playback (audio FIFOs,
DMA channels, companion chips, etc) have been enabled to begin data transfers.
audio_stop is designed to only stop the audio transfers. The resources used
for playback are released using audio_disable.

A new enum omap_dss_audio_state is introduced to help the implementations of
the interface to keep track of the audio state. The initial state is _DISABLED;
then, the state transitions to _CONFIGURED, and then, when it is ready to
play audio, to _ENABLED. The state _PLAYING is used when the audio is being
rendered.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>

Showing 2 changed files with 79 additions and 0 deletions Inline Diff

Documentation/arm/OMAP/DSS
Diff comments   View file @ 9c0b842
1 OMAP2/3 Display Subsystem 1 OMAP2/3 Display Subsystem
2 ------------------------- 2 -------------------------
3 3
4 This is an almost total rewrite of the OMAP FB driver in drivers/video/omap 4 This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
5 (let's call it DSS1). The main differences between DSS1 and DSS2 are DSI, 5 (let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
6 TV-out and multiple display support, but there are lots of small improvements 6 TV-out and multiple display support, but there are lots of small improvements
7 also. 7 also.
8 8
9 The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB, 9 The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
10 panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live 10 panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
11 currently side by side, you can choose which one to use. 11 currently side by side, you can choose which one to use.
12 12
13 Features 13 Features
14 -------- 14 --------
15 15
16 Working and tested features include: 16 Working and tested features include:
17 17
18 - MIPI DPI (parallel) output 18 - MIPI DPI (parallel) output
19 - MIPI DSI output in command mode 19 - MIPI DSI output in command mode
20 - MIPI DBI (RFBI) output 20 - MIPI DBI (RFBI) output
21 - SDI output 21 - SDI output
22 - TV output 22 - TV output
23 - All pieces can be compiled as a module or inside kernel 23 - All pieces can be compiled as a module or inside kernel
24 - Use DISPC to update any of the outputs 24 - Use DISPC to update any of the outputs
25 - Use CPU to update RFBI or DSI output 25 - Use CPU to update RFBI or DSI output
26 - OMAP DISPC planes 26 - OMAP DISPC planes
27 - RGB16, RGB24 packed, RGB24 unpacked 27 - RGB16, RGB24 packed, RGB24 unpacked
28 - YUV2, UYVY 28 - YUV2, UYVY
29 - Scaling 29 - Scaling
30 - Adjusting DSS FCK to find a good pixel clock 30 - Adjusting DSS FCK to find a good pixel clock
31 - Use DSI DPLL to create DSS FCK 31 - Use DSI DPLL to create DSS FCK
32 32
33 Tested boards include: 33 Tested boards include:
34 - OMAP3 SDP board 34 - OMAP3 SDP board
35 - Beagle board 35 - Beagle board
36 - N810 36 - N810
37 37
38 omapdss driver 38 omapdss driver
39 -------------- 39 --------------
40 40
41 The DSS driver does not itself have any support for Linux framebuffer, V4L or 41 The DSS driver does not itself have any support for Linux framebuffer, V4L or
42 such like the current ones, but it has an internal kernel API that upper level 42 such like the current ones, but it has an internal kernel API that upper level
43 drivers can use. 43 drivers can use.
44 44
45 The DSS driver models OMAP's overlays, overlay managers and displays in a 45 The DSS driver models OMAP's overlays, overlay managers and displays in a
46 flexible way to enable non-common multi-display configuration. In addition to 46 flexible way to enable non-common multi-display configuration. In addition to
47 modelling the hardware overlays, omapdss supports virtual overlays and overlay 47 modelling the hardware overlays, omapdss supports virtual overlays and overlay
48 managers. These can be used when updating a display with CPU or system DMA. 48 managers. These can be used when updating a display with CPU or system DMA.
49 49
50 omapdss driver support for audio
51 --------------------------------
52 There exist several display technologies and standards that support audio as
53 well. Hence, it is relevant to update the DSS device driver to provide an audio
54 interface that may be used by an audio driver or any other driver interested in
55 the functionality.
56
57 The audio_enable function is intended to prepare the relevant
58 IP for playback (e.g., enabling an audio FIFO, taking in/out of reset
59 some IP, enabling companion chips, etc). It is intended to be called before
60 audio_start. The audio_disable function performs the reverse operation and is
61 intended to be called after audio_stop.
62
63 While a given DSS device driver may support audio, it is possible that for
64 certain configurations audio is not supported (e.g., an HDMI display using a
65 VESA video timing). The audio_supported function is intended to query whether
66 the current configuration of the display supports audio.
67
68 The audio_config function is intended to configure all the relevant audio
69 parameters of the display. In order to make the function independent of any
70 specific DSS device driver, a struct omap_dss_audio is defined. Its purpose
71 is to contain all the required parameters for audio configuration. At the
72 moment, such structure contains pointers to IEC-60958 channel status word
73 and CEA-861 audio infoframe structures. This should be enough to support
74 HDMI and DisplayPort, as both are based on CEA-861 and IEC-60958.
75
76 The audio_enable/disable, audio_config and audio_supported functions could be
77 implemented as functions that may sleep. Hence, they should not be called
78 while holding a spinlock or a readlock.
79
80 The audio_start/audio_stop function is intended to effectively start/stop audio
81 playback after the configuration has taken place. These functions are designed
82 to be used in an atomic context. Hence, audio_start should return quickly and be
83 called only after all the needed resources for audio playback (audio FIFOs,
84 DMA channels, companion chips, etc) have been enabled to begin data transfers.
85 audio_stop is designed to only stop the audio transfers. The resources used
86 for playback are released using audio_disable.
87
88 The enum omap_dss_audio_state may be used to help the implementations of
89 the interface to keep track of the audio state. The initial state is _DISABLED;
90 then, the state transitions to _CONFIGURED, and then, when it is ready to
91 play audio, to _ENABLED. The state _PLAYING is used when the audio is being
92 rendered.
93
94
50 Panel and controller drivers 95 Panel and controller drivers
51 ---------------------------- 96 ----------------------------
52 97
53 The drivers implement panel or controller specific functionality and are not 98 The drivers implement panel or controller specific functionality and are not
54 usually visible to users except through omapfb driver. They register 99 usually visible to users except through omapfb driver. They register
55 themselves to the DSS driver. 100 themselves to the DSS driver.
56 101
57 omapfb driver 102 omapfb driver
58 ------------- 103 -------------
59 104
60 The omapfb driver implements arbitrary number of standard linux framebuffers. 105 The omapfb driver implements arbitrary number of standard linux framebuffers.
61 These framebuffers can be routed flexibly to any overlays, thus allowing very 106 These framebuffers can be routed flexibly to any overlays, thus allowing very
62 dynamic display architecture. 107 dynamic display architecture.
63 108
64 The driver exports some omapfb specific ioctls, which are compatible with the 109 The driver exports some omapfb specific ioctls, which are compatible with the
65 ioctls in the old driver. 110 ioctls in the old driver.
66 111
67 The rest of the non standard features are exported via sysfs. Whether the final 112 The rest of the non standard features are exported via sysfs. Whether the final
68 implementation will use sysfs, or ioctls, is still open. 113 implementation will use sysfs, or ioctls, is still open.
69 114
70 V4L2 drivers 115 V4L2 drivers
71 ------------ 116 ------------
72 117
73 V4L2 is being implemented in TI. 118 V4L2 is being implemented in TI.
74 119
75 From omapdss point of view the V4L2 drivers should be similar to framebuffer 120 From omapdss point of view the V4L2 drivers should be similar to framebuffer
76 driver. 121 driver.
77 122
78 Architecture 123 Architecture
79 -------------------- 124 --------------------
80 125
81 Some clarification what the different components do: 126 Some clarification what the different components do:
82 127
83 - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the 128 - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
84 pixel data for the image. Framebuffer has width and height and color 129 pixel data for the image. Framebuffer has width and height and color
85 depth. 130 depth.
86 - Overlay defines where the pixels are read from and where they go on the 131 - Overlay defines where the pixels are read from and where they go on the
87 screen. The overlay may be smaller than framebuffer, thus displaying only 132 screen. The overlay may be smaller than framebuffer, thus displaying only
88 part of the framebuffer. The position of the overlay may be changed if 133 part of the framebuffer. The position of the overlay may be changed if
89 the overlay is smaller than the display. 134 the overlay is smaller than the display.
90 - Overlay manager combines the overlays in to one image and feeds them to 135 - Overlay manager combines the overlays in to one image and feeds them to
91 display. 136 display.
92 - Display is the actual physical display device. 137 - Display is the actual physical display device.
93 138
94 A framebuffer can be connected to multiple overlays to show the same pixel data 139 A framebuffer can be connected to multiple overlays to show the same pixel data
95 on all of the overlays. Note that in this case the overlay input sizes must be 140 on all of the overlays. Note that in this case the overlay input sizes must be
96 the same, but, in case of video overlays, the output size can be different. Any 141 the same, but, in case of video overlays, the output size can be different. Any
97 framebuffer can be connected to any overlay. 142 framebuffer can be connected to any overlay.
98 143
99 An overlay can be connected to one overlay manager. Also DISPC overlays can be 144 An overlay can be connected to one overlay manager. Also DISPC overlays can be
100 connected only to DISPC overlay managers, and virtual overlays can be only 145 connected only to DISPC overlay managers, and virtual overlays can be only
101 connected to virtual overlays. 146 connected to virtual overlays.
102 147
103 An overlay manager can be connected to one display. There are certain 148 An overlay manager can be connected to one display. There are certain
104 restrictions which kinds of displays an overlay manager can be connected: 149 restrictions which kinds of displays an overlay manager can be connected:
105 150
106 - DISPC TV overlay manager can be only connected to TV display. 151 - DISPC TV overlay manager can be only connected to TV display.
107 - Virtual overlay managers can only be connected to DBI or DSI displays. 152 - Virtual overlay managers can only be connected to DBI or DSI displays.
108 - DISPC LCD overlay manager can be connected to all displays, except TV 153 - DISPC LCD overlay manager can be connected to all displays, except TV
109 display. 154 display.
110 155
111 Sysfs 156 Sysfs
112 ----- 157 -----
113 The sysfs interface is mainly used for testing. I don't think sysfs 158 The sysfs interface is mainly used for testing. I don't think sysfs
114 interface is the best for this in the final version, but I don't quite know 159 interface is the best for this in the final version, but I don't quite know
115 what would be the best interfaces for these things. 160 what would be the best interfaces for these things.
116 161
117 The sysfs interface is divided to two parts: DSS and FB. 162 The sysfs interface is divided to two parts: DSS and FB.
118 163
119 /sys/class/graphics/fb? directory: 164 /sys/class/graphics/fb? directory:
120 mirror 0=off, 1=on 165 mirror 0=off, 1=on
121 rotate Rotation 0-3 for 0, 90, 180, 270 degrees 166 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
122 rotate_type 0 = DMA rotation, 1 = VRFB rotation 167 rotate_type 0 = DMA rotation, 1 = VRFB rotation
123 overlays List of overlay numbers to which framebuffer pixels go 168 overlays List of overlay numbers to which framebuffer pixels go
124 phys_addr Physical address of the framebuffer 169 phys_addr Physical address of the framebuffer
125 virt_addr Virtual address of the framebuffer 170 virt_addr Virtual address of the framebuffer
126 size Size of the framebuffer 171 size Size of the framebuffer
127 172
128 /sys/devices/platform/omapdss/overlay? directory: 173 /sys/devices/platform/omapdss/overlay? directory:
129 enabled 0=off, 1=on 174 enabled 0=off, 1=on
130 input_size width,height (ie. the framebuffer size) 175 input_size width,height (ie. the framebuffer size)
131 manager Destination overlay manager name 176 manager Destination overlay manager name
132 name 177 name
133 output_size width,height 178 output_size width,height
134 position x,y 179 position x,y
135 screen_width width 180 screen_width width
136 global_alpha global alpha 0-255 0=transparent 255=opaque 181 global_alpha global alpha 0-255 0=transparent 255=opaque
137 182
138 /sys/devices/platform/omapdss/manager? directory: 183 /sys/devices/platform/omapdss/manager? directory:
139 display Destination display 184 display Destination display
140 name 185 name
141 alpha_blending_enabled 0=off, 1=on 186 alpha_blending_enabled 0=off, 1=on
142 trans_key_enabled 0=off, 1=on 187 trans_key_enabled 0=off, 1=on
143 trans_key_type gfx-destination, video-source 188 trans_key_type gfx-destination, video-source
144 trans_key_value transparency color key (RGB24) 189 trans_key_value transparency color key (RGB24)
145 default_color default background color (RGB24) 190 default_color default background color (RGB24)
146 191
147 /sys/devices/platform/omapdss/display? directory: 192 /sys/devices/platform/omapdss/display? directory:
148 ctrl_name Controller name 193 ctrl_name Controller name
149 mirror 0=off, 1=on 194 mirror 0=off, 1=on
150 update_mode 0=off, 1=auto, 2=manual 195 update_mode 0=off, 1=auto, 2=manual
151 enabled 0=off, 1=on 196 enabled 0=off, 1=on
152 name 197 name
153 rotate Rotation 0-3 for 0, 90, 180, 270 degrees 198 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
154 timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw) 199 timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
155 When writing, two special timings are accepted for tv-out: 200 When writing, two special timings are accepted for tv-out:
156 "pal" and "ntsc" 201 "pal" and "ntsc"
157 panel_name 202 panel_name
158 tear_elim Tearing elimination 0=off, 1=on 203 tear_elim Tearing elimination 0=off, 1=on
159 output_type Output type (video encoder only): "composite" or "svideo" 204 output_type Output type (video encoder only): "composite" or "svideo"
160 205
161 There are also some debugfs files at <debugfs>/omapdss/ which show information 206 There are also some debugfs files at <debugfs>/omapdss/ which show information
162 about clocks and registers. 207 about clocks and registers.
163 208
164 Examples 209 Examples
165 -------- 210 --------
166 211
167 The following definitions have been made for the examples below: 212 The following definitions have been made for the examples below:
168 213
169 ovl0=/sys/devices/platform/omapdss/overlay0 214 ovl0=/sys/devices/platform/omapdss/overlay0
170 ovl1=/sys/devices/platform/omapdss/overlay1 215 ovl1=/sys/devices/platform/omapdss/overlay1
171 ovl2=/sys/devices/platform/omapdss/overlay2 216 ovl2=/sys/devices/platform/omapdss/overlay2
172 217
173 mgr0=/sys/devices/platform/omapdss/manager0 218 mgr0=/sys/devices/platform/omapdss/manager0
174 mgr1=/sys/devices/platform/omapdss/manager1 219 mgr1=/sys/devices/platform/omapdss/manager1
175 220
176 lcd=/sys/devices/platform/omapdss/display0 221 lcd=/sys/devices/platform/omapdss/display0
177 dvi=/sys/devices/platform/omapdss/display1 222 dvi=/sys/devices/platform/omapdss/display1
178 tv=/sys/devices/platform/omapdss/display2 223 tv=/sys/devices/platform/omapdss/display2
179 224
180 fb0=/sys/class/graphics/fb0 225 fb0=/sys/class/graphics/fb0
181 fb1=/sys/class/graphics/fb1 226 fb1=/sys/class/graphics/fb1
182 fb2=/sys/class/graphics/fb2 227 fb2=/sys/class/graphics/fb2
183 228
184 Default setup on OMAP3 SDP 229 Default setup on OMAP3 SDP
185 -------------------------- 230 --------------------------
186 231
187 Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI 232 Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
188 and TV-out are not in use. The columns from left to right are: 233 and TV-out are not in use. The columns from left to right are:
189 framebuffers, overlays, overlay managers, displays. Framebuffers are 234 framebuffers, overlays, overlay managers, displays. Framebuffers are
190 handled by omapfb, and the rest by the DSS. 235 handled by omapfb, and the rest by the DSS.
191 236
192 FB0 --- GFX -\ DVI 237 FB0 --- GFX -\ DVI
193 FB1 --- VID1 --+- LCD ---- LCD 238 FB1 --- VID1 --+- LCD ---- LCD
194 FB2 --- VID2 -/ TV ----- TV 239 FB2 --- VID2 -/ TV ----- TV
195 240
196 Example: Switch from LCD to DVI 241 Example: Switch from LCD to DVI
197 ---------------------- 242 ----------------------
198 243
199 w=`cat $dvi/timings | cut -d "," -f 2 | cut -d "/" -f 1` 244 w=`cat $dvi/timings | cut -d "," -f 2 | cut -d "/" -f 1`
200 h=`cat $dvi/timings | cut -d "," -f 3 | cut -d "/" -f 1` 245 h=`cat $dvi/timings | cut -d "," -f 3 | cut -d "/" -f 1`
201 246
202 echo "0" > $lcd/enabled 247 echo "0" > $lcd/enabled
203 echo "" > $mgr0/display 248 echo "" > $mgr0/display
204 fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h 249 fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
205 # at this point you have to switch the dvi/lcd dip-switch from the omap board 250 # at this point you have to switch the dvi/lcd dip-switch from the omap board
206 echo "dvi" > $mgr0/display 251 echo "dvi" > $mgr0/display
207 echo "1" > $dvi/enabled 252 echo "1" > $dvi/enabled
208 253
209 After this the configuration looks like: 254 After this the configuration looks like:
210 255
211 FB0 --- GFX -\ -- DVI 256 FB0 --- GFX -\ -- DVI
212 FB1 --- VID1 --+- LCD -/ LCD 257 FB1 --- VID1 --+- LCD -/ LCD
213 FB2 --- VID2 -/ TV ----- TV 258 FB2 --- VID2 -/ TV ----- TV
214 259
215 Example: Clone GFX overlay to LCD and TV 260 Example: Clone GFX overlay to LCD and TV
216 ------------------------------- 261 -------------------------------
217 262
218 w=`cat $tv/timings | cut -d "," -f 2 | cut -d "/" -f 1` 263 w=`cat $tv/timings | cut -d "," -f 2 | cut -d "/" -f 1`
219 h=`cat $tv/timings | cut -d "," -f 3 | cut -d "/" -f 1` 264 h=`cat $tv/timings | cut -d "," -f 3 | cut -d "/" -f 1`
220 265
221 echo "0" > $ovl0/enabled 266 echo "0" > $ovl0/enabled
222 echo "0" > $ovl1/enabled 267 echo "0" > $ovl1/enabled
223 268
224 echo "" > $fb1/overlays 269 echo "" > $fb1/overlays
225 echo "0,1" > $fb0/overlays 270 echo "0,1" > $fb0/overlays
226 271
227 echo "$w,$h" > $ovl1/output_size 272 echo "$w,$h" > $ovl1/output_size
228 echo "tv" > $ovl1/manager 273 echo "tv" > $ovl1/manager
229 274
230 echo "1" > $ovl0/enabled 275 echo "1" > $ovl0/enabled
231 echo "1" > $ovl1/enabled 276 echo "1" > $ovl1/enabled
232 277
233 echo "1" > $tv/enabled 278 echo "1" > $tv/enabled
234 279
235 After this the configuration looks like (only relevant parts shown): 280 After this the configuration looks like (only relevant parts shown):
236 281
237 FB0 +-- GFX ---- LCD ---- LCD 282 FB0 +-- GFX ---- LCD ---- LCD
238 \- VID1 ---- TV ---- TV 283 \- VID1 ---- TV ---- TV
239 284
240 Misc notes 285 Misc notes
241 ---------- 286 ----------
242 287
243 OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator. 288 OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
244 289
245 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock 290 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
246 of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI. 291 of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
247 292
248 Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB 293 Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
249 does not support mirroring. 294 does not support mirroring.
250 295
251 VRFB rotation requires much more memory than non-rotated framebuffer, so you 296 VRFB rotation requires much more memory than non-rotated framebuffer, so you
252 probably need to increase your vram setting before using VRFB rotation. Also, 297 probably need to increase your vram setting before using VRFB rotation. Also,
253 many applications may not work with VRFB if they do not pay attention to all 298 many applications may not work with VRFB if they do not pay attention to all
254 framebuffer parameters. 299 framebuffer parameters.
255 300
256 Kernel boot arguments 301 Kernel boot arguments
257 --------------------- 302 ---------------------
258 303
259 vram=<size>[,<physaddr>] 304 vram=<size>[,<physaddr>]
260 - Amount of total VRAM to preallocate and optionally a physical start 305 - Amount of total VRAM to preallocate and optionally a physical start
261 memory address. For example, "10M". omapfb allocates memory for 306 memory address. For example, "10M". omapfb allocates memory for
262 framebuffers from VRAM. 307 framebuffers from VRAM.
263 308
264 omapfb.mode=<display>:<mode>[,...] 309 omapfb.mode=<display>:<mode>[,...]
265 - Default video mode for specified displays. For example, 310 - Default video mode for specified displays. For example,
266 "dvi:800x400MR-24@60". See drivers/video/modedb.c. 311 "dvi:800x400MR-24@60". See drivers/video/modedb.c.
267 There are also two special modes: "pal" and "ntsc" that 312 There are also two special modes: "pal" and "ntsc" that
268 can be used to tv out. 313 can be used to tv out.
269 314
270 omapfb.vram=<fbnum>:<size>[@<physaddr>][,...] 315 omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
271 - VRAM allocated for a framebuffer. Normally omapfb allocates vram 316 - VRAM allocated for a framebuffer. Normally omapfb allocates vram
272 depending on the display size. With this you can manually allocate 317 depending on the display size. With this you can manually allocate
273 more or define the physical address of each framebuffer. For example, 318 more or define the physical address of each framebuffer. For example,
274 "1:4M" to allocate 4M for fb1. 319 "1:4M" to allocate 4M for fb1.
275 320
276 omapfb.debug=<y|n> 321 omapfb.debug=<y|n>
277 - Enable debug printing. You have to have OMAPFB debug support enabled 322 - Enable debug printing. You have to have OMAPFB debug support enabled
278 in kernel config. 323 in kernel config.
279 324
280 omapfb.test=<y|n> 325 omapfb.test=<y|n>
281 - Draw test pattern to framebuffer whenever framebuffer settings change. 326 - Draw test pattern to framebuffer whenever framebuffer settings change.
282 You need to have OMAPFB debug support enabled in kernel config. 327 You need to have OMAPFB debug support enabled in kernel config.
283 328
284 omapfb.vrfb=<y|n> 329 omapfb.vrfb=<y|n>
285 - Use VRFB rotation for all framebuffers. 330 - Use VRFB rotation for all framebuffers.
286 331
287 omapfb.rotate=<angle> 332 omapfb.rotate=<angle>
288 - Default rotation applied to all framebuffers. 333 - Default rotation applied to all framebuffers.
289 0 - 0 degree rotation 334 0 - 0 degree rotation
290 1 - 90 degree rotation 335 1 - 90 degree rotation
291 2 - 180 degree rotation 336 2 - 180 degree rotation
292 3 - 270 degree rotation 337 3 - 270 degree rotation
293 338
294 omapfb.mirror=<y|n> 339 omapfb.mirror=<y|n>
295 - Default mirror for all framebuffers. Only works with DMA rotation. 340 - Default mirror for all framebuffers. Only works with DMA rotation.
296 341
297 omapdss.def_disp=<display> 342 omapdss.def_disp=<display>
298 - Name of default display, to which all overlays will be connected. 343 - Name of default display, to which all overlays will be connected.
299 Common examples are "lcd" or "tv". 344 Common examples are "lcd" or "tv".
300 345
301 omapdss.debug=<y|n> 346 omapdss.debug=<y|n>
302 - Enable debug printing. You have to have DSS debug support enabled in 347 - Enable debug printing. You have to have DSS debug support enabled in
303 kernel config. 348 kernel config.
304 349
305 TODO 350 TODO
306 ---- 351 ----
307 352
308 DSS locking 353 DSS locking
309 354
310 Error checking 355 Error checking
311 - Lots of checks are missing or implemented just as BUG() 356 - Lots of checks are missing or implemented just as BUG()
312 357
313 System DMA update for DSI 358 System DMA update for DSI
314 - Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how 359 - Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
315 to skip the empty byte?) 360 to skip the empty byte?)
316 361
317 OMAP1 support 362 OMAP1 support
318 - Not sure if needed 363 - Not sure if needed
319 364
320 365
include/video/omapdss.h
Diff comments   View file @ 9c0b842
1 /* 1 /*
2 * Copyright (C) 2008 Nokia Corporation 2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by 6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation. 7 * the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>. 15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */ 16 */
17 17
18 #ifndef __OMAP_OMAPDSS_H 18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H 19 #define __OMAP_OMAPDSS_H
20 20
21 #include <linux/list.h> 21 #include <linux/list.h>
22 #include <linux/kobject.h> 22 #include <linux/kobject.h>
23 #include <linux/device.h> 23 #include <linux/device.h>
24 24
25 #define DISPC_IRQ_FRAMEDONE (1 << 0) 25 #define DISPC_IRQ_FRAMEDONE (1 << 0)
26 #define DISPC_IRQ_VSYNC (1 << 1) 26 #define DISPC_IRQ_VSYNC (1 << 1)
27 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) 27 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28 #define DISPC_IRQ_EVSYNC_ODD (1 << 3) 28 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) 29 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) 30 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) 31 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32 #define DISPC_IRQ_GFX_END_WIN (1 << 7) 32 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
33 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) 33 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34 #define DISPC_IRQ_OCP_ERR (1 << 9) 34 #define DISPC_IRQ_OCP_ERR (1 << 9)
35 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) 35 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36 #define DISPC_IRQ_VID1_END_WIN (1 << 11) 36 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
37 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) 37 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38 #define DISPC_IRQ_VID2_END_WIN (1 << 13) 38 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
39 #define DISPC_IRQ_SYNC_LOST (1 << 14) 39 #define DISPC_IRQ_SYNC_LOST (1 << 14)
40 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) 40 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41 #define DISPC_IRQ_WAKEUP (1 << 16) 41 #define DISPC_IRQ_WAKEUP (1 << 16)
42 #define DISPC_IRQ_SYNC_LOST2 (1 << 17) 42 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43 #define DISPC_IRQ_VSYNC2 (1 << 18) 43 #define DISPC_IRQ_VSYNC2 (1 << 18)
44 #define DISPC_IRQ_VID3_END_WIN (1 << 19) 44 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
45 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) 45 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
47 #define DISPC_IRQ_FRAMEDONE2 (1 << 22) 47 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
48 #define DISPC_IRQ_FRAMEDONEWB (1 << 23) 48 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
49 #define DISPC_IRQ_FRAMEDONETV (1 << 24) 49 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
50 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 50 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
51 51
52 struct omap_dss_device; 52 struct omap_dss_device;
53 struct omap_overlay_manager; 53 struct omap_overlay_manager;
54 struct snd_aes_iec958;
55 struct snd_cea_861_aud_if;
54 56
55 enum omap_display_type { 57 enum omap_display_type {
56 OMAP_DISPLAY_TYPE_NONE = 0, 58 OMAP_DISPLAY_TYPE_NONE = 0,
57 OMAP_DISPLAY_TYPE_DPI = 1 << 0, 59 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
58 OMAP_DISPLAY_TYPE_DBI = 1 << 1, 60 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
59 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 61 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
60 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 62 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
61 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 63 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
62 OMAP_DISPLAY_TYPE_HDMI = 1 << 5, 64 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
63 }; 65 };
64 66
65 enum omap_plane { 67 enum omap_plane {
66 OMAP_DSS_GFX = 0, 68 OMAP_DSS_GFX = 0,
67 OMAP_DSS_VIDEO1 = 1, 69 OMAP_DSS_VIDEO1 = 1,
68 OMAP_DSS_VIDEO2 = 2, 70 OMAP_DSS_VIDEO2 = 2,
69 OMAP_DSS_VIDEO3 = 3, 71 OMAP_DSS_VIDEO3 = 3,
70 }; 72 };
71 73
72 enum omap_channel { 74 enum omap_channel {
73 OMAP_DSS_CHANNEL_LCD = 0, 75 OMAP_DSS_CHANNEL_LCD = 0,
74 OMAP_DSS_CHANNEL_DIGIT = 1, 76 OMAP_DSS_CHANNEL_DIGIT = 1,
75 OMAP_DSS_CHANNEL_LCD2 = 2, 77 OMAP_DSS_CHANNEL_LCD2 = 2,
76 }; 78 };
77 79
78 enum omap_color_mode { 80 enum omap_color_mode {
79 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ 81 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
80 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ 82 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
81 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ 83 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
82 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ 84 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
83 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ 85 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
84 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ 86 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
85 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ 87 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
86 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ 88 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
87 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ 89 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
88 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ 90 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
89 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ 91 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
90 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ 92 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
91 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ 93 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
92 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ 94 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
93 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ 95 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
94 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ 96 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
95 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ 97 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
96 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ 98 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
97 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ 99 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
98 }; 100 };
99 101
100 enum omap_lcd_display_type { 102 enum omap_lcd_display_type {
101 OMAP_DSS_LCD_DISPLAY_STN, 103 OMAP_DSS_LCD_DISPLAY_STN,
102 OMAP_DSS_LCD_DISPLAY_TFT, 104 OMAP_DSS_LCD_DISPLAY_TFT,
103 }; 105 };
104 106
105 enum omap_dss_load_mode { 107 enum omap_dss_load_mode {
106 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 108 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
107 OMAP_DSS_LOAD_CLUT_ONLY = 1, 109 OMAP_DSS_LOAD_CLUT_ONLY = 1,
108 OMAP_DSS_LOAD_FRAME_ONLY = 2, 110 OMAP_DSS_LOAD_FRAME_ONLY = 2,
109 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, 111 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
110 }; 112 };
111 113
112 enum omap_dss_trans_key_type { 114 enum omap_dss_trans_key_type {
113 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 115 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
114 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 116 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
115 }; 117 };
116 118
117 enum omap_rfbi_te_mode { 119 enum omap_rfbi_te_mode {
118 OMAP_DSS_RFBI_TE_MODE_1 = 1, 120 OMAP_DSS_RFBI_TE_MODE_1 = 1,
119 OMAP_DSS_RFBI_TE_MODE_2 = 2, 121 OMAP_DSS_RFBI_TE_MODE_2 = 2,
120 }; 122 };
121 123
122 enum omap_panel_config { 124 enum omap_panel_config {
123 OMAP_DSS_LCD_IVS = 1<<0, 125 OMAP_DSS_LCD_IVS = 1<<0,
124 OMAP_DSS_LCD_IHS = 1<<1, 126 OMAP_DSS_LCD_IHS = 1<<1,
125 OMAP_DSS_LCD_IPC = 1<<2, 127 OMAP_DSS_LCD_IPC = 1<<2,
126 OMAP_DSS_LCD_IEO = 1<<3, 128 OMAP_DSS_LCD_IEO = 1<<3,
127 OMAP_DSS_LCD_RF = 1<<4, 129 OMAP_DSS_LCD_RF = 1<<4,
128 OMAP_DSS_LCD_ONOFF = 1<<5, 130 OMAP_DSS_LCD_ONOFF = 1<<5,
129 131
130 OMAP_DSS_LCD_TFT = 1<<20, 132 OMAP_DSS_LCD_TFT = 1<<20,
131 }; 133 };
132 134
133 enum omap_dss_venc_type { 135 enum omap_dss_venc_type {
134 OMAP_DSS_VENC_TYPE_COMPOSITE, 136 OMAP_DSS_VENC_TYPE_COMPOSITE,
135 OMAP_DSS_VENC_TYPE_SVIDEO, 137 OMAP_DSS_VENC_TYPE_SVIDEO,
136 }; 138 };
137 139
138 enum omap_dss_dsi_pixel_format { 140 enum omap_dss_dsi_pixel_format {
139 OMAP_DSS_DSI_FMT_RGB888, 141 OMAP_DSS_DSI_FMT_RGB888,
140 OMAP_DSS_DSI_FMT_RGB666, 142 OMAP_DSS_DSI_FMT_RGB666,
141 OMAP_DSS_DSI_FMT_RGB666_PACKED, 143 OMAP_DSS_DSI_FMT_RGB666_PACKED,
142 OMAP_DSS_DSI_FMT_RGB565, 144 OMAP_DSS_DSI_FMT_RGB565,
143 }; 145 };
144 146
145 enum omap_dss_dsi_mode { 147 enum omap_dss_dsi_mode {
146 OMAP_DSS_DSI_CMD_MODE = 0, 148 OMAP_DSS_DSI_CMD_MODE = 0,
147 OMAP_DSS_DSI_VIDEO_MODE, 149 OMAP_DSS_DSI_VIDEO_MODE,
148 }; 150 };
149 151
150 enum omap_display_caps { 152 enum omap_display_caps {
151 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, 153 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
152 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, 154 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
153 }; 155 };
154 156
155 enum omap_dss_display_state { 157 enum omap_dss_display_state {
156 OMAP_DSS_DISPLAY_DISABLED = 0, 158 OMAP_DSS_DISPLAY_DISABLED = 0,
157 OMAP_DSS_DISPLAY_ACTIVE, 159 OMAP_DSS_DISPLAY_ACTIVE,
158 OMAP_DSS_DISPLAY_SUSPENDED, 160 OMAP_DSS_DISPLAY_SUSPENDED,
159 }; 161 };
160 162
163 enum omap_dss_audio_state {
164 OMAP_DSS_AUDIO_DISABLED = 0,
165 OMAP_DSS_AUDIO_ENABLED,
166 OMAP_DSS_AUDIO_CONFIGURED,
167 OMAP_DSS_AUDIO_PLAYING,
168 };
169
161 /* XXX perhaps this should be removed */ 170 /* XXX perhaps this should be removed */
162 enum omap_dss_overlay_managers { 171 enum omap_dss_overlay_managers {
163 OMAP_DSS_OVL_MGR_LCD, 172 OMAP_DSS_OVL_MGR_LCD,
164 OMAP_DSS_OVL_MGR_TV, 173 OMAP_DSS_OVL_MGR_TV,
165 OMAP_DSS_OVL_MGR_LCD2, 174 OMAP_DSS_OVL_MGR_LCD2,
166 }; 175 };
167 176
168 enum omap_dss_rotation_type { 177 enum omap_dss_rotation_type {
169 OMAP_DSS_ROT_DMA = 0, 178 OMAP_DSS_ROT_DMA = 0,
170 OMAP_DSS_ROT_VRFB = 1, 179 OMAP_DSS_ROT_VRFB = 1,
171 }; 180 };
172 181
173 /* clockwise rotation angle */ 182 /* clockwise rotation angle */
174 enum omap_dss_rotation_angle { 183 enum omap_dss_rotation_angle {
175 OMAP_DSS_ROT_0 = 0, 184 OMAP_DSS_ROT_0 = 0,
176 OMAP_DSS_ROT_90 = 1, 185 OMAP_DSS_ROT_90 = 1,
177 OMAP_DSS_ROT_180 = 2, 186 OMAP_DSS_ROT_180 = 2,
178 OMAP_DSS_ROT_270 = 3, 187 OMAP_DSS_ROT_270 = 3,
179 }; 188 };
180 189
181 enum omap_overlay_caps { 190 enum omap_overlay_caps {
182 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 191 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
183 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 192 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
184 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 193 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
185 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 194 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
186 }; 195 };
187 196
188 enum omap_overlay_manager_caps { 197 enum omap_overlay_manager_caps {
189 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ 198 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
190 }; 199 };
191 200
192 enum omap_dss_clk_source { 201 enum omap_dss_clk_source {
193 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK 202 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
194 * OMAP4: DSS_FCLK */ 203 * OMAP4: DSS_FCLK */
195 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK 204 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
196 * OMAP4: PLL1_CLK1 */ 205 * OMAP4: PLL1_CLK1 */
197 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK 206 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
198 * OMAP4: PLL1_CLK2 */ 207 * OMAP4: PLL1_CLK2 */
199 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ 208 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
200 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 209 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
201 }; 210 };
202 211
203 enum omap_hdmi_flags { 212 enum omap_hdmi_flags {
204 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, 213 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
205 }; 214 };
206 215
207 /* RFBI */ 216 /* RFBI */
208 217
209 struct rfbi_timings { 218 struct rfbi_timings {
210 int cs_on_time; 219 int cs_on_time;
211 int cs_off_time; 220 int cs_off_time;
212 int we_on_time; 221 int we_on_time;
213 int we_off_time; 222 int we_off_time;
214 int re_on_time; 223 int re_on_time;
215 int re_off_time; 224 int re_off_time;
216 int we_cycle_time; 225 int we_cycle_time;
217 int re_cycle_time; 226 int re_cycle_time;
218 int cs_pulse_width; 227 int cs_pulse_width;
219 int access_time; 228 int access_time;
220 229
221 int clk_div; 230 int clk_div;
222 231
223 u32 tim[5]; /* set by rfbi_convert_timings() */ 232 u32 tim[5]; /* set by rfbi_convert_timings() */
224 233
225 int converted; 234 int converted;
226 }; 235 };
227 236
228 void omap_rfbi_write_command(const void *buf, u32 len); 237 void omap_rfbi_write_command(const void *buf, u32 len);
229 void omap_rfbi_read_data(void *buf, u32 len); 238 void omap_rfbi_read_data(void *buf, u32 len);
230 void omap_rfbi_write_data(const void *buf, u32 len); 239 void omap_rfbi_write_data(const void *buf, u32 len);
231 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, 240 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
232 u16 x, u16 y, 241 u16 x, u16 y,
233 u16 w, u16 h); 242 u16 w, u16 h);
234 int omap_rfbi_enable_te(bool enable, unsigned line); 243 int omap_rfbi_enable_te(bool enable, unsigned line);
235 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, 244 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
236 unsigned hs_pulse_time, unsigned vs_pulse_time, 245 unsigned hs_pulse_time, unsigned vs_pulse_time,
237 int hs_pol_inv, int vs_pol_inv, int extif_div); 246 int hs_pol_inv, int vs_pol_inv, int extif_div);
238 void rfbi_bus_lock(void); 247 void rfbi_bus_lock(void);
239 void rfbi_bus_unlock(void); 248 void rfbi_bus_unlock(void);
240 249
241 /* DSI */ 250 /* DSI */
242 251
243 struct omap_dss_dsi_videomode_data { 252 struct omap_dss_dsi_videomode_data {
244 /* DSI video mode blanking data */ 253 /* DSI video mode blanking data */
245 /* Unit: byte clock cycles */ 254 /* Unit: byte clock cycles */
246 u16 hsa; 255 u16 hsa;
247 u16 hfp; 256 u16 hfp;
248 u16 hbp; 257 u16 hbp;
249 /* Unit: line clocks */ 258 /* Unit: line clocks */
250 u16 vsa; 259 u16 vsa;
251 u16 vfp; 260 u16 vfp;
252 u16 vbp; 261 u16 vbp;
253 262
254 /* DSI blanking modes */ 263 /* DSI blanking modes */
255 int blanking_mode; 264 int blanking_mode;
256 int hsa_blanking_mode; 265 int hsa_blanking_mode;
257 int hbp_blanking_mode; 266 int hbp_blanking_mode;
258 int hfp_blanking_mode; 267 int hfp_blanking_mode;
259 268
260 /* Video port sync events */ 269 /* Video port sync events */
261 int vp_de_pol; 270 int vp_de_pol;
262 int vp_hsync_pol; 271 int vp_hsync_pol;
263 int vp_vsync_pol; 272 int vp_vsync_pol;
264 bool vp_vsync_end; 273 bool vp_vsync_end;
265 bool vp_hsync_end; 274 bool vp_hsync_end;
266 275
267 bool ddr_clk_always_on; 276 bool ddr_clk_always_on;
268 int window_sync; 277 int window_sync;
269 }; 278 };
270 279
271 void dsi_bus_lock(struct omap_dss_device *dssdev); 280 void dsi_bus_lock(struct omap_dss_device *dssdev);
272 void dsi_bus_unlock(struct omap_dss_device *dssdev); 281 void dsi_bus_unlock(struct omap_dss_device *dssdev);
273 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 282 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
274 int len); 283 int len);
275 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 284 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
276 int len); 285 int len);
277 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); 286 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
278 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); 287 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
279 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 288 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
280 u8 param); 289 u8 param);
281 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, 290 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
282 u8 param); 291 u8 param);
283 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, 292 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
284 u8 param1, u8 param2); 293 u8 param1, u8 param2);
285 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 294 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
286 u8 *data, int len); 295 u8 *data, int len);
287 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 296 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
288 u8 *data, int len); 297 u8 *data, int len);
289 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 298 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
290 u8 *buf, int buflen); 299 u8 *buf, int buflen);
291 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, 300 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
292 int buflen); 301 int buflen);
293 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, 302 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
294 u8 *buf, int buflen); 303 u8 *buf, int buflen);
295 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, 304 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
296 u8 param1, u8 param2, u8 *buf, int buflen); 305 u8 param1, u8 param2, u8 *buf, int buflen);
297 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 306 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
298 u16 len); 307 u16 len);
299 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 308 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
300 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); 309 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
301 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); 310 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
302 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); 311 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
303 312
304 /* Board specific data */ 313 /* Board specific data */
305 struct omap_dss_board_info { 314 struct omap_dss_board_info {
306 int (*get_context_loss_count)(struct device *dev); 315 int (*get_context_loss_count)(struct device *dev);
307 int num_devices; 316 int num_devices;
308 struct omap_dss_device **devices; 317 struct omap_dss_device **devices;
309 struct omap_dss_device *default_device; 318 struct omap_dss_device *default_device;
310 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); 319 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
311 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); 320 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
312 int (*set_min_bus_tput)(struct device *dev, unsigned long r); 321 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
313 }; 322 };
314 323
315 /* Init with the board info */ 324 /* Init with the board info */
316 extern int omap_display_init(struct omap_dss_board_info *board_data); 325 extern int omap_display_init(struct omap_dss_board_info *board_data);
317 /* HDMI mux init*/ 326 /* HDMI mux init*/
318 extern int omap_hdmi_init(enum omap_hdmi_flags flags); 327 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
319 328
320 struct omap_video_timings { 329 struct omap_video_timings {
321 /* Unit: pixels */ 330 /* Unit: pixels */
322 u16 x_res; 331 u16 x_res;
323 /* Unit: pixels */ 332 /* Unit: pixels */
324 u16 y_res; 333 u16 y_res;
325 /* Unit: KHz */ 334 /* Unit: KHz */
326 u32 pixel_clock; 335 u32 pixel_clock;
327 /* Unit: pixel clocks */ 336 /* Unit: pixel clocks */
328 u16 hsw; /* Horizontal synchronization pulse width */ 337 u16 hsw; /* Horizontal synchronization pulse width */
329 /* Unit: pixel clocks */ 338 /* Unit: pixel clocks */
330 u16 hfp; /* Horizontal front porch */ 339 u16 hfp; /* Horizontal front porch */
331 /* Unit: pixel clocks */ 340 /* Unit: pixel clocks */
332 u16 hbp; /* Horizontal back porch */ 341 u16 hbp; /* Horizontal back porch */
333 /* Unit: line clocks */ 342 /* Unit: line clocks */
334 u16 vsw; /* Vertical synchronization pulse width */ 343 u16 vsw; /* Vertical synchronization pulse width */
335 /* Unit: line clocks */ 344 /* Unit: line clocks */
336 u16 vfp; /* Vertical front porch */ 345 u16 vfp; /* Vertical front porch */
337 /* Unit: line clocks */ 346 /* Unit: line clocks */
338 u16 vbp; /* Vertical back porch */ 347 u16 vbp; /* Vertical back porch */
339 }; 348 };
340 349
341 #ifdef CONFIG_OMAP2_DSS_VENC 350 #ifdef CONFIG_OMAP2_DSS_VENC
342 /* Hardcoded timings for tv modes. Venc only uses these to 351 /* Hardcoded timings for tv modes. Venc only uses these to
343 * identify the mode, and does not actually use the configs 352 * identify the mode, and does not actually use the configs
344 * itself. However, the configs should be something that 353 * itself. However, the configs should be something that
345 * a normal monitor can also show */ 354 * a normal monitor can also show */
346 extern const struct omap_video_timings omap_dss_pal_timings; 355 extern const struct omap_video_timings omap_dss_pal_timings;
347 extern const struct omap_video_timings omap_dss_ntsc_timings; 356 extern const struct omap_video_timings omap_dss_ntsc_timings;
348 #endif 357 #endif
349 358
350 struct omap_dss_cpr_coefs { 359 struct omap_dss_cpr_coefs {
351 s16 rr, rg, rb; 360 s16 rr, rg, rb;
352 s16 gr, gg, gb; 361 s16 gr, gg, gb;
353 s16 br, bg, bb; 362 s16 br, bg, bb;
354 }; 363 };
355 364
356 struct omap_overlay_info { 365 struct omap_overlay_info {
357 u32 paddr; 366 u32 paddr;
358 u32 p_uv_addr; /* for NV12 format */ 367 u32 p_uv_addr; /* for NV12 format */
359 u16 screen_width; 368 u16 screen_width;
360 u16 width; 369 u16 width;
361 u16 height; 370 u16 height;
362 enum omap_color_mode color_mode; 371 enum omap_color_mode color_mode;
363 u8 rotation; 372 u8 rotation;
364 enum omap_dss_rotation_type rotation_type; 373 enum omap_dss_rotation_type rotation_type;
365 bool mirror; 374 bool mirror;
366 375
367 u16 pos_x; 376 u16 pos_x;
368 u16 pos_y; 377 u16 pos_y;
369 u16 out_width; /* if 0, out_width == width */ 378 u16 out_width; /* if 0, out_width == width */
370 u16 out_height; /* if 0, out_height == height */ 379 u16 out_height; /* if 0, out_height == height */
371 u8 global_alpha; 380 u8 global_alpha;
372 u8 pre_mult_alpha; 381 u8 pre_mult_alpha;
373 u8 zorder; 382 u8 zorder;
374 }; 383 };
375 384
376 struct omap_overlay { 385 struct omap_overlay {
377 struct kobject kobj; 386 struct kobject kobj;
378 struct list_head list; 387 struct list_head list;
379 388
380 /* static fields */ 389 /* static fields */
381 const char *name; 390 const char *name;
382 enum omap_plane id; 391 enum omap_plane id;
383 enum omap_color_mode supported_modes; 392 enum omap_color_mode supported_modes;
384 enum omap_overlay_caps caps; 393 enum omap_overlay_caps caps;
385 394
386 /* dynamic fields */ 395 /* dynamic fields */
387 struct omap_overlay_manager *manager; 396 struct omap_overlay_manager *manager;
388 397
389 /* 398 /*
390 * The following functions do not block: 399 * The following functions do not block:
391 * 400 *
392 * is_enabled 401 * is_enabled
393 * set_overlay_info 402 * set_overlay_info
394 * get_overlay_info 403 * get_overlay_info
395 * 404 *
396 * The rest of the functions may block and cannot be called from 405 * The rest of the functions may block and cannot be called from
397 * interrupt context 406 * interrupt context
398 */ 407 */
399 408
400 int (*enable)(struct omap_overlay *ovl); 409 int (*enable)(struct omap_overlay *ovl);
401 int (*disable)(struct omap_overlay *ovl); 410 int (*disable)(struct omap_overlay *ovl);
402 bool (*is_enabled)(struct omap_overlay *ovl); 411 bool (*is_enabled)(struct omap_overlay *ovl);
403 412
404 int (*set_manager)(struct omap_overlay *ovl, 413 int (*set_manager)(struct omap_overlay *ovl,
405 struct omap_overlay_manager *mgr); 414 struct omap_overlay_manager *mgr);
406 int (*unset_manager)(struct omap_overlay *ovl); 415 int (*unset_manager)(struct omap_overlay *ovl);
407 416
408 int (*set_overlay_info)(struct omap_overlay *ovl, 417 int (*set_overlay_info)(struct omap_overlay *ovl,
409 struct omap_overlay_info *info); 418 struct omap_overlay_info *info);
410 void (*get_overlay_info)(struct omap_overlay *ovl, 419 void (*get_overlay_info)(struct omap_overlay *ovl,
411 struct omap_overlay_info *info); 420 struct omap_overlay_info *info);
412 421
413 int (*wait_for_go)(struct omap_overlay *ovl); 422 int (*wait_for_go)(struct omap_overlay *ovl);
414 }; 423 };
415 424
416 struct omap_overlay_manager_info { 425 struct omap_overlay_manager_info {
417 u32 default_color; 426 u32 default_color;
418 427
419 enum omap_dss_trans_key_type trans_key_type; 428 enum omap_dss_trans_key_type trans_key_type;
420 u32 trans_key; 429 u32 trans_key;
421 bool trans_enabled; 430 bool trans_enabled;
422 431
423 bool partial_alpha_enabled; 432 bool partial_alpha_enabled;
424 433
425 bool cpr_enable; 434 bool cpr_enable;
426 struct omap_dss_cpr_coefs cpr_coefs; 435 struct omap_dss_cpr_coefs cpr_coefs;
427 }; 436 };
428 437
429 struct omap_overlay_manager { 438 struct omap_overlay_manager {
430 struct kobject kobj; 439 struct kobject kobj;
431 440
432 /* static fields */ 441 /* static fields */
433 const char *name; 442 const char *name;
434 enum omap_channel id; 443 enum omap_channel id;
435 enum omap_overlay_manager_caps caps; 444 enum omap_overlay_manager_caps caps;
436 struct list_head overlays; 445 struct list_head overlays;
437 enum omap_display_type supported_displays; 446 enum omap_display_type supported_displays;
438 447
439 /* dynamic fields */ 448 /* dynamic fields */
440 struct omap_dss_device *device; 449 struct omap_dss_device *device;
441 450
442 /* 451 /*
443 * The following functions do not block: 452 * The following functions do not block:
444 * 453 *
445 * set_manager_info 454 * set_manager_info
446 * get_manager_info 455 * get_manager_info
447 * apply 456 * apply
448 * 457 *
449 * The rest of the functions may block and cannot be called from 458 * The rest of the functions may block and cannot be called from
450 * interrupt context 459 * interrupt context
451 */ 460 */
452 461
453 int (*set_device)(struct omap_overlay_manager *mgr, 462 int (*set_device)(struct omap_overlay_manager *mgr,
454 struct omap_dss_device *dssdev); 463 struct omap_dss_device *dssdev);
455 int (*unset_device)(struct omap_overlay_manager *mgr); 464 int (*unset_device)(struct omap_overlay_manager *mgr);
456 465
457 int (*set_manager_info)(struct omap_overlay_manager *mgr, 466 int (*set_manager_info)(struct omap_overlay_manager *mgr,
458 struct omap_overlay_manager_info *info); 467 struct omap_overlay_manager_info *info);
459 void (*get_manager_info)(struct omap_overlay_manager *mgr, 468 void (*get_manager_info)(struct omap_overlay_manager *mgr,
460 struct omap_overlay_manager_info *info); 469 struct omap_overlay_manager_info *info);
461 470
462 int (*apply)(struct omap_overlay_manager *mgr); 471 int (*apply)(struct omap_overlay_manager *mgr);
463 int (*wait_for_go)(struct omap_overlay_manager *mgr); 472 int (*wait_for_go)(struct omap_overlay_manager *mgr);
464 int (*wait_for_vsync)(struct omap_overlay_manager *mgr); 473 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
465 }; 474 };
466 475
467 /* 22 pins means 1 clk lane and 10 data lanes */ 476 /* 22 pins means 1 clk lane and 10 data lanes */
468 #define OMAP_DSS_MAX_DSI_PINS 22 477 #define OMAP_DSS_MAX_DSI_PINS 22
469 478
470 struct omap_dsi_pin_config { 479 struct omap_dsi_pin_config {
471 int num_pins; 480 int num_pins;
472 /* 481 /*
473 * pin numbers in the following order: 482 * pin numbers in the following order:
474 * clk+, clk- 483 * clk+, clk-
475 * data1+, data1- 484 * data1+, data1-
476 * data2+, data2- 485 * data2+, data2-
477 * ... 486 * ...
478 */ 487 */
479 int pins[OMAP_DSS_MAX_DSI_PINS]; 488 int pins[OMAP_DSS_MAX_DSI_PINS];
480 }; 489 };
481 490
482 struct omap_dss_device { 491 struct omap_dss_device {
483 struct device dev; 492 struct device dev;
484 493
485 enum omap_display_type type; 494 enum omap_display_type type;
486 495
487 enum omap_channel channel; 496 enum omap_channel channel;
488 497
489 union { 498 union {
490 struct { 499 struct {
491 u8 data_lines; 500 u8 data_lines;
492 } dpi; 501 } dpi;
493 502
494 struct { 503 struct {
495 u8 channel; 504 u8 channel;
496 u8 data_lines; 505 u8 data_lines;
497 } rfbi; 506 } rfbi;
498 507
499 struct { 508 struct {
500 u8 datapairs; 509 u8 datapairs;
501 } sdi; 510 } sdi;
502 511
503 struct { 512 struct {
504 int module; 513 int module;
505 514
506 bool ext_te; 515 bool ext_te;
507 u8 ext_te_gpio; 516 u8 ext_te_gpio;
508 } dsi; 517 } dsi;
509 518
510 struct { 519 struct {
511 enum omap_dss_venc_type type; 520 enum omap_dss_venc_type type;
512 bool invert_polarity; 521 bool invert_polarity;
513 } venc; 522 } venc;
514 } phy; 523 } phy;
515 524
516 struct { 525 struct {
517 struct { 526 struct {
518 struct { 527 struct {
519 u16 lck_div; 528 u16 lck_div;
520 u16 pck_div; 529 u16 pck_div;
521 enum omap_dss_clk_source lcd_clk_src; 530 enum omap_dss_clk_source lcd_clk_src;
522 } channel; 531 } channel;
523 532
524 enum omap_dss_clk_source dispc_fclk_src; 533 enum omap_dss_clk_source dispc_fclk_src;
525 } dispc; 534 } dispc;
526 535
527 struct { 536 struct {
528 /* regn is one greater than TRM's REGN value */ 537 /* regn is one greater than TRM's REGN value */
529 u16 regn; 538 u16 regn;
530 u16 regm; 539 u16 regm;
531 u16 regm_dispc; 540 u16 regm_dispc;
532 u16 regm_dsi; 541 u16 regm_dsi;
533 542
534 u16 lp_clk_div; 543 u16 lp_clk_div;
535 enum omap_dss_clk_source dsi_fclk_src; 544 enum omap_dss_clk_source dsi_fclk_src;
536 } dsi; 545 } dsi;
537 546
538 struct { 547 struct {
539 /* regn is one greater than TRM's REGN value */ 548 /* regn is one greater than TRM's REGN value */
540 u16 regn; 549 u16 regn;
541 u16 regm2; 550 u16 regm2;
542 } hdmi; 551 } hdmi;
543 } clocks; 552 } clocks;
544 553
545 struct { 554 struct {
546 struct omap_video_timings timings; 555 struct omap_video_timings timings;
547 556
548 int acbi; /* ac-bias pin transitions per interrupt */ 557 int acbi; /* ac-bias pin transitions per interrupt */
549 /* Unit: line clocks */ 558 /* Unit: line clocks */
550 int acb; /* ac-bias pin frequency */ 559 int acb; /* ac-bias pin frequency */
551 560
552 enum omap_panel_config config; 561 enum omap_panel_config config;
553 562
554 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 563 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
555 enum omap_dss_dsi_mode dsi_mode; 564 enum omap_dss_dsi_mode dsi_mode;
556 struct omap_dss_dsi_videomode_data dsi_vm_data; 565 struct omap_dss_dsi_videomode_data dsi_vm_data;
557 } panel; 566 } panel;
558 567
559 struct { 568 struct {
560 u8 pixel_size; 569 u8 pixel_size;
561 struct rfbi_timings rfbi_timings; 570 struct rfbi_timings rfbi_timings;
562 } ctrl; 571 } ctrl;
563 572
564 int reset_gpio; 573 int reset_gpio;
565 574
566 int max_backlight_level; 575 int max_backlight_level;
567 576
568 const char *name; 577 const char *name;
569 578
570 /* used to match device to driver */ 579 /* used to match device to driver */
571 const char *driver_name; 580 const char *driver_name;
572 581
573 void *data; 582 void *data;
574 583
575 struct omap_dss_driver *driver; 584 struct omap_dss_driver *driver;
576 585
577 /* helper variable for driver suspend/resume */ 586 /* helper variable for driver suspend/resume */
578 bool activate_after_resume; 587 bool activate_after_resume;
579 588
580 enum omap_display_caps caps; 589 enum omap_display_caps caps;
581 590
582 struct omap_overlay_manager *manager; 591 struct omap_overlay_manager *manager;
583 592
584 enum omap_dss_display_state state; 593 enum omap_dss_display_state state;
585 594
595 enum omap_dss_audio_state audio_state;
596
586 /* platform specific */ 597 /* platform specific */
587 int (*platform_enable)(struct omap_dss_device *dssdev); 598 int (*platform_enable)(struct omap_dss_device *dssdev);
588 void (*platform_disable)(struct omap_dss_device *dssdev); 599 void (*platform_disable)(struct omap_dss_device *dssdev);
589 int (*set_backlight)(struct omap_dss_device *dssdev, int level); 600 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
590 int (*get_backlight)(struct omap_dss_device *dssdev); 601 int (*get_backlight)(struct omap_dss_device *dssdev);
591 }; 602 };
592 603
593 struct omap_dss_hdmi_data 604 struct omap_dss_hdmi_data
594 { 605 {
595 int hpd_gpio; 606 int hpd_gpio;
596 }; 607 };
597 608
609 struct omap_dss_audio {
610 struct snd_aes_iec958 *iec;
611 struct snd_cea_861_aud_if *cea;
612 };
613
598 struct omap_dss_driver { 614 struct omap_dss_driver {
599 struct device_driver driver; 615 struct device_driver driver;
600 616
601 int (*probe)(struct omap_dss_device *); 617 int (*probe)(struct omap_dss_device *);
602 void (*remove)(struct omap_dss_device *); 618 void (*remove)(struct omap_dss_device *);
603 619
604 int (*enable)(struct omap_dss_device *display); 620 int (*enable)(struct omap_dss_device *display);
605 void (*disable)(struct omap_dss_device *display); 621 void (*disable)(struct omap_dss_device *display);
606 int (*suspend)(struct omap_dss_device *display); 622 int (*suspend)(struct omap_dss_device *display);
607 int (*resume)(struct omap_dss_device *display); 623 int (*resume)(struct omap_dss_device *display);
608 int (*run_test)(struct omap_dss_device *display, int test); 624 int (*run_test)(struct omap_dss_device *display, int test);
609 625
610 int (*update)(struct omap_dss_device *dssdev, 626 int (*update)(struct omap_dss_device *dssdev,
611 u16 x, u16 y, u16 w, u16 h); 627 u16 x, u16 y, u16 w, u16 h);
612 int (*sync)(struct omap_dss_device *dssdev); 628 int (*sync)(struct omap_dss_device *dssdev);
613 629
614 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 630 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
615 int (*get_te)(struct omap_dss_device *dssdev); 631 int (*get_te)(struct omap_dss_device *dssdev);
616 632
617 u8 (*get_rotate)(struct omap_dss_device *dssdev); 633 u8 (*get_rotate)(struct omap_dss_device *dssdev);
618 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); 634 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
619 635
620 bool (*get_mirror)(struct omap_dss_device *dssdev); 636 bool (*get_mirror)(struct omap_dss_device *dssdev);
621 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); 637 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
622 638
623 int (*memory_read)(struct omap_dss_device *dssdev, 639 int (*memory_read)(struct omap_dss_device *dssdev,
624 void *buf, size_t size, 640 void *buf, size_t size,
625 u16 x, u16 y, u16 w, u16 h); 641 u16 x, u16 y, u16 w, u16 h);
626 642
627 void (*get_resolution)(struct omap_dss_device *dssdev, 643 void (*get_resolution)(struct omap_dss_device *dssdev,
628 u16 *xres, u16 *yres); 644 u16 *xres, u16 *yres);
629 void (*get_dimensions)(struct omap_dss_device *dssdev, 645 void (*get_dimensions)(struct omap_dss_device *dssdev,
630 u32 *width, u32 *height); 646 u32 *width, u32 *height);
631 int (*get_recommended_bpp)(struct omap_dss_device *dssdev); 647 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
632 648
633 int (*check_timings)(struct omap_dss_device *dssdev, 649 int (*check_timings)(struct omap_dss_device *dssdev,
634 struct omap_video_timings *timings); 650 struct omap_video_timings *timings);
635 void (*set_timings)(struct omap_dss_device *dssdev, 651 void (*set_timings)(struct omap_dss_device *dssdev,
636 struct omap_video_timings *timings); 652 struct omap_video_timings *timings);
637 void (*get_timings)(struct omap_dss_device *dssdev, 653 void (*get_timings)(struct omap_dss_device *dssdev,
638 struct omap_video_timings *timings); 654 struct omap_video_timings *timings);
639 655
640 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 656 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
641 u32 (*get_wss)(struct omap_dss_device *dssdev); 657 u32 (*get_wss)(struct omap_dss_device *dssdev);
642 658
643 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 659 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
644 bool (*detect)(struct omap_dss_device *dssdev); 660 bool (*detect)(struct omap_dss_device *dssdev);
661
662 /*
663 * For display drivers that support audio. This encompasses
664 * HDMI and DisplayPort at the moment.
665 */
666 /*
667 * Note: These functions might sleep. Do not call while
668 * holding a spinlock/readlock.
669 */
670 int (*audio_enable)(struct omap_dss_device *dssdev);
671 void (*audio_disable)(struct omap_dss_device *dssdev);
672 bool (*audio_supported)(struct omap_dss_device *dssdev);
673 int (*audio_config)(struct omap_dss_device *dssdev,
674 struct omap_dss_audio *audio);
675 /* Note: These functions may not sleep */
676 int (*audio_start)(struct omap_dss_device *dssdev);
677 void (*audio_stop)(struct omap_dss_device *dssdev);
678
645 }; 679 };
646 680
647 int omap_dss_register_driver(struct omap_dss_driver *); 681 int omap_dss_register_driver(struct omap_dss_driver *);
648 void omap_dss_unregister_driver(struct omap_dss_driver *); 682 void omap_dss_unregister_driver(struct omap_dss_driver *);
649 683
650 void omap_dss_get_device(struct omap_dss_device *dssdev); 684 void omap_dss_get_device(struct omap_dss_device *dssdev);
651 void omap_dss_put_device(struct omap_dss_device *dssdev); 685 void omap_dss_put_device(struct omap_dss_device *dssdev);
652 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) 686 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
653 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); 687 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
654 struct omap_dss_device *omap_dss_find_device(void *data, 688 struct omap_dss_device *omap_dss_find_device(void *data,
655 int (*match)(struct omap_dss_device *dssdev, void *data)); 689 int (*match)(struct omap_dss_device *dssdev, void *data));
656 690
657 int omap_dss_start_device(struct omap_dss_device *dssdev); 691 int omap_dss_start_device(struct omap_dss_device *dssdev);
658 void omap_dss_stop_device(struct omap_dss_device *dssdev); 692 void omap_dss_stop_device(struct omap_dss_device *dssdev);
659 693
660 int omap_dss_get_num_overlay_managers(void); 694 int omap_dss_get_num_overlay_managers(void);
661 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); 695 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
662 696
663 int omap_dss_get_num_overlays(void); 697 int omap_dss_get_num_overlays(void);
664 struct omap_overlay *omap_dss_get_overlay(int num); 698 struct omap_overlay *omap_dss_get_overlay(int num);
665 699
666 void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 700 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
667 u16 *xres, u16 *yres); 701 u16 *xres, u16 *yres);
668 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 702 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
669 void omapdss_default_get_timings(struct omap_dss_device *dssdev, 703 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
670 struct omap_video_timings *timings); 704 struct omap_video_timings *timings);
671 705
672 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 706 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
673 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 707 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
674 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 708 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
675 709
676 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); 710 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
677 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, 711 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
678 unsigned long timeout); 712 unsigned long timeout);
679 713
680 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) 714 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
681 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) 715 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
682 716
683 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 717 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
684 bool enable); 718 bool enable);
685 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); 719 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
686 720
687 int omap_dsi_update(struct omap_dss_device *dssdev, int channel, 721 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
688 void (*callback)(int, void *), void *data); 722 void (*callback)(int, void *), void *data);
689 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); 723 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
690 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); 724 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
691 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); 725 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
692 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, 726 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
693 const struct omap_dsi_pin_config *pin_cfg); 727 const struct omap_dsi_pin_config *pin_cfg);
694 728
695 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); 729 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
696 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, 730 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
697 bool disconnect_lanes, bool enter_ulps); 731 bool disconnect_lanes, bool enter_ulps);
698 732
699 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); 733 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
700 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); 734 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
701 void dpi_set_timings(struct omap_dss_device *dssdev, 735 void dpi_set_timings(struct omap_dss_device *dssdev,
702 struct omap_video_timings *timings); 736 struct omap_video_timings *timings);
703 int dpi_check_timings(struct omap_dss_device *dssdev, 737 int dpi_check_timings(struct omap_dss_device *dssdev,
704 struct omap_video_timings *timings); 738 struct omap_video_timings *timings);
705 739
706 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); 740 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
707 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); 741 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
708 742
709 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); 743 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
710 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); 744 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
711 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, 745 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
712 u16 *x, u16 *y, u16 *w, u16 *h); 746 u16 *x, u16 *y, u16 *w, u16 *h);
713 int omap_rfbi_update(struct omap_dss_device *dssdev, 747 int omap_rfbi_update(struct omap_dss_device *dssdev,
714 u16 x, u16 y, u16 w, u16 h, 748 u16 x, u16 y, u16 w, u16 h,
715 void (*callback)(void *), void *data); 749 void (*callback)(void *), void *data);
716 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size, 750 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
717 int data_lines); 751 int data_lines);
718 752
719 #endif 753 #endif
720 754