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Commit 9ea359f7314132cbcb5a502d2d8ef095be1f45e4

Authored by Grygorii Strashko
Committed by Wolfram Sang
1 parent 7cc78f8fa0
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

i2c: davinci: generate STP always when NACK is received 

According to I2C specification the NACK should be handled as follows:
"When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal. The master can then generate either a STOP condition to
abort the transfer, or a repeated START condition to start a new transfer."
[I2C spec Rev. 6, 3.1.6: http://www.nxp.com/documents/user_manual/UM10204.pdf]

Currently the Davinci i2c driver interrupts the transfer on receipt of a
NACK but fails to send a STOP in some situations and so makes the bus
stuck until next I2C IP reset (idle/enable).

For example, the issue will happen during SMBus read transfer which
consists from two i2c messages write command/address and read data:

S Slave Address Wr A Command Code A Sr Slave Address Rd A D1..Dn A P
<--- write -----------------------> <--- read --------------------->

The I2C client device will send NACK if it can't recognize "Command Code"
and it's expected from I2C master to generate STP in this case.
But now, Davinci i2C driver will just exit with -EREMOTEIO and STP will
not be generated.

Hence, fix it by generating Stop condition (STP) always when NACK is received.

This patch fixes Davinci I2C in the same way it was done for OMAP I2C
commit cda2109a26eb ("i2c: omap: query STP always when NACK is received").

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reported-by: Hein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org

Showing 1 changed file with 3 additions and 5 deletions Inline Diff

drivers/i2c/busses/i2c-davinci.c
Diff comments   View file @ 9ea359f
1 /* 1 /*
2 * TI DAVINCI I2C adapter driver. 2 * TI DAVINCI I2C adapter driver.
3 * 3 *
4 * Copyright (C) 2006 Texas Instruments. 4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc. 5 * Copyright (C) 2007 MontaVista Software Inc.
6 * 6 *
7 * Updated by Vinod & Sudhakar Feb 2005 7 * Updated by Vinod & Sudhakar Feb 2005
8 * 8 *
9 * ---------------------------------------------------------------------------- 9 * ----------------------------------------------------------------------------
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version. 14 * (at your option) any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * ---------------------------------------------------------------------------- 20 * ----------------------------------------------------------------------------
21 * 21 *
22 */ 22 */
23 #include <linux/kernel.h> 23 #include <linux/kernel.h>
24 #include <linux/module.h> 24 #include <linux/module.h>
25 #include <linux/delay.h> 25 #include <linux/delay.h>
26 #include <linux/i2c.h> 26 #include <linux/i2c.h>
27 #include <linux/clk.h> 27 #include <linux/clk.h>
28 #include <linux/errno.h> 28 #include <linux/errno.h>
29 #include <linux/sched.h> 29 #include <linux/sched.h>
30 #include <linux/err.h> 30 #include <linux/err.h>
31 #include <linux/interrupt.h> 31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h> 32 #include <linux/platform_device.h>
33 #include <linux/io.h> 33 #include <linux/io.h>
34 #include <linux/slab.h> 34 #include <linux/slab.h>
35 #include <linux/cpufreq.h> 35 #include <linux/cpufreq.h>
36 #include <linux/gpio.h> 36 #include <linux/gpio.h>
37 #include <linux/of_device.h> 37 #include <linux/of_device.h>
38 #include <linux/platform_data/i2c-davinci.h> 38 #include <linux/platform_data/i2c-davinci.h>
39 39
40 /* ----- global defines ----------------------------------------------- */ 40 /* ----- global defines ----------------------------------------------- */
41 41
42 #define DAVINCI_I2C_TIMEOUT (1*HZ) 42 #define DAVINCI_I2C_TIMEOUT (1*HZ)
43 #define DAVINCI_I2C_MAX_TRIES 2 43 #define DAVINCI_I2C_MAX_TRIES 2
44 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ 44 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
45 DAVINCI_I2C_IMR_SCD | \ 45 DAVINCI_I2C_IMR_SCD | \
46 DAVINCI_I2C_IMR_ARDY | \ 46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \ 47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL) 48 DAVINCI_I2C_IMR_AL)
49 49
50 #define DAVINCI_I2C_OAR_REG 0x00 50 #define DAVINCI_I2C_OAR_REG 0x00
51 #define DAVINCI_I2C_IMR_REG 0x04 51 #define DAVINCI_I2C_IMR_REG 0x04
52 #define DAVINCI_I2C_STR_REG 0x08 52 #define DAVINCI_I2C_STR_REG 0x08
53 #define DAVINCI_I2C_CLKL_REG 0x0c 53 #define DAVINCI_I2C_CLKL_REG 0x0c
54 #define DAVINCI_I2C_CLKH_REG 0x10 54 #define DAVINCI_I2C_CLKH_REG 0x10
55 #define DAVINCI_I2C_CNT_REG 0x14 55 #define DAVINCI_I2C_CNT_REG 0x14
56 #define DAVINCI_I2C_DRR_REG 0x18 56 #define DAVINCI_I2C_DRR_REG 0x18
57 #define DAVINCI_I2C_SAR_REG 0x1c 57 #define DAVINCI_I2C_SAR_REG 0x1c
58 #define DAVINCI_I2C_DXR_REG 0x20 58 #define DAVINCI_I2C_DXR_REG 0x20
59 #define DAVINCI_I2C_MDR_REG 0x24 59 #define DAVINCI_I2C_MDR_REG 0x24
60 #define DAVINCI_I2C_IVR_REG 0x28 60 #define DAVINCI_I2C_IVR_REG 0x28
61 #define DAVINCI_I2C_EMDR_REG 0x2c 61 #define DAVINCI_I2C_EMDR_REG 0x2c
62 #define DAVINCI_I2C_PSC_REG 0x30 62 #define DAVINCI_I2C_PSC_REG 0x30
63 63
64 #define DAVINCI_I2C_IVR_AAS 0x07 64 #define DAVINCI_I2C_IVR_AAS 0x07
65 #define DAVINCI_I2C_IVR_SCD 0x06 65 #define DAVINCI_I2C_IVR_SCD 0x06
66 #define DAVINCI_I2C_IVR_XRDY 0x05 66 #define DAVINCI_I2C_IVR_XRDY 0x05
67 #define DAVINCI_I2C_IVR_RDR 0x04 67 #define DAVINCI_I2C_IVR_RDR 0x04
68 #define DAVINCI_I2C_IVR_ARDY 0x03 68 #define DAVINCI_I2C_IVR_ARDY 0x03
69 #define DAVINCI_I2C_IVR_NACK 0x02 69 #define DAVINCI_I2C_IVR_NACK 0x02
70 #define DAVINCI_I2C_IVR_AL 0x01 70 #define DAVINCI_I2C_IVR_AL 0x01
71 71
72 #define DAVINCI_I2C_STR_BB BIT(12) 72 #define DAVINCI_I2C_STR_BB BIT(12)
73 #define DAVINCI_I2C_STR_RSFULL BIT(11) 73 #define DAVINCI_I2C_STR_RSFULL BIT(11)
74 #define DAVINCI_I2C_STR_SCD BIT(5) 74 #define DAVINCI_I2C_STR_SCD BIT(5)
75 #define DAVINCI_I2C_STR_ARDY BIT(2) 75 #define DAVINCI_I2C_STR_ARDY BIT(2)
76 #define DAVINCI_I2C_STR_NACK BIT(1) 76 #define DAVINCI_I2C_STR_NACK BIT(1)
77 #define DAVINCI_I2C_STR_AL BIT(0) 77 #define DAVINCI_I2C_STR_AL BIT(0)
78 78
79 #define DAVINCI_I2C_MDR_NACK BIT(15) 79 #define DAVINCI_I2C_MDR_NACK BIT(15)
80 #define DAVINCI_I2C_MDR_STT BIT(13) 80 #define DAVINCI_I2C_MDR_STT BIT(13)
81 #define DAVINCI_I2C_MDR_STP BIT(11) 81 #define DAVINCI_I2C_MDR_STP BIT(11)
82 #define DAVINCI_I2C_MDR_MST BIT(10) 82 #define DAVINCI_I2C_MDR_MST BIT(10)
83 #define DAVINCI_I2C_MDR_TRX BIT(9) 83 #define DAVINCI_I2C_MDR_TRX BIT(9)
84 #define DAVINCI_I2C_MDR_XA BIT(8) 84 #define DAVINCI_I2C_MDR_XA BIT(8)
85 #define DAVINCI_I2C_MDR_RM BIT(7) 85 #define DAVINCI_I2C_MDR_RM BIT(7)
86 #define DAVINCI_I2C_MDR_IRS BIT(5) 86 #define DAVINCI_I2C_MDR_IRS BIT(5)
87 87
88 #define DAVINCI_I2C_IMR_AAS BIT(6) 88 #define DAVINCI_I2C_IMR_AAS BIT(6)
89 #define DAVINCI_I2C_IMR_SCD BIT(5) 89 #define DAVINCI_I2C_IMR_SCD BIT(5)
90 #define DAVINCI_I2C_IMR_XRDY BIT(4) 90 #define DAVINCI_I2C_IMR_XRDY BIT(4)
91 #define DAVINCI_I2C_IMR_RRDY BIT(3) 91 #define DAVINCI_I2C_IMR_RRDY BIT(3)
92 #define DAVINCI_I2C_IMR_ARDY BIT(2) 92 #define DAVINCI_I2C_IMR_ARDY BIT(2)
93 #define DAVINCI_I2C_IMR_NACK BIT(1) 93 #define DAVINCI_I2C_IMR_NACK BIT(1)
94 #define DAVINCI_I2C_IMR_AL BIT(0) 94 #define DAVINCI_I2C_IMR_AL BIT(0)
95 95
96 struct davinci_i2c_dev { 96 struct davinci_i2c_dev {
97 struct device *dev; 97 struct device *dev;
98 void __iomem *base; 98 void __iomem *base;
99 struct completion cmd_complete; 99 struct completion cmd_complete;
100 struct clk *clk; 100 struct clk *clk;
101 int cmd_err; 101 int cmd_err;
102 u8 *buf; 102 u8 *buf;
103 size_t buf_len; 103 size_t buf_len;
104 int irq; 104 int irq;
105 int stop; 105 int stop;
106 u8 terminate; 106 u8 terminate;
107 struct i2c_adapter adapter; 107 struct i2c_adapter adapter;
108 #ifdef CONFIG_CPU_FREQ 108 #ifdef CONFIG_CPU_FREQ
109 struct completion xfr_complete; 109 struct completion xfr_complete;
110 struct notifier_block freq_transition; 110 struct notifier_block freq_transition;
111 #endif 111 #endif
112 struct davinci_i2c_platform_data *pdata; 112 struct davinci_i2c_platform_data *pdata;
113 }; 113 };
114 114
115 /* default platform data to use if not supplied in the platform_device */ 115 /* default platform data to use if not supplied in the platform_device */
116 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { 116 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
117 .bus_freq = 100, 117 .bus_freq = 100,
118 .bus_delay = 0, 118 .bus_delay = 0,
119 }; 119 };
120 120
121 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 121 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
122 int reg, u16 val) 122 int reg, u16 val)
123 { 123 {
124 writew_relaxed(val, i2c_dev->base + reg); 124 writew_relaxed(val, i2c_dev->base + reg);
125 } 125 }
126 126
127 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 127 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
128 { 128 {
129 return readw_relaxed(i2c_dev->base + reg); 129 return readw_relaxed(i2c_dev->base + reg);
130 } 130 }
131 131
132 /* Generate a pulse on the i2c clock pin. */ 132 /* Generate a pulse on the i2c clock pin. */
133 static void davinci_i2c_clock_pulse(unsigned int scl_pin) 133 static void davinci_i2c_clock_pulse(unsigned int scl_pin)
134 { 134 {
135 u16 i; 135 u16 i;
136 136
137 if (scl_pin) { 137 if (scl_pin) {
138 /* Send high and low on the SCL line */ 138 /* Send high and low on the SCL line */
139 for (i = 0; i < 9; i++) { 139 for (i = 0; i < 9; i++) {
140 gpio_set_value(scl_pin, 0); 140 gpio_set_value(scl_pin, 0);
141 udelay(20); 141 udelay(20);
142 gpio_set_value(scl_pin, 1); 142 gpio_set_value(scl_pin, 1);
143 udelay(20); 143 udelay(20);
144 } 144 }
145 } 145 }
146 } 146 }
147 147
148 /* This routine does i2c bus recovery as specified in the 148 /* This routine does i2c bus recovery as specified in the
149 * i2c protocol Rev. 03 section 3.16 titled "Bus clear" 149 * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
150 */ 150 */
151 static void davinci_i2c_recover_bus(struct davinci_i2c_dev *dev) 151 static void davinci_i2c_recover_bus(struct davinci_i2c_dev *dev)
152 { 152 {
153 u32 flag = 0; 153 u32 flag = 0;
154 struct davinci_i2c_platform_data *pdata = dev->pdata; 154 struct davinci_i2c_platform_data *pdata = dev->pdata;
155 155
156 dev_err(dev->dev, "initiating i2c bus recovery\n"); 156 dev_err(dev->dev, "initiating i2c bus recovery\n");
157 /* Send NACK to the slave */ 157 /* Send NACK to the slave */
158 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 158 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
159 flag |= DAVINCI_I2C_MDR_NACK; 159 flag |= DAVINCI_I2C_MDR_NACK;
160 /* write the data into mode register */ 160 /* write the data into mode register */
161 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 161 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
162 davinci_i2c_clock_pulse(pdata->scl_pin); 162 davinci_i2c_clock_pulse(pdata->scl_pin);
163 /* Send STOP */ 163 /* Send STOP */
164 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 164 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
165 flag |= DAVINCI_I2C_MDR_STP; 165 flag |= DAVINCI_I2C_MDR_STP;
166 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 166 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
167 } 167 }
168 168
169 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 169 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
170 int val) 170 int val)
171 { 171 {
172 u16 w; 172 u16 w;
173 173
174 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); 174 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
175 if (!val) /* put I2C into reset */ 175 if (!val) /* put I2C into reset */
176 w &= ~DAVINCI_I2C_MDR_IRS; 176 w &= ~DAVINCI_I2C_MDR_IRS;
177 else /* take I2C out of reset */ 177 else /* take I2C out of reset */
178 w |= DAVINCI_I2C_MDR_IRS; 178 w |= DAVINCI_I2C_MDR_IRS;
179 179
180 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); 180 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
181 } 181 }
182 182
183 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 183 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
184 { 184 {
185 struct davinci_i2c_platform_data *pdata = dev->pdata; 185 struct davinci_i2c_platform_data *pdata = dev->pdata;
186 u16 psc; 186 u16 psc;
187 u32 clk; 187 u32 clk;
188 u32 d; 188 u32 d;
189 u32 clkh; 189 u32 clkh;
190 u32 clkl; 190 u32 clkl;
191 u32 input_clock = clk_get_rate(dev->clk); 191 u32 input_clock = clk_get_rate(dev->clk);
192 192
193 /* NOTE: I2C Clock divider programming info 193 /* NOTE: I2C Clock divider programming info
194 * As per I2C specs the following formulas provide prescaler 194 * As per I2C specs the following formulas provide prescaler
195 * and low/high divider values 195 * and low/high divider values
196 * input clk --> PSC Div -----------> ICCL/H Div --> output clock 196 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
197 * module clk 197 * module clk
198 * 198 *
199 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] 199 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
200 * 200 *
201 * Thus, 201 * Thus,
202 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; 202 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
203 * 203 *
204 * where if PSC == 0, d = 7, 204 * where if PSC == 0, d = 7,
205 * if PSC == 1, d = 6 205 * if PSC == 1, d = 6
206 * if PSC > 1 , d = 5 206 * if PSC > 1 , d = 5
207 */ 207 */
208 208
209 /* get minimum of 7 MHz clock, but max of 12 MHz */ 209 /* get minimum of 7 MHz clock, but max of 12 MHz */
210 psc = (input_clock / 7000000) - 1; 210 psc = (input_clock / 7000000) - 1;
211 if ((input_clock / (psc + 1)) > 12000000) 211 if ((input_clock / (psc + 1)) > 12000000)
212 psc++; /* better to run under spec than over */ 212 psc++; /* better to run under spec than over */
213 d = (psc >= 2) ? 5 : 7 - psc; 213 d = (psc >= 2) ? 5 : 7 - psc;
214 214
215 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); 215 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
216 clkh = clk >> 1; 216 clkh = clk >> 1;
217 clkl = clk - clkh; 217 clkl = clk - clkh;
218 218
219 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 219 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
220 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 220 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
221 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); 221 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
222 222
223 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); 223 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
224 } 224 }
225 225
226 /* 226 /*
227 * This function configures I2C and brings I2C out of reset. 227 * This function configures I2C and brings I2C out of reset.
228 * This function is called during I2C init function. This function 228 * This function is called during I2C init function. This function
229 * also gets called if I2C encounters any errors. 229 * also gets called if I2C encounters any errors.
230 */ 230 */
231 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 231 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
232 { 232 {
233 struct davinci_i2c_platform_data *pdata = dev->pdata; 233 struct davinci_i2c_platform_data *pdata = dev->pdata;
234 234
235 /* put I2C into reset */ 235 /* put I2C into reset */
236 davinci_i2c_reset_ctrl(dev, 0); 236 davinci_i2c_reset_ctrl(dev, 0);
237 237
238 /* compute clock dividers */ 238 /* compute clock dividers */
239 i2c_davinci_calc_clk_dividers(dev); 239 i2c_davinci_calc_clk_dividers(dev);
240 240
241 /* Respond at reserved "SMBus Host" slave address" (and zero); 241 /* Respond at reserved "SMBus Host" slave address" (and zero);
242 * we seem to have no option to not respond... 242 * we seem to have no option to not respond...
243 */ 243 */
244 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); 244 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
245 245
246 dev_dbg(dev->dev, "PSC = %d\n", 246 dev_dbg(dev->dev, "PSC = %d\n",
247 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 247 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
248 dev_dbg(dev->dev, "CLKL = %d\n", 248 dev_dbg(dev->dev, "CLKL = %d\n",
249 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 249 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
250 dev_dbg(dev->dev, "CLKH = %d\n", 250 dev_dbg(dev->dev, "CLKH = %d\n",
251 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 251 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
252 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 252 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
253 pdata->bus_freq, pdata->bus_delay); 253 pdata->bus_freq, pdata->bus_delay);
254 254
255 255
256 /* Take the I2C module out of reset: */ 256 /* Take the I2C module out of reset: */
257 davinci_i2c_reset_ctrl(dev, 1); 257 davinci_i2c_reset_ctrl(dev, 1);
258 258
259 /* Enable interrupts */ 259 /* Enable interrupts */
260 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); 260 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
261 261
262 return 0; 262 return 0;
263 } 263 }
264 264
265 /* 265 /*
266 * Waiting for bus not busy 266 * Waiting for bus not busy
267 */ 267 */
268 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, 268 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
269 char allow_sleep) 269 char allow_sleep)
270 { 270 {
271 unsigned long timeout; 271 unsigned long timeout;
272 static u16 to_cnt; 272 static u16 to_cnt;
273 273
274 timeout = jiffies + dev->adapter.timeout; 274 timeout = jiffies + dev->adapter.timeout;
275 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) 275 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
276 & DAVINCI_I2C_STR_BB) { 276 & DAVINCI_I2C_STR_BB) {
277 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { 277 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
278 if (time_after(jiffies, timeout)) { 278 if (time_after(jiffies, timeout)) {
279 dev_warn(dev->dev, 279 dev_warn(dev->dev,
280 "timeout waiting for bus ready\n"); 280 "timeout waiting for bus ready\n");
281 to_cnt++; 281 to_cnt++;
282 return -ETIMEDOUT; 282 return -ETIMEDOUT;
283 } else { 283 } else {
284 to_cnt = 0; 284 to_cnt = 0;
285 davinci_i2c_recover_bus(dev); 285 davinci_i2c_recover_bus(dev);
286 i2c_davinci_init(dev); 286 i2c_davinci_init(dev);
287 } 287 }
288 } 288 }
289 if (allow_sleep) 289 if (allow_sleep)
290 schedule_timeout(1); 290 schedule_timeout(1);
291 } 291 }
292 292
293 return 0; 293 return 0;
294 } 294 }
295 295
296 /* 296 /*
297 * Low level master read/write transaction. This function is called 297 * Low level master read/write transaction. This function is called
298 * from i2c_davinci_xfer. 298 * from i2c_davinci_xfer.
299 */ 299 */
300 static int 300 static int
301 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 301 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
302 { 302 {
303 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 303 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
304 struct davinci_i2c_platform_data *pdata = dev->pdata; 304 struct davinci_i2c_platform_data *pdata = dev->pdata;
305 u32 flag; 305 u32 flag;
306 u16 w; 306 u16 w;
307 int r; 307 int r;
308 308
309 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 309 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
310 if (pdata->bus_delay) 310 if (pdata->bus_delay)
311 udelay(pdata->bus_delay); 311 udelay(pdata->bus_delay);
312 312
313 /* set the slave address */ 313 /* set the slave address */
314 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); 314 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
315 315
316 dev->buf = msg->buf; 316 dev->buf = msg->buf;
317 dev->buf_len = msg->len; 317 dev->buf_len = msg->len;
318 dev->stop = stop; 318 dev->stop = stop;
319 319
320 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); 320 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
321 321
322 reinit_completion(&dev->cmd_complete); 322 reinit_completion(&dev->cmd_complete);
323 dev->cmd_err = 0; 323 dev->cmd_err = 0;
324 324
325 /* Take I2C out of reset and configure it as master */ 325 /* Take I2C out of reset and configure it as master */
326 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; 326 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
327 327
328 /* if the slave address is ten bit address, enable XA bit */ 328 /* if the slave address is ten bit address, enable XA bit */
329 if (msg->flags & I2C_M_TEN) 329 if (msg->flags & I2C_M_TEN)
330 flag |= DAVINCI_I2C_MDR_XA; 330 flag |= DAVINCI_I2C_MDR_XA;
331 if (!(msg->flags & I2C_M_RD)) 331 if (!(msg->flags & I2C_M_RD))
332 flag |= DAVINCI_I2C_MDR_TRX; 332 flag |= DAVINCI_I2C_MDR_TRX;
333 if (msg->len == 0) 333 if (msg->len == 0)
334 flag |= DAVINCI_I2C_MDR_RM; 334 flag |= DAVINCI_I2C_MDR_RM;
335 335
336 /* Enable receive or transmit interrupts */ 336 /* Enable receive or transmit interrupts */
337 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); 337 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
338 if (msg->flags & I2C_M_RD) 338 if (msg->flags & I2C_M_RD)
339 w |= DAVINCI_I2C_IMR_RRDY; 339 w |= DAVINCI_I2C_IMR_RRDY;
340 else 340 else
341 w |= DAVINCI_I2C_IMR_XRDY; 341 w |= DAVINCI_I2C_IMR_XRDY;
342 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); 342 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
343 343
344 dev->terminate = 0; 344 dev->terminate = 0;
345 345
346 /* 346 /*
347 * Write mode register first as needed for correct behaviour 347 * Write mode register first as needed for correct behaviour
348 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY 348 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
349 * occurring before we have loaded DXR 349 * occurring before we have loaded DXR
350 */ 350 */
351 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 351 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
352 352
353 /* 353 /*
354 * First byte should be set here, not after interrupt, 354 * First byte should be set here, not after interrupt,
355 * because transmit-data-ready interrupt can come before 355 * because transmit-data-ready interrupt can come before
356 * NACK-interrupt during sending of previous message and 356 * NACK-interrupt during sending of previous message and
357 * ICDXR may have wrong data 357 * ICDXR may have wrong data
358 * It also saves us one interrupt, slightly faster 358 * It also saves us one interrupt, slightly faster
359 */ 359 */
360 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { 360 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
361 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); 361 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
362 dev->buf_len--; 362 dev->buf_len--;
363 } 363 }
364 364
365 /* Set STT to begin transmit now DXR is loaded */ 365 /* Set STT to begin transmit now DXR is loaded */
366 flag |= DAVINCI_I2C_MDR_STT; 366 flag |= DAVINCI_I2C_MDR_STT;
367 if (stop && msg->len != 0) 367 if (stop && msg->len != 0)
368 flag |= DAVINCI_I2C_MDR_STP; 368 flag |= DAVINCI_I2C_MDR_STP;
369 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 369 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
370 370
371 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, 371 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
372 dev->adapter.timeout); 372 dev->adapter.timeout);
373 if (r == 0) { 373 if (r == 0) {
374 dev_err(dev->dev, "controller timed out\n"); 374 dev_err(dev->dev, "controller timed out\n");
375 davinci_i2c_recover_bus(dev); 375 davinci_i2c_recover_bus(dev);
376 i2c_davinci_init(dev); 376 i2c_davinci_init(dev);
377 dev->buf_len = 0; 377 dev->buf_len = 0;
378 return -ETIMEDOUT; 378 return -ETIMEDOUT;
379 } 379 }
380 if (dev->buf_len) { 380 if (dev->buf_len) {
381 /* This should be 0 if all bytes were transferred 381 /* This should be 0 if all bytes were transferred
382 * or dev->cmd_err denotes an error. 382 * or dev->cmd_err denotes an error.
383 * A signal may have aborted the transfer. 383 * A signal may have aborted the transfer.
384 */ 384 */
385 if (r >= 0) { 385 if (r >= 0) {
386 dev_err(dev->dev, "abnormal termination buf_len=%i\n", 386 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
387 dev->buf_len); 387 dev->buf_len);
388 r = -EREMOTEIO; 388 r = -EREMOTEIO;
389 } 389 }
390 dev->terminate = 1; 390 dev->terminate = 1;
391 wmb(); 391 wmb();
392 dev->buf_len = 0; 392 dev->buf_len = 0;
393 } 393 }
394 if (r < 0) 394 if (r < 0)
395 return r; 395 return r;
396 396
397 /* no error */ 397 /* no error */
398 if (likely(!dev->cmd_err)) 398 if (likely(!dev->cmd_err))
399 return msg->len; 399 return msg->len;
400 400
401 /* We have an error */ 401 /* We have an error */
402 if (dev->cmd_err & DAVINCI_I2C_STR_AL) { 402 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
403 i2c_davinci_init(dev); 403 i2c_davinci_init(dev);
404 return -EIO; 404 return -EIO;
405 } 405 }
406 406
407 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { 407 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
408 if (msg->flags & I2C_M_IGNORE_NAK) 408 if (msg->flags & I2C_M_IGNORE_NAK)
409 return msg->len; 409 return msg->len;
410 if (stop) { 410 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
411 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 411 w |= DAVINCI_I2C_MDR_STP;
412 w |= DAVINCI_I2C_MDR_STP; 412 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
413 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
414 }
415 return -EREMOTEIO; 413 return -EREMOTEIO;
416 } 414 }
417 return -EIO; 415 return -EIO;
418 } 416 }
419 417
420 /* 418 /*
421 * Prepare controller for a transaction and call i2c_davinci_xfer_msg 419 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
422 */ 420 */
423 static int 421 static int
424 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 422 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
425 { 423 {
426 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 424 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
427 int i; 425 int i;
428 int ret; 426 int ret;
429 427
430 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 428 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
431 429
432 ret = i2c_davinci_wait_bus_not_busy(dev, 1); 430 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
433 if (ret < 0) { 431 if (ret < 0) {
434 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 432 dev_warn(dev->dev, "timeout waiting for bus ready\n");
435 return ret; 433 return ret;
436 } 434 }
437 435
438 for (i = 0; i < num; i++) { 436 for (i = 0; i < num; i++) {
439 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); 437 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
440 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, 438 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
441 ret); 439 ret);
442 if (ret < 0) 440 if (ret < 0)
443 return ret; 441 return ret;
444 } 442 }
445 443
446 #ifdef CONFIG_CPU_FREQ 444 #ifdef CONFIG_CPU_FREQ
447 complete(&dev->xfr_complete); 445 complete(&dev->xfr_complete);
448 #endif 446 #endif
449 447
450 return num; 448 return num;
451 } 449 }
452 450
453 static u32 i2c_davinci_func(struct i2c_adapter *adap) 451 static u32 i2c_davinci_func(struct i2c_adapter *adap)
454 { 452 {
455 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 453 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
456 } 454 }
457 455
458 static void terminate_read(struct davinci_i2c_dev *dev) 456 static void terminate_read(struct davinci_i2c_dev *dev)
459 { 457 {
460 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 458 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
461 w |= DAVINCI_I2C_MDR_NACK; 459 w |= DAVINCI_I2C_MDR_NACK;
462 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 460 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
463 461
464 /* Throw away data */ 462 /* Throw away data */
465 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); 463 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
466 if (!dev->terminate) 464 if (!dev->terminate)
467 dev_err(dev->dev, "RDR IRQ while no data requested\n"); 465 dev_err(dev->dev, "RDR IRQ while no data requested\n");
468 } 466 }
469 static void terminate_write(struct davinci_i2c_dev *dev) 467 static void terminate_write(struct davinci_i2c_dev *dev)
470 { 468 {
471 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 469 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
472 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; 470 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
473 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 471 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
474 472
475 if (!dev->terminate) 473 if (!dev->terminate)
476 dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); 474 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
477 } 475 }
478 476
479 /* 477 /*
480 * Interrupt service routine. This gets called whenever an I2C interrupt 478 * Interrupt service routine. This gets called whenever an I2C interrupt
481 * occurs. 479 * occurs.
482 */ 480 */
483 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) 481 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
484 { 482 {
485 struct davinci_i2c_dev *dev = dev_id; 483 struct davinci_i2c_dev *dev = dev_id;
486 u32 stat; 484 u32 stat;
487 int count = 0; 485 int count = 0;
488 u16 w; 486 u16 w;
489 487
490 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { 488 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
491 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); 489 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
492 if (count++ == 100) { 490 if (count++ == 100) {
493 dev_warn(dev->dev, "Too much work in one IRQ\n"); 491 dev_warn(dev->dev, "Too much work in one IRQ\n");
494 break; 492 break;
495 } 493 }
496 494
497 switch (stat) { 495 switch (stat) {
498 case DAVINCI_I2C_IVR_AL: 496 case DAVINCI_I2C_IVR_AL:
499 /* Arbitration lost, must retry */ 497 /* Arbitration lost, must retry */
500 dev->cmd_err |= DAVINCI_I2C_STR_AL; 498 dev->cmd_err |= DAVINCI_I2C_STR_AL;
501 dev->buf_len = 0; 499 dev->buf_len = 0;
502 complete(&dev->cmd_complete); 500 complete(&dev->cmd_complete);
503 break; 501 break;
504 502
505 case DAVINCI_I2C_IVR_NACK: 503 case DAVINCI_I2C_IVR_NACK:
506 dev->cmd_err |= DAVINCI_I2C_STR_NACK; 504 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
507 dev->buf_len = 0; 505 dev->buf_len = 0;
508 complete(&dev->cmd_complete); 506 complete(&dev->cmd_complete);
509 break; 507 break;
510 508
511 case DAVINCI_I2C_IVR_ARDY: 509 case DAVINCI_I2C_IVR_ARDY:
512 davinci_i2c_write_reg(dev, 510 davinci_i2c_write_reg(dev,
513 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); 511 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
514 if (((dev->buf_len == 0) && (dev->stop != 0)) || 512 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
515 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { 513 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
516 w = davinci_i2c_read_reg(dev, 514 w = davinci_i2c_read_reg(dev,
517 DAVINCI_I2C_MDR_REG); 515 DAVINCI_I2C_MDR_REG);
518 w |= DAVINCI_I2C_MDR_STP; 516 w |= DAVINCI_I2C_MDR_STP;
519 davinci_i2c_write_reg(dev, 517 davinci_i2c_write_reg(dev,
520 DAVINCI_I2C_MDR_REG, w); 518 DAVINCI_I2C_MDR_REG, w);
521 } 519 }
522 complete(&dev->cmd_complete); 520 complete(&dev->cmd_complete);
523 break; 521 break;
524 522
525 case DAVINCI_I2C_IVR_RDR: 523 case DAVINCI_I2C_IVR_RDR:
526 if (dev->buf_len) { 524 if (dev->buf_len) {
527 *dev->buf++ = 525 *dev->buf++ =
528 davinci_i2c_read_reg(dev, 526 davinci_i2c_read_reg(dev,
529 DAVINCI_I2C_DRR_REG); 527 DAVINCI_I2C_DRR_REG);
530 dev->buf_len--; 528 dev->buf_len--;
531 if (dev->buf_len) 529 if (dev->buf_len)
532 continue; 530 continue;
533 531
534 davinci_i2c_write_reg(dev, 532 davinci_i2c_write_reg(dev,
535 DAVINCI_I2C_STR_REG, 533 DAVINCI_I2C_STR_REG,
536 DAVINCI_I2C_IMR_RRDY); 534 DAVINCI_I2C_IMR_RRDY);
537 } else { 535 } else {
538 /* signal can terminate transfer */ 536 /* signal can terminate transfer */
539 terminate_read(dev); 537 terminate_read(dev);
540 } 538 }
541 break; 539 break;
542 540
543 case DAVINCI_I2C_IVR_XRDY: 541 case DAVINCI_I2C_IVR_XRDY:
544 if (dev->buf_len) { 542 if (dev->buf_len) {
545 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, 543 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
546 *dev->buf++); 544 *dev->buf++);
547 dev->buf_len--; 545 dev->buf_len--;
548 if (dev->buf_len) 546 if (dev->buf_len)
549 continue; 547 continue;
550 548
551 w = davinci_i2c_read_reg(dev, 549 w = davinci_i2c_read_reg(dev,
552 DAVINCI_I2C_IMR_REG); 550 DAVINCI_I2C_IMR_REG);
553 w &= ~DAVINCI_I2C_IMR_XRDY; 551 w &= ~DAVINCI_I2C_IMR_XRDY;
554 davinci_i2c_write_reg(dev, 552 davinci_i2c_write_reg(dev,
555 DAVINCI_I2C_IMR_REG, 553 DAVINCI_I2C_IMR_REG,
556 w); 554 w);
557 } else { 555 } else {
558 /* signal can terminate transfer */ 556 /* signal can terminate transfer */
559 terminate_write(dev); 557 terminate_write(dev);
560 } 558 }
561 break; 559 break;
562 560
563 case DAVINCI_I2C_IVR_SCD: 561 case DAVINCI_I2C_IVR_SCD:
564 davinci_i2c_write_reg(dev, 562 davinci_i2c_write_reg(dev,
565 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); 563 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
566 complete(&dev->cmd_complete); 564 complete(&dev->cmd_complete);
567 break; 565 break;
568 566
569 case DAVINCI_I2C_IVR_AAS: 567 case DAVINCI_I2C_IVR_AAS:
570 dev_dbg(dev->dev, "Address as slave interrupt\n"); 568 dev_dbg(dev->dev, "Address as slave interrupt\n");
571 break; 569 break;
572 570
573 default: 571 default:
574 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); 572 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
575 break; 573 break;
576 } 574 }
577 } 575 }
578 576
579 return count ? IRQ_HANDLED : IRQ_NONE; 577 return count ? IRQ_HANDLED : IRQ_NONE;
580 } 578 }
581 579
582 #ifdef CONFIG_CPU_FREQ 580 #ifdef CONFIG_CPU_FREQ
583 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, 581 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
584 unsigned long val, void *data) 582 unsigned long val, void *data)
585 { 583 {
586 struct davinci_i2c_dev *dev; 584 struct davinci_i2c_dev *dev;
587 585
588 dev = container_of(nb, struct davinci_i2c_dev, freq_transition); 586 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
589 if (val == CPUFREQ_PRECHANGE) { 587 if (val == CPUFREQ_PRECHANGE) {
590 wait_for_completion(&dev->xfr_complete); 588 wait_for_completion(&dev->xfr_complete);
591 davinci_i2c_reset_ctrl(dev, 0); 589 davinci_i2c_reset_ctrl(dev, 0);
592 } else if (val == CPUFREQ_POSTCHANGE) { 590 } else if (val == CPUFREQ_POSTCHANGE) {
593 i2c_davinci_calc_clk_dividers(dev); 591 i2c_davinci_calc_clk_dividers(dev);
594 davinci_i2c_reset_ctrl(dev, 1); 592 davinci_i2c_reset_ctrl(dev, 1);
595 } 593 }
596 594
597 return 0; 595 return 0;
598 } 596 }
599 597
600 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 598 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
601 { 599 {
602 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition; 600 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
603 601
604 return cpufreq_register_notifier(&dev->freq_transition, 602 return cpufreq_register_notifier(&dev->freq_transition,
605 CPUFREQ_TRANSITION_NOTIFIER); 603 CPUFREQ_TRANSITION_NOTIFIER);
606 } 604 }
607 605
608 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 606 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
609 { 607 {
610 cpufreq_unregister_notifier(&dev->freq_transition, 608 cpufreq_unregister_notifier(&dev->freq_transition,
611 CPUFREQ_TRANSITION_NOTIFIER); 609 CPUFREQ_TRANSITION_NOTIFIER);
612 } 610 }
613 #else 611 #else
614 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 612 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
615 { 613 {
616 return 0; 614 return 0;
617 } 615 }
618 616
619 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 617 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
620 { 618 {
621 } 619 }
622 #endif 620 #endif
623 621
624 static struct i2c_algorithm i2c_davinci_algo = { 622 static struct i2c_algorithm i2c_davinci_algo = {
625 .master_xfer = i2c_davinci_xfer, 623 .master_xfer = i2c_davinci_xfer,
626 .functionality = i2c_davinci_func, 624 .functionality = i2c_davinci_func,
627 }; 625 };
628 626
629 static const struct of_device_id davinci_i2c_of_match[] = { 627 static const struct of_device_id davinci_i2c_of_match[] = {
630 {.compatible = "ti,davinci-i2c", }, 628 {.compatible = "ti,davinci-i2c", },
631 {}, 629 {},
632 }; 630 };
633 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match); 631 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
634 632
635 static int davinci_i2c_probe(struct platform_device *pdev) 633 static int davinci_i2c_probe(struct platform_device *pdev)
636 { 634 {
637 struct davinci_i2c_dev *dev; 635 struct davinci_i2c_dev *dev;
638 struct i2c_adapter *adap; 636 struct i2c_adapter *adap;
639 struct resource *mem, *irq; 637 struct resource *mem, *irq;
640 int r; 638 int r;
641 639
642 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 640 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
643 if (!irq) { 641 if (!irq) {
644 dev_err(&pdev->dev, "no irq resource?\n"); 642 dev_err(&pdev->dev, "no irq resource?\n");
645 return -ENODEV; 643 return -ENODEV;
646 } 644 }
647 645
648 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev), 646 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
649 GFP_KERNEL); 647 GFP_KERNEL);
650 if (!dev) { 648 if (!dev) {
651 dev_err(&pdev->dev, "Memory allocation failed\n"); 649 dev_err(&pdev->dev, "Memory allocation failed\n");
652 return -ENOMEM; 650 return -ENOMEM;
653 } 651 }
654 652
655 init_completion(&dev->cmd_complete); 653 init_completion(&dev->cmd_complete);
656 #ifdef CONFIG_CPU_FREQ 654 #ifdef CONFIG_CPU_FREQ
657 init_completion(&dev->xfr_complete); 655 init_completion(&dev->xfr_complete);
658 #endif 656 #endif
659 dev->dev = &pdev->dev; 657 dev->dev = &pdev->dev;
660 dev->irq = irq->start; 658 dev->irq = irq->start;
661 dev->pdata = dev_get_platdata(&pdev->dev); 659 dev->pdata = dev_get_platdata(&pdev->dev);
662 platform_set_drvdata(pdev, dev); 660 platform_set_drvdata(pdev, dev);
663 661
664 if (!dev->pdata && pdev->dev.of_node) { 662 if (!dev->pdata && pdev->dev.of_node) {
665 u32 prop; 663 u32 prop;
666 664
667 dev->pdata = devm_kzalloc(&pdev->dev, 665 dev->pdata = devm_kzalloc(&pdev->dev,
668 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL); 666 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
669 if (!dev->pdata) 667 if (!dev->pdata)
670 return -ENOMEM; 668 return -ENOMEM;
671 669
672 memcpy(dev->pdata, &davinci_i2c_platform_data_default, 670 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
673 sizeof(struct davinci_i2c_platform_data)); 671 sizeof(struct davinci_i2c_platform_data));
674 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency", 672 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
675 &prop)) 673 &prop))
676 dev->pdata->bus_freq = prop / 1000; 674 dev->pdata->bus_freq = prop / 1000;
677 } else if (!dev->pdata) { 675 } else if (!dev->pdata) {
678 dev->pdata = &davinci_i2c_platform_data_default; 676 dev->pdata = &davinci_i2c_platform_data_default;
679 } 677 }
680 678
681 dev->clk = devm_clk_get(&pdev->dev, NULL); 679 dev->clk = devm_clk_get(&pdev->dev, NULL);
682 if (IS_ERR(dev->clk)) 680 if (IS_ERR(dev->clk))
683 return -ENODEV; 681 return -ENODEV;
684 clk_prepare_enable(dev->clk); 682 clk_prepare_enable(dev->clk);
685 683
686 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 684 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
687 dev->base = devm_ioremap_resource(&pdev->dev, mem); 685 dev->base = devm_ioremap_resource(&pdev->dev, mem);
688 if (IS_ERR(dev->base)) { 686 if (IS_ERR(dev->base)) {
689 r = PTR_ERR(dev->base); 687 r = PTR_ERR(dev->base);
690 goto err_unuse_clocks; 688 goto err_unuse_clocks;
691 } 689 }
692 690
693 i2c_davinci_init(dev); 691 i2c_davinci_init(dev);
694 692
695 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0, 693 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
696 pdev->name, dev); 694 pdev->name, dev);
697 if (r) { 695 if (r) {
698 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 696 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
699 goto err_unuse_clocks; 697 goto err_unuse_clocks;
700 } 698 }
701 699
702 r = i2c_davinci_cpufreq_register(dev); 700 r = i2c_davinci_cpufreq_register(dev);
703 if (r) { 701 if (r) {
704 dev_err(&pdev->dev, "failed to register cpufreq\n"); 702 dev_err(&pdev->dev, "failed to register cpufreq\n");
705 goto err_unuse_clocks; 703 goto err_unuse_clocks;
706 } 704 }
707 705
708 adap = &dev->adapter; 706 adap = &dev->adapter;
709 i2c_set_adapdata(adap, dev); 707 i2c_set_adapdata(adap, dev);
710 adap->owner = THIS_MODULE; 708 adap->owner = THIS_MODULE;
711 adap->class = I2C_CLASS_DEPRECATED; 709 adap->class = I2C_CLASS_DEPRECATED;
712 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); 710 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
713 adap->algo = &i2c_davinci_algo; 711 adap->algo = &i2c_davinci_algo;
714 adap->dev.parent = &pdev->dev; 712 adap->dev.parent = &pdev->dev;
715 adap->timeout = DAVINCI_I2C_TIMEOUT; 713 adap->timeout = DAVINCI_I2C_TIMEOUT;
716 adap->dev.of_node = pdev->dev.of_node; 714 adap->dev.of_node = pdev->dev.of_node;
717 715
718 adap->nr = pdev->id; 716 adap->nr = pdev->id;
719 r = i2c_add_numbered_adapter(adap); 717 r = i2c_add_numbered_adapter(adap);
720 if (r) { 718 if (r) {
721 dev_err(&pdev->dev, "failure adding adapter\n"); 719 dev_err(&pdev->dev, "failure adding adapter\n");
722 goto err_unuse_clocks; 720 goto err_unuse_clocks;
723 } 721 }
724 722
725 return 0; 723 return 0;
726 724
727 err_unuse_clocks: 725 err_unuse_clocks:
728 clk_disable_unprepare(dev->clk); 726 clk_disable_unprepare(dev->clk);
729 dev->clk = NULL; 727 dev->clk = NULL;
730 return r; 728 return r;
731 } 729 }
732 730
733 static int davinci_i2c_remove(struct platform_device *pdev) 731 static int davinci_i2c_remove(struct platform_device *pdev)
734 { 732 {
735 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); 733 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
736 734
737 i2c_davinci_cpufreq_deregister(dev); 735 i2c_davinci_cpufreq_deregister(dev);
738 736
739 i2c_del_adapter(&dev->adapter); 737 i2c_del_adapter(&dev->adapter);
740 738
741 clk_disable_unprepare(dev->clk); 739 clk_disable_unprepare(dev->clk);
742 dev->clk = NULL; 740 dev->clk = NULL;
743 741
744 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); 742 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
745 743
746 return 0; 744 return 0;
747 } 745 }
748 746
749 #ifdef CONFIG_PM 747 #ifdef CONFIG_PM
750 static int davinci_i2c_suspend(struct device *dev) 748 static int davinci_i2c_suspend(struct device *dev)
751 { 749 {
752 struct platform_device *pdev = to_platform_device(dev); 750 struct platform_device *pdev = to_platform_device(dev);
753 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 751 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
754 752
755 /* put I2C into reset */ 753 /* put I2C into reset */
756 davinci_i2c_reset_ctrl(i2c_dev, 0); 754 davinci_i2c_reset_ctrl(i2c_dev, 0);
757 clk_disable_unprepare(i2c_dev->clk); 755 clk_disable_unprepare(i2c_dev->clk);
758 756
759 return 0; 757 return 0;
760 } 758 }
761 759
762 static int davinci_i2c_resume(struct device *dev) 760 static int davinci_i2c_resume(struct device *dev)
763 { 761 {
764 struct platform_device *pdev = to_platform_device(dev); 762 struct platform_device *pdev = to_platform_device(dev);
765 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 763 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
766 764
767 clk_prepare_enable(i2c_dev->clk); 765 clk_prepare_enable(i2c_dev->clk);
768 /* take I2C out of reset */ 766 /* take I2C out of reset */
769 davinci_i2c_reset_ctrl(i2c_dev, 1); 767 davinci_i2c_reset_ctrl(i2c_dev, 1);
770 768
771 return 0; 769 return 0;
772 } 770 }
773 771
774 static const struct dev_pm_ops davinci_i2c_pm = { 772 static const struct dev_pm_ops davinci_i2c_pm = {
775 .suspend = davinci_i2c_suspend, 773 .suspend = davinci_i2c_suspend,
776 .resume = davinci_i2c_resume, 774 .resume = davinci_i2c_resume,
777 }; 775 };
778 776
779 #define davinci_i2c_pm_ops (&davinci_i2c_pm) 777 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
780 #else 778 #else
781 #define davinci_i2c_pm_ops NULL 779 #define davinci_i2c_pm_ops NULL
782 #endif 780 #endif
783 781
784 /* work with hotplug and coldplug */ 782 /* work with hotplug and coldplug */
785 MODULE_ALIAS("platform:i2c_davinci"); 783 MODULE_ALIAS("platform:i2c_davinci");
786 784
787 static struct platform_driver davinci_i2c_driver = { 785 static struct platform_driver davinci_i2c_driver = {
788 .probe = davinci_i2c_probe, 786 .probe = davinci_i2c_probe,
789 .remove = davinci_i2c_remove, 787 .remove = davinci_i2c_remove,
790 .driver = { 788 .driver = {
791 .name = "i2c_davinci", 789 .name = "i2c_davinci",
792 .owner = THIS_MODULE, 790 .owner = THIS_MODULE,
793 .pm = davinci_i2c_pm_ops, 791 .pm = davinci_i2c_pm_ops,
794 .of_match_table = davinci_i2c_of_match, 792 .of_match_table = davinci_i2c_of_match,
795 }, 793 },
796 }; 794 };
797 795
798 /* I2C may be needed to bring up other drivers */ 796 /* I2C may be needed to bring up other drivers */
799 static int __init davinci_i2c_init_driver(void) 797 static int __init davinci_i2c_init_driver(void)
800 { 798 {
801 return platform_driver_register(&davinci_i2c_driver); 799 return platform_driver_register(&davinci_i2c_driver);
802 } 800 }
803 subsys_initcall(davinci_i2c_init_driver); 801 subsys_initcall(davinci_i2c_init_driver);
804 802
805 static void __exit davinci_i2c_exit_driver(void) 803 static void __exit davinci_i2c_exit_driver(void)
806 { 804 {
807 platform_driver_unregister(&davinci_i2c_driver); 805 platform_driver_unregister(&davinci_i2c_driver);
808 } 806 }
809 module_exit(davinci_i2c_exit_driver); 807 module_exit(davinci_i2c_exit_driver);
810 808
811 MODULE_AUTHOR("Texas Instruments India"); 809 MODULE_AUTHOR("Texas Instruments India");
812 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); 810 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
813 MODULE_LICENSE("GPL"); 811 MODULE_LICENSE("GPL");
814 812