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Commit a3576e471f71e8e7559fa85ef503b2278d9b04a1

Authored by Fabio Estevam
Committed by Greg Kroah-Hartman
1 parent 1fb91db57f

ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling 

commit 7a9f0604bd56936b2b18f49824e0e392dc7878c3 upstream.

GPIO2_5 is the reset GPIO for the USB3317 ULPI PHY. Instead of modelling it as
a regulator, the correct approach is to use the 'reset_gpios' property of the
"usb-nop-xceiv" node.

GPIO1_7 is the reset GPIO for the USB2517 USB hub. As we currently don't have
dt bindings to describe a HUB reset, let's keep using the regulator approach.

Rename the regulator to 'reg_hub_reset' to better describe its function and bind
it with the USB host1 port instead.

USB host support has been introduced by commit 9bf206a9d13be3 ("ARM: dts:
imx51-babbage: Add USB Host1 support"), which landed in 3.16 and it seems that
USB has only been functional due to previous bootloader initialization.

With this patch applied we can get USB host to work without relying on the
bootloader.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 1 changed file with 5 additions and 17 deletions Inline Diff

arch/arm/boot/dts/imx51-babbage.dts
Diff comments   View file @ a3576e4
1 /* 1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations: 7 * Version 2 or later at the following locations:
8 * 8 *
9 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13 /dts-v1/; 13 /dts-v1/;
14 #include "imx51.dtsi" 14 #include "imx51.dtsi"
15 15
16 / { 16 / {
17 model = "Freescale i.MX51 Babbage Board"; 17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51"; 18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19 19
20 chosen { 20 chosen {
21 stdout-path = &uart1; 21 stdout-path = &uart1;
22 }; 22 };
23 23
24 memory { 24 memory {
25 reg = <0x90000000 0x20000000>; 25 reg = <0x90000000 0x20000000>;
26 }; 26 };
27 27
28 clocks { 28 clocks {
29 ckih1 { 29 ckih1 {
30 clock-frequency = <22579200>; 30 clock-frequency = <22579200>;
31 }; 31 };
32 32
33 clk_26M: codec_clock { 33 clk_26M: codec_clock {
34 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
35 reg=<0>; 35 reg=<0>;
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <26000000>; 37 clock-frequency = <26000000>;
38 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 38 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
39 }; 39 };
40 }; 40 };
41 41
42 display0: display@di0 { 42 display0: display@di0 {
43 compatible = "fsl,imx-parallel-display"; 43 compatible = "fsl,imx-parallel-display";
44 interface-pix-fmt = "rgb24"; 44 interface-pix-fmt = "rgb24";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ipu_disp1>; 46 pinctrl-0 = <&pinctrl_ipu_disp1>;
47 display-timings { 47 display-timings {
48 native-mode = <&timing0>; 48 native-mode = <&timing0>;
49 timing0: dvi { 49 timing0: dvi {
50 clock-frequency = <65000000>; 50 clock-frequency = <65000000>;
51 hactive = <1024>; 51 hactive = <1024>;
52 vactive = <768>; 52 vactive = <768>;
53 hback-porch = <220>; 53 hback-porch = <220>;
54 hfront-porch = <40>; 54 hfront-porch = <40>;
55 vback-porch = <21>; 55 vback-porch = <21>;
56 vfront-porch = <7>; 56 vfront-porch = <7>;
57 hsync-len = <60>; 57 hsync-len = <60>;
58 vsync-len = <10>; 58 vsync-len = <10>;
59 }; 59 };
60 }; 60 };
61 61
62 port { 62 port {
63 display0_in: endpoint { 63 display0_in: endpoint {
64 remote-endpoint = <&ipu_di0_disp0>; 64 remote-endpoint = <&ipu_di0_disp0>;
65 }; 65 };
66 }; 66 };
67 }; 67 };
68 68
69 display1: display@di1 { 69 display1: display@di1 {
70 compatible = "fsl,imx-parallel-display"; 70 compatible = "fsl,imx-parallel-display";
71 interface-pix-fmt = "rgb565"; 71 interface-pix-fmt = "rgb565";
72 pinctrl-names = "default"; 72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_ipu_disp2>; 73 pinctrl-0 = <&pinctrl_ipu_disp2>;
74 status = "disabled"; 74 status = "disabled";
75 display-timings { 75 display-timings {
76 native-mode = <&timing1>; 76 native-mode = <&timing1>;
77 timing1: claawvga { 77 timing1: claawvga {
78 clock-frequency = <27000000>; 78 clock-frequency = <27000000>;
79 hactive = <800>; 79 hactive = <800>;
80 vactive = <480>; 80 vactive = <480>;
81 hback-porch = <40>; 81 hback-porch = <40>;
82 hfront-porch = <60>; 82 hfront-porch = <60>;
83 vback-porch = <10>; 83 vback-porch = <10>;
84 vfront-porch = <10>; 84 vfront-porch = <10>;
85 hsync-len = <20>; 85 hsync-len = <20>;
86 vsync-len = <10>; 86 vsync-len = <10>;
87 hsync-active = <0>; 87 hsync-active = <0>;
88 vsync-active = <0>; 88 vsync-active = <0>;
89 de-active = <1>; 89 de-active = <1>;
90 pixelclk-active = <0>; 90 pixelclk-active = <0>;
91 }; 91 };
92 }; 92 };
93 93
94 port { 94 port {
95 display1_in: endpoint { 95 display1_in: endpoint {
96 remote-endpoint = <&ipu_di1_disp1>; 96 remote-endpoint = <&ipu_di1_disp1>;
97 }; 97 };
98 }; 98 };
99 }; 99 };
100 100
101 gpio-keys { 101 gpio-keys {
102 compatible = "gpio-keys"; 102 compatible = "gpio-keys";
103 pinctrl-names = "default"; 103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_gpio_keys>; 104 pinctrl-0 = <&pinctrl_gpio_keys>;
105 105
106 power { 106 power {
107 label = "Power Button"; 107 label = "Power Button";
108 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 108 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
109 linux,code = <KEY_POWER>; 109 linux,code = <KEY_POWER>;
110 gpio-key,wakeup; 110 gpio-key,wakeup;
111 }; 111 };
112 }; 112 };
113 113
114 leds { 114 leds {
115 compatible = "gpio-leds"; 115 compatible = "gpio-leds";
116 pinctrl-names = "default"; 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gpio_leds>; 117 pinctrl-0 = <&pinctrl_gpio_leds>;
118 118
119 led-diagnostic { 119 led-diagnostic {
120 label = "diagnostic"; 120 label = "diagnostic";
121 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 121 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
122 }; 122 };
123 }; 123 };
124 124
125 regulators { 125 regulators {
126 compatible = "simple-bus"; 126 compatible = "simple-bus";
127 #address-cells = <1>; 127 #address-cells = <1>;
128 #size-cells = <0>; 128 #size-cells = <0>;
129 129
130 reg_usbh1_vbus: regulator@0 { 130 reg_hub_reset: regulator@0 {
131 compatible = "regulator-fixed"; 131 compatible = "regulator-fixed";
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh1reg>; 133 pinctrl-0 = <&pinctrl_usbotgreg>;
134 reg = <0>; 134 reg = <0>;
135 regulator-name = "usbh1_vbus"; 135 regulator-name = "hub_reset";
136 regulator-min-microvolt = <5000000>; 136 regulator-min-microvolt = <5000000>;
137 regulator-max-microvolt = <5000000>; 137 regulator-max-microvolt = <5000000>;
138 gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141
142 reg_usbotg_vbus: regulator@1 {
143 compatible = "regulator-fixed";
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_usbotgreg>;
146 reg = <1>;
147 regulator-name = "usbotg_vbus";
148 regulator-min-microvolt = <5000000>;
149 regulator-max-microvolt = <5000000>;
150 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 138 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
151 enable-active-high; 139 enable-active-high;
152 }; 140 };
153 }; 141 };
154 142
155 sound { 143 sound {
156 compatible = "fsl,imx51-babbage-sgtl5000", 144 compatible = "fsl,imx51-babbage-sgtl5000",
157 "fsl,imx-audio-sgtl5000"; 145 "fsl,imx-audio-sgtl5000";
158 model = "imx51-babbage-sgtl5000"; 146 model = "imx51-babbage-sgtl5000";
159 ssi-controller = <&ssi2>; 147 ssi-controller = <&ssi2>;
160 audio-codec = <&sgtl5000>; 148 audio-codec = <&sgtl5000>;
161 audio-routing = 149 audio-routing =
162 "MIC_IN", "Mic Jack", 150 "MIC_IN", "Mic Jack",
163 "Mic Jack", "Mic Bias", 151 "Mic Jack", "Mic Bias",
164 "Headphone Jack", "HP_OUT"; 152 "Headphone Jack", "HP_OUT";
165 mux-int-port = <2>; 153 mux-int-port = <2>;
166 mux-ext-port = <3>; 154 mux-ext-port = <3>;
167 }; 155 };
168 156
169 usbphy { 157 usbphy {
170 #address-cells = <1>; 158 #address-cells = <1>;
171 #size-cells = <0>; 159 #size-cells = <0>;
172 compatible = "simple-bus"; 160 compatible = "simple-bus";
173 161
174 usbh1phy: usbh1phy@0 { 162 usbh1phy: usbh1phy@0 {
175 compatible = "usb-nop-xceiv"; 163 compatible = "usb-nop-xceiv";
176 reg = <0>; 164 reg = <0>;
177 clocks = <&clks IMX5_CLK_DUMMY>; 165 clocks = <&clks IMX5_CLK_DUMMY>;
178 clock-names = "main_clk"; 166 clock-names = "main_clk";
167 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
179 }; 168 };
180 }; 169 };
181 }; 170 };
182 171
183 &audmux { 172 &audmux {
184 pinctrl-names = "default"; 173 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_audmux>; 174 pinctrl-0 = <&pinctrl_audmux>;
186 status = "okay"; 175 status = "okay";
187 }; 176 };
188 177
189 &ecspi1 { 178 &ecspi1 {
190 pinctrl-names = "default"; 179 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_ecspi1>; 180 pinctrl-0 = <&pinctrl_ecspi1>;
192 fsl,spi-num-chipselects = <2>; 181 fsl,spi-num-chipselects = <2>;
193 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, 182 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
194 <&gpio4 25 GPIO_ACTIVE_LOW>; 183 <&gpio4 25 GPIO_ACTIVE_LOW>;
195 status = "okay"; 184 status = "okay";
196 185
197 pmic: mc13892@0 { 186 pmic: mc13892@0 {
198 compatible = "fsl,mc13892"; 187 compatible = "fsl,mc13892";
199 pinctrl-names = "default"; 188 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_pmic>; 189 pinctrl-0 = <&pinctrl_pmic>;
201 spi-max-frequency = <6000000>; 190 spi-max-frequency = <6000000>;
202 spi-cs-high; 191 spi-cs-high;
203 reg = <0>; 192 reg = <0>;
204 interrupt-parent = <&gpio1>; 193 interrupt-parent = <&gpio1>;
205 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 194 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
206 fsl,mc13xxx-uses-rtc; 195 fsl,mc13xxx-uses-rtc;
207 196
208 regulators { 197 regulators {
209 sw1_reg: sw1 { 198 sw1_reg: sw1 {
210 regulator-min-microvolt = <600000>; 199 regulator-min-microvolt = <600000>;
211 regulator-max-microvolt = <1375000>; 200 regulator-max-microvolt = <1375000>;
212 regulator-boot-on; 201 regulator-boot-on;
213 regulator-always-on; 202 regulator-always-on;
214 }; 203 };
215 204
216 sw2_reg: sw2 { 205 sw2_reg: sw2 {
217 regulator-min-microvolt = <900000>; 206 regulator-min-microvolt = <900000>;
218 regulator-max-microvolt = <1850000>; 207 regulator-max-microvolt = <1850000>;
219 regulator-boot-on; 208 regulator-boot-on;
220 regulator-always-on; 209 regulator-always-on;
221 }; 210 };
222 211
223 sw3_reg: sw3 { 212 sw3_reg: sw3 {
224 regulator-min-microvolt = <1100000>; 213 regulator-min-microvolt = <1100000>;
225 regulator-max-microvolt = <1850000>; 214 regulator-max-microvolt = <1850000>;
226 regulator-boot-on; 215 regulator-boot-on;
227 regulator-always-on; 216 regulator-always-on;
228 }; 217 };
229 218
230 sw4_reg: sw4 { 219 sw4_reg: sw4 {
231 regulator-min-microvolt = <1100000>; 220 regulator-min-microvolt = <1100000>;
232 regulator-max-microvolt = <1850000>; 221 regulator-max-microvolt = <1850000>;
233 regulator-boot-on; 222 regulator-boot-on;
234 regulator-always-on; 223 regulator-always-on;
235 }; 224 };
236 225
237 vpll_reg: vpll { 226 vpll_reg: vpll {
238 regulator-min-microvolt = <1050000>; 227 regulator-min-microvolt = <1050000>;
239 regulator-max-microvolt = <1800000>; 228 regulator-max-microvolt = <1800000>;
240 regulator-boot-on; 229 regulator-boot-on;
241 regulator-always-on; 230 regulator-always-on;
242 }; 231 };
243 232
244 vdig_reg: vdig { 233 vdig_reg: vdig {
245 regulator-min-microvolt = <1650000>; 234 regulator-min-microvolt = <1650000>;
246 regulator-max-microvolt = <1650000>; 235 regulator-max-microvolt = <1650000>;
247 regulator-boot-on; 236 regulator-boot-on;
248 }; 237 };
249 238
250 vsd_reg: vsd { 239 vsd_reg: vsd {
251 regulator-min-microvolt = <1800000>; 240 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <3150000>; 241 regulator-max-microvolt = <3150000>;
253 }; 242 };
254 243
255 vusb2_reg: vusb2 { 244 vusb2_reg: vusb2 {
256 regulator-min-microvolt = <2400000>; 245 regulator-min-microvolt = <2400000>;
257 regulator-max-microvolt = <2775000>; 246 regulator-max-microvolt = <2775000>;
258 regulator-boot-on; 247 regulator-boot-on;
259 regulator-always-on; 248 regulator-always-on;
260 }; 249 };
261 250
262 vvideo_reg: vvideo { 251 vvideo_reg: vvideo {
263 regulator-min-microvolt = <2775000>; 252 regulator-min-microvolt = <2775000>;
264 regulator-max-microvolt = <2775000>; 253 regulator-max-microvolt = <2775000>;
265 }; 254 };
266 255
267 vaudio_reg: vaudio { 256 vaudio_reg: vaudio {
268 regulator-min-microvolt = <2300000>; 257 regulator-min-microvolt = <2300000>;
269 regulator-max-microvolt = <3000000>; 258 regulator-max-microvolt = <3000000>;
270 }; 259 };
271 260
272 vcam_reg: vcam { 261 vcam_reg: vcam {
273 regulator-min-microvolt = <2500000>; 262 regulator-min-microvolt = <2500000>;
274 regulator-max-microvolt = <3000000>; 263 regulator-max-microvolt = <3000000>;
275 }; 264 };
276 265
277 vgen1_reg: vgen1 { 266 vgen1_reg: vgen1 {
278 regulator-min-microvolt = <1200000>; 267 regulator-min-microvolt = <1200000>;
279 regulator-max-microvolt = <1200000>; 268 regulator-max-microvolt = <1200000>;
280 }; 269 };
281 270
282 vgen2_reg: vgen2 { 271 vgen2_reg: vgen2 {
283 regulator-min-microvolt = <1200000>; 272 regulator-min-microvolt = <1200000>;
284 regulator-max-microvolt = <3150000>; 273 regulator-max-microvolt = <3150000>;
285 regulator-always-on; 274 regulator-always-on;
286 }; 275 };
287 276
288 vgen3_reg: vgen3 { 277 vgen3_reg: vgen3 {
289 regulator-min-microvolt = <1800000>; 278 regulator-min-microvolt = <1800000>;
290 regulator-max-microvolt = <2900000>; 279 regulator-max-microvolt = <2900000>;
291 regulator-always-on; 280 regulator-always-on;
292 }; 281 };
293 }; 282 };
294 }; 283 };
295 284
296 flash: at45db321d@1 { 285 flash: at45db321d@1 {
297 #address-cells = <1>; 286 #address-cells = <1>;
298 #size-cells = <1>; 287 #size-cells = <1>;
299 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; 288 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
300 spi-max-frequency = <25000000>; 289 spi-max-frequency = <25000000>;
301 reg = <1>; 290 reg = <1>;
302 291
303 partition@0 { 292 partition@0 {
304 label = "U-Boot"; 293 label = "U-Boot";
305 reg = <0x0 0x40000>; 294 reg = <0x0 0x40000>;
306 read-only; 295 read-only;
307 }; 296 };
308 297
309 partition@40000 { 298 partition@40000 {
310 label = "Kernel"; 299 label = "Kernel";
311 reg = <0x40000 0x3c0000>; 300 reg = <0x40000 0x3c0000>;
312 }; 301 };
313 }; 302 };
314 }; 303 };
315 304
316 &esdhc1 { 305 &esdhc1 {
317 pinctrl-names = "default"; 306 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_esdhc1>; 307 pinctrl-0 = <&pinctrl_esdhc1>;
319 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 308 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
320 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 309 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
321 status = "okay"; 310 status = "okay";
322 }; 311 };
323 312
324 &esdhc2 { 313 &esdhc2 {
325 pinctrl-names = "default"; 314 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_esdhc2>; 315 pinctrl-0 = <&pinctrl_esdhc2>;
327 cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 316 cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
328 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 317 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
329 status = "okay"; 318 status = "okay";
330 }; 319 };
331 320
332 &fec { 321 &fec {
333 pinctrl-names = "default"; 322 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_fec>; 323 pinctrl-0 = <&pinctrl_fec>;
335 phy-mode = "mii"; 324 phy-mode = "mii";
336 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; 325 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
337 phy-reset-duration = <1>; 326 phy-reset-duration = <1>;
338 status = "okay"; 327 status = "okay";
339 }; 328 };
340 329
341 &i2c1 { 330 &i2c1 {
342 pinctrl-names = "default"; 331 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_i2c1>; 332 pinctrl-0 = <&pinctrl_i2c1>;
344 status = "okay"; 333 status = "okay";
345 }; 334 };
346 335
347 &i2c2 { 336 &i2c2 {
348 pinctrl-names = "default"; 337 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_i2c2>; 338 pinctrl-0 = <&pinctrl_i2c2>;
350 status = "okay"; 339 status = "okay";
351 340
352 sgtl5000: codec@0a { 341 sgtl5000: codec@0a {
353 compatible = "fsl,sgtl5000"; 342 compatible = "fsl,sgtl5000";
354 pinctrl-names = "default"; 343 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_clkcodec>; 344 pinctrl-0 = <&pinctrl_clkcodec>;
356 reg = <0x0a>; 345 reg = <0x0a>;
357 clocks = <&clk_26M>; 346 clocks = <&clk_26M>;
358 VDDA-supply = <&vdig_reg>; 347 VDDA-supply = <&vdig_reg>;
359 VDDIO-supply = <&vvideo_reg>; 348 VDDIO-supply = <&vvideo_reg>;
360 }; 349 };
361 }; 350 };
362 351
363 &ipu_di0_disp0 { 352 &ipu_di0_disp0 {
364 remote-endpoint = <&display0_in>; 353 remote-endpoint = <&display0_in>;
365 }; 354 };
366 355
367 &ipu_di1_disp1 { 356 &ipu_di1_disp1 {
368 remote-endpoint = <&display1_in>; 357 remote-endpoint = <&display1_in>;
369 }; 358 };
370 359
371 &kpp { 360 &kpp {
372 pinctrl-names = "default"; 361 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_kpp>; 362 pinctrl-0 = <&pinctrl_kpp>;
374 linux,keymap = < 363 linux,keymap = <
375 MATRIX_KEY(0, 0, KEY_UP) 364 MATRIX_KEY(0, 0, KEY_UP)
376 MATRIX_KEY(0, 1, KEY_DOWN) 365 MATRIX_KEY(0, 1, KEY_DOWN)
377 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) 366 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
378 MATRIX_KEY(0, 3, KEY_HOME) 367 MATRIX_KEY(0, 3, KEY_HOME)
379 MATRIX_KEY(1, 0, KEY_RIGHT) 368 MATRIX_KEY(1, 0, KEY_RIGHT)
380 MATRIX_KEY(1, 1, KEY_LEFT) 369 MATRIX_KEY(1, 1, KEY_LEFT)
381 MATRIX_KEY(1, 2, KEY_ENTER) 370 MATRIX_KEY(1, 2, KEY_ENTER)
382 MATRIX_KEY(1, 3, KEY_VOLUMEUP) 371 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
383 MATRIX_KEY(2, 0, KEY_F6) 372 MATRIX_KEY(2, 0, KEY_F6)
384 MATRIX_KEY(2, 1, KEY_F8) 373 MATRIX_KEY(2, 1, KEY_F8)
385 MATRIX_KEY(2, 2, KEY_F9) 374 MATRIX_KEY(2, 2, KEY_F9)
386 MATRIX_KEY(2, 3, KEY_F10) 375 MATRIX_KEY(2, 3, KEY_F10)
387 MATRIX_KEY(3, 0, KEY_F1) 376 MATRIX_KEY(3, 0, KEY_F1)
388 MATRIX_KEY(3, 1, KEY_F2) 377 MATRIX_KEY(3, 1, KEY_F2)
389 MATRIX_KEY(3, 2, KEY_F3) 378 MATRIX_KEY(3, 2, KEY_F3)
390 MATRIX_KEY(3, 3, KEY_POWER) 379 MATRIX_KEY(3, 3, KEY_POWER)
391 >; 380 >;
392 status = "okay"; 381 status = "okay";
393 }; 382 };
394 383
395 &ssi2 { 384 &ssi2 {
396 status = "okay"; 385 status = "okay";
397 }; 386 };
398 387
399 &uart1 { 388 &uart1 {
400 pinctrl-names = "default"; 389 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_uart1>; 390 pinctrl-0 = <&pinctrl_uart1>;
402 fsl,uart-has-rtscts; 391 fsl,uart-has-rtscts;
403 status = "okay"; 392 status = "okay";
404 }; 393 };
405 394
406 &uart2 { 395 &uart2 {
407 pinctrl-names = "default"; 396 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_uart2>; 397 pinctrl-0 = <&pinctrl_uart2>;
409 status = "okay"; 398 status = "okay";
410 }; 399 };
411 400
412 &uart3 { 401 &uart3 {
413 pinctrl-names = "default"; 402 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_uart3>; 403 pinctrl-0 = <&pinctrl_uart3>;
415 fsl,uart-has-rtscts; 404 fsl,uart-has-rtscts;
416 status = "okay"; 405 status = "okay";
417 }; 406 };
418 407
419 &usbh1 { 408 &usbh1 {
420 pinctrl-names = "default"; 409 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_usbh1>; 410 pinctrl-0 = <&pinctrl_usbh1>;
422 vbus-supply = <&reg_usbh1_vbus>; 411 vbus-supply = <&reg_hub_reset>;
423 fsl,usbphy = <&usbh1phy>; 412 fsl,usbphy = <&usbh1phy>;
424 phy_type = "ulpi"; 413 phy_type = "ulpi";
425 status = "okay"; 414 status = "okay";
426 }; 415 };
427 416
428 &usbotg { 417 &usbotg {
429 dr_mode = "otg"; 418 dr_mode = "otg";
430 disable-over-current; 419 disable-over-current;
431 phy_type = "utmi_wide"; 420 phy_type = "utmi_wide";
432 vbus-supply = <&reg_usbotg_vbus>;
433 status = "okay"; 421 status = "okay";
434 }; 422 };
435 423
436 &iomuxc { 424 &iomuxc {
437 imx51-babbage { 425 imx51-babbage {
438 pinctrl_audmux: audmuxgrp { 426 pinctrl_audmux: audmuxgrp {
439 fsl,pins = < 427 fsl,pins = <
440 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 428 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
441 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 429 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
442 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 430 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
443 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 431 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
444 >; 432 >;
445 }; 433 };
446 434
447 pinctrl_clkcodec: clkcodecgrp { 435 pinctrl_clkcodec: clkcodecgrp {
448 fsl,pins = < 436 fsl,pins = <
449 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 437 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
450 >; 438 >;
451 }; 439 };
452 440
453 pinctrl_ecspi1: ecspi1grp { 441 pinctrl_ecspi1: ecspi1grp {
454 fsl,pins = < 442 fsl,pins = <
455 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 443 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
456 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 444 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
457 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 445 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
458 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 446 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
459 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ 447 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
460 >; 448 >;
461 }; 449 };
462 450
463 pinctrl_esdhc1: esdhc1grp { 451 pinctrl_esdhc1: esdhc1grp {
464 fsl,pins = < 452 fsl,pins = <
465 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 453 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
466 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 454 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
467 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 455 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
468 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 456 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
469 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 457 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
470 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 458 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
471 MX51_PAD_GPIO1_0__GPIO1_0 0x100 459 MX51_PAD_GPIO1_0__GPIO1_0 0x100
472 MX51_PAD_GPIO1_1__GPIO1_1 0x100 460 MX51_PAD_GPIO1_1__GPIO1_1 0x100
473 >; 461 >;
474 }; 462 };
475 463
476 pinctrl_esdhc2: esdhc2grp { 464 pinctrl_esdhc2: esdhc2grp {
477 fsl,pins = < 465 fsl,pins = <
478 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 466 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
479 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 467 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
480 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 468 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
481 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 469 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
482 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 470 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
483 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 471 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
484 MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ 472 MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
485 MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ 473 MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
486 >; 474 >;
487 }; 475 };
488 476
489 pinctrl_fec: fecgrp { 477 pinctrl_fec: fecgrp {
490 fsl,pins = < 478 fsl,pins = <
491 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 479 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
492 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 480 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
493 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 481 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
494 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 482 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
495 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 483 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
496 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 484 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
497 MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 485 MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
498 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 486 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
499 MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 487 MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
500 MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 488 MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
501 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 489 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
502 MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 490 MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
503 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 491 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
504 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 492 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
505 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 493 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
506 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 494 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
507 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 495 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
508 MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 496 MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
509 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ 497 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
510 >; 498 >;
511 }; 499 };
512 500
513 pinctrl_gpio_keys: gpiokeysgrp { 501 pinctrl_gpio_keys: gpiokeysgrp {
514 fsl,pins = < 502 fsl,pins = <
515 MX51_PAD_EIM_A27__GPIO2_21 0x5 503 MX51_PAD_EIM_A27__GPIO2_21 0x5
516 >; 504 >;
517 }; 505 };
518 506
519 pinctrl_gpio_leds: gpioledsgrp { 507 pinctrl_gpio_leds: gpioledsgrp {
520 fsl,pins = < 508 fsl,pins = <
521 MX51_PAD_EIM_D22__GPIO2_6 0x80000000 509 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
522 >; 510 >;
523 }; 511 };
524 512
525 pinctrl_i2c1: i2c1grp { 513 pinctrl_i2c1: i2c1grp {
526 fsl,pins = < 514 fsl,pins = <
527 MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed 515 MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
528 MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed 516 MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
529 >; 517 >;
530 }; 518 };
531 519
532 pinctrl_i2c2: i2c2grp { 520 pinctrl_i2c2: i2c2grp {
533 fsl,pins = < 521 fsl,pins = <
534 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 522 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
535 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 523 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
536 >; 524 >;
537 }; 525 };
538 526
539 pinctrl_ipu_disp1: ipudisp1grp { 527 pinctrl_ipu_disp1: ipudisp1grp {
540 fsl,pins = < 528 fsl,pins = <
541 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 529 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
542 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 530 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
543 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 531 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
544 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 532 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
545 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 533 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
546 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 534 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
547 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 535 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
548 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 536 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
549 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 537 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
550 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 538 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
551 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 539 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
552 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 540 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
553 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 541 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
554 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 542 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
555 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 543 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
556 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 544 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
557 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 545 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
558 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 546 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
559 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 547 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
560 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 548 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
561 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 549 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
562 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 550 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
563 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 551 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
564 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 552 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
565 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 553 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
566 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 554 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
567 >; 555 >;
568 }; 556 };
569 557
570 pinctrl_ipu_disp2: ipudisp2grp { 558 pinctrl_ipu_disp2: ipudisp2grp {
571 fsl,pins = < 559 fsl,pins = <
572 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 560 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
573 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 561 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
574 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 562 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
575 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 563 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
576 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 564 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
577 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 565 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
578 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 566 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
579 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 567 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
580 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 568 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
581 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 569 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
582 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 570 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
583 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 571 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
584 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 572 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
585 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 573 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
586 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 574 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
587 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 575 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
588 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 576 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
589 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 577 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
590 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 578 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
591 MX51_PAD_DI_GP4__DI2_PIN15 0x5 579 MX51_PAD_DI_GP4__DI2_PIN15 0x5
592 >; 580 >;
593 }; 581 };
594 582
595 pinctrl_kpp: kppgrp { 583 pinctrl_kpp: kppgrp {
596 fsl,pins = < 584 fsl,pins = <
597 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 585 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
598 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 586 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
599 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 587 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
600 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 588 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
601 MX51_PAD_KEY_COL0__KEY_COL0 0xe8 589 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
602 MX51_PAD_KEY_COL1__KEY_COL1 0xe8 590 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
603 MX51_PAD_KEY_COL2__KEY_COL2 0xe8 591 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
604 MX51_PAD_KEY_COL3__KEY_COL3 0xe8 592 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
605 >; 593 >;
606 }; 594 };
607 595
608 pinctrl_pmic: pmicgrp { 596 pinctrl_pmic: pmicgrp {
609 fsl,pins = < 597 fsl,pins = <
610 MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ 598 MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
611 >; 599 >;
612 }; 600 };
613 601
614 pinctrl_uart1: uart1grp { 602 pinctrl_uart1: uart1grp {
615 fsl,pins = < 603 fsl,pins = <
616 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 604 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
617 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 605 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
618 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 606 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
619 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 607 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
620 >; 608 >;
621 }; 609 };
622 610
623 pinctrl_uart2: uart2grp { 611 pinctrl_uart2: uart2grp {
624 fsl,pins = < 612 fsl,pins = <
625 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 613 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
626 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 614 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
627 >; 615 >;
628 }; 616 };
629 617
630 pinctrl_uart3: uart3grp { 618 pinctrl_uart3: uart3grp {
631 fsl,pins = < 619 fsl,pins = <
632 MX51_PAD_EIM_D25__UART3_RXD 0x1c5 620 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
633 MX51_PAD_EIM_D26__UART3_TXD 0x1c5 621 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
634 MX51_PAD_EIM_D27__UART3_RTS 0x1c5 622 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
635 MX51_PAD_EIM_D24__UART3_CTS 0x1c5 623 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
636 >; 624 >;
637 }; 625 };
638 626
639 pinctrl_usbh1: usbh1grp { 627 pinctrl_usbh1: usbh1grp {
640 fsl,pins = < 628 fsl,pins = <
641 MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 629 MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
642 MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 630 MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
643 MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 631 MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
644 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 632 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
645 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 633 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
646 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 634 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
647 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 635 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
648 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 636 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
649 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 637 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
650 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 638 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
651 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 639 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
652 >; 640 >;
653 }; 641 };
654 642
655 pinctrl_usbh1reg: usbh1reggrp { 643 pinctrl_usbh1reg: usbh1reggrp {
656 fsl,pins = < 644 fsl,pins = <
657 MX51_PAD_EIM_D21__GPIO2_5 0x85 645 MX51_PAD_EIM_D21__GPIO2_5 0x85
658 >; 646 >;
659 }; 647 };
660 648
661 pinctrl_usbotgreg: usbotgreggrp { 649 pinctrl_usbotgreg: usbotgreggrp {
662 fsl,pins = < 650 fsl,pins = <
663 MX51_PAD_GPIO1_7__GPIO1_7 0x85 651 MX51_PAD_GPIO1_7__GPIO1_7 0x85
664 >; 652 >;
665 }; 653 };
666 }; 654 };
667 }; 655 };