Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit a6fa60f5614352eb53fc57b23f1984fed4e71eac

Authored by James Hogan 2016-04-22 17:38:46 +0800

Committed by Greg Kroah-Hartman 2016-06-02 03:15:52 +0800

Exists in smarct4x-processor-sdk-linux-03.00.00.04 and in 2 other branches

MIPS: KVM: Fix timer IRQ race when writing CP0_Compare

commit b45bacd2d048f405c7760e5cc9b60dd67708734f upstream.

Writing CP0_Compare clears the timer interrupt pending bit
(CP0_Cause.TI), but this wasn't being done atomically. If a timer
interrupt raced with the write of the guest CP0_Compare, the timer
interrupt could end up being pending even though the new CP0_Compare is
nowhere near CP0_Count.

We were already updating the hrtimer expiry with
kvm_mips_update_hrtimer(), which used both kvm_mips_freeze_hrtimer() and
kvm_mips_resume_hrtimer(). Close the race window by expanding out
kvm_mips_update_hrtimer(), and clearing CP0_Cause.TI and setting
CP0_Compare between the freeze and resume. Since the pending timer
interrupt should not be cleared when CP0_Compare is written via the KVM
user API, an ack argument is added to distinguish the source of the
write.

Fixes: e30492bbe95a ("MIPS: KVM: Rewrite count/compare timer emulation")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim KrÄmÃ¡Å™" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 3 changed files with 29 additions and 36 deletions Inline Diff

arch/mips/include/asm/kvm_host.h
arch/mips/kvm/emulate.c
arch/mips/kvm/trap_emul.c

arch/mips/include/asm/kvm_host.h

Diff comments View file @ a6fa60f

1	/*	1	/*
2	* This file is subject to the terms and conditions of the GNU General Public	2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive	3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.	4	* for more details.
5	*	5	*
6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.	6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7	* Authors: Sanjay Lal <sanjayl@kymasys.com>	7	* Authors: Sanjay Lal <sanjayl@kymasys.com>
8	*/	8	*/
9		9
10	#ifndef __MIPS_KVM_HOST_H__	10	#ifndef __MIPS_KVM_HOST_H__
11	#define __MIPS_KVM_HOST_H__	11	#define __MIPS_KVM_HOST_H__
12		12
13	#include <linux/mutex.h>	13	#include <linux/mutex.h>
14	#include <linux/hrtimer.h>	14	#include <linux/hrtimer.h>
15	#include <linux/interrupt.h>	15	#include <linux/interrupt.h>
16	#include <linux/types.h>	16	#include <linux/types.h>
17	#include <linux/kvm.h>	17	#include <linux/kvm.h>
18	#include <linux/kvm_types.h>	18	#include <linux/kvm_types.h>
19	#include <linux/threads.h>	19	#include <linux/threads.h>
20	#include <linux/spinlock.h>	20	#include <linux/spinlock.h>
21		21
22	/* MIPS KVM register ids */	22	/* MIPS KVM register ids */
23	#define MIPS_CP0_32(_R, _S) \	23	#define MIPS_CP0_32(_R, _S) \
24	(KVM_REG_MIPS_CP0 \| KVM_REG_SIZE_U32 \| (8 * (_R) + (_S)))	24	(KVM_REG_MIPS_CP0 \| KVM_REG_SIZE_U32 \| (8 * (_R) + (_S)))
25		25
26	#define MIPS_CP0_64(_R, _S) \	26	#define MIPS_CP0_64(_R, _S) \
27	(KVM_REG_MIPS_CP0 \| KVM_REG_SIZE_U64 \| (8 * (_R) + (_S)))	27	(KVM_REG_MIPS_CP0 \| KVM_REG_SIZE_U64 \| (8 * (_R) + (_S)))
28		28
29	#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)	29	#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30	#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)	30	#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31	#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)	31	#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32	#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)	32	#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33	#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)	33	#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34	#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)	34	#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35	#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)	35	#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36	#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)	36	#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37	#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)	37	#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38	#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)	38	#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39	#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)	39	#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40	#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)	40	#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41	#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)	41	#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42	#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)	42	#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43	#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)	43	#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44	#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)	44	#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45	#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)	45	#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
46	#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)	46	#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
47	#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)	47	#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
48	#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)	48	#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
49	#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)	49	#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
50	#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)	50	#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
51	#define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)	51	#define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
52	#define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)	52	#define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
53	#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)	53	#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
54	#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)	54	#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
55	#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)	55	#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
56		56
57		57
58	#define KVM_MAX_VCPUS 1	58	#define KVM_MAX_VCPUS 1
59	#define KVM_USER_MEM_SLOTS 8	59	#define KVM_USER_MEM_SLOTS 8
60	/* memory slots that does not exposed to userspace */	60	/* memory slots that does not exposed to userspace */
61	#define KVM_PRIVATE_MEM_SLOTS 0	61	#define KVM_PRIVATE_MEM_SLOTS 0
62		62
63	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1	63	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64	#define KVM_HALT_POLL_NS_DEFAULT 500000	64	#define KVM_HALT_POLL_NS_DEFAULT 500000
65		65
66		66
67		67
68	/* Special address that contains the comm page, used for reducing # of traps */	68	/* Special address that contains the comm page, used for reducing # of traps */
69	#define KVM_GUEST_COMMPAGE_ADDR 0x0	69	#define KVM_GUEST_COMMPAGE_ADDR 0x0
70		70
71	#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL \| ST0_ERL)) \|\| \	71	#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL \| ST0_ERL)) \|\| \
72	((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))	72	((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
73		73
74	#define KVM_GUEST_KUSEG 0x00000000UL	74	#define KVM_GUEST_KUSEG 0x00000000UL
75	#define KVM_GUEST_KSEG0 0x40000000UL	75	#define KVM_GUEST_KSEG0 0x40000000UL
76	#define KVM_GUEST_KSEG23 0x60000000UL	76	#define KVM_GUEST_KSEG23 0x60000000UL
77	#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)	77	#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
78	#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)	78	#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
79		79
80	#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG0)	80	#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG0)
81	#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG1)	81	#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG1)
82	#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG23)	82	#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG23)
83		83
84	/*	84	/*
85	* Map an address to a certain kernel segment	85	* Map an address to a certain kernel segment
86	*/	86	*/
87	#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG0)	87	#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG0)
88	#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG1)	88	#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG1)
89	#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG23)	89	#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) \| KVM_GUEST_KSEG23)
90		90
91	#define KVM_INVALID_PAGE 0xdeadbeef	91	#define KVM_INVALID_PAGE 0xdeadbeef
92	#define KVM_INVALID_INST 0xdeadbeef	92	#define KVM_INVALID_INST 0xdeadbeef
93	#define KVM_INVALID_ADDR 0xdeadbeef	93	#define KVM_INVALID_ADDR 0xdeadbeef
94		94
95	#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL	95	#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
96		96
97	#define GUEST_TICKS_PER_JIFFY (40000000/HZ)	97	#define GUEST_TICKS_PER_JIFFY (40000000/HZ)
98	#define MS_TO_NS(x) (x * 1E6L)	98	#define MS_TO_NS(x) (x * 1E6L)
99		99
100	#define CAUSEB_DC 27	100	#define CAUSEB_DC 27
101	#define CAUSEF_DC (_ULCAST_(1) << 27)	101	#define CAUSEF_DC (_ULCAST_(1) << 27)
102		102
103	extern atomic_t kvm_mips_instance;	103	extern atomic_t kvm_mips_instance;
104	extern pfn_t(kvm_mips_gfn_to_pfn) (struct kvm kvm, gfn_t gfn);	104	extern pfn_t(kvm_mips_gfn_to_pfn) (struct kvm kvm, gfn_t gfn);
105	extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);	105	extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
106	extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);	106	extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
107		107
108	struct kvm_vm_stat {	108	struct kvm_vm_stat {
109	u32 remote_tlb_flush;	109	u32 remote_tlb_flush;
110	};	110	};
111		111
112	struct kvm_vcpu_stat {	112	struct kvm_vcpu_stat {
113	u32 wait_exits;	113	u32 wait_exits;
114	u32 cache_exits;	114	u32 cache_exits;
115	u32 signal_exits;	115	u32 signal_exits;
116	u32 int_exits;	116	u32 int_exits;
117	u32 cop_unusable_exits;	117	u32 cop_unusable_exits;
118	u32 tlbmod_exits;	118	u32 tlbmod_exits;
119	u32 tlbmiss_ld_exits;	119	u32 tlbmiss_ld_exits;
120	u32 tlbmiss_st_exits;	120	u32 tlbmiss_st_exits;
121	u32 addrerr_st_exits;	121	u32 addrerr_st_exits;
122	u32 addrerr_ld_exits;	122	u32 addrerr_ld_exits;
123	u32 syscall_exits;	123	u32 syscall_exits;
124	u32 resvd_inst_exits;	124	u32 resvd_inst_exits;
125	u32 break_inst_exits;	125	u32 break_inst_exits;
126	u32 trap_inst_exits;	126	u32 trap_inst_exits;
127	u32 msa_fpe_exits;	127	u32 msa_fpe_exits;
128	u32 fpe_exits;	128	u32 fpe_exits;
129	u32 msa_disabled_exits;	129	u32 msa_disabled_exits;
130	u32 flush_dcache_exits;	130	u32 flush_dcache_exits;
131	u32 halt_successful_poll;	131	u32 halt_successful_poll;
132	u32 halt_attempted_poll;	132	u32 halt_attempted_poll;
133	u32 halt_wakeup;	133	u32 halt_wakeup;
134	};	134	};
135		135
136	enum kvm_mips_exit_types {	136	enum kvm_mips_exit_types {
137	WAIT_EXITS,	137	WAIT_EXITS,
138	CACHE_EXITS,	138	CACHE_EXITS,
139	SIGNAL_EXITS,	139	SIGNAL_EXITS,
140	INT_EXITS,	140	INT_EXITS,
141	COP_UNUSABLE_EXITS,	141	COP_UNUSABLE_EXITS,
142	TLBMOD_EXITS,	142	TLBMOD_EXITS,
143	TLBMISS_LD_EXITS,	143	TLBMISS_LD_EXITS,
144	TLBMISS_ST_EXITS,	144	TLBMISS_ST_EXITS,
145	ADDRERR_ST_EXITS,	145	ADDRERR_ST_EXITS,
146	ADDRERR_LD_EXITS,	146	ADDRERR_LD_EXITS,
147	SYSCALL_EXITS,	147	SYSCALL_EXITS,
148	RESVD_INST_EXITS,	148	RESVD_INST_EXITS,
149	BREAK_INST_EXITS,	149	BREAK_INST_EXITS,
150	TRAP_INST_EXITS,	150	TRAP_INST_EXITS,
151	MSA_FPE_EXITS,	151	MSA_FPE_EXITS,
152	FPE_EXITS,	152	FPE_EXITS,
153	MSA_DISABLED_EXITS,	153	MSA_DISABLED_EXITS,
154	FLUSH_DCACHE_EXITS,	154	FLUSH_DCACHE_EXITS,
155	MAX_KVM_MIPS_EXIT_TYPES	155	MAX_KVM_MIPS_EXIT_TYPES
156	};	156	};
157		157
158	struct kvm_arch_memory_slot {	158	struct kvm_arch_memory_slot {
159	};	159	};
160		160
161	struct kvm_arch {	161	struct kvm_arch {
162	/* Guest GVA->HPA page table */	162	/* Guest GVA->HPA page table */
163	unsigned long *guest_pmap;	163	unsigned long *guest_pmap;
164	unsigned long guest_pmap_npages;	164	unsigned long guest_pmap_npages;
165		165
166	/* Wired host TLB used for the commpage */	166	/* Wired host TLB used for the commpage */
167	int commpage_tlb;	167	int commpage_tlb;
168	};	168	};
169		169
170	#define N_MIPS_COPROC_REGS 32	170	#define N_MIPS_COPROC_REGS 32
171	#define N_MIPS_COPROC_SEL 8	171	#define N_MIPS_COPROC_SEL 8
172		172
173	struct mips_coproc {	173	struct mips_coproc {
174	unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];	174	unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
175	#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS	175	#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
176	unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];	176	unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
177	#endif	177	#endif
178	};	178	};
179		179
180	/*	180	/*
181	* Coprocessor 0 register names	181	* Coprocessor 0 register names
182	*/	182	*/
183	#define MIPS_CP0_TLB_INDEX 0	183	#define MIPS_CP0_TLB_INDEX 0
184	#define MIPS_CP0_TLB_RANDOM 1	184	#define MIPS_CP0_TLB_RANDOM 1
185	#define MIPS_CP0_TLB_LOW 2	185	#define MIPS_CP0_TLB_LOW 2
186	#define MIPS_CP0_TLB_LO0 2	186	#define MIPS_CP0_TLB_LO0 2
187	#define MIPS_CP0_TLB_LO1 3	187	#define MIPS_CP0_TLB_LO1 3
188	#define MIPS_CP0_TLB_CONTEXT 4	188	#define MIPS_CP0_TLB_CONTEXT 4
189	#define MIPS_CP0_TLB_PG_MASK 5	189	#define MIPS_CP0_TLB_PG_MASK 5
190	#define MIPS_CP0_TLB_WIRED 6	190	#define MIPS_CP0_TLB_WIRED 6
191	#define MIPS_CP0_HWRENA 7	191	#define MIPS_CP0_HWRENA 7
192	#define MIPS_CP0_BAD_VADDR 8	192	#define MIPS_CP0_BAD_VADDR 8
193	#define MIPS_CP0_COUNT 9	193	#define MIPS_CP0_COUNT 9
194	#define MIPS_CP0_TLB_HI 10	194	#define MIPS_CP0_TLB_HI 10
195	#define MIPS_CP0_COMPARE 11	195	#define MIPS_CP0_COMPARE 11
196	#define MIPS_CP0_STATUS 12	196	#define MIPS_CP0_STATUS 12
197	#define MIPS_CP0_CAUSE 13	197	#define MIPS_CP0_CAUSE 13
198	#define MIPS_CP0_EXC_PC 14	198	#define MIPS_CP0_EXC_PC 14
199	#define MIPS_CP0_PRID 15	199	#define MIPS_CP0_PRID 15
200	#define MIPS_CP0_CONFIG 16	200	#define MIPS_CP0_CONFIG 16
201	#define MIPS_CP0_LLADDR 17	201	#define MIPS_CP0_LLADDR 17
202	#define MIPS_CP0_WATCH_LO 18	202	#define MIPS_CP0_WATCH_LO 18
203	#define MIPS_CP0_WATCH_HI 19	203	#define MIPS_CP0_WATCH_HI 19
204	#define MIPS_CP0_TLB_XCONTEXT 20	204	#define MIPS_CP0_TLB_XCONTEXT 20
205	#define MIPS_CP0_ECC 26	205	#define MIPS_CP0_ECC 26
206	#define MIPS_CP0_CACHE_ERR 27	206	#define MIPS_CP0_CACHE_ERR 27
207	#define MIPS_CP0_TAG_LO 28	207	#define MIPS_CP0_TAG_LO 28
208	#define MIPS_CP0_TAG_HI 29	208	#define MIPS_CP0_TAG_HI 29
209	#define MIPS_CP0_ERROR_PC 30	209	#define MIPS_CP0_ERROR_PC 30
210	#define MIPS_CP0_DEBUG 23	210	#define MIPS_CP0_DEBUG 23
211	#define MIPS_CP0_DEPC 24	211	#define MIPS_CP0_DEPC 24
212	#define MIPS_CP0_PERFCNT 25	212	#define MIPS_CP0_PERFCNT 25
213	#define MIPS_CP0_ERRCTL 26	213	#define MIPS_CP0_ERRCTL 26
214	#define MIPS_CP0_DATA_LO 28	214	#define MIPS_CP0_DATA_LO 28
215	#define MIPS_CP0_DATA_HI 29	215	#define MIPS_CP0_DATA_HI 29
216	#define MIPS_CP0_DESAVE 31	216	#define MIPS_CP0_DESAVE 31
217		217
218	#define MIPS_CP0_CONFIG_SEL 0	218	#define MIPS_CP0_CONFIG_SEL 0
219	#define MIPS_CP0_CONFIG1_SEL 1	219	#define MIPS_CP0_CONFIG1_SEL 1
220	#define MIPS_CP0_CONFIG2_SEL 2	220	#define MIPS_CP0_CONFIG2_SEL 2
221	#define MIPS_CP0_CONFIG3_SEL 3	221	#define MIPS_CP0_CONFIG3_SEL 3
222	#define MIPS_CP0_CONFIG4_SEL 4	222	#define MIPS_CP0_CONFIG4_SEL 4
223	#define MIPS_CP0_CONFIG5_SEL 5	223	#define MIPS_CP0_CONFIG5_SEL 5
224		224
225	/* Config0 register bits */	225	/* Config0 register bits */
226	#define CP0C0_M 31	226	#define CP0C0_M 31
227	#define CP0C0_K23 28	227	#define CP0C0_K23 28
228	#define CP0C0_KU 25	228	#define CP0C0_KU 25
229	#define CP0C0_MDU 20	229	#define CP0C0_MDU 20
230	#define CP0C0_MM 17	230	#define CP0C0_MM 17
231	#define CP0C0_BM 16	231	#define CP0C0_BM 16
232	#define CP0C0_BE 15	232	#define CP0C0_BE 15
233	#define CP0C0_AT 13	233	#define CP0C0_AT 13
234	#define CP0C0_AR 10	234	#define CP0C0_AR 10
235	#define CP0C0_MT 7	235	#define CP0C0_MT 7
236	#define CP0C0_VI 3	236	#define CP0C0_VI 3
237	#define CP0C0_K0 0	237	#define CP0C0_K0 0
238		238
239	/* Config1 register bits */	239	/* Config1 register bits */
240	#define CP0C1_M 31	240	#define CP0C1_M 31
241	#define CP0C1_MMU 25	241	#define CP0C1_MMU 25
242	#define CP0C1_IS 22	242	#define CP0C1_IS 22
243	#define CP0C1_IL 19	243	#define CP0C1_IL 19
244	#define CP0C1_IA 16	244	#define CP0C1_IA 16
245	#define CP0C1_DS 13	245	#define CP0C1_DS 13
246	#define CP0C1_DL 10	246	#define CP0C1_DL 10
247	#define CP0C1_DA 7	247	#define CP0C1_DA 7
248	#define CP0C1_C2 6	248	#define CP0C1_C2 6
249	#define CP0C1_MD 5	249	#define CP0C1_MD 5
250	#define CP0C1_PC 4	250	#define CP0C1_PC 4
251	#define CP0C1_WR 3	251	#define CP0C1_WR 3
252	#define CP0C1_CA 2	252	#define CP0C1_CA 2
253	#define CP0C1_EP 1	253	#define CP0C1_EP 1
254	#define CP0C1_FP 0	254	#define CP0C1_FP 0
255		255
256	/* Config2 Register bits */	256	/* Config2 Register bits */
257	#define CP0C2_M 31	257	#define CP0C2_M 31
258	#define CP0C2_TU 28	258	#define CP0C2_TU 28
259	#define CP0C2_TS 24	259	#define CP0C2_TS 24
260	#define CP0C2_TL 20	260	#define CP0C2_TL 20
261	#define CP0C2_TA 16	261	#define CP0C2_TA 16
262	#define CP0C2_SU 12	262	#define CP0C2_SU 12
263	#define CP0C2_SS 8	263	#define CP0C2_SS 8
264	#define CP0C2_SL 4	264	#define CP0C2_SL 4
265	#define CP0C2_SA 0	265	#define CP0C2_SA 0
266		266
267	/* Config3 Register bits */	267	/* Config3 Register bits */
268	#define CP0C3_M 31	268	#define CP0C3_M 31
269	#define CP0C3_ISA_ON_EXC 16	269	#define CP0C3_ISA_ON_EXC 16
270	#define CP0C3_ULRI 13	270	#define CP0C3_ULRI 13
271	#define CP0C3_DSPP 10	271	#define CP0C3_DSPP 10
272	#define CP0C3_LPA 7	272	#define CP0C3_LPA 7
273	#define CP0C3_VEIC 6	273	#define CP0C3_VEIC 6
274	#define CP0C3_VInt 5	274	#define CP0C3_VInt 5
275	#define CP0C3_SP 4	275	#define CP0C3_SP 4
276	#define CP0C3_MT 2	276	#define CP0C3_MT 2
277	#define CP0C3_SM 1	277	#define CP0C3_SM 1
278	#define CP0C3_TL 0	278	#define CP0C3_TL 0
279		279
280	/* MMU types, the first four entries have the same layout as the	280	/* MMU types, the first four entries have the same layout as the
281	CP0C0_MT field. */	281	CP0C0_MT field. */
282	enum mips_mmu_types {	282	enum mips_mmu_types {
283	MMU_TYPE_NONE,	283	MMU_TYPE_NONE,
284	MMU_TYPE_R4000,	284	MMU_TYPE_R4000,
285	MMU_TYPE_RESERVED,	285	MMU_TYPE_RESERVED,
286	MMU_TYPE_FMT,	286	MMU_TYPE_FMT,
287	MMU_TYPE_R3000,	287	MMU_TYPE_R3000,
288	MMU_TYPE_R6000,	288	MMU_TYPE_R6000,
289	MMU_TYPE_R8000	289	MMU_TYPE_R8000
290	};	290	};
291		291
292	/*	292	/*
293	* Trap codes	293	* Trap codes
294	*/	294	*/
295	#define T_INT 0 /* Interrupt pending */	295	#define T_INT 0 /* Interrupt pending */
296	#define T_TLB_MOD 1 /* TLB modified fault */	296	#define T_TLB_MOD 1 /* TLB modified fault */
297	#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */	297	#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
298	#define T_TLB_ST_MISS 3 /* TLB miss on a store */	298	#define T_TLB_ST_MISS 3 /* TLB miss on a store */
299	#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */	299	#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
300	#define T_ADDR_ERR_ST 5 /* Address error on a store */	300	#define T_ADDR_ERR_ST 5 /* Address error on a store */
301	#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */	301	#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
302	#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */	302	#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
303	#define T_SYSCALL 8 /* System call */	303	#define T_SYSCALL 8 /* System call */
304	#define T_BREAK 9 /* Breakpoint */	304	#define T_BREAK 9 /* Breakpoint */
305	#define T_RES_INST 10 /* Reserved instruction exception */	305	#define T_RES_INST 10 /* Reserved instruction exception */
306	#define T_COP_UNUSABLE 11 /* Coprocessor unusable */	306	#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
307	#define T_OVFLOW 12 /* Arithmetic overflow */	307	#define T_OVFLOW 12 /* Arithmetic overflow */
308		308
309	/*	309	/*
310	* Trap definitions added for r4000 port.	310	* Trap definitions added for r4000 port.
311	*/	311	*/
312	#define T_TRAP 13 /* Trap instruction */	312	#define T_TRAP 13 /* Trap instruction */
313	#define T_VCEI 14 /* Virtual coherency exception */	313	#define T_VCEI 14 /* Virtual coherency exception */
314	#define T_MSAFPE 14 /* MSA floating point exception */	314	#define T_MSAFPE 14 /* MSA floating point exception */
315	#define T_FPE 15 /* Floating point exception */	315	#define T_FPE 15 /* Floating point exception */
316	#define T_MSADIS 21 /* MSA disabled exception */	316	#define T_MSADIS 21 /* MSA disabled exception */
317	#define T_WATCH 23 /* Watch address reference */	317	#define T_WATCH 23 /* Watch address reference */
318	#define T_VCED 31 /* Virtual coherency data */	318	#define T_VCED 31 /* Virtual coherency data */
319		319
320	/* Resume Flags */	320	/* Resume Flags */
321	#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */	321	#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
322	#define RESUME_FLAG_HOST (1<<1) /* Resume host? */	322	#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
323		323
324	#define RESUME_GUEST 0	324	#define RESUME_GUEST 0
325	#define RESUME_GUEST_DR RESUME_FLAG_DR	325	#define RESUME_GUEST_DR RESUME_FLAG_DR
326	#define RESUME_HOST RESUME_FLAG_HOST	326	#define RESUME_HOST RESUME_FLAG_HOST
327		327
328	enum emulation_result {	328	enum emulation_result {
329	EMULATE_DONE, /* no further processing */	329	EMULATE_DONE, /* no further processing */
330	EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */	330	EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
331	EMULATE_FAIL, /* can't emulate this instruction */	331	EMULATE_FAIL, /* can't emulate this instruction */
332	EMULATE_WAIT, /* WAIT instruction */	332	EMULATE_WAIT, /* WAIT instruction */
333	EMULATE_PRIV_FAIL,	333	EMULATE_PRIV_FAIL,
334	};	334	};
335		335
336	#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */	336	#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
337	#define MIPS3_PG_V 0x00000002 /* Valid */	337	#define MIPS3_PG_V 0x00000002 /* Valid */
338	#define MIPS3_PG_NV 0x00000000	338	#define MIPS3_PG_NV 0x00000000
339	#define MIPS3_PG_D 0x00000004 /* Dirty */	339	#define MIPS3_PG_D 0x00000004 /* Dirty */
340		340
341	#define mips3_paddr_to_tlbpfn(x) \	341	#define mips3_paddr_to_tlbpfn(x) \
342	(((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)	342	(((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
343	#define mips3_tlbpfn_to_paddr(x) \	343	#define mips3_tlbpfn_to_paddr(x) \
344	((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)	344	((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
345		345
346	#define MIPS3_PG_SHIFT 6	346	#define MIPS3_PG_SHIFT 6
347	#define MIPS3_PG_FRAME 0x3fffffc0	347	#define MIPS3_PG_FRAME 0x3fffffc0
348		348
349	#define VPN2_MASK 0xffffe000	349	#define VPN2_MASK 0xffffe000
350	#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \	350	#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
351	((x).tlb_lo1 & MIPS3_PG_G))	351	((x).tlb_lo1 & MIPS3_PG_G))
352	#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)	352	#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
353	#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)	353	#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
354	#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \	354	#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
355	? ((x).tlb_lo1 & MIPS3_PG_V) \	355	? ((x).tlb_lo1 & MIPS3_PG_V) \
356	: ((x).tlb_lo0 & MIPS3_PG_V))	356	: ((x).tlb_lo0 & MIPS3_PG_V))
357	#define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \	357	#define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
358	((y) & VPN2_MASK & ~(x).tlb_mask))	358	((y) & VPN2_MASK & ~(x).tlb_mask))
359	#define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) \|\| \	359	#define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) \|\| \
360	TLB_ASID(x) == ((y) & ASID_MASK))	360	TLB_ASID(x) == ((y) & ASID_MASK))
361		361
362	struct kvm_mips_tlb {	362	struct kvm_mips_tlb {
363	long tlb_mask;	363	long tlb_mask;
364	long tlb_hi;	364	long tlb_hi;
365	long tlb_lo0;	365	long tlb_lo0;
366	long tlb_lo1;	366	long tlb_lo1;
367	};	367	};
368		368
369	#define KVM_MIPS_FPU_FPU 0x1	369	#define KVM_MIPS_FPU_FPU 0x1
370	#define KVM_MIPS_FPU_MSA 0x2	370	#define KVM_MIPS_FPU_MSA 0x2
371		371
372	#define KVM_MIPS_GUEST_TLB_SIZE 64	372	#define KVM_MIPS_GUEST_TLB_SIZE 64
373	struct kvm_vcpu_arch {	373	struct kvm_vcpu_arch {
374	void host_ebase, guest_ebase;	374	void host_ebase, guest_ebase;
375	unsigned long host_stack;	375	unsigned long host_stack;
376	unsigned long host_gp;	376	unsigned long host_gp;
377		377
378	/* Host CP0 registers used when handling exits from guest */	378	/* Host CP0 registers used when handling exits from guest */
379	unsigned long host_cp0_badvaddr;	379	unsigned long host_cp0_badvaddr;
380	unsigned long host_cp0_cause;	380	unsigned long host_cp0_cause;
381	unsigned long host_cp0_epc;	381	unsigned long host_cp0_epc;
382	unsigned long host_cp0_entryhi;	382	unsigned long host_cp0_entryhi;
383	uint32_t guest_inst;	383	uint32_t guest_inst;
384		384
385	/* GPRS */	385	/* GPRS */
386	unsigned long gprs[32];	386	unsigned long gprs[32];
387	unsigned long hi;	387	unsigned long hi;
388	unsigned long lo;	388	unsigned long lo;
389	unsigned long pc;	389	unsigned long pc;
390		390
391	/* FPU State */	391	/* FPU State */
392	struct mips_fpu_struct fpu;	392	struct mips_fpu_struct fpu;
393	/* Which FPU state is loaded (KVM_MIPS_FPU_) /	393	/* Which FPU state is loaded (KVM_MIPS_FPU_) /
394	unsigned int fpu_inuse;	394	unsigned int fpu_inuse;
395		395
396	/* COP0 State */	396	/* COP0 State */
397	struct mips_coproc *cop0;	397	struct mips_coproc *cop0;
398		398
399	/* Host KSEG0 address of the EI/DI offset */	399	/* Host KSEG0 address of the EI/DI offset */
400	void *kseg0_commpage;	400	void *kseg0_commpage;
401		401
402	u32 io_gpr; /* GPR used as IO source/target */	402	u32 io_gpr; /* GPR used as IO source/target */
403		403
404	struct hrtimer comparecount_timer;	404	struct hrtimer comparecount_timer;
405	/* Count timer control KVM register */	405	/* Count timer control KVM register */
406	uint32_t count_ctl;	406	uint32_t count_ctl;
407	/* Count bias from the raw time */	407	/* Count bias from the raw time */
408	uint32_t count_bias;	408	uint32_t count_bias;
409	/* Frequency of timer in Hz */	409	/* Frequency of timer in Hz */
410	uint32_t count_hz;	410	uint32_t count_hz;
411	/* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */	411	/* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
412	s64 count_dyn_bias;	412	s64 count_dyn_bias;
413	/* Resume time */	413	/* Resume time */
414	ktime_t count_resume;	414	ktime_t count_resume;
415	/* Period of timer tick in ns */	415	/* Period of timer tick in ns */
416	u64 count_period;	416	u64 count_period;
417		417
418	/* Bitmask of exceptions that are pending */	418	/* Bitmask of exceptions that are pending */
419	unsigned long pending_exceptions;	419	unsigned long pending_exceptions;
420		420
421	/* Bitmask of pending exceptions to be cleared */	421	/* Bitmask of pending exceptions to be cleared */
422	unsigned long pending_exceptions_clr;	422	unsigned long pending_exceptions_clr;
423		423
424	unsigned long pending_load_cause;	424	unsigned long pending_load_cause;
425		425
426	/* Save/Restore the entryhi register when are are preempted/scheduled back in */	426	/* Save/Restore the entryhi register when are are preempted/scheduled back in */
427	unsigned long preempt_entryhi;	427	unsigned long preempt_entryhi;
428		428
429	/* S/W Based TLB for guest */	429	/* S/W Based TLB for guest */
430	struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];	430	struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
431		431
432	/* Cached guest kernel/user ASIDs */	432	/* Cached guest kernel/user ASIDs */
433	uint32_t guest_user_asid[NR_CPUS];	433	uint32_t guest_user_asid[NR_CPUS];
434	uint32_t guest_kernel_asid[NR_CPUS];	434	uint32_t guest_kernel_asid[NR_CPUS];
435	struct mm_struct guest_kernel_mm, guest_user_mm;	435	struct mm_struct guest_kernel_mm, guest_user_mm;
436		436
437	int last_sched_cpu;	437	int last_sched_cpu;
438		438
439	/* WAIT executed */	439	/* WAIT executed */
440	int wait;	440	int wait;
441		441
442	u8 fpu_enabled;	442	u8 fpu_enabled;
443	u8 msa_enabled;	443	u8 msa_enabled;
444	};	444	};
445		445
446		446
447	#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])	447	#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
448	#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)	448	#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
449	#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])	449	#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
450	#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])	450	#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
451	#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])	451	#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
452	#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))	452	#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
453	#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])	453	#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
454	#define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))	454	#define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
455	#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])	455	#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
456	#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))	456	#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
457	#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])	457	#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
458	#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))	458	#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
459	#define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])	459	#define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
460	#define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))	460	#define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
461	#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])	461	#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
462	#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))	462	#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
463	#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])	463	#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
464	#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))	464	#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
465	#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])	465	#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
466	#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))	466	#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
467	#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])	467	#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
468	#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))	468	#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
469	#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])	469	#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
470	#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))	470	#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
471	#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])	471	#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
472	#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))	472	#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
473	#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])	473	#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
474	#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))	474	#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
475	#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])	475	#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
476	#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))	476	#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
477	#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])	477	#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
478	#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))	478	#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
479	#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])	479	#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
480	#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))	480	#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
481	#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])	481	#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
482	#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])	482	#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
483	#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])	483	#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
484	#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])	484	#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
485	#define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])	485	#define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
486	#define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])	486	#define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
487	#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])	487	#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
488	#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))	488	#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
489	#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))	489	#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
490	#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))	490	#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
491	#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))	491	#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
492	#define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))	492	#define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
493	#define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))	493	#define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
494	#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))	494	#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
495	#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])	495	#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
496	#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))	496	#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
497		497
498	/*	498	/*
499	* Some of the guest registers may be modified asynchronously (e.g. from a	499	* Some of the guest registers may be modified asynchronously (e.g. from a
500	* hrtimer callback in hard irq context) and therefore need stronger atomicity	500	* hrtimer callback in hard irq context) and therefore need stronger atomicity
501	* guarantees than other registers.	501	* guarantees than other registers.
502	*/	502	*/
503		503
504	static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,	504	static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
505	unsigned long val)	505	unsigned long val)
506	{	506	{
507	unsigned long temp;	507	unsigned long temp;
508	do {	508	do {
509	__asm__ __volatile__(	509	__asm__ __volatile__(
510	" .set mips3 \n"	510	" .set mips3 \n"
511	" " __LL "%0, %1 \n"	511	" " __LL "%0, %1 \n"
512	" or %0, %2 \n"	512	" or %0, %2 \n"
513	" " __SC "%0, %1 \n"	513	" " __SC "%0, %1 \n"
514	" .set mips0 \n"	514	" .set mips0 \n"
515	: "=&r" (temp), "+m" (*reg)	515	: "=&r" (temp), "+m" (*reg)
516	: "r" (val));	516	: "r" (val));
517	} while (unlikely(!temp));	517	} while (unlikely(!temp));
518	}	518	}
519		519
520	static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,	520	static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
521	unsigned long val)	521	unsigned long val)
522	{	522	{
523	unsigned long temp;	523	unsigned long temp;
524	do {	524	do {
525	__asm__ __volatile__(	525	__asm__ __volatile__(
526	" .set mips3 \n"	526	" .set mips3 \n"
527	" " __LL "%0, %1 \n"	527	" " __LL "%0, %1 \n"
528	" and %0, %2 \n"	528	" and %0, %2 \n"
529	" " __SC "%0, %1 \n"	529	" " __SC "%0, %1 \n"
530	" .set mips0 \n"	530	" .set mips0 \n"
531	: "=&r" (temp), "+m" (*reg)	531	: "=&r" (temp), "+m" (*reg)
532	: "r" (~val));	532	: "r" (~val));
533	} while (unlikely(!temp));	533	} while (unlikely(!temp));
534	}	534	}
535		535
536	static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,	536	static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
537	unsigned long change,	537	unsigned long change,
538	unsigned long val)	538	unsigned long val)
539	{	539	{
540	unsigned long temp;	540	unsigned long temp;
541	do {	541	do {
542	__asm__ __volatile__(	542	__asm__ __volatile__(
543	" .set mips3 \n"	543	" .set mips3 \n"
544	" " __LL "%0, %1 \n"	544	" " __LL "%0, %1 \n"
545	" and %0, %2 \n"	545	" and %0, %2 \n"
546	" or %0, %3 \n"	546	" or %0, %3 \n"
547	" " __SC "%0, %1 \n"	547	" " __SC "%0, %1 \n"
548	" .set mips0 \n"	548	" .set mips0 \n"
549	: "=&r" (temp), "+m" (*reg)	549	: "=&r" (temp), "+m" (*reg)
550	: "r" (~change), "r" (val & change));	550	: "r" (~change), "r" (val & change));
551	} while (unlikely(!temp));	551	} while (unlikely(!temp));
552	}	552	}
553		553
554	#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] \|= (val))	554	#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] \|= (val))
555	#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))	555	#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
556		556
557	/* Cause can be modified asynchronously from hardirq hrtimer callback */	557	/* Cause can be modified asynchronously from hardirq hrtimer callback */
558	#define kvm_set_c0_guest_cause(cop0, val) \	558	#define kvm_set_c0_guest_cause(cop0, val) \
559	_kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)	559	_kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
560	#define kvm_clear_c0_guest_cause(cop0, val) \	560	#define kvm_clear_c0_guest_cause(cop0, val) \
561	_kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)	561	_kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
562	#define kvm_change_c0_guest_cause(cop0, change, val) \	562	#define kvm_change_c0_guest_cause(cop0, change, val) \
563	_kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \	563	_kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
564	change, val)	564	change, val)
565		565
566	#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] \|= (val))	566	#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] \|= (val))
567	#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))	567	#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
568	#define kvm_change_c0_guest_ebase(cop0, change, val) \	568	#define kvm_change_c0_guest_ebase(cop0, change, val) \
569	{ \	569	{ \
570	kvm_clear_c0_guest_ebase(cop0, change); \	570	kvm_clear_c0_guest_ebase(cop0, change); \
571	kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \	571	kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
572	}	572	}
573		573
574	/* Helpers */	574	/* Helpers */
575		575
576	static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)	576	static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
577	{	577	{
578	return (!__builtin_constant_p(cpu_has_fpu) \|\| cpu_has_fpu) &&	578	return (!__builtin_constant_p(cpu_has_fpu) \|\| cpu_has_fpu) &&
579	vcpu->fpu_enabled;	579	vcpu->fpu_enabled;
580	}	580	}
581		581
582	static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)	582	static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
583	{	583	{
584	return kvm_mips_guest_can_have_fpu(vcpu) &&	584	return kvm_mips_guest_can_have_fpu(vcpu) &&
585	kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;	585	kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
586	}	586	}
587		587
588	static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)	588	static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
589	{	589	{
590	return (!__builtin_constant_p(cpu_has_msa) \|\| cpu_has_msa) &&	590	return (!__builtin_constant_p(cpu_has_msa) \|\| cpu_has_msa) &&
591	vcpu->msa_enabled;	591	vcpu->msa_enabled;
592	}	592	}
593		593
594	static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)	594	static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
595	{	595	{
596	return kvm_mips_guest_can_have_msa(vcpu) &&	596	return kvm_mips_guest_can_have_msa(vcpu) &&
597	kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;	597	kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
598	}	598	}
599		599
600	struct kvm_mips_callbacks {	600	struct kvm_mips_callbacks {
601	int (handle_cop_unusable)(struct kvm_vcpu vcpu);	601	int (handle_cop_unusable)(struct kvm_vcpu vcpu);
602	int (handle_tlb_mod)(struct kvm_vcpu vcpu);	602	int (handle_tlb_mod)(struct kvm_vcpu vcpu);
603	int (handle_tlb_ld_miss)(struct kvm_vcpu vcpu);	603	int (handle_tlb_ld_miss)(struct kvm_vcpu vcpu);
604	int (handle_tlb_st_miss)(struct kvm_vcpu vcpu);	604	int (handle_tlb_st_miss)(struct kvm_vcpu vcpu);
605	int (handle_addr_err_st)(struct kvm_vcpu vcpu);	605	int (handle_addr_err_st)(struct kvm_vcpu vcpu);
606	int (handle_addr_err_ld)(struct kvm_vcpu vcpu);	606	int (handle_addr_err_ld)(struct kvm_vcpu vcpu);
607	int (handle_syscall)(struct kvm_vcpu vcpu);	607	int (handle_syscall)(struct kvm_vcpu vcpu);
608	int (handle_res_inst)(struct kvm_vcpu vcpu);	608	int (handle_res_inst)(struct kvm_vcpu vcpu);
609	int (handle_break)(struct kvm_vcpu vcpu);	609	int (handle_break)(struct kvm_vcpu vcpu);
610	int (handle_trap)(struct kvm_vcpu vcpu);	610	int (handle_trap)(struct kvm_vcpu vcpu);
611	int (handle_msa_fpe)(struct kvm_vcpu vcpu);	611	int (handle_msa_fpe)(struct kvm_vcpu vcpu);
612	int (handle_fpe)(struct kvm_vcpu vcpu);	612	int (handle_fpe)(struct kvm_vcpu vcpu);
613	int (handle_msa_disabled)(struct kvm_vcpu vcpu);	613	int (handle_msa_disabled)(struct kvm_vcpu vcpu);
614	int (vm_init)(struct kvm kvm);	614	int (vm_init)(struct kvm kvm);
615	int (vcpu_init)(struct kvm_vcpu vcpu);	615	int (vcpu_init)(struct kvm_vcpu vcpu);
616	int (vcpu_setup)(struct kvm_vcpu vcpu);	616	int (vcpu_setup)(struct kvm_vcpu vcpu);
617	gpa_t (*gva_to_gpa)(gva_t gva);	617	gpa_t (*gva_to_gpa)(gva_t gva);
618	void (queue_timer_int)(struct kvm_vcpu vcpu);	618	void (queue_timer_int)(struct kvm_vcpu vcpu);
619	void (dequeue_timer_int)(struct kvm_vcpu vcpu);	619	void (dequeue_timer_int)(struct kvm_vcpu vcpu);
620	void (queue_io_int)(struct kvm_vcpu vcpu,	620	void (queue_io_int)(struct kvm_vcpu vcpu,
621	struct kvm_mips_interrupt *irq);	621	struct kvm_mips_interrupt *irq);
622	void (dequeue_io_int)(struct kvm_vcpu vcpu,	622	void (dequeue_io_int)(struct kvm_vcpu vcpu,
623	struct kvm_mips_interrupt *irq);	623	struct kvm_mips_interrupt *irq);
624	int (irq_deliver)(struct kvm_vcpu vcpu, unsigned int priority,	624	int (irq_deliver)(struct kvm_vcpu vcpu, unsigned int priority,
625	uint32_t cause);	625	uint32_t cause);
626	int (irq_clear)(struct kvm_vcpu vcpu, unsigned int priority,	626	int (irq_clear)(struct kvm_vcpu vcpu, unsigned int priority,
627	uint32_t cause);	627	uint32_t cause);
628	int (get_one_reg)(struct kvm_vcpu vcpu,	628	int (get_one_reg)(struct kvm_vcpu vcpu,
629	const struct kvm_one_reg reg, s64 v);	629	const struct kvm_one_reg reg, s64 v);
630	int (set_one_reg)(struct kvm_vcpu vcpu,	630	int (set_one_reg)(struct kvm_vcpu vcpu,
631	const struct kvm_one_reg *reg, s64 v);	631	const struct kvm_one_reg *reg, s64 v);
632	int (vcpu_get_regs)(struct kvm_vcpu vcpu);	632	int (vcpu_get_regs)(struct kvm_vcpu vcpu);
633	int (vcpu_set_regs)(struct kvm_vcpu vcpu);	633	int (vcpu_set_regs)(struct kvm_vcpu vcpu);
634	};	634	};
635	extern struct kvm_mips_callbacks *kvm_mips_callbacks;	635	extern struct kvm_mips_callbacks *kvm_mips_callbacks;
636	int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);	636	int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
637		637
638	/* Debug: dump vcpu state */	638	/* Debug: dump vcpu state */
639	int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);	639	int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
640		640
641	/* Trampoline ASM routine to start running in "Guest" context */	641	/* Trampoline ASM routine to start running in "Guest" context */
642	extern int __kvm_mips_vcpu_run(struct kvm_run run, struct kvm_vcpu vcpu);	642	extern int __kvm_mips_vcpu_run(struct kvm_run run, struct kvm_vcpu vcpu);
643		643
644	/* FPU/MSA context management */	644	/* FPU/MSA context management */
645	void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);	645	void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
646	void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);	646	void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
647	void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);	647	void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
648	void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);	648	void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
649	void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);	649	void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
650	void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);	650	void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
651	void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);	651	void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
652	void kvm_own_fpu(struct kvm_vcpu *vcpu);	652	void kvm_own_fpu(struct kvm_vcpu *vcpu);
653	void kvm_own_msa(struct kvm_vcpu *vcpu);	653	void kvm_own_msa(struct kvm_vcpu *vcpu);
654	void kvm_drop_fpu(struct kvm_vcpu *vcpu);	654	void kvm_drop_fpu(struct kvm_vcpu *vcpu);
655	void kvm_lose_fpu(struct kvm_vcpu *vcpu);	655	void kvm_lose_fpu(struct kvm_vcpu *vcpu);
656		656
657	/* TLB handling */	657	/* TLB handling */
658	uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);	658	uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
659		659
660	uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);	660	uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
661		661
662	uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);	662	uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
663		663
664	extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,	664	extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
665	struct kvm_vcpu *vcpu);	665	struct kvm_vcpu *vcpu);
666		666
667	extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,	667	extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
668	struct kvm_vcpu *vcpu);	668	struct kvm_vcpu *vcpu);
669		669
670	extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,	670	extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
671	struct kvm_mips_tlb *tlb,	671	struct kvm_mips_tlb *tlb,
672	unsigned long *hpa0,	672	unsigned long *hpa0,
673	unsigned long *hpa1);	673	unsigned long *hpa1);
674		674
675	extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,	675	extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
676	uint32_t *opc,	676	uint32_t *opc,
677	struct kvm_run *run,	677	struct kvm_run *run,
678	struct kvm_vcpu *vcpu);	678	struct kvm_vcpu *vcpu);
679		679
680	extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,	680	extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
681	uint32_t *opc,	681	uint32_t *opc,
682	struct kvm_run *run,	682	struct kvm_run *run,
683	struct kvm_vcpu *vcpu);	683	struct kvm_vcpu *vcpu);
684		684
685	extern void kvm_mips_dump_host_tlbs(void);	685	extern void kvm_mips_dump_host_tlbs(void);
686	extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);	686	extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
687	extern void kvm_mips_flush_host_tlb(int skip_kseg0);	687	extern void kvm_mips_flush_host_tlb(int skip_kseg0);
688	extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);	688	extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
689	extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);	689	extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
690		690
691	extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,	691	extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
692	unsigned long entryhi);	692	unsigned long entryhi);
693	extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);	693	extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
694	extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,	694	extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
695	unsigned long gva);	695	unsigned long gva);
696	extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,	696	extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
697	struct kvm_vcpu *vcpu);	697	struct kvm_vcpu *vcpu);
698	extern void kvm_local_flush_tlb_all(void);	698	extern void kvm_local_flush_tlb_all(void);
699	extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);	699	extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
700	extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);	700	extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
701	extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);	701	extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
702		702
703	/* Emulation */	703	/* Emulation */
704	uint32_t kvm_get_inst(uint32_t opc, struct kvm_vcpu vcpu);	704	uint32_t kvm_get_inst(uint32_t opc, struct kvm_vcpu vcpu);
705	enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);	705	enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
706		706
707	extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,	707	extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
708	uint32_t *opc,	708	uint32_t *opc,
709	struct kvm_run *run,	709	struct kvm_run *run,
710	struct kvm_vcpu *vcpu);	710	struct kvm_vcpu *vcpu);
711		711
712	extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,	712	extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
713	uint32_t *opc,	713	uint32_t *opc,
714	struct kvm_run *run,	714	struct kvm_run *run,
715	struct kvm_vcpu *vcpu);	715	struct kvm_vcpu *vcpu);
716		716
717	extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,	717	extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
718	uint32_t *opc,	718	uint32_t *opc,
719	struct kvm_run *run,	719	struct kvm_run *run,
720	struct kvm_vcpu *vcpu);	720	struct kvm_vcpu *vcpu);
721		721
722	extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,	722	extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
723	uint32_t *opc,	723	uint32_t *opc,
724	struct kvm_run *run,	724	struct kvm_run *run,
725	struct kvm_vcpu *vcpu);	725	struct kvm_vcpu *vcpu);
726		726
727	extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,	727	extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
728	uint32_t *opc,	728	uint32_t *opc,
729	struct kvm_run *run,	729	struct kvm_run *run,
730	struct kvm_vcpu *vcpu);	730	struct kvm_vcpu *vcpu);
731		731
732	extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,	732	extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
733	uint32_t *opc,	733	uint32_t *opc,
734	struct kvm_run *run,	734	struct kvm_run *run,
735	struct kvm_vcpu *vcpu);	735	struct kvm_vcpu *vcpu);
736		736
737	extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,	737	extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
738	uint32_t *opc,	738	uint32_t *opc,
739	struct kvm_run *run,	739	struct kvm_run *run,
740	struct kvm_vcpu *vcpu);	740	struct kvm_vcpu *vcpu);
741		741
742	extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,	742	extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
743	uint32_t *opc,	743	uint32_t *opc,
744	struct kvm_run *run,	744	struct kvm_run *run,
745	struct kvm_vcpu *vcpu);	745	struct kvm_vcpu *vcpu);
746		746
747	extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,	747	extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
748	uint32_t *opc,	748	uint32_t *opc,
749	struct kvm_run *run,	749	struct kvm_run *run,
750	struct kvm_vcpu *vcpu);	750	struct kvm_vcpu *vcpu);
751		751
752	extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,	752	extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
753	uint32_t *opc,	753	uint32_t *opc,
754	struct kvm_run *run,	754	struct kvm_run *run,
755	struct kvm_vcpu *vcpu);	755	struct kvm_vcpu *vcpu);
756		756
757	extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,	757	extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
758	uint32_t *opc,	758	uint32_t *opc,
759	struct kvm_run *run,	759	struct kvm_run *run,
760	struct kvm_vcpu *vcpu);	760	struct kvm_vcpu *vcpu);
761		761
762	extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,	762	extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
763	uint32_t *opc,	763	uint32_t *opc,
764	struct kvm_run *run,	764	struct kvm_run *run,
765	struct kvm_vcpu *vcpu);	765	struct kvm_vcpu *vcpu);
766		766
767	extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,	767	extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
768	uint32_t *opc,	768	uint32_t *opc,
769	struct kvm_run *run,	769	struct kvm_run *run,
770	struct kvm_vcpu *vcpu);	770	struct kvm_vcpu *vcpu);
771		771
772	extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,	772	extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
773	uint32_t *opc,	773	uint32_t *opc,
774	struct kvm_run *run,	774	struct kvm_run *run,
775	struct kvm_vcpu *vcpu);	775	struct kvm_vcpu *vcpu);
776		776
777	extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,	777	extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
778	uint32_t *opc,	778	uint32_t *opc,
779	struct kvm_run *run,	779	struct kvm_run *run,
780	struct kvm_vcpu *vcpu);	780	struct kvm_vcpu *vcpu);
781		781
782	extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,	782	extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
783	struct kvm_run *run);	783	struct kvm_run *run);
784		784
785	uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);	785	uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
786	void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);	786	void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
787	void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);	787	void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack);
788	void kvm_mips_init_count(struct kvm_vcpu *vcpu);	788	void kvm_mips_init_count(struct kvm_vcpu *vcpu);
789	int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);	789	int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
790	int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);	790	int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
791	int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);	791	int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
792	void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);	792	void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
793	void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);	793	void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
794	enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);	794	enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
795		795
796	enum emulation_result kvm_mips_check_privilege(unsigned long cause,	796	enum emulation_result kvm_mips_check_privilege(unsigned long cause,
797	uint32_t *opc,	797	uint32_t *opc,
798	struct kvm_run *run,	798	struct kvm_run *run,
799	struct kvm_vcpu *vcpu);	799	struct kvm_vcpu *vcpu);
800		800
801	enum emulation_result kvm_mips_emulate_cache(uint32_t inst,	801	enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
802	uint32_t *opc,	802	uint32_t *opc,
803	uint32_t cause,	803	uint32_t cause,
804	struct kvm_run *run,	804	struct kvm_run *run,
805	struct kvm_vcpu *vcpu);	805	struct kvm_vcpu *vcpu);
806	enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,	806	enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
807	uint32_t *opc,	807	uint32_t *opc,
808	uint32_t cause,	808	uint32_t cause,
809	struct kvm_run *run,	809	struct kvm_run *run,
810	struct kvm_vcpu *vcpu);	810	struct kvm_vcpu *vcpu);
811	enum emulation_result kvm_mips_emulate_store(uint32_t inst,	811	enum emulation_result kvm_mips_emulate_store(uint32_t inst,
812	uint32_t cause,	812	uint32_t cause,
813	struct kvm_run *run,	813	struct kvm_run *run,
814	struct kvm_vcpu *vcpu);	814	struct kvm_vcpu *vcpu);
815	enum emulation_result kvm_mips_emulate_load(uint32_t inst,	815	enum emulation_result kvm_mips_emulate_load(uint32_t inst,
816	uint32_t cause,	816	uint32_t cause,
817	struct kvm_run *run,	817	struct kvm_run *run,
818	struct kvm_vcpu *vcpu);	818	struct kvm_vcpu *vcpu);
819		819
820	unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);	820	unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
821	unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);	821	unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
822	unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);	822	unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
823	unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);	823	unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
824		824
825	/* Dynamic binary translation */	825	/* Dynamic binary translation */
826	extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,	826	extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
827	struct kvm_vcpu *vcpu);	827	struct kvm_vcpu *vcpu);
828	extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,	828	extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
829	struct kvm_vcpu *vcpu);	829	struct kvm_vcpu *vcpu);
830	extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,	830	extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
831	struct kvm_vcpu *vcpu);	831	struct kvm_vcpu *vcpu);
832	extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,	832	extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
833	struct kvm_vcpu *vcpu);	833	struct kvm_vcpu *vcpu);
834		834
835	/* Misc */	835	/* Misc */
836	extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);	836	extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
837	extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);	837	extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
838		838
839	static inline void kvm_arch_hardware_disable(void) {}	839	static inline void kvm_arch_hardware_disable(void) {}
840	static inline void kvm_arch_hardware_unsetup(void) {}	840	static inline void kvm_arch_hardware_unsetup(void) {}
841	static inline void kvm_arch_sync_events(struct kvm *kvm) {}	841	static inline void kvm_arch_sync_events(struct kvm *kvm) {}
842	static inline void kvm_arch_free_memslot(struct kvm *kvm,	842	static inline void kvm_arch_free_memslot(struct kvm *kvm,
843	struct kvm_memory_slot free, struct kvm_memory_slot dont) {}	843	struct kvm_memory_slot free, struct kvm_memory_slot dont) {}
844	static inline void kvm_arch_memslots_updated(struct kvm kvm, struct kvm_memslots slots) {}	844	static inline void kvm_arch_memslots_updated(struct kvm kvm, struct kvm_memslots slots) {}
845	static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}	845	static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
846	static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,	846	static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
847	struct kvm_memory_slot *slot) {}	847	struct kvm_memory_slot *slot) {}
848	static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}	848	static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
849	static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}	849	static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
850	static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}	850	static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
851	static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}	851	static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
852		852
853	#endif /* __MIPS_KVM_HOST_H__ */	853	#endif /* __MIPS_KVM_HOST_H__ */
854		854

arch/mips/kvm/emulate.c

Diff comments View file @ a6fa60f

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * KVM/MIPS: Instruction/Exception emulation
  *
  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  */
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/ktime.h>
 #include <linux/kvm_host.h>
 #include <linux/module.h>
 #include <linux/vmalloc.h>
 #include <linux/fs.h>
 #include <linux/bootmem.h>
 #include <linux/random.h>
 #include <asm/page.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu-info.h>
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
 #include <asm/inst.h>
 #undef CONFIG_MIPS_MT
 #include <asm/r4kcache.h>
 #define CONFIG_MIPS_MT
 #include "opcode.h"
 #include "interrupt.h"
 #include "commpage.h"
 #include "trace.h"
 /*
  * Compute the return address and do emulate branch simulation, if required.
  * This function should be called only in branch delay slot active.
  */
 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
 	unsigned long instpc)
 {
 	unsigned int dspcontrol;
 	union mips_instruction insn;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	long epc = instpc;
 	long nextpc = KVM_INVALID_INST;
 	if (epc & 3)
 		goto unaligned;
 	/* Read the instruction */
 	insn.word = kvm_get_inst((uint32_t *) epc, vcpu);
 	if (insn.word == KVM_INVALID_INST)
 		return KVM_INVALID_INST;
 	switch (insn.i_format.opcode) {
 		/* jr and jalr are in r_format format. */
 	case spec_op:
 		switch (insn.r_format.func) {
 		case jalr_op:
 			arch->gprs[insn.r_format.rd] = epc + 8;
 			/* Fall through */
 		case jr_op:
 			nextpc = arch->gprs[insn.r_format.rs];
 			break;
 		}
 		break;
 		/*
 		 * This group contains:
 		 * bltz_op, bgez_op, bltzl_op, bgezl_op,
 		 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
 		 */
 	case bcond_op:
 		switch (insn.i_format.rt) {
 		case bltz_op:
 		case bltzl_op:
 			if ((long)arch->gprs[insn.i_format.rs] < 0)
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 			else
 				epc += 8;
 			nextpc = epc;
 			break;
 		case bgez_op:
 		case bgezl_op:
 			if ((long)arch->gprs[insn.i_format.rs] >= 0)
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 			else
 				epc += 8;
 			nextpc = epc;
 			break;
 		case bltzal_op:
 		case bltzall_op:
 			arch->gprs[31] = epc + 8;
 			if ((long)arch->gprs[insn.i_format.rs] < 0)
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 			else
 				epc += 8;
 			nextpc = epc;
 			break;
 		case bgezal_op:
 		case bgezall_op:
 			arch->gprs[31] = epc + 8;
 			if ((long)arch->gprs[insn.i_format.rs] >= 0)
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 			else
 				epc += 8;
 			nextpc = epc;
 			break;
 		case bposge32_op:
 			if (!cpu_has_dsp)
 				goto sigill;
 			dspcontrol = rddsp(0x01);
 			if (dspcontrol >= 32)
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
 			else
 				epc += 8;
 			nextpc = epc;
 			break;
 		}
 		break;
 		/* These are unconditional and in j_format. */
 	case jal_op:
 		arch->gprs[31] = instpc + 8;
 	case j_op:
 		epc += 4;
 		epc >>= 28;
 		epc <<= 28;
 		epc |= (insn.j_format.target << 2);
 		nextpc = epc;
 		break;
 		/* These are conditional and in i_format. */
 	case beq_op:
 	case beql_op:
 		if (arch->gprs[insn.i_format.rs] ==
 		    arch->gprs[insn.i_format.rt])
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		nextpc = epc;
 		break;
 	case bne_op:
 	case bnel_op:
 		if (arch->gprs[insn.i_format.rs] !=
 		    arch->gprs[insn.i_format.rt])
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		nextpc = epc;
 		break;
 	case blez_op:		/* not really i_format */
 	case blezl_op:
 		/* rt field assumed to be zero */
 		if ((long)arch->gprs[insn.i_format.rs] <= 0)
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		nextpc = epc;
 		break;
 	case bgtz_op:
 	case bgtzl_op:
 		/* rt field assumed to be zero */
 		if ((long)arch->gprs[insn.i_format.rs] > 0)
 			epc = epc + 4 + (insn.i_format.simmediate << 2);
 		else
 			epc += 8;
 		nextpc = epc;
 		break;
 		/* And now the FPA/cp1 branch instructions. */
 	case cop1_op:
 		kvm_err("%s: unsupported cop1_op\n", __func__);
 		break;
 	}
 	return nextpc;
 unaligned:
 	kvm_err("%s: unaligned epc\n", __func__);
 	return nextpc;
 sigill:
 	kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
 	return nextpc;
 }
 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause)
 {
 	unsigned long branch_pc;
 	enum emulation_result er = EMULATE_DONE;
 	if (cause & CAUSEF_BD) {
 		branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
 		if (branch_pc == KVM_INVALID_INST) {
 			er = EMULATE_FAIL;
 		} else {
 			vcpu->arch.pc = branch_pc;
 			kvm_debug("BD update_pc(): New PC: %#lx\n",
 				  vcpu->arch.pc);
 		}
 	} else
 		vcpu->arch.pc += 4;
 	kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
 	return er;
 }
 /**
  * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
  * @vcpu:	Virtual CPU.
  *
  * Returns:	1 if the CP0_Count timer is disabled by either the guest
  *		CP0_Cause.DC bit or the count_ctl.DC bit.
  *		0 otherwise (in which case CP0_Count timer is running).
  */
 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	return	(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
 		(kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
 }
 /**
  * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
  *
  * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
  *
  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
  */
 static uint32_t kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
 {
 	s64 now_ns, periods;
 	u64 delta;
 	now_ns = ktime_to_ns(now);
 	delta = now_ns + vcpu->arch.count_dyn_bias;
 	if (delta >= vcpu->arch.count_period) {
 		/* If delta is out of safe range the bias needs adjusting */
 		periods = div64_s64(now_ns, vcpu->arch.count_period);
 		vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
 		/* Recalculate delta with new bias */
 		delta = now_ns + vcpu->arch.count_dyn_bias;
 	}
 	/*
 	 * We've ensured that:
 	 *   delta < count_period
 	 *
 	 * Therefore the intermediate delta*count_hz will never overflow since
 	 * at the boundary condition:
 	 *   delta = count_period
 	 *   delta = NSEC_PER_SEC * 2^32 / count_hz
 	 *   delta * count_hz = NSEC_PER_SEC * 2^32
 	 */
 	return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
 }
 /**
  * kvm_mips_count_time() - Get effective current time.
  * @vcpu:	Virtual CPU.
  *
  * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
  * except when the master disable bit is set in count_ctl, in which case it is
  * count_resume, i.e. the time that the count was disabled.
  *
  * Returns:	Effective monotonic ktime for CP0_Count.
  */
 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
 {
 	if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
 		return vcpu->arch.count_resume;
 	return ktime_get();
 }
 /**
  * kvm_mips_read_count_running() - Read the current count value as if running.
  * @vcpu:	Virtual CPU.
  * @now:	Kernel time to read CP0_Count at.
  *
  * Returns the current guest CP0_Count register at time @now and handles if the
  * timer interrupt is pending and hasn't been handled yet.
  *
  * Returns:	The current value of the guest CP0_Count register.
  */
 static uint32_t kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	ktime_t expires, threshold;
 	uint32_t count, compare;
 	int running;
 	/* Calculate the biased and scaled guest CP0_Count */
 	count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
 	compare = kvm_read_c0_guest_compare(cop0);
 	/*
 	 * Find whether CP0_Count has reached the closest timer interrupt. If
 	 * not, we shouldn't inject it.
 	 */
 	if ((int32_t)(count - compare) < 0)
 		return count;
 	/*
 	 * The CP0_Count we're going to return has already reached the closest
 	 * timer interrupt. Quickly check if it really is a new interrupt by
 	 * looking at whether the interval until the hrtimer expiry time is
 	 * less than 1/4 of the timer period.
 	 */
 	expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
 	threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
 	if (ktime_before(expires, threshold)) {
 		/*
 		 * Cancel it while we handle it so there's no chance of
 		 * interference with the timeout handler.
 		 */
 		running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
 		/* Nothing should be waiting on the timeout */
 		kvm_mips_callbacks->queue_timer_int(vcpu);
 		/*
 		 * Restart the timer if it was running based on the expiry time
 		 * we read, so that we don't push it back 2 periods.
 		 */
 		if (running) {
 			expires = ktime_add_ns(expires,
 					       vcpu->arch.count_period);
 			hrtimer_start(&vcpu->arch.comparecount_timer, expires,
 				      HRTIMER_MODE_ABS);
 		}
 	}
 	return count;
 }
 /**
  * kvm_mips_read_count() - Read the current count value.
  * @vcpu:	Virtual CPU.
  *
  * Read the current guest CP0_Count value, taking into account whether the timer
  * is stopped.
  *
  * Returns:	The current guest CP0_Count value.
  */
 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	/* If count disabled just read static copy of count */
 	if (kvm_mips_count_disabled(vcpu))
 		return kvm_read_c0_guest_count(cop0);
 	return kvm_mips_read_count_running(vcpu, ktime_get());
 }
 /**
  * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
  * @vcpu:	Virtual CPU.
  * @count:	Output pointer for CP0_Count value at point of freeze.
  *
  * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
  * at the point it was frozen. It is guaranteed that any pending interrupts at
  * the point it was frozen are handled, and none after that point.
  *
  * This is useful where the time/CP0_Count is needed in the calculation of the
  * new parameters.
  *
  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
  *
  * Returns:	The ktime at the point of freeze.
  */
 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu,
 				       uint32_t *count)
 {
 	ktime_t now;
 	/* stop hrtimer before finding time */
 	hrtimer_cancel(&vcpu->arch.comparecount_timer);
 	now = ktime_get();
 	/* find count at this point and handle pending hrtimer */
 	*count = kvm_mips_read_count_running(vcpu, now);
 	return now;
 }
 /**
  * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
  * @vcpu:	Virtual CPU.
  * @now:	ktime at point of resume.
  * @count:	CP0_Count at point of resume.
  *
  * Resumes the timer and updates the timer expiry based on @now and @count.
  * This can be used in conjunction with kvm_mips_freeze_timer() when timer
  * parameters need to be changed.
  *
  * It is guaranteed that a timer interrupt immediately after resume will be
  * handled, but not if CP_Compare is exactly at @count. That case is already
  * handled by kvm_mips_freeze_timer().
  *
  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
  */
 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
 				    ktime_t now, uint32_t count)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	uint32_t compare;
 	u64 delta;
 	ktime_t expire;
 	/* Calculate timeout (wrap 0 to 2^32) */
 	compare = kvm_read_c0_guest_compare(cop0);
 	delta = (u64)(uint32_t)(compare - count - 1) + 1;
 	delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
 	expire = ktime_add_ns(now, delta);
 	/* Update hrtimer to use new timeout */
 	hrtimer_cancel(&vcpu->arch.comparecount_timer);
 	hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
 }
 /**
- * kvm_mips_update_hrtimer() - Update next expiry time of hrtimer.
- * @vcpu:	Virtual CPU.
- *
- * Recalculates and updates the expiry time of the hrtimer. This can be used
- * after timer parameters have been altered which do not depend on the time that
- * the change occurs (in those cases kvm_mips_freeze_hrtimer() and
- * kvm_mips_resume_hrtimer() are used directly).
- *
- * It is guaranteed that no timer interrupts will be lost in the process.
- *
- * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
- */
-static void kvm_mips_update_hrtimer(struct kvm_vcpu *vcpu)
-{
-	ktime_t now;
-	uint32_t count;
-	/*
-	 * freeze_hrtimer takes care of a timer interrupts <= count, and
-	 * resume_hrtimer the hrtimer takes care of a timer interrupts > count.
-	 */
-	now = kvm_mips_freeze_hrtimer(vcpu, &count);
-	kvm_mips_resume_hrtimer(vcpu, now, count);
-}
-/**
  * kvm_mips_write_count() - Modify the count and update timer.
  * @vcpu:	Virtual CPU.
  * @count:	Guest CP0_Count value to set.
  *
  * Sets the CP0_Count value and updates the timer accordingly.
  */
 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	ktime_t now;
 	/* Calculate bias */
 	now = kvm_mips_count_time(vcpu);
 	vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
 	if (kvm_mips_count_disabled(vcpu))
 		/* The timer's disabled, adjust the static count */
 		kvm_write_c0_guest_count(cop0, count);
 	else
 		/* Update timeout */
 		kvm_mips_resume_hrtimer(vcpu, now, count);
 }
 /**
  * kvm_mips_init_count() - Initialise timer.
  * @vcpu:	Virtual CPU.
  *
  * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
  * it going if it's enabled.
  */
 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
 {
 	/* 100 MHz */
 	vcpu->arch.count_hz = 100*1000*1000;
 	vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
 					  vcpu->arch.count_hz);
 	vcpu->arch.count_dyn_bias = 0;
 	/* Starting at 0 */
 	kvm_mips_write_count(vcpu, 0);
 }
 /**
  * kvm_mips_set_count_hz() - Update the frequency of the timer.
  * @vcpu:	Virtual CPU.
  * @count_hz:	Frequency of CP0_Count timer in Hz.
  *
  * Change the frequency of the CP0_Count timer. This is done atomically so that
  * CP0_Count is continuous and no timer interrupt is lost.
  *
  * Returns:	-EINVAL if @count_hz is out of range.
  *		0 on success.
  */
 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	int dc;
 	ktime_t now;
 	u32 count;
 	/* ensure the frequency is in a sensible range... */
 	if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
 		return -EINVAL;
 	/* ... and has actually changed */
 	if (vcpu->arch.count_hz == count_hz)
 		return 0;
 	/* Safely freeze timer so we can keep it continuous */
 	dc = kvm_mips_count_disabled(vcpu);
 	if (dc) {
 		now = kvm_mips_count_time(vcpu);
 		count = kvm_read_c0_guest_count(cop0);
 	} else {
 		now = kvm_mips_freeze_hrtimer(vcpu, &count);
 	}
 	/* Update the frequency */
 	vcpu->arch.count_hz = count_hz;
 	vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
 	vcpu->arch.count_dyn_bias = 0;
 	/* Calculate adjusted bias so dynamic count is unchanged */
 	vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
 	/* Update and resume hrtimer */
 	if (!dc)
 		kvm_mips_resume_hrtimer(vcpu, now, count);
 	return 0;
 }
 /**
  * kvm_mips_write_compare() - Modify compare and update timer.
  * @vcpu:	Virtual CPU.
  * @compare:	New CP0_Compare value.
+ * @ack:	Whether to acknowledge timer interrupt.
  *
  * Update CP0_Compare to a new value and update the timeout.
+ * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
+ * any pending timer interrupt is preserved.
  */
-void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare)
+void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
+	int dc;
+	u32 old_compare = kvm_read_c0_guest_compare(cop0);
+	ktime_t now;
+	uint32_t count;
 	/* if unchanged, must just be an ack */
-	if (kvm_read_c0_guest_compare(cop0) == compare)
+	if (old_compare == compare) {
+		if (!ack)
+			return;
+		kvm_mips_callbacks->dequeue_timer_int(vcpu);
+		kvm_write_c0_guest_compare(cop0, compare);
 		return;
+	}
-	/* Update compare */
+	/* freeze_hrtimer() takes care of timer interrupts <= count */
+	dc = kvm_mips_count_disabled(vcpu);
+	if (!dc)
+		now = kvm_mips_freeze_hrtimer(vcpu, &count);
+	if (ack)
+		kvm_mips_callbacks->dequeue_timer_int(vcpu);
 	kvm_write_c0_guest_compare(cop0, compare);
-	/* Update timeout if count enabled */
+	/* resume_hrtimer() takes care of timer interrupts > count */
-	if (!kvm_mips_count_disabled(vcpu))
+	if (!dc)
-		kvm_mips_update_hrtimer(vcpu);
+		kvm_mips_resume_hrtimer(vcpu, now, count);
 }
 /**
  * kvm_mips_count_disable() - Disable count.
  * @vcpu:	Virtual CPU.
  *
  * Disable the CP0_Count timer. A timer interrupt on or before the final stop
  * time will be handled but not after.
  *
  * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
  * count_ctl.DC has been set (count disabled).
  *
  * Returns:	The time that the timer was stopped.
  */
 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	uint32_t count;
 	ktime_t now;
 	/* Stop hrtimer */
 	hrtimer_cancel(&vcpu->arch.comparecount_timer);
 	/* Set the static count from the dynamic count, handling pending TI */
 	now = ktime_get();
 	count = kvm_mips_read_count_running(vcpu, now);
 	kvm_write_c0_guest_count(cop0, count);
 	return now;
 }
 /**
  * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
  * @vcpu:	Virtual CPU.
  *
  * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
  * before the final stop time will be handled if the timer isn't disabled by
  * count_ctl.DC, but not after.
  *
  * Assumes CP0_Cause.DC is clear (count enabled).
  */
 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
 	if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
 		kvm_mips_count_disable(vcpu);
 }
 /**
  * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
  * @vcpu:	Virtual CPU.
  *
  * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
  * the start time will be handled if the timer isn't disabled by count_ctl.DC,
  * potentially before even returning, so the caller should be careful with
  * ordering of CP0_Cause modifications so as not to lose it.
  *
  * Assumes CP0_Cause.DC is set (count disabled).
  */
 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	uint32_t count;
 	kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
 	/*
 	 * Set the dynamic count to match the static count.
 	 * This starts the hrtimer if count_ctl.DC allows it.
 	 * Otherwise it conveniently updates the biases.
 	 */
 	count = kvm_read_c0_guest_count(cop0);
 	kvm_mips_write_count(vcpu, count);
 }
 /**
  * kvm_mips_set_count_ctl() - Update the count control KVM register.
  * @vcpu:	Virtual CPU.
  * @count_ctl:	Count control register new value.
  *
  * Set the count control KVM register. The timer is updated accordingly.
  *
  * Returns:	-EINVAL if reserved bits are set.
  *		0 on success.
  */
 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	s64 changed = count_ctl ^ vcpu->arch.count_ctl;
 	s64 delta;
 	ktime_t expire, now;
 	uint32_t count, compare;
 	/* Only allow defined bits to be changed */
 	if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
 		return -EINVAL;
 	/* Apply new value */
 	vcpu->arch.count_ctl = count_ctl;
 	/* Master CP0_Count disable */
 	if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
 		/* Is CP0_Cause.DC already disabling CP0_Count? */
 		if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
 			if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
 				/* Just record the current time */
 				vcpu->arch.count_resume = ktime_get();
 		} else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
 			/* disable timer and record current time */
 			vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
 		} else {
 			/*
 			 * Calculate timeout relative to static count at resume
 			 * time (wrap 0 to 2^32).
 			 */
 			count = kvm_read_c0_guest_count(cop0);
 			compare = kvm_read_c0_guest_compare(cop0);
 			delta = (u64)(uint32_t)(compare - count - 1) + 1;
 			delta = div_u64(delta * NSEC_PER_SEC,
 					vcpu->arch.count_hz);
 			expire = ktime_add_ns(vcpu->arch.count_resume, delta);
 			/* Handle pending interrupt */
 			now = ktime_get();
 			if (ktime_compare(now, expire) >= 0)
 				/* Nothing should be waiting on the timeout */
 				kvm_mips_callbacks->queue_timer_int(vcpu);
 			/* Resume hrtimer without changing bias */
 			count = kvm_mips_read_count_running(vcpu, now);
 			kvm_mips_resume_hrtimer(vcpu, now, count);
 		}
 	}
 	return 0;
 }
 /**
  * kvm_mips_set_count_resume() - Update the count resume KVM register.
  * @vcpu:		Virtual CPU.
  * @count_resume:	Count resume register new value.
  *
  * Set the count resume KVM register.
  *
  * Returns:	-EINVAL if out of valid range (0..now).
  *		0 on success.
  */
 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
 {
 	/*
 	 * It doesn't make sense for the resume time to be in the future, as it
 	 * would be possible for the next interrupt to be more than a full
 	 * period in the future.
 	 */
 	if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
 		return -EINVAL;
 	vcpu->arch.count_resume = ns_to_ktime(count_resume);
 	return 0;
 }
 /**
  * kvm_mips_count_timeout() - Push timer forward on timeout.
  * @vcpu:	Virtual CPU.
  *
  * Handle an hrtimer event by push the hrtimer forward a period.
  *
  * Returns:	The hrtimer_restart value to return to the hrtimer subsystem.
  */
 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
 {
 	/* Add the Count period to the current expiry time */
 	hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
 			       vcpu->arch.count_period);
 	return HRTIMER_RESTART;
 }
 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	enum emulation_result er = EMULATE_DONE;
 	if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
 		kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
 			  kvm_read_c0_guest_epc(cop0));
 		kvm_clear_c0_guest_status(cop0, ST0_EXL);
 		vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
 	} else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
 		kvm_clear_c0_guest_status(cop0, ST0_ERL);
 		vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
 	} else {
 		kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
 			vcpu->arch.pc);
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
 {
 	kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
 		  vcpu->arch.pending_exceptions);
 	++vcpu->stat.wait_exits;
 	trace_kvm_exit(vcpu, WAIT_EXITS);
 	if (!vcpu->arch.pending_exceptions) {
 		vcpu->arch.wait = 1;
 		kvm_vcpu_block(vcpu);
 		/*
 		 * We we are runnable, then definitely go off to user space to
 		 * check if any I/O interrupts are pending.
 		 */
 		if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
 			clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
 			vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
 		}
 	}
 	return EMULATE_DONE;
 }
 /*
  * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
  * we can catch this, if things ever change
  */
 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	uint32_t pc = vcpu->arch.pc;
 	kvm_err("[%#x] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
 	return EMULATE_FAIL;
 }
 /* Write Guest TLB Entry @ Index */
 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	int index = kvm_read_c0_guest_index(cop0);
 	struct kvm_mips_tlb *tlb = NULL;
 	uint32_t pc = vcpu->arch.pc;
 	if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
 		kvm_debug("%s: illegal index: %d\n", __func__, index);
 		kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
 			  pc, index, kvm_read_c0_guest_entryhi(cop0),
 			  kvm_read_c0_guest_entrylo0(cop0),
 			  kvm_read_c0_guest_entrylo1(cop0),
 			  kvm_read_c0_guest_pagemask(cop0));
 		index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
 	}
 	tlb = &vcpu->arch.guest_tlb[index];
 	/*
 	 * Probe the shadow host TLB for the entry being overwritten, if one
 	 * matches, invalidate it
 	 */
 	kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
 	tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
 	tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
 	tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
 	tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
 	kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
 		  pc, index, kvm_read_c0_guest_entryhi(cop0),
 		  kvm_read_c0_guest_entrylo0(cop0),
 		  kvm_read_c0_guest_entrylo1(cop0),
 		  kvm_read_c0_guest_pagemask(cop0));
 	return EMULATE_DONE;
 }
 /* Write Guest TLB Entry @ Random Index */
 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_mips_tlb *tlb = NULL;
 	uint32_t pc = vcpu->arch.pc;
 	int index;
 	get_random_bytes(&index, sizeof(index));
 	index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
 	tlb = &vcpu->arch.guest_tlb[index];
 	/*
 	 * Probe the shadow host TLB for the entry being overwritten, if one
 	 * matches, invalidate it
 	 */
 	kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
 	tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
 	tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
 	tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
 	tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
 	kvm_debug("[%#x] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
 		  pc, index, kvm_read_c0_guest_entryhi(cop0),
 		  kvm_read_c0_guest_entrylo0(cop0),
 		  kvm_read_c0_guest_entrylo1(cop0));
 	return EMULATE_DONE;
 }
 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	long entryhi = kvm_read_c0_guest_entryhi(cop0);
 	uint32_t pc = vcpu->arch.pc;
 	int index = -1;
 	index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
 	kvm_write_c0_guest_index(cop0, index);
 	kvm_debug("[%#x] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
 		  index);
 	return EMULATE_DONE;
 }
 /**
  * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
  * @vcpu:	Virtual CPU.
  *
  * Finds the mask of bits which are writable in the guest's Config1 CP0
  * register, by userland (currently read-only to the guest).
  */
 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
 {
 	unsigned int mask = 0;
 	/* Permit FPU to be present if FPU is supported */
 	if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
 		mask |= MIPS_CONF1_FP;
 	return mask;
 }
 /**
  * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
  * @vcpu:	Virtual CPU.
  *
  * Finds the mask of bits which are writable in the guest's Config3 CP0
  * register, by userland (currently read-only to the guest).
  */
 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
 {
 	/* Config4 is optional */
 	unsigned int mask = MIPS_CONF_M;
 	/* Permit MSA to be present if MSA is supported */
 	if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 		mask |= MIPS_CONF3_MSA;
 	return mask;
 }
 /**
  * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
  * @vcpu:	Virtual CPU.
  *
  * Finds the mask of bits which are writable in the guest's Config4 CP0
  * register, by userland (currently read-only to the guest).
  */
 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
 {
 	/* Config5 is optional */
 	return MIPS_CONF_M;
 }
 /**
  * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
  * @vcpu:	Virtual CPU.
  *
  * Finds the mask of bits which are writable in the guest's Config5 CP0
  * register, by the guest itself.
  */
 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
 {
 	unsigned int mask = 0;
 	/* Permit MSAEn changes if MSA supported and enabled */
 	if (kvm_mips_guest_has_msa(&vcpu->arch))
 		mask |= MIPS_CONF5_MSAEN;
 	/*
 	 * Permit guest FPU mode changes if FPU is enabled and the relevant
 	 * feature exists according to FIR register.
 	 */
 	if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
 		if (cpu_has_fre)
 			mask |= MIPS_CONF5_FRE;
 		/* We don't support UFR or UFE */
 	}
 	return mask;
 }
 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
 					   uint32_t cause, struct kvm_run *run,
 					   struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	enum emulation_result er = EMULATE_DONE;
 	int32_t rt, rd, copz, sel, co_bit, op;
 	uint32_t pc = vcpu->arch.pc;
 	unsigned long curr_pc;
 	/*
 	 * Update PC and hold onto current PC in case there is
 	 * an error and we want to rollback the PC
 	 */
 	curr_pc = vcpu->arch.pc;
 	er = update_pc(vcpu, cause);
 	if (er == EMULATE_FAIL)
 		return er;
 	copz = (inst >> 21) & 0x1f;
 	rt = (inst >> 16) & 0x1f;
 	rd = (inst >> 11) & 0x1f;
 	sel = inst & 0x7;
 	co_bit = (inst >> 25) & 1;
 	if (co_bit) {
 		op = (inst) & 0xff;
 		switch (op) {
 		case tlbr_op:	/*  Read indexed TLB entry  */
 			er = kvm_mips_emul_tlbr(vcpu);
 			break;
 		case tlbwi_op:	/*  Write indexed  */
 			er = kvm_mips_emul_tlbwi(vcpu);
 			break;
 		case tlbwr_op:	/*  Write random  */
 			er = kvm_mips_emul_tlbwr(vcpu);
 			break;
 		case tlbp_op:	/* TLB Probe */
 			er = kvm_mips_emul_tlbp(vcpu);
 			break;
 		case rfe_op:
 			kvm_err("!!!COP0_RFE!!!\n");
 			break;
 		case eret_op:
 			er = kvm_mips_emul_eret(vcpu);
 			goto dont_update_pc;
 			break;
 		case wait_op:
 			er = kvm_mips_emul_wait(vcpu);
 			break;
 		}
 	} else {
 		switch (copz) {
 		case mfc_op:
 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 			cop0->stat[rd][sel]++;
 #endif
 			/* Get reg */
 			if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
 				vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
 			} else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
 				vcpu->arch.gprs[rt] = 0x0;
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 				kvm_mips_trans_mfc0(inst, opc, vcpu);
 #endif
 			} else {
 				vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 				kvm_mips_trans_mfc0(inst, opc, vcpu);
 #endif
 			}
 			kvm_debug
 			    ("[%#x] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n",
 			     pc, rd, sel, rt, vcpu->arch.gprs[rt]);
 			break;
 		case dmfc_op:
 			vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
 			break;
 		case mtc_op:
 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 			cop0->stat[rd][sel]++;
 #endif
 			if ((rd == MIPS_CP0_TLB_INDEX)
 			    && (vcpu->arch.gprs[rt] >=
 				KVM_MIPS_GUEST_TLB_SIZE)) {
 				kvm_err("Invalid TLB Index: %ld",
 					vcpu->arch.gprs[rt]);
 				er = EMULATE_FAIL;
 				break;
 			}
 #define C0_EBASE_CORE_MASK 0xff
 			if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
 				/* Preserve CORE number */
 				kvm_change_c0_guest_ebase(cop0,
 							  ~(C0_EBASE_CORE_MASK),
 							  vcpu->arch.gprs[rt]);
 				kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
 					kvm_read_c0_guest_ebase(cop0));
 			} else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
 				uint32_t nasid =
 					vcpu->arch.gprs[rt] & ASID_MASK;
 				if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
 				    ((kvm_read_c0_guest_entryhi(cop0) &
 				      ASID_MASK) != nasid)) {
 					kvm_debug("MTCz, change ASID from %#lx to %#lx\n",
 						kvm_read_c0_guest_entryhi(cop0)
 						& ASID_MASK,
 						vcpu->arch.gprs[rt]
 						& ASID_MASK);
 					/* Blow away the shadow host TLBs */
 					kvm_mips_flush_host_tlb(1);
 				}
 				kvm_write_c0_guest_entryhi(cop0,
 							   vcpu->arch.gprs[rt]);
 			}
 			/* Are we writing to COUNT */
 			else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
 				kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
 				goto done;
 			} else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
 				kvm_debug("[%#x] MTCz, COMPARE %#lx <- %#lx\n",
 					  pc, kvm_read_c0_guest_compare(cop0),
 					  vcpu->arch.gprs[rt]);
 				/* If we are writing to COMPARE */
 				/* Clear pending timer interrupt, if any */
-				kvm_mips_callbacks->dequeue_timer_int(vcpu);
 				kvm_mips_write_compare(vcpu,
-						       vcpu->arch.gprs[rt]);
+						       vcpu->arch.gprs[rt],
+						       true);
 			} else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
 				unsigned int old_val, val, change;
 				old_val = kvm_read_c0_guest_status(cop0);
 				val = vcpu->arch.gprs[rt];
 				change = val ^ old_val;
 				/* Make sure that the NMI bit is never set */
 				val &= ~ST0_NMI;
 				/*
 				 * Don't allow CU1 or FR to be set unless FPU
 				 * capability enabled and exists in guest
 				 * configuration.
 				 */
 				if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 					val &= ~(ST0_CU1 | ST0_FR);
 				/*
 				 * Also don't allow FR to be set if host doesn't
 				 * support it.
 				 */
 				if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
 					val &= ~ST0_FR;
 				/* Handle changes in FPU mode */
 				preempt_disable();
 				/*
 				 * FPU and Vector register state is made
 				 * UNPREDICTABLE by a change of FR, so don't
 				 * even bother saving it.
 				 */
 				if (change & ST0_FR)
 					kvm_drop_fpu(vcpu);
 				/*
 				 * If MSA state is already live, it is undefined
 				 * how it interacts with FR=0 FPU state, and we
 				 * don't want to hit reserved instruction
 				 * exceptions trying to save the MSA state later
 				 * when CU=1 && FR=1, so play it safe and save
 				 * it first.
 				 */
 				if (change & ST0_CU1 && !(val & ST0_FR) &&
 				    vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
 					kvm_lose_fpu(vcpu);
 				/*
 				 * Propagate CU1 (FPU enable) changes
 				 * immediately if the FPU context is already
 				 * loaded. When disabling we leave the context
 				 * loaded so it can be quickly enabled again in
 				 * the near future.
 				 */
 				if (change & ST0_CU1 &&
 				    vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
 					change_c0_status(ST0_CU1, val);
 				preempt_enable();
 				kvm_write_c0_guest_status(cop0, val);
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 				/*
 				 * If FPU present, we need CU1/FR bits to take
 				 * effect fairly soon.
 				 */
 				if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 					kvm_mips_trans_mtc0(inst, opc, vcpu);
 #endif
 			} else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
 				unsigned int old_val, val, change, wrmask;
 				old_val = kvm_read_c0_guest_config5(cop0);
 				val = vcpu->arch.gprs[rt];
 				/* Only a few bits are writable in Config5 */
 				wrmask = kvm_mips_config5_wrmask(vcpu);
 				change = (val ^ old_val) & wrmask;
 				val = old_val ^ change;
 				/* Handle changes in FPU/MSA modes */
 				preempt_disable();
 				/*
 				 * Propagate FRE changes immediately if the FPU
 				 * context is already loaded.
 				 */
 				if (change & MIPS_CONF5_FRE &&
 				    vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
 					change_c0_config5(MIPS_CONF5_FRE, val);
 				/*
 				 * Propagate MSAEn changes immediately if the
 				 * MSA context is already loaded. When disabling
 				 * we leave the context loaded so it can be
 				 * quickly enabled again in the near future.
 				 */
 				if (change & MIPS_CONF5_MSAEN &&
 				    vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
 					change_c0_config5(MIPS_CONF5_MSAEN,
 							  val);
 				preempt_enable();
 				kvm_write_c0_guest_config5(cop0, val);
 			} else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
 				uint32_t old_cause, new_cause;
 				old_cause = kvm_read_c0_guest_cause(cop0);
 				new_cause = vcpu->arch.gprs[rt];
 				/* Update R/W bits */
 				kvm_change_c0_guest_cause(cop0, 0x08800300,
 							  new_cause);
 				/* DC bit enabling/disabling timer? */
 				if ((old_cause ^ new_cause) & CAUSEF_DC) {
 					if (new_cause & CAUSEF_DC)
 						kvm_mips_count_disable_cause(vcpu);
 					else
 						kvm_mips_count_enable_cause(vcpu);
 				}
 			} else {
 				cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 				kvm_mips_trans_mtc0(inst, opc, vcpu);
 #endif
 			}
 			kvm_debug("[%#x] MTCz, cop0->reg[%d][%d]: %#lx\n", pc,
 				  rd, sel, cop0->reg[rd][sel]);
 			break;
 		case dmtc_op:
 			kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
 				vcpu->arch.pc, rt, rd, sel);
 			er = EMULATE_FAIL;
 			break;
 		case mfmcz_op:
 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
 			cop0->stat[MIPS_CP0_STATUS][0]++;
 #endif
 			if (rt != 0) {
 				vcpu->arch.gprs[rt] =
 				    kvm_read_c0_guest_status(cop0);
 			}
 			/* EI */
 			if (inst & 0x20) {
 				kvm_debug("[%#lx] mfmcz_op: EI\n",
 					  vcpu->arch.pc);
 				kvm_set_c0_guest_status(cop0, ST0_IE);
 			} else {
 				kvm_debug("[%#lx] mfmcz_op: DI\n",
 					  vcpu->arch.pc);
 				kvm_clear_c0_guest_status(cop0, ST0_IE);
 			}
 			break;
 		case wrpgpr_op:
 			{
 				uint32_t css =
 				    cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
 				uint32_t pss =
 				    (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
 				/*
 				 * We don't support any shadow register sets, so
 				 * SRSCtl[PSS] == SRSCtl[CSS] = 0
 				 */
 				if (css || pss) {
 					er = EMULATE_FAIL;
 					break;
 				}
 				kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
 					  vcpu->arch.gprs[rt]);
 				vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
 			}
 			break;
 		default:
 			kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
 				vcpu->arch.pc, copz);
 			er = EMULATE_FAIL;
 			break;
 		}
 	}
 done:
 	/* Rollback PC only if emulation was unsuccessful */
 	if (er == EMULATE_FAIL)
 		vcpu->arch.pc = curr_pc;
 dont_update_pc:
 	/*
 	 * This is for special instructions whose emulation
 	 * updates the PC, so do not overwrite the PC under
 	 * any circumstances
 	 */
 	return er;
 }
 enum emulation_result kvm_mips_emulate_store(uint32_t inst, uint32_t cause,
 					     struct kvm_run *run,
 					     struct kvm_vcpu *vcpu)
 {
 	enum emulation_result er = EMULATE_DO_MMIO;
 	int32_t op, base, rt, offset;
 	uint32_t bytes;
 	void *data = run->mmio.data;
 	unsigned long curr_pc;
 	/*
 	 * Update PC and hold onto current PC in case there is
 	 * an error and we want to rollback the PC
 	 */
 	curr_pc = vcpu->arch.pc;
 	er = update_pc(vcpu, cause);
 	if (er == EMULATE_FAIL)
 		return er;
 	rt = (inst >> 16) & 0x1f;
 	base = (inst >> 21) & 0x1f;
 	offset = inst & 0xffff;
 	op = (inst >> 26) & 0x3f;
 	switch (op) {
 	case sb_op:
 		bytes = 1;
 		if (bytes > sizeof(run->mmio.data)) {
 			kvm_err("%s: bad MMIO length: %d\n", __func__,
 			       run->mmio.len);
 		}
 		run->mmio.phys_addr =
 		    kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
 						   host_cp0_badvaddr);
 		if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.len = bytes;
 		run->mmio.is_write = 1;
 		vcpu->mmio_needed = 1;
 		vcpu->mmio_is_write = 1;
 		*(u8 *) data = vcpu->arch.gprs[rt];
 		kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
 			  vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
 			  *(uint8_t *) data);
 		break;
 	case sw_op:
 		bytes = 4;
 		if (bytes > sizeof(run->mmio.data)) {
 			kvm_err("%s: bad MMIO length: %d\n", __func__,
 			       run->mmio.len);
 		}
 		run->mmio.phys_addr =
 		    kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
 						   host_cp0_badvaddr);
 		if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.len = bytes;
 		run->mmio.is_write = 1;
 		vcpu->mmio_needed = 1;
 		vcpu->mmio_is_write = 1;
 		*(uint32_t *) data = vcpu->arch.gprs[rt];
 		kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
 			  vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
 			  vcpu->arch.gprs[rt], *(uint32_t *) data);
 		break;
 	case sh_op:
 		bytes = 2;
 		if (bytes > sizeof(run->mmio.data)) {
 			kvm_err("%s: bad MMIO length: %d\n", __func__,
 			       run->mmio.len);
 		}
 		run->mmio.phys_addr =
 		    kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
 						   host_cp0_badvaddr);
 		if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.len = bytes;
 		run->mmio.is_write = 1;
 		vcpu->mmio_needed = 1;
 		vcpu->mmio_is_write = 1;
 		*(uint16_t *) data = vcpu->arch.gprs[rt];
 		kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
 			  vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
 			  vcpu->arch.gprs[rt], *(uint32_t *) data);
 		break;
 	default:
 		kvm_err("Store not yet supported");
 		er = EMULATE_FAIL;
 		break;
 	}
 	/* Rollback PC if emulation was unsuccessful */
 	if (er == EMULATE_FAIL)
 		vcpu->arch.pc = curr_pc;
 	return er;
 }
 enum emulation_result kvm_mips_emulate_load(uint32_t inst, uint32_t cause,
 					    struct kvm_run *run,
 					    struct kvm_vcpu *vcpu)
 {
 	enum emulation_result er = EMULATE_DO_MMIO;
 	int32_t op, base, rt, offset;
 	uint32_t bytes;
 	rt = (inst >> 16) & 0x1f;
 	base = (inst >> 21) & 0x1f;
 	offset = inst & 0xffff;
 	op = (inst >> 26) & 0x3f;
 	vcpu->arch.pending_load_cause = cause;
 	vcpu->arch.io_gpr = rt;
 	switch (op) {
 	case lw_op:
 		bytes = 4;
 		if (bytes > sizeof(run->mmio.data)) {
 			kvm_err("%s: bad MMIO length: %d\n", __func__,
 			       run->mmio.len);
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.phys_addr =
 		    kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
 						   host_cp0_badvaddr);
 		if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.len = bytes;
 		run->mmio.is_write = 0;
 		vcpu->mmio_needed = 1;
 		vcpu->mmio_is_write = 0;
 		break;
 	case lh_op:
 	case lhu_op:
 		bytes = 2;
 		if (bytes > sizeof(run->mmio.data)) {
 			kvm_err("%s: bad MMIO length: %d\n", __func__,
 			       run->mmio.len);
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.phys_addr =
 		    kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
 						   host_cp0_badvaddr);
 		if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.len = bytes;
 		run->mmio.is_write = 0;
 		vcpu->mmio_needed = 1;
 		vcpu->mmio_is_write = 0;
 		if (op == lh_op)
 			vcpu->mmio_needed = 2;
 		else
 			vcpu->mmio_needed = 1;
 		break;
 	case lbu_op:
 	case lb_op:
 		bytes = 1;
 		if (bytes > sizeof(run->mmio.data)) {
 			kvm_err("%s: bad MMIO length: %d\n", __func__,
 			       run->mmio.len);
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.phys_addr =
 		    kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
 						   host_cp0_badvaddr);
 		if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
 			er = EMULATE_FAIL;
 			break;
 		}
 		run->mmio.len = bytes;
 		run->mmio.is_write = 0;
 		vcpu->mmio_is_write = 0;
 		if (op == lb_op)
 			vcpu->mmio_needed = 2;
 		else
 			vcpu->mmio_needed = 1;
 		break;
 	default:
 		kvm_err("Load not yet supported");
 		er = EMULATE_FAIL;
 		break;
 	}
 	return er;
 }
 int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu *vcpu)
 {
 	unsigned long offset = (va & ~PAGE_MASK);
 	struct kvm *kvm = vcpu->kvm;
 	unsigned long pa;
 	gfn_t gfn;
 	pfn_t pfn;
 	gfn = va >> PAGE_SHIFT;
 	if (gfn >= kvm->arch.guest_pmap_npages) {
 		kvm_err("%s: Invalid gfn: %#llx\n", __func__, gfn);
 		kvm_mips_dump_host_tlbs();
 		kvm_arch_vcpu_dump_regs(vcpu);
 		return -1;
 	}
 	pfn = kvm->arch.guest_pmap[gfn];
 	pa = (pfn << PAGE_SHIFT) | offset;
 	kvm_debug("%s: va: %#lx, unmapped: %#x\n", __func__, va,
 		  CKSEG0ADDR(pa));
 	local_flush_icache_range(CKSEG0ADDR(pa), 32);
 	return 0;
 }
 #define MIPS_CACHE_OP_INDEX_INV         0x0
 #define MIPS_CACHE_OP_INDEX_LD_TAG      0x1
 #define MIPS_CACHE_OP_INDEX_ST_TAG      0x2
 #define MIPS_CACHE_OP_IMP               0x3
 #define MIPS_CACHE_OP_HIT_INV           0x4
 #define MIPS_CACHE_OP_FILL_WB_INV       0x5
 #define MIPS_CACHE_OP_HIT_HB            0x6
 #define MIPS_CACHE_OP_FETCH_LOCK        0x7
 #define MIPS_CACHE_ICACHE               0x0
 #define MIPS_CACHE_DCACHE               0x1
 #define MIPS_CACHE_SEC                  0x3
 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
 					     uint32_t cause,
 					     struct kvm_run *run,
 					     struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	enum emulation_result er = EMULATE_DONE;
 	int32_t offset, cache, op_inst, op, base;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	unsigned long va;
 	unsigned long curr_pc;
 	/*
 	 * Update PC and hold onto current PC in case there is
 	 * an error and we want to rollback the PC
 	 */
 	curr_pc = vcpu->arch.pc;
 	er = update_pc(vcpu, cause);
 	if (er == EMULATE_FAIL)
 		return er;
 	base = (inst >> 21) & 0x1f;
 	op_inst = (inst >> 16) & 0x1f;
 	offset = (int16_t)inst;
 	cache = (inst >> 16) & 0x3;
 	op = (inst >> 18) & 0x7;
 	va = arch->gprs[base] + offset;
 	kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
 		  cache, op, base, arch->gprs[base], offset);
 	/*
 	 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
 	 * invalidate the caches entirely by stepping through all the
 	 * ways/indexes
 	 */
 	if (op == MIPS_CACHE_OP_INDEX_INV) {
 		kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
 			  vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
 			  arch->gprs[base], offset);
 		if (cache == MIPS_CACHE_DCACHE)
 			r4k_blast_dcache();
 		else if (cache == MIPS_CACHE_ICACHE)
 			r4k_blast_icache();
 		else {
 			kvm_err("%s: unsupported CACHE INDEX operation\n",
 				__func__);
 			return EMULATE_FAIL;
 		}
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 		kvm_mips_trans_cache_index(inst, opc, vcpu);
 #endif
 		goto done;
 	}
 	preempt_disable();
 	if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
 		if (kvm_mips_host_tlb_lookup(vcpu, va) < 0)
 			kvm_mips_handle_kseg0_tlb_fault(va, vcpu);
 	} else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
 		   KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
 		int index;
 		/* If an entry already exists then skip */
 		if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
 			goto skip_fault;
 		/*
 		 * If address not in the guest TLB, then give the guest a fault,
 		 * the resulting handler will do the right thing
 		 */
 		index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
 						  (kvm_read_c0_guest_entryhi
 						   (cop0) & ASID_MASK));
 		if (index < 0) {
 			vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
 			vcpu->arch.host_cp0_badvaddr = va;
 			er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
 							 vcpu);
 			preempt_enable();
 			goto dont_update_pc;
 		} else {
 			struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
 			/*
 			 * Check if the entry is valid, if not then setup a TLB
 			 * invalid exception to the guest
 			 */
 			if (!TLB_IS_VALID(*tlb, va)) {
 				er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
 								run, vcpu);
 				preempt_enable();
 				goto dont_update_pc;
 			} else {
 				/*
 				 * We fault an entry from the guest tlb to the
 				 * shadow host TLB
 				 */
 				kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
 								     NULL,
 								     NULL);
 			}
 		}
 	} else {
 		kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
 			cache, op, base, arch->gprs[base], offset);
 		er = EMULATE_FAIL;
 		preempt_enable();
 		goto dont_update_pc;
 	}
 skip_fault:
 	/* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
 	if (cache == MIPS_CACHE_DCACHE
 	    && (op == MIPS_CACHE_OP_FILL_WB_INV
 		|| op == MIPS_CACHE_OP_HIT_INV)) {
 		flush_dcache_line(va);
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 		/*
 		 * Replace the CACHE instruction, with a SYNCI, not the same,
 		 * but avoids a trap
 		 */
 		kvm_mips_trans_cache_va(inst, opc, vcpu);
 #endif
 	} else if (op == MIPS_CACHE_OP_HIT_INV && cache == MIPS_CACHE_ICACHE) {
 		flush_dcache_line(va);
 		flush_icache_line(va);
 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
 		/* Replace the CACHE instruction, with a SYNCI */
 		kvm_mips_trans_cache_va(inst, opc, vcpu);
 #endif
 	} else {
 		kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
 			cache, op, base, arch->gprs[base], offset);
 		er = EMULATE_FAIL;
 		preempt_enable();
 		goto dont_update_pc;
 	}
 	preempt_enable();
 dont_update_pc:
 	/* Rollback PC */
 	vcpu->arch.pc = curr_pc;
 done:
 	return er;
 }
 enum emulation_result kvm_mips_emulate_inst(unsigned long cause, uint32_t *opc,
 					    struct kvm_run *run,
 					    struct kvm_vcpu *vcpu)
 {
 	enum emulation_result er = EMULATE_DONE;
 	uint32_t inst;
 	/* Fetch the instruction. */
 	if (cause & CAUSEF_BD)
 		opc += 1;
 	inst = kvm_get_inst(opc, vcpu);
 	switch (((union mips_instruction)inst).r_format.opcode) {
 	case cop0_op:
 		er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
 		break;
 	case sb_op:
 	case sh_op:
 	case sw_op:
 		er = kvm_mips_emulate_store(inst, cause, run, vcpu);
 		break;
 	case lb_op:
 	case lbu_op:
 	case lhu_op:
 	case lh_op:
 	case lw_op:
 		er = kvm_mips_emulate_load(inst, cause, run, vcpu);
 		break;
 	case cache_op:
 		++vcpu->stat.cache_exits;
 		trace_kvm_exit(vcpu, CACHE_EXITS);
 		er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
 		break;
 	default:
 		kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
 			inst);
 		kvm_arch_vcpu_dump_regs(vcpu);
 		er = EMULATE_FAIL;
 		break;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
 					       uint32_t *opc,
 					       struct kvm_run *run,
 					       struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_SYSCALL << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
 						  uint32_t *opc,
 						  struct kvm_run *run,
 						  struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	unsigned long entryhi = (vcpu->arch.  host_cp0_badvaddr & VPN2_MASK) |
 				(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		/* set pc to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x0;
 	} else {
 		kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	}
 	kvm_change_c0_guest_cause(cop0, (0xff),
 				  (T_TLB_LD_MISS << CAUSEB_EXCCODE));
 	/* setup badvaddr, context and entryhi registers for the guest */
 	kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
 	/* XXXKYMA: is the context register used by linux??? */
 	kvm_write_c0_guest_entryhi(cop0, entryhi);
 	/* Blow away the shadow host TLBs */
 	kvm_mips_flush_host_tlb(1);
 	return EMULATE_DONE;
 }
 enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
 						 uint32_t *opc,
 						 struct kvm_run *run,
 						 struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	unsigned long entryhi =
 		(vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
 		(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
 			  arch->pc);
 		/* set pc to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	}
 	kvm_change_c0_guest_cause(cop0, (0xff),
 				  (T_TLB_LD_MISS << CAUSEB_EXCCODE));
 	/* setup badvaddr, context and entryhi registers for the guest */
 	kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
 	/* XXXKYMA: is the context register used by linux??? */
 	kvm_write_c0_guest_entryhi(cop0, entryhi);
 	/* Blow away the shadow host TLBs */
 	kvm_mips_flush_host_tlb(1);
 	return EMULATE_DONE;
 }
 enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
 						  uint32_t *opc,
 						  struct kvm_run *run,
 						  struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
 				(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x0;
 	} else {
 		kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	}
 	kvm_change_c0_guest_cause(cop0, (0xff),
 				  (T_TLB_ST_MISS << CAUSEB_EXCCODE));
 	/* setup badvaddr, context and entryhi registers for the guest */
 	kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
 	/* XXXKYMA: is the context register used by linux??? */
 	kvm_write_c0_guest_entryhi(cop0, entryhi);
 	/* Blow away the shadow host TLBs */
 	kvm_mips_flush_host_tlb(1);
 	return EMULATE_DONE;
 }
 enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
 						 uint32_t *opc,
 						 struct kvm_run *run,
 						 struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
 		(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
 			  arch->pc);
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	}
 	kvm_change_c0_guest_cause(cop0, (0xff),
 				  (T_TLB_ST_MISS << CAUSEB_EXCCODE));
 	/* setup badvaddr, context and entryhi registers for the guest */
 	kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
 	/* XXXKYMA: is the context register used by linux??? */
 	kvm_write_c0_guest_entryhi(cop0, entryhi);
 	/* Blow away the shadow host TLBs */
 	kvm_mips_flush_host_tlb(1);
 	return EMULATE_DONE;
 }
 /* TLBMOD: store into address matching TLB with Dirty bit off */
 enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, uint32_t *opc,
 					     struct kvm_run *run,
 					     struct kvm_vcpu *vcpu)
 {
 	enum emulation_result er = EMULATE_DONE;
 #ifdef DEBUG
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
 				(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
 	int index;
 	/* If address not in the guest TLB, then we are in trouble */
 	index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
 	if (index < 0) {
 		/* XXXKYMA Invalidate and retry */
 		kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
 		kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
 		     __func__, entryhi);
 		kvm_mips_dump_guest_tlbs(vcpu);
 		kvm_mips_dump_host_tlbs();
 		return EMULATE_FAIL;
 	}
 #endif
 	er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
 	return er;
 }
 enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
 					      uint32_t *opc,
 					      struct kvm_run *run,
 					      struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
 				(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
 			  arch->pc);
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
 			  arch->pc);
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	}
 	kvm_change_c0_guest_cause(cop0, (0xff), (T_TLB_MOD << CAUSEB_EXCCODE));
 	/* setup badvaddr, context and entryhi registers for the guest */
 	kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
 	/* XXXKYMA: is the context register used by linux??? */
 	kvm_write_c0_guest_entryhi(cop0, entryhi);
 	/* Blow away the shadow host TLBs */
 	kvm_mips_flush_host_tlb(1);
 	return EMULATE_DONE;
 }
 enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
 					       uint32_t *opc,
 					       struct kvm_run *run,
 					       struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 	}
 	arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	kvm_change_c0_guest_cause(cop0, (0xff),
 				  (T_COP_UNUSABLE << CAUSEB_EXCCODE));
 	kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
 	return EMULATE_DONE;
 }
 enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
 					      uint32_t *opc,
 					      struct kvm_run *run,
 					      struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_RES_INST << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver RI when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
 					      uint32_t *opc,
 					      struct kvm_run *run,
 					      struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_BREAK << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver BP when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
 						uint32_t *opc,
 						struct kvm_run *run,
 						struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_TRAP << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver TRAP when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
 						  uint32_t *opc,
 						  struct kvm_run *run,
 						  struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_MSAFPE << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
 					       uint32_t *opc,
 					       struct kvm_run *run,
 					       struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_FPE << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver FPE when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
 						  uint32_t *opc,
 						  struct kvm_run *run,
 						  struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (T_MSADIS << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 	} else {
 		kvm_err("Trying to deliver MSADIS when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 /* ll/sc, rdhwr, sync emulation */
 #define OPCODE 0xfc000000
 #define BASE   0x03e00000
 #define RT     0x001f0000
 #define OFFSET 0x0000ffff
 #define LL     0xc0000000
 #define SC     0xe0000000
 #define SPEC0  0x00000000
 #define SPEC3  0x7c000000
 #define RD     0x0000f800
 #define FUNC   0x0000003f
 #define SYNC   0x0000000f
 #define RDHWR  0x0000003b
 enum emulation_result kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
 					 struct kvm_run *run,
 					 struct kvm_vcpu *vcpu)
 {
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	unsigned long curr_pc;
 	uint32_t inst;
 	/*
 	 * Update PC and hold onto current PC in case there is
 	 * an error and we want to rollback the PC
 	 */
 	curr_pc = vcpu->arch.pc;
 	er = update_pc(vcpu, cause);
 	if (er == EMULATE_FAIL)
 		return er;
 	/* Fetch the instruction. */
 	if (cause & CAUSEF_BD)
 		opc += 1;
 	inst = kvm_get_inst(opc, vcpu);
 	if (inst == KVM_INVALID_INST) {
 		kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
 		return EMULATE_FAIL;
 	}
 	if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
 		int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
 		int rd = (inst & RD) >> 11;
 		int rt = (inst & RT) >> 16;
 		/* If usermode, check RDHWR rd is allowed by guest HWREna */
 		if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
 			kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
 				  rd, opc);
 			goto emulate_ri;
 		}
 		switch (rd) {
 		case 0:	/* CPU number */
 			arch->gprs[rt] = 0;
 			break;
 		case 1:	/* SYNCI length */
 			arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
 					     current_cpu_data.icache.linesz);
 			break;
 		case 2:	/* Read count register */
 			arch->gprs[rt] = kvm_mips_read_count(vcpu);
 			break;
 		case 3:	/* Count register resolution */
 			switch (current_cpu_data.cputype) {
 			case CPU_20KC:
 			case CPU_25KF:
 				arch->gprs[rt] = 1;
 				break;
 			default:
 				arch->gprs[rt] = 2;
 			}
 			break;
 		case 29:
 			arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
 			break;
 		default:
 			kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
 			goto emulate_ri;
 		}
 	} else {
 		kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
 		goto emulate_ri;
 	}
 	return EMULATE_DONE;
 emulate_ri:
 	/*
 	 * Rollback PC (if in branch delay slot then the PC already points to
 	 * branch target), and pass the RI exception to the guest OS.
 	 */
 	vcpu->arch.pc = curr_pc;
 	return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
 }
 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 						  struct kvm_run *run)
 {
 	unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
 	enum emulation_result er = EMULATE_DONE;
 	if (run->mmio.len > sizeof(*gpr)) {
 		kvm_err("Bad MMIO length: %d", run->mmio.len);
 		er = EMULATE_FAIL;
 		goto done;
 	}
 	er = update_pc(vcpu, vcpu->arch.pending_load_cause);
 	if (er == EMULATE_FAIL)
 		return er;
 	switch (run->mmio.len) {
 	case 4:
 		*gpr = *(int32_t *) run->mmio.data;
 		break;
 	case 2:
 		if (vcpu->mmio_needed == 2)
 			*gpr = *(int16_t *) run->mmio.data;
 		else
 			*gpr = *(uint16_t *)run->mmio.data;
 		break;
 	case 1:
 		if (vcpu->mmio_needed == 2)
 			*gpr = *(int8_t *) run->mmio.data;
 		else
 			*gpr = *(u8 *) run->mmio.data;
 		break;
 	}
 	if (vcpu->arch.pending_load_cause & CAUSEF_BD)
 		kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n",
 			  vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr,
 			  vcpu->mmio_needed);
 done:
 	return er;
 }
 static enum emulation_result kvm_mips_emulate_exc(unsigned long cause,
 						  uint32_t *opc,
 						  struct kvm_run *run,
 						  struct kvm_vcpu *vcpu)
 {
 	uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
 	struct mips_coproc *cop0 = vcpu->arch.cop0;
 	struct kvm_vcpu_arch *arch = &vcpu->arch;
 	enum emulation_result er = EMULATE_DONE;
 	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
 		/* save old pc */
 		kvm_write_c0_guest_epc(cop0, arch->pc);
 		kvm_set_c0_guest_status(cop0, ST0_EXL);
 		if (cause & CAUSEF_BD)
 			kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
 		else
 			kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
 		kvm_change_c0_guest_cause(cop0, (0xff),
 					  (exccode << CAUSEB_EXCCODE));
 		/* Set PC to the exception entry point */
 		arch->pc = KVM_GUEST_KSEG0 + 0x180;
 		kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
 		kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
 			  exccode, kvm_read_c0_guest_epc(cop0),
 			  kvm_read_c0_guest_badvaddr(cop0));
 	} else {
 		kvm_err("Trying to deliver EXC when EXL is already set\n");
 		er = EMULATE_FAIL;
 	}
 	return er;
 }
 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
 					       uint32_t *opc,
 					       struct kvm_run *run,
 					       struct kvm_vcpu *vcpu)
 {
 	enum emulation_result er = EMULATE_DONE;
 	uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
 	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
 	int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
 	if (usermode) {
 		switch (exccode) {
 		case T_INT:
 		case T_SYSCALL:
 		case T_BREAK:
 		case T_RES_INST:
 		case T_TRAP:
 		case T_MSAFPE:
 		case T_FPE:
 		case T_MSADIS:
 			break;
 		case T_COP_UNUSABLE:
 			if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
 				er = EMULATE_PRIV_FAIL;
 			break;
 		case T_TLB_MOD:
 			break;
 		case T_TLB_LD_MISS:
 			/*
 			 * We we are accessing Guest kernel space, then send an
 			 * address error exception to the guest
 			 */
 			if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
 				kvm_debug("%s: LD MISS @ %#lx\n", __func__,
 					  badvaddr);
 				cause &= ~0xff;
 				cause |= (T_ADDR_ERR_LD << CAUSEB_EXCCODE);
 				er = EMULATE_PRIV_FAIL;
 			}
 			break;
 		case T_TLB_ST_MISS:
 			/*
 			 * We we are accessing Guest kernel space, then send an
 			 * address error exception to the guest
 			 */
 			if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
 				kvm_debug("%s: ST MISS @ %#lx\n", __func__,
 					  badvaddr);
 				cause &= ~0xff;
 				cause |= (T_ADDR_ERR_ST << CAUSEB_EXCCODE);
 				er = EMULATE_PRIV_FAIL;
 			}
 			break;
 		case T_ADDR_ERR_ST:
 			kvm_debug("%s: address error ST @ %#lx\n", __func__,
 				  badvaddr);
 			if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
 				cause &= ~0xff;
 				cause |= (T_TLB_ST_MISS << CAUSEB_EXCCODE);
 			}
 			er = EMULATE_PRIV_FAIL;
 			break;
 		case T_ADDR_ERR_LD:
 			kvm_debug("%s: address error LD @ %#lx\n", __func__,
 				  badvaddr);
 			if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
 				cause &= ~0xff;
 				cause |= (T_TLB_LD_MISS << CAUSEB_EXCCODE);
 			}
 			er = EMULATE_PRIV_FAIL;
 			break;
 		default:
 			er = EMULATE_PRIV_FAIL;
 			break;
 		}
 	}
 	if (er == EMULATE_PRIV_FAIL)
 		kvm_mips_emulate_exc(cause, opc, run, vcpu);
 	return er;
 }
 /*
  * User Address (UA) fault, this could happen if
  * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
  *     case we pass on the fault to the guest kernel and let it handle it.
  * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
  *     case we inject the TLB from the Guest TLB into the shadow host TLB
  */
 enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
 					      uint32_t *opc,
 					      struct kvm_run *run,
 					      struct kvm_vcpu *vcpu)
 {
 	enum emulation_result er = EMULATE_DONE;
 	uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
 	unsigned long va = vcpu->arch.host_cp0_badvaddr;
 	int index;
 	kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx, entryhi: %#lx\n",
 		  vcpu->arch.host_cp0_badvaddr, vcpu->arch.host_cp0_entryhi);
 	/*
 	 * KVM would not have got the exception if this entry was valid in the
 	 * shadow host TLB. Check the Guest TLB, if the entry is not there then
 	 * send the guest an exception. The guest exc handler should then inject
 	 * an entry into the guest TLB.
 	 */
 	index = kvm_mips_guest_tlb_lookup(vcpu,
 					  (va & VPN2_MASK) |
 					  (kvm_read_c0_guest_entryhi
 					   (vcpu->arch.cop0) & ASID_MASK));
 	if (index < 0) {
 		if (exccode == T_TLB_LD_MISS) {
 			er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
 		} else if (exccode == T_TLB_ST_MISS) {
 			er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
 		} else {
 			kvm_err("%s: invalid exc code: %d\n", __func__,
 				exccode);
 			er = EMULATE_FAIL;
 		}
 	} else {
 		struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
 		/*
 		 * Check if the entry is valid, if not then setup a TLB invalid
 		 * exception to the guest
 		 */
 		if (!TLB_IS_VALID(*tlb, va)) {
 			if (exccode == T_TLB_LD_MISS) {
 				er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
 								vcpu);
 			} else if (exccode == T_TLB_ST_MISS) {
 				er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
 								vcpu);

arch/mips/kvm/trap_emul.c

Diff comments View file @ a6fa60f

1	/*	1	/*
2	* This file is subject to the terms and conditions of the GNU General Public	2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive	3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.	4	* for more details.
5	*	5	*
6	* KVM/MIPS: Deliver/Emulate exceptions to the guest kernel	6	* KVM/MIPS: Deliver/Emulate exceptions to the guest kernel
7	*	7	*
8	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.	8	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9	* Authors: Sanjay Lal <sanjayl@kymasys.com>	9	* Authors: Sanjay Lal <sanjayl@kymasys.com>
10	*/	10	*/
11		11
12	#include <linux/errno.h>	12	#include <linux/errno.h>
13	#include <linux/err.h>	13	#include <linux/err.h>
14	#include <linux/module.h>	14	#include <linux/module.h>
15	#include <linux/vmalloc.h>	15	#include <linux/vmalloc.h>
16		16
17	#include <linux/kvm_host.h>	17	#include <linux/kvm_host.h>
18		18
19	#include "opcode.h"	19	#include "opcode.h"
20	#include "interrupt.h"	20	#include "interrupt.h"
21		21
22	static gpa_t kvm_trap_emul_gva_to_gpa_cb(gva_t gva)	22	static gpa_t kvm_trap_emul_gva_to_gpa_cb(gva_t gva)
23	{	23	{
24	gpa_t gpa;	24	gpa_t gpa;
25	uint32_t kseg = KSEGX(gva);	25	uint32_t kseg = KSEGX(gva);
26		26
27	if ((kseg == CKSEG0) \|\| (kseg == CKSEG1))	27	if ((kseg == CKSEG0) \|\| (kseg == CKSEG1))
28	gpa = CPHYSADDR(gva);	28	gpa = CPHYSADDR(gva);
29	else {	29	else {
30	kvm_err("%s: cannot find GPA for GVA: %#lx\n", __func__, gva);	30	kvm_err("%s: cannot find GPA for GVA: %#lx\n", __func__, gva);
31	kvm_mips_dump_host_tlbs();	31	kvm_mips_dump_host_tlbs();
32	gpa = KVM_INVALID_ADDR;	32	gpa = KVM_INVALID_ADDR;
33	}	33	}
34		34
35	kvm_debug("%s: gva %#lx, gpa: %#llx\n", __func__, gva, gpa);	35	kvm_debug("%s: gva %#lx, gpa: %#llx\n", __func__, gva, gpa);
36		36
37	return gpa;	37	return gpa;
38	}	38	}
39		39
40	static int kvm_trap_emul_handle_cop_unusable(struct kvm_vcpu *vcpu)	40	static int kvm_trap_emul_handle_cop_unusable(struct kvm_vcpu *vcpu)
41	{	41	{
42	struct mips_coproc *cop0 = vcpu->arch.cop0;	42	struct mips_coproc *cop0 = vcpu->arch.cop0;
43	struct kvm_run *run = vcpu->run;	43	struct kvm_run *run = vcpu->run;
44	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	44	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
45	unsigned long cause = vcpu->arch.host_cp0_cause;	45	unsigned long cause = vcpu->arch.host_cp0_cause;
46	enum emulation_result er = EMULATE_DONE;	46	enum emulation_result er = EMULATE_DONE;
47	int ret = RESUME_GUEST;	47	int ret = RESUME_GUEST;
48		48
49	if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 1) {	49	if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 1) {
50	/* FPU Unusable */	50	/* FPU Unusable */
51	if (!kvm_mips_guest_has_fpu(&vcpu->arch) \|\|	51	if (!kvm_mips_guest_has_fpu(&vcpu->arch) \|\|
52	(kvm_read_c0_guest_status(cop0) & ST0_CU1) == 0) {	52	(kvm_read_c0_guest_status(cop0) & ST0_CU1) == 0) {
53	/*	53	/*
54	* Unusable/no FPU in guest:	54	* Unusable/no FPU in guest:
55	* deliver guest COP1 Unusable Exception	55	* deliver guest COP1 Unusable Exception
56	*/	56	*/
57	er = kvm_mips_emulate_fpu_exc(cause, opc, run, vcpu);	57	er = kvm_mips_emulate_fpu_exc(cause, opc, run, vcpu);
58	} else {	58	} else {
59	/* Restore FPU state */	59	/* Restore FPU state */
60	kvm_own_fpu(vcpu);	60	kvm_own_fpu(vcpu);
61	er = EMULATE_DONE;	61	er = EMULATE_DONE;
62	}	62	}
63	} else {	63	} else {
64	er = kvm_mips_emulate_inst(cause, opc, run, vcpu);	64	er = kvm_mips_emulate_inst(cause, opc, run, vcpu);
65	}	65	}
66		66
67	switch (er) {	67	switch (er) {
68	case EMULATE_DONE:	68	case EMULATE_DONE:
69	ret = RESUME_GUEST;	69	ret = RESUME_GUEST;
70	break;	70	break;
71		71
72	case EMULATE_FAIL:	72	case EMULATE_FAIL:
73	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	73	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
74	ret = RESUME_HOST;	74	ret = RESUME_HOST;
75	break;	75	break;
76		76
77	case EMULATE_WAIT:	77	case EMULATE_WAIT:
78	run->exit_reason = KVM_EXIT_INTR;	78	run->exit_reason = KVM_EXIT_INTR;
79	ret = RESUME_HOST;	79	ret = RESUME_HOST;
80	break;	80	break;
81		81
82	default:	82	default:
83	BUG();	83	BUG();
84	}	84	}
85	return ret;	85	return ret;
86	}	86	}
87		87
88	static int kvm_trap_emul_handle_tlb_mod(struct kvm_vcpu *vcpu)	88	static int kvm_trap_emul_handle_tlb_mod(struct kvm_vcpu *vcpu)
89	{	89	{
90	struct kvm_run *run = vcpu->run;	90	struct kvm_run *run = vcpu->run;
91	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	91	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
92	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;	92	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
93	unsigned long cause = vcpu->arch.host_cp0_cause;	93	unsigned long cause = vcpu->arch.host_cp0_cause;
94	enum emulation_result er = EMULATE_DONE;	94	enum emulation_result er = EMULATE_DONE;
95	int ret = RESUME_GUEST;	95	int ret = RESUME_GUEST;
96		96
97	if (KVM_GUEST_KSEGX(badvaddr) < KVM_GUEST_KSEG0	97	if (KVM_GUEST_KSEGX(badvaddr) < KVM_GUEST_KSEG0
98	\|\| KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG23) {	98	\|\| KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG23) {
99	kvm_debug("USER/KSEG23 ADDR TLB MOD fault: cause %#lx, PC: %p, BadVaddr: %#lx\n",	99	kvm_debug("USER/KSEG23 ADDR TLB MOD fault: cause %#lx, PC: %p, BadVaddr: %#lx\n",
100	cause, opc, badvaddr);	100	cause, opc, badvaddr);
101	er = kvm_mips_handle_tlbmod(cause, opc, run, vcpu);	101	er = kvm_mips_handle_tlbmod(cause, opc, run, vcpu);
102		102
103	if (er == EMULATE_DONE)	103	if (er == EMULATE_DONE)
104	ret = RESUME_GUEST;	104	ret = RESUME_GUEST;
105	else {	105	else {
106	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	106	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
107	ret = RESUME_HOST;	107	ret = RESUME_HOST;
108	}	108	}
109	} else if (KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG0) {	109	} else if (KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG0) {
110	/*	110	/*
111	* XXXKYMA: The guest kernel does not expect to get this fault	111	* XXXKYMA: The guest kernel does not expect to get this fault
112	* when we are not using HIGHMEM. Need to address this in a	112	* when we are not using HIGHMEM. Need to address this in a
113	* HIGHMEM kernel	113	* HIGHMEM kernel
114	*/	114	*/
115	kvm_err("TLB MOD fault not handled, cause %#lx, PC: %p, BadVaddr: %#lx\n",	115	kvm_err("TLB MOD fault not handled, cause %#lx, PC: %p, BadVaddr: %#lx\n",
116	cause, opc, badvaddr);	116	cause, opc, badvaddr);
117	kvm_mips_dump_host_tlbs();	117	kvm_mips_dump_host_tlbs();
118	kvm_arch_vcpu_dump_regs(vcpu);	118	kvm_arch_vcpu_dump_regs(vcpu);
119	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	119	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
120	ret = RESUME_HOST;	120	ret = RESUME_HOST;
121	} else {	121	} else {
122	kvm_err("Illegal TLB Mod fault address , cause %#lx, PC: %p, BadVaddr: %#lx\n",	122	kvm_err("Illegal TLB Mod fault address , cause %#lx, PC: %p, BadVaddr: %#lx\n",
123	cause, opc, badvaddr);	123	cause, opc, badvaddr);
124	kvm_mips_dump_host_tlbs();	124	kvm_mips_dump_host_tlbs();
125	kvm_arch_vcpu_dump_regs(vcpu);	125	kvm_arch_vcpu_dump_regs(vcpu);
126	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	126	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
127	ret = RESUME_HOST;	127	ret = RESUME_HOST;
128	}	128	}
129	return ret;	129	return ret;
130	}	130	}
131		131
132	static int kvm_trap_emul_handle_tlb_st_miss(struct kvm_vcpu *vcpu)	132	static int kvm_trap_emul_handle_tlb_st_miss(struct kvm_vcpu *vcpu)
133	{	133	{
134	struct kvm_run *run = vcpu->run;	134	struct kvm_run *run = vcpu->run;
135	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	135	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
136	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;	136	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
137	unsigned long cause = vcpu->arch.host_cp0_cause;	137	unsigned long cause = vcpu->arch.host_cp0_cause;
138	enum emulation_result er = EMULATE_DONE;	138	enum emulation_result er = EMULATE_DONE;
139	int ret = RESUME_GUEST;	139	int ret = RESUME_GUEST;
140		140
141	if (((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR)	141	if (((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR)
142	&& KVM_GUEST_KERNEL_MODE(vcpu)) {	142	&& KVM_GUEST_KERNEL_MODE(vcpu)) {
143	if (kvm_mips_handle_commpage_tlb_fault(badvaddr, vcpu) < 0) {	143	if (kvm_mips_handle_commpage_tlb_fault(badvaddr, vcpu) < 0) {
144	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	144	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
145	ret = RESUME_HOST;	145	ret = RESUME_HOST;
146	}	146	}
147	} else if (KVM_GUEST_KSEGX(badvaddr) < KVM_GUEST_KSEG0	147	} else if (KVM_GUEST_KSEGX(badvaddr) < KVM_GUEST_KSEG0
148	\|\| KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG23) {	148	\|\| KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG23) {
149	kvm_debug("USER ADDR TLB LD fault: cause %#lx, PC: %p, BadVaddr: %#lx\n",	149	kvm_debug("USER ADDR TLB LD fault: cause %#lx, PC: %p, BadVaddr: %#lx\n",
150	cause, opc, badvaddr);	150	cause, opc, badvaddr);
151	er = kvm_mips_handle_tlbmiss(cause, opc, run, vcpu);	151	er = kvm_mips_handle_tlbmiss(cause, opc, run, vcpu);
152	if (er == EMULATE_DONE)	152	if (er == EMULATE_DONE)
153	ret = RESUME_GUEST;	153	ret = RESUME_GUEST;
154	else {	154	else {
155	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	155	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
156	ret = RESUME_HOST;	156	ret = RESUME_HOST;
157	}	157	}
158	} else if (KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG0) {	158	} else if (KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG0) {
159	/*	159	/*
160	* All KSEG0 faults are handled by KVM, as the guest kernel does	160	* All KSEG0 faults are handled by KVM, as the guest kernel does
161	* not expect to ever get them	161	* not expect to ever get them
162	*/	162	*/
163	if (kvm_mips_handle_kseg0_tlb_fault	163	if (kvm_mips_handle_kseg0_tlb_fault
164	(vcpu->arch.host_cp0_badvaddr, vcpu) < 0) {	164	(vcpu->arch.host_cp0_badvaddr, vcpu) < 0) {
165	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	165	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
166	ret = RESUME_HOST;	166	ret = RESUME_HOST;
167	}	167	}
168	} else {	168	} else {
169	kvm_err("Illegal TLB LD fault address , cause %#lx, PC: %p, BadVaddr: %#lx\n",	169	kvm_err("Illegal TLB LD fault address , cause %#lx, PC: %p, BadVaddr: %#lx\n",
170	cause, opc, badvaddr);	170	cause, opc, badvaddr);
171	kvm_mips_dump_host_tlbs();	171	kvm_mips_dump_host_tlbs();
172	kvm_arch_vcpu_dump_regs(vcpu);	172	kvm_arch_vcpu_dump_regs(vcpu);
173	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	173	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
174	ret = RESUME_HOST;	174	ret = RESUME_HOST;
175	}	175	}
176	return ret;	176	return ret;
177	}	177	}
178		178
179	static int kvm_trap_emul_handle_tlb_ld_miss(struct kvm_vcpu *vcpu)	179	static int kvm_trap_emul_handle_tlb_ld_miss(struct kvm_vcpu *vcpu)
180	{	180	{
181	struct kvm_run *run = vcpu->run;	181	struct kvm_run *run = vcpu->run;
182	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	182	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
183	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;	183	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
184	unsigned long cause = vcpu->arch.host_cp0_cause;	184	unsigned long cause = vcpu->arch.host_cp0_cause;
185	enum emulation_result er = EMULATE_DONE;	185	enum emulation_result er = EMULATE_DONE;
186	int ret = RESUME_GUEST;	186	int ret = RESUME_GUEST;
187		187
188	if (((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR)	188	if (((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR)
189	&& KVM_GUEST_KERNEL_MODE(vcpu)) {	189	&& KVM_GUEST_KERNEL_MODE(vcpu)) {
190	if (kvm_mips_handle_commpage_tlb_fault(badvaddr, vcpu) < 0) {	190	if (kvm_mips_handle_commpage_tlb_fault(badvaddr, vcpu) < 0) {
191	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	191	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
192	ret = RESUME_HOST;	192	ret = RESUME_HOST;
193	}	193	}
194	} else if (KVM_GUEST_KSEGX(badvaddr) < KVM_GUEST_KSEG0	194	} else if (KVM_GUEST_KSEGX(badvaddr) < KVM_GUEST_KSEG0
195	\|\| KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG23) {	195	\|\| KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG23) {
196	kvm_debug("USER ADDR TLB ST fault: PC: %#lx, BadVaddr: %#lx\n",	196	kvm_debug("USER ADDR TLB ST fault: PC: %#lx, BadVaddr: %#lx\n",
197	vcpu->arch.pc, badvaddr);	197	vcpu->arch.pc, badvaddr);
198		198
199	/*	199	/*
200	* User Address (UA) fault, this could happen if	200	* User Address (UA) fault, this could happen if
201	* (1) TLB entry not present/valid in both Guest and shadow host	201	* (1) TLB entry not present/valid in both Guest and shadow host
202	* TLBs, in this case we pass on the fault to the guest	202	* TLBs, in this case we pass on the fault to the guest
203	* kernel and let it handle it.	203	* kernel and let it handle it.
204	* (2) TLB entry is present in the Guest TLB but not in the	204	* (2) TLB entry is present in the Guest TLB but not in the
205	* shadow, in this case we inject the TLB from the Guest TLB	205	* shadow, in this case we inject the TLB from the Guest TLB
206	* into the shadow host TLB	206	* into the shadow host TLB
207	*/	207	*/
208		208
209	er = kvm_mips_handle_tlbmiss(cause, opc, run, vcpu);	209	er = kvm_mips_handle_tlbmiss(cause, opc, run, vcpu);
210	if (er == EMULATE_DONE)	210	if (er == EMULATE_DONE)
211	ret = RESUME_GUEST;	211	ret = RESUME_GUEST;
212	else {	212	else {
213	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	213	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
214	ret = RESUME_HOST;	214	ret = RESUME_HOST;
215	}	215	}
216	} else if (KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG0) {	216	} else if (KVM_GUEST_KSEGX(badvaddr) == KVM_GUEST_KSEG0) {
217	if (kvm_mips_handle_kseg0_tlb_fault	217	if (kvm_mips_handle_kseg0_tlb_fault
218	(vcpu->arch.host_cp0_badvaddr, vcpu) < 0) {	218	(vcpu->arch.host_cp0_badvaddr, vcpu) < 0) {
219	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	219	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
220	ret = RESUME_HOST;	220	ret = RESUME_HOST;
221	}	221	}
222	} else {	222	} else {
223	kvm_err("Illegal TLB ST fault address , cause %#lx, PC: %p, BadVaddr: %#lx\n",	223	kvm_err("Illegal TLB ST fault address , cause %#lx, PC: %p, BadVaddr: %#lx\n",
224	cause, opc, badvaddr);	224	cause, opc, badvaddr);
225	kvm_mips_dump_host_tlbs();	225	kvm_mips_dump_host_tlbs();
226	kvm_arch_vcpu_dump_regs(vcpu);	226	kvm_arch_vcpu_dump_regs(vcpu);
227	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	227	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
228	ret = RESUME_HOST;	228	ret = RESUME_HOST;
229	}	229	}
230	return ret;	230	return ret;
231	}	231	}
232		232
233	static int kvm_trap_emul_handle_addr_err_st(struct kvm_vcpu *vcpu)	233	static int kvm_trap_emul_handle_addr_err_st(struct kvm_vcpu *vcpu)
234	{	234	{
235	struct kvm_run *run = vcpu->run;	235	struct kvm_run *run = vcpu->run;
236	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	236	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
237	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;	237	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
238	unsigned long cause = vcpu->arch.host_cp0_cause;	238	unsigned long cause = vcpu->arch.host_cp0_cause;
239	enum emulation_result er = EMULATE_DONE;	239	enum emulation_result er = EMULATE_DONE;
240	int ret = RESUME_GUEST;	240	int ret = RESUME_GUEST;
241		241
242	if (KVM_GUEST_KERNEL_MODE(vcpu)	242	if (KVM_GUEST_KERNEL_MODE(vcpu)
243	&& (KSEGX(badvaddr) == CKSEG0 \|\| KSEGX(badvaddr) == CKSEG1)) {	243	&& (KSEGX(badvaddr) == CKSEG0 \|\| KSEGX(badvaddr) == CKSEG1)) {
244	kvm_debug("Emulate Store to MMIO space\n");	244	kvm_debug("Emulate Store to MMIO space\n");
245	er = kvm_mips_emulate_inst(cause, opc, run, vcpu);	245	er = kvm_mips_emulate_inst(cause, opc, run, vcpu);
246	if (er == EMULATE_FAIL) {	246	if (er == EMULATE_FAIL) {
247	kvm_err("Emulate Store to MMIO space failed\n");	247	kvm_err("Emulate Store to MMIO space failed\n");
248	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	248	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
249	ret = RESUME_HOST;	249	ret = RESUME_HOST;
250	} else {	250	} else {
251	run->exit_reason = KVM_EXIT_MMIO;	251	run->exit_reason = KVM_EXIT_MMIO;
252	ret = RESUME_HOST;	252	ret = RESUME_HOST;
253	}	253	}
254	} else {	254	} else {
255	kvm_err("Address Error (STORE): cause %#lx, PC: %p, BadVaddr: %#lx\n",	255	kvm_err("Address Error (STORE): cause %#lx, PC: %p, BadVaddr: %#lx\n",
256	cause, opc, badvaddr);	256	cause, opc, badvaddr);
257	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	257	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
258	ret = RESUME_HOST;	258	ret = RESUME_HOST;
259	}	259	}
260	return ret;	260	return ret;
261	}	261	}
262		262
263	static int kvm_trap_emul_handle_addr_err_ld(struct kvm_vcpu *vcpu)	263	static int kvm_trap_emul_handle_addr_err_ld(struct kvm_vcpu *vcpu)
264	{	264	{
265	struct kvm_run *run = vcpu->run;	265	struct kvm_run *run = vcpu->run;
266	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	266	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
267	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;	267	unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
268	unsigned long cause = vcpu->arch.host_cp0_cause;	268	unsigned long cause = vcpu->arch.host_cp0_cause;
269	enum emulation_result er = EMULATE_DONE;	269	enum emulation_result er = EMULATE_DONE;
270	int ret = RESUME_GUEST;	270	int ret = RESUME_GUEST;
271		271
272	if (KSEGX(badvaddr) == CKSEG0 \|\| KSEGX(badvaddr) == CKSEG1) {	272	if (KSEGX(badvaddr) == CKSEG0 \|\| KSEGX(badvaddr) == CKSEG1) {
273	kvm_debug("Emulate Load from MMIO space @ %#lx\n", badvaddr);	273	kvm_debug("Emulate Load from MMIO space @ %#lx\n", badvaddr);
274	er = kvm_mips_emulate_inst(cause, opc, run, vcpu);	274	er = kvm_mips_emulate_inst(cause, opc, run, vcpu);
275	if (er == EMULATE_FAIL) {	275	if (er == EMULATE_FAIL) {
276	kvm_err("Emulate Load from MMIO space failed\n");	276	kvm_err("Emulate Load from MMIO space failed\n");
277	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	277	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
278	ret = RESUME_HOST;	278	ret = RESUME_HOST;
279	} else {	279	} else {
280	run->exit_reason = KVM_EXIT_MMIO;	280	run->exit_reason = KVM_EXIT_MMIO;
281	ret = RESUME_HOST;	281	ret = RESUME_HOST;
282	}	282	}
283	} else {	283	} else {
284	kvm_err("Address Error (LOAD): cause %#lx, PC: %p, BadVaddr: %#lx\n",	284	kvm_err("Address Error (LOAD): cause %#lx, PC: %p, BadVaddr: %#lx\n",
285	cause, opc, badvaddr);	285	cause, opc, badvaddr);
286	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	286	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
287	ret = RESUME_HOST;	287	ret = RESUME_HOST;
288	er = EMULATE_FAIL;	288	er = EMULATE_FAIL;
289	}	289	}
290	return ret;	290	return ret;
291	}	291	}
292		292
293	static int kvm_trap_emul_handle_syscall(struct kvm_vcpu *vcpu)	293	static int kvm_trap_emul_handle_syscall(struct kvm_vcpu *vcpu)
294	{	294	{
295	struct kvm_run *run = vcpu->run;	295	struct kvm_run *run = vcpu->run;
296	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	296	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
297	unsigned long cause = vcpu->arch.host_cp0_cause;	297	unsigned long cause = vcpu->arch.host_cp0_cause;
298	enum emulation_result er = EMULATE_DONE;	298	enum emulation_result er = EMULATE_DONE;
299	int ret = RESUME_GUEST;	299	int ret = RESUME_GUEST;
300		300
301	er = kvm_mips_emulate_syscall(cause, opc, run, vcpu);	301	er = kvm_mips_emulate_syscall(cause, opc, run, vcpu);
302	if (er == EMULATE_DONE)	302	if (er == EMULATE_DONE)
303	ret = RESUME_GUEST;	303	ret = RESUME_GUEST;
304	else {	304	else {
305	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	305	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
306	ret = RESUME_HOST;	306	ret = RESUME_HOST;
307	}	307	}
308	return ret;	308	return ret;
309	}	309	}
310		310
311	static int kvm_trap_emul_handle_res_inst(struct kvm_vcpu *vcpu)	311	static int kvm_trap_emul_handle_res_inst(struct kvm_vcpu *vcpu)
312	{	312	{
313	struct kvm_run *run = vcpu->run;	313	struct kvm_run *run = vcpu->run;
314	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	314	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
315	unsigned long cause = vcpu->arch.host_cp0_cause;	315	unsigned long cause = vcpu->arch.host_cp0_cause;
316	enum emulation_result er = EMULATE_DONE;	316	enum emulation_result er = EMULATE_DONE;
317	int ret = RESUME_GUEST;	317	int ret = RESUME_GUEST;
318		318
319	er = kvm_mips_handle_ri(cause, opc, run, vcpu);	319	er = kvm_mips_handle_ri(cause, opc, run, vcpu);
320	if (er == EMULATE_DONE)	320	if (er == EMULATE_DONE)
321	ret = RESUME_GUEST;	321	ret = RESUME_GUEST;
322	else {	322	else {
323	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	323	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
324	ret = RESUME_HOST;	324	ret = RESUME_HOST;
325	}	325	}
326	return ret;	326	return ret;
327	}	327	}
328		328
329	static int kvm_trap_emul_handle_break(struct kvm_vcpu *vcpu)	329	static int kvm_trap_emul_handle_break(struct kvm_vcpu *vcpu)
330	{	330	{
331	struct kvm_run *run = vcpu->run;	331	struct kvm_run *run = vcpu->run;
332	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	332	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
333	unsigned long cause = vcpu->arch.host_cp0_cause;	333	unsigned long cause = vcpu->arch.host_cp0_cause;
334	enum emulation_result er = EMULATE_DONE;	334	enum emulation_result er = EMULATE_DONE;
335	int ret = RESUME_GUEST;	335	int ret = RESUME_GUEST;
336		336
337	er = kvm_mips_emulate_bp_exc(cause, opc, run, vcpu);	337	er = kvm_mips_emulate_bp_exc(cause, opc, run, vcpu);
338	if (er == EMULATE_DONE)	338	if (er == EMULATE_DONE)
339	ret = RESUME_GUEST;	339	ret = RESUME_GUEST;
340	else {	340	else {
341	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	341	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
342	ret = RESUME_HOST;	342	ret = RESUME_HOST;
343	}	343	}
344	return ret;	344	return ret;
345	}	345	}
346		346
347	static int kvm_trap_emul_handle_trap(struct kvm_vcpu *vcpu)	347	static int kvm_trap_emul_handle_trap(struct kvm_vcpu *vcpu)
348	{	348	{
349	struct kvm_run *run = vcpu->run;	349	struct kvm_run *run = vcpu->run;
350	uint32_t __user opc = (uint32_t __user )vcpu->arch.pc;	350	uint32_t __user opc = (uint32_t __user )vcpu->arch.pc;
351	unsigned long cause = vcpu->arch.host_cp0_cause;	351	unsigned long cause = vcpu->arch.host_cp0_cause;
352	enum emulation_result er = EMULATE_DONE;	352	enum emulation_result er = EMULATE_DONE;
353	int ret = RESUME_GUEST;	353	int ret = RESUME_GUEST;
354		354
355	er = kvm_mips_emulate_trap_exc(cause, opc, run, vcpu);	355	er = kvm_mips_emulate_trap_exc(cause, opc, run, vcpu);
356	if (er == EMULATE_DONE) {	356	if (er == EMULATE_DONE) {
357	ret = RESUME_GUEST;	357	ret = RESUME_GUEST;
358	} else {	358	} else {
359	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	359	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
360	ret = RESUME_HOST;	360	ret = RESUME_HOST;
361	}	361	}
362	return ret;	362	return ret;
363	}	363	}
364		364
365	static int kvm_trap_emul_handle_msa_fpe(struct kvm_vcpu *vcpu)	365	static int kvm_trap_emul_handle_msa_fpe(struct kvm_vcpu *vcpu)
366	{	366	{
367	struct kvm_run *run = vcpu->run;	367	struct kvm_run *run = vcpu->run;
368	uint32_t __user opc = (uint32_t __user )vcpu->arch.pc;	368	uint32_t __user opc = (uint32_t __user )vcpu->arch.pc;
369	unsigned long cause = vcpu->arch.host_cp0_cause;	369	unsigned long cause = vcpu->arch.host_cp0_cause;
370	enum emulation_result er = EMULATE_DONE;	370	enum emulation_result er = EMULATE_DONE;
371	int ret = RESUME_GUEST;	371	int ret = RESUME_GUEST;
372		372
373	er = kvm_mips_emulate_msafpe_exc(cause, opc, run, vcpu);	373	er = kvm_mips_emulate_msafpe_exc(cause, opc, run, vcpu);
374	if (er == EMULATE_DONE) {	374	if (er == EMULATE_DONE) {
375	ret = RESUME_GUEST;	375	ret = RESUME_GUEST;
376	} else {	376	} else {
377	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	377	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
378	ret = RESUME_HOST;	378	ret = RESUME_HOST;
379	}	379	}
380	return ret;	380	return ret;
381	}	381	}
382		382
383	static int kvm_trap_emul_handle_fpe(struct kvm_vcpu *vcpu)	383	static int kvm_trap_emul_handle_fpe(struct kvm_vcpu *vcpu)
384	{	384	{
385	struct kvm_run *run = vcpu->run;	385	struct kvm_run *run = vcpu->run;
386	uint32_t __user opc = (uint32_t __user )vcpu->arch.pc;	386	uint32_t __user opc = (uint32_t __user )vcpu->arch.pc;
387	unsigned long cause = vcpu->arch.host_cp0_cause;	387	unsigned long cause = vcpu->arch.host_cp0_cause;
388	enum emulation_result er = EMULATE_DONE;	388	enum emulation_result er = EMULATE_DONE;
389	int ret = RESUME_GUEST;	389	int ret = RESUME_GUEST;
390		390
391	er = kvm_mips_emulate_fpe_exc(cause, opc, run, vcpu);	391	er = kvm_mips_emulate_fpe_exc(cause, opc, run, vcpu);
392	if (er == EMULATE_DONE) {	392	if (er == EMULATE_DONE) {
393	ret = RESUME_GUEST;	393	ret = RESUME_GUEST;
394	} else {	394	} else {
395	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	395	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
396	ret = RESUME_HOST;	396	ret = RESUME_HOST;
397	}	397	}
398	return ret;	398	return ret;
399	}	399	}
400		400
401	/**	401	/**
402	* kvm_trap_emul_handle_msa_disabled() - Guest used MSA while disabled in root.	402	* kvm_trap_emul_handle_msa_disabled() - Guest used MSA while disabled in root.
403	* @vcpu: Virtual CPU context.	403	* @vcpu: Virtual CPU context.
404	*	404	*
405	* Handle when the guest attempts to use MSA when it is disabled.	405	* Handle when the guest attempts to use MSA when it is disabled.
406	*/	406	*/
407	static int kvm_trap_emul_handle_msa_disabled(struct kvm_vcpu *vcpu)	407	static int kvm_trap_emul_handle_msa_disabled(struct kvm_vcpu *vcpu)
408	{	408	{
409	struct mips_coproc *cop0 = vcpu->arch.cop0;	409	struct mips_coproc *cop0 = vcpu->arch.cop0;
410	struct kvm_run *run = vcpu->run;	410	struct kvm_run *run = vcpu->run;
411	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;	411	uint32_t __user opc = (uint32_t __user ) vcpu->arch.pc;
412	unsigned long cause = vcpu->arch.host_cp0_cause;	412	unsigned long cause = vcpu->arch.host_cp0_cause;
413	enum emulation_result er = EMULATE_DONE;	413	enum emulation_result er = EMULATE_DONE;
414	int ret = RESUME_GUEST;	414	int ret = RESUME_GUEST;
415		415
416	if (!kvm_mips_guest_has_msa(&vcpu->arch) \|\|	416	if (!kvm_mips_guest_has_msa(&vcpu->arch) \|\|
417	(kvm_read_c0_guest_status(cop0) & (ST0_CU1 \| ST0_FR)) == ST0_CU1) {	417	(kvm_read_c0_guest_status(cop0) & (ST0_CU1 \| ST0_FR)) == ST0_CU1) {
418	/*	418	/*
419	* No MSA in guest, or FPU enabled and not in FR=1 mode,	419	* No MSA in guest, or FPU enabled and not in FR=1 mode,
420	* guest reserved instruction exception	420	* guest reserved instruction exception
421	*/	421	*/
422	er = kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);	422	er = kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
423	} else if (!(kvm_read_c0_guest_config5(cop0) & MIPS_CONF5_MSAEN)) {	423	} else if (!(kvm_read_c0_guest_config5(cop0) & MIPS_CONF5_MSAEN)) {
424	/* MSA disabled by guest, guest MSA disabled exception */	424	/* MSA disabled by guest, guest MSA disabled exception */
425	er = kvm_mips_emulate_msadis_exc(cause, opc, run, vcpu);	425	er = kvm_mips_emulate_msadis_exc(cause, opc, run, vcpu);
426	} else {	426	} else {
427	/* Restore MSA/FPU state */	427	/* Restore MSA/FPU state */
428	kvm_own_msa(vcpu);	428	kvm_own_msa(vcpu);
429	er = EMULATE_DONE;	429	er = EMULATE_DONE;
430	}	430	}
431		431
432	switch (er) {	432	switch (er) {
433	case EMULATE_DONE:	433	case EMULATE_DONE:
434	ret = RESUME_GUEST;	434	ret = RESUME_GUEST;
435	break;	435	break;
436		436
437	case EMULATE_FAIL:	437	case EMULATE_FAIL:
438	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;	438	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
439	ret = RESUME_HOST;	439	ret = RESUME_HOST;
440	break;	440	break;
441		441
442	default:	442	default:
443	BUG();	443	BUG();
444	}	444	}
445	return ret;	445	return ret;
446	}	446	}
447		447
448	static int kvm_trap_emul_vm_init(struct kvm *kvm)	448	static int kvm_trap_emul_vm_init(struct kvm *kvm)
449	{	449	{
450	return 0;	450	return 0;
451	}	451	}
452		452
453	static int kvm_trap_emul_vcpu_init(struct kvm_vcpu *vcpu)	453	static int kvm_trap_emul_vcpu_init(struct kvm_vcpu *vcpu)
454	{	454	{
455	return 0;	455	return 0;
456	}	456	}
457		457
458	static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)	458	static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
459	{	459	{
460	struct mips_coproc *cop0 = vcpu->arch.cop0;	460	struct mips_coproc *cop0 = vcpu->arch.cop0;
461	uint32_t config1;	461	uint32_t config1;
462	int vcpu_id = vcpu->vcpu_id;	462	int vcpu_id = vcpu->vcpu_id;
463		463
464	/*	464	/*
465	* Arch specific stuff, set up config registers properly so that the	465	* Arch specific stuff, set up config registers properly so that the
466	* guest will come up as expected, for now we simulate a MIPS 24kc	466	* guest will come up as expected, for now we simulate a MIPS 24kc
467	*/	467	*/
468	kvm_write_c0_guest_prid(cop0, 0x00019300);	468	kvm_write_c0_guest_prid(cop0, 0x00019300);
469	/* Have config1, Cacheable, noncoherent, write-back, write allocate */	469	/* Have config1, Cacheable, noncoherent, write-back, write allocate */
470	kvm_write_c0_guest_config(cop0, MIPS_CONF_M \| (0x3 << CP0C0_K0) \|	470	kvm_write_c0_guest_config(cop0, MIPS_CONF_M \| (0x3 << CP0C0_K0) \|
471	(0x1 << CP0C0_AR) \|	471	(0x1 << CP0C0_AR) \|
472	(MMU_TYPE_R4000 << CP0C0_MT));	472	(MMU_TYPE_R4000 << CP0C0_MT));
473		473
474	/* Read the cache characteristics from the host Config1 Register */	474	/* Read the cache characteristics from the host Config1 Register */
475	config1 = (read_c0_config1() & ~0x7f);	475	config1 = (read_c0_config1() & ~0x7f);
476		476
477	/* Set up MMU size */	477	/* Set up MMU size */
478	config1 &= ~(0x3f << 25);	478	config1 &= ~(0x3f << 25);
479	config1 \|= ((KVM_MIPS_GUEST_TLB_SIZE - 1) << 25);	479	config1 \|= ((KVM_MIPS_GUEST_TLB_SIZE - 1) << 25);
480		480
481	/* We unset some bits that we aren't emulating */	481	/* We unset some bits that we aren't emulating */
482	config1 &=	482	config1 &=
483	~((1 << CP0C1_C2) \| (1 << CP0C1_MD) \| (1 << CP0C1_PC) \|	483	~((1 << CP0C1_C2) \| (1 << CP0C1_MD) \| (1 << CP0C1_PC) \|
484	(1 << CP0C1_WR) \| (1 << CP0C1_CA));	484	(1 << CP0C1_WR) \| (1 << CP0C1_CA));
485	kvm_write_c0_guest_config1(cop0, config1);	485	kvm_write_c0_guest_config1(cop0, config1);
486		486
487	/* Have config3, no tertiary/secondary caches implemented */	487	/* Have config3, no tertiary/secondary caches implemented */
488	kvm_write_c0_guest_config2(cop0, MIPS_CONF_M);	488	kvm_write_c0_guest_config2(cop0, MIPS_CONF_M);
489	/* MIPS_CONF_M \| (read_c0_config2() & 0xfff) */	489	/* MIPS_CONF_M \| (read_c0_config2() & 0xfff) */
490		490
491	/* Have config4, UserLocal */	491	/* Have config4, UserLocal */
492	kvm_write_c0_guest_config3(cop0, MIPS_CONF_M \| MIPS_CONF3_ULRI);	492	kvm_write_c0_guest_config3(cop0, MIPS_CONF_M \| MIPS_CONF3_ULRI);
493		493
494	/* Have config5 */	494	/* Have config5 */
495	kvm_write_c0_guest_config4(cop0, MIPS_CONF_M);	495	kvm_write_c0_guest_config4(cop0, MIPS_CONF_M);
496		496
497	/* No config6 */	497	/* No config6 */
498	kvm_write_c0_guest_config5(cop0, 0);	498	kvm_write_c0_guest_config5(cop0, 0);
499		499
500	/* Set Wait IE/IXMT Ignore in Config7, IAR, AR */	500	/* Set Wait IE/IXMT Ignore in Config7, IAR, AR */
501	kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) \| (1 << 10));	501	kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) \| (1 << 10));
502		502
503	/*	503	/*
504	* Setup IntCtl defaults, compatibilty mode for timer interrupts (HW5)	504	* Setup IntCtl defaults, compatibilty mode for timer interrupts (HW5)
505	*/	505	*/
506	kvm_write_c0_guest_intctl(cop0, 0xFC000000);	506	kvm_write_c0_guest_intctl(cop0, 0xFC000000);
507		507
508	/* Put in vcpu id as CPUNum into Ebase Reg to handle SMP Guests */	508	/* Put in vcpu id as CPUNum into Ebase Reg to handle SMP Guests */
509	kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 \| (vcpu_id & 0xFF));	509	kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 \| (vcpu_id & 0xFF));
510		510
511	return 0;	511	return 0;
512	}	512	}
513		513
514	static int kvm_trap_emul_get_one_reg(struct kvm_vcpu *vcpu,	514	static int kvm_trap_emul_get_one_reg(struct kvm_vcpu *vcpu,
515	const struct kvm_one_reg *reg,	515	const struct kvm_one_reg *reg,
516	s64 *v)	516	s64 *v)
517	{	517	{
518	switch (reg->id) {	518	switch (reg->id) {
519	case KVM_REG_MIPS_CP0_COUNT:	519	case KVM_REG_MIPS_CP0_COUNT:
520	*v = kvm_mips_read_count(vcpu);	520	*v = kvm_mips_read_count(vcpu);
521	break;	521	break;
522	case KVM_REG_MIPS_COUNT_CTL:	522	case KVM_REG_MIPS_COUNT_CTL:
523	*v = vcpu->arch.count_ctl;	523	*v = vcpu->arch.count_ctl;
524	break;	524	break;
525	case KVM_REG_MIPS_COUNT_RESUME:	525	case KVM_REG_MIPS_COUNT_RESUME:
526	*v = ktime_to_ns(vcpu->arch.count_resume);	526	*v = ktime_to_ns(vcpu->arch.count_resume);
527	break;	527	break;
528	case KVM_REG_MIPS_COUNT_HZ:	528	case KVM_REG_MIPS_COUNT_HZ:
529	*v = vcpu->arch.count_hz;	529	*v = vcpu->arch.count_hz;
530	break;	530	break;
531	default:	531	default:
532	return -EINVAL;	532	return -EINVAL;
533	}	533	}
534	return 0;	534	return 0;
535	}	535	}
536		536
537	static int kvm_trap_emul_set_one_reg(struct kvm_vcpu *vcpu,	537	static int kvm_trap_emul_set_one_reg(struct kvm_vcpu *vcpu,
538	const struct kvm_one_reg *reg,	538	const struct kvm_one_reg *reg,
539	s64 v)	539	s64 v)
540	{	540	{
541	struct mips_coproc *cop0 = vcpu->arch.cop0;	541	struct mips_coproc *cop0 = vcpu->arch.cop0;
542	int ret = 0;	542	int ret = 0;
543	unsigned int cur, change;	543	unsigned int cur, change;
544		544
545	switch (reg->id) {	545	switch (reg->id) {
546	case KVM_REG_MIPS_CP0_COUNT:	546	case KVM_REG_MIPS_CP0_COUNT:
547	kvm_mips_write_count(vcpu, v);	547	kvm_mips_write_count(vcpu, v);
548	break;	548	break;
549	case KVM_REG_MIPS_CP0_COMPARE:	549	case KVM_REG_MIPS_CP0_COMPARE:
550	kvm_mips_write_compare(vcpu, v);	550	kvm_mips_write_compare(vcpu, v, false);
551	break;	551	break;
552	case KVM_REG_MIPS_CP0_CAUSE:	552	case KVM_REG_MIPS_CP0_CAUSE:
553	/*	553	/*
554	* If the timer is stopped or started (DC bit) it must look	554	* If the timer is stopped or started (DC bit) it must look
555	* atomic with changes to the interrupt pending bits (TI, IRQ5).	555	* atomic with changes to the interrupt pending bits (TI, IRQ5).
556	* A timer interrupt should not happen in between.	556	* A timer interrupt should not happen in between.
557	*/	557	*/
558	if ((kvm_read_c0_guest_cause(cop0) ^ v) & CAUSEF_DC) {	558	if ((kvm_read_c0_guest_cause(cop0) ^ v) & CAUSEF_DC) {
559	if (v & CAUSEF_DC) {	559	if (v & CAUSEF_DC) {
560	/* disable timer first */	560	/* disable timer first */
561	kvm_mips_count_disable_cause(vcpu);	561	kvm_mips_count_disable_cause(vcpu);
562	kvm_change_c0_guest_cause(cop0, ~CAUSEF_DC, v);	562	kvm_change_c0_guest_cause(cop0, ~CAUSEF_DC, v);
563	} else {	563	} else {
564	/* enable timer last */	564	/* enable timer last */
565	kvm_change_c0_guest_cause(cop0, ~CAUSEF_DC, v);	565	kvm_change_c0_guest_cause(cop0, ~CAUSEF_DC, v);
566	kvm_mips_count_enable_cause(vcpu);	566	kvm_mips_count_enable_cause(vcpu);
567	}	567	}
568	} else {	568	} else {
569	kvm_write_c0_guest_cause(cop0, v);	569	kvm_write_c0_guest_cause(cop0, v);
570	}	570	}
571	break;	571	break;
572	case KVM_REG_MIPS_CP0_CONFIG:	572	case KVM_REG_MIPS_CP0_CONFIG:
573	/* read-only for now */	573	/* read-only for now */
574	break;	574	break;
575	case KVM_REG_MIPS_CP0_CONFIG1:	575	case KVM_REG_MIPS_CP0_CONFIG1:
576	cur = kvm_read_c0_guest_config1(cop0);	576	cur = kvm_read_c0_guest_config1(cop0);
577	change = (cur ^ v) & kvm_mips_config1_wrmask(vcpu);	577	change = (cur ^ v) & kvm_mips_config1_wrmask(vcpu);
578	if (change) {	578	if (change) {
579	v = cur ^ change;	579	v = cur ^ change;
580	kvm_write_c0_guest_config1(cop0, v);	580	kvm_write_c0_guest_config1(cop0, v);
581	}	581	}
582	break;	582	break;
583	case KVM_REG_MIPS_CP0_CONFIG2:	583	case KVM_REG_MIPS_CP0_CONFIG2:
584	/* read-only for now */	584	/* read-only for now */
585	break;	585	break;
586	case KVM_REG_MIPS_CP0_CONFIG3:	586	case KVM_REG_MIPS_CP0_CONFIG3:
587	cur = kvm_read_c0_guest_config3(cop0);	587	cur = kvm_read_c0_guest_config3(cop0);
588	change = (cur ^ v) & kvm_mips_config3_wrmask(vcpu);	588	change = (cur ^ v) & kvm_mips_config3_wrmask(vcpu);
589	if (change) {	589	if (change) {
590	v = cur ^ change;	590	v = cur ^ change;
591	kvm_write_c0_guest_config3(cop0, v);	591	kvm_write_c0_guest_config3(cop0, v);
592	}	592	}
593	break;	593	break;
594	case KVM_REG_MIPS_CP0_CONFIG4:	594	case KVM_REG_MIPS_CP0_CONFIG4:
595	cur = kvm_read_c0_guest_config4(cop0);	595	cur = kvm_read_c0_guest_config4(cop0);
596	change = (cur ^ v) & kvm_mips_config4_wrmask(vcpu);	596	change = (cur ^ v) & kvm_mips_config4_wrmask(vcpu);
597	if (change) {	597	if (change) {
598	v = cur ^ change;	598	v = cur ^ change;
599	kvm_write_c0_guest_config4(cop0, v);	599	kvm_write_c0_guest_config4(cop0, v);
600	}	600	}
601	break;	601	break;
602	case KVM_REG_MIPS_CP0_CONFIG5:	602	case KVM_REG_MIPS_CP0_CONFIG5:
603	cur = kvm_read_c0_guest_config5(cop0);	603	cur = kvm_read_c0_guest_config5(cop0);
604	change = (cur ^ v) & kvm_mips_config5_wrmask(vcpu);	604	change = (cur ^ v) & kvm_mips_config5_wrmask(vcpu);
605	if (change) {	605	if (change) {
606	v = cur ^ change;	606	v = cur ^ change;
607	kvm_write_c0_guest_config5(cop0, v);	607	kvm_write_c0_guest_config5(cop0, v);
608	}	608	}
609	break;	609	break;
610	case KVM_REG_MIPS_COUNT_CTL:	610	case KVM_REG_MIPS_COUNT_CTL:
611	ret = kvm_mips_set_count_ctl(vcpu, v);	611	ret = kvm_mips_set_count_ctl(vcpu, v);
612	break;	612	break;
613	case KVM_REG_MIPS_COUNT_RESUME:	613	case KVM_REG_MIPS_COUNT_RESUME:
614	ret = kvm_mips_set_count_resume(vcpu, v);	614	ret = kvm_mips_set_count_resume(vcpu, v);
615	break;	615	break;
616	case KVM_REG_MIPS_COUNT_HZ:	616	case KVM_REG_MIPS_COUNT_HZ:
617	ret = kvm_mips_set_count_hz(vcpu, v);	617	ret = kvm_mips_set_count_hz(vcpu, v);
618	break;	618	break;
619	default:	619	default:
620	return -EINVAL;	620	return -EINVAL;
621	}	621	}
622	return ret;	622	return ret;
623	}	623	}
624		624
625	static int kvm_trap_emul_vcpu_get_regs(struct kvm_vcpu *vcpu)	625	static int kvm_trap_emul_vcpu_get_regs(struct kvm_vcpu *vcpu)
626	{	626	{
627	kvm_lose_fpu(vcpu);	627	kvm_lose_fpu(vcpu);
628		628
629	return 0;	629	return 0;
630	}	630	}
631		631
632	static int kvm_trap_emul_vcpu_set_regs(struct kvm_vcpu *vcpu)	632	static int kvm_trap_emul_vcpu_set_regs(struct kvm_vcpu *vcpu)
633	{	633	{
634	return 0;	634	return 0;
635	}	635	}
636		636
637	static struct kvm_mips_callbacks kvm_trap_emul_callbacks = {	637	static struct kvm_mips_callbacks kvm_trap_emul_callbacks = {
638	/* exit handlers */	638	/* exit handlers */
639	.handle_cop_unusable = kvm_trap_emul_handle_cop_unusable,	639	.handle_cop_unusable = kvm_trap_emul_handle_cop_unusable,
640	.handle_tlb_mod = kvm_trap_emul_handle_tlb_mod,	640	.handle_tlb_mod = kvm_trap_emul_handle_tlb_mod,
641	.handle_tlb_st_miss = kvm_trap_emul_handle_tlb_st_miss,	641	.handle_tlb_st_miss = kvm_trap_emul_handle_tlb_st_miss,
642	.handle_tlb_ld_miss = kvm_trap_emul_handle_tlb_ld_miss,	642	.handle_tlb_ld_miss = kvm_trap_emul_handle_tlb_ld_miss,
643	.handle_addr_err_st = kvm_trap_emul_handle_addr_err_st,	643	.handle_addr_err_st = kvm_trap_emul_handle_addr_err_st,
644	.handle_addr_err_ld = kvm_trap_emul_handle_addr_err_ld,	644	.handle_addr_err_ld = kvm_trap_emul_handle_addr_err_ld,
645	.handle_syscall = kvm_trap_emul_handle_syscall,	645	.handle_syscall = kvm_trap_emul_handle_syscall,
646	.handle_res_inst = kvm_trap_emul_handle_res_inst,	646	.handle_res_inst = kvm_trap_emul_handle_res_inst,
647	.handle_break = kvm_trap_emul_handle_break,	647	.handle_break = kvm_trap_emul_handle_break,
648	.handle_trap = kvm_trap_emul_handle_trap,	648	.handle_trap = kvm_trap_emul_handle_trap,
649	.handle_msa_fpe = kvm_trap_emul_handle_msa_fpe,	649	.handle_msa_fpe = kvm_trap_emul_handle_msa_fpe,
650	.handle_fpe = kvm_trap_emul_handle_fpe,	650	.handle_fpe = kvm_trap_emul_handle_fpe,
651	.handle_msa_disabled = kvm_trap_emul_handle_msa_disabled,	651	.handle_msa_disabled = kvm_trap_emul_handle_msa_disabled,
652		652
653	.vm_init = kvm_trap_emul_vm_init,	653	.vm_init = kvm_trap_emul_vm_init,
654	.vcpu_init = kvm_trap_emul_vcpu_init,	654	.vcpu_init = kvm_trap_emul_vcpu_init,
655	.vcpu_setup = kvm_trap_emul_vcpu_setup,	655	.vcpu_setup = kvm_trap_emul_vcpu_setup,
656	.gva_to_gpa = kvm_trap_emul_gva_to_gpa_cb,	656	.gva_to_gpa = kvm_trap_emul_gva_to_gpa_cb,
657	.queue_timer_int = kvm_mips_queue_timer_int_cb,	657	.queue_timer_int = kvm_mips_queue_timer_int_cb,
658	.dequeue_timer_int = kvm_mips_dequeue_timer_int_cb,	658	.dequeue_timer_int = kvm_mips_dequeue_timer_int_cb,
659	.queue_io_int = kvm_mips_queue_io_int_cb,	659	.queue_io_int = kvm_mips_queue_io_int_cb,
660	.dequeue_io_int = kvm_mips_dequeue_io_int_cb,	660	.dequeue_io_int = kvm_mips_dequeue_io_int_cb,
661	.irq_deliver = kvm_mips_irq_deliver_cb,	661	.irq_deliver = kvm_mips_irq_deliver_cb,
662	.irq_clear = kvm_mips_irq_clear_cb,	662	.irq_clear = kvm_mips_irq_clear_cb,
663	.get_one_reg = kvm_trap_emul_get_one_reg,	663	.get_one_reg = kvm_trap_emul_get_one_reg,
664	.set_one_reg = kvm_trap_emul_set_one_reg,	664	.set_one_reg = kvm_trap_emul_set_one_reg,
665	.vcpu_get_regs = kvm_trap_emul_vcpu_get_regs,	665	.vcpu_get_regs = kvm_trap_emul_vcpu_get_regs,
666	.vcpu_set_regs = kvm_trap_emul_vcpu_set_regs,	666	.vcpu_set_regs = kvm_trap_emul_vcpu_set_regs,
667	};	667	};
668		668
669	int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)	669	int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)
670	{	670	{
671	*install_callbacks = &kvm_trap_emul_callbacks;	671	*install_callbacks = &kvm_trap_emul_callbacks;
672	return 0;	672	return 0;
673	}	673	}
674		674