Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit b187f180cc942e50007aa039f8e3a620ee5f3171

Authored by Yinghai Lu 2007-07-18 15:49:10 +0800

Committed by Linus Torvalds 2007-07-18 23:38:22 +0800

serial: add early_serial_setup() back to header file

early_serial_setup was removed from serial.h, but forgot to put in
serial_8250.h

Signed-off-by: Yinghai Lu <yinghai.lu@sun.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 24 changed files with 25 additions and 0 deletions Inline Diff

arch/frv/kernel/setup.c
arch/mips/basler/excite/excite_setup.c
arch/mips/gt64120/wrppmc/setup.c
arch/mips/mips-boards/atlas/atlas_setup.c
arch/mips/mips-boards/sead/sead_setup.c
arch/mips/mipssim/sim_setup.c
arch/mips/pmc-sierra/msp71xx/msp_serial.c
arch/mips/pmc-sierra/yosemite/setup.c
arch/ppc/platforms/4xx/bamboo.c
arch/ppc/platforms/4xx/bubinga.c
arch/ppc/platforms/4xx/cpci405.c
arch/ppc/platforms/4xx/ebony.c
arch/ppc/platforms/4xx/luan.c
arch/ppc/platforms/4xx/ocotea.c
arch/ppc/platforms/4xx/taishan.c
arch/ppc/platforms/4xx/yucca.c
arch/ppc/platforms/85xx/sbc8560.c
arch/ppc/platforms/chestnut.c
arch/ppc/platforms/ev64260.c
arch/ppc/platforms/radstone_ppc7d.c
arch/ppc/platforms/spruce.c
drivers/parisc/superio.c
drivers/serial/8250_hp300.c
include/linux/serial_8250.h

arch/frv/kernel/setup.c

Diff comments View file @ b187f18

 /* setup.c: FRV specific setup
  *
  * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
  * - Derived from arch/m68k/kernel/setup.c
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
 #include <linux/utsrelease.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/fs.h>
 #include <linux/mm.h>
 #include <linux/fb.h>
 #include <linux/console.h>
 #include <linux/genhd.h>
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/major.h>
 #include <linux/bootmem.h>
 #include <linux/highmem.h>
 #include <linux/seq_file.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
 #include <asm/setup.h>
 #include <asm/irq.h>
 #include <asm/sections.h>
 #include <asm/pgalloc.h>
 #include <asm/busctl-regs.h>
 #include <asm/serial-regs.h>
 #include <asm/timer-regs.h>
 #include <asm/irc-regs.h>
 #include <asm/spr-regs.h>
 #include <asm/mb-regs.h>
 #include <asm/mb93493-regs.h>
 #include <asm/gdb-stub.h>
 #include <asm/io.h>
 #ifdef CONFIG_BLK_DEV_INITRD
 #include <linux/blk.h>
 #include <asm/pgtable.h>
 #endif
 #include "local.h"
 #ifdef CONFIG_MB93090_MB00
 static void __init mb93090_display(void);
 #endif
 #ifdef CONFIG_MMU
 static void __init setup_linux_memory(void);
 #else
 static void __init setup_uclinux_memory(void);
 #endif
 #ifdef CONFIG_MB93090_MB00
 static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
 static char __initdata mb93090_version[] = UTS_RELEASE;
 int __nongprelbss mb93090_mb00_detected;
 #endif
 const char __frv_unknown_system[] = "unknown";
 const char __frv_mb93091_cb10[] = "mb93091-cb10";
 const char __frv_mb93091_cb11[] = "mb93091-cb11";
 const char __frv_mb93091_cb30[] = "mb93091-cb30";
 const char __frv_mb93091_cb41[] = "mb93091-cb41";
 const char __frv_mb93091_cb60[] = "mb93091-cb60";
 const char __frv_mb93091_cb70[] = "mb93091-cb70";
 const char __frv_mb93091_cb451[] = "mb93091-cb451";
 const char __frv_mb93090_mb00[] = "mb93090-mb00";
 const char __frv_mb93493[] = "mb93493";
 const char __frv_mb93093[] = "mb93093";
 static const char *__nongprelbss cpu_series;
 static const char *__nongprelbss cpu_core;
 static const char *__nongprelbss cpu_silicon;
 static const char *__nongprelbss cpu_mmu;
 static const char *__nongprelbss cpu_system;
 static const char *__nongprelbss cpu_board1;
 static const char *__nongprelbss cpu_board2;
 static unsigned long __nongprelbss cpu_psr_all;
 static unsigned long __nongprelbss cpu_hsr0_all;
 unsigned long __nongprelbss pdm_suspend_mode;
 unsigned long __nongprelbss rom_length;
 unsigned long __nongprelbss memory_start;
 unsigned long __nongprelbss memory_end;
 unsigned long __nongprelbss dma_coherent_mem_start;
 unsigned long __nongprelbss dma_coherent_mem_end;
 unsigned long __initdata __sdram_old_base;
 unsigned long __initdata num_mappedpages;
 struct cpuinfo_frv __nongprelbss boot_cpu_data;
 char __initdata command_line[COMMAND_LINE_SIZE];
 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
 #ifdef CONFIG_PM
 #define __pminit
 #define __pminitdata
 #else
 #define __pminit __init
 #define __pminitdata __initdata
 #endif
 struct clock_cmode {
 	uint8_t	xbus, sdram, corebus, core, dsu;
 };
 #define _frac(N,D) ((N)<<4 | (D))
 #define _x0_16	_frac(1,6)
 #define _x0_25	_frac(1,4)
 #define _x0_33	_frac(1,3)
 #define _x0_375	_frac(3,8)
 #define _x0_5	_frac(1,2)
 #define _x0_66	_frac(2,3)
 #define _x0_75	_frac(3,4)
 #define _x1	_frac(1,1)
 #define _x1_5	_frac(3,2)
 #define _x2	_frac(2,1)
 #define _x3	_frac(3,1)
 #define _x4	_frac(4,1)
 #define _x4_5	_frac(9,2)
 #define _x6	_frac(6,1)
 #define _x8	_frac(8,1)
 #define _x9	_frac(9,1)
 int __nongprelbss clock_p0_current;
 int __nongprelbss clock_cm_current;
 int __nongprelbss clock_cmode_current;
 #ifdef CONFIG_PM
 int __nongprelbss clock_cmodes_permitted;
 unsigned long __nongprelbss clock_bits_settable;
 #endif
 static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
 	[4]	= {	_x1,	_x1,	_x2,	_x2,	_x0_25	},
 	[5]	= { 	_x1,	_x2,	_x4,	_x4,	_x0_5	},
 	[8]	= { 	_x1,	_x1,	_x1,	_x2,	_x0_25	},
 	[9]	= { 	_x1,	_x2,	_x2,	_x4,	_x0_5	},
 	[11]	= { 	_x1,	_x4,	_x4,	_x8,	_x1	},
 	[12]	= { 	_x1,	_x1,	_x2,	_x4,	_x0_5	},
 	[13]	= { 	_x1,	_x2,	_x4,	_x8,	_x1	},
 };
 static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
 	[0]	= {	_x1,	_x1,	_x1,	_x1,	_x0_5	},
 	[1]	= {	_x1,	_x1,	_x1,	_x3,	_x0_25	},
 	[2]	= {	_x1,	_x1,	_x2,	_x6,	_x0_5	},
 	[3]	= {	_x1,	_x2,	_x2,	_x6,	_x0_5	},
 	[4]	= {	_x1,	_x1,	_x2,	_x2,	_x0_16	},
 	[8]	= { 	_x1,	_x1,	_x1,	_x2,	_x0_16	},
 	[9]	= { 	_x1,	_x2,	_x2,	_x4,	_x0_33	},
 	[12]	= { 	_x1,	_x1,	_x2,	_x4,	_x0_33	},
 	[14]	= { 	_x1,	_x3,	_x3,	_x9,	_x0_75	},
 	[15]	= { 	_x1,	_x1_5,	_x1_5,	_x4_5,	_x0_375	},
 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
 };
 static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
 	[0]	= {	_x1,	_x2,	_x2,	_x4,	_x0_33	},
 	[1]	= {	_x1,	_x3,	_x3,	_x6,	_x0_5	},
 	[2]	= {	_x1,	_x2,	_x4,	_x8,	_x0_66	},
 	[3]	= {	_x1,	_x1_5,	_x3,	_x6,	_x0_5	},
 	[4]	= {	_x1,	_x3,	_x3,	_x9,	_x0_75	},
 	[5]	= {	_x1,	_x2,	_x2,	_x6,	_x0_5	},
 	[6]	= {	_x1,	_x1_5,	_x1_5,	_x4_5,	_x0_375	},
 };
 static const struct clock_cmode __pminitdata *clock_cmodes;
 static int __pminitdata clock_doubled;
 static struct uart_port __pminitdata __frv_uart0 = {
 	.uartclk		= 0,
 	.membase		= (char *) UART0_BASE,
 	.irq			= IRQ_CPU_UART0,
 	.regshift		= 3,
 	.iotype			= UPIO_MEM,
 	.flags			= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 };
 static struct uart_port __pminitdata __frv_uart1 = {
 	.uartclk		= 0,
 	.membase		= (char *) UART1_BASE,
 	.irq			= IRQ_CPU_UART1,
 	.regshift		= 3,
 	.iotype			= UPIO_MEM,
 	.flags			= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 };
 #if 0
 static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
 {
 	unsigned long phys, virt, cxn, size;
 #ifdef CONFIG_MMU
 	virt = amlr & 0xffffc000;
 	cxn = amlr & 0x3fff;
 #else
 	virt = ampr & 0xffffc000;
 	cxn = 0;
 #endif
 	phys = ampr & xAMPRx_PPFN;
 	size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
 	printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
 	       i_d, n,
 	       virt, virt + size - 1,
 	       phys,
 	       ampr & xAMPRx_S  ? 'S' : '-',
 	       ampr & xAMPRx_C  ? 'C' : '-',
 	       ampr & DAMPRx_WP ? 'W' : '-',
 	       ampr & xAMPRx_V  ? 'V' : '-',
 	       cxn
 	       );
 }
 #endif
 /*****************************************************************************/
 /*
  * dump the memory map
  */
 static void __init dump_memory_map(void)
 {
 #if 0
 	/* dump the protection map */
 	printk_xampr(__get_IAMPR(0),  __get_IAMLR(0),  'I', 0);
 	printk_xampr(__get_IAMPR(1),  __get_IAMLR(1),  'I', 1);
 	printk_xampr(__get_IAMPR(2),  __get_IAMLR(2),  'I', 2);
 	printk_xampr(__get_IAMPR(3),  __get_IAMLR(3),  'I', 3);
 	printk_xampr(__get_IAMPR(4),  __get_IAMLR(4),  'I', 4);
 	printk_xampr(__get_IAMPR(5),  __get_IAMLR(5),  'I', 5);
 	printk_xampr(__get_IAMPR(6),  __get_IAMLR(6),  'I', 6);
 	printk_xampr(__get_IAMPR(7),  __get_IAMLR(7),  'I', 7);
 	printk_xampr(__get_IAMPR(8),  __get_IAMLR(8),  'I', 8);
 	printk_xampr(__get_IAMPR(9),  __get_IAMLR(9),  'i', 9);
 	printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
 	printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
 	printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
 	printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
 	printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
 	printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
 	printk_xampr(__get_DAMPR(0),  __get_DAMLR(0),  'D', 0);
 	printk_xampr(__get_DAMPR(1),  __get_DAMLR(1),  'D', 1);
 	printk_xampr(__get_DAMPR(2),  __get_DAMLR(2),  'D', 2);
 	printk_xampr(__get_DAMPR(3),  __get_DAMLR(3),  'D', 3);
 	printk_xampr(__get_DAMPR(4),  __get_DAMLR(4),  'D', 4);
 	printk_xampr(__get_DAMPR(5),  __get_DAMLR(5),  'D', 5);
 	printk_xampr(__get_DAMPR(6),  __get_DAMLR(6),  'D', 6);
 	printk_xampr(__get_DAMPR(7),  __get_DAMLR(7),  'D', 7);
 	printk_xampr(__get_DAMPR(8),  __get_DAMLR(8),  'D', 8);
 	printk_xampr(__get_DAMPR(9),  __get_DAMLR(9),  'D', 9);
 	printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
 	printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
 	printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
 	printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
 	printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
 	printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
 #endif
 #if 0
 	/* dump the bus controller registers */
 	printk("LGCR: %08lx\n", __get_LGCR());
 	printk("Master: %08lx-%08lx CR=%08lx\n",
 	       __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
 	       __get_LMAICR());
 	int loop;
 	for (loop = 1; loop <= 7; loop++) {
 		unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
 		printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
 		       loop,
 		       lsbr, lsbr + __get_LSAM(loop),
 		       lcr & 0x80000000 ? 'r' : '-',
 		       lcr & 0x40000000 ? 'w' : '-',
 		       lcr & 0x08000000 ? 'b' : '-',
 		       lcr & 0x04000000 ? 'B' : '-',
 		       lcr & 0x02000000 ? 'C' : '-',
 		       lcr & 0x01000000 ? 'D' : '-',
 		       lcr & 0x00800000 ? 'W' : '-',
 		       lcr & 0x00400000 ? 'R' : '-',
 		       (lcr & 0x00030000) == 0x00000000 ? '4' :
 		       (lcr & 0x00030000) == 0x00010000 ? '2' :
 		       (lcr & 0x00030000) == 0x00020000 ? '1' :
 		       '-'
 		       );
 	}
 #endif
 #if 0
 	printk("\n");
 #endif
 } /* end dump_memory_map() */
 /*****************************************************************************/
 /*
  * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
  */
 #ifdef CONFIG_MB93091_VDK
 static void __init detect_mb93091(void)
 {
 #ifdef CONFIG_MB93090_MB00
 	/* Detect CB70 without motherboard */
 	if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
 		cpu_board1 = __frv_mb93090_mb00;
 		mb93090_mb00_detected = 1;
 	}
 #endif
 #ifdef CONFIG_FUJITSU_MB93493
 	cpu_board2 = __frv_mb93493;
 #endif
 } /* end detect_mb93091() */
 #endif
 /*****************************************************************************/
 /*
  * determine the CPU type and set appropriate parameters
  *
  * Family     Series      CPU Core    Silicon    Imple  Vers
  * ----------------------------------------------------------
  * FR-V --+-> FR400 --+-> FR401 --+-> MB93401     02     00 [1]
  *        |           |           |
  *        |           |           +-> MB93401/A   02     01
  *        |           |           |
  *        |           |           +-> MB93403     02     02
  *        |           |
  *        |           +-> FR405 ----> MB93405     04     00
  *        |
  *        +-> FR450 ----> FR451 ----> MB93451     05     00
  *        |
  *        +-> FR500 ----> FR501 --+-> MB93501     01     01 [2]
  *        |                       |
  *        |                       +-> MB93501/A   01     02
  *        |
  *        +-> FR550 --+-> FR551 ----> MB93555     03     01
  *
  *  [1] The MB93401 is an obsolete CPU replaced by the MB93401A
  *  [2] The MB93501 is an obsolete CPU replaced by the MB93501A
  *
  * Imple is PSR(Processor Status Register)[31:28].
  * Vers is PSR(Processor Status Register)[27:24].
  *
  * A "Silicon" consists of CPU core and some on-chip peripherals.
  */
 static void __init determine_cpu(void)
 {
 	unsigned long hsr0 = __get_HSR(0);
 	unsigned long psr = __get_PSR();
 	/* work out what selectable services the CPU supports */
 	__set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
 	cpu_psr_all = __get_PSR();
 	__set_PSR(psr);
 	__set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
 	cpu_hsr0_all = __get_HSR(0);
 	__set_HSR(0, hsr0);
 	/* derive other service specs from the CPU type */
 	cpu_series		= "unknown";
 	cpu_core		= "unknown";
 	cpu_silicon		= "unknown";
 	cpu_mmu			= "Prot";
 	cpu_system		= __frv_unknown_system;
 	clock_cmodes		= NULL;
 	clock_doubled		= 0;
 #ifdef CONFIG_PM
 	clock_bits_settable	= CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
 #endif
 	switch (PSR_IMPLE(psr)) {
 	case PSR_IMPLE_FR401:
 		cpu_series	= "fr400";
 		cpu_core	= "fr401";
 		pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 		switch (PSR_VERSION(psr)) {
 		case PSR_VERSION_FR401_MB93401:
 			cpu_silicon	= "mb93401";
 			cpu_system	= __frv_mb93091_cb10;
 			clock_cmodes	= clock_cmodes_fr401_fr403;
 			clock_doubled	= 1;
 			break;
 		case PSR_VERSION_FR401_MB93401A:
 			cpu_silicon	= "mb93401/A";
 			cpu_system	= __frv_mb93091_cb11;
 			clock_cmodes	= clock_cmodes_fr401_fr403;
 			break;
 		case PSR_VERSION_FR401_MB93403:
 			cpu_silicon	= "mb93403";
 #ifndef CONFIG_MB93093_PDK
 			cpu_system	= __frv_mb93091_cb30;
 #else
 			cpu_system	= __frv_mb93093;
 #endif
 			clock_cmodes	= clock_cmodes_fr401_fr403;
 			break;
 		default:
 			break;
 		}
 		break;
 	case PSR_IMPLE_FR405:
 		cpu_series	= "fr400";
 		cpu_core	= "fr405";
 		pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 		switch (PSR_VERSION(psr)) {
 		case PSR_VERSION_FR405_MB93405:
 			cpu_silicon	= "mb93405";
 			cpu_system	= __frv_mb93091_cb60;
 			clock_cmodes	= clock_cmodes_fr405;
 #ifdef CONFIG_PM
 			clock_bits_settable |= CLOCK_BIT_CMODE;
 			clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
 #endif
 			/* the FPGA on the CB70 has extra registers
 			 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
 			 *   how we tell the difference between it and a CB60
 			 */
 			if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
 				cpu_system = __frv_mb93091_cb70;
 			break;
 		default:
 			break;
 		}
 		break;
 	case PSR_IMPLE_FR451:
 		cpu_series	= "fr450";
 		cpu_core	= "fr451";
 		pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 #ifdef CONFIG_PM
 		clock_bits_settable |= CLOCK_BIT_CMODE;
 		clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
 #endif
 		switch (PSR_VERSION(psr)) {
 		case PSR_VERSION_FR451_MB93451:
 			cpu_silicon	= "mb93451";
 			cpu_mmu		= "Prot, SAT, xSAT, DAT";
 			cpu_system	= __frv_mb93091_cb451;
 			clock_cmodes	= clock_cmodes_fr405;
 			break;
 		default:
 			break;
 		}
 		break;
 	case PSR_IMPLE_FR501:
 		cpu_series	= "fr500";
 		cpu_core	= "fr501";
 		pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 		switch (PSR_VERSION(psr)) {
 		case PSR_VERSION_FR501_MB93501:  cpu_silicon = "mb93501";   break;
 		case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
 		default:
 			break;
 		}
 		break;
 	case PSR_IMPLE_FR551:
 		cpu_series	= "fr550";
 		cpu_core	= "fr551";
 		pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 		switch (PSR_VERSION(psr)) {
 		case PSR_VERSION_FR551_MB93555:
 			cpu_silicon	= "mb93555";
 			cpu_mmu		= "Prot, SAT";
 			cpu_system	= __frv_mb93091_cb41;
 			clock_cmodes	= clock_cmodes_fr555;
 			clock_doubled	= 1;
 			break;
 		default:
 			break;
 		}
 		break;
 	default:
 		break;
 	}
 	printk("- Series:%s CPU:%s Silicon:%s\n",
 	       cpu_series, cpu_core, cpu_silicon);
 #ifdef CONFIG_MB93091_VDK
 	detect_mb93091();
 #endif
 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
 	cpu_board2 = __frv_mb93493;
 #endif
 } /* end determine_cpu() */
 /*****************************************************************************/
 /*
  * calculate the bus clock speed
  */
 void __pminit determine_clocks(int verbose)
 {
 	const struct clock_cmode *mode, *tmode;
 	unsigned long clkc, psr, quot;
 	clkc = __get_CLKC();
 	psr = __get_PSR();
 	clock_p0_current = !!(clkc & CLKC_P0);
 	clock_cm_current = clkc & CLKC_CM;
 	clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
 	if (verbose)
 		printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
 	/* the CB70 has some alternative ways of setting the clock speed through switches accessed
 	 * through the FPGA.  */
 	if (cpu_system == __frv_mb93091_cb70) {
 		unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
 		if (clkswr & 0x1000)
 			__clkin_clock_speed_HZ = 60000000UL;
 		else
 			__clkin_clock_speed_HZ =
 				((clkswr >> 8) & 0xf) * 10000000 +
 				((clkswr >> 4) & 0xf) * 1000000 +
 				((clkswr     ) & 0xf) * 100000;
 	}
 	/* the FR451 is currently fixed at 24MHz */
 	else if (cpu_system == __frv_mb93091_cb451) {
 		//__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
 		unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
 		if (clkswr & 0x1000)
 			__clkin_clock_speed_HZ = 60000000UL;
 		else
 			__clkin_clock_speed_HZ =
 				((clkswr >> 8) & 0xf) * 10000000 +
 				((clkswr >> 4) & 0xf) * 1000000 +
 				((clkswr     ) & 0xf) * 100000;
 	}
 	/* otherwise determine the clockspeed from VDK or other registers */
 	else {
 		__clkin_clock_speed_HZ = __get_CLKIN();
 	}
 	/* look up the appropriate clock relationships table entry */
 	mode = &undef_clock_cmode;
 	if (clock_cmodes) {
 		tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
 		if (tmode->xbus)
 			mode = tmode;
 	}
 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
 	if (clock_doubled)
 		__clkin_clock_speed_HZ <<= 1;
 	__ext_bus_clock_speed_HZ	= CLOCK(__clkin_clock_speed_HZ, mode->xbus);
 	__sdram_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 	__dsu_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->dsu);
 	switch (clkc & CLKC_CM) {
 	case 0: /* High */
 		__core_bus_clock_speed_HZ	= CLOCK(__clkin_clock_speed_HZ, mode->corebus);
 		__core_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->core);
 		break;
 	case 1: /* Medium */
 		__core_bus_clock_speed_HZ	= CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 		__core_clock_speed_HZ		= CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 		break;
 	case 2: /* Low; not supported */
 	case 3: /* UNDEF */
 		printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
 		panic("Bye");
 	}
 	__res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
 	if (clkc & CLKC_P0)
 		__res_bus_clock_speed_HZ >>= 1;
 	if (verbose) {
 		printk("CLKIN: %lu.%3.3luMHz\n",
 		       __clkin_clock_speed_HZ / 1000000,
 		       (__clkin_clock_speed_HZ / 1000) % 1000);
 		printk("CLKS:"
 		       " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
 		       __ext_bus_clock_speed_HZ / 1000000,
 		       __res_bus_clock_speed_HZ / 1000000,
 		       __sdram_clock_speed_HZ / 1000000,
 		       __core_bus_clock_speed_HZ / 1000000,
 		       __core_clock_speed_HZ / 1000000,
 		       __dsu_clock_speed_HZ / 1000000
 		       );
 	}
 	/* calculate the number of __delay() loop iterations per sec (2 insn loop) */
 	__delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
 	/* set the serial prescaler */
 	__serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
 	quot = 1;
 	while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
 		quot += 1;
 	/* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
 	 * - we have to be careful - dividing too much can mean we can't get 115200 baud
 	 */
 	if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
 		quot <<= 1;
 	__serial_clock_speed_HZ /= quot;
 	__frv_uart0.uartclk = __serial_clock_speed_HZ;
 	__frv_uart1.uartclk = __serial_clock_speed_HZ;
 	if (verbose)
 		printk("      uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
 	while (!(__get_UART0_LSR() & UART_LSR_TEMT))
 		continue;
 	while (!(__get_UART1_LSR() & UART_LSR_TEMT))
 		continue;
 	__set_UCPVR(quot);
 	__set_UCPSR(0);
 } /* end determine_clocks() */
 /*****************************************************************************/
 /*
  * reserve some DMA consistent memory
  */
 #ifdef CONFIG_RESERVE_DMA_COHERENT
 static void __init reserve_dma_coherent(void)
 {
 	unsigned long ampr;
 	/* find the first non-kernel memory tile and steal it */
 #define __steal_AMPR(r)						\
 	if (__get_DAMPR(r) & xAMPRx_V) {			\
 		ampr = __get_DAMPR(r);				\
 		__set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C);	\
 		__set_IAMPR(r, 0);				\
 		goto found;					\
 	}
 	__steal_AMPR(1);
 	__steal_AMPR(2);
 	__steal_AMPR(3);
 	__steal_AMPR(4);
 	__steal_AMPR(5);
 	__steal_AMPR(6);
 	if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
 		__steal_AMPR(7);
 		__steal_AMPR(8);
 		__steal_AMPR(9);
 		__steal_AMPR(10);
 		__steal_AMPR(11);
 		__steal_AMPR(12);
 		__steal_AMPR(13);
 		__steal_AMPR(14);
 	}
 	/* unable to grant any DMA consistent memory */
 	printk("No DMA consistent memory reserved\n");
 	return;
  found:
 	dma_coherent_mem_start = ampr & xAMPRx_PPFN;
 	ampr &= xAMPRx_SS;
 	ampr >>= 4;
 	ampr = 1 << (ampr - 3 + 20);
 	dma_coherent_mem_end = dma_coherent_mem_start + ampr;
 	printk("DMA consistent memory reserved %lx-%lx\n",
 	       dma_coherent_mem_start, dma_coherent_mem_end);
 } /* end reserve_dma_coherent() */
 #endif
 /*****************************************************************************/
 /*
  * calibrate the delay loop
  */
 void __init calibrate_delay(void)
 {
 	loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
 	printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
 	       loops_per_jiffy / (500000 / HZ),
 	       (loops_per_jiffy / (5000 / HZ)) % 100);
 } /* end calibrate_delay() */
 /*****************************************************************************/
 /*
  * look through the command line for some things we need to know immediately
  */
 static void __init parse_cmdline_early(char *cmdline)
 {
 	if (!cmdline)
 		return;
 	while (*cmdline) {
 		if (*cmdline == ' ')
 			cmdline++;
 		/* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
 		 * out from the SDRAM controller mask register
 		 */
 		if (!memcmp(cmdline, "mem=", 4)) {
 			unsigned long long mem_size;
 			mem_size = memparse(cmdline + 4, &cmdline);
 			memory_end = memory_start + mem_size;
 		}
 		while (*cmdline && *cmdline != ' ')
 			cmdline++;
 	}
 } /* end parse_cmdline_early() */
 /*****************************************************************************/
 /*
  *
  */
 void __init setup_arch(char **cmdline_p)
 {
 #ifdef CONFIG_MMU
 	printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
 #else
 	printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
 #endif
 	memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
 	determine_cpu();
 	determine_clocks(1);
 	/* For printk-directly-beats-on-serial-hardware hack */
 	console_set_baud(115200);
 #ifdef CONFIG_GDBSTUB
 	gdbstub_set_baud(115200);
 #endif
 #ifdef CONFIG_RESERVE_DMA_COHERENT
 	reserve_dma_coherent();
 #endif
 	dump_memory_map();
 #ifdef CONFIG_MB93090_MB00
 	if (mb93090_mb00_detected)
 		mb93090_display();
 #endif
 	/* register those serial ports that are available */
 #ifdef CONFIG_FRV_ONCPU_SERIAL
 #ifndef CONFIG_GDBSTUB_UART0
 	__reg(UART0_BASE + UART_IER * 8) = 0;
 	early_serial_setup(&__frv_uart0);
 #endif
 #ifndef CONFIG_GDBSTUB_UART1
 	__reg(UART1_BASE + UART_IER * 8) = 0;
 	early_serial_setup(&__frv_uart1);
 #endif
 #endif
 	/* deal with the command line - RedBoot may have passed one to the kernel */
 	memcpy(command_line, boot_command_line, sizeof(command_line));
 	*cmdline_p = &command_line[0];
 	parse_cmdline_early(command_line);
 	/* set up the memory description
 	 * - by now the stack is part of the init task */
 	printk("Memory %08lx-%08lx\n", memory_start, memory_end);
 	BUG_ON(memory_start == memory_end);
 	init_mm.start_code = (unsigned long) &_stext;
 	init_mm.end_code = (unsigned long) &_etext;
 	init_mm.end_data = (unsigned long) &_edata;
 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
 	init_mm.brk = (unsigned long) &_end;
 #else
 	init_mm.brk = (unsigned long) 0;
 #endif
 #ifdef DEBUG
 	printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
 	       (int) &_stext, (int) &_etext,
 	       (int) &_sdata, (int) &_edata,
 	       (int) &_sbss, (int) &_ebss);
 #endif
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
         conswitchp = &vga_con;
 #elif defined(CONFIG_DUMMY_CONSOLE)
         conswitchp = &dummy_con;
 #endif
 #endif
 #ifdef CONFIG_MMU
 	setup_linux_memory();
 #else
 	setup_uclinux_memory();
 #endif
 	/* get kmalloc into gear */
 	paging_init();
 	/* init DMA */
 	frv_dma_init();
 #ifdef DEBUG
 	printk("Done setup_arch\n");
 #endif
 	/* start the decrement timer running */
 //	asm volatile("movgs %0,timerd" :: "r"(10000000));
 //	__set_HSR(0, __get_HSR(0) | HSR0_ETMD);
 } /* end setup_arch() */
 #if 0
 /*****************************************************************************/
 /*
  *
  */
 static int __devinit setup_arch_serial(void)
 {
 	/* register those serial ports that are available */
 #ifndef CONFIG_GDBSTUB_UART0
 	early_serial_setup(&__frv_uart0);
 #endif
 #ifndef CONFIG_GDBSTUB_UART1
 	early_serial_setup(&__frv_uart1);
 #endif
 	return 0;
 } /* end setup_arch_serial() */
 late_initcall(setup_arch_serial);
 #endif
 /*****************************************************************************/
 /*
  * set up the memory map for normal MMU linux
  */
 #ifdef CONFIG_MMU
 static void __init setup_linux_memory(void)
 {
 	unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
 	kstart	= (unsigned long) &__kernel_image_start - PAGE_OFFSET;
 	kend	= (unsigned long) &__kernel_image_end - PAGE_OFFSET;
 	kstart = kstart & PAGE_MASK;
 	kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
 	/* give all the memory to the bootmap allocator,  tell it to put the
 	 * boot mem_map immediately following the kernel image
 	 */
 	bootmap_size = init_bootmem_node(NODE_DATA(0),
 					 kend >> PAGE_SHIFT,		/* map addr */
 					 memory_start >> PAGE_SHIFT,	/* start of RAM */
 					 memory_end >> PAGE_SHIFT	/* end of RAM */
 					 );
 	/* pass the memory that the kernel can immediately use over to the bootmem allocator */
 	max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
 	low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
 	high_mem = 0;
 	if (num_physpages > low_top_pfn) {
 #ifdef CONFIG_HIGHMEM
 		high_mem = num_physpages - low_top_pfn;
 #else
 		max_mapnr = num_physpages = low_top_pfn;
 #endif
 	}
 	else {
 		low_top_pfn = num_physpages;
 	}
 	min_low_pfn = memory_start >> PAGE_SHIFT;
 	max_low_pfn = low_top_pfn;
 	max_pfn = memory_end >> PAGE_SHIFT;
 	num_mappedpages = low_top_pfn;
 	printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
 	free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
 #ifdef CONFIG_HIGHMEM
 	if (high_mem)
 		printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
 #endif
 	/* take back the memory occupied by the kernel image and the bootmem alloc map */
 	reserve_bootmem(kstart, kend - kstart + bootmap_size);
 	/* reserve the memory occupied by the initial ramdisk */
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (LOADER_TYPE && INITRD_START) {
 		if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
 			reserve_bootmem(INITRD_START, INITRD_SIZE);
 			initrd_start = INITRD_START + PAGE_OFFSET;
 			initrd_end = initrd_start + INITRD_SIZE;
 		}
 		else {
 			printk(KERN_ERR
 			       "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
 			       "disabling initrd\n",
 			       INITRD_START + INITRD_SIZE,
 			       low_top_pfn << PAGE_SHIFT);
 			initrd_start = 0;
 		}
 	}
 #endif
 } /* end setup_linux_memory() */
 #endif
 /*****************************************************************************/
 /*
  * set up the memory map for uClinux
  */
 #ifndef CONFIG_MMU
 static void __init setup_uclinux_memory(void)
 {
 #ifdef CONFIG_PROTECT_KERNEL
 	unsigned long dampr;
 #endif
 	unsigned long kend;
 	int bootmap_size;
 	kend = (unsigned long) &__kernel_image_end;
 	kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
 	/* give all the memory to the bootmap allocator,  tell it to put the
 	 * boot mem_map immediately following the kernel image
 	 */
 	bootmap_size = init_bootmem_node(NODE_DATA(0),
 					 kend >> PAGE_SHIFT,		/* map addr */
 					 memory_start >> PAGE_SHIFT,	/* start of RAM */
 					 memory_end >> PAGE_SHIFT	/* end of RAM */
 					 );
 	/* free all the usable memory */
 	free_bootmem(memory_start, memory_end - memory_start);
 	high_memory = (void *) (memory_end & PAGE_MASK);
 	max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
 	min_low_pfn = memory_start >> PAGE_SHIFT;
 	max_low_pfn = memory_end >> PAGE_SHIFT;
 	max_pfn = max_low_pfn;
 	/* now take back the bits the core kernel is occupying */
 #ifndef CONFIG_PROTECT_KERNEL
 	reserve_bootmem(kend, bootmap_size);
 	reserve_bootmem((unsigned long) &__kernel_image_start,
 			kend - (unsigned long) &__kernel_image_start);
 #else
 	dampr = __get_DAMPR(0);
 	dampr &= xAMPRx_SS;
 	dampr = (dampr >> 4) + 17;
 	dampr = 1 << dampr;
 	reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr);
 #endif
 	/* reserve some memory to do uncached DMA through if requested */
 #ifdef CONFIG_RESERVE_DMA_COHERENT
 	if (dma_coherent_mem_start)
 		reserve_bootmem(dma_coherent_mem_start,
 				dma_coherent_mem_end - dma_coherent_mem_start);
 #endif
 } /* end setup_uclinux_memory() */
 #endif
 /*****************************************************************************/
 /*
  * get CPU information for use by procfs
  */
 static int show_cpuinfo(struct seq_file *m, void *v)
 {
 	const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
 #ifdef CONFIG_PM
 	const char *sep;
 #endif
 	gr  = cpu_hsr0_all & HSR0_GRHE	? "gr0-63"	: "gr0-31";
 	fr  = cpu_hsr0_all & HSR0_FRHE	? "fr0-63"	: "fr0-31";
 	fm  = cpu_psr_all  & PSR_EM	? ", Media"	: "";
 	fp  = cpu_psr_all  & PSR_EF	? ", FPU"	: "";
 	cm  = cpu_psr_all  & PSR_CM	? ", CCCR"	: "";
 	nem = cpu_psr_all  & PSR_NEM	? ", NE"	: "";
 	ble = cpu_psr_all  & PSR_BE	? "BE"		: "LE";
 	seq_printf(m,
 		   "CPU-Series:\t%s\n"
 		   "CPU-Core:\t%s, %s, %s%s%s\n"
 		   "CPU:\t\t%s\n"
 		   "MMU:\t\t%s\n"
 		   "FP-Media:\t%s%s%s\n"
 		   "System:\t\t%s",
 		   cpu_series,
 		   cpu_core, gr, ble, cm, nem,
 		   cpu_silicon,
 		   cpu_mmu,
 		   fr, fm, fp,
 		   cpu_system);
 	if (cpu_board1)
 		seq_printf(m, ", %s", cpu_board1);
 	if (cpu_board2)
 		seq_printf(m, ", %s", cpu_board2);
 	seq_printf(m, "\n");
 #ifdef CONFIG_PM
 	seq_printf(m, "PM-Controls:");
 	sep = "\t";
 	if (clock_bits_settable & CLOCK_BIT_CMODE) {
 		seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
 		sep = ", ";
 	}
 	if (clock_bits_settable & CLOCK_BIT_CM) {
 		seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
 		sep = ", ";
 	}
 	if (clock_bits_settable & CLOCK_BIT_P0) {
 		seq_printf(m, "%sp0=0x3", sep);
 		sep = ", ";
 	}
 	seq_printf(m, "%ssuspend=0x22\n", sep);
 #endif
 	seq_printf(m,
 		   "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
 		   clock_cmode_current, clock_cm_current, clock_p0_current);
 #define print_clk(TAG, VAR) \
 	seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
 	print_clk("In",    __clkin_clock_speed_HZ);
 	print_clk("Core",  __core_clock_speed_HZ);
 	print_clk("SDRAM", __sdram_clock_speed_HZ);
 	print_clk("CBus",  __core_bus_clock_speed_HZ);
 	print_clk("Res",   __res_bus_clock_speed_HZ);
 	print_clk("Ext",   __ext_bus_clock_speed_HZ);
 	print_clk("DSU",   __dsu_clock_speed_HZ);
 	seq_printf(m,
 		   "BogoMips:\t%lu.%02lu\n",
 		   (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
 	return 0;
 } /* end show_cpuinfo() */
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
 	return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
 }
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 {
 	++*pos;
 	return c_start(m, pos);
 }
 static void c_stop(struct seq_file *m, void *v)
 {
 }
 struct seq_operations cpuinfo_op = {
 	.start	= c_start,
 	.next	= c_next,
 	.stop	= c_stop,
 	.show	= show_cpuinfo,
 };
 void arch_gettod(int *year, int *mon, int *day, int *hour,
 		 int *min, int *sec)
 {
 	*year = *mon = *day = *hour = *min = *sec = 0;
 }
 /*****************************************************************************/
 /*
  *
  */
 #ifdef CONFIG_MB93090_MB00
 static void __init mb93090_sendlcdcmd(uint32_t cmd)
 {
 	unsigned long base = __addr_LCD();
 	int loop;
 	/* request reading of the busy flag */
 	__set_LCD(base, LCD_CMD_READ_BUSY);
 	__set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
 	/* wait for the busy flag to become clear */
 	for (loop = 10000; loop > 0; loop--)
 		if (!(__get_LCD(base) & 0x80))
 			break;
 	/* send the command */
 	__set_LCD(base, cmd);
 	__set_LCD(base, cmd & ~LCD_E);
 } /* end mb93090_sendlcdcmd() */
 /*****************************************************************************/
 /*
  * write to the MB93090 LEDs and LCD
  */
 static void __init mb93090_display(void)
 {
 	const char *p;
 	__set_LEDS(0);
 	/* set up the LCD */
 	mb93090_sendlcdcmd(LCD_CMD_CLEAR);
 	mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
 	mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
 	mb93090_sendlcdcmd(LCD_CMD_HOME);
 	mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
 	for (p = mb93090_banner; *p; p++)
 		mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
 	mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
 	for (p = mb93090_version; *p; p++)
 		mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
 } /* end mb93090_display() */
 #endif // CONFIG_MB93090_MB00

arch/mips/basler/excite/excite_setup.c

Diff comments View file @ b187f18

 /*
  *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
  *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
  *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
  *  Manish Lachwani.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2 of the License, or
  *  (at your option) any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/string.h>
 #include <linux/tty.h>
 #include <linux/serial_core.h>
 #include <linux/serial.h>
+#include <linux/serial_8250.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
 #include <asm/bootinfo.h>
 #include <asm/mipsregs.h>
 #include <asm/pgtable-32.h>
 #include <asm/io.h>
 #include <asm/time.h>
 #include <asm/rm9k-ocd.h>
 #include <excite.h>
 #define TITAN_UART_CLK	25000000
 #if 1
 /* normal serial port assignment */
 #define REGBASE_SER0	0x0208
 #define REGBASE_SER1	0x0238
 #define MASK_SER0	0x1
 #define MASK_SER1	0x2
 #else
 /* serial ports swapped */
 #define REGBASE_SER0	0x0238
 #define REGBASE_SER1	0x0208
 #define MASK_SER0	0x2
 #define MASK_SER1	0x1
 #endif
 unsigned long memsize;
 char modetty[30];
 unsigned int titan_irq = TITAN_IRQ;
 static void __iomem * ctl_regs;
 u32 unit_id;
 volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
 volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
 /* Protect access to shared GPI registers */
 DEFINE_SPINLOCK(titan_lock);
 int titan_irqflags;
 static void excite_timer_init(void)
 {
 	const u32 modebit5 = ocd_readl(0x00e4);
 	unsigned int
 		mult = ((modebit5 >> 11) & 0x1f) + 2,
 		div = ((modebit5 >> 16) & 0x1f) + 2;
 	if (div == 33) div = 1;
 	mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
 }
 void __init plat_timer_setup(struct irqaction *irq)
 {
 	/* The eXcite platform uses the alternate timer interrupt */
 	set_c0_intcontrol(0x80);
 	setup_irq(TIMER_IRQ, irq);
 }
 static int __init excite_init_console(void)
 {
 #if defined(CONFIG_SERIAL_8250)
 	static __initdata char serr[] =
 		KERN_ERR "Serial port #%u setup failed\n";
 	struct uart_port up;
 	/* Take the DUART out of reset */
 	titan_writel(0x00ff1cff, CPRR);
 #if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
 	/* Enable both ports */
 	titan_writel(MASK_SER0 | MASK_SER1, UACFG);
 #else
 	/* Enable port #0 only */
 	titan_writel(MASK_SER0, UACFG);
 #endif	/* defined(CONFIG_KGDB) */
  	/*
 	 * Set up serial port #0. Do not use autodetection; the result is
 	 * not what we want.
  	 */
 	memset(&up, 0, sizeof(up));
 	up.membase	= (char *) titan_addr(REGBASE_SER0);
 	up.irq		= TITAN_IRQ;
 	up.uartclk	= TITAN_UART_CLK;
 	up.regshift	= 0;
 	up.iotype	= UPIO_RM9000;
 	up.type		= PORT_RM9000;
 	up.flags	= UPF_SHARE_IRQ;
 	up.line		= 0;
 	if (early_serial_setup(&up))
 		printk(serr, up.line);
 #if CONFIG_SERIAL_8250_NR_UARTS > 1
 	/* And now for port #1. */
 	up.membase	= (char *) titan_addr(REGBASE_SER1);
 	up.line		= 1;
  	if (early_serial_setup(&up))
 		printk(serr, up.line);
 #endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
 #else
 	/* Leave the DUART in reset */
 	titan_writel(0x00ff3cff, CPRR);
 #endif  /* defined(CONFIG_SERIAL_8250) */
 	return 0;
 }
 static int __init excite_platform_init(void)
 {
 	unsigned int i;
 	unsigned char buf[3];
 	u8 reg;
 	void __iomem * dpr;
 	/* BIU buffer allocations */
 	ocd_writel(8, CPURSLMT);	/* CPU */
 	titan_writel(4, CPGRWL);	/* GPI / Ethernet */
 	/* Map control registers located in FPGA */
 	ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
 	if (!ctl_regs)
 		panic("eXcite: failed to map platform control registers\n");
 	memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
 	unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
 	/* Clear the reboot flag */
 	dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
 	reg = __raw_readb(dpr);
 	__raw_writeb(reg & 0x7f, dpr);
 	iounmap(dpr);
 	/* Interrupt controller setup */
 	for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
 		ocd_writel(0x00000000, i + 0x04);
 		ocd_writel(0xffffffff, i + 0x0c);
 	}
 	ocd_writel(0x2, NMICONFIG);
 	ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
 		   INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
 	ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
 		   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
 		   INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
 	ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
 		   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
 		   INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
 	ocd_writel((0x1 << (PHY_MSGINT % 0x20))
 		   | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
 		   INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
 #if USB_IRQ < 10
 	ocd_writel((0x1 << (USB_MSGINT % 0x20))
 		   | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
 		   INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
 #endif
 	/* Enable the packet FIFO, XDMA and XDMA arbiter */
 	titan_writel(0x00ff18ff, CPRR);
 	/*
 	 * Set up the PADMUX. Power down all ethernet slices,
 	 * they will be powered up and configured at device startup.
 	 */
 	titan_writel(0x00878206, CPTC1R);
 	titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
 	/* Reset and enable the FIFO block */
 	titan_writel(0x00000001, SDRXFCIE);
 	titan_writel(0x00000001, SDTXFCIE);
 	titan_writel(0x00000100, SDRXFCIE);
 	titan_writel(0x00000000, SDTXFCIE);
 	/*
 	 * Initialize the common interrupt shared by all components of
 	 * the GPI/Ethernet subsystem.
 	 */
 	titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
 	titan_writel(TITAN_MSGINT, CPCFG1);
 	/*
 	 * XDMA configuration.
 	 * In order for the XDMA to be sharable among multiple drivers,
 	 * the setup must be done here in the platform. The reason is that
 	 * this setup can only be done while the XDMA is in reset. If this
 	 * were done in a driver, it would interrupt all other drivers
 	 * using the XDMA.
 	 */
 	titan_writel(0x80021dff, GXCFG);	/* XDMA reset */
 	titan_writel(0x00000000, CPXCISRA);
 	titan_writel(0x00000000, CPXCISRB);	/* clear pending interrupts */
 #if defined (CONFIG_HIGHMEM)
 #	error change for HIGHMEM support!
 #else
 	titan_writel(0x00000000, GXDMADRPFX);	/* buffer address prefix */
 #endif
 	titan_writel(0, GXDMA_DESCADR);
 	for (i = 0x5040; i <= 0x5300; i += 0x0040)
 		titan_writel(0x80080000, i);	/* reset channel */
 	titan_writel((0x1 << 29)			/* no sparse tx descr. */
 		     | (0x1 << 28)			/* no sparse rx descr. */
 		     | (0x1 << 23) | (0x1 << 24)	/* descriptor coherency */
 		     | (0x1 << 21) | (0x1 << 22)	/* data coherency */
 		     | (0x1 << 17)
 		     | 0x1dff,
 		     GXCFG);
 #if defined(CONFIG_SMP)
 #	error No SMP support
 #else
 	/* All interrupts go to core #0 only. */
 	titan_writel(0x1f007fff, CPDST0A);
 	titan_writel(0x00000000, CPDST0B);
 	titan_writel(0x0000ff3f, CPDST1A);
 	titan_writel(0x00000000, CPDST1B);
 	titan_writel(0x00ffffff, CPXDSTA);
 	titan_writel(0x00000000, CPXDSTB);
 #endif
 	/* Enable DUART interrupts, disable everything else. */
 	titan_writel(0x04000000, CPGIG0ER);
 	titan_writel(0x000000c0, CPGIG1ER);
 	excite_procfs_init();
 	return 0;
 }
 void __init plat_mem_setup(void)
 {
 	volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
 	/* Announce RAM to system */
 	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
 	/* Set up timer initialization hooks */
 	board_time_init = excite_timer_init;
 	/* Set up the peripheral address map */
 	*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
 	*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
 	*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
 	*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
 	wmb();
 	*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
 	wmb();
 	ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
 	ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
 	ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
 	ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
 	/* Local bus slot #0 */
 	ocd_writel(0x00040510, LDP0);
 	ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
 	ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
 	/* Local bus slot #2 */
 	ocd_writel(0x00000330, LDP2);
 	ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
 	ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
 	/* Local bus slot #3 */
 	ocd_writel(0x00123413, LDP3);
 	ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
 	ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
 }
 console_initcall(excite_init_console);
 arch_initcall(excite_platform_init);
 EXPORT_SYMBOL(titan_lock);
 EXPORT_SYMBOL(titan_irqflags);
 EXPORT_SYMBOL(titan_irq);
 EXPORT_SYMBOL(ocd_base);
 EXPORT_SYMBOL(titan_base);

arch/mips/gt64120/wrppmc/setup.c

Diff comments View file @ b187f18

 /*
  * setup.c: Setup pointers to hardware dependent routines.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
  */
 #include <linux/init.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/pm.h>
 #include <asm/io.h>
 #include <asm/bootinfo.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
 #include <asm/gt64120.h>
 unsigned long gt64120_base = KSEG1ADDR(0x14000000);
 #ifdef WRPPMC_EARLY_DEBUG
 static volatile unsigned char * wrppmc_led = \
 	(volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
 /*
  * PPMC LED control register:
  * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
  * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
  * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
  */
 void wrppmc_led_on(int mask)
 {
 	unsigned char value = *wrppmc_led;
 	value &= (0xF8 | mask);
 	*wrppmc_led = value;
 }
 /* If mask = 0, turn off all LEDs */
 void wrppmc_led_off(int mask)
 {
 	unsigned char value = *wrppmc_led;
 	value |= (0x7 & mask);
 	*wrppmc_led = value;
 }
 /*
  * We assume that bootloader has initialized UART16550 correctly
  */
 void __init wrppmc_early_putc(char ch)
 {
 	static volatile unsigned char *wrppmc_uart = \
 		(volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
 	unsigned char value;
 	/* Wait until Transmit-Holding-Register is empty */
 	while (1) {
 		value = *(wrppmc_uart + 5);
 		if (value & 0x20)
 			break;
 	}
 	*wrppmc_uart = ch;
 }
 void __init wrppmc_early_printk(const char *fmt, ...)
 {
 	static char pbuf[256] = {'\0', };
 	char *ch = pbuf;
 	va_list args;
 	unsigned int i;
 	memset(pbuf, 0, 256);
 	va_start(args, fmt);
 	i = vsprintf(pbuf, fmt, args);
 	va_end(args);
 	/* Print the string */
 	while (*ch != '\0') {
 		wrppmc_early_putc(*ch);
 		/* if print '\n', also print '\r' */
 		if (*ch++ == '\n')
 			wrppmc_early_putc('\r');
 	}
 }
 #endif /* WRPPMC_EARLY_DEBUG */
 void __init prom_free_prom_memory(void)
 {
 }
 #ifdef CONFIG_SERIAL_8250
 static void wrppmc_setup_serial(void)
 {
 	struct uart_port up;
 	memset(&up, 0x00, sizeof(struct uart_port));
 	/*
 	 * A note about mapbase/membase
 	 * -) mapbase is the physical address of the IO port.
 	 * -) membase is an 'ioremapped' cookie.
 	 */
 	up.line = 0;
 	up.type = PORT_16550;
 	up.iotype = UPIO_MEM;
 	up.mapbase = WRPPMC_UART16550_BASE;
 	up.membase = ioremap(up.mapbase, 8);
 	up.irq = WRPPMC_UART16550_IRQ;
 	up.uartclk = WRPPMC_UART16550_CLOCK;
 	up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
 	up.regshift = 0;
 	early_serial_setup(&up);
 }
 #endif
 void __init plat_mem_setup(void)
 {
 	extern void wrppmc_time_init(void);
 	extern void wrppmc_machine_restart(char *command);
 	extern void wrppmc_machine_halt(void);
 	extern void wrppmc_machine_power_off(void);
 	_machine_restart = wrppmc_machine_restart;
 	_machine_halt	 = wrppmc_machine_halt;
 	pm_power_off	 = wrppmc_machine_power_off;
 	/* Use MIPS Count/Compare Timer */
 	board_time_init   = wrppmc_time_init;
 	/* This makes the operations of 'in/out[bwl]' to the
 	 * physical address ( < KSEG0) can work via KSEG1
 	 */
 	set_io_port_base(KSEG1);
 #ifdef CONFIG_SERIAL_8250
 	wrppmc_setup_serial();
 #endif
 }
 const char *get_system_type(void)
 {
 	return "Wind River PPMC (GT64120)";
 }
 /*
  * Initializes basic routines and structures pointers, memory size (as
  * given by the bios and saves the command line.
  */
 void __init prom_init(void)
 {
 	mips_machgroup = MACH_GROUP_WINDRIVER;
 	mips_machtype = MACH_WRPPMC;
 	add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
 	add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
 	wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
 			WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
 }

arch/mips/mips-boards/atlas/atlas_setup.c

Diff comments View file @ b187f18

 /*
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
  *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  *
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  */
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
 #include <asm/mips-boards/atlas.h>
 #include <asm/mips-boards/atlasint.h>
 #include <asm/time.h>
 #include <asm/traps.h>
 extern void mips_reboot_setup(void);
 extern void mips_time_init(void);
 extern unsigned long mips_rtc_get_time(void);
 #ifdef CONFIG_KGDB
 extern void kgdb_config(void);
 #endif
 static void __init serial_init(void);
 const char *get_system_type(void)
 {
 	return "MIPS Atlas";
 }
 const char display_string[] = "        LINUX ON ATLAS       ";
 void __init plat_mem_setup(void)
 {
 	mips_pcibios_init();
 	ioport_resource.end = 0x7fffffff;
 	serial_init ();
 #ifdef CONFIG_KGDB
 	kgdb_config();
 #endif
 	mips_reboot_setup();
 	board_time_init = mips_time_init;
 	rtc_mips_get_time = mips_rtc_get_time;
 }
 static void __init serial_init(void)
 {
 #ifdef CONFIG_SERIAL_8250
 	struct uart_port s;
 	memset(&s, 0, sizeof(s));
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 	s.iobase = ATLAS_UART_REGS_BASE;
 #else
 	s.iobase = ATLAS_UART_REGS_BASE+3;
 #endif
 	s.irq = ATLAS_INT_UART;
 	s.uartclk = ATLAS_BASE_BAUD * 16;
 	s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
 	s.iotype = UPIO_PORT;
 	s.regshift = 3;
 	if (early_serial_setup(&s) != 0) {
 		printk(KERN_ERR "Serial setup failed!\n");
 	}
 #endif
 }

arch/mips/mips-boards/sead/sead_setup.c

Diff comments View file @ b187f18

 /*
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
  *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  *
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
  * SEAD specific setup.
  */
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
 #include <asm/mips-boards/sead.h>
 #include <asm/mips-boards/seadint.h>
 #include <asm/time.h>
 extern void mips_reboot_setup(void);
 extern void mips_time_init(void);
 static void __init serial_init(void);
 const char *get_system_type(void)
 {
 	return "MIPS SEAD";
 }
 const char display_string[] = "        LINUX ON SEAD       ";
 void __init plat_mem_setup(void)
 {
 	ioport_resource.end = 0x7fffffff;
 	serial_init ();
 	board_time_init = mips_time_init;
 	mips_reboot_setup();
 }
 static void __init serial_init(void)
 {
 #ifdef CONFIG_SERIAL_8250
 	struct uart_port s;
 	memset(&s, 0, sizeof(s));
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 	s.iobase = SEAD_UART0_REGS_BASE;
 #else
 	s.iobase = SEAD_UART0_REGS_BASE+3;
 #endif
 	s.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_UART0;
 	s.uartclk = SEAD_BASE_BAUD * 16;
 	s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
 	s.iotype = UPIO_PORT;
 	s.regshift = 3;
 	if (early_serial_setup(&s) != 0) {
 		printk(KERN_ERR "Serial setup failed!\n");
 	}
 #endif
 }

arch/mips/mipssim/sim_setup.c

Diff comments View file @ b187f18

 /*
  * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
  *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  *
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
  */
 #include <linux/init.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/ioport.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
 #include <asm/time.h>
 #include <asm/mips-boards/sim.h>
 #include <asm/mips-boards/simint.h>
 extern void sim_time_init(void);
 static void __init serial_init(void);
 unsigned int _isbonito = 0;
 extern void __init sanitize_tlb_entries(void);
 const char *get_system_type(void)
 {
 	return "MIPSsim";
 }
 void __init plat_mem_setup(void)
 {
 	set_io_port_base(0xbfd00000);
 	serial_init();
 	board_time_init = sim_time_init;
 	pr_info("Linux started...\n");
 #ifdef CONFIG_MIPS_MT_SMP
 	sanitize_tlb_entries();
 #endif
 }
 void __init prom_init(void)
 {
 	set_io_port_base(0xbfd00000);
 	pr_info("\nLINUX started...\n");
 	prom_init_cmdline();
 	prom_meminit();
 }
 static void __init serial_init(void)
 {
 #ifdef CONFIG_SERIAL_8250
 	struct uart_port s;
 	memset(&s, 0, sizeof(s));
 	s.iobase = 0x3f8;
 	/* hardware int 4 - the serial int, is CPU int 6
 	 but poll for now */
 	s.irq =  0;
 	s.uartclk = 1843200;
 	s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	s.iotype = UPIO_PORT;
 	s.regshift = 0;
 	s.timeout = 4;
 	if (early_serial_setup(&s) != 0) {
 		printk(KERN_ERR "Serial setup failed!\n");
 	}
 #endif
 }

arch/mips/pmc-sierra/msp71xx/msp_serial.c

Diff comments View file @ b187f18

 /*
  * The setup file for serial related hardware on PMC-Sierra MSP processors.
  *
  * Copyright 2005 PMC-Sierra, Inc.
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
  *  option) any later version.
  *
  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/serial_reg.h>
 #include <asm/bootinfo.h>
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/serial.h>
+#include <linux/serial_8250.h>
 #include <msp_prom.h>
 #include <msp_int.h>
 #include <msp_regs.h>
 #ifdef CONFIG_KGDB
 /*
  * kgdb uses serial port 1 so the console can remain on port 0.
  * To use port 0 change the definition to read as follows:
  * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
  */
 #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
 int putDebugChar(char c)
 {
 	volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
 	uint32_t val = (uint32_t)c;
 	local_irq_disable();
 	while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
 	uart[0] = val;
 	while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
 	local_irq_enable();
 	return 1;
 }
 char getDebugChar(void)
 {
 	volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
 	uint32_t val;
 	while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
 	val = uart[0];
 	return (char)val;
 }
 void initDebugPort(unsigned int uartclk, unsigned int baudrate)
 {
 	unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
 	/* Enable FIFOs */
 	writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
 			UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
 		(char *)DEBUG_PORT_BASE + (UART_FCR * 4));
 	/* Select brtc divisor */
 	writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
 	/* Store divisor lsb */
 	writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
 	/* Store divisor msb */
 	writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
 	/* Set 8N1 mode */
 	writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
 	/* Disable flow control */
 	writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
 	/* Disable receive interrupt(!) */
 	writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
 }
 #endif
 void __init msp_serial_setup(void)
 {
 	char    *s;
 	char    *endp;
 	struct uart_port up;
 	unsigned int uartclk;
 	memset(&up, 0, sizeof(up));
 	/* Check if clock was specified in environment */
 	s = prom_getenv("uartfreqhz");
 	if(!(s && *s && (uartclk = simple_strtoul(s, &endp, 10)) && *endp == 0))
 		uartclk = MSP_BASE_BAUD;
 	ppfinit("UART clock set to %d\n", uartclk);
 	/* Initialize first serial port */
 	up.mapbase      = MSP_UART0_BASE;
 	up.membase      = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN);
 	up.irq          = MSP_INT_UART0;
 	up.uartclk      = uartclk;
 	up.regshift     = 2;
 	up.iotype       = UPIO_DWAPB; /* UPIO_MEM like */
 	up.flags        = STD_COM_FLAGS;
 	up.type         = PORT_16550A;
 	up.line         = 0;
 	up.private_data		= (void*)UART0_STATUS_REG;
 	if (early_serial_setup(&up))
 		printk(KERN_ERR "Early serial init of port 0 failed\n");
 	/* Initialize the second serial port, if one exists */
 	switch (mips_machtype) {
 		case MACH_MSP4200_EVAL:
 		case MACH_MSP4200_GW:
 		case MACH_MSP4200_FPGA:
 		case MACH_MSP7120_EVAL:
 		case MACH_MSP7120_GW:
 		case MACH_MSP7120_FPGA:
 			/* Enable UART1 on MSP4200 and MSP7120 */
 			*GPIO_CFG2_REG = 0x00002299;
 #ifdef CONFIG_KGDB
 			/* Initialize UART1 for kgdb since PMON doesn't */
 			if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
 				if( mips_machtype == MACH_MSP4200_FPGA
 				 || mips_machtype == MACH_MSP7120_FPGA )
 					initDebugPort(uartclk,19200);
 				else
 					initDebugPort(uartclk,57600);
 			}
 #endif
 			break;
 		default:
 			return; /* No second serial port, good-bye. */
 	}
 	up.mapbase      = MSP_UART1_BASE;
 	up.membase      = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN);
 	up.irq          = MSP_INT_UART1;
 	up.line         = 1;
 	up.private_data		= (void*)UART1_STATUS_REG;
 	if (early_serial_setup(&up))
 		printk(KERN_ERR "Early serial init of port 1 failed\n");
 }

arch/mips/pmc-sierra/yosemite/setup.c

Diff comments View file @ b187f18

 /*
  *  Copyright (C) 2003 PMC-Sierra Inc.
  *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
  *
  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
  *  option) any later version.
  *
  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/bcd.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/mm.h>
 #include <linux/bootmem.h>
 #include <linux/swap.h>
 #include <linux/ioport.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/timex.h>
 #include <linux/termios.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/time.h>
 #include <asm/bootinfo.h>
 #include <asm/page.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/serial.h>
 #include <asm/titan_dep.h>
 #include <asm/m48t37.h>
 #include "setup.h"
 unsigned char titan_ge_mac_addr_base[6] = {
 	// 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
 	0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
 };
 unsigned long cpu_clock;
 unsigned long yosemite_base;
 static struct m48t37_rtc *m48t37_base;
 void __init bus_error_init(void)
 {
 	/* Do nothing */
 }
 unsigned long m48t37y_get_time(void)
 {
 	unsigned int year, month, day, hour, min, sec;
 	unsigned long flags;
 	spin_lock_irqsave(&rtc_lock, flags);
 	/* Stop the update to the time */
 	m48t37_base->control = 0x40;
 	year = BCD2BIN(m48t37_base->year);
 	year += BCD2BIN(m48t37_base->century) * 100;
 	month = BCD2BIN(m48t37_base->month);
 	day = BCD2BIN(m48t37_base->date);
 	hour = BCD2BIN(m48t37_base->hour);
 	min = BCD2BIN(m48t37_base->min);
 	sec = BCD2BIN(m48t37_base->sec);
 	/* Start the update to the time again */
 	m48t37_base->control = 0x00;
 	spin_unlock_irqrestore(&rtc_lock, flags);
 	return mktime(year, month, day, hour, min, sec);
 }
 int m48t37y_set_time(unsigned long sec)
 {
 	struct rtc_time tm;
 	unsigned long flags;
 	/* convert to a more useful format -- note months count from 0 */
 	to_tm(sec, &tm);
 	tm.tm_mon += 1;
 	spin_lock_irqsave(&rtc_lock, flags);
 	/* enable writing */
 	m48t37_base->control = 0x80;
 	/* year */
 	m48t37_base->year = BIN2BCD(tm.tm_year % 100);
 	m48t37_base->century = BIN2BCD(tm.tm_year / 100);
 	/* month */
 	m48t37_base->month = BIN2BCD(tm.tm_mon);
 	/* day */
 	m48t37_base->date = BIN2BCD(tm.tm_mday);
 	/* hour/min/sec */
 	m48t37_base->hour = BIN2BCD(tm.tm_hour);
 	m48t37_base->min = BIN2BCD(tm.tm_min);
 	m48t37_base->sec = BIN2BCD(tm.tm_sec);
 	/* day of week -- not really used, but let's keep it up-to-date */
 	m48t37_base->day = BIN2BCD(tm.tm_wday + 1);
 	/* disable writing */
 	m48t37_base->control = 0x00;
 	spin_unlock_irqrestore(&rtc_lock, flags);
 	return 0;
 }
 void __init plat_timer_setup(struct irqaction *irq)
 {
 	setup_irq(7, irq);
 }
 void yosemite_time_init(void)
 {
 	mips_hpt_frequency = cpu_clock / 2;
 mips_hpt_frequency = 33000000 * 3 * 5;
 }
 /* No other usable initialization hook than this ...  */
 extern void (*late_time_init)(void);
 unsigned long ocd_base;
 EXPORT_SYMBOL(ocd_base);
 /*
  * Common setup before any secondaries are started
  */
 #define TITAN_UART_CLK		3686400
 #define TITAN_SERIAL_BASE_BAUD	(TITAN_UART_CLK / 16)
 #define TITAN_SERIAL_IRQ	4
 #define TITAN_SERIAL_BASE	0xfd000008UL
 static void __init py_map_ocd(void)
 {
 	ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
 	if (!ocd_base)
 		panic("Mapping OCD failed - game over.  Your score is 0.");
 	/* Kludge for PMON bug ... */
 	OCD_WRITE(0x0710, 0x0ffff029);
 }
 static void __init py_uart_setup(void)
 {
 #ifdef CONFIG_SERIAL_8250
 	struct uart_port up;
 	/*
 	 * Register to interrupt zero because we share the interrupt with
 	 * the serial driver which we don't properly support yet.
 	 */
 	memset(&up, 0, sizeof(up));
 	up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
 	up.irq          = TITAN_SERIAL_IRQ;
 	up.uartclk      = TITAN_UART_CLK;
 	up.regshift     = 0;
 	up.iotype       = UPIO_MEM;
 	up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	up.line         = 0;
 	if (early_serial_setup(&up))
 		printk(KERN_ERR "Early serial init of port 0 failed\n");
 #endif /* CONFIG_SERIAL_8250 */
 }
 static void __init py_rtc_setup(void)
 {
 	m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
 	if (!m48t37_base)
 		printk(KERN_ERR "Mapping the RTC failed\n");
 	rtc_mips_get_time = m48t37y_get_time;
 	rtc_mips_set_time = m48t37y_set_time;
 	write_seqlock(&xtime_lock);
 	xtime.tv_sec = m48t37y_get_time();
 	xtime.tv_nsec = 0;
 	set_normalized_timespec(&wall_to_monotonic,
 	                        -xtime.tv_sec, -xtime.tv_nsec);
 	write_sequnlock(&xtime_lock);
 }
 /* Not only time init but that's what the hook it's called through is named */
 static void __init py_late_time_init(void)
 {
 	py_map_ocd();
 	py_uart_setup();
 	py_rtc_setup();
 }
 void __init plat_mem_setup(void)
 {
 	board_time_init = yosemite_time_init;
 	late_time_init = py_late_time_init;
 	/* Add memory regions */
 	add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
 #if 0 /* XXX Crash ...  */
 	OCD_WRITE(RM9000x2_OCD_HTSC,
 	          OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
 	/* Set the BAR. Shifted mode */
 	OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
 	OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
 #endif
 }

arch/ppc/platforms/4xx/bamboo.c

Diff comments View file @ b187f18

 /*
  * Bamboo board specific routines
  *
  * Wade Farnsworth <wfarnsworth@mvista.com>
  * Copyright 2004 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/ethtool.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/ocp.h>
 #include <asm/pci-bridge.h>
 #include <asm/time.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
 #include <syslib/gen550.h>
 #include <syslib/ibm440gx_common.h>
 extern bd_t __res;
 static struct ibm44x_clocks clocks __initdata;
 /*
  * Bamboo external IRQ triggering/polarity settings
  */
 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
 	(IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
 };
 static void __init
 bamboo_calibrate_decr(void)
 {
 	unsigned int freq;
 	if (mfspr(SPRN_CCR1) & CCR1_TCS)
 		freq = BAMBOO_TMRCLK;
 	else
 		freq = clocks.cpu;
 	ibm44x_calibrate_decr(freq);
 }
 static int
 bamboo_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: IBM\n");
 	seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
 	return 0;
 }
 static inline int
 bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 	/*
 	 *	PCI IDSEL/INTPIN->INTLINE
 	 * 	   A   B   C   D
 	 */
 	{
 		{ 28, 28, 28, 28 },	/* IDSEL 1 - PCI Slot 0 */
 		{ 27, 27, 27, 27 },	/* IDSEL 2 - PCI Slot 1 */
 		{ 26, 26, 26, 26 },	/* IDSEL 3 - PCI Slot 2 */
 		{ 25, 25, 25, 25 },	/* IDSEL 4 - PCI Slot 3 */
 	};
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 static void __init bamboo_set_emacdata(void)
 {
 	u8 * base_addr;
 	struct ocp_def *def;
 	struct ocp_func_emac_data *emacdata;
 	u8 val;
 	int mode;
 	u32 excluded = 0;
 	base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
 	val = readb(base_addr);
 	iounmap((void *) base_addr);
 	if (BAMBOO_SEL_MII(val))
 		mode = PHY_MODE_MII;
 	else if (BAMBOO_SEL_RMII(val))
 		mode = PHY_MODE_RMII;
 	else
 		mode = PHY_MODE_SMII;
 	/*
 	 * SW2 on the Bamboo is used for ethernet configuration and is accessed
 	 * via the CONFIG2 register in the FPGA.  If the ANEG pin is set,
 	 * overwrite the supported features with the settings in SW2.
 	 *
 	 * This is used as a workaround for the improperly biased RJ-45 sockets
 	 * on the Rev. 0 Bamboo.  By default only 10baseT is functional.
 	 * Removing inductors L17 and L18 from the board allows 100baseT, but
 	 * disables 10baseT.  The Rev. 1 has no such limitations.
 	 */
 	base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
 	val = readb(base_addr);
 	iounmap((void *) base_addr);
 	if (!BAMBOO_AUTONEGOTIATE(val)) {
 		excluded |= SUPPORTED_Autoneg;
 		if (BAMBOO_FORCE_100Mbps(val)) {
 			excluded |= SUPPORTED_10baseT_Full;
 			excluded |= SUPPORTED_10baseT_Half;
 			if (BAMBOO_FULL_DUPLEX_EN(val))
 				excluded |= SUPPORTED_100baseT_Half;
 			else
 				excluded |= SUPPORTED_100baseT_Full;
 		} else {
 			excluded |= SUPPORTED_100baseT_Full;
 			excluded |= SUPPORTED_100baseT_Half;
 			if (BAMBOO_FULL_DUPLEX_EN(val))
 				excluded |= SUPPORTED_10baseT_Half;
 			else
 				excluded |= SUPPORTED_10baseT_Full;
 		}
 	}
 	/* Set mac_addr, phy mode and unsupported phy features for each EMAC */
 	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 	emacdata = def->additions;
 	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 	emacdata->phy_mode = mode;
 	emacdata->phy_feat_exc = excluded;
 	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 	emacdata = def->additions;
 	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 	emacdata->phy_mode = mode;
 	emacdata->phy_feat_exc = excluded;
 }
 static int
 bamboo_exclude_device(unsigned char bus, unsigned char devfn)
 {
 	return (bus == 0 && devfn == 0);
 }
 #define PCI_READW(offset) \
         (readw((void *)((u32)pci_reg_base+offset)))
 #define PCI_WRITEW(value, offset) \
 	(writew(value, (void *)((u32)pci_reg_base+offset)))
 #define PCI_WRITEL(value, offset) \
 	(writel(value, (void *)((u32)pci_reg_base+offset)))
 static void __init
 bamboo_setup_pci(void)
 {
 	void *pci_reg_base;
 	unsigned long memory_size;
 	memory_size = ppc_md.find_end_of_memory();
 	pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
 	/* Enable PCI I/O, Mem, and Busmaster cycles */
 	PCI_WRITEW(PCI_READW(PCI_COMMAND) |
 		   PCI_COMMAND_MEMORY |
 		   PCI_COMMAND_MASTER, PCI_COMMAND);
 	/* Disable region first */
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
 	/* PLB starting addr: 0x00000000A0000000 */
 	PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
 	/* PCI start addr, 0xA0000000 (PCI Address) */
 	PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
 	/* Enable no pre-fetch, enable region */
 	PCI_WRITEL(((0xffffffff -
 		     (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
 		      BAMBOO_PCIL0_PMM0MA);
 	/* Disable region one */
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 	/* Disable region two */
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
 	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 	/* Now configure the PCI->PLB windows, we only use PTM1
 	 *
 	 * For Inbound flow, set the window size to all available memory
 	 * This is required because if size is smaller,
 	 * then Eth/PCI DD would fail as PCI card not able to access
 	 * the memory allocated by DD.
 	 */
 	PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);	/* disabled region 1 */
 	PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);	/* begin of address map */
 	memory_size = 1 << fls(memory_size - 1);
 	/* Size low + Enabled */
 	PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
 	eieio();
 	iounmap(pci_reg_base);
 }
 static void __init
 bamboo_setup_hose(void)
 {
 	unsigned int bar_response, bar;
 	struct pci_controller *hose;
 	bamboo_setup_pci();
 	hose = pcibios_alloc_controller();
 	if (!hose)
 		return;
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 	hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
 	pci_init_resource(&hose->io_resource,
 			BAMBOO_PCI_LOWER_IO,
 			BAMBOO_PCI_UPPER_IO,
 			IORESOURCE_IO,
 			"PCI host bridge");
 	pci_init_resource(&hose->mem_resources[0],
 			BAMBOO_PCI_LOWER_MEM,
 			BAMBOO_PCI_UPPER_MEM,
 			IORESOURCE_MEM,
 			"PCI host bridge");
 	ppc_md.pci_exclude_device = bamboo_exclude_device;
 	hose->io_space.start = BAMBOO_PCI_LOWER_IO;
 	hose->io_space.end = BAMBOO_PCI_UPPER_IO;
 	hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
 	hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
 	isa_io_base =
 		(unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
 	hose->io_base_virt = (void *)isa_io_base;
 	setup_indirect_pci(hose,
 			BAMBOO_PCI_CFGA_PLB32,
 			BAMBOO_PCI_CFGD_PLB32);
 	hose->set_cfg_type = 1;
 	/* Zero config bars */
 	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 		early_write_config_dword(hose, hose->first_busno,
 					 PCI_FUNC(hose->first_busno), bar,
 					 0x00000000);
 		early_read_config_dword(hose, hose->first_busno,
 					PCI_FUNC(hose->first_busno), bar,
 					&bar_response);
 	}
 	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = bamboo_map_irq;
 }
 TODC_ALLOC();
 static void __init
 bamboo_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup ioremapped serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
 	port.irq = 0;
 	port.uartclk = clocks.uart0;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(0, &port);
 #endif
 	port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
 	port.irq = 1;
 	port.uartclk = clocks.uart1;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(1, &port);
 #endif
 	port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
 	port.irq = 3;
 	port.uartclk = clocks.uart2;
 	port.line = 2;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 2 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(2, &port);
 #endif
 	port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
 	port.irq = 4;
 	port.uartclk = clocks.uart3;
 	port.line = 3;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 3 failed\n");
 	}
 }
 static void __init
 bamboo_setup_arch(void)
 {
 	bamboo_set_emacdata();
 	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 	ocp_sys_info.opb_bus_freq = clocks.opb;
 	/* Setup TODC access */
 	TODC_INIT(TODC_TYPE_DS1743,
 			0,
 			0,
 			ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
 			8);
 	/* init to some ~sane value until calibrate_delay() runs */
         loops_per_jiffy = 50000000/HZ;
 	/* Setup PCI host bridge */
 	bamboo_setup_hose();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	bamboo_early_serial_map();
 	/* Identify the system */
 	printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
 }
 void __init platform_init(unsigned long r3, unsigned long r4,
 		unsigned long r5, unsigned long r6, unsigned long r7)
 {
 	ibm44x_platform_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = bamboo_setup_arch;
 	ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
 	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
 	ppc_md.calibrate_decr = bamboo_calibrate_decr;
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = bamboo_early_serial_map;
 #endif
 }

arch/ppc/platforms/4xx/bubinga.c

Diff comments View file @ b187f18

 /*
  * Support for IBM PPC 405EP evaluation board (Bubinga).
  *
  * Author: SAW (IBM), derived from walnut.c.
  *         Maintained by MontaVista Software <source@mvista.com>
  *
  * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
  * terms of the GNU General Public License version 2. This program is
  * licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/threads.h>
 #include <linux/param.h>
 #include <linux/string.h>
 #include <linux/blkdev.h>
 #include <linux/pci.h>
 #include <linux/rtc.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/system.h>
 #include <asm/pci-bridge.h>
 #include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/page.h>
 #include <asm/time.h>
 #include <asm/io.h>
 #include <asm/todc.h>
 #include <asm/kgdb.h>
 #include <asm/ocp.h>
 #include <asm/ibm_ocp_pci.h>
 #include <platforms/4xx/ibm405ep.h>
 #undef DEBUG
 #ifdef DEBUG
 #define DBG(x...) printk(x)
 #else
 #define DBG(x...)
 #endif
 extern bd_t __res;
 void *bubinga_rtc_base;
 /* Some IRQs unique to the board
  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  */
 int __init
 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 	    /*
 	     *      PCI IDSEL/INTPIN->INTLINE
 	     *      A       B       C       D
 	     */
 	{
 		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
 		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
 		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
 		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
 	};
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 };
 /* The serial clock for the chip is an internal clock determined by
  * different clock speeds/dividers.
  * Calculate the proper input baud rate and setup the serial driver.
  */
 static void __init
 bubinga_early_serial_map(void)
 {
 	u32 uart_div;
 	int uart_clock;
 	struct uart_port port;
          /* Calculate the serial clock input frequency
           *
           * The base baud is the PLL OUTA (provided in the board info
           * structure) divided by the external UART Divisor, divided
           * by 16.
           */
 	uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
 	uart_clock = __res.bi_procfreq / uart_div;
 	/* Setup serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = (void*)ACTING_UART0_IO_BASE;
 	port.irq = ACTING_UART0_INT;
 	port.uartclk = uart_clock;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 	port.membase = (void*)ACTING_UART1_IO_BASE;
 	port.irq = ACTING_UART1_INT;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 }
 void __init
 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 {
 #ifdef CONFIG_PCI
 	unsigned int bar_response, bar;
 	/*
 	 * Expected PCI mapping:
 	 *
 	 *  PLB addr             PCI memory addr
 	 *  ---------------------       ---------------------
 	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 	 *
 	 *  PLB addr             PCI io addr
 	 *  ---------------------       ---------------------
 	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 	 *
 	 * The following code is simplified by assuming that the bootrom
 	 * has been well behaved in following this mapping.
 	 */
 #ifdef DEBUG
 	int i;
 	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 	printk("PCI bridge regs before fixup \n");
 	for (i = 0; i <= 3; i++) {
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 	}
 	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 #endif
 	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
 	/* Disable region first */
 	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 	/* PLB starting addr, PCI: 0x80000000 */
 	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 	/* PCI start addr, 0x80000000 */
 	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 	/* 512MB range of PLB to PCI */
 	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 	/* Enable no pre-fetch, enable region */
 	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 						(PPC405_PCI_UPPER_MEM -
 						 PPC405_PCI_MEM_BASE)) | 0x01));
 	/* Disable region one */
 	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 	out_le32((void *) &(pcip->ptm1ms), 0x00000001);
 	/* Disable region two */
 	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 	out_le32((void *) &(pcip->ptm2la), 0x00000000);
 	/* Zero config bars */
 	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 		early_write_config_dword(hose, hose->first_busno,
 					 PCI_FUNC(hose->first_busno), bar,
 					 0x00000000);
 		early_read_config_dword(hose, hose->first_busno,
 					PCI_FUNC(hose->first_busno), bar,
 					&bar_response);
 		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 		    hose->first_busno, PCI_SLOT(hose->first_busno),
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
 	/* end workaround */
 #ifdef DEBUG
 	printk("PCI bridge regs after fixup \n");
 	for (i = 0; i <= 3; i++) {
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 	}
 	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 #endif
 #endif
 }
 void __init
 bubinga_setup_arch(void)
 {
 	ppc4xx_setup_arch();
 	ibm_ocp_set_emac(0, 1);
         bubinga_early_serial_map();
         /* RTC step for the evb405ep */
         bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
         TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
                   bubinga_rtc_base, 8);
         /* Identify the system */
         printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
 }
 void __init
 bubinga_map_io(void)
 {
 	ppc4xx_map_io();
      	io_block_mapping(BUBINGA_RTC_VADDR,
                          BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
 }
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
 {
 	ppc4xx_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = bubinga_setup_arch;
 	ppc_md.setup_io_mappings = bubinga_map_io;
 #ifdef CONFIG_GEN_RTC
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 #endif
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = bubinga_early_serial_map;
 #endif
 }

arch/ppc/platforms/4xx/cpci405.c

Diff comments View file @ b187f18

 /*
  * Board setup routines for the esd CPCI-405 cPCI Board.
  *
  * Copyright 2001-2006 esd electronic system design - hannover germany
  *
  * Authors: Matthias Fuchs
  *          matthias.fuchs@esd-electronics.com
  *          Stefan Roese
  *          stefan.roese@esd-electronics.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  */
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <asm/system.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 #include <asm/todc.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/ocp.h>
 #include <asm/ibm_ocp_pci.h>
 #include <platforms/4xx/ibm405gp.h>
 #ifdef CONFIG_GEN_RTC
 void *cpci405_nvram;
 #endif
 extern bd_t __res;
 /*
  * Some IRQs unique to CPCI-405.
  */
 int __init
 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 	/*
 	 *      PCI IDSEL/INTPIN->INTLINE
 	 *      A       B       C       D
 	 */
 	{
 		{28,	29,	30,	27},	/* IDSEL 15 - cPCI slot 8 */
 		{29,	30,	27,	28},	/* IDSEL 16 - cPCI slot 7 */
 		{30,	27,	28,	29},	/* IDSEL 17 - cPCI slot 6 */
 		{27,	28,	29,	30},	/* IDSEL 18 - cPCI slot 5 */
 		{28,	29,	30,	27},	/* IDSEL 19 - cPCI slot 4 */
 		{29,	30,	27,	28},	/* IDSEL 20 - cPCI slot 3 */
 		{30,	27,	28,	29},	/* IDSEL 21 - cPCI slot 2 */
         };
 	const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 };
 /* The serial clock for the chip is an internal clock determined by
  * different clock speeds/dividers.
  * Calculate the proper input baud rate and setup the serial driver.
  */
 static void __init
 cpci405_early_serial_map(void)
 {
 	u32 uart_div;
 	int uart_clock;
 	struct uart_port port;
          /* Calculate the serial clock input frequency
           *
           * The uart clock is the cpu frequency (provided in the board info
           * structure) divided by the external UART Divisor.
           */
 	uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
 	uart_clock = __res.bi_procfreq / uart_div;
 	/* Setup serial port access */
 	memset(&port, 0, sizeof(port));
 #if defined(CONFIG_UART0_TTYS0)
 	port.membase = (void*)UART0_IO_BASE;
 	port.irq = UART0_INT;
 #else
 	port.membase = (void*)UART1_IO_BASE;
 	port.irq = UART1_INT;
 #endif
 	port.uartclk = uart_clock;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 #if defined(CONFIG_UART0_TTYS0)
 	port.membase = (void*)UART1_IO_BASE;
 	port.irq = UART1_INT;
 #else
 	port.membase = (void*)UART0_IO_BASE;
 	port.irq = UART0_INT;
 #endif
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 }
 void __init
 cpci405_setup_arch(void)
 {
 	ppc4xx_setup_arch();
 	ibm_ocp_set_emac(0, 0);
         cpci405_early_serial_map();
 #ifdef CONFIG_GEN_RTC
 	TODC_INIT(TODC_TYPE_MK48T35,
 		  cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
 #endif
 }
 void __init
 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 {
 #ifdef CONFIG_PCI
 	unsigned int bar_response, bar;
 	/* Disable region first */
 	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 	/* PLB starting addr, PCI: 0x80000000 */
 	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 	/* PCI start addr, 0x80000000 */
 	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 	/* 512MB range of PLB to PCI */
 	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 	/* Enable no pre-fetch, enable region */
 	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 						(PPC405_PCI_UPPER_MEM -
 						 PPC405_PCI_MEM_BASE)) | 0x01));
 	/* Disable region one */
 	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 	out_le32((void *) &(pcip->ptm1ms), 0x00000001);
 	/* Disable region two */
 	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 	out_le32((void *) &(pcip->ptm2la), 0x00000000);
 	/* Zero config bars */
 	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 		early_write_config_dword(hose, hose->first_busno,
 					 PCI_FUNC(hose->first_busno), bar,
 					 0x00000000);
 		early_read_config_dword(hose, hose->first_busno,
 					PCI_FUNC(hose->first_busno), bar,
 					&bar_response);
 	}
 #endif
 }
 void __init
 cpci405_map_io(void)
 {
 	ppc4xx_map_io();
 #ifdef CONFIG_GEN_RTC
 	cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
 #endif
 }
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
 {
 	ppc4xx_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = cpci405_setup_arch;
 	ppc_md.setup_io_mappings = cpci405_map_io;
 #ifdef CONFIG_GEN_RTC
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 #endif
 }

arch/ppc/platforms/4xx/ebony.c

Diff comments View file @ b187f18

 /*
  * Ebony board specific routines
  *
  * Matt Porter <mporter@kernel.crashing.org>
  * Copyright 2002-2005 MontaVista Software Inc.
  *
  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  * Copyright (c) 2003-2005 Zultys Technologies
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/ocp.h>
 #include <asm/pci-bridge.h>
 #include <asm/time.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
 #include <asm/tlbflush.h>
 #include <syslib/gen550.h>
 #include <syslib/ibm440gp_common.h>
 extern bd_t __res;
 static struct ibm44x_clocks clocks __initdata;
 /*
  * Ebony external IRQ triggering/polarity settings
  */
 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ0: PCI slot 0 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ1: PCI slot 1 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ2: PCI slot 2 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ3: PCI slot 3 */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ4: IRDA */
 	(IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),	/* IRQ5: SMI pushbutton */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ6: PHYs */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ7: AUX */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ8: EXT */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ9: EXT */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ10: EXT */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ11: EXT */
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ12: EXT */
 };
 static void __init
 ebony_calibrate_decr(void)
 {
 	unsigned int freq;
 	/*
 	 * Determine system clock speed
 	 *
 	 * If we are on Rev. B silicon, then use
 	 * default external system clock.  If we are
 	 * on Rev. C silicon then errata forces us to
 	 * use the internal clock.
 	 */
 	if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
 		freq = EBONY_440GP_RB_SYSCLK;
 	else
 		freq = EBONY_440GP_RC_SYSCLK;
 	ibm44x_calibrate_decr(freq);
 }
 static int
 ebony_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: IBM\n");
 	seq_printf(m, "machine\t\t: Ebony\n");
 	return 0;
 }
 static inline int
 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 	/*
 	 *	PCI IDSEL/INTPIN->INTLINE
 	 * 	   A   B   C   D
 	 */
 	{
 		{ 23, 23, 23, 23 },	/* IDSEL 1 - PCI Slot 0 */
 		{ 24, 24, 24, 24 },	/* IDSEL 2 - PCI Slot 1 */
 		{ 25, 25, 25, 25 },	/* IDSEL 3 - PCI Slot 2 */
 		{ 26, 26, 26, 26 },	/* IDSEL 4 - PCI Slot 3 */
 	};
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 #define PCIX_WRITEL(value, offset) \
 	(writel(value, pcix_reg_base + offset))
 /*
  * FIXME: This is only here to "make it work".  This will move
  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
  * configuration library. -Matt
  */
 static void __init
 ebony_setup_pcix(void)
 {
 	void __iomem *pcix_reg_base;
 	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 	/* Disable all windows */
 	PCIX_WRITEL(0, PCIX0_POM0SA);
 	PCIX_WRITEL(0, PCIX0_POM1SA);
 	PCIX_WRITEL(0, PCIX0_POM2SA);
 	PCIX_WRITEL(0, PCIX0_PIM0SA);
 	PCIX_WRITEL(0, PCIX0_PIM1SA);
 	PCIX_WRITEL(0, PCIX0_PIM2SA);
 	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 	eieio();
 }
 static void __init
 ebony_setup_hose(void)
 {
 	struct pci_controller *hose;
 	/* Configure windows on the PCI-X host bridge */
 	ebony_setup_pcix();
 	hose = pcibios_alloc_controller();
 	if (!hose)
 		return;
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 	hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
 	pci_init_resource(&hose->io_resource,
 			EBONY_PCI_LOWER_IO,
 			EBONY_PCI_UPPER_IO,
 			IORESOURCE_IO,
 			"PCI host bridge");
 	pci_init_resource(&hose->mem_resources[0],
 			EBONY_PCI_LOWER_MEM,
 			EBONY_PCI_UPPER_MEM,
 			IORESOURCE_MEM,
 			"PCI host bridge");
 	hose->io_space.start = EBONY_PCI_LOWER_IO;
 	hose->io_space.end = EBONY_PCI_UPPER_IO;
 	hose->mem_space.start = EBONY_PCI_LOWER_MEM;
 	hose->mem_space.end = EBONY_PCI_UPPER_MEM;
 	hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
 	isa_io_base = (unsigned long)hose->io_base_virt;
 	setup_indirect_pci(hose,
 			EBONY_PCI_CFGA_PLB32,
 			EBONY_PCI_CFGD_PLB32);
 	hose->set_cfg_type = 1;
 	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = ebony_map_irq;
 }
 TODC_ALLOC();
 static void __init
 ebony_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup ioremapped serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
 	port.irq = 0;
 	port.uartclk = clocks.uart0;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(0, &port);
 	/* Purge TLB entry added in head_44x.S for early serial access */
 	_tlbie(UART0_IO_BASE);
 #endif
 	port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
 	port.irq = 1;
 	port.uartclk = clocks.uart1;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(1, &port);
 #endif
 }
 static void __init
 ebony_setup_arch(void)
 {
 	struct ocp_def *def;
 	struct ocp_func_emac_data *emacdata;
 	/* Set mac_addr for each EMAC */
 	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 	emacdata = def->additions;
 	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
 	emacdata->phy_mode = PHY_MODE_RMII;
 	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 	emacdata = def->additions;
 	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
 	emacdata->phy_mode = PHY_MODE_RMII;
 	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 	/*
 	 * Determine various clocks.
 	 * To be completely correct we should get SysClk
 	 * from FPGA, because it can be changed by on-board switches
 	 * --ebs
 	 */
 	ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
 	ocp_sys_info.opb_bus_freq = clocks.opb;
 	/* Setup TODC access */
 	TODC_INIT(TODC_TYPE_DS1743,
 			0,
 			0,
 			ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
 			8);
 	/* init to some ~sane value until calibrate_delay() runs */
         loops_per_jiffy = 50000000/HZ;
 	/* Setup PCI host bridge */
 	ebony_setup_hose();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	ebony_early_serial_map();
 	/* Identify the system */
 	printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
 }
 void __init platform_init(unsigned long r3, unsigned long r4,
 		unsigned long r5, unsigned long r6, unsigned long r7)
 {
 	ibm44x_platform_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = ebony_setup_arch;
 	ppc_md.show_cpuinfo = ebony_show_cpuinfo;
 	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
 	ppc_md.calibrate_decr = ebony_calibrate_decr;
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = ebony_early_serial_map;
 #endif
 }

arch/ppc/platforms/4xx/luan.c

Diff comments View file @ b187f18

 /*
  * Luan board specific routines
  *
  * Matt Porter <mporter@kernel.crashing.org>
  *
  * Copyright 2004-2005 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/ocp.h>
 #include <asm/pci-bridge.h>
 #include <asm/time.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
 #include <syslib/ibm44x_common.h>
 #include <syslib/ibm440gx_common.h>
 #include <syslib/ibm440sp_common.h>
 extern bd_t __res;
 static struct ibm44x_clocks clocks __initdata;
 static void __init
 luan_calibrate_decr(void)
 {
 	unsigned int freq;
 	if (mfspr(SPRN_CCR1) & CCR1_TCS)
 		freq = LUAN_TMR_CLK;
 	else
 		freq = clocks.cpu;
 	ibm44x_calibrate_decr(freq);
 }
 static int
 luan_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: IBM\n");
 	seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
 	return 0;
 }
 static inline int
 luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
 	/* PCIX0 in adapter mode, no host interrupt routing */
 	/* PCIX1 */
 	if (hose->index == 0) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 *	  A   B   C   D
 		 */
 		{
 			{ 49, 49, 49, 49 },	/* IDSEL 1 - PCIX1 Slot 0 */
 			{ 49, 49, 49, 49 },	/* IDSEL 2 - PCIX1 Slot 1 */
 			{ 49, 49, 49, 49 },	/* IDSEL 3 - PCIX1 Slot 2 */
 			{ 49, 49, 49, 49 },	/* IDSEL 4 - PCIX1 Slot 3 */
 		};
 		const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	/* PCIX2 */
 	} else if (hose->index == 1) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 *	  A   B   C   D
 		 */
 		{
 			{ 50, 50, 50, 50 },	/* IDSEL 1 - PCIX2 Slot 0 */
 			{ 50, 50, 50, 50 },	/* IDSEL 2 - PCIX2 Slot 1 */
 			{ 50, 50, 50, 50 },	/* IDSEL 3 - PCIX2 Slot 2 */
 			{ 50, 50, 50, 50 },	/* IDSEL 4 - PCIX2 Slot 3 */
 		};
 		const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	}
 	return -1;
 }
 static void __init luan_set_emacdata(void)
 {
 	struct ocp_def *def;
 	struct ocp_func_emac_data *emacdata;
 	/* Set phy_map, phy_mode, and mac_addr for the EMAC */
 	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 	emacdata = def->additions;
 	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
 	emacdata->phy_mode = PHY_MODE_GMII;
 	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 }
 #define PCIX_READW(offset) \
 	(readw((void *)((u32)pcix_reg_base+offset)))
 #define PCIX_WRITEW(value, offset) \
 	(writew(value, (void *)((u32)pcix_reg_base+offset)))
 #define PCIX_WRITEL(value, offset) \
 	(writel(value, (void *)((u32)pcix_reg_base+offset)))
 static void __init
 luan_setup_pcix(void)
 {
 	int i;
 	void *pcix_reg_base;
 	for (i=0;i<3;i++) {
 		pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
 		/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 		PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 		/* Disable all windows */
 		PCIX_WRITEL(0, PCIX0_POM0SA);
 		PCIX_WRITEL(0, PCIX0_POM1SA);
 		PCIX_WRITEL(0, PCIX0_POM2SA);
 		PCIX_WRITEL(0, PCIX0_PIM0SA);
 		PCIX_WRITEL(0, PCIX0_PIM0SAH);
 		PCIX_WRITEL(0, PCIX0_PIM1SA);
 		PCIX_WRITEL(0, PCIX0_PIM2SA);
 		PCIX_WRITEL(0, PCIX0_PIM2SAH);
 		/*
 		 * Setup 512MB PLB->PCI outbound mem window
 		 * (a_n000_0000->0_n000_0000)
 		 * */
 		PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
 		PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
 		PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 		PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
 		PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
 		/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 		PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 		PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 		PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
 		PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 		iounmap(pcix_reg_base);
 	}
 	eieio();
 }
 static void __init
 luan_setup_hose(struct pci_controller *hose,
 		int lower_mem,
 		int upper_mem,
 		int cfga,
 		int cfgd,
 		u64 pcix_io_base)
 {
 	char name[20];
 	sprintf(name, "PCIX%d host bridge", hose->index);
 	hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
 	pci_init_resource(&hose->io_resource,
 			LUAN_PCIX_LOWER_IO,
 			LUAN_PCIX_UPPER_IO,
 			IORESOURCE_IO,
 			name);
 	pci_init_resource(&hose->mem_resources[0],
 			lower_mem,
 			upper_mem,
 			IORESOURCE_MEM,
 			name);
 	hose->io_space.start = LUAN_PCIX_LOWER_IO;
 	hose->io_space.end = LUAN_PCIX_UPPER_IO;
 	hose->mem_space.start = lower_mem;
 	hose->mem_space.end = upper_mem;
 	hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
 	isa_io_base = (unsigned long) hose->io_base_virt;
 	setup_indirect_pci(hose, cfga, cfgd);
 	hose->set_cfg_type = 1;
 }
 static void __init
 luan_setup_hoses(void)
 {
 	struct pci_controller *hose1, *hose2;
 	/* Configure windows on the PCI-X host bridge */
 	luan_setup_pcix();
 	/* Allocate hoses for PCIX1 and PCIX2 */
 	hose1 = pcibios_alloc_controller();
 	hose2 = pcibios_alloc_controller();
 	if (!hose1 || !hose2)
 		return;
 	/* Setup PCIX1 */
 	hose1->first_busno = 0;
 	hose1->last_busno = 0xff;
 	luan_setup_hose(hose1,
 			LUAN_PCIX1_LOWER_MEM,
 			LUAN_PCIX1_UPPER_MEM,
 			PCIX1_CFGA,
 			PCIX1_CFGD,
 			PCIX1_IO_BASE);
 	hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
 	/* Setup PCIX2 */
 	hose2->first_busno = hose1->last_busno + 1;
 	hose2->last_busno = 0xff;
 	luan_setup_hose(hose2,
 			LUAN_PCIX2_LOWER_MEM,
 			LUAN_PCIX2_UPPER_MEM,
 			PCIX2_CFGA,
 			PCIX2_CFGD,
 			PCIX2_IO_BASE);
 	hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = luan_map_irq;
 }
 TODC_ALLOC();
 static void __init
 luan_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup ioremapped serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
 	port.irq = UART0_INT;
 	port.uartclk = clocks.uart0;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 	port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
 	port.irq = UART1_INT;
 	port.uartclk = clocks.uart1;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 	port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
 	port.irq = UART2_INT;
 	port.uartclk = BASE_BAUD;
 	port.line = 2;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 2 failed\n");
 	}
 }
 static void __init
 luan_setup_arch(void)
 {
 	luan_set_emacdata();
 #if !defined(CONFIG_BDI_SWITCH)
 	/*
 	 * The Abatron BDI JTAG debugger does not tolerate others
 	 * mucking with the debug registers.
 	 */
         mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
 #endif
 	/*
 	 * Determine various clocks.
 	 * To be completely correct we should get SysClk
 	 * from FPGA, because it can be changed by on-board switches
 	 * --ebs
 	 */
 	/* 440GX and 440SP clocking is the same -mdp */
 	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 	ocp_sys_info.opb_bus_freq = clocks.opb;
 	/* init to some ~sane value until calibrate_delay() runs */
         loops_per_jiffy = 50000000/HZ;
 	/* Setup PCIXn host bridges */
 	luan_setup_hoses();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	luan_early_serial_map();
 	/* Identify the system */
 	printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
 }
 void __init platform_init(unsigned long r3, unsigned long r4,
 		unsigned long r5, unsigned long r6, unsigned long r7)
 {
 	ibm44x_platform_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = luan_setup_arch;
 	ppc_md.show_cpuinfo = luan_show_cpuinfo;
 	ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
 	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
 	ppc_md.calibrate_decr = luan_calibrate_decr;
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = luan_early_serial_map;
 #endif
 }

arch/ppc/platforms/4xx/ocotea.c

Diff comments View file @ b187f18

 /*
  * Ocotea board specific routines
  *
  * Matt Porter <mporter@kernel.crashing.org>
  *
  * Copyright 2003-2005 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/ocp.h>
 #include <asm/pci-bridge.h>
 #include <asm/time.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
 #include <asm/tlbflush.h>
 #include <syslib/gen550.h>
 #include <syslib/ibm440gx_common.h>
 extern bd_t __res;
 static struct ibm44x_clocks clocks __initdata;
 static void __init
 ocotea_calibrate_decr(void)
 {
 	unsigned int freq;
 	if (mfspr(SPRN_CCR1) & CCR1_TCS)
 		freq = OCOTEA_TMR_CLK;
 	else
 		freq = clocks.cpu;
 	ibm44x_calibrate_decr(freq);
 }
 static int
 ocotea_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: IBM\n");
 	seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
 	ibm440gx_show_cpuinfo(m);
 	return 0;
 }
 static inline int
 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 	/*
 	 *	PCI IDSEL/INTPIN->INTLINE
 	 * 	   A   B   C   D
 	 */
 	{
 		{ 23, 23, 23, 23 },	/* IDSEL 1 - PCI Slot 0 */
 		{ 24, 24, 24, 24 },	/* IDSEL 2 - PCI Slot 1 */
 		{ 25, 25, 25, 25 },	/* IDSEL 3 - PCI Slot 2 */
 		{ 26, 26, 26, 26 },	/* IDSEL 4 - PCI Slot 3 */
 	};
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 static void __init ocotea_set_emacdata(void)
 {
 	struct ocp_def *def;
 	struct ocp_func_emac_data *emacdata;
 	int i;
 	/*
 	 * Note: Current rev. board only operates in Group 4a
 	 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
 	 * for RGMII (though these could run in RTBI just the same).
 	 *
 	 * The FPGA reg 3 information isn't even suitable for
 	 * determining the phy_mode, so if the board becomes
 	 * usable in !4a, it will be necessary to parse an environment
 	 * variable from the firmware or similar to properly configure
 	 * the phy_map/phy_mode.
 	 */
 	/* Set phy_map, phy_mode, and mac_addr for each EMAC */
 	for (i=0; i<4; i++) {
 		def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
 		emacdata = def->additions;
 		if (i < 2) {
 			emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
 			emacdata->phy_mode = PHY_MODE_SMII;
 		}
 		else {
 			emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
 			emacdata->phy_mode = PHY_MODE_RGMII;
 		}
 		if (i == 0)
 			memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 		else if (i == 1)
 			memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 		else if (i == 2)
 			memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
 		else if (i == 3)
 			memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
 	}
 }
 #define PCIX_READW(offset) \
 	(readw(pcix_reg_base+offset))
 #define PCIX_WRITEW(value, offset) \
 	(writew(value, pcix_reg_base+offset))
 #define PCIX_WRITEL(value, offset) \
 	(writel(value, pcix_reg_base+offset))
 /*
  * FIXME: This is only here to "make it work".  This will move
  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
  * configuration library. -Matt
  */
 static void __init
 ocotea_setup_pcix(void)
 {
 	void *pcix_reg_base;
 	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 	/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 	PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 	/* Disable all windows */
 	PCIX_WRITEL(0, PCIX0_POM0SA);
 	PCIX_WRITEL(0, PCIX0_POM1SA);
 	PCIX_WRITEL(0, PCIX0_POM2SA);
 	PCIX_WRITEL(0, PCIX0_PIM0SA);
 	PCIX_WRITEL(0, PCIX0_PIM0SAH);
 	PCIX_WRITEL(0, PCIX0_PIM1SA);
 	PCIX_WRITEL(0, PCIX0_PIM2SA);
 	PCIX_WRITEL(0, PCIX0_PIM2SAH);
 	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 	eieio();
 }
 static void __init
 ocotea_setup_hose(void)
 {
 	struct pci_controller *hose;
 	/* Configure windows on the PCI-X host bridge */
 	ocotea_setup_pcix();
 	hose = pcibios_alloc_controller();
 	if (!hose)
 		return;
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 	hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
 	pci_init_resource(&hose->io_resource,
 			OCOTEA_PCI_LOWER_IO,
 			OCOTEA_PCI_UPPER_IO,
 			IORESOURCE_IO,
 			"PCI host bridge");
 	pci_init_resource(&hose->mem_resources[0],
 			OCOTEA_PCI_LOWER_MEM,
 			OCOTEA_PCI_UPPER_MEM,
 			IORESOURCE_MEM,
 			"PCI host bridge");
 	hose->io_space.start = OCOTEA_PCI_LOWER_IO;
 	hose->io_space.end = OCOTEA_PCI_UPPER_IO;
 	hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
 	hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
 	hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
 	isa_io_base = (unsigned long) hose->io_base_virt;
 	setup_indirect_pci(hose,
 			OCOTEA_PCI_CFGA_PLB32,
 			OCOTEA_PCI_CFGD_PLB32);
 	hose->set_cfg_type = 1;
 	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = ocotea_map_irq;
 }
 TODC_ALLOC();
 static void __init
 ocotea_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup ioremapped serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
 	port.irq = UART0_INT;
 	port.uartclk = clocks.uart0;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(0, &port);
 	/* Purge TLB entry added in head_44x.S for early serial access */
 	_tlbie(UART0_IO_BASE);
 #endif
 	port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
 	port.irq = UART1_INT;
 	port.uartclk = clocks.uart1;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(1, &port);
 #endif
 }
 static void __init
 ocotea_setup_arch(void)
 {
 	ocotea_set_emacdata();
 	ibm440gx_tah_enable();
 	/*
 	 * Determine various clocks.
 	 * To be completely correct we should get SysClk
 	 * from FPGA, because it can be changed by on-board switches
 	 * --ebs
 	 */
 	ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200);
 	ocp_sys_info.opb_bus_freq = clocks.opb;
 	/* Setup TODC access */
 	TODC_INIT(TODC_TYPE_DS1743,
 			0,
 			0,
 			ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
 			8);
 	/* init to some ~sane value until calibrate_delay() runs */
         loops_per_jiffy = 50000000/HZ;
 	/* Setup PCI host bridge */
 	ocotea_setup_hose();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	ocotea_early_serial_map();
 	/* Identify the system */
 	printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
 }
 static void __init ocotea_init(void)
 {
 	ibm440gx_l2c_setup(&clocks);
 }
 void __init platform_init(unsigned long r3, unsigned long r4,
 		unsigned long r5, unsigned long r6, unsigned long r7)
 {
 	ibm440gx_platform_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = ocotea_setup_arch;
 	ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
 	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
 	ppc_md.calibrate_decr = ocotea_calibrate_decr;
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = ocotea_early_serial_map;
 #endif
 	ppc_md.init = ocotea_init;
 }

arch/ppc/platforms/4xx/taishan.c

Diff comments View file @ b187f18

 /*
  * arch/ppc/platforms/4xx/taishan.c
  *
  * AMCC Taishan board specific routines
  *
  * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/ndfc.h>
 #include <linux/mtd/physmap.h>
 #include <asm/machdep.h>
 #include <asm/ocp.h>
 #include <asm/bootinfo.h>
 #include <asm/ppcboot.h>
 #include <syslib/gen550.h>
 #include <syslib/ibm440gx_common.h>
 extern bd_t __res;
 static struct ibm44x_clocks clocks __initdata;
 /*
  * NOR FLASH configuration (using mtd physmap driver)
  */
 /* start will be added dynamically, end is always fixed */
 static struct resource taishan_nor_resource = {
 	.start = TAISHAN_FLASH_ADDR,
 	.end   = 0x1ffffffffULL,
 	.flags = IORESOURCE_MEM,
 };
 #define RW_PART0_OF	0
 #define RW_PART0_SZ	0x180000
 #define RW_PART1_SZ	0x200000
 /* Partition 2 will be autosized dynamically... */
 #define RW_PART3_SZ	0x80000
 #define RW_PART4_SZ	0x40000
 static struct mtd_partition taishan_nor_parts[] = {
 	{
 		.name = "kernel",
 		.offset = 0,
 		.size = RW_PART0_SZ
 	},
 	{
 		.name = "root",
 		.offset = MTDPART_OFS_APPEND,
 		.size = RW_PART1_SZ,
 	},
 	{
 		.name = "user",
 		.offset = MTDPART_OFS_APPEND,
 /*		.size = RW_PART2_SZ */ /* will be adjusted dynamically */
 	},
 	{
 		.name = "env",
 		.offset = MTDPART_OFS_APPEND,
 		.size = RW_PART3_SZ,
 	},
 	{
 		.name = "u-boot",
 		.offset = MTDPART_OFS_APPEND,
 		.size = RW_PART4_SZ,
 	}
 };
 static struct physmap_flash_data taishan_nor_data = {
 	.width		= 4,
 	.parts		= taishan_nor_parts,
 	.nr_parts	= ARRAY_SIZE(taishan_nor_parts),
 };
 static struct platform_device taishan_nor_device = {
 	.name		= "physmap-flash",
 	.id		= 0,
 	.dev = {
 			.platform_data = &taishan_nor_data,
 		},
 	.num_resources	= 1,
 	.resource	= &taishan_nor_resource,
 };
 static int taishan_setup_flash(void)
 {
 	/*
 	 * Adjust partition 2 to flash size
 	 */
 	taishan_nor_parts[2].size = __res.bi_flashsize -
 		RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
 	platform_device_register(&taishan_nor_device);
 	return 0;
 }
 arch_initcall(taishan_setup_flash);
 static void __init
 taishan_calibrate_decr(void)
 {
 	unsigned int freq;
 	if (mfspr(SPRN_CCR1) & CCR1_TCS)
 		freq = TAISHAN_TMR_CLK;
 	else
 		freq = clocks.cpu;
 	ibm44x_calibrate_decr(freq);
 }
 static int
 taishan_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: AMCC\n");
 	seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
 	ibm440gx_show_cpuinfo(m);
 	return 0;
 }
 static inline int
 taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 	/*
 	 *	PCI IDSEL/INTPIN->INTLINE
 	 * 	   A   B   C   D
 	 */
 	{
 		{ 23, 24, 25, 26 },	/* IDSEL 1 - PCI Slot 0 */
 		{ 24, 25, 26, 23 },	/* IDSEL 2 - PCI Slot 1 */
 	};
 	const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 static void __init taishan_set_emacdata(void)
 {
 	struct ocp_def *def;
 	struct ocp_func_emac_data *emacdata;
 	int i;
 	/* Set phy_map, phy_mode, and mac_addr for each EMAC */
 	for (i=2; i<4; i++) {
 		def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
 		emacdata = def->additions;
 		if (i < 2) {
 			emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
 			emacdata->phy_mode = PHY_MODE_SMII;
 		} else {
 			emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 			emacdata->phy_mode = PHY_MODE_RGMII;
 		}
 		if (i == 0)
 			memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
 		else if (i == 1)
 			memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
 		else if (i == 2)
 			memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 		else if (i == 3)
 			memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 	}
 }
 #define PCIX_READW(offset) \
 	(readw(pcix_reg_base+offset))
 #define PCIX_WRITEW(value, offset) \
 	(writew(value, pcix_reg_base+offset))
 #define PCIX_WRITEL(value, offset) \
 	(writel(value, pcix_reg_base+offset))
 /*
  * FIXME: This is only here to "make it work".  This will move
  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
  * configuration library. -Matt
  */
 static void __init
 taishan_setup_pcix(void)
 {
 	void *pcix_reg_base;
 	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 	/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 	PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 	/* Disable all windows */
 	PCIX_WRITEL(0, PCIX0_POM0SA);
 	PCIX_WRITEL(0, PCIX0_POM1SA);
 	PCIX_WRITEL(0, PCIX0_POM2SA);
 	PCIX_WRITEL(0, PCIX0_PIM0SA);
 	PCIX_WRITEL(0, PCIX0_PIM0SAH);
 	PCIX_WRITEL(0, PCIX0_PIM1SA);
 	PCIX_WRITEL(0, PCIX0_PIM2SA);
 	PCIX_WRITEL(0, PCIX0_PIM2SAH);
 	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 	PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 	iounmap(pcix_reg_base);
 	eieio();
 }
 static void __init
 taishan_setup_hose(void)
 {
 	struct pci_controller *hose;
 	/* Configure windows on the PCI-X host bridge */
 	taishan_setup_pcix();
 	hose = pcibios_alloc_controller();
 	if (!hose)
 		return;
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 	hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
 	pci_init_resource(&hose->io_resource,
 			TAISHAN_PCI_LOWER_IO,
 			TAISHAN_PCI_UPPER_IO,
 			IORESOURCE_IO,
 			"PCI host bridge");
 	pci_init_resource(&hose->mem_resources[0],
 			TAISHAN_PCI_LOWER_MEM,
 			TAISHAN_PCI_UPPER_MEM,
 			IORESOURCE_MEM,
 			"PCI host bridge");
 	hose->io_space.start = TAISHAN_PCI_LOWER_IO;
 	hose->io_space.end = TAISHAN_PCI_UPPER_IO;
 	hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
 	hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
 	hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
 	isa_io_base = (unsigned long) hose->io_base_virt;
 	setup_indirect_pci(hose,
 			TAISHAN_PCI_CFGA_PLB32,
 			TAISHAN_PCI_CFGD_PLB32);
 	hose->set_cfg_type = 1;
 	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = taishan_map_irq;
 }
 static void __init
 taishan_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup ioremapped serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
 	port.irq = UART0_INT;
 	port.uartclk = clocks.uart0;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0)
 		printk("Early serial init of port 0 failed\n");
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(0, &port);
 	/* Purge TLB entry added in head_44x.S for early serial access */
 	_tlbie(UART0_IO_BASE);
 #endif
 	port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
 	port.irq = UART1_INT;
 	port.uartclk = clocks.uart1;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0)
 		printk("Early serial init of port 1 failed\n");
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(1, &port);
 #endif
 }
 static void __init
 taishan_setup_arch(void)
 {
 	taishan_set_emacdata();
 	ibm440gx_tah_enable();
 	/*
 	 * Determine various clocks.
 	 * To be completely correct we should get SysClk
 	 * from FPGA, because it can be changed by on-board switches
 	 * --ebs
 	 */
 	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 	ocp_sys_info.opb_bus_freq = clocks.opb;
 	/* init to some ~sane value until calibrate_delay() runs */
         loops_per_jiffy = 50000000/HZ;
 	/* Setup PCI host bridge */
 	taishan_setup_hose();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	taishan_early_serial_map();
 	/* Identify the system */
 	printk("AMCC PowerPC 440GX Taishan Platform\n");
 }
 static void __init taishan_init(void)
 {
 	ibm440gx_l2c_setup(&clocks);
 }
 void __init platform_init(unsigned long r3, unsigned long r4,
 		unsigned long r5, unsigned long r6, unsigned long r7)
 {
 	ibm44x_platform_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = taishan_setup_arch;
 	ppc_md.show_cpuinfo = taishan_show_cpuinfo;
 	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
 	ppc_md.calibrate_decr = taishan_calibrate_decr;
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = taishan_early_serial_map;
 #endif
 	ppc_md.init = taishan_init;
 }

arch/ppc/platforms/4xx/yucca.c

Diff comments View file @ b187f18

 /*
  * Yucca board specific routines
  *
  * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
  *
  * Copyright 2004-2005 MontaVista Software Inc.
  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/ocp.h>
 #include <asm/pci-bridge.h>
 #include <asm/time.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
 #include <syslib/ibm44x_common.h>
 #include <syslib/ibm440gx_common.h>
 #include <syslib/ibm440sp_common.h>
 #include <syslib/ppc440spe_pcie.h>
 extern bd_t __res;
 static struct ibm44x_clocks clocks __initdata;
 static void __init
 yucca_calibrate_decr(void)
 {
 	unsigned int freq;
 	if (mfspr(SPRN_CCR1) & CCR1_TCS)
 		freq = YUCCA_TMR_CLK;
 	else
 		freq = clocks.cpu;
 	ibm44x_calibrate_decr(freq);
 }
 static int
 yucca_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: AMCC\n");
 	seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
 	return 0;
 }
 static enum {
 	HOSE_UNKNOWN,
 	HOSE_PCIX,
 	HOSE_PCIE0,
 	HOSE_PCIE1,
 	HOSE_PCIE2
 } hose_type[4];
 static inline int
 yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
 	if (hose_type[hose->index] == HOSE_PCIX) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 *	  A   B   C   D
 		 */
 		{
 			{ 81, -1, -1, -1 },	/* IDSEL 1 - PCIX0 Slot 0 */
 		};
 		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	} else if (hose_type[hose->index] == HOSE_PCIE0) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 *	  A   B   C   D
 		 */
 		{
 			{ 96, 97, 98, 99 },
 		};
 		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	} else if (hose_type[hose->index] == HOSE_PCIE1) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 *	  A   B   C   D
 		 */
 		{
 			{ 100, 101, 102, 103 },
 		};
 		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	} else if (hose_type[hose->index] == HOSE_PCIE2) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 *	  A   B   C   D
 		 */
 		{
 			{ 104, 105, 106, 107 },
 		};
 		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	}
 	return -1;
 }
 static void __init yucca_set_emacdata(void)
 {
 	struct ocp_def *def;
 	struct ocp_func_emac_data *emacdata;
 	/* Set phy_map, phy_mode, and mac_addr for the EMAC */
 	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 	emacdata = def->additions;
 	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
 	emacdata->phy_mode = PHY_MODE_GMII;
 	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 }
 static int __init yucca_pcie_card_present(int port)
 {
    void __iomem *pcie_fpga_base;
    u16 reg;
    pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
    reg = in_be16(pcie_fpga_base + FPGA_REG1C);
    iounmap(pcie_fpga_base);
    switch(port) {
    case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
    case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
    case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
    default: return 0;
    }
 }
 /*
  * For the given slot, set rootpoint mode, send power to the slot,
  * turn on the green LED and turn off the yellow LED, enable the clock
  * and turn off reset.
  */
 static void __init yucca_setup_pcie_fpga_rootpoint(int port)
 {
 	void __iomem *pcie_reg_fpga_base;
 	u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 	pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
 	switch(port) {
 	case 0:
 		rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 		endpoint    = 0;
 		power 	    = FPGA_REG1A_PE0_PWRON;
 		green_led   = FPGA_REG1A_PE0_GLED;
 		clock 	    = FPGA_REG1A_PE0_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE0_YLED;
 		reset_off   = FPGA_REG1C_PE0_PERST;
 		break;
 	case 1:
 		rootpoint   = 0;
 		endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 		power 	    = FPGA_REG1A_PE1_PWRON;
 		green_led   = FPGA_REG1A_PE1_GLED;
 		clock 	    = FPGA_REG1A_PE1_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE1_YLED;
 		reset_off   = FPGA_REG1C_PE1_PERST;
 		break;
 	case 2:
 		rootpoint   = 0;
 		endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 		power 	    = FPGA_REG1A_PE2_PWRON;
 		green_led   = FPGA_REG1A_PE2_GLED;
 		clock 	    = FPGA_REG1A_PE2_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE2_YLED;
 		reset_off   = FPGA_REG1C_PE2_PERST;
 		break;
 	default:
 		return;
 	}
 	out_be16(pcie_reg_fpga_base + FPGA_REG1A,
 		 ~(power | clock | green_led) &
 		 (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
 	out_be16(pcie_reg_fpga_base + FPGA_REG1C,
 		 ~(endpoint | reset_off) &
 		 (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
 	/*
 	 * Leave device in reset for a while after powering on the
 	 * slot to give it a chance to initialize.
 	 */
 	mdelay(250);
 	out_be16(pcie_reg_fpga_base + FPGA_REG1C,
 		 reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
 	iounmap(pcie_reg_fpga_base);
 }
 static void __init
 yucca_setup_hoses(void)
 {
 	struct pci_controller *hose;
 	char name[20];
 	int i;
 	if (0 && ppc440spe_init_pcie()) {
 		printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
 		return;
 	}
 	for (i = 0; i <= 2; ++i) {
 		if (!yucca_pcie_card_present(i))
 			continue;
 		printk(KERN_INFO "PCIE%d: card present\n", i);
 		yucca_setup_pcie_fpga_rootpoint(i);
 		if (ppc440spe_init_pcie_rootport(i)) {
 			printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
 			continue;
 		}
 		hose = pcibios_alloc_controller();
 		if (!hose)
 			return;
 		sprintf(name, "PCIE%d host bridge", i);
 		pci_init_resource(&hose->io_resource,
 				  YUCCA_PCIX_LOWER_IO,
 				  YUCCA_PCIX_UPPER_IO,
 				  IORESOURCE_IO,
 				  name);
 		hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
 			i * YUCCA_PCIE_MEM_SIZE;
 		hose->mem_space.end   = hose->mem_space.start +
 			YUCCA_PCIE_MEM_SIZE - 1;
 		pci_init_resource(&hose->mem_resources[0],
 				  hose->mem_space.start,
 				  hose->mem_space.end,
 				  IORESOURCE_MEM,
 				  name);
 		hose->first_busno = 0;
 		hose->last_busno  = 15;
 		hose_type[hose->index] = HOSE_PCIE0 + i;
 		ppc440spe_setup_pcie(hose, i);
 		hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 	}
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = yucca_map_irq;
 }
 TODC_ALLOC();
 static void __init
 yucca_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup ioremapped serial port access */
 	memset(&port, 0, sizeof(port));
 	port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
 	port.irq = UART0_INT;
 	port.uartclk = clocks.uart0;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 	port.line = 0;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 0 failed\n");
 	}
 	port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
 	port.irq = UART1_INT;
 	port.uartclk = clocks.uart1;
 	port.line = 1;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 1 failed\n");
 	}
 	port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
 	port.irq = UART2_INT;
 	port.uartclk = BASE_BAUD;
 	port.line = 2;
 	if (early_serial_setup(&port) != 0) {
 		printk("Early serial init of port 2 failed\n");
 	}
 }
 static void __init
 yucca_setup_arch(void)
 {
 	yucca_set_emacdata();
 #if !defined(CONFIG_BDI_SWITCH)
 	/*
 	 * The Abatron BDI JTAG debugger does not tolerate others
 	 * mucking with the debug registers.
 	 */
 	mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
 #endif
 	/*
 	 * Determine various clocks.
 	 * To be completely correct we should get SysClk
 	 * from FPGA, because it can be changed by on-board switches
 	 * --ebs
 	 */
 	/* 440GX and 440SPe clocking is the same - rd */
 	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 	ocp_sys_info.opb_bus_freq = clocks.opb;
 	/* init to some ~sane value until calibrate_delay() runs */
 	loops_per_jiffy = 50000000/HZ;
 	/* Setup PCIXn host bridges */
 	yucca_setup_hoses();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	yucca_early_serial_map();
 	/* Identify the system */
 	printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
 }
 void __init platform_init(unsigned long r3, unsigned long r4,
 		unsigned long r5, unsigned long r6, unsigned long r7)
 {
 	ibm44x_platform_init(r3, r4, r5, r6, r7);
 	ppc_md.setup_arch = yucca_setup_arch;
 	ppc_md.show_cpuinfo = yucca_show_cpuinfo;
 	ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
 	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
 	ppc_md.calibrate_decr = yucca_calibrate_decr;
 #ifdef CONFIG_KGDB
 	ppc_md.early_serial_map = yucca_early_serial_map;
 #endif
 }

arch/ppc/platforms/85xx/sbc8560.c

Diff comments View file @ b187f18

 /*
  * Wind River SBC8560 board specific routines
  *
  * Maintainer: Kumar Gala
  *
  * Copyright 2004 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/major.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/serial.h>
 #include <linux/tty.h>	/* for linux/serial_core.h */
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/initrd.h>
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/atomic.h>
 #include <asm/time.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/open_pic.h>
 #include <asm/bootinfo.h>
 #include <asm/pci-bridge.h>
 #include <asm/mpc85xx.h>
 #include <asm/irq.h>
 #include <asm/immap_85xx.h>
 #include <asm/kgdb.h>
 #include <asm/ppc_sys.h>
 #include <mm/mmu_decl.h>
 #include <syslib/ppc85xx_common.h>
 #include <syslib/ppc85xx_setup.h>
 #ifdef CONFIG_SERIAL_8250
 static void __init
 sbc8560_early_serial_map(void)
 {
         struct uart_port uart_req;
         /* Setup serial port access */
         memset(&uart_req, 0, sizeof (uart_req));
 	uart_req.irq = MPC85xx_IRQ_EXT9;
 	uart_req.flags = STD_COM_FLAGS;
 	uart_req.uartclk = BASE_BAUD * 16;
         uart_req.iotype = UPIO_MEM;
         uart_req.mapbase = UARTA_ADDR;
         uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART0_SIZE);
 	uart_req.type = PORT_16650;
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
         gen550_init(0, &uart_req);
 #endif
         if (early_serial_setup(&uart_req) != 0)
                 printk("Early serial init of port 0 failed\n");
         /* Assume early_serial_setup() doesn't modify uart_req */
 	uart_req.line = 1;
         uart_req.mapbase = UARTB_ADDR;
         uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART1_SIZE);
 	uart_req.irq = MPC85xx_IRQ_EXT10;
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
         gen550_init(1, &uart_req);
 #endif
         if (early_serial_setup(&uart_req) != 0)
                 printk("Early serial init of port 1 failed\n");
 }
 #endif
 /* ************************************************************************
  *
  * Setup the architecture
  *
  */
 static void __init
 sbc8560_setup_arch(void)
 {
 	bd_t *binfo = (bd_t *) __res;
 	unsigned int freq;
 	struct gianfar_platform_data *pdata;
 	struct gianfar_mdio_data *mdata;
 	/* get the core frequency */
 	freq = binfo->bi_intfreq;
 	if (ppc_md.progress)
 		ppc_md.progress("sbc8560_setup_arch()", 0);
 	/* Set loops_per_jiffy to a half-way reasonable value,
 	   for use until calibrate_delay gets called. */
 	loops_per_jiffy = freq / HZ;
 #ifdef CONFIG_PCI
 	/* setup PCI host bridges */
 	mpc85xx_setup_hose();
 #endif
 #ifdef CONFIG_SERIAL_8250
 	sbc8560_early_serial_map();
 #endif
 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 	/* Invalidate the entry we stole earlier the serial ports
 	 * should be properly mapped */
 	invalidate_tlbcam_entry(num_tlbcam_entries - 1);
 #endif
 	/* setup the board related info for the MDIO bus */
 	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
 	mdata->irq[25] = MPC85xx_IRQ_EXT6;
 	mdata->irq[26] = MPC85xx_IRQ_EXT7;
 	mdata->irq[31] = PHY_POLL;
 	/* setup the board related information for the enet controllers */
 	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 	if (pdata) {
 		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 		pdata->bus_id = 0;
 		pdata->phy_id = 25;
 		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 	}
 	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 	if (pdata) {
 		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 		pdata->bus_id = 0;
 		pdata->phy_id = 26;
 		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 	}
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef  CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 }
 /* ************************************************************************ */
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
 {
 	/* parse_bootinfo must always be called first */
 	parse_bootinfo(find_bootinfo());
 	/*
 	 * If we were passed in a board information, copy it into the
 	 * residual data area.
 	 */
 	if (r3) {
 		memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 		       sizeof (bd_t));
 	}
 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 	/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
 	settlbcam(num_tlbcam_entries - 1, UARTA_ADDR,
 		  UARTA_ADDR, 0x1000, _PAGE_IO, 0);
 #endif
 #if defined(CONFIG_BLK_DEV_INITRD)
 	/*
 	 * If the init RAM disk has been configured in, and there's a valid
 	 * starting address for it, set it up.
 	 */
 	if (r4) {
 		initrd_start = r4 + KERNELBASE;
 		initrd_end = r5 + KERNELBASE;
 	}
 #endif				/* CONFIG_BLK_DEV_INITRD */
 	/* Copy the kernel command line arguments to a safe place. */
 	if (r6) {
 		*(char *) (r7 + KERNELBASE) = 0;
 		strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 	}
 	identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 	/* setup the PowerPC module struct */
 	ppc_md.setup_arch = sbc8560_setup_arch;
 	ppc_md.show_cpuinfo = sbc8560_show_cpuinfo;
 	ppc_md.init_IRQ = sbc8560_init_IRQ;
 	ppc_md.get_irq = openpic_get_irq;
 	ppc_md.restart = mpc85xx_restart;
 	ppc_md.power_off = mpc85xx_power_off;
 	ppc_md.halt = mpc85xx_halt;
 	ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 	ppc_md.time_init = NULL;
 	ppc_md.set_rtc_time = NULL;
 	ppc_md.get_rtc_time = NULL;
 	ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 	ppc_md.progress = gen550_progress;
 #endif	/* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
 	ppc_md.early_serial_map = sbc8560_early_serial_map;
 #endif	/* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 	if (ppc_md.progress)
 		ppc_md.progress("sbc8560_init(): exit", 0);
 }

arch/ppc/platforms/chestnut.c

Diff comments View file @ b187f18

 /*
  * Board setup routines for IBM Chestnut
  *
  * Author: <source@mvista.com>
  *
  * <2004> (c) MontaVista Software, Inc. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/kdev_t.h>
 #include <linux/major.h>
 #include <linux/blkdev.h>
 #include <linux/console.h>
 #include <linux/root_dev.h>
 #include <linux/initrd.h>
 #include <linux/delay.h>
 #include <linux/seq_file.h>
 #include <linux/ide.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/time.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/hw_irq.h>
 #include <asm/machdep.h>
 #include <asm/kgdb.h>
 #include <asm/bootinfo.h>
 #include <asm/mv64x60.h>
 #include <platforms/chestnut.h>
 static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
 static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
 static mv64x60_handle_t	bh;
 extern void gen550_progress(char *, unsigned short);
 extern void gen550_init(int, struct uart_port *);
 extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
 #define BIT(x) (1<<x)
 #define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
 				BIT(MV64x60_CPU2DEV_1_WIN) | \
 				BIT(MV64x60_CPU2DEV_2_WIN) | \
 				BIT(MV64x60_CPU2DEV_3_WIN) | \
 				BIT(MV64x60_CPU2BOOT_WIN))
 /**************************************************************************
  * FUNCTION: chestnut_calibrate_decr
  *
  * DESCRIPTION: initialize decrementer interrupt frequency (used as system
  *              timer)
  *
  ****/
 static void __init
 chestnut_calibrate_decr(void)
 {
 	ulong freq;
 	freq = CHESTNUT_BUS_SPEED / 4;
 	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
 		freq/1000000, freq%1000000);
 	tb_ticks_per_jiffy = freq / HZ;
 	tb_to_us = mulhwu_scale_factor(freq, 1000000);
 }
 static int
 chestnut_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: IBM\n");
 	seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
 	return 0;
 }
 /**************************************************************************
  * FUNCTION: chestnut_find_end_of_memory
  *
  * DESCRIPTION: ppc_md memory size callback
  *
  ****/
 unsigned long __init
 chestnut_find_end_of_memory(void)
 {
    	static int  mem_size = 0;
    	if (mem_size == 0) {
       		mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 				MV64x60_TYPE_MV64460);
    	}
    	return mem_size;
 }
 #if defined(CONFIG_SERIAL_8250)
 static void __init
 chestnut_early_serial_map(void)
 {
 	struct uart_port port;
 	/* Setup serial port access */
 	memset(&port, 0, sizeof(port));
 	port.uartclk = BASE_BAUD * 16;
 	port.irq = UART0_INT;
 	port.flags = STD_COM_FLAGS | UPF_IOREMAP;
 	port.iotype = UPIO_MEM;
 	port.mapbase = CHESTNUT_UART0_IO_BASE;
 	port.regshift = 0;
 	if (early_serial_setup(&port) != 0)
 		printk("Early serial init of port 0 failed\n");
 	/* Assume early_serial_setup() doesn't modify serial_req */
 	port.line = 1;
 	port.irq = UART1_INT;
 	port.mapbase = CHESTNUT_UART1_IO_BASE;
 	if (early_serial_setup(&port) != 0)
 		printk("Early serial init of port 1 failed\n");
 }
 #endif
 /**************************************************************************
  * FUNCTION: chestnut_map_irq
  *
  * DESCRIPTION: 0 return since PCI IRQs not needed
  *
  ****/
 static int __init
 chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] = {
 		{CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
 		 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
 		{CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
 		 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
 		{CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
 		 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
 		{CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
 		 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
 	};
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 /**************************************************************************
  * FUNCTION: chestnut_setup_bridge
  *
  * DESCRIPTION: initalize board-specific settings on the MV64360
  *
  ****/
 static void __init
 chestnut_setup_bridge(void)
 {
 	struct mv64x60_setup_info	si;
 	int i;
    	if ( ppc_md.progress )
 		ppc_md.progress("chestnut_setup_bridge: enter", 0);
 	memset(&si, 0, sizeof(si));
 	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 	/* setup only PCI bus 0 (bus 1 not used) */
 	si.pci_0.enable_bus = 1;
 	si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
 	si.pci_0.pci_io.pci_base_hi = 0;
 	si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
 	si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
 	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 	si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
 	si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
 	si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
 	si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
 	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 	si.pci_0.pci_cmd_bits = 0;
 	si.pci_0.latency_timer = 0x80;
 	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 #if defined(CONFIG_NOT_COHERENT_CACHE)
 		si.cpu_prot_options[i] = 0;
 		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 		si.pci_1.acc_cntl_options[i] =
 		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
 		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 #else
 		si.cpu_prot_options[i] = 0;
 		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 		si.pci_1.acc_cntl_options[i] =
 		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
 		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
 		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 #endif
 	}
    	/* Lookup host bridge - on CPU 0 - no SMP support */
    	if (mv64x60_init(&bh, &si)) {
         	printk("\n\nPCI Bridge initialization failed!\n");
    	}
 	pci_dram_offset = 0;
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = chestnut_map_irq;
 	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 	mv64x60_set_bus(&bh, 0, 0);
 	bh.hose_a->first_busno = 0;
 	bh.hose_a->last_busno = 0xff;
 	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 }
 void __init
 chestnut_setup_peripherals(void)
 {
    	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 			CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 			CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 			CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 	cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 			CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 			CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
    	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 			CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 #ifdef CONFIG_NOT_COHERENT_CACHE
    	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 #else
    	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 #endif
 	sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
    	memset(sram_base, 0, MV64360_SRAM_SIZE);
 	/*
 	 * Configure MPP pins for PCI DMA
 	 *
 	 * PCI Slot	GNT pin		REQ pin
 	 *	0	MPP16		MPP17
 	 *	1	MPP18		MPP19
 	 *	2	MPP20		MPP21
 	 *	3	MPP22		MPP23
 	 */
 	mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
 			(0x1 << 0)  |	/* MPPSel16 PCI0_GNT[0] */
 			(0x1 << 4)  |	/* MPPSel17 PCI0_REQ[0] */
 			(0x1 << 8)  |	/* MPPSel18 PCI0_GNT[1] */
 			(0x1 << 12) |	/* MPPSel19 PCI0_REQ[1] */
 			(0x1 << 16) |	/* MPPSel20 PCI0_GNT[2] */
 			(0x1 << 20) |	/* MPPSel21 PCI0_REQ[2] */
 			(0x1 << 24) |	/* MPPSel22 PCI0_GNT[3] */
 			(0x1 << 28));	/* MPPSel23 PCI0_REQ[3] */
 	/*
 	 * Set unused MPP pins for output, as per schematic note
 	 *
 	 * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
 	 *		MPP09, MPP10, MPP13, MPP14, MPP15
 	 */
 	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
 			(0xf << 4)  |	/* MPPSel01 GPIO[1] */
 			(0xf << 8)  |	/* MPPSel02 GPIO[2] */
 			(0xf << 16) |	/* MPPSel04 GPIO[4] */
 			(0xf << 20) |	/* MPPSel05 GPIO[5] */
 			(0xf << 24));	/* MPPSel06 GPIO[6] */
 	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
 			(0xf << 4)  |	/* MPPSel09 GPIO[9] */
 			(0xf << 8)  |	/* MPPSel10 GPIO[10] */
 			(0xf << 20) |	/* MPPSel13 GPIO[13] */
 			(0xf << 24) |	/* MPPSel14 GPIO[14] */
 			(0xf << 28));	/* MPPSel15 GPIO[15] */
 	mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
 			BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
 			BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15));
    	/*
     	 * Configure the following MPP pins to indicate a level
     	 * triggered interrupt
     	 *
        	 * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
        	 * MPP25 - UART A  (high)
        	 * MPP26 - UART B  (high)
 	 * MPP28 - PCI Slot 3 (low)
 	 * MPP29 - PCI Slot 2 (low)
 	 * MPP30 - PCI Slot 1 (low)
 	 * MPP31 - PCI Slot 0 (low)
     	 */
         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
                         BIT(3) | BIT(2) | BIT(1) | BIT(0)	 | /* MPP 24 */
                         BIT(7) | BIT(6) | BIT(5) | BIT(4)	 | /* MPP 25 */
                         BIT(11) | BIT(10) | BIT(9) | BIT(8)	 | /* MPP 26 */
 			BIT(19) | BIT(18) | BIT(17) | BIT(16)	 | /* MPP 28 */
 			BIT(23) | BIT(22) | BIT(21) | BIT(20)	 | /* MPP 29 */
 			BIT(27) | BIT(26) | BIT(25) | BIT(24)	 | /* MPP 30 */
 			BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
    	/*
 	 * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
 	 * 31 (low) interrupt polarity input signal and level triggered
     	 */
    	mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
    	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
 			BIT(28) | BIT(29) | BIT(30) | BIT(31));
    	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
 			BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 			BIT(31));
    	/* Config GPP interrupt controller to respond to level trigger */
    	mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
    	/*
     	 * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
     	 */
    	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
 			~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 			  BIT(31)));
    	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
 			BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 			BIT(31));
    	/*
     	 * Dismiss and then enable interrupt on CPU #0 high cause register
     	 * BIT27 summarizes GPP interrupts 24-31
     	 */
    	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
    	if (ppc_md.progress)
 		ppc_md.progress("chestnut_setup_bridge: exit", 0);
 }
 /**************************************************************************
  * FUNCTION: chestnut_setup_arch
  *
  * DESCRIPTION: ppc_md machine configuration callback
  *
  ****/
 static void __init
 chestnut_setup_arch(void)
 {
 	if (ppc_md.progress)
       		ppc_md.progress("chestnut_setup_arch: enter", 0);
 	/* init to some ~sane value until calibrate_delay() runs */
 	loops_per_jiffy = 50000000 / HZ;
    	/* if the time base value is greater than bus freq/4 (the TB and
     	* decrementer tick rate) + signed integer rollover value, we
     	* can spend a fair amount of time waiting for the rollover to
     	* happen.  To get around this, initialize the time base register
     	* to a "safe" value.
     	*/
    	set_tb(0, 0);
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_SDA2;
 #endif
    	/*
     	* Set up the L2CR register.
     	*/
  	_set_L2CR(_get_L2CR() | L2CR_L2E);
 	chestnut_setup_bridge();
 	chestnut_setup_peripherals();
 #ifdef CONFIG_DUMMY_CONSOLE
 	conswitchp = &dummy_con;
 #endif
 #if defined(CONFIG_SERIAL_8250)
 	chestnut_early_serial_map();
 #endif
 	/* Identify the system */
 	printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
 	printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
 		" (source@mvista.com)\n");
 	if (ppc_md.progress)
       		ppc_md.progress("chestnut_setup_arch: exit", 0);
 }
 #ifdef CONFIG_MTD_PHYSMAP
 static struct mtd_partition ptbl;
 static int __init
 chestnut_setup_mtd(void)
 {
 	memset(&ptbl, 0, sizeof(ptbl));
 	ptbl.name = "User FS";
 	ptbl.size = CHESTNUT_32BIT_SIZE;
 	physmap_map.size = CHESTNUT_32BIT_SIZE;
 	physmap_set_partitions(&ptbl, 1);
 	return 0;
 }
 arch_initcall(chestnut_setup_mtd);
 #endif
 /**************************************************************************
  * FUNCTION: chestnut_restart
  *
  * DESCRIPTION: ppc_md machine reset callback
  *              reset the board via the CPLD command register
  *
  ****/
 static void
 chestnut_restart(char *cmd)
 {
 	volatile ulong i = 10000000;
 	local_irq_disable();
         /*
          * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
          *
          * MPP24 - board reset
          */
    	writeb(0x1, cpld_base + 3);
 	/* GPP pin tied to MPP earlier */
         mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
    	while (i-- > 0);
    	panic("restart failed\n");
 }
 static void
 chestnut_halt(void)
 {
 	local_irq_disable();
 	for (;;);
 	/* NOTREACHED */
 }
 static void
 chestnut_power_off(void)
 {
 	chestnut_halt();
 	/* NOTREACHED */
 }
 /**************************************************************************
  * FUNCTION: chestnut_map_io
  *
  * DESCRIPTION: configure fixed memory-mapped IO
  *
  ****/
 static void __init
 chestnut_map_io(void)
 {
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
 		_PAGE_IO);
 #endif
 }
 /**************************************************************************
  * FUNCTION: chestnut_set_bat
  *
  * DESCRIPTION: configures a (temporary) bat mapping for early access to
  *              device I/O
  *
  ****/
 static __inline__ void
 chestnut_set_bat(void)
 {
         mb();
         mtspr(SPRN_DBAT3U, 0xf0001ffe);
         mtspr(SPRN_DBAT3L, 0xf000002a);
         mb();
 }
 /**************************************************************************
  * FUNCTION: platform_init
  *
  * DESCRIPTION: main entry point for configuring board-specific machine
  *              callbacks
  *
  ****/
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
 {
 	parse_bootinfo(find_bootinfo());
         /* Copy the kernel command line arguments to a safe place. */
         if (r6) {
                 *(char *) (r7 + KERNELBASE) = 0;
                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
         }
 	isa_mem_base = 0;
 	ppc_md.setup_arch = chestnut_setup_arch;
 	ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
 	ppc_md.init_IRQ = mv64360_init_irq;
 	ppc_md.get_irq = mv64360_get_irq;
 	ppc_md.init = NULL;
 	ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
 	ppc_md.setup_io_mappings  = chestnut_map_io;
 	ppc_md.restart = chestnut_restart;
    	ppc_md.power_off = chestnut_power_off;
    	ppc_md.halt = chestnut_halt;
 	ppc_md.time_init = NULL;
 	ppc_md.set_rtc_time = NULL;
 	ppc_md.get_rtc_time = NULL;
 	ppc_md.calibrate_decr = chestnut_calibrate_decr;
 	ppc_md.nvram_read_val = NULL;
 	ppc_md.nvram_write_val = NULL;
 	ppc_md.heartbeat = NULL;
 	bh.p_base = CONFIG_MV64X60_NEW_BASE;
 	chestnut_set_bat();
 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 	ppc_md.progress = gen550_progress;
 #endif
 #if defined(CONFIG_KGDB)
 	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 #endif
 	if (ppc_md.progress)
                 ppc_md.progress("chestnut_init(): exit", 0);
 }

arch/ppc/platforms/ev64260.c

Diff comments View file @ b187f18

 /*
  * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
  * 2001-2003 (c) MontaVista, Software, Inc.  This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
 /*
  * The EV-64260-BP port is the result of hard work from many people from
  * many companies.  In particular, employees of Marvell/Galileo, Mission
  * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
  *
  * Note: I have not been able to get *all* PCI slots to work reliably
  *	at 66 MHz.  I recommend setting jumpers J15 & J16 to short pins 1&2
  *	so that 33 MHz is used. --MAG
  * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
  * 	At 100MHz, they are solid.
  */
 #include <linux/delay.h>
 #include <linux/pci.h>
 #include <linux/ide.h>
 #include <linux/irq.h>
 #include <linux/fs.h>
 #include <linux/seq_file.h>
 #include <linux/console.h>
 #include <linux/initrd.h>
 #include <linux/root_dev.h>
 #include <linux/platform_device.h>
 #if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #else
 #include <linux/mv643xx.h>
 #endif
 #include <asm/bootinfo.h>
 #include <asm/machdep.h>
 #include <asm/mv64x60.h>
 #include <asm/todc.h>
 #include <asm/time.h>
 #include <platforms/ev64260.h>
 #define BOARD_VENDOR	"Marvell/Galileo"
 #define BOARD_MACHINE	"EV-64260-BP"
 static struct mv64x60_handle	bh;
 #if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
 extern void gen550_progress(char *, unsigned short);
 extern void gen550_init(int, struct uart_port *);
 #endif
 static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
 	18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
 };
 static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
 	{ 1, 15, 14,  2,  4, 13,  5,  9,  6, 11,  8, 10, 16, 12,  7,  0 },
 	{ 0, 30,  0,  2,  0, 26,  0, 18,  0, 22, 20, 24, 28, 32,  0,  0 }
 };
 TODC_ALLOC();
 static int
 ev64260_get_bus_speed(void)
 {
 	return 100000000;
 }
 static int
 ev64260_get_cpu_speed(void)
 {
 	unsigned long	pvr, hid1, pll_ext;
 	pvr = PVR_VER(mfspr(SPRN_PVR));
 	if (pvr != PVR_VER(PVR_7450)) {
 		hid1 = mfspr(SPRN_HID1) >> 28;
 		return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
 	}
 	else {
 		hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13;
 		pll_ext = 0; /* No way to read; must get from schematic */
 		return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
 	}
 }
 unsigned long __init
 ev64260_find_end_of_memory(void)
 {
 	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 		MV64x60_TYPE_GT64260A);
 }
 /*
  * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
  * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
  *	PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
  *	This is the most IRQs you can get from one bus with this board, though.
  */
 static int __init
 ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
 	if (hose->index == 0) {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 * 	   A   B   C   D
 		 */
 		{
 			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
 			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
 		};
 		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	}
 	else {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
 		 * 	   A   B   C   D
 		 */
 		{
 			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
 			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
 		};
 		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
 	}
 }
 static void __init
 ev64260_setup_peripherals(void)
 {
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 		EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 		EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 		EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 		EV64260_UART_BASE, EV64260_UART_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 		EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
 			ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
 	mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29)));
 	mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
 	if (ev64260_get_bus_speed() > 100000000)
 		mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
 	mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
 	mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
         /*
          * Enabling of PCI internal-vs-external arbitration
          * is a platform- and errata-dependent decision.
          */
         if (bh.type == MV64x60_TYPE_GT64260A )  {
                 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
                 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
         }
         mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
 	/*
 	 * Turn off timer/counters.  Not turning off watchdog timer because
 	 * can't read its reg on the 64260A so don't know if we'll be enabling
 	 * or disabling.
 	 */
 	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
 	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
 			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
 	/*
 	 * Set MPSC Multiplex RMII
 	 * NOTE: ethernet driver modifies bit 0 and 1
 	 */
 	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
 	/*
 	 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
 	 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
 	 * register).  Need to route the MPP inputs to the GPP and set the
 	 * polarity correctly.
 	 *
 	 * In MPP Control 2 Register
 	 *   MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
 	 *   MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
 	 */
 	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
 	/*
 	 * In MPP Control 3 Register
 	 *   MPP 26 -> GPP 26 (RTC INT)		bits  8-11 -> 0
 	 *   MPP 27 -> GPP 27 (PCI 0 INTA)	bits 12-15 -> 0
 	 *   MPP 29 -> GPP 29 (PCI 1 INTA)	bits 20-23 -> 0
 	 */
 	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20));
 #define GPP_EXTERNAL_INTERRUPTS \
 		((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
 	/* DUART & PCI interrupts are inputs */
 	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
 	/* DUART & PCI interrupts are active low */
 	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
 	/* Clear any pending interrupts for these inputs and enable them. */
 	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
 	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
 	return;
 }
 static void __init
 ev64260_setup_bridge(void)
 {
 	struct mv64x60_setup_info	si;
 	int				i;
 	memset(&si, 0, sizeof(si));
 	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 	si.pci_0.enable_bus = 1;
 	si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE;
 	si.pci_0.pci_io.pci_base_hi = 0;
 	si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE;
 	si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE;
 	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE;
 	si.pci_0.pci_mem[0].pci_base_hi = 0;
 	si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE;
 	si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE;
 	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_0.pci_cmd_bits = 0;
 	si.pci_0.latency_timer = 0x8;
 	si.pci_1.enable_bus = 1;
 	si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE;
 	si.pci_1.pci_io.pci_base_hi = 0;
 	si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE;
 	si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE;
 	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE;
 	si.pci_1.pci_mem[0].pci_base_hi = 0;
 	si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE;
 	si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE;
 	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_1.pci_cmd_bits = 0;
 	si.pci_1.latency_timer = 0x8;
 	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 		si.cpu_prot_options[i] = 0;
 		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
 		si.pci_0.acc_cntl_options[i] =
 			GT64260_PCI_ACC_CNTL_DREADEN |
 			GT64260_PCI_ACC_CNTL_RDPREFETCH |
 			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
 			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
 			GT64260_PCI_ACC_CNTL_SWAP_NONE |
 			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
 		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
 		si.pci_1.acc_cntl_options[i] =
 			GT64260_PCI_ACC_CNTL_DREADEN |
 			GT64260_PCI_ACC_CNTL_RDPREFETCH |
 			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
 			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
 			GT64260_PCI_ACC_CNTL_SWAP_NONE |
 			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
 		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
 	}
         /* Lookup PCI host bridges */
         if (mv64x60_init(&bh, &si))
                 printk(KERN_ERR "Bridge initialization failed.\n");
 	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = ev64260_map_irq;
 	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 	mv64x60_set_bus(&bh, 0, 0);
 	bh.hose_a->first_busno = 0;
 	bh.hose_a->last_busno = 0xff;
 	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
 	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
 	bh.hose_b->last_busno = 0xff;
 	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
 		bh.hose_b->first_busno);
 	return;
 }
 #if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
 static void __init
 ev64260_early_serial_map(void)
 {
 	struct uart_port	port;
 	static char		first_time = 1;
 	if (first_time) {
 		memset(&port, 0, sizeof(port));
 		port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
 		port.irq = EV64260_UART_0_IRQ;
 		port.uartclk = BASE_BAUD * 16;
 		port.regshift = 2;
 		port.iotype = UPIO_MEM;
 		port.flags = STD_COM_FLAGS;
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 		gen550_init(0, &port);
 #endif
 		if (early_serial_setup(&port) != 0)
 			printk(KERN_WARNING "Early serial init of port 0"
 				"failed\n");
 		first_time = 0;
 	}
 	return;
 }
 #elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
 static void __init
 ev64260_early_serial_map(void)
 {
 }
 #endif
 static void __init
 ev64260_setup_arch(void)
 {
 	if (ppc_md.progress)
 		ppc_md.progress("ev64260_setup_arch: enter", 0);
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef	CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_SDA2;
 #endif
 	if (ppc_md.progress)
 		ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
 	/* Enable L2 and L3 caches (if 745x) */
 	_set_L2CR(_get_L2CR() | L2CR_L2E);
 	_set_L3CR(_get_L3CR() | L3CR_L3E);
 	if (ppc_md.progress)
 		ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
 	ev64260_setup_bridge();		/* set up PCI bridge(s) */
 	ev64260_setup_peripherals();	/* set up chip selects/GPP/MPP etc */
 	if (ppc_md.progress)
 		ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
 	ev64260_early_serial_map();
 #endif
 	printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc."
 		"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
 	if (ppc_md.progress)
 		ppc_md.progress("ev64260_setup_arch: exit", 0);
 	return;
 }
 /* Platform device data fixup routines. */
 #if defined(CONFIG_SERIAL_MPSC)
 static void __init
 ev64260_fixup_mpsc_pdata(struct platform_device *pdev)
 {
 	struct mpsc_pdata *pdata;
 	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 	pdata->max_idle = 40;
 	pdata->default_baud = EV64260_DEFAULT_BAUD;
 	pdata->brg_clk_src = EV64260_MPSC_CLK_SRC;
 	pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
 	return;
 }
 static int
 ev64260_platform_notify(struct device *dev)
 {
 	static struct {
 		char	*bus_id;
 		void	((*rtn)(struct platform_device *pdev));
 	} dev_map[] = {
 		{ MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata },
 		{ MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata },
 	};
 	struct platform_device	*pdev;
 	int	i;
 	if (dev && dev->bus_id)
 		for (i=0; i<ARRAY_SIZE(dev_map); i++)
 			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 				BUS_ID_SIZE)) {
 				pdev = container_of(dev,
 					struct platform_device, dev);
 				dev_map[i].rtn(pdev);
 			}
 	return 0;
 }
 #endif
 static void
 ev64260_reset_board(void *addr)
 {
 	local_irq_disable();
 	/* disable and invalidate the L2 cache */
 	_set_L2CR(0);
 	_set_L2CR(0x200000);
 	/* flush and disable L1 I/D cache */
 	__asm__ __volatile__
 	("mfspr   3,1008\n\t"
 	 "ori	5,5,0xcc00\n\t"
 	 "ori	4,3,0xc00\n\t"
 	 "andc	5,3,5\n\t"
 	 "sync\n\t"
 	 "mtspr	1008,4\n\t"
 	 "isync\n\t"
 	 "sync\n\t"
 	 "mtspr	1008,5\n\t"
 	 "isync\n\t"
 	 "sync\n\t");
 	/* unmap any other random cs's that might overlap with bootcs */
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
 	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
 	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
 	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
 	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 	/* map bootrom back in to gt @ reset defaults */
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 						0xff800000, 8*1024*1024, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 	/* move reg base back to default, setup default pci0 */
 	mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
 		(1<<24) | CONFIG_MV64X60_BASE >> 20);
 	/* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
 	 * via BAT or MMU, and MSR IR/DR is ON */
 	/* SRR0 has system reset vector, SRR1 has default MSR value */
 	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
 	/* NOTE: assumes reset vector is at 0xfff00100 */
 	__asm__ __volatile__
 	("mtspr   26, %0\n\t"
 	 "li      4,(1<<6)\n\t"
 	 "mtspr   27,4\n\t"
 	 "rfi\n\t"
 	 :: "r" (addr):"r4");
 	return;
 }
 static void
 ev64260_restart(char *cmd)
 {
 	volatile ulong	i = 10000000;
 	ev64260_reset_board((void *)0xfff00100);
 	while (i-- > 0);
 	panic("restart failed\n");
 }
 static void
 ev64260_halt(void)
 {
 	local_irq_disable();
 	while (1);
 	/* NOTREACHED */
 }
 static void
 ev64260_power_off(void)
 {
 	ev64260_halt();
 	/* NOTREACHED */
 }
 static int
 ev64260_show_cpuinfo(struct seq_file *m)
 {
 	uint pvid;
 	pvid = mfspr(SPRN_PVR);
 	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
 	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
 	seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
 	seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
 	return 0;
 }
 /* DS1501 RTC has too much variation to use RTC for calibration */
 static void __init
 ev64260_calibrate_decr(void)
 {
 	ulong freq;
 	freq = ev64260_get_bus_speed()/4;
 	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
 	       freq/1000000, freq%1000000);
 	tb_ticks_per_jiffy = freq / HZ;
 	tb_to_us = mulhwu_scale_factor(freq, 1000000);
 	return;
 }
 /*
  * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
  */
 static __inline__ void
 ev64260_set_bat(void)
 {
 	mb();
 	mtspr(SPRN_DBAT1U, 0xfb0001fe);
 	mtspr(SPRN_DBAT1L, 0xfb00002a);
 	mb();
 	return;
 }
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 static void __init
 ev64260_map_io(void)
 {
 	io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
 }
 #endif
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
 {
 #ifdef CONFIG_BLK_DEV_INITRD
 	extern int	initrd_below_start_ok;
 	initrd_start=initrd_end=0;
 	initrd_below_start_ok=0;
 #endif /* CONFIG_BLK_DEV_INITRD */
 	parse_bootinfo(find_bootinfo());
 	isa_mem_base = 0;
 	isa_io_base = EV64260_PCI0_IO_CPU_BASE;
 	pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE;
 	loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
 	ppc_md.setup_arch = ev64260_setup_arch;
 	ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
 	ppc_md.init_IRQ = gt64260_init_irq;
 	ppc_md.get_irq = gt64260_get_irq;
 	ppc_md.restart = ev64260_restart;
 	ppc_md.power_off = ev64260_power_off;
 	ppc_md.halt = ev64260_halt;
 	ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
 	ppc_md.init = NULL;
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 	ppc_md.calibrate_decr = ev64260_calibrate_decr;
 	bh.p_base = CONFIG_MV64X60_NEW_BASE;
 	ev64260_set_bat();
 #ifdef	CONFIG_SERIAL_8250
 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 	ppc_md.setup_io_mappings = ev64260_map_io;
 	ppc_md.progress = gen550_progress;
 #endif
 #if defined(CONFIG_KGDB)
 	ppc_md.setup_io_mappings = ev64260_map_io;
 	ppc_md.early_serial_map = ev64260_early_serial_map;
 #endif
 #elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
 #ifdef	CONFIG_SERIAL_TEXT_DEBUG
 	ppc_md.setup_io_mappings = ev64260_map_io;
 	ppc_md.progress = mv64x60_mpsc_progress;
 	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
 #endif	/* CONFIG_SERIAL_TEXT_DEBUG */
 #ifdef	CONFIG_KGDB
 	ppc_md.setup_io_mappings = ev64260_map_io;
 	ppc_md.early_serial_map = ev64260_early_serial_map;
 #endif	/* CONFIG_KGDB */
 #endif
 #if defined(CONFIG_SERIAL_MPSC)
 	platform_notify = ev64260_platform_notify;
 #endif
 	return;
 }

arch/ppc/platforms/radstone_ppc7d.c

Diff comments View file @ b187f18

 /*
  * Board setup routines for the Radstone PPC7D boards.
  *
  * Author: James Chapman <jchapman@katalix.com>
  *
  * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  */
 /* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs,
  * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse,
  * 4 serial ports, 2 high speed serial ports (MPSCs) and optional
  * SCSI / VGA.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/major.h>
 #include <linux/initrd.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/serial.h>
 #include <linux/tty.h>		/* for linux/serial_core.h */
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/mv643xx.h>
 #include <linux/netdevice.h>
 #include <linux/platform_device.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/time.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/prom.h>
 #include <asm/smp.h>
 #include <asm/vga.h>
 #include <asm/open_pic.h>
 #include <asm/i8259.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/mpc10x.h>
 #include <asm/pci-bridge.h>
 #include <asm/mv64x60.h>
 #include "radstone_ppc7d.h"
 #undef DEBUG
 #define PPC7D_RST_PIN			17 	/* GPP17 */
 extern u32 mv64360_irq_base;
 extern spinlock_t rtc_lock;
 static struct mv64x60_handle bh;
 static int ppc7d_has_alma;
 extern void gen550_progress(char *, unsigned short);
 extern void gen550_init(int, struct uart_port *);
 /* FIXME - move to h file */
 extern int ds1337_do_command(int id, int cmd, void *arg);
 #define DS1337_GET_DATE         0
 #define DS1337_SET_DATE         1
 /* residual data */
 unsigned char __res[sizeof(bd_t)];
 /*****************************************************************************
  * Serial port code
  *****************************************************************************/
 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
 static void __init ppc7d_early_serial_map(void)
 {
 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
 	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
 #elif defined(CONFIG_SERIAL_8250)
 	struct uart_port serial_req;
 	/* Setup serial port access */
 	memset(&serial_req, 0, sizeof(serial_req));
 	serial_req.uartclk = UART_CLK;
 	serial_req.irq = 4;
 	serial_req.flags = STD_COM_FLAGS;
 	serial_req.iotype = UPIO_MEM;
 	serial_req.membase = (u_char *) PPC7D_SERIAL_0;
 	gen550_init(0, &serial_req);
 	if (early_serial_setup(&serial_req) != 0)
 		printk(KERN_ERR "Early serial init of port 0 failed\n");
 	/* Assume early_serial_setup() doesn't modify serial_req */
 	serial_req.line = 1;
 	serial_req.irq = 3;
 	serial_req.membase = (u_char *) PPC7D_SERIAL_1;
 	gen550_init(1, &serial_req);
 	if (early_serial_setup(&serial_req) != 0)
 		printk(KERN_ERR "Early serial init of port 1 failed\n");
 #else
 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
 #endif
 }
 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
 /*****************************************************************************
  * Low-level board support code
  *****************************************************************************/
 static unsigned long __init ppc7d_find_end_of_memory(void)
 {
 	bd_t *bp = (bd_t *) __res;
 	if (bp->bi_memsize)
 		return bp->bi_memsize;
 	return (256 * 1024 * 1024);
 }
 static void __init ppc7d_map_io(void)
 {
 	/* remove temporary mapping */
 	mtspr(SPRN_DBAT3U, 0x00000000);
 	mtspr(SPRN_DBAT3L, 0x00000000);
 	io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO);
 	io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 }
 static void ppc7d_restart(char *cmd)
 {
 	u32 data;
 	/* Disable GPP17 interrupt */
 	data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 	data &= ~(1 << PPC7D_RST_PIN);
 	mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
 	/* Configure MPP17 as GPP */
 	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
 	data &= ~(0x0000000f << 4);
 	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
 	/* Enable pin GPP17 for output */
 	data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
 	data |= (1 << PPC7D_RST_PIN);
 	mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
 	/* Toggle GPP9 pin to reset the board */
 	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN);
 	mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN);
 	for (;;) ;		/* Spin until reset happens */
 	/* NOTREACHED */
 }
 static void ppc7d_power_off(void)
 {
 	u32 data;
 	local_irq_disable();
 	/* Ensure that internal MV643XX watchdog is disabled.
 	 * The Disco watchdog uses MPP17 on this hardware.
 	 */
 	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
 	data &= ~(0x0000000f << 4);
 	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
 	data = mv64x60_read(&bh, MV64x60_WDT_WDC);
 	if (data & 0x80000000) {
 		mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24);
 		mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24);
 	}
 	for (;;) ;		/* No way to shut power off with software */
 	/* NOTREACHED */
 }
 static void ppc7d_halt(void)
 {
 	ppc7d_power_off();
 	/* NOTREACHED */
 }
 static unsigned long ppc7d_led_no_pulse;
 static int __init ppc7d_led_pulse_disable(char *str)
 {
 	ppc7d_led_no_pulse = 1;
 	return 1;
 }
 /* This kernel option disables the heartbeat pulsing of a board LED */
 __setup("ledoff", ppc7d_led_pulse_disable);
 static void ppc7d_heartbeat(void)
 {
 	u32 data32;
 	u8 data8;
 	static int max706_wdog = 0;
 	/* Unfortunately we can't access the LED control registers
 	 * during early init because they're on the CPLD which is the
 	 * other side of a PCI bridge which goes unreachable during
 	 * PCI scan. So write the LEDs only if the MV64360 watchdog is
 	 * enabled (i.e. userspace apps are running so kernel is up)..
 	 */
 	data32 = mv64x60_read(&bh, MV64x60_WDT_WDC);
 	if (data32 & 0x80000000) {
 		/* Enable MAX706 watchdog if not done already */
 		if (!max706_wdog) {
 			outb(3, PPC7D_CPLD_RESET);
 			max706_wdog = 1;
 		}
 		/* Hit the MAX706 watchdog */
 		outb(0, PPC7D_CPLD_WATCHDOG_TRIG);
 		/* Pulse LED DS219 if not disabled */
 		if (!ppc7d_led_no_pulse) {
 			static int led_on = 0;
 			data8 = inb(PPC7D_CPLD_LEDS);
 			if (led_on)
 				data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK;
 			else
 				data8 |= PPC7D_CPLD_LEDS_DS219_MASK;
 			outb(data8, PPC7D_CPLD_LEDS);
 			led_on = !led_on;
 		}
 	}
 	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
 }
 static int ppc7d_show_cpuinfo(struct seq_file *m)
 {
 	u8 val;
 	u8 val1, val2;
 	static int flash_sizes[4] = { 64, 32, 0, 16 };
 	static int flash_banks[4] = { 4, 3, 2, 1 };
 	static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
 	int sdram_num_banks = 2;
 	static char *pci_modes[] = { "PCI33", "PCI66",
 		"Unknown", "Unknown",
 		"PCIX33", "PCIX66",
 		"PCIX100", "PCIX133"
 	};
 	seq_printf(m, "vendor\t\t: Radstone Technology\n");
 	seq_printf(m, "machine\t\t: PPC7D\n");
 	val = inb(PPC7D_CPLD_BOARD_REVISION);
 	val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
 	val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK);
 	seq_printf(m, "revision\t: %hd%c%c\n",
 		   val1,
 		   (val2 <= 0x18) ? 'A' + val2 : 'Y',
 		   (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' ');
 	val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE);
 	val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK;
 	val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK |
 		      PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK);
 	seq_printf(m, "bus speed\t: %dMHz\n",
 		   (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 :
 		   (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
 		   (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
 	val = inb(PPC7D_CPLD_MEM_CONFIG);
 	if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
 	val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
 	val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
 	seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
 		   sdram_num_banks,
 		   sdram_bank_sizes[val1],
 		   (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
 		   sdram_num_banks * sdram_bank_sizes[val1],
 		   (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
 	if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
 		seq_printf(m, " [ECC %sabled]",
 			   (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
 			   "dis");
 	}
 	seq_printf(m, "\n");
 	val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK);
 	val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2;
 	seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n",
 		   flash_banks[val2], flash_sizes[val1],
 		   flash_banks[val2] * flash_sizes[val1]);
 	val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL);
 	val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
 	seq_printf(m, "  write links\t: %s%s%s%s\n",
 		   (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "",
 		   (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
 			   PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
 			   PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) ==
 		   0 ? "NONE" : "");
 	seq_printf(m, "  write sector h/w enables: %s%s%s%s%s\n",
 		   (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " :
 		   "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "",
 		   (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " :
 		   "",
 		   (((val &
 		      (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK |
 		       PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK |
 		       PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0)
 		    && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ==
 			0)) ? "NONE" : "");
 	val1 =
 	    inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) &
 	    (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK |
 	     PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK);
 	seq_printf(m, "  software sector enables: %s%s%s\n",
 		   (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT "
 		   : "",
 		   (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "",
 		   (val1 == 0) ? "NONE " : "");
 	seq_printf(m, "Boot options\t: %s%s%s%s\n",
 		   (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ?
 		   "ALTERNATE " : "",
 		   (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " :
 		   "",
 		   (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY "
 		   : "",
 		   ((val &
 		     (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK |
 		      PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK |
 		      PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) ==
 		    0) ? "NONE" : "");
 	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1);
 	seq_printf(m, "Fitted modules\t: %s%s%s%s\n",
 		   (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ",
 		   (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ",
 		   (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "",
 		   ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
 			    PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK |
 			    PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) ==
 		    (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
 		     PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : "");
 	if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) {
 		static const char *ids[] = {
 			"unknown",
 			"1553 (Dual Channel)",
 			"1553 (Single Channel)",
 			"8-bit SCSI + VGA",
 			"16-bit SCSI + VGA",
 			"1553 (Single Channel with sideband)",
 			"1553 (Dual Channel with sideband)",
 			NULL
 		};
 		u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03);
 		seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id,
 			   id < 7 ? ids[id] : "unknown");
 	}
 	val = inb(PPC7D_CPLD_PCI_CONFIG);
 	val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4;
 	val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK);
 	seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
 		   pci_modes[val1], pci_modes[val2]);
 	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
 	seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
 		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v",
 		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v");
 	seq_printf(m, "PMC power source: %s\n",
 		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" :
 		   "internal");
 	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4);
 	val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
 	seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n",
 		   (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "",
 		   (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "",
 		   (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "",
 		   (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "",
 		   (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "",
 		   (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "",
 		   (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " :
 		   "");
 	val = inb(PPC7D_CPLD_ID_LINK);
 	val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK |
 		      PPC7D_CPLD_ID_LINK_E7_MASK |
 		      PPC7D_CPLD_ID_LINK_E12_MASK |
 		      PPC7D_CPLD_ID_LINK_E13_MASK);
 	val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) &
 	    (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
 	     PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
 	     PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK);
 	seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n",
 		   (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "",
 		   (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "",
 		   (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "",
 		   (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "",
 		   (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "",
 		   ((val == 0) && (val1 == 0)) ? "NONE" : "");
 	val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK);
 	seq_printf(m, "Front panel reset switch: %sabled\n",
 		   (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en");
 	return 0;
 }
 static void __init ppc7d_calibrate_decr(void)
 {
 	ulong freq;
 	freq = 100000000 / 4;
 	pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
 		 freq / 1000000, freq % 1000000);
 	tb_ticks_per_jiffy = freq / HZ;
 	tb_to_us = mulhwu_scale_factor(freq, 1000000);
 }
 /*****************************************************************************
  * Interrupt stuff
  *****************************************************************************/
 static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id)
 {
 	u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
 	if (temp & (1 << 28)) {
 		i8259_irq();
 		mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 /*
  * Each interrupt cause is assigned an IRQ number.
  * Southbridge has 16*2 (two 8259's) interrupts.
  * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
  * If multiple interrupts are pending, get_irq() returns the
  * lowest pending irq number first.
  *
  *
  * IRQ #   Source                              Trig   Active
  * =============================================================
  *
  * Southbridge
  * -----------
  * IRQ #   Source                              Trig
  * =============================================================
  * 0       ISA High Resolution Counter         Edge
  * 1       Keyboard                            Edge
  * 2       Cascade From (IRQ 8-15)             Edge
  * 3       Com 2 (Uart 2)                      Edge
  * 4       Com 1 (Uart 1)                      Edge
  * 5       PCI Int D/AFIX IRQZ ID4 (2,7)       Level
  * 6       GPIO                                Level
  * 7       LPT                                 Edge
  * 8       RTC Alarm                           Edge
  * 9       PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
  * 10      PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
  * 11      USB2                                Level
  * 12      Mouse                               Edge
  * 13      Reserved internally by Ali M1535+
  * 14      PCI Int C/VME/AFIX IRQY ID3 (2,6)   Level
  * 15      COM 5/6                             Level
  *
  * 16..112 Discovery-II...
  *
  * MPP28   Southbridge                         Edge   High
  *
  *
  * Interrupts are cascaded through to the Discovery-II.
  *
  *  PCI ---
  *         \
  * CPLD --> ALI1535 -------> DISCOVERY-II
  *        INTF           MPP28
  */
 static void __init ppc7d_init_irq(void)
 {
 	int irq;
 	pr_debug("%s\n", __FUNCTION__);
 	i8259_init(0, 0);
 	mv64360_init_irq();
 	/* IRQs 5,6,9,10,11,14,15 are level sensitive */
 	irq_desc[5].status |= IRQ_LEVEL;
 	irq_desc[6].status |= IRQ_LEVEL;
 	irq_desc[9].status |= IRQ_LEVEL;
 	irq_desc[10].status |= IRQ_LEVEL;
 	irq_desc[11].status |= IRQ_LEVEL;
 	irq_desc[14].status |= IRQ_LEVEL;
 	irq_desc[15].status |= IRQ_LEVEL;
 	/* GPP28 is edge triggered */
 	irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
 }
 static u32 ppc7d_irq_canonicalize(u32 irq)
 {
 	if ((irq >= 16) && (irq < (16 + 96)))
 		irq -= 16;
 	return irq;
 }
 static int ppc7d_get_irq(void)
 {
 	int irq;
 	irq = mv64360_get_irq();
 	if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
 		irq = i8259_irq();
 	return irq;
 }
 /*
  * 9       PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
  * 10      PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
  * 14      PCI Int C/VME/AFIX IRQY ID3 (2,6)   Level
  * 5       PCI Int D/AFIX IRQZ ID4 (2,7)       Level
  */
 static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
 				unsigned char pin)
 {
 	static const char pci_irq_table[][4] =
 	    /*
 	     *      PCI IDSEL/INTPIN->INTLINE
 	     *         A   B   C   D
 	     */
 	{
 		{10, 14, 5, 9},	/* IDSEL 10 - PMC2 / AFIX IRQW */
 		{9, 10, 14, 5},	/* IDSEL 11 - PMC1 / AFIX IRQX */
 		{5, 9, 10, 14},	/* IDSEL 12 - AFIX IRQY */
 		{14, 5, 9, 10},	/* IDSEL 13 - AFIX IRQZ */
 	};
 	const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
 	pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__,
 		 dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 void __init ppc7d_intr_setup(void)
 {
 	u32 data;
 	/*
 	 * Define GPP 28 interrupt polarity as active high
 	 * input signal and level triggered
 	 */
 	data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
 	data &= ~(1 << 28);
 	mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
 	data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
 	data &= ~(1 << 28);
 	mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
 	/* Config GPP intr ctlr to respond to level trigger */
 	data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
 	data |= (1 << 10);
 	mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);
 	/* XXXX Erranum FEr PCI-#8 */
 	data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
 	data &= ~((1 << 5) | (1 << 9));
 	mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
 	data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
 	data &= ~((1 << 5) | (1 << 9));
 	mv64x60_write(&bh, MV64x60_PCI1_CMD, data);
 	/*
 	 * Dismiss and then enable interrupt on GPP interrupt cause
 	 * for CPU #0
 	 */
 	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
 	data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 	data |= (1 << 28);
 	mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
 	/*
 	 * Dismiss and then enable interrupt on CPU #0 high cause reg
 	 * BIT27 summarizes GPP interrupts 23-31
 	 */
 	mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
 	data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
 	data |= (1 << 27);
 	mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
 }
 /*****************************************************************************
  * Platform device data fixup routines.
  *****************************************************************************/
 #if defined(CONFIG_SERIAL_MPSC)
 static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev)
 {
 	struct mpsc_pdata *pdata;
 	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 	pdata->max_idle = 40;
 	pdata->default_baud = PPC7D_DEFAULT_BAUD;
 	pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC;
 	pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ;
 	return;
 }
 #endif
 #if defined(CONFIG_MV643XX_ETH)
 static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev)
 {
 	struct mv643xx_eth_platform_data *eth_pd;
 	static u16 phy_addr[] = {
 		PPC7D_ETH0_PHY_ADDR,
 		PPC7D_ETH1_PHY_ADDR,
 		PPC7D_ETH2_PHY_ADDR,
 	};
 	int i;
 	eth_pd = pdev->dev.platform_data;
 	eth_pd->force_phy_addr = 1;
 	eth_pd->phy_addr = phy_addr[pdev->id];
 	eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE;
 	eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE;
 	/* Adjust IRQ by mv64360_irq_base */
 	for (i = 0; i < pdev->num_resources; i++) {
 		struct resource *r = &pdev->resource[i];
 		if (r->flags & IORESOURCE_IRQ) {
 			r->start += mv64360_irq_base;
 			r->end += mv64360_irq_base;
 			pr_debug("%s, uses IRQ %d\n", pdev->name,
 				 (int)r->start);
 		}
 	}
 }
 #endif
 #if defined(CONFIG_I2C_MV64XXX)
 static void __init
 ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
 {
 	struct mv64xxx_i2c_pdata *pdata;
 	int i;
 	pdata = pdev->dev.platform_data;
 	if (pdata == NULL) {
 		pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 		if (pdata == NULL)
 			return;
 		pdev->dev.platform_data = pdata;
 	}
 	/* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
 	pdata->freq_m = 8;
 	pdata->freq_n = 3;
 	pdata->timeout = 500;
 	pdata->retries = 3;
 	/* Adjust IRQ by mv64360_irq_base */
 	for (i = 0; i < pdev->num_resources; i++) {
 		struct resource *r = &pdev->resource[i];
 		if (r->flags & IORESOURCE_IRQ) {
 			r->start += mv64360_irq_base;
 			r->end += mv64360_irq_base;
 			pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
 		}
 	}
 }
 #endif
 static int ppc7d_platform_notify(struct device *dev)
 {
 	static struct {
 		char *bus_id;
 		void ((*rtn) (struct platform_device * pdev));
 	} dev_map[] = {
 #if defined(CONFIG_SERIAL_MPSC)
 		{ MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
 		{ MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
 #endif
 #if defined(CONFIG_MV643XX_ETH)
 		{ MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
 		{ MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
 		{ MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
 #endif
 #if defined(CONFIG_I2C_MV64XXX)
 		{ MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
 #endif
 	};
 	struct platform_device *pdev;
 	int i;
 	if (dev && dev->bus_id)
 		for (i = 0; i < ARRAY_SIZE(dev_map); i++)
 			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 				     BUS_ID_SIZE)) {
 				pdev = container_of(dev,
 						    struct platform_device,
 						    dev);
 				dev_map[i].rtn(pdev);
 			}
 	return 0;
 }
 /*****************************************************************************
  * PCI device fixups.
  * These aren't really fixups per se. They are used to init devices as they
  * are found during PCI scan.
  *
  * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
  * scan in order to find other devices on its secondary side.
  *****************************************************************************/
 static void __init ppc7d_fixup_hb8(struct pci_dev *dev)
 {
 	u16 val16;
 	if (dev->bus->number == 0) {
 		pr_debug("PCI: HB8 init\n");
 		pci_write_config_byte(dev, 0x1c,
 				      ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000)
 				       >> 8) | 0x01);
 		pci_write_config_byte(dev, 0x1d,
 				      (((PPC7D_PCI0_IO_START_PCI_ADDR +
 					 PPC7D_PCI0_IO_SIZE -
 					 1) & 0xf000) >> 8) | 0x01);
 		pci_write_config_word(dev, 0x30,
 				      PPC7D_PCI0_IO_START_PCI_ADDR >> 16);
 		pci_write_config_word(dev, 0x32,
 				      ((PPC7D_PCI0_IO_START_PCI_ADDR +
 					PPC7D_PCI0_IO_SIZE -
 					1) >> 16) & 0xffff);
 		pci_write_config_word(dev, 0x20,
 				      PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16);
 		pci_write_config_word(dev, 0x22,
 				      ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR +
 					PPC7D_PCI0_MEM0_SIZE -
 					1) >> 16) & 0xffff);
 		pci_write_config_word(dev, 0x24, 0);
 		pci_write_config_word(dev, 0x26, 0);
 		pci_write_config_dword(dev, 0x28, 0);
 		pci_write_config_dword(dev, 0x2c, 0);
 		pci_read_config_word(dev, 0x3e, &val16);
 		val16 |= ((1 << 5) | (1 << 1));	/* signal master aborts and
 						 * SERR to primary
 						 */
 		val16 &= ~(1 << 2);		/* ISA disable, so all ISA
 						 * ports forwarded to secondary
 						 */
 		pci_write_config_word(dev, 0x3e, val16);
 	}
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8);
 /* This should perhaps be a separate driver as we're actually initializing
  * the chip for this board here. It's hardly a fixup...
  */
 static void __init ppc7d_fixup_ali1535(struct pci_dev *dev)
 {
 	pr_debug("PCI: ALI1535 init\n");
 	if (dev->bus->number == 1) {
 		/* Configure the ISA Port Settings */
 		pci_write_config_byte(dev, 0x43, 0x00);
 		/* Disable PCI Interrupt polling mode */
 		pci_write_config_byte(dev, 0x45, 0x00);
 		/* Multifunction pin select INTFJ -> INTF */
 		pci_write_config_byte(dev, 0x78, 0x00);
 		/* Set PCI INT -> IRQ Routing control in for external
 		 * pins south bridge.
 		 */
 		pci_write_config_byte(dev, 0x48, 0x31);	/* [7-4] INT B -> IRQ10
 							 * [3-0] INT A -> IRQ9
 							 */
 		pci_write_config_byte(dev, 0x49, 0x5D);	/* [7-4] INT D -> IRQ5
 							 * [3-0] INT C -> IRQ14
 							 */
 		/* PPC7D setup */
 		/* NEC USB device on IRQ 11 (INTE) - INTF disabled */
 		pci_write_config_byte(dev, 0x4A, 0x09);
 		/* GPIO on IRQ 6 */
 		pci_write_config_byte(dev, 0x76, 0x07);
 		/* SIRQ I (COMS 5/6) use IRQ line 15.
 		 * Positive (not subtractive) address decode.
 		 */
 		pci_write_config_byte(dev, 0x44, 0x0f);
 		/* SIRQ II disabled */
 		pci_write_config_byte(dev, 0x75, 0x0);
 		/* On board USB and RTC disabled */
 		pci_write_config_word(dev, 0x52, (1 << 14));
 		pci_write_config_byte(dev, 0x74, 0x00);
 		/* On board IDE disabled */
 		pci_write_config_byte(dev, 0x58, 0x00);
 		/* Decode 32-bit addresses */
 		pci_write_config_byte(dev, 0x5b, 0);
 		/* Disable docking IO */
 		pci_write_config_word(dev, 0x5c, 0x0000);
 		/* Disable modem, enable sound */
 		pci_write_config_byte(dev, 0x77, (1 << 6));
 		/* Disable hot-docking mode */
 		pci_write_config_byte(dev, 0x7d, 0x00);
 	}
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535);
 static int ppc7d_pci_exclude_device(u8 bus, u8 devfn)
 {
 	/* Early versions of this board were fitted with IBM ALMA
 	 * PCI-VME bridge chips. The PCI config space of these devices
 	 * was not set up correctly and causes PCI scan problems.
 	 */
 	if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	return mv64x60_pci_exclude_device(bus, devfn);
 }
 /* This hook is called when each PCI bus is probed.
  */
 static void ppc7d_pci_fixup_bus(struct pci_bus *bus)
 {
 	pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
 		 bus->number,
 		 bus->resource[0] ? bus->resource[0]->start : 0,
 		 bus->resource[0] ? bus->resource[0]->end : 0,
 		 bus->resource[1] ? bus->resource[1]->start : 0,
 		 bus->resource[1] ? bus->resource[1]->end : 0,
 		 bus->resource[2] ? bus->resource[2]->start : 0,
 		 bus->resource[2] ? bus->resource[2]->end : 0,
 		 bus->resource[3] ? bus->resource[3]->start : 0,
 		 bus->resource[3] ? bus->resource[3]->end : 0);
 	if ((bus->number == 1) && (bus->resource[2] != NULL)) {
 		/* Hide PCI window 2 of Bus 1 which is used only to
 		 * map legacy ISA memory space.
 		 */
 		bus->resource[2]->start = 0;
 		bus->resource[2]->end = 0;
 		bus->resource[2]->flags = 0;
 	}
 }
 /*****************************************************************************
  * Board device setup code
  *****************************************************************************/
 void __init ppc7d_setup_peripherals(void)
 {
 	u32 val32;
 	/* Set up windows for boot CS */
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 				 PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE,
 				 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 	/* Boot firmware configures the following DevCS addresses.
 	 * DevCS0 - board control/status
 	 * DevCS1 - test registers
 	 * DevCS2 - AFIX port/address registers (for identifying)
 	 * DevCS3 - FLASH
 	 *
 	 * We don't use DevCS0, DevCS1.
 	 */
 	val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE);
 	val32 |= ((1 << 4) | (1 << 5));
 	mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32);
 	mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0);
 	mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0);
 	mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0);
 	mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 				 PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 				 PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 				 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
 				 0);
 	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 	/* Set up Enet->SRAM window */
 	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
 				 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
 				 0x2);
 	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 	/* Give enet r/w access to memory region */
 	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0);
 	val32 |= (0x3 << (4 << 1));
 	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32);
 	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1);
 	val32 |= (0x3 << (4 << 1));
 	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32);
 	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2);
 	val32 |= (0x3 << (4 << 1));
 	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32);
 	val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL);
 	val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
 	mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32);
 	/* Enumerate pci bus.
 	 *
 	 * We scan PCI#0 first (the bus with the HB8 and other
 	 * on-board peripherals). We must configure the 64360 before
 	 * each scan, according to the bus number assignments.  Busses
 	 * are assigned incrementally, starting at 0.  PCI#0 is
 	 * usually assigned bus#0, the secondary side of the HB8 gets
 	 * bus#1 and PCI#1 (second PMC site) gets bus#2.  However, if
 	 * any PMC card has a PCI bridge, these bus assignments will
 	 * change.
 	 */
 	/* Turn off PCI retries */
 	val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
 	val32 |= (1 << 17);
 	mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
 	/* Scan PCI#0 */
 	mv64x60_set_bus(&bh, 0, 0);
 	bh.hose_a->first_busno = 0;
 	bh.hose_a->last_busno = 0xff;
 	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 	printk(KERN_INFO "PCI#0: first=%d last=%d\n",
 	       bh.hose_a->first_busno, bh.hose_a->last_busno);
 	/* Scan PCI#1 */
 	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
 	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
 	bh.hose_b->last_busno = 0xff;
 	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
 		bh.hose_b->first_busno);
 	printk(KERN_INFO "PCI#1: first=%d last=%d\n",
 	       bh.hose_b->first_busno, bh.hose_b->last_busno);
 	/* Turn on PCI retries */
 	val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
 	val32 &= ~(1 << 17);
 	mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
 	/* Setup interrupts */
 	ppc7d_intr_setup();
 }
 static void __init ppc7d_setup_bridge(void)
 {
 	struct mv64x60_setup_info si;
 	int i;
 	u32 temp;
 	mv64360_irq_base = 16;	/* first 16 intrs are 2 x 8259's */
 	memset(&si, 0, sizeof(si));
 	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 	si.pci_0.enable_bus = 1;
 	si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR;
 	si.pci_0.pci_io.pci_base_hi = 0;
 	si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR;
 	si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE;
 	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR;
 	si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR;
 	si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
 	si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE;
 	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR;
 	si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR;
 	si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR;
 	si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE;
 	si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_0.pci_cmd_bits = 0;
 	si.pci_0.latency_timer = 0x80;
 	si.pci_1.enable_bus = 1;
 	si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR;
 	si.pci_1.pci_io.pci_base_hi = 0;
 	si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR;
 	si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE;
 	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR;
 	si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR;
 	si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
 	si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE;
 	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR;
 	si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR;
 	si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR;
 	si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE;
 	si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
 	si.pci_1.pci_cmd_bits = 0;
 	si.pci_1.latency_timer = 0x80;
 	/* Don't clear the SRAM window since we use it for debug */
 	si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN);
 	printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n",
 	       si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size);
 	printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n",
 	       si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size);
 	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
 #if defined(CONFIG_NOT_COHERENT_CACHE)
 		si.cpu_prot_options[i] = 0;
 		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 		si.pci_0.acc_cntl_options[i] =
 		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
 		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 		si.pci_1.acc_cntl_options[i] =
 		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
 		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 #else
 		si.cpu_prot_options[i] = 0;
 		/* All PPC7D hardware uses B0 or newer MV64360 silicon which
 		 * does not have snoop bugs.
 		 */
 		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
 		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
 		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
 		si.pci_0.acc_cntl_options[i] =
 		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
 		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
 		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 		si.pci_1.acc_cntl_options[i] =
 		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
 		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
 		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 #endif
 	}
 	/* Lookup PCI host bridges */
 	if (mv64x60_init(&bh, &si))
 		printk(KERN_ERR "MV64360 initialization failed.\n");
 	pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base);
 	/* Enable WB Cache coherency on SRAM */
 	temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG);
 	pr_debug("SRAM_CONFIG: %x\n", temp);
 #if defined(CONFIG_NOT_COHERENT_CACHE)
 	mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2);
 #else
 	mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2);
 #endif
 	/* If system operates with internal bus arbiter (CPU master
 	 * control bit8) clear AACK Delay bit [25] in CPU
 	 * configuration register.
 	 */
 	temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL);
 	if (temp & (1 << 8)) {
 		temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
 		mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25)));
 	}
 	/* Data and address parity is enabled */
 	temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
 	mv64x60_write(&bh, MV64x60_CPU_CONFIG,
 		      (temp | (1 << 26) | (1 << 19)));
 	pci_dram_offset = 0;	/* sys mem at same addr on PCI & cpu bus */
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = ppc7d_map_irq;
 	ppc_md.pci_exclude_device = ppc7d_pci_exclude_device;
 	mv64x60_set_bus(&bh, 0, 0);
 	bh.hose_a->first_busno = 0;
 	bh.hose_a->last_busno = 0xff;
 	bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
 	bh.hose_a->mem_space.end =
 	    PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE;
 	/* These will be set later, as a result of PCI0 scan */
 	bh.hose_b->first_busno = 0;
 	bh.hose_b->last_busno = 0xff;
 	bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
 	bh.hose_b->mem_space.end =
 	    PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE;
 	pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
 		 mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50),
 		 mv64x60_read(&bh, 0xf0));
 }
 static void __init ppc7d_setup_arch(void)
 {
 	int port;
 	loops_per_jiffy = 100000000 / HZ;
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef	CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_HDA1;
 #endif
 	if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) ||
 	    (cur_cpu_spec->cpu_features & CPU_FTR_L3CR))
 		/* 745x is different.  We only want to pass along enable. */
 		_set_L2CR(L2CR_L2E);
 	else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR)
 		/* All modules have 1MB of L2.  We also assume that an
 		 * L2 divisor of 3 will work.
 		 */
 		_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
 			  | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
 	if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)
 		/* No L3 cache */
 		_set_L3CR(0);
 #ifdef CONFIG_DUMMY_CONSOLE
 	conswitchp = &dummy_con;
 #endif
 	/* Lookup PCI host bridges */
 	if (ppc_md.progress)
 		ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0);
 	ppc7d_setup_bridge();
 	ppc7d_setup_peripherals();
 	/* Disable ethernet. It might have been setup by the bootrom */
 	for (port = 0; port < 3; port++)
 		mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
 			      0x0000ff00);
 	/* Clear queue pointers to ensure they are all initialized,
 	 * otherwise since queues 1-7 are unused, they have random
 	 * pointers which look strange in register dumps. Don't bother
 	 * with queue 0 since it will be initialized later.
 	 */
 	for (port = 0; port < 3; port++) {
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
 			      0x00000000);
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
 			      0x00000000);
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
 			      0x00000000);
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
 			      0x00000000);
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
 			      0x00000000);
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
 			      0x00000000);
 		mv64x60_write(&bh,
 			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
 			      0x00000000);
 	}
 	printk(KERN_INFO "Radstone Technology PPC7D\n");
 	if (ppc_md.progress)
 		ppc_md.progress("ppc7d_setup_arch: exit", 0);
 }
 /* Real Time Clock support.
  * PPC7D has a DS1337 accessed by I2C.
  */
 static ulong ppc7d_get_rtc_time(void)
 {
         struct rtc_time tm;
         int result;
         spin_lock(&rtc_lock);
         result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
         spin_unlock(&rtc_lock);
         if (result == 0)
                 result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
         return result;
 }
 static int ppc7d_set_rtc_time(unsigned long nowtime)
 {
         struct rtc_time tm;
         int result;
         spin_lock(&rtc_lock);
         to_tm(nowtime, &tm);
         result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
         spin_unlock(&rtc_lock);
         return result;
 }
 /* This kernel command line parameter can be used to have the target
  * wait for a JTAG debugger to attach. Of course, a JTAG debugger
  * with hardware breakpoint support can have the target stop at any
  * location during init, but this is a convenience feature that makes
  * it easier in the common case of loading the code using the ppcboot
  * bootloader..
  */
 static unsigned long ppc7d_wait_debugger;
 static int __init ppc7d_waitdbg(char *str)
 {
 	ppc7d_wait_debugger = 1;
 	return 1;
 }
 __setup("waitdbg", ppc7d_waitdbg);
 /* Second phase board init, called after other (architecture common)
  * low-level services have been initialized.
  */
 static void ppc7d_init2(void)
 {
 	unsigned long flags;
 	u32 data;
 	u8 data8;
 	pr_debug("%s: enter\n", __FUNCTION__);
 	/* Wait for debugger? */
 	if (ppc7d_wait_debugger) {
 		printk("Waiting for debugger...\n");
 		while (readl(&ppc7d_wait_debugger)) ;
 	}
 	/* Hook up i8259 interrupt which is connected to GPP28 */
 	request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr,
 		    IRQF_DISABLED, "I8259 (GPP28) interrupt", (void *)0);
 	/* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
 	spin_lock_irqsave(&mv64x60_lock, flags);
 	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
 	data &= ~(0x0000000f << 0);
 	data |= (0x00000004 << 0);
 	data &= ~(0x0000000f << 4);
 	data |= (0x00000004 << 4);
 	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
 	spin_unlock_irqrestore(&mv64x60_lock, flags);
 	/* All LEDs off */
 	data8 = inb(PPC7D_CPLD_LEDS);
 	data8 &= ~0x08;
 	data8 |= 0x07;
 	outb(data8, PPC7D_CPLD_LEDS);
         /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
         ppc_md.set_rtc_time = ppc7d_set_rtc_time;
         ppc_md.get_rtc_time = ppc7d_get_rtc_time;
 	pr_debug("%s: exit\n", __FUNCTION__);
 }
 /* Called from machine_init(), early, before any of the __init functions
  * have run. We must init software-configurable pins before other functions
  * such as interrupt controllers are initialised.
  */
 void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 			  unsigned long r6, unsigned long r7)
 {
 	u8 val8;
 	u8 rev_num;
 	/* Map 0xe0000000-0xffffffff early because we need access to SRAM
 	 * and the ISA memory space (for serial port) here. This mapping
 	 * is redone properly in ppc7d_map_io() later.
 	 */
 	mtspr(SPRN_DBAT3U, 0xe0003fff);
 	mtspr(SPRN_DBAT3L, 0xe000002a);
 	/*
 	 * Zero SRAM. Note that this generates parity errors on
 	 * internal data path in SRAM if it's first time accessing it
 	 * after reset.
 	 *
 	 * We do this ASAP to avoid parity errors when reading
 	 * uninitialized SRAM.
 	 */
 	memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);
 	pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
 		 r3, r4, r5, r6, r7);
 	parse_bootinfo(find_bootinfo());
 	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 	 * are non-zero, then we should use the board info from the bd_t
 	 * structure and the cmdline pointed to by r6 instead of the
 	 * information from birecs, if any.  Otherwise, use the information
 	 * from birecs as discovered by the preceding call to
 	 * parse_bootinfo().  This rule should work with both PPCBoot, which
 	 * uses a bd_t board info structure, and the kernel boot wrapper,
 	 * which uses birecs.
 	 */
 	if (r3 && r6) {
 		bd_t *bp = (bd_t *) __res;
 		/* copy board info structure */
 		memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
 		/* copy command line */
 		*(char *)(r7 + KERNELBASE) = 0;
 		strcpy(cmd_line, (char *)(r6 + KERNELBASE));
 		printk(KERN_INFO "Board info data:-\n");
 		printk(KERN_INFO "  Internal freq: %lu MHz, bus freq: %lu MHz\n",
 		       bp->bi_intfreq, bp->bi_busfreq);
 		printk(KERN_INFO "  Memory: %lx, size %lx\n", bp->bi_memstart,
 		       bp->bi_memsize);
 		printk(KERN_INFO "  Console baudrate: %lu\n", bp->bi_baudrate);
 		printk(KERN_INFO "  Ethernet address: "
 		       "%02x:%02x:%02x:%02x:%02x:%02x\n",
 		       bp->bi_enetaddr[0], bp->bi_enetaddr[1],
 		       bp->bi_enetaddr[2], bp->bi_enetaddr[3],
 		       bp->bi_enetaddr[4], bp->bi_enetaddr[5]);
 	}
 #ifdef CONFIG_BLK_DEV_INITRD
 	/* take care of initrd if we have one */
 	if (r4) {
 		initrd_start = r4 + KERNELBASE;
 		initrd_end = r5 + KERNELBASE;
 		printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);
 	}
 #endif /* CONFIG_BLK_DEV_INITRD */
 	/* Map in board regs, etc. */
 	isa_io_base = 0xe8000000;
 	isa_mem_base = 0xe8000000;
 	pci_dram_offset = 0x00000000;
 	ISA_DMA_THRESHOLD = 0x00ffffff;
 	DMA_MODE_READ = 0x44;
 	DMA_MODE_WRITE = 0x48;
 	ppc_md.setup_arch = ppc7d_setup_arch;
 	ppc_md.init = ppc7d_init2;
 	ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;
 	/* XXX this is broken... */
 	ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;
 	ppc_md.init_IRQ = ppc7d_init_irq;
 	ppc_md.get_irq = ppc7d_get_irq;
 	ppc_md.restart = ppc7d_restart;
 	ppc_md.power_off = ppc7d_power_off;
 	ppc_md.halt = ppc7d_halt;
 	ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;
 	ppc_md.setup_io_mappings = ppc7d_map_io;
 	ppc_md.time_init = NULL;
 	ppc_md.set_rtc_time = NULL;
 	ppc_md.get_rtc_time = NULL;
 	ppc_md.calibrate_decr = ppc7d_calibrate_decr;
 	ppc_md.nvram_read_val = NULL;
 	ppc_md.nvram_write_val = NULL;
 	ppc_md.heartbeat = ppc7d_heartbeat;
 	ppc_md.heartbeat_reset = HZ;
 	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
 	ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
     defined(CONFIG_I2C_MV64XXX)
 	platform_notify = ppc7d_platform_notify;
 #endif
 #ifdef CONFIG_SERIAL_MPSC
 	/* On PPC7D, we must configure MPSC support via CPLD control
 	 * registers.
 	 */
 	outb(PPC7D_CPLD_RTS_COM4_SCLK |
 	     PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);
 	outb(PPC7D_CPLD_COMS_COM3_TCLKEN |
 	     PPC7D_CPLD_COMS_COM3_TXEN |
 	     PPC7D_CPLD_COMS_COM4_TCLKEN |
 	     PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);
 #endif /* CONFIG_SERIAL_MPSC */
 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
 	ppc7d_early_serial_map();
 #ifdef  CONFIG_SERIAL_TEXT_DEBUG
 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
 	ppc_md.progress = mv64x60_mpsc_progress;
 #elif defined(CONFIG_SERIAL_8250)
 	ppc_md.progress = gen550_progress;
 #else
 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
 #endif /* CONFIG_SERIAL_8250 */
 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
 	/* Enable write access to user flash.  This is necessary for
 	 * flash probe.
 	 */
 	val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
 	writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &
 		       PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),
 	       (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
 	/* Determine if this board has IBM ALMA VME devices */
 	val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);
 	rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
 	if (rev_num <= 1)
 		ppc7d_has_alma = 1;
 #ifdef DEBUG
 	console_printk[0] = 8;
 #endif
 }

arch/ppc/platforms/spruce.c

Diff comments View file @ b187f18

 /*
  * Board and PCI setup routines for IBM Spruce
  *
  * Author: MontaVista Software <source@mvista.com>
  *
  * 2000-2004 (c) MontaVista, Software, Inc.  This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
 #include <linux/pci.h>
 #include <linux/kdev_t.h>
 #include <linux/types.h>
 #include <linux/major.h>
 #include <linux/initrd.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/seq_file.h>
 #include <linux/ide.h>
 #include <linux/root_dev.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
 #include <asm/time.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/kgdb.h>
 #include <syslib/cpc700.h>
 #include "spruce.h"
 static inline int
 spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
 		/*
 		 * 	PCI IDSEL/INTPIN->INTLINE
 		 * 	A	B	C	D
 		 */
 	{
 		{23, 24, 25, 26},	/* IDSEL 1 - PCI slot 3 */
 		{24, 25, 26, 23},	/* IDSEL 2 - PCI slot 2 */
 		{25, 26, 23, 24},	/* IDSEL 3 - PCI slot 1 */
 		{26, 23, 24, 25},	/* IDSEL 4 - PCI slot 0 */
 	};
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
 }
 static void __init
 spruce_setup_hose(void)
 {
 	struct pci_controller *hose;
 	/* Setup hose */
 	hose = pcibios_alloc_controller();
 	if (!hose)
 		return;
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 	pci_init_resource(&hose->io_resource,
 			SPRUCE_PCI_LOWER_IO,
 			SPRUCE_PCI_UPPER_IO,
 			IORESOURCE_IO,
 			"PCI host bridge");
 	pci_init_resource(&hose->mem_resources[0],
 			SPRUCE_PCI_LOWER_MEM,
 			SPRUCE_PCI_UPPER_MEM,
 			IORESOURCE_MEM,
 			"PCI host bridge");
 	hose->io_space.start = SPRUCE_PCI_LOWER_IO;
 	hose->io_space.end = SPRUCE_PCI_UPPER_IO;
 	hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
 	hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
 	hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
 	setup_indirect_pci(hose,
 			SPRUCE_PCI_CONFIG_ADDR,
 			SPRUCE_PCI_CONFIG_DATA);
 	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 	ppc_md.pci_swizzle = common_swizzle;
 	ppc_md.pci_map_irq = spruce_map_irq;
 }
 /*
  * CPC700 PIC interrupt programming table
  *
  * First entry is the sensitivity (level/edge), second is the polarity.
  */
 unsigned int cpc700_irq_assigns[32][2] = {
 	{ 1, 1 },       /* IRQ  0: ECC Correctable Error - rising edge */
 	{ 1, 1 },       /* IRQ  1: PCI Write Mem Range   - rising edge */
 	{ 0, 1 },       /* IRQ  2: PCI Write Command Reg - active high */
 	{ 0, 1 },       /* IRQ  3: UART 0                - active high */
 	{ 0, 1 },       /* IRQ  4: UART 1                - active high */
 	{ 0, 1 },       /* IRQ  5: ICC 0                 - active high */
 	{ 0, 1 },       /* IRQ  6: ICC 1                 - active high */
 	{ 0, 1 },       /* IRQ  7: GPT Compare 0         - active high */
 	{ 0, 1 },       /* IRQ  8: GPT Compare 1         - active high */
 	{ 0, 1 },       /* IRQ  9: GPT Compare 2         - active high */
 	{ 0, 1 },       /* IRQ 10: GPT Compare 3         - active high */
 	{ 0, 1 },       /* IRQ 11: GPT Compare 4         - active high */
 	{ 0, 1 },       /* IRQ 12: GPT Capture 0         - active high */
 	{ 0, 1 },       /* IRQ 13: GPT Capture 1         - active high */
 	{ 0, 1 },       /* IRQ 14: GPT Capture 2         - active high */
 	{ 0, 1 },       /* IRQ 15: GPT Capture 3         - active high */
 	{ 0, 1 },       /* IRQ 16: GPT Capture 4         - active high */
 	{ 0, 0 },       /* IRQ 17: Reserved */
 	{ 0, 0 },       /* IRQ 18: Reserved */
 	{ 0, 0 },       /* IRQ 19: Reserved */
 	{ 0, 1 },       /* IRQ 20: FPGA EXT_IRQ0         - active high */
 	{ 1, 1 },       /* IRQ 21: Mouse                 - rising edge */
 	{ 1, 1 },       /* IRQ 22: Keyboard              - rising edge */
 	{ 0, 0 },       /* IRQ 23: PCI Slot 3            - active low */
 	{ 0, 0 },       /* IRQ 24: PCI Slot 2            - active low */
 	{ 0, 0 },       /* IRQ 25: PCI Slot 1            - active low */
 	{ 0, 0 },       /* IRQ 26: PCI Slot 0            - active low */
 };
 static void __init
 spruce_calibrate_decr(void)
 {
 	int freq, divisor = 4;
 	/* determine processor bus speed */
 	freq = SPRUCE_BUS_SPEED;
 	tb_ticks_per_jiffy = freq / HZ / divisor;
 	tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
 }
 static int
 spruce_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "vendor\t\t: IBM\n");
 	seq_printf(m, "machine\t\t: Spruce\n");
 	return 0;
 }
 static void __init
 spruce_early_serial_map(void)
 {
 	u32 uart_clk;
 	struct uart_port serial_req;
 	if (SPRUCE_UARTCLK_IS_33M(readb(SPRUCE_FPGA_REG_A)))
 		uart_clk = SPRUCE_BAUD_33M * 16;
 	else
 		uart_clk = SPRUCE_BAUD_30M * 16;
 	/* Setup serial port access */
 	memset(&serial_req, 0, sizeof(serial_req));
 	serial_req.uartclk = uart_clk;
 	serial_req.irq = UART0_INT;
 	serial_req.flags = UPF_BOOT_AUTOCONF;
 	serial_req.iotype = UPIO_MEM;
 	serial_req.membase = (u_char *)UART0_IO_BASE;
 	serial_req.regshift = 0;
 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
 	gen550_init(0, &serial_req);
 #endif
 #ifdef CONFIG_SERIAL_8250
 	if (early_serial_setup(&serial_req) != 0)
 		printk("Early serial init of port 0 failed\n");
 #endif
 	/* Assume early_serial_setup() doesn't modify serial_req */
 	serial_req.line = 1;
 	serial_req.irq = UART1_INT;
 	serial_req.membase = (u_char *)UART1_IO_BASE;
 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
 	gen550_init(1, &serial_req);
 #endif
 #ifdef CONFIG_SERIAL_8250
 	if (early_serial_setup(&serial_req) != 0)
 		printk("Early serial init of port 1 failed\n");
 #endif
 }
 TODC_ALLOC();
 static void __init
 spruce_setup_arch(void)
 {
 	/* Setup TODC access */
 	TODC_INIT(TODC_TYPE_DS1643, 0, 0, SPRUCE_RTC_BASE_ADDR, 8);
 	/* init to some ~sane value until calibrate_delay() runs */
 	loops_per_jiffy = 50000000 / HZ;
 	/* Setup PCI host bridge */
 	spruce_setup_hose();
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (initrd_start)
 		ROOT_DEV = Root_RAM0;
 	else
 #endif
 #ifdef CONFIG_ROOT_NFS
 		ROOT_DEV = Root_NFS;
 #else
 		ROOT_DEV = Root_SDA1;
 #endif
 	/* Identify the system */
 	printk(KERN_INFO "System Identification: IBM Spruce\n");
 	printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 }
 static void
 spruce_restart(char *cmd)
 {
 	local_irq_disable();
 	/* SRR0 has system reset vector, SRR1 has default MSR value */
 	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
 	__asm__ __volatile__
 	("\n\
 	lis	3,0xfff0	\n\
 	ori	3,3,0x0100	\n\
 	mtspr	26,3		\n\
 	li	3,0		\n\
 	mtspr	27,3		\n\
 	rfi			\n\
 	");
 	for(;;);
 }
 static void
 spruce_power_off(void)
 {
 	for(;;);
 }
 static void
 spruce_halt(void)
 {
 	spruce_restart(NULL);
 }
 static void __init
 spruce_map_io(void)
 {
 	io_block_mapping(SPRUCE_PCI_IO_BASE, SPRUCE_PCI_PHY_IO_BASE,
 			 0x08000000, _PAGE_IO);
 }
 /*
  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
  */
 static __inline__ void
 spruce_set_bat(void)
 {
 	mb();
 	mtspr(SPRN_DBAT1U, 0xf8000ffe);
 	mtspr(SPRN_DBAT1L, 0xf800002a);
 	mb();
 }
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
 {
 	parse_bootinfo(find_bootinfo());
 	/* Map in board regs, etc. */
 	spruce_set_bat();
 	isa_io_base = SPRUCE_ISA_IO_BASE;
 	pci_dram_offset = SPRUCE_PCI_SYS_MEM_BASE;
 	ppc_md.setup_arch = spruce_setup_arch;
 	ppc_md.show_cpuinfo = spruce_show_cpuinfo;
 	ppc_md.init_IRQ = cpc700_init_IRQ;
 	ppc_md.get_irq = cpc700_get_irq;
 	ppc_md.setup_io_mappings = spruce_map_io;
 	ppc_md.restart = spruce_restart;
 	ppc_md.power_off = spruce_power_off;
 	ppc_md.halt = spruce_halt;
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.calibrate_decr = spruce_calibrate_decr;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 	spruce_early_serial_map();
 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 	ppc_md.progress = gen550_progress;
 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
 #ifdef CONFIG_KGDB
 	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 #endif
 }

drivers/parisc/superio.c

Diff comments View file @ b187f18

 /*      National Semiconductor NS87560UBD Super I/O controller used in
  *      HP [BCJ]x000 workstations.
  *
  *      This chip is a horrid piece of engineering, and National
  *      denies any knowledge of its existence. Thus no datasheet is
  *      available off www.national.com.
  *
  *	(C) Copyright 2000 Linuxcare, Inc.
  * 	(C) Copyright 2000 Linuxcare Canada, Inc.
  *	(C) Copyright 2000 Martin K. Petersen <mkp@linuxcare.com>
  * 	(C) Copyright 2000 Alex deVries <alex@onefishtwo.ca>
  *      (C) Copyright 2001 John Marvin <jsm fc hp com>
  *      (C) Copyright 2003 Grant Grundler <grundler parisc-linux org>
  *	(C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org>
  *	(C) Copyright 2006 Helge Deller <deller@gmx.de>
  *
  *	This program is free software; you can redistribute it and/or
  *	modify it under the terms of the GNU General Public License as
  *	published by the Free Software Foundation; either version 2 of
  *	the License, or (at your option) any later version.
  *
  *	The initial version of this is by Martin Peterson.  Alex deVries
  *	has spent a bit of time trying to coax it into working.
  *
  *      Major changes to get basic interrupt infrastructure working to
  *      hopefully be able to support all SuperIO devices. Currently
  *      works with serial. -- John Marvin <jsm@fc.hp.com>
  *
  *	Converted superio_init() to be a PCI_FIXUP_FINAL callee.
  *         -- Kyle McMartin <kyle@parisc-linux.org>
  */
 /* NOTES:
  *
  * Function 0 is an IDE controller. It is identical to a PC87415 IDE
  * controller (and identifies itself as such).
  *
  * Function 1 is a "Legacy I/O" controller. Under this function is a
  * whole mess of legacy I/O peripherals. Of course, HP hasn't enabled
  * all the functionality in hardware, but the following is available:
  *
  *      Two 16550A compatible serial controllers
  *      An IEEE 1284 compatible parallel port
  *      A floppy disk controller
  *
  * Function 2 is a USB controller.
  *
  * We must be incredibly careful during initialization.  Since all
  * interrupts are routed through function 1 (which is not allowed by
  * the PCI spec), we need to program the PICs on the legacy I/O port
  * *before* we attempt to set up IDE and USB.  @#$!&
  *
  * According to HP, devices are only enabled by firmware if they have
  * a physical device connected.
  *
  * Configuration register bits:
  *     0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
  *     0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
  *
  */
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial.h>
 #include <linux/pci.h>
 #include <linux/parport.h>
 #include <linux/parport_pc.h>
 #include <linux/termios.h>
 #include <linux/tty.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/delay.h>
 #include <asm/io.h>
 #include <asm/hardware.h>
 #include <asm/superio.h>
 static struct superio_device sio_dev;
 #undef DEBUG_SUPERIO_INIT
 #ifdef DEBUG_SUPERIO_INIT
 #define DBG_INIT(x...)  printk(x)
 #else
 #define DBG_INIT(x...)
 #endif
 #define SUPERIO	"SuperIO"
 #define PFX	SUPERIO ": "
 static irqreturn_t
 superio_interrupt(int parent_irq, void *devp)
 {
 	u8 results;
 	u8 local_irq;
 	/* Poll the 8259 to see if there's an interrupt. */
 	outb (OCW3_POLL,IC_PIC1+0);
 	results = inb(IC_PIC1+0);
 	/*
 	 * Bit    7:	1 = active Interrupt; 0 = no Interrupt pending
 	 * Bits 6-3:	zero
 	 * Bits 2-0:	highest priority, active requesting interrupt ID (0-7)
 	 */
 	if ((results & 0x80) == 0) {
 		/* I suspect "spurious" interrupts are from unmasking an IRQ.
 		 * We don't know if an interrupt was/is pending and thus
 		 * just call the handler for that IRQ as if it were pending.
 		 */
 		return IRQ_NONE;
 	}
 	/* Check to see which device is interrupting */
 	local_irq = results & 0x0f;
 	if (local_irq == 2 || local_irq > 7) {
 		printk(KERN_ERR PFX "slave interrupted!\n");
 		return IRQ_HANDLED;
 	}
 	if (local_irq == 7) {
 		/* Could be spurious. Check in service bits */
 		outb(OCW3_ISR,IC_PIC1+0);
 		results = inb(IC_PIC1+0);
 		if ((results & 0x80) == 0) { /* if ISR7 not set: spurious */
 			printk(KERN_WARNING PFX "spurious interrupt!\n");
 			return IRQ_HANDLED;
 		}
 	}
 	/* Call the appropriate device's interrupt */
 	__do_IRQ(local_irq);
 	/* set EOI - forces a new interrupt if a lower priority device
 	 * still needs service.
 	 */
 	outb((OCW2_SEOI|local_irq),IC_PIC1 + 0);
 	return IRQ_HANDLED;
 }
 /* Initialize Super I/O device */
 static void
 superio_init(struct pci_dev *pcidev)
 {
 	struct superio_device *sio = &sio_dev;
 	struct pci_dev *pdev = sio->lio_pdev;
 	u16 word;
 	if (sio->suckyio_irq_enabled)
 		return;
 	BUG_ON(!pdev);
 	BUG_ON(!sio->usb_pdev);
 	/* use the IRQ iosapic found for USB INT D... */
 	pdev->irq = sio->usb_pdev->irq;
 	/* ...then properly fixup the USB to point at suckyio PIC */
 	sio->usb_pdev->irq = superio_fixup_irq(sio->usb_pdev);
 	printk(KERN_INFO PFX "Found NS87560 Legacy I/O device at %s (IRQ %i) \n",
 	       pci_name(pdev), pdev->irq);
 	pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base);
 	sio->sp1_base &= ~1;
 	printk(KERN_INFO PFX "Serial port 1 at 0x%x\n", sio->sp1_base);
 	pci_read_config_dword (pdev, SIO_SP2BAR, &sio->sp2_base);
 	sio->sp2_base &= ~1;
 	printk(KERN_INFO PFX "Serial port 2 at 0x%x\n", sio->sp2_base);
 	pci_read_config_dword (pdev, SIO_PPBAR, &sio->pp_base);
 	sio->pp_base &= ~1;
 	printk(KERN_INFO PFX "Parallel port at 0x%x\n", sio->pp_base);
 	pci_read_config_dword (pdev, SIO_FDCBAR, &sio->fdc_base);
 	sio->fdc_base &= ~1;
 	printk(KERN_INFO PFX "Floppy controller at 0x%x\n", sio->fdc_base);
 	pci_read_config_dword (pdev, SIO_ACPIBAR, &sio->acpi_base);
 	sio->acpi_base &= ~1;
 	printk(KERN_INFO PFX "ACPI at 0x%x\n", sio->acpi_base);
 	request_region (IC_PIC1, 0x1f, "pic1");
 	request_region (IC_PIC2, 0x1f, "pic2");
 	request_region (sio->acpi_base, 0x1f, "acpi");
 	/* Enable the legacy I/O function */
 	pci_read_config_word (pdev, PCI_COMMAND, &word);
 	word |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_IO;
 	pci_write_config_word (pdev, PCI_COMMAND, word);
 	pci_set_master (pdev);
 	pci_enable_device(pdev);
 	/*
 	 * Next project is programming the onboard interrupt controllers.
 	 * PDC hasn't done this for us, since it's using polled I/O.
 	 *
 	 * XXX Use dword writes to avoid bugs in Elroy or Suckyio Config
 	 *     space access.  PCI is by nature a 32-bit bus and config
 	 *     space can be sensitive to that.
 	 */
 	/* 0x64 - 0x67 :
 		DMA Rtg 2
 		DMA Rtg 3
 		DMA Chan Ctl
 		TRIGGER_1    == 0x82   USB & IDE level triggered, rest to edge
 	*/
 	pci_write_config_dword (pdev, 0x64,         0x82000000U);
 	/* 0x68 - 0x6b :
 		TRIGGER_2    == 0x00   all edge triggered (not used)
 		CFG_IR_SER   == 0x43   SerPort1 = IRQ3, SerPort2 = IRQ4
 		CFG_IR_PF    == 0x65   ParPort  = IRQ5, FloppyCtlr = IRQ6
 		CFG_IR_IDE   == 0x07   IDE1 = IRQ7, reserved
 	*/
 	pci_write_config_dword (pdev, TRIGGER_2,    0x07654300U);
 	/* 0x6c - 0x6f :
 		CFG_IR_INTAB == 0x00
 		CFG_IR_INTCD == 0x10   USB = IRQ1
 		CFG_IR_PS2   == 0x00
 		CFG_IR_FXBUS == 0x00
 	*/
 	pci_write_config_dword (pdev, CFG_IR_INTAB, 0x00001000U);
 	/* 0x70 - 0x73 :
 		CFG_IR_USB   == 0x00  not used. USB is connected to INTD.
 		CFG_IR_ACPI  == 0x00  not used.
 		DMA Priority == 0x4c88  Power on default value. NFC.
 	*/
 	pci_write_config_dword (pdev, CFG_IR_USB, 0x4c880000U);
 	/* PIC1 Initialization Command Word register programming */
 	outb (0x11,IC_PIC1+0);	/* ICW1: ICW4 write req | ICW1 */
 	outb (0x00,IC_PIC1+1);	/* ICW2: interrupt vector table - not used */
 	outb (0x04,IC_PIC1+1);	/* ICW3: Cascade */
 	outb (0x01,IC_PIC1+1);	/* ICW4: x86 mode */
 	/* PIC1 Program Operational Control Words */
 	outb (0xff,IC_PIC1+1);	/* OCW1: Mask all interrupts */
 	outb (0xc2,IC_PIC1+0);  /* OCW2: priority (3-7,0-2) */
 	/* PIC2 Initialization Command Word register programming */
 	outb (0x11,IC_PIC2+0);	/* ICW1: ICW4 write req | ICW1 */
 	outb (0x00,IC_PIC2+1);	/* ICW2: N/A */
 	outb (0x02,IC_PIC2+1);	/* ICW3: Slave ID code */
 	outb (0x01,IC_PIC2+1);	/* ICW4: x86 mode */
 	/* Program Operational Control Words */
 	outb (0xff,IC_PIC1+1);	/* OCW1: Mask all interrupts */
 	outb (0x68,IC_PIC1+0);	/* OCW3: OCW3 select | ESMM | SMM */
 	/* Write master mask reg */
 	outb (0xff,IC_PIC1+1);
 	/* Setup USB power regulation */
 	outb(1, sio->acpi_base + USB_REG_CR);
 	if (inb(sio->acpi_base + USB_REG_CR) & 1)
 		printk(KERN_INFO PFX "USB regulator enabled\n");
 	else
 		printk(KERN_ERR PFX "USB regulator not initialized!\n");
 	if (request_irq(pdev->irq, superio_interrupt, IRQF_DISABLED,
 			SUPERIO, (void *)sio)) {
 		printk(KERN_ERR PFX "could not get irq\n");
 		BUG();
 		return;
 	}
 	sio->suckyio_irq_enabled = 1;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO, superio_init);
 static void superio_disable_irq(unsigned int irq)
 {
 	u8 r8;
 	if ((irq < 1) || (irq == 2) || (irq > 7)) {
 		printk(KERN_ERR PFX "Illegal irq number.\n");
 		BUG();
 		return;
 	}
 	/* Mask interrupt */
 	r8 = inb(IC_PIC1+1);
 	r8 |= (1 << irq);
 	outb (r8,IC_PIC1+1);
 }
 static void superio_enable_irq(unsigned int irq)
 {
 	u8 r8;
 	if ((irq < 1) || (irq == 2) || (irq > 7)) {
 		printk(KERN_ERR PFX "Illegal irq number (%d).\n", irq);
 		BUG();
 		return;
 	}
 	/* Unmask interrupt */
 	r8 = inb(IC_PIC1+1);
 	r8 &= ~(1 << irq);
 	outb (r8,IC_PIC1+1);
 }
 static unsigned int superio_startup_irq(unsigned int irq)
 {
 	superio_enable_irq(irq);
 	return 0;
 }
 static struct hw_interrupt_type superio_interrupt_type = {
 	.typename =	SUPERIO,
 	.startup =	superio_startup_irq,
 	.shutdown =	superio_disable_irq,
 	.enable =	superio_enable_irq,
 	.disable =	superio_disable_irq,
 	.ack =		no_ack_irq,
 	.end =		no_end_irq,
 };
 #ifdef DEBUG_SUPERIO_INIT
 static unsigned short expected_device[3] = {
 	PCI_DEVICE_ID_NS_87415,
 	PCI_DEVICE_ID_NS_87560_LIO,
 	PCI_DEVICE_ID_NS_87560_USB
 };
 #endif
 int superio_fixup_irq(struct pci_dev *pcidev)
 {
 	int local_irq, i;
 #ifdef DEBUG_SUPERIO_INIT
 	int fn;
 	fn = PCI_FUNC(pcidev->devfn);
 	/* Verify the function number matches the expected device id. */
 	if (expected_device[fn] != pcidev->device) {
 		BUG();
 		return -1;
 	}
 	printk("superio_fixup_irq(%s) ven 0x%x dev 0x%x from %p\n",
 		pci_name(pcidev),
 		pcidev->vendor, pcidev->device,
 		__builtin_return_address(0));
 #endif
 	for (i = 0; i < 16; i++) {
 		irq_desc[i].chip = &superio_interrupt_type;
 	}
 	/*
 	 * We don't allocate a SuperIO irq for the legacy IO function,
 	 * since it is a "bridge". Instead, we will allocate irq's for
 	 * each legacy device as they are initialized.
 	 */
 	switch(pcidev->device) {
 	case PCI_DEVICE_ID_NS_87415:		/* Function 0 */
 		local_irq = IDE_IRQ;
 		break;
 	case PCI_DEVICE_ID_NS_87560_LIO:	/* Function 1 */
 		sio_dev.lio_pdev = pcidev;	/* save for superio_init() */
 		return -1;
 	case PCI_DEVICE_ID_NS_87560_USB:	/* Function 2 */
 		sio_dev.usb_pdev = pcidev;	/* save for superio_init() */
 		local_irq = USB_IRQ;
 		break;
 	default:
 		local_irq = -1;
 		BUG();
 		break;
 	}
 	return local_irq;
 }
 static void __init superio_serial_init(void)
 {
 #ifdef CONFIG_SERIAL_8250
 	int retval;
 	struct uart_port serial_port;
 	memset(&serial_port, 0, sizeof(serial_port));
 	serial_port.iotype	= UPIO_PORT;
 	serial_port.type	= PORT_16550A;
 	serial_port.uartclk	= 115200*16;
 	serial_port.fifosize	= 16;
 	spin_lock_init(&serial_port.lock);
 	/* serial port #1 */
 	serial_port.iobase	= sio_dev.sp1_base;
 	serial_port.irq		= SP1_IRQ;
 	serial_port.line	= 0;
 	retval = early_serial_setup(&serial_port);
 	if (retval < 0) {
 		printk(KERN_WARNING PFX "Register Serial #0 failed.\n");
 		return;
 	}
 	/* serial port #2 */
 	serial_port.iobase	= sio_dev.sp2_base;
 	serial_port.irq		= SP2_IRQ;
 	serial_port.line	= 1;
 	retval = early_serial_setup(&serial_port);
 	if (retval < 0)
 		printk(KERN_WARNING PFX "Register Serial #1 failed.\n");
 #endif /* CONFIG_SERIAL_8250 */
 }
 static void __init superio_parport_init(void)
 {
 #ifdef CONFIG_PARPORT_PC
 	if (!parport_pc_probe_port(sio_dev.pp_base,
 			0 /*base_hi*/,
 			PAR_IRQ,
 			PARPORT_DMA_NONE /* dma */,
 			NULL /*struct pci_dev* */) )
 		printk(KERN_WARNING PFX "Probing parallel port failed.\n");
 #endif	/* CONFIG_PARPORT_PC */
 }
 static void superio_fixup_pci(struct pci_dev *pdev)
 {
 	u8 prog;
 	pdev->class |= 0x5;
 	pci_write_config_byte(pdev, PCI_CLASS_PROG, pdev->class);
 	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
 	printk("PCI: Enabled native mode for NS87415 (pif=0x%x)\n", prog);
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, superio_fixup_pci);
 static int __init
 superio_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
 	struct superio_device *sio = &sio_dev;
 	/*
 	** superio_probe(00:0e.0) ven 0x100b dev 0x2 sv 0x0 sd 0x0 class 0x1018a
 	** superio_probe(00:0e.1) ven 0x100b dev 0xe sv 0x0 sd 0x0 class 0x68000
 	** superio_probe(00:0e.2) ven 0x100b dev 0x12 sv 0x0 sd 0x0 class 0xc0310
 	*/
 	DBG_INIT("superio_probe(%s) ven 0x%x dev 0x%x sv 0x%x sd 0x%x class 0x%x\n",
 		pci_name(dev),
 		dev->vendor, dev->device,
 		dev->subsystem_vendor, dev->subsystem_device,
 		dev->class);
 	BUG_ON(!sio->suckyio_irq_enabled);	/* Enabled by PCI_FIXUP_FINAL */
 	if (dev->device == PCI_DEVICE_ID_NS_87560_LIO) {	/* Function 1 */
 		superio_parport_init();
 		superio_serial_init();
 		/* REVISIT XXX : superio_fdc_init() ? */
 		return 0;
 	} else if (dev->device == PCI_DEVICE_ID_NS_87415) {	/* Function 0 */
 		DBG_INIT("superio_probe: ignoring IDE 87415\n");
 	} else if (dev->device == PCI_DEVICE_ID_NS_87560_USB) {	/* Function 2 */
 		DBG_INIT("superio_probe: ignoring USB OHCI controller\n");
 	} else {
 		DBG_INIT("superio_probe: WTF? Fire Extinguisher?\n");
 	}
 	/* Let appropriate other driver claim this device. */
 	return -ENODEV;
 }
 static const struct pci_device_id superio_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_USB) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415) },
 	{ 0, }
 };
 static struct pci_driver superio_driver = {
 	.name =         SUPERIO,
 	.id_table =     superio_tbl,
 	.probe =        superio_probe,
 };
 static int __init superio_modinit(void)
 {
 	return pci_register_driver(&superio_driver);
 }
 static void __exit superio_exit(void)
 {
 	pci_unregister_driver(&superio_driver);
 }
 module_init(superio_modinit);
 module_exit(superio_exit);

drivers/serial/8250_hp300.c

Diff comments View file @ b187f18

 /*
  * Driver for the 98626/98644/internal serial interface on hp300/hp400
  * (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
  *
  * Ported from 2.2 and modified to use the normal 8250 driver
  * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
  */
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/delay.h>
 #include <linux/dio.h>
 #include <linux/console.h>
 #include <asm/io.h>
 #include "8250.h"
 #if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI)
 #warning CONFIG_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
 #endif
 #ifdef CONFIG_HPAPCI
 struct hp300_port
 {
 	struct hp300_port *next;	/* next port */
 	int line;			/* line (tty) number */
 };
 static struct hp300_port *hp300_ports;
 #endif
 #ifdef CONFIG_HPDCA
 static int __devinit hpdca_init_one(struct dio_dev *d,
                                 const struct dio_device_id *ent);
 static void __devexit hpdca_remove_one(struct dio_dev *d);
 static struct dio_device_id hpdca_dio_tbl[] = {
 	{ DIO_ID_DCA0 },
 	{ DIO_ID_DCA0REM },
 	{ DIO_ID_DCA1 },
 	{ DIO_ID_DCA1REM },
 	{ 0 }
 };
 static struct dio_driver hpdca_driver = {
 	.name      = "hpdca",
 	.id_table  = hpdca_dio_tbl,
 	.probe     = hpdca_init_one,
 	.remove    = __devexit_p(hpdca_remove_one),
 };
 #endif
 static unsigned int num_ports;
 extern int hp300_uart_scode;
 /* Offset to UART registers from base of DCA */
 #define UART_OFFSET	17
 #define DCA_ID		0x01	/* ID (read), reset (write) */
 #define DCA_IC		0x03	/* Interrupt control        */
 /* Interrupt control */
 #define DCA_IC_IE	0x80	/* Master interrupt enable  */
 #define HPDCA_BAUD_BASE 153600
 /* Base address of the Frodo part */
 #define FRODO_BASE	(0x41c000)
 /*
  * Where we find the 8250-like APCI ports, and how far apart they are.
  */
 #define FRODO_APCIBASE		0x0
 #define FRODO_APCISPACE		0x20
 #define FRODO_APCI_OFFSET(x)	(FRODO_APCIBASE + ((x) * FRODO_APCISPACE))
 #define HPAPCI_BAUD_BASE 500400
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 /*
  * Parse the bootinfo to find descriptions for headless console and
  * debug serial ports and register them with the 8250 driver.
  * This function should be called before serial_console_init() is called
  * to make sure the serial console will be available for use. IA-64 kernel
  * calls this function from setup_arch() after the EFI and ACPI tables have
  * been parsed.
  */
 int __init hp300_setup_serial_console(void)
 {
 	int scode;
 	struct uart_port port;
 	memset(&port, 0, sizeof(port));
 	if (hp300_uart_scode < 0 || hp300_uart_scode > DIO_SCMAX)
 		return 0;
 	if (DIO_SCINHOLE(hp300_uart_scode))
 		return 0;
 	scode = hp300_uart_scode;
 	/* Memory mapped I/O */
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
 	port.type = PORT_UNKNOWN;
 	/* Check for APCI console */
 	if (scode == 256) {
 #ifdef CONFIG_HPAPCI
 		printk(KERN_INFO "Serial console is HP APCI 1\n");
 		port.uartclk = HPAPCI_BAUD_BASE * 16;
 		port.mapbase = (FRODO_BASE + FRODO_APCI_OFFSET(1));
 		port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
 		port.regshift = 2;
 		add_preferred_console("ttyS", port.line, "9600n8");
 #else
 		printk(KERN_WARNING "Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
 		return 0;
 #endif
 	}
 	else {
 #ifdef CONFIG_HPDCA
 		unsigned long pa = dio_scodetophysaddr(scode);
 		if (!pa) {
 			return 0;
 		}
 		printk(KERN_INFO "Serial console is HP DCA at select code %d\n", scode);
 		port.uartclk = HPDCA_BAUD_BASE * 16;
 		port.mapbase = (pa + UART_OFFSET);
 		port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
 		port.regshift = 1;
 		port.irq = DIO_IPL(pa + DIO_VIRADDRBASE);
 		/* Enable board-interrupts */
 		out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
 		if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80) {
 			add_preferred_console("ttyS", port.line, "9600n8");
 		}
 #else
 		printk(KERN_WARNING "Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
 		return 0;
 #endif
 	}
 	if (early_serial_setup(&port) < 0) {
 		printk(KERN_WARNING "hp300_setup_serial_console(): early_serial_setup() failed.\n");
 	}
 	return 0;
 }
 #endif /* CONFIG_SERIAL_8250_CONSOLE */
 #ifdef CONFIG_HPDCA
 static int __devinit hpdca_init_one(struct dio_dev *d,
                                 const struct dio_device_id *ent)
 {
 	struct uart_port port;
 	int line;
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 	if (hp300_uart_scode == d->scode) {
 		/* Already got it. */
 		return 0;
 	}
 #endif
 	memset(&port, 0, sizeof(struct uart_port));
 	/* Memory mapped I/O */
 	port.iotype = UPIO_MEM;
 	port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
 	port.irq = d->ipl;
 	port.uartclk = HPDCA_BAUD_BASE * 16;
 	port.mapbase = (d->resource.start + UART_OFFSET);
 	port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
 	port.regshift = 1;
 	port.dev = &d->dev;
 	line = serial8250_register_port(&port);
 	if (line < 0) {
 		printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d"
 		       " irq %d failed\n", d->scode, port.irq);
 		return -ENOMEM;
 	}
 	/* Enable board-interrupts */
 	out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
 	dio_set_drvdata(d, (void *)line);
 	/* Reset the DCA */
 	out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
 	udelay(100);
 	num_ports++;
 	return 0;
 }
 #endif
 static int __init hp300_8250_init(void)
 {
 	static int called = 0;
 #ifdef CONFIG_HPAPCI
 	int line;
 	unsigned long base;
 	struct uart_port uport;
 	struct hp300_port *port;
 	int i;
 #endif
 	if (called)
 		return -ENODEV;
 	called = 1;
 	if (!MACH_IS_HP300)
 		return -ENODEV;
 #ifdef CONFIG_HPDCA
 	dio_register_driver(&hpdca_driver);
 #endif
 #ifdef CONFIG_HPAPCI
 	if (hp300_model < HP_400) {
 		if (!num_ports)
 			return -ENODEV;
 		return 0;
 	}
 	/* These models have the Frodo chip.
 	 * Port 0 is reserved for the Apollo Domain keyboard.
 	 * Port 1 is either the console or the DCA.
 	 */
 	for (i = 1; i < 4; i++) {
 		/* Port 1 is the console on a 425e, on other machines it's mapped to
 		 * DCA.
 		 */
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 		if (i == 1) {
 			continue;
 		}
 #endif
 		/* Create new serial device */
 		port = kmalloc(sizeof(struct hp300_port), GFP_KERNEL);
 		if (!port)
 			return -ENOMEM;
 		memset(&uport, 0, sizeof(struct uart_port));
 		base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
 		/* Memory mapped I/O */
 		uport.iotype = UPIO_MEM;
 		uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
 		/* XXX - no interrupt support yet */
 		uport.irq = 0;
 		uport.uartclk = HPAPCI_BAUD_BASE * 16;
 		uport.mapbase = base;
 		uport.membase = (char *)(base + DIO_VIRADDRBASE);
 		uport.regshift = 2;
 		line = serial8250_register_port(&uport);
 		if (line < 0) {
 			printk(KERN_NOTICE "8250_hp300: register_serial() APCI %d"
 			       " irq %d failed\n", i, uport.irq);
 			kfree(port);
 			continue;
 		}
 		port->line = line;
 		port->next = hp300_ports;
 		hp300_ports = port;
 		num_ports++;
 	}
 #endif
 	/* Any boards found? */
 	if (!num_ports)
 		return -ENODEV;
 	return 0;
 }
 #ifdef CONFIG_HPDCA
 static void __devexit hpdca_remove_one(struct dio_dev *d)
 {
 	int line;
 	line = (int) dio_get_drvdata(d);
 	if (d->resource.start) {
 		/* Disable board-interrupts */
 		out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0);
 	}
 	serial8250_unregister_port(line);
 }
 #endif
 static void __exit hp300_8250_exit(void)
 {
 #ifdef CONFIG_HPAPCI
 	struct hp300_port *port, *to_free;
 	for (port = hp300_ports; port; ) {
 		serial8250_unregister_port(port->line);
 		to_free = port;
 		port = port->next;
 		kfree(to_free);
 	}
 	hp300_ports = NULL;
 #endif
 #ifdef CONFIG_HPDCA
 	dio_unregister_driver(&hpdca_driver);
 #endif
 }
 module_init(hp300_8250_init);
 module_exit(hp300_8250_exit);
 MODULE_DESCRIPTION("HP DCA/APCI serial driver");
 MODULE_AUTHOR("Kars de Jong <jongk@linux-m68k.org>");
 MODULE_LICENSE("GPL");

include/linux/serial_8250.h

Diff comments View file @ b187f18

 /*
  *  linux/include/linux/serial_8250.h
  *
  *  Copyright (C) 2004 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
 #ifndef _LINUX_SERIAL_8250_H
 #define _LINUX_SERIAL_8250_H
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 /*
  * This is the platform device platform_data structure
  */
 struct plat_serial8250_port {
 	unsigned long	iobase;		/* io base address */
 	void __iomem	*membase;	/* ioremap cookie or NULL */
 	unsigned long	mapbase;	/* resource base */
 	unsigned int	irq;		/* interrupt number */
 	unsigned int	uartclk;	/* UART clock rate */
 	unsigned char	regshift;	/* register shift */
 	unsigned char	iotype;		/* UPIO_* */
 	unsigned char	hub6;
 	upf_t		flags;		/* UPF_* flags */
 };
 /*
  * Allocate 8250 platform device IDs.  Nothing is implied by
  * the numbering here, except for the legacy entry being -1.
  */
 enum {
 	PLAT8250_DEV_LEGACY = -1,
 	PLAT8250_DEV_PLATFORM,
 	PLAT8250_DEV_PLATFORM1,
 	PLAT8250_DEV_PLATFORM2,
 	PLAT8250_DEV_FOURPORT,
 	PLAT8250_DEV_ACCENT,
 	PLAT8250_DEV_BOCA,
 	PLAT8250_DEV_EXAR_ST16C554,
 	PLAT8250_DEV_HUB6,
 	PLAT8250_DEV_MCA,
 	PLAT8250_DEV_AU1X00,
 };
 /*
  * This should be used by drivers which want to register
  * their own 8250 ports without registering their own
  * platform device.  Using these will make your driver
  * dependent on the 8250 driver.
  */
 struct uart_port;
 int serial8250_register_port(struct uart_port *);
 void serial8250_unregister_port(int line);
 void serial8250_suspend_port(int line);
 void serial8250_resume_port(int line);
+extern int early_serial_setup(struct uart_port *port);
 extern int serial8250_find_port(struct uart_port *p);
 extern int serial8250_find_port_for_earlycon(void);
 extern int setup_early_serial8250_console(char *cmdline);
 #endif