Eric Lee / smarc-ti-linux-kernel

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Commit c15018e9192bbaa1a0f68ebee0284f701491b800

Authored by Marc Zyngier
Committed by Jason Cooper
1 parent cf86bfdd68
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

irqchip: sirfsoc: Convert to handle_domain_irq 

Use the new handle_domain_irq method to handle interrupts.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1409047421-27649-13-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Showing 1 changed file with 2 additions and 4 deletions Inline Diff

drivers/irqchip/irq-sirfsoc.c
Diff comments   View file @ c15018e
1 /* 1 /*
2 * interrupt controller support for CSR SiRFprimaII 2 * interrupt controller support for CSR SiRFprimaII
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 * 5 *
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9 #include <linux/init.h> 9 #include <linux/init.h>
10 #include <linux/io.h> 10 #include <linux/io.h>
11 #include <linux/irq.h> 11 #include <linux/irq.h>
12 #include <linux/of.h> 12 #include <linux/of.h>
13 #include <linux/of_address.h> 13 #include <linux/of_address.h>
14 #include <linux/irqdomain.h> 14 #include <linux/irqdomain.h>
15 #include <linux/syscore_ops.h> 15 #include <linux/syscore_ops.h>
16 #include <asm/mach/irq.h> 16 #include <asm/mach/irq.h>
17 #include <asm/exception.h> 17 #include <asm/exception.h>
18 #include "irqchip.h" 18 #include "irqchip.h"
19 19
20 #define SIRFSOC_INT_RISC_MASK0 0x0018 20 #define SIRFSOC_INT_RISC_MASK0 0x0018
21 #define SIRFSOC_INT_RISC_MASK1 0x001C 21 #define SIRFSOC_INT_RISC_MASK1 0x001C
22 #define SIRFSOC_INT_RISC_LEVEL0 0x0020 22 #define SIRFSOC_INT_RISC_LEVEL0 0x0020
23 #define SIRFSOC_INT_RISC_LEVEL1 0x0024 23 #define SIRFSOC_INT_RISC_LEVEL1 0x0024
24 #define SIRFSOC_INIT_IRQ_ID 0x0038 24 #define SIRFSOC_INIT_IRQ_ID 0x0038
25 25
26 #define SIRFSOC_NUM_IRQS 64 26 #define SIRFSOC_NUM_IRQS 64
27 27
28 static struct irq_domain *sirfsoc_irqdomain; 28 static struct irq_domain *sirfsoc_irqdomain;
29 29
30 static __init void 30 static __init void
31 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 31 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
32 { 32 {
33 struct irq_chip_generic *gc; 33 struct irq_chip_generic *gc;
34 struct irq_chip_type *ct; 34 struct irq_chip_type *ct;
35 int ret; 35 int ret;
36 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 36 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
37 unsigned int set = IRQ_LEVEL; 37 unsigned int set = IRQ_LEVEL;
38 38
39 ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc", 39 ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
40 handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE); 40 handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
41 41
42 gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start); 42 gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
43 gc->reg_base = base; 43 gc->reg_base = base;
44 ct = gc->chip_types; 44 ct = gc->chip_types;
45 ct->chip.irq_mask = irq_gc_mask_clr_bit; 45 ct->chip.irq_mask = irq_gc_mask_clr_bit;
46 ct->chip.irq_unmask = irq_gc_mask_set_bit; 46 ct->chip.irq_unmask = irq_gc_mask_set_bit;
47 ct->regs.mask = SIRFSOC_INT_RISC_MASK0; 47 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
48 } 48 }
49 49
50 static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) 50 static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
51 { 51 {
52 void __iomem *base = sirfsoc_irqdomain->host_data; 52 void __iomem *base = sirfsoc_irqdomain->host_data;
53 u32 irqstat, irqnr; 53 u32 irqstat;
54 54
55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); 55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
56 irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff); 56 handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
57
58 handle_IRQ(irqnr, regs);
59 } 57 }
60 58
61 static int __init sirfsoc_irq_init(struct device_node *np, 59 static int __init sirfsoc_irq_init(struct device_node *np,
62 struct device_node *parent) 60 struct device_node *parent)
63 { 61 {
64 void __iomem *base = of_iomap(np, 0); 62 void __iomem *base = of_iomap(np, 0);
65 if (!base) 63 if (!base)
66 panic("unable to map intc cpu registers\n"); 64 panic("unable to map intc cpu registers\n");
67 65
68 sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS, 66 sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
69 &irq_generic_chip_ops, base); 67 &irq_generic_chip_ops, base);
70 68
71 sirfsoc_alloc_gc(base, 0, 32); 69 sirfsoc_alloc_gc(base, 0, 32);
72 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); 70 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
73 71
74 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); 72 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
75 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); 73 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
76 74
77 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); 75 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
78 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); 76 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
79 77
80 set_handle_irq(sirfsoc_handle_irq); 78 set_handle_irq(sirfsoc_handle_irq);
81 79
82 return 0; 80 return 0;
83 } 81 }
84 IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init); 82 IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
85 83
86 struct sirfsoc_irq_status { 84 struct sirfsoc_irq_status {
87 u32 mask0; 85 u32 mask0;
88 u32 mask1; 86 u32 mask1;
89 u32 level0; 87 u32 level0;
90 u32 level1; 88 u32 level1;
91 }; 89 };
92 90
93 static struct sirfsoc_irq_status sirfsoc_irq_st; 91 static struct sirfsoc_irq_status sirfsoc_irq_st;
94 92
95 static int sirfsoc_irq_suspend(void) 93 static int sirfsoc_irq_suspend(void)
96 { 94 {
97 void __iomem *base = sirfsoc_irqdomain->host_data; 95 void __iomem *base = sirfsoc_irqdomain->host_data;
98 96
99 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); 97 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
100 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); 98 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
101 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); 99 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
102 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); 100 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
103 101
104 return 0; 102 return 0;
105 } 103 }
106 104
107 static void sirfsoc_irq_resume(void) 105 static void sirfsoc_irq_resume(void)
108 { 106 {
109 void __iomem *base = sirfsoc_irqdomain->host_data; 107 void __iomem *base = sirfsoc_irqdomain->host_data;
110 108
111 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); 109 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
112 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); 110 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
113 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); 111 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
114 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); 112 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
115 } 113 }
116 114
117 static struct syscore_ops sirfsoc_irq_syscore_ops = { 115 static struct syscore_ops sirfsoc_irq_syscore_ops = {
118 .suspend = sirfsoc_irq_suspend, 116 .suspend = sirfsoc_irq_suspend,
119 .resume = sirfsoc_irq_resume, 117 .resume = sirfsoc_irq_resume,
120 }; 118 };
121 119
122 static int __init sirfsoc_irq_pm_init(void) 120 static int __init sirfsoc_irq_pm_init(void)
123 { 121 {
124 if (!sirfsoc_irqdomain) 122 if (!sirfsoc_irqdomain)
125 return 0; 123 return 0;
126 124
127 register_syscore_ops(&sirfsoc_irq_syscore_ops); 125 register_syscore_ops(&sirfsoc_irq_syscore_ops);
128 return 0; 126 return 0;
129 } 127 }
130 device_initcall(sirfsoc_irq_pm_init); 128 device_initcall(sirfsoc_irq_pm_init);
131 129