Commit c239208a68dc4056e93eb987379464a2289ad3e3
1 parent
bc1695bfcb
Exists in
smarc-ti-linux-3.14.y
Fix Dual LAN package loss problem
Showing 1 changed file with 5 additions and 0 deletions Inline Diff
arch/arm/boot/dts/am335x-smarc-common.dtsi
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* state the resources this carrier uses for audio function*/ | 9 | /* state the resources this carrier uses for audio function*/ |
| 10 | /* the pin header uses for Audio*/ | 10 | /* the pin header uses for Audio*/ |
| 11 | /* | 11 | /* |
| 12 | "S.39", mcasp1: mcasp0_fsr.mcasp1_fsx mode3 | 12 | "S.39", mcasp1: mcasp0_fsr.mcasp1_fsx mode3 |
| 13 | "S.40", mcasp1: mcasp0_axr1.mcasp1_axr0 mode3 | 13 | "S.40", mcasp1: mcasp0_axr1.mcasp1_axr0 mode3 |
| 14 | "S.41", mcasp1: mcasp0_ahclkx.mcasp1_axr1 mode3 | 14 | "S.41", mcasp1: mcasp0_ahclkx.mcasp1_axr1 mode3 |
| 15 | "S.42", mcasp1: mcasp0_aclkr.mcasp1_aclkx mode3 | 15 | "S.42", mcasp1: mcasp0_aclkr.mcasp1_aclkx mode3 |
| 16 | */ | 16 | */ |
| 17 | /* the pin header uses for SPI1*/ | 17 | /* the pin header uses for SPI1*/ |
| 18 | /* | 18 | /* |
| 19 | "P.54", spi1: mcasp0_ahclkr.spi1_cs0n mode3 | 19 | "P.54", spi1: mcasp0_ahclkr.spi1_cs0n mode3 |
| 20 | "P.55", spi1: xdma_event_intro0.spi1_cs1n mode4 | 20 | "P.55", spi1: xdma_event_intro0.spi1_cs1n mode4 |
| 21 | "P.56", spi1: mcasp0_aclkx.spi1_sclk mode3 | 21 | "P.56", spi1: mcasp0_aclkx.spi1_sclk mode3 |
| 22 | "P.57", spi1: mcasp0_fsx.spi1_d0 mode3 | 22 | "P.57", spi1: mcasp0_fsx.spi1_d0 mode3 |
| 23 | "P.58", spi1: mcasp0_axr0.spi1_d1 mode3 | 23 | "P.58", spi1: mcasp0_axr0.spi1_d1 mode3 |
| 24 | */ | 24 | */ |
| 25 | /* the pin header uses for LCD*/ | 25 | /* the pin header uses for LCD*/ |
| 26 | /* | 26 | /* |
| 27 | "S.114", lcd: lcd_data0.lcd_data0 mode0 | 27 | "S.114", lcd: lcd_data0.lcd_data0 mode0 |
| 28 | "S.115", lcd: lcd_data1.lcd_data1 mode0 | 28 | "S.115", lcd: lcd_data1.lcd_data1 mode0 |
| 29 | "S.116", lcd: lcd_data2.lcd_data2 mode0 | 29 | "S.116", lcd: lcd_data2.lcd_data2 mode0 |
| 30 | "S.117", lcd: lcd_data3.lcd_data3 mode0 | 30 | "S.117", lcd: lcd_data3.lcd_data3 mode0 |
| 31 | "S.118", lcd: lcd_data4.lcd_data4 mode0 | 31 | "S.118", lcd: lcd_data4.lcd_data4 mode0 |
| 32 | "S.104", lcd: lcd_data5.lcd_data5 mode0 | 32 | "S.104", lcd: lcd_data5.lcd_data5 mode0 |
| 33 | "S.105", lcd: lcd_data6.lcd_data6 mode0 | 33 | "S.105", lcd: lcd_data6.lcd_data6 mode0 |
| 34 | "S.106", lcd: lcd_data7.lcd_data7 mode0 | 34 | "S.106", lcd: lcd_data7.lcd_data7 mode0 |
| 35 | "S.107", lcd: lcd_data8.lcd_data8 mode0 | 35 | "S.107", lcd: lcd_data8.lcd_data8 mode0 |
| 36 | "S.108", lcd: lcd_data9.lcd_data9 mode0 | 36 | "S.108", lcd: lcd_data9.lcd_data9 mode0 |
| 37 | "S.109", lcd: lcd_data10.lcd_data10 mode0 | 37 | "S.109", lcd: lcd_data10.lcd_data10 mode0 |
| 38 | "S.96", lcd: lcd_data11.lcd_data11 mode0 | 38 | "S.96", lcd: lcd_data11.lcd_data11 mode0 |
| 39 | "S.97", lcd: lcd_data12.lcd_data12 mode0 | 39 | "S.97", lcd: lcd_data12.lcd_data12 mode0 |
| 40 | "S.98", lcd: lcd_data13.lcd_data13 mode0 | 40 | "S.98", lcd: lcd_data13.lcd_data13 mode0 |
| 41 | "S.99", lcd: lcd_data14.lcd_data14 mode0 | 41 | "S.99", lcd: lcd_data14.lcd_data14 mode0 |
| 42 | "S.100", lcd: lcd_data15.lcd_data15 mode0 | 42 | "S.100", lcd: lcd_data15.lcd_data15 mode0 |
| 43 | "S.113", lcd: lcd_data16.gpmc_ad15 mode0 | 43 | "S.113", lcd: lcd_data16.gpmc_ad15 mode0 |
| 44 | "S.95", lcd: lcd_data17.gpmc_ad14 mode0 | 44 | "S.95", lcd: lcd_data17.gpmc_ad14 mode0 |
| 45 | "S.112", lcd: lcd_data18.gpmc_ad13 mode0 | 45 | "S.112", lcd: lcd_data18.gpmc_ad13 mode0 |
| 46 | "S.103", lcd: lcd_data19.gpmc_ad12 mode0 | 46 | "S.103", lcd: lcd_data19.gpmc_ad12 mode0 |
| 47 | "S.94", lcd: lcd_data20.gpmc_ad11 mode0 | 47 | "S.94", lcd: lcd_data20.gpmc_ad11 mode0 |
| 48 | "S.111", lcd: lcd_data21.gpmc_ad10 mode0 | 48 | "S.111", lcd: lcd_data21.gpmc_ad10 mode0 |
| 49 | "S.102", lcd: lcd_data22.gpmc_ad9 mode0 | 49 | "S.102", lcd: lcd_data22.gpmc_ad9 mode0 |
| 50 | "S.93", lcd: lcd_data23.gpmc_ad8 mode0 | 50 | "S.93", lcd: lcd_data23.gpmc_ad8 mode0 |
| 51 | "S.121", lcd: lcd_vsync.lcd_vsync mode0 | 51 | "S.121", lcd: lcd_vsync.lcd_vsync mode0 |
| 52 | "S.122", lcd: lcd_hsync.lcd_hsync mode0 | 52 | "S.122", lcd: lcd_hsync.lcd_hsync mode0 |
| 53 | "S.123", lcd: lcd_pclk.lcd_pclk mode0 | 53 | "S.123", lcd: lcd_pclk.lcd_pclk mode0 |
| 54 | "S.120", lcd_de: lcd_ac_bias_en.lcd_ac_bias_en mode0 | 54 | "S.120", lcd_de: lcd_ac_bias_en.lcd_ac_bias_en mode0 |
| 55 | "S.133", lcd_vdd_en: gpmc_a7.gpio1_23 mode7 | 55 | "S.133", lcd_vdd_en: gpmc_a7.gpio1_23 mode7 |
| 56 | "S.127", lcd_bklt_en: gpmc_a6.gpio1_22 mode7 | 56 | "S.127", lcd_bklt_en: gpmc_a6.gpio1_22 mode7 |
| 57 | ` */ | 57 | ` */ |
| 58 | /* the pin header uses for DCAN0*/ | 58 | /* the pin header uses for DCAN0*/ |
| 59 | /* | 59 | /* |
| 60 | "P.143", dcan0_tx: gmii1_txd3.dcan0_tx mode1 | 60 | "P.143", dcan0_tx: gmii1_txd3.dcan0_tx mode1 |
| 61 | "P.144", dcan0_rx: gmii1_txd2.dcan0_rx mode1 | 61 | "P.144", dcan0_rx: gmii1_txd2.dcan0_rx mode1 |
| 62 | */ | 62 | */ |
| 63 | /* the hardware ip uses */ | 63 | /* the hardware ip uses */ |
| 64 | /* | 64 | /* |
| 65 | "mcasp1", | 65 | "mcasp1", |
| 66 | "i2c0", | 66 | "i2c0", |
| 67 | "i2c1", | 67 | "i2c1", |
| 68 | "i2c2", | 68 | "i2c2", |
| 69 | "uart0", | 69 | "uart0", |
| 70 | "uart2", | 70 | "uart2", |
| 71 | "uart3", | 71 | "uart3", |
| 72 | "touch", | 72 | "touch", |
| 73 | "mmc0/SD", | 73 | "mmc0/SD", |
| 74 | "emmc", | 74 | "emmc", |
| 75 | "ecap0/backlight", | 75 | "ecap0/backlight", |
| 76 | "emac0", | 76 | "emac0", |
| 77 | "emac1", | 77 | "emac1", |
| 78 | "gpio1_22", | 78 | "gpio1_22", |
| 79 | "gpio1_23", | 79 | "gpio1_23", |
| 80 | "gpio1_19", | 80 | "gpio1_19", |
| 81 | "lcd", | 81 | "lcd", |
| 82 | "dcan0", | 82 | "dcan0", |
| 83 | "spi0", | 83 | "spi0", |
| 84 | "spi1"; | 84 | "spi1"; |
| 85 | */ | 85 | */ |
| 86 | 86 | ||
| 87 | 87 | ||
| 88 | / { | 88 | / { |
| 89 | model = "TI AM335x SMARCT335X"; | 89 | model = "TI AM335x SMARCT335X"; |
| 90 | compatible = "ti,am335x-smarct335x", "ti,am33xx"; | 90 | compatible = "ti,am335x-smarct335x", "ti,am33xx"; |
| 91 | 91 | ||
| 92 | cpus { | 92 | cpus { |
| 93 | cpu@0 { | 93 | cpu@0 { |
| 94 | cpu0-supply = <&dcdc2_reg>; | 94 | cpu0-supply = <&dcdc2_reg>; |
| 95 | }; | 95 | }; |
| 96 | }; | 96 | }; |
| 97 | 97 | ||
| 98 | memory { | 98 | memory { |
| 99 | device_type = "memory"; | 99 | device_type = "memory"; |
| 100 | reg = <0x80000000 0x20000000>; /* 512 MB */ | 100 | reg = <0x80000000 0x20000000>; /* 512 MB */ |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | vmmcsd_fixed: fixedregulator@0 { | 103 | vmmcsd_fixed: fixedregulator@0 { |
| 104 | compatible = "regulator-fixed"; | 104 | compatible = "regulator-fixed"; |
| 105 | regulator-name = "vmmcsd_fixed"; | 105 | regulator-name = "vmmcsd_fixed"; |
| 106 | regulator-min-microvolt = <3300000>; | 106 | regulator-min-microvolt = <3300000>; |
| 107 | regulator-max-microvolt = <3300000>; | 107 | regulator-max-microvolt = <3300000>; |
| 108 | }; | 108 | }; |
| 109 | 109 | ||
| 110 | backlight { | 110 | backlight { |
| 111 | compatible = "pwm-backlight"; | 111 | compatible = "pwm-backlight"; |
| 112 | enable-gpios = <&gpio1 22 0>; /* Backlight Enable Pin*/ | 112 | enable-gpios = <&gpio1 22 0>; /* Backlight Enable Pin*/ |
| 113 | pwms = <&ecap0 0 50000 0>; | 113 | pwms = <&ecap0 0 50000 0>; |
| 114 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | 114 | brightness-levels = <0 51 53 56 62 75 101 152 255>; |
| 115 | default-brightness-level = <8>; | 115 | default-brightness-level = <8>; |
| 116 | }; | 116 | }; |
| 117 | 117 | ||
| 118 | panel { | 118 | panel { |
| 119 | compatible = "ti,tilcdc,panel"; | 119 | compatible = "ti,tilcdc,panel"; |
| 120 | status = "okay"; | 120 | status = "okay"; |
| 121 | panel-info { | 121 | panel-info { |
| 122 | ac-bias = <255>; | 122 | ac-bias = <255>; |
| 123 | ac-bias-intrpt = <0>; | 123 | ac-bias-intrpt = <0>; |
| 124 | dma-burst-sz = <16>; | 124 | dma-burst-sz = <16>; |
| 125 | bpp = <32>; | 125 | bpp = <32>; |
| 126 | fdd = <0x80>; | 126 | fdd = <0x80>; |
| 127 | sync-edge = <0>; | 127 | sync-edge = <0>; |
| 128 | sync-ctrl = <1>; | 128 | sync-ctrl = <1>; |
| 129 | raster-order = <0>; | 129 | raster-order = <0>; |
| 130 | fifo-th = <0>; | 130 | fifo-th = <0>; |
| 131 | /*invert-pxl-clk;*/ /*pixel clock polarity*/ | 131 | /*invert-pxl-clk;*/ /*pixel clock polarity*/ |
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | display-timings { | 134 | display-timings { |
| 135 | 800x480p60 { | 135 | 800x480p60 { |
| 136 | clock-frequency = <32000000>; | 136 | clock-frequency = <32000000>; |
| 137 | hactive = <800>; | 137 | hactive = <800>; |
| 138 | vactive = <480>; | 138 | vactive = <480>; |
| 139 | hfront-porch = <42>; | 139 | hfront-porch = <42>; |
| 140 | hback-porch = <84>; | 140 | hback-porch = <84>; |
| 141 | hsync-len = <128>; | 141 | hsync-len = <128>; |
| 142 | vback-porch = <33>; | 142 | vback-porch = <33>; |
| 143 | vfront-porch = <10>; | 143 | vfront-porch = <10>; |
| 144 | vsync-len = <2>; | 144 | vsync-len = <2>; |
| 145 | hsync-active = <0>; | 145 | hsync-active = <0>; |
| 146 | vsync-active = <0>; | 146 | vsync-active = <0>; |
| 147 | }; | 147 | }; |
| 148 | }; | 148 | }; |
| 149 | }; | 149 | }; |
| 150 | 150 | ||
| 151 | sound { | 151 | sound { |
| 152 | compatible = "ti,da830-evm-audio"; | 152 | compatible = "ti,da830-evm-audio"; |
| 153 | ti,model = "TLV320AIC3X SOUND CARD"; | 153 | ti,model = "TLV320AIC3X SOUND CARD"; |
| 154 | ti,audio-codec = <&tlv320aic3106>; | 154 | ti,audio-codec = <&tlv320aic3106>; |
| 155 | ti,mcasp-controller = <&mcasp1>; | 155 | ti,mcasp-controller = <&mcasp1>; |
| 156 | ti,codec-clock-rate = <24576000>; | 156 | ti,codec-clock-rate = <24576000>; |
| 157 | ti,audio-routing = | 157 | ti,audio-routing = |
| 158 | "Headphone Jack", "HPLOUT", | 158 | "Headphone Jack", "HPLOUT", |
| 159 | "Headphone Jack", "HPROUT", | 159 | "Headphone Jack", "HPROUT", |
| 160 | "LINE1L", "Line In", | 160 | "LINE1L", "Line In", |
| 161 | "LINE1R", "Line In"; | 161 | "LINE1R", "Line In"; |
| 162 | }; | 162 | }; |
| 163 | }; | 163 | }; |
| 164 | 164 | ||
| 165 | 165 | ||
| 166 | &am33xx_pinmux { | 166 | &am33xx_pinmux { |
| 167 | pinctrl-names = "default"; | 167 | pinctrl-names = "default"; |
| 168 | pinctrl-0 = <&clkout2_pin &gpio_pins_default>; | 168 | pinctrl-0 = <&clkout2_pin &gpio_pins_default>; |
| 169 | 169 | ||
| 170 | i2c0_pins: pinmux_i2c0_pins { | 170 | i2c0_pins: pinmux_i2c0_pins { |
| 171 | pinctrl-single,pins = < | 171 | pinctrl-single,pins = < |
| 172 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | 172 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 173 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | 173 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 174 | >; | 174 | >; |
| 175 | }; | 175 | }; |
| 176 | 176 | ||
| 177 | i2c1_pins: pinmux_i2c1_pins { | 177 | i2c1_pins: pinmux_i2c1_pins { |
| 178 | pinctrl-single,pins = < | 178 | pinctrl-single,pins = < |
| 179 | 0x180 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */ | 179 | 0x180 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */ |
| 180 | 0x184 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txd.i2c1_scl */ | 180 | 0x184 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txd.i2c1_scl */ |
| 181 | >; | 181 | >; |
| 182 | }; | 182 | }; |
| 183 | 183 | ||
| 184 | i2c2_pins: pinmux_i2c2_pins { | 184 | i2c2_pins: pinmux_i2c2_pins { |
| 185 | pinctrl-single,pins = < | 185 | pinctrl-single,pins = < |
| 186 | 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ | 186 | 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ |
| 187 | 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ | 187 | 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ |
| 188 | >; | 188 | >; |
| 189 | }; | 189 | }; |
| 190 | 190 | ||
| 191 | uart0_pins: pinmux_uart0_pins { | 191 | uart0_pins: pinmux_uart0_pins { |
| 192 | pinctrl-single,pins = < | 192 | pinctrl-single,pins = < |
| 193 | 0x168 (PIN_INPUT_PULLUP | MUX_MODE6) /* uart0_ctsn.uart0_ctsn */ | 193 | 0x168 (PIN_INPUT_PULLUP | MUX_MODE6) /* uart0_ctsn.uart0_ctsn */ |
| 194 | 0x16c (PIN_OUTPUT | MUX_MODE6) /* uart0_rtsn.uart0_rtsn */ | 194 | 0x16c (PIN_OUTPUT | MUX_MODE6) /* uart0_rtsn.uart0_rtsn */ |
| 195 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | 195 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 196 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | 196 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| 197 | >; | 197 | >; |
| 198 | }; | 198 | }; |
| 199 | 199 | ||
| 200 | uart2_pins: pinmux_uart2_pins { | 200 | uart2_pins: pinmux_uart2_pins { |
| 201 | pinctrl-single,pins = < | 201 | pinctrl-single,pins = < |
| 202 | 0x12c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txclk.uart2_rxd */ | 202 | 0x12c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txclk.uart2_rxd */ |
| 203 | 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxclk.uart2_txd */ | 203 | 0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxclk.uart2_txd */ |
| 204 | >; | 204 | >; |
| 205 | }; | 205 | }; |
| 206 | 206 | ||
| 207 | uart3_pins: pinmux_uart3_pins { | 207 | uart3_pins: pinmux_uart3_pins { |
| 208 | pinctrl-single,pins = < | 208 | pinctrl-single,pins = < |
| 209 | 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ | 209 | 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */ |
| 210 | 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ | 210 | 0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */ |
| 211 | >; | 211 | >; |
| 212 | }; | 212 | }; |
| 213 | 213 | ||
| 214 | clkout2_pin: pinmux_clkout2_pin { | 214 | clkout2_pin: pinmux_clkout2_pin { |
| 215 | pinctrl-single,pins = < | 215 | pinctrl-single,pins = < |
| 216 | 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ | 216 | 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ |
| 217 | >; | 217 | >; |
| 218 | }; | 218 | }; |
| 219 | 219 | ||
| 220 | /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ | 220 | /*GPIO0-GPIO11, GPIO0-5 is input and GPIO6-11 is output by default.*/ |
| 221 | gpio_pins_default: pinmux_gpio_pin { | 221 | gpio_pins_default: pinmux_gpio_pin { |
| 222 | pinctrl-single,pins = < | 222 | pinctrl-single,pins = < |
| 223 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gmii1_rx_dv.gpio3_4 */ | 223 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gmii1_rx_dv.gpio3_4 */ |
| 224 | 0x09c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ | 224 | 0x09c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ |
| 225 | 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ | 225 | 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ |
| 226 | 0x060 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1_24 */ | 226 | 0x060 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a8.gpio1_24 */ |
| 227 | 0x098 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2_4 */ | 227 | 0x098 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2_4 */ |
| 228 | 0x094 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oenren.gpio2_3 */ | 228 | 0x094 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oenren.gpio2_3 */ |
| 229 | 0x078 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.gpio1_28 */ | 229 | 0x078 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben1.gpio1_28 */ |
| 230 | 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ | 230 | 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ |
| 231 | 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ | 231 | 0x088 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ |
| 232 | 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2_1 */ | 232 | 0x08c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.gpio2_1 */ |
| 233 | 0x1e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu0.gpio3_7 */ | 233 | 0x1e4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu0.gpio3_7 */ |
| 234 | 0x1e8 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu1.gpio3_8 */ | 234 | 0x1e8 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* emu1.gpio3_8 */ |
| 235 | >; | 235 | >; |
| 236 | }; | 236 | }; |
| 237 | 237 | ||
| 238 | ecap0_pins: backlight_pins { | 238 | ecap0_pins: backlight_pins { |
| 239 | pinctrl-single,pins = < | 239 | pinctrl-single,pins = < |
| 240 | 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | 240 | 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ |
| 241 | >; | 241 | >; |
| 242 | }; | 242 | }; |
| 243 | 243 | ||
| 244 | ecap0_pins_sleep: ecap0_pins_sleep { | 244 | ecap0_pins_sleep: ecap0_pins_sleep { |
| 245 | pinctrl-single,pins = < | 245 | pinctrl-single,pins = < |
| 246 | 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ | 246 | 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ |
| 247 | >; | 247 | >; |
| 248 | }; | 248 | }; |
| 249 | 249 | ||
| 250 | cpsw_default: cpsw_default { | 250 | cpsw_default: cpsw_default { |
| 251 | pinctrl-single,pins = < | 251 | pinctrl-single,pins = < |
| 252 | /* Slave 1 */ | 252 | /* Slave 1 */ |
| 253 | 0x10c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ | 253 | 0x10c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ |
| 254 | 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ | 254 | 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ |
| 255 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ | 255 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ |
| 256 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ | 256 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ |
| 257 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ | 257 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ |
| 258 | 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ | 258 | 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ |
| 259 | 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ | 259 | 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ |
| 260 | 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* rmii1_ref_clk.rmii1_ref_clk */ | 260 | 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* rmii1_ref_clk.rmii1_ref_clk */ |
| 261 | 261 | ||
| 262 | /* Slave 2 */ | 262 | /* Slave 2 */ |
| 263 | 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ | 263 | 0x070 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ |
| 264 | 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ | 264 | 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ |
| 265 | 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */ | 265 | 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */ |
| 266 | 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ | 266 | 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ |
| 267 | 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ | 267 | 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ |
| 268 | 0x068 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ | 268 | 0x068 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ |
| 269 | 0x06c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ | 269 | 0x06c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ |
| 270 | 0x108 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_col.rmii2_ref_clk */ | 270 | 0x108 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_col.rmii2_ref_clk */ |
| 271 | >; | 271 | >; |
| 272 | }; | 272 | }; |
| 273 | 273 | ||
| 274 | cpsw_sleep: cpsw_sleep { | 274 | cpsw_sleep: cpsw_sleep { |
| 275 | pinctrl-single,pins = < | 275 | pinctrl-single,pins = < |
| 276 | /* Slave 1 reset value */ | 276 | /* Slave 1 reset value */ |
| 277 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 277 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 278 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 278 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 279 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 279 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 280 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 280 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 281 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 281 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 282 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 282 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 283 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 283 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 284 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 284 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 285 | 285 | ||
| 286 | /* Slave 2 reset value */ | 286 | /* Slave 2 reset value */ |
| 287 | 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 287 | 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 288 | 0x074 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 288 | 0x074 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 289 | 0x040 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 289 | 0x040 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 290 | 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 290 | 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 291 | 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 291 | 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 292 | 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 292 | 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 293 | 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 293 | 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 294 | 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 294 | 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 295 | >; | 295 | >; |
| 296 | }; | 296 | }; |
| 297 | 297 | ||
| 298 | davinci_mdio_default: davinci_mdio_default { | 298 | davinci_mdio_default: davinci_mdio_default { |
| 299 | pinctrl-single,pins = < | 299 | pinctrl-single,pins = < |
| 300 | /* MDIO */ | 300 | /* MDIO */ |
| 301 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | 301 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 302 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | 302 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 303 | >; | 303 | >; |
| 304 | }; | 304 | }; |
| 305 | 305 | ||
| 306 | davinci_mdio_sleep: davinci_mdio_sleep { | 306 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 307 | pinctrl-single,pins = < | 307 | pinctrl-single,pins = < |
| 308 | /* MDIO reset value */ | 308 | /* MDIO reset value */ |
| 309 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 309 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 310 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | 310 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 311 | >; | 311 | >; |
| 312 | }; | 312 | }; |
| 313 | 313 | ||
| 314 | mmc1_pins: pinmux_mmc1_pins { | 314 | mmc1_pins: pinmux_mmc1_pins { |
| 315 | pinctrl-single,pins = < | 315 | pinctrl-single,pins = < |
| 316 | 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ | 316 | 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ |
| 317 | 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ | 317 | 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ |
| 318 | 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ | 318 | 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ |
| 319 | 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ | 319 | 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ |
| 320 | 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ | 320 | 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ |
| 321 | 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ | 321 | 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ |
| 322 | 0x048 (PIN_INPUT | MUX_MODE7) /* GPIO1_18, MMC0_CD */ | 322 | 0x048 (PIN_INPUT | MUX_MODE7) /* GPIO1_18, MMC0_CD */ |
| 323 | 0x044 (PIN_INPUT | MUX_MODE7) /* GPIO1_17, MMC0_WP */ | 323 | 0x044 (PIN_INPUT | MUX_MODE7) /* GPIO1_17, MMC0_WP */ |
| 324 | >; | 324 | >; |
| 325 | }; | 325 | }; |
| 326 | 326 | ||
| 327 | mmc1_pins_sleep: pinmux_mmc1_pins_sleep { | 327 | mmc1_pins_sleep: pinmux_mmc1_pins_sleep { |
| 328 | pinctrl-single,pins = < | 328 | pinctrl-single,pins = < |
| 329 | 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 329 | 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 330 | 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 330 | 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 331 | 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 331 | 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 332 | 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7) | 332 | 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 333 | 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 333 | 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 334 | 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 334 | 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 335 | 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 335 | 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 336 | 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 336 | 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 337 | >; | 337 | >; |
| 338 | }; | 338 | }; |
| 339 | 339 | ||
| 340 | emmc_pins: pinmux_emmc_pins { | 340 | emmc_pins: pinmux_emmc_pins { |
| 341 | pinctrl-single,pins = < | 341 | pinctrl-single,pins = < |
| 342 | 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | 342 | 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 343 | 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | 343 | 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 344 | 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ | 344 | 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 345 | 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | 345 | 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 346 | 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | 346 | 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 347 | 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | 347 | 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 348 | 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ | 348 | 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 349 | 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ | 349 | 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 350 | 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ | 350 | 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 351 | 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ | 351 | 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
| 352 | >; | 352 | >; |
| 353 | }; | 353 | }; |
| 354 | 354 | ||
| 355 | lcd_pins_default: lcd_pins_default { | 355 | lcd_pins_default: lcd_pins_default { |
| 356 | pinctrl-single,pins = < | 356 | pinctrl-single,pins = < |
| 357 | 0x3c 0x01 /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */ | 357 | 0x3c 0x01 /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */ |
| 358 | 0x38 0x01 /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */ | 358 | 0x38 0x01 /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */ |
| 359 | 0x34 0x01 /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */ | 359 | 0x34 0x01 /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */ |
| 360 | 0x30 0x01 /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */ | 360 | 0x30 0x01 /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */ |
| 361 | 0x2c 0x01 /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */ | 361 | 0x2c 0x01 /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */ |
| 362 | 0x28 0x01 /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */ | 362 | 0x28 0x01 /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */ |
| 363 | 0x24 0x01 /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */ | 363 | 0x24 0x01 /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */ |
| 364 | 0x20 0x01 /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */ | 364 | 0x20 0x01 /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */ |
| 365 | 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ | 365 | 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ |
| 366 | 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ | 366 | 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ |
| 367 | 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ | 367 | 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ |
| 368 | 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ | 368 | 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ |
| 369 | 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ | 369 | 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ |
| 370 | 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ | 370 | 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ |
| 371 | 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ | 371 | 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ |
| 372 | 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ | 372 | 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ |
| 373 | 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ | 373 | 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ |
| 374 | 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ | 374 | 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ |
| 375 | 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ | 375 | 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ |
| 376 | 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ | 376 | 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ |
| 377 | 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ | 377 | 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ |
| 378 | 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ | 378 | 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ |
| 379 | 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ | 379 | 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ |
| 380 | 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ | 380 | 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ |
| 381 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ | 381 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ |
| 382 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ | 382 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ |
| 383 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ | 383 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ |
| 384 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ | 384 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ |
| 385 | 0x5c 0x17 /* gpmc_a7.gpio1_23, MODE7 - LCD_VDD_EN */ | 385 | 0x5c 0x17 /* gpmc_a7.gpio1_23, MODE7 - LCD_VDD_EN */ |
| 386 | >; | 386 | >; |
| 387 | }; | 387 | }; |
| 388 | 388 | ||
| 389 | lcd_pins_sleep: lcd_pins_sleep { | 389 | lcd_pins_sleep: lcd_pins_sleep { |
| 390 | pinctrl-single,pins = < | 390 | pinctrl-single,pins = < |
| 391 | 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */ | 391 | 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16, OUTPUT | MODE1 */ |
| 392 | 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */ | 392 | 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17, OUTPUT | MODE1 */ |
| 393 | 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */ | 393 | 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18, OUTPUT | MODE1 */ |
| 394 | 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */ | 394 | 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19, OUTPUT | MODE1 */ |
| 395 | 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */ | 395 | 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20, OUTPUT | MODE1 */ |
| 396 | 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */ | 396 | 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21, OUTPUT | MODE1 */ |
| 397 | 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */ | 397 | 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22, OUTPUT | MODE1 */ |
| 398 | 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */ | 398 | 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23, OUTPUT | MODE1 */ |
| 399 | 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ | 399 | 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ |
| 400 | 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ | 400 | 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ |
| 401 | 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ | 401 | 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ |
| 402 | 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ | 402 | 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ |
| 403 | 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ | 403 | 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ |
| 404 | 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ | 404 | 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ |
| 405 | 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ | 405 | 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ |
| 406 | 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ | 406 | 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ |
| 407 | 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ | 407 | 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ |
| 408 | 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ | 408 | 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ |
| 409 | 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ | 409 | 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ |
| 410 | 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ | 410 | 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ |
| 411 | 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ | 411 | 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ |
| 412 | 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ | 412 | 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ |
| 413 | 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ | 413 | 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ |
| 414 | 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ | 414 | 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ |
| 415 | 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ | 415 | 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ |
| 416 | 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ | 416 | 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ |
| 417 | 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ | 417 | 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ |
| 418 | 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ | 418 | 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ |
| 419 | >; | 419 | >; |
| 420 | }; | 420 | }; |
| 421 | 421 | ||
| 422 | mcasp1_pins: mcasp1_pins { | 422 | mcasp1_pins: mcasp1_pins { |
| 423 | pinctrl-single,pins = < | 423 | pinctrl-single,pins = < |
| 424 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ | 424 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkr.mcasp1_aclkx */ |
| 425 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ | 425 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_fsr.mcasp1_fsx */ |
| 426 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ | 426 | 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr1.mcasp1_axr0 */ |
| 427 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ | 427 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_ahclkx.mcasp1_axr1 */ |
| 428 | >; | 428 | >; |
| 429 | }; | 429 | }; |
| 430 | 430 | ||
| 431 | mcasp1_sleep_pins: mcasp1_sleep_pins { | 431 | mcasp1_sleep_pins: mcasp1_sleep_pins { |
| 432 | pinctrl-single,pins = < | 432 | pinctrl-single,pins = < |
| 433 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 433 | 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 434 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 434 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 435 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) | 435 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 436 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) | 436 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 437 | >; | 437 | >; |
| 438 | }; | 438 | }; |
| 439 | 439 | ||
| 440 | rtc@44e3e000 { | 440 | rtc@44e3e000 { |
| 441 | compatible = "ti,am3352-rtc"; | 441 | compatible = "ti,am3352-rtc"; |
| 442 | reg = <0x44e3e000 0x1000>; | 442 | reg = <0x44e3e000 0x1000>; |
| 443 | interrupts = <75 76>; | 443 | interrupts = <75 76>; |
| 444 | status = "disabled"; | 444 | status = "disabled"; |
| 445 | ti = "disabled"; | 445 | ti = "disabled"; |
| 446 | }; | 446 | }; |
| 447 | 447 | ||
| 448 | spi0_pins: pinmux_spi0_pins { | 448 | spi0_pins: pinmux_spi0_pins { |
| 449 | pinctrl-single,pins = < | 449 | pinctrl-single,pins = < |
| 450 | 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ | 450 | 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ |
| 451 | 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ | 451 | 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ |
| 452 | 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ | 452 | 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ |
| 453 | 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ | 453 | 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ |
| 454 | 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1.spi0_cs1 */ | 454 | 0x160 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs1.spi0_cs1 */ |
| 455 | >; | 455 | >; |
| 456 | }; | 456 | }; |
| 457 | 457 | ||
| 458 | spi1_pins: pinmux_spi1_pins { | 458 | spi1_pins: pinmux_spi1_pins { |
| 459 | pinctrl-single,pins = < | 459 | pinctrl-single,pins = < |
| 460 | 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ | 460 | 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ |
| 461 | 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ | 461 | 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ |
| 462 | 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ | 462 | 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ |
| 463 | 0x19c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ | 463 | 0x19c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ |
| 464 | 0x1b0 (PIN_OUTPUT_PULLUP | MUX_MODE4) /* xdma_event_intr0.spi1_cs1 */ | 464 | 0x1b0 (PIN_OUTPUT_PULLUP | MUX_MODE4) /* xdma_event_intr0.spi1_cs1 */ |
| 465 | >; | 465 | >; |
| 466 | }; | 466 | }; |
| 467 | dcan0_default: dcan0_default_pins { | 467 | dcan0_default: dcan0_default_pins { |
| 468 | pinctrl-single,pins = < | 468 | pinctrl-single,pins = < |
| 469 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gmii1_txd3.dcan0_tx */ | 469 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gmii1_txd3.dcan0_tx */ |
| 470 | 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* gmii1_txd2.dcan0_rx */ | 470 | 0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* gmii1_txd2.dcan0_rx */ |
| 471 | >; | 471 | >; |
| 472 | }; | 472 | }; |
| 473 | }; | 473 | }; |
| 474 | 474 | ||
| 475 | &uart0 { | 475 | &uart0 { |
| 476 | pinctrl-names = "default"; | 476 | pinctrl-names = "default"; |
| 477 | pinctrl-0 = <&uart0_pins>; | 477 | pinctrl-0 = <&uart0_pins>; |
| 478 | 478 | ||
| 479 | status = "okay"; | 479 | status = "okay"; |
| 480 | }; | 480 | }; |
| 481 | 481 | ||
| 482 | &uart2 { | 482 | &uart2 { |
| 483 | pinctrl-names = "default"; | 483 | pinctrl-names = "default"; |
| 484 | pinctrl-0 = <&uart2_pins>; | 484 | pinctrl-0 = <&uart2_pins>; |
| 485 | 485 | ||
| 486 | status = "okay"; | 486 | status = "okay"; |
| 487 | }; | 487 | }; |
| 488 | 488 | ||
| 489 | &uart3 { | 489 | &uart3 { |
| 490 | pinctrl-names = "default"; | 490 | pinctrl-names = "default"; |
| 491 | pinctrl-0 = <&uart3_pins>; | 491 | pinctrl-0 = <&uart3_pins>; |
| 492 | 492 | ||
| 493 | status = "okay"; | 493 | status = "okay"; |
| 494 | }; | 494 | }; |
| 495 | 495 | ||
| 496 | &i2c0 { | 496 | &i2c0 { |
| 497 | pinctrl-names = "default"; | 497 | pinctrl-names = "default"; |
| 498 | pinctrl-0 = <&i2c0_pins>; | 498 | pinctrl-0 = <&i2c0_pins>; |
| 499 | 499 | ||
| 500 | status = "okay"; | 500 | status = "okay"; |
| 501 | clock-frequency = <100000>; | 501 | clock-frequency = <100000>; |
| 502 | 502 | ||
| 503 | /* Set OPP50 (0.95V) for VDD core */ | 503 | /* Set OPP50 (0.95V) for VDD core */ |
| 504 | sleep-sequence = /bits/ 8 < | 504 | sleep-sequence = /bits/ 8 < |
| 505 | 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ | 505 | 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ |
| 506 | 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ | 506 | 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ |
| 507 | 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ | 507 | 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ |
| 508 | 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ | 508 | 0x02 0x24 0x10 0x02 /* Set DCDC3 to 0.95V */ |
| 509 | 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ | 509 | 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ |
| 510 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ | 510 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ |
| 511 | 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ | 511 | 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ |
| 512 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ | 512 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ |
| 513 | >; | 513 | >; |
| 514 | 514 | ||
| 515 | /* Set OPP100 (1.10V) for VDD core */ | 515 | /* Set OPP100 (1.10V) for VDD core */ |
| 516 | wake-sequence = /bits/ 8 < | 516 | wake-sequence = /bits/ 8 < |
| 517 | 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ | 517 | 0x02 0x24 0x0b 0x6d /* Password unlock 1 */ |
| 518 | 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ | 518 | 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ |
| 519 | 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ | 519 | 0x02 0x24 0x0b 0x6d /* Password unlock 2 */ |
| 520 | 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ | 520 | 0x02 0x24 0x10 0x08 /* Set DCDC3 to 1.1V */ |
| 521 | 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ | 521 | 0x02 0x24 0x0b 0x6c /* Password unlock 1 */ |
| 522 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ | 522 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ |
| 523 | 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ | 523 | 0x02 0x24 0x0b 0x6c /* Password unlock 2 */ |
| 524 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ | 524 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ |
| 525 | >; | 525 | >; |
| 526 | 526 | ||
| 527 | tps: tps@24 { | 527 | tps: tps@24 { |
| 528 | reg = <0x24>; | 528 | reg = <0x24>; |
| 529 | }; | 529 | }; |
| 530 | 530 | ||
| 531 | s35390a: s35390a@30 { | 531 | s35390a: s35390a@30 { |
| 532 | compatible = "s35390a"; | 532 | compatible = "s35390a"; |
| 533 | reg = <0x30>; | 533 | reg = <0x30>; |
| 534 | }; | 534 | }; |
| 535 | 535 | ||
| 536 | baseboard_eeprom: baseboard_eeprom@50 { | 536 | baseboard_eeprom: baseboard_eeprom@50 { |
| 537 | compatible = "at,24c256"; | 537 | compatible = "at,24c256"; |
| 538 | reg = <0x50>; | 538 | reg = <0x50>; |
| 539 | }; | 539 | }; |
| 540 | 540 | ||
| 541 | cape_eeprom0: cape_eeprom@57 { | 541 | cape_eeprom0: cape_eeprom@57 { |
| 542 | compatible = "at,24c256"; | 542 | compatible = "at,24c256"; |
| 543 | reg = <0x57>; | 543 | reg = <0x57>; |
| 544 | }; | 544 | }; |
| 545 | 545 | ||
| 546 | tlv320aic3106: tlv320aic3106@1b { | 546 | tlv320aic3106: tlv320aic3106@1b { |
| 547 | compatible = "ti,tlv320aic3106"; | 547 | compatible = "ti,tlv320aic3106"; |
| 548 | reg = <0x1b>; | 548 | reg = <0x1b>; |
| 549 | status = "okay"; | 549 | status = "okay"; |
| 550 | }; | 550 | }; |
| 551 | 551 | ||
| 552 | }; | 552 | }; |
| 553 | 553 | ||
| 554 | &i2c1 { | 554 | &i2c1 { |
| 555 | pinctrl-names = "default"; | 555 | pinctrl-names = "default"; |
| 556 | pinctrl-0 = <&i2c1_pins>; | 556 | pinctrl-0 = <&i2c1_pins>; |
| 557 | status = "okay"; | 557 | status = "okay"; |
| 558 | clock-frequency = <100000>; | 558 | clock-frequency = <100000>; |
| 559 | }; | 559 | }; |
| 560 | 560 | ||
| 561 | &i2c2 { | 561 | &i2c2 { |
| 562 | pinctrl-names = "default"; | 562 | pinctrl-names = "default"; |
| 563 | pinctrl-0 = <&i2c2_pins>; | 563 | pinctrl-0 = <&i2c2_pins>; |
| 564 | status = "okay"; | 564 | status = "okay"; |
| 565 | clock-frequency = <100000>; | 565 | clock-frequency = <100000>; |
| 566 | }; | 566 | }; |
| 567 | 567 | ||
| 568 | &spi0 { | 568 | &spi0 { |
| 569 | pinctrl-names = "default"; | 569 | pinctrl-names = "default"; |
| 570 | pinctrl-0 = <&spi0_pins>; | 570 | pinctrl-0 = <&spi0_pins>; |
| 571 | status = "okay"; | 571 | status = "okay"; |
| 572 | 572 | ||
| 573 | spidev0: spi@0 { | 573 | spidev0: spi@0 { |
| 574 | compatible = "spidev"; | 574 | compatible = "spidev"; |
| 575 | reg = <0>; | 575 | reg = <0>; |
| 576 | spi-max-frequency = <16000000>; | 576 | spi-max-frequency = <16000000>; |
| 577 | spi-cpha; | 577 | spi-cpha; |
| 578 | }; | 578 | }; |
| 579 | 579 | ||
| 580 | spidev2: spi@1 { | 580 | spidev2: spi@1 { |
| 581 | compatible = "spidev"; | 581 | compatible = "spidev"; |
| 582 | reg = <1>; | 582 | reg = <1>; |
| 583 | spi-max-frequency = <16000000>; | 583 | spi-max-frequency = <16000000>; |
| 584 | }; | 584 | }; |
| 585 | }; | 585 | }; |
| 586 | 586 | ||
| 587 | &spi1 { | 587 | &spi1 { |
| 588 | pinctrl-names = "default"; | 588 | pinctrl-names = "default"; |
| 589 | pinctrl-0 = <&spi1_pins>; | 589 | pinctrl-0 = <&spi1_pins>; |
| 590 | status = "okay"; | 590 | status = "okay"; |
| 591 | 591 | ||
| 592 | spidev1: spi@0 { | 592 | spidev1: spi@0 { |
| 593 | compatible = "spidev"; | 593 | compatible = "spidev"; |
| 594 | reg = <0>; | 594 | reg = <0>; |
| 595 | spi-max-frequency = <16000000>; | 595 | spi-max-frequency = <16000000>; |
| 596 | spi-cpha; | 596 | spi-cpha; |
| 597 | }; | 597 | }; |
| 598 | 598 | ||
| 599 | spidev3: spi@1 { | 599 | spidev3: spi@1 { |
| 600 | compatible = "spidev"; | 600 | compatible = "spidev"; |
| 601 | reg = <1>; | 601 | reg = <1>; |
| 602 | spi-max-frequency = <16000000>; | 602 | spi-max-frequency = <16000000>; |
| 603 | }; | 603 | }; |
| 604 | }; | 604 | }; |
| 605 | 605 | ||
| 606 | &lcdc { | 606 | &lcdc { |
| 607 | status = "okay"; | 607 | status = "okay"; |
| 608 | pinctrl-names = "default", "sleep"; | 608 | pinctrl-names = "default", "sleep"; |
| 609 | pinctrl-0 = <&lcd_pins_default>; | 609 | pinctrl-0 = <&lcd_pins_default>; |
| 610 | pinctrl-1 = <&lcd_pins_sleep>; | 610 | pinctrl-1 = <&lcd_pins_sleep>; |
| 611 | }; | 611 | }; |
| 612 | 612 | ||
| 613 | &epwmss0 { | 613 | &epwmss0 { |
| 614 | status = "okay"; | 614 | status = "okay"; |
| 615 | 615 | ||
| 616 | ecap0: ecap@48300100 { | 616 | ecap0: ecap@48300100 { |
| 617 | status = "okay"; | 617 | status = "okay"; |
| 618 | pinctrl-names = "default"; | 618 | pinctrl-names = "default"; |
| 619 | pinctrl-0 = <&ecap0_pins>; | 619 | pinctrl-0 = <&ecap0_pins>; |
| 620 | pinctrl-1 = <&ecap0_pins_sleep>; | 620 | pinctrl-1 = <&ecap0_pins_sleep>; |
| 621 | }; | 621 | }; |
| 622 | }; | 622 | }; |
| 623 | 623 | ||
| 624 | /include/ "tps65217.dtsi" | 624 | /include/ "tps65217.dtsi" |
| 625 | 625 | ||
| 626 | &mcasp1 { | 626 | &mcasp1 { |
| 627 | pinctrl-names = "default"; | 627 | pinctrl-names = "default"; |
| 628 | pinctrl-0 = <&mcasp1_pins>; | 628 | pinctrl-0 = <&mcasp1_pins>; |
| 629 | pinctrl-1 = <&mcasp1_sleep_pins>; | 629 | pinctrl-1 = <&mcasp1_sleep_pins>; |
| 630 | 630 | ||
| 631 | status = "okay"; | 631 | status = "okay"; |
| 632 | 632 | ||
| 633 | op-mode = <0>; /* MCASP_IIS_MODE */ | 633 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 634 | tdm-slots = <2>; | 634 | tdm-slots = <2>; |
| 635 | /* 4 serializers */ | 635 | /* 4 serializers */ |
| 636 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | 636 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 637 | 1 2 0 0 | 637 | 1 2 0 0 |
| 638 | >; | 638 | >; |
| 639 | tx-num-evt = <1>; | 639 | tx-num-evt = <1>; |
| 640 | rx-num-evt = <1>; | 640 | rx-num-evt = <1>; |
| 641 | }; | 641 | }; |
| 642 | 642 | ||
| 643 | &tps { | 643 | &tps { |
| 644 | regulators { | 644 | regulators { |
| 645 | dcdc1_reg: regulator@0 { | 645 | dcdc1_reg: regulator@0 { |
| 646 | regulator-always-on; | 646 | regulator-always-on; |
| 647 | }; | 647 | }; |
| 648 | 648 | ||
| 649 | dcdc2_reg: regulator@1 { | 649 | dcdc2_reg: regulator@1 { |
| 650 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ | 650 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 651 | regulator-name = "vdd_mpu"; | 651 | regulator-name = "vdd_mpu"; |
| 652 | regulator-min-microvolt = <925000>; | 652 | regulator-min-microvolt = <925000>; |
| 653 | regulator-max-microvolt = <1325000>; | 653 | regulator-max-microvolt = <1325000>; |
| 654 | regulator-boot-on; | 654 | regulator-boot-on; |
| 655 | regulator-always-on; | 655 | regulator-always-on; |
| 656 | }; | 656 | }; |
| 657 | 657 | ||
| 658 | dcdc3_reg: regulator@2 { | 658 | dcdc3_reg: regulator@2 { |
| 659 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ | 659 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 660 | regulator-name = "vdd_core"; | 660 | regulator-name = "vdd_core"; |
| 661 | regulator-min-microvolt = <925000>; | 661 | regulator-min-microvolt = <925000>; |
| 662 | regulator-max-microvolt = <1150000>; | 662 | regulator-max-microvolt = <1150000>; |
| 663 | regulator-boot-on; | 663 | regulator-boot-on; |
| 664 | regulator-always-on; | 664 | regulator-always-on; |
| 665 | }; | 665 | }; |
| 666 | 666 | ||
| 667 | ldo1_reg: regulator@3 { | 667 | ldo1_reg: regulator@3 { |
| 668 | regulator-always-on; | 668 | regulator-always-on; |
| 669 | }; | 669 | }; |
| 670 | 670 | ||
| 671 | ldo2_reg: regulator@4 { | 671 | ldo2_reg: regulator@4 { |
| 672 | regulator-always-on; | 672 | regulator-always-on; |
| 673 | }; | 673 | }; |
| 674 | 674 | ||
| 675 | ldo3_reg: regulator@5 { | 675 | ldo3_reg: regulator@5 { |
| 676 | regulator-always-on; | 676 | regulator-always-on; |
| 677 | }; | 677 | }; |
| 678 | 678 | ||
| 679 | ldo4_reg: regulator@6 { | 679 | ldo4_reg: regulator@6 { |
| 680 | regulator-always-on; | 680 | regulator-always-on; |
| 681 | }; | 681 | }; |
| 682 | }; | 682 | }; |
| 683 | }; | 683 | }; |
| 684 | 684 | ||
| 685 | &mac { | 685 | &mac { |
| 686 | /*slaves = <2>;*/ | 686 | /*slaves = <2>;*/ |
| 687 | pinctrl-names = "default", "sleep"; | 687 | pinctrl-names = "default", "sleep"; |
| 688 | pinctrl-0 = <&cpsw_default>; | 688 | pinctrl-0 = <&cpsw_default>; |
| 689 | pinctrl-1 = <&cpsw_sleep>; | 689 | pinctrl-1 = <&cpsw_sleep>; |
| 690 | dual_emac = <1>; | 690 | dual_emac = <1>; |
| 691 | }; | 691 | }; |
| 692 | 692 | ||
| 693 | &davinci_mdio { | 693 | &davinci_mdio { |
| 694 | pinctrl-names = "default", "sleep"; | 694 | pinctrl-names = "default", "sleep"; |
| 695 | pinctrl-0 = <&davinci_mdio_default>; | 695 | pinctrl-0 = <&davinci_mdio_default>; |
| 696 | pinctrl-1 = <&davinci_mdio_sleep>; | 696 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 697 | }; | 697 | }; |
| 698 | 698 | ||
| 699 | &cpsw_emac0 { | 699 | &cpsw_emac0 { |
| 700 | phy_id = <&davinci_mdio>, <0>; | 700 | phy_id = <&davinci_mdio>, <0>; |
| 701 | phy-mode = "rmii"; | 701 | phy-mode = "rmii"; |
| 702 | dual_emac_res_vlan = <1>; | 702 | dual_emac_res_vlan = <1>; |
| 703 | }; | 703 | }; |
| 704 | 704 | ||
| 705 | &cpsw_emac1 { | 705 | &cpsw_emac1 { |
| 706 | phy_id = <&davinci_mdio>, <1>; | 706 | phy_id = <&davinci_mdio>, <1>; |
| 707 | phy-mode = "rmii"; | 707 | phy-mode = "rmii"; |
| 708 | dual_emac_res_vlan = <2>; | 708 | dual_emac_res_vlan = <2>; |
| 709 | }; | 709 | }; |
| 710 | 710 | ||
| 711 | &phy_sel { | ||
| 712 | reg= <0x44e10650 0xf5>; | ||
| 713 | rmii-clock-ext; | ||
| 714 | }; | ||
| 715 | |||
| 711 | &usb { | 716 | &usb { |
| 712 | status = "okay"; | 717 | status = "okay"; |
| 713 | 718 | ||
| 714 | control@44e10620 { | 719 | control@44e10620 { |
| 715 | status = "okay"; | 720 | status = "okay"; |
| 716 | }; | 721 | }; |
| 717 | 722 | ||
| 718 | usb-phy@47401300 { | 723 | usb-phy@47401300 { |
| 719 | status = "okay"; | 724 | status = "okay"; |
| 720 | }; | 725 | }; |
| 721 | 726 | ||
| 722 | usb-phy@47401b00 { | 727 | usb-phy@47401b00 { |
| 723 | status = "okay"; | 728 | status = "okay"; |
| 724 | }; | 729 | }; |
| 725 | 730 | ||
| 726 | usb@47401000 { | 731 | usb@47401000 { |
| 727 | status = "okay"; | 732 | status = "okay"; |
| 728 | dr_mode = "host"; | 733 | dr_mode = "host"; |
| 729 | }; | 734 | }; |
| 730 | 735 | ||
| 731 | usb@47401800 { | 736 | usb@47401800 { |
| 732 | status = "okay"; | 737 | status = "okay"; |
| 733 | dr_mode = "host"; | 738 | dr_mode = "host"; |
| 734 | }; | 739 | }; |
| 735 | 740 | ||
| 736 | dma-controller@47402000 { | 741 | dma-controller@47402000 { |
| 737 | status = "okay"; | 742 | status = "okay"; |
| 738 | }; | 743 | }; |
| 739 | }; | 744 | }; |
| 740 | 745 | ||
| 741 | &tscadc { | 746 | &tscadc { |
| 742 | status = "okay"; | 747 | status = "okay"; |
| 743 | tsc { | 748 | tsc { |
| 744 | ti,wires = <4>; | 749 | ti,wires = <4>; |
| 745 | ti,x-plate-resistance = <200>; | 750 | ti,x-plate-resistance = <200>; |
| 746 | ti,coordinate-readouts = <5>; | 751 | ti,coordinate-readouts = <5>; |
| 747 | ti,wire-config = <0x00 0x11 0x22 0x33>; | 752 | ti,wire-config = <0x00 0x11 0x22 0x33>; |
| 748 | }; | 753 | }; |
| 749 | 754 | ||
| 750 | adc { | 755 | adc { |
| 751 | ti,adc-channels = <0 1 2 3>; | 756 | ti,adc-channels = <0 1 2 3>; |
| 752 | }; | 757 | }; |
| 753 | }; | 758 | }; |
| 754 | 759 | ||
| 755 | &edma { | 760 | &edma { |
| 756 | ti,edma-xbar-event-map = <1 12 | 761 | ti,edma-xbar-event-map = <1 12 |
| 757 | 2 13>; | 762 | 2 13>; |
| 758 | }; | 763 | }; |
| 759 | 764 | ||
| 760 | &mmc1 { | 765 | &mmc1 { |
| 761 | status = "okay"; | 766 | status = "okay"; |
| 762 | bus-width = <0x4>; | 767 | bus-width = <0x4>; |
| 763 | pinctrl-names = "default"; | 768 | pinctrl-names = "default"; |
| 764 | pinctrl-0 = <&mmc1_pins>; | 769 | pinctrl-0 = <&mmc1_pins>; |
| 765 | gpios = <&gpio1 19 1>; /* mmc0 power enable*/ | 770 | gpios = <&gpio1 19 1>; /* mmc0 power enable*/ |
| 766 | cd-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; | 771 | cd-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; |
| 767 | cd-inverted; | 772 | cd-inverted; |
| 768 | }; | 773 | }; |
| 769 | 774 | ||
| 770 | &dcan0 { | 775 | &dcan0 { |
| 771 | pinctrl-names = "default"; | 776 | pinctrl-names = "default"; |
| 772 | pinctrl-0 = <&dcan0_default>; | 777 | pinctrl-0 = <&dcan0_default>; |
| 773 | status = "okay"; | 778 | status = "okay"; |
| 774 | }; | 779 | }; |
| 775 | 780 | ||
| 776 | &sham { | 781 | &sham { |
| 777 | status = "okay"; | 782 | status = "okay"; |
| 778 | }; | 783 | }; |
| 779 | 784 | ||
| 780 | &aes { | 785 | &aes { |
| 781 | status = "okay"; | 786 | status = "okay"; |
| 782 | }; | 787 | }; |
| 783 | 788 | ||
| 784 | &wkup_m3 { | 789 | &wkup_m3 { |
| 785 | ti,scale-data-fw = "am335x-evm-scale-data.bin"; | 790 | ti,scale-data-fw = "am335x-evm-scale-data.bin"; |
| 786 | }; | 791 | }; |
| 787 | 792 | ||
| 788 | &rtc { | 793 | &rtc { |
| 789 | ti,system-power-controller; | 794 | ti,system-power-controller; |
| 790 | }; | 795 | }; |
| 791 | 796 |